diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt index c7fbf1e909f..f33b1bb7a8b 100644 --- a/.github/.cSpellWords.txt +++ b/.github/.cSpellWords.txt @@ -1,4 +1,3 @@ - A AADLENR AAIC @@ -100,7 +99,9 @@ AEEVT AEIE AERR AESCCM +AESCE AESCMAC +AESGCM AESNI AESR AFECR @@ -307,6 +308,7 @@ BCTRL BCUT BDCR BDEV +BDEVOPENMODE BDEVTEST BDEVTESTPARAM BDFA @@ -323,6 +325,7 @@ BERR BESR BFAR BFARV +BFARVALID BFHFNMIGN BFRX BFSR @@ -430,6 +433,7 @@ BUFNA BUFWREN BUMEN BUSA +BUSFAULTENA BUSFAULTSR BUSP BUSTKE @@ -646,6 +650,7 @@ CLKPR CLKPS CLKRQ CLKS +CLKSOURCE CLKSR CLKSTA CLKVCLR @@ -719,6 +724,7 @@ CMock CNBTR CNDA CNDTR +CNOT CNTALOAD CNTAMAX CNTBLOAD @@ -761,6 +767,7 @@ CPCSTOP CPCTRG CPDI CPHA +CPIEVTENA CPIN CPINREADY CPIV @@ -862,6 +869,11 @@ CWTA CWTAVAL CWTIF CWUF +CYCCNT +CYCCNTENA +CYCEVTENA +CYCMATCH +CYCTAP CYGNAL Cbmc Centralised @@ -1491,7 +1503,9 @@ EWRL EWRX EWUP EXCC +EXCEVTENA EXCOL +EXCTRCENA EXDEF EXEDG EXID @@ -1567,6 +1581,7 @@ FERR FESETERR FESR FFCR +FFDH FFDHE FFDR FFER @@ -1599,6 +1614,7 @@ FMULTCLK FMXR FNTR FNUM +FOLDEVTENA FOLVA FOLVB FOOB @@ -2116,6 +2132,7 @@ INVD INVI INVON INVPC +Inited IOCE IOCF IOCLR @@ -2233,6 +2250,7 @@ JKJKJKJK JKKKKKKK JNCH JOFR +JPAKE JSQR JSWSTRT JTAG @@ -2494,6 +2512,7 @@ MASKH MASKL MAXBLKL MAXFS +MAXFSIZE MAXFSSIZE MAXMB MAXRTX @@ -2568,6 +2587,7 @@ MDTX MEDEMSR MEM MEMA +MEMFAULTENA MEMFAULTSR MEMP MERASE @@ -2599,6 +2619,7 @@ MISRA MLAN MMAR MMARV +MMARVALID MMCCR MMCIT MMCR @@ -2860,6 +2881,7 @@ Nfontname Ngan Nios Nmap +Nondet Npcap Nullpuc Nullpx @@ -3251,6 +3273,7 @@ PRFTBS PRIA PRIS PRIVDEFEN +PRIVDEFENA PRKLAST PRLH PRLL @@ -3609,6 +3632,7 @@ RMEN RMII RMIIEN RMIIMII +RMTAUTH RMTE RMTEN RMUTE @@ -3987,6 +4011,8 @@ SECEV SECP SECU SEGGER +SELEXTCLK +SELEXTEN SENDA SEQR SESREQ @@ -4042,6 +4068,8 @@ SLBDIS SLCKSEL SLCR SLCT +SLEEPEVTENA +SLEEPONEXIT SLEWCTL SLICEBY SLIPIF @@ -4285,6 +4313,7 @@ SYBYPSR SYMM SYNCA SYNCB +SYNCENA SYNCR SYNMAXRTX SYNSR @@ -4522,6 +4551,7 @@ TRAPA TRARECLENGTH TRAS TRCD +TRCENA TRCMD TRCMPAD TRCMPAU @@ -4900,6 +4930,7 @@ USEND USEPWMDIV USEQ USGA +USGFAULTENA USGFAULTSR USGTRGAF USGTRGAR @@ -4963,6 +4994,8 @@ VDTO VECT VECTACTIVE VECTCLRACTIVE +VECTKEY +VECTKEYSTAT VECTPENDING VECTRESET VECTTBL @@ -5012,6 +5045,7 @@ VRRSTEN VRRSTS VSDB VSYNC +VTASKLIST VTIR VTOFFR VTOR @@ -5138,6 +5172,7 @@ XADD XAPM XAXIPMON XBLANK +XCALLBACK XCANPS XCOL XCOREAI @@ -5270,6 +5305,7 @@ addif addiu adge aeevt +aesce aesni alldevs ambig @@ -5336,10 +5372,12 @@ coalescences codecov comms converttounixtime +coreid coremqtt cortexa coverity covfs +covg cpas cpbs cpcdis @@ -5402,8 +5440,10 @@ enetrg epage epdisc eqcfg +equalto equidistribution eret +estack ethernetif etrgs evba @@ -5581,6 +5621,7 @@ lpstart lpthread lptr lsls +lteq ltorg ltry lums @@ -5588,6 +5629,8 @@ lusecs lxip macaddrhr macaddrlr +maes +maxfsize maxiosz maxnpacks mbar @@ -5637,6 +5680,7 @@ movne movs movw movx +mpclmul mpcr mqdes mqttexample @@ -5649,6 +5693,7 @@ mrsne mspgcc msplim msreq +msse mstatus mstroff mtdr @@ -5679,6 +5724,7 @@ noassert nocrypt noheap noint +nondet nopts nostdint notifyzz @@ -5858,6 +5904,7 @@ reti revsh rgmii riscv +rmtauth rovr rsar rslcx @@ -6008,6 +6055,7 @@ txrx u uadd uasx +ubasetype ublock ublox uchars @@ -6027,6 +6075,7 @@ unhashed unifdef uninitialised uninitializing +unprecise unsubscriptions unsuspended unsuspends @@ -6049,10 +6098,14 @@ utilising utrhf utrhfgdghfg ux +uxdeletedtaskwaiting uxindex +uxpriority uxsource uxtab +uxtasknumber uxtb +uxtopreadypriority vactive vblank vcmp @@ -6120,6 +6173,7 @@ xfindobjectwithlabelandclass xfscompat xgetslotlist xheader +xidx xinitializepkcs xlarge xlength diff --git a/.github/scripts/common/header_checker.py b/.github/scripts/common/header_checker.py index 57a5c2dcd1c..68c1e9f4ee3 100755 --- a/.github/scripts/common/header_checker.py +++ b/.github/scripts/common/header_checker.py @@ -216,6 +216,10 @@ def isValidFile(self, path): print("PASS") print("-" * 85) return True + elif self.customCheck(path): + print("PASS") + print("-" * 85) + return True elif self.isThirdPartyFile(path): print("FAIL") print("-" * 85) @@ -435,3 +439,6 @@ def validateSpdxLine(self, lines): else: error_count += 1 return error_count == 0 + + def customCheck(self, path): + return False diff --git a/.github/scripts/common/requirements.txt b/.github/scripts/common/requirements.txt index b5722b8466d..c5a9cb27c54 100644 --- a/.github/scripts/common/requirements.txt +++ b/.github/scripts/common/requirements.txt @@ -1,5 +1,5 @@ Deprecated -GitPython +GitPython>=3.1.41 PyGithub PyJWT PyYAML @@ -10,5 +10,5 @@ gitdb idna requests smmap -urllib3 +urllib3 >= 2.0.7 wrapt diff --git a/.github/scripts/core_checker.py b/.github/scripts/core_checker.py index a348e6c804d..34bbc29daa8 100755 --- a/.github/scripts/core_checker.py +++ b/.github/scripts/core_checker.py @@ -44,8 +44,10 @@ '.cfg', '.cgp', '.checksum', + '.clang-format', '.cmake', '.cmd', + '.code-workspace', '.config', '.cpp', '.cproj', @@ -258,7 +260,7 @@ FREERTOS_IGNORED_PATTERNS = [ r'.*\.git.*', - r'.*mbedtls_config\.h.*', + r'.*mbedtls_config*', r'.*CMSIS.*', r'.*/Nordic_Code/*', r'.*/Nuvoton_Code/*', @@ -303,13 +305,21 @@ r'FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/include/.*', r'FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/.*', r'FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/.*', + r'FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/.*', + r'FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/.*', + r'FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/.*', r'FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/.*', r'FreeRTOS/Demo/AVR32_UC3/.*', + r'FreeRTOS/Demo/AVR_ATMega4809_IAR/.*', + r'FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/.*', + r'FreeRTOS/Demo/AVR_Dx_IAR/.*', + r'FreeRTOS/Demo/AVR_Dx_MPLAB.X/.*', r'FreeRTOS/Demo/ARM7_STR75x_GCC/STLibrary/inc/.*', r'FreeRTOS/Demo/ARM7_STR75x_IAR/STLibrary/inc/.*', r'FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/.*', r'FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/drivers/misc/.*', r'FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/.*', + r'FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/.*', r'FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/.*', r'FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/Trace_Recorder_Configuration/.*', r'FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/common/WinPCap/.*', @@ -321,16 +331,16 @@ r'FreeRTOS/Demo/AVR32_UC3/FreeRTOSConfig.h', r'FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/.*', r'FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/.*', - r'FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS\+/src/smc_gen/.*' + r'FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS\+/src/smc_gen/.*', + r'FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/.*' ] FREERTOS_IGNORED_FILES = [ 'cspell.config.yaml', + '.ccsproject', + '.clang-format', '.cproject', '.project', - 'fyi-another-way-to-ignore-file.txt', - 'mbedtls_config.h', - 'mbedtls_config_v3.2.1.h', 'requirements.txt', 'run-cbmc-proofs.py', '.editorconfig', diff --git a/.github/scripts/release-requirements.txt b/.github/scripts/release-requirements.txt index b5722b8466d..130809087e0 100644 --- a/.github/scripts/release-requirements.txt +++ b/.github/scripts/release-requirements.txt @@ -1,5 +1,5 @@ Deprecated -GitPython +GitPython>=3.1.41 PyGithub PyJWT PyYAML diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml index d0860e5b790..7f7ce165558 100644 --- a/.github/workflows/auto-release.yml +++ b/.github/workflows/auto-release.yml @@ -38,14 +38,18 @@ jobs: fetch-depth: 0 - name: Release + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + ACTOR: ${{ github.actor }} + COMMIT_ID: ${{ github.event.inputs.commit_id }} + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + GITHUB_ORG: ${{ github.repository_owner }} run: | # Configure repo for push - git config --global user.name ${{ github.actor }} - git config --global user.email ${{ github.actor }}@users.noreply.github.com + git config --global user.name "$ACTOR" + git config --global user.email "$ACTOR"@users.noreply.github.com # Run the release script pip install -r ./tools/.github/scripts/release-requirements.txt - ./tools/.github/scripts/release.py FreeRTOS --core-repo-path=local_core --core-commit=${{ github.event.inputs.commit_id }} --new-core-version=${{ github.event.inputs.version_number }} + ./tools/.github/scripts/release.py "$GITHUB_ORG" --core-repo-path=local_core --core-commit="$COMMIT_ID" --new-core-version="$VERSION_NUMBER" exit $? - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index e64341a7ed1..384e926436d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -2,7 +2,7 @@ name: CI Checks env: bashPass: \033[32;1mPASSED - - bashWarn: \033[33;1mWARNING - + bashInfo: \033[33;1mINFO - bashFail: \033[31;1mFAILED - bashEnd: \033[0m @@ -81,7 +81,7 @@ jobs: # Therefore, we can just download it. mkdir -p freertos/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent/source/dependency/coreMQTT/docs/doxygen/output wget -O freertos/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent/source/dependency/coreMQTT/docs/doxygen/output/mqtt.tag \ - "https://freertos.org/Documentation/api-ref/coreMQTT/docs/doxygen/output/mqtt.tag" + "https://freertos.github.io/coreMQTT/main/mqtt.tag" - name: Generate doxygen ZIP uses: FreeRTOS/CI-CD-Github-Actions/doxygen@main @@ -90,11 +90,12 @@ jobs: # List of directories containing libraries whose doxygen output will be generated. libs_parent_dir_path: FreeRTOS-Plus/Source,FreeRTOS-Plus/Source/AWS,FreeRTOS-Plus/Source/Application-Protocols,FreeRTOS-Plus/Source/Utilities generate_zip: true + doxygen_dependencies: libclang-18-dev libclang-cpp18 graphviz - name: Upload doxygen artifact if main branch if: success() && ( github.ref == 'refs/heads/main' || github.ref == 'refs/heads/release-candidate' ) env: GIT_SHA: - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: name: doxygen.zip-${{ github.sha }} path: ./freertos/doxygen.zip @@ -144,29 +145,32 @@ jobs: Upload memory size report as artifact (for main and release-candidate ONLY) if: success() && ( github.ref == 'refs/heads/main' || github.ref == 'refs/heads/release-candidate' ) - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: name: freertos-memory-estimates path: ./freertos_lts_memory_estimates.json retention-days: 2 proof_ci: - if: ${{ github.event.pull_request }} + if: ${{ github.event.pull_request }} || ${{ github.event.workflow }} runs-on: cbmc_ubuntu-latest_16-core steps: - uses: actions/checkout@v3 - env: stepName: Install Dependencies run: | - echo -e "::group::${{ env.stepName }}" + # ${{ env.stepName }} + echo -e "::group:: ${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" git submodule update --init --checkout --recursive --depth 1 - sudo apt-get update + sudo apt-get update -y sudo apt-get install --yes --no-install-recommends gcc-multilib echo -e "::endgroup::" echo -e "${{ env.bashPass }} ${{env.stepName}} ${{ env.bashEnd }}" - name: Set up CBMC runner uses: FreeRTOS/CI-CD-Github-Actions/set_up_cbmc_runner@main + with: + cbmc_version: "5.95.1" - name: Run CBMC uses: FreeRTOS/CI-CD-Github-Actions/run_cbmc@main diff --git a/.github/workflows/freertos_demos.yml b/.github/workflows/freertos_demos.yml index ad610251b3d..36730d8a4bc 100644 --- a/.github/workflows/freertos_demos.yml +++ b/.github/workflows/freertos_demos.yml @@ -24,7 +24,7 @@ jobs: stepName: Checkout Repository name: ${{ env.stepName }} uses: actions/checkout@v3 - + - env: stepName: Fetch Required Submodule name: ${{ env.stepName }} @@ -62,7 +62,8 @@ jobs: $content = Get-Content -Path 'main.c' -Raw $newContent = $content -replace 'int\s+main(.*?)void(.*?)\r?\n\s*{', 'int main( void ){setvbuf( stdout, NULL, _IONBF, 0 );' $newContent | Set-Content -Path 'main.c' - msbuild WIN32.sln -t:rebuild + msbuild WIN32.sln /p:Platform=Win32 -t:rebuild + msbuild WIN32.sln /p:Platform=x64 -t:rebuild $exitStatus = $? echo "::endgroup::" if($exitStatus -eq 1) { @@ -73,11 +74,21 @@ jobs: } - env: - stepName: Run and monitor WIN32-MSVC Full Demo + stepName: Run and monitor WIN32-MSVC Full Demo - Win32 + name: ${{ env.stepName }} + uses: FreeRTOS/CI-CD-GitHub-Actions/executable-monitor@main + with: + exe-path: FreeRTOS/Demo/WIN32-MSVC/Win32/Debug/RTOSDemo.exe + timeout-seconds: 60 + success-line: "No errors - tick count" + retry-attempts: 3 + + - env: + stepName: Run and monitor WIN32-MSVC Full Demo - x64 name: ${{ env.stepName }} uses: FreeRTOS/CI-CD-GitHub-Actions/executable-monitor@main with: - exe-path: FreeRTOS/Demo/WIN32-MSVC/Debug/RTOSDemo.exe + exe-path: FreeRTOS/Demo/WIN32-MSVC/x64/Debug/RTOSDemo.exe timeout-seconds: 60 success-line: "No errors - tick count" retry-attempts: 3 @@ -93,7 +104,8 @@ jobs: $content = Get-Content -Path 'main.c' -Raw $newContent = $content -replace '#define\s+mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\s+0', '#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1' $newContent | Set-Content -Path 'main.c' - msbuild WIN32.sln -t:rebuild + msbuild WIN32.sln /p:Platform=Win32 -t:rebuild + msbuild WIN32.sln /p:Platform=x64 -t:rebuild echo "::endgroup::" $exitStatus = $? if($exitStatus -eq 1) { @@ -104,11 +116,21 @@ jobs: } - env: - stepName: Run and monitor WIN32-MSVC Blinky Demo + stepName: Run and monitor WIN32-MSVC Blinky Demo - Win32 + name: ${{ env.stepName }} + uses: FreeRTOS/CI-CD-GitHub-Actions/executable-monitor@main + with: + exe-path: FreeRTOS/Demo/WIN32-MSVC/Win32/Debug/RTOSDemo.exe + timeout-seconds: 60 + success-line: "Message received from software timer" + retry-attempts: 3 + + - env: + stepName: Run and monitor WIN32-MSVC Blinky Demo - x64 name: ${{ env.stepName }} uses: FreeRTOS/CI-CD-GitHub-Actions/executable-monitor@main with: - exe-path: FreeRTOS/Demo/WIN32-MSVC/Debug/RTOSDemo.exe + exe-path: FreeRTOS/Demo/WIN32-MSVC/x64/Debug/RTOSDemo.exe timeout-seconds: 60 success-line: "Message received from software timer" retry-attempts: 3 @@ -384,8 +406,12 @@ jobs: # ${{ env.stepName }} echo -e "::group::${{ env.stepName }}" set +e - sudo apt-get -y update - sudo apt-get -y install gcc-msp430 build-essential + curl -L -O https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z + sudo apt update -y + sudo apt install -y p7zip-full + 7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z + chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run + sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended exitStatus=$? set -e echo -e "::endgroup::" @@ -405,7 +431,7 @@ jobs: # ${{ env.stepName }} echo -e "::group::${{ env.stepName }}" set +e - make -j + make -j CC=/usr/bin/msp430-gcc/bin/msp430-elf-gcc OPT="-Os -I/usr/bin/msp430-gcc/include -L/usr/bin/msp430-gcc/include" exitStatus=$? set -e echo -e "::endgroup::" @@ -433,7 +459,7 @@ jobs: # ${{ env.stepName }} echo -e "::group::${{ env.stepName }}" set +e - git submodule update --checkout --init --depth 1 FreeRTOS/Source FreeRTOS/Demo/ThirdParty/Community-Supported-Demos + git submodule update --checkout --init --depth 1 FreeRTOS/Source FreeRTOS/Demo/ThirdParty/Community-Supported-Demos FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace exitStatus=$? set -e echo -e "::endgroup::" @@ -454,7 +480,7 @@ jobs: set +e sudo apt-get -y update sudo apt-get -y install gcc-arm-none-eabi build-essential cmake git ninja-build python3-minimal - sudo apt-get -y install qemu-system-arm qemu-efi + sudo apt-get -y install qemu-system-arm qemu-efi-arm exitStatus=$? set -e echo -e "::endgroup::" diff --git a/.github/workflows/freertos_mpu_demo.yml b/.github/workflows/freertos_mpu_demo.yml new file mode 100644 index 00000000000..39677cb4bbe --- /dev/null +++ b/.github/workflows/freertos_mpu_demo.yml @@ -0,0 +1,69 @@ +name: FreeRTOS MPU Demo +on: + push: + pull_request: + workflow_dispatch: + +env: + bashPass: \033[32;1mPASSED - + bashInfo: \033[33;1mINFO - + bashFail: \033[31;1mFAILED - + bashEnd: \033[0m + +jobs: + Cortex-Rx-MPU-Demos: + name: TI-Hercules RM46 and RM57 MPU Demos + runs-on: ubuntu-latest + steps: + - env: + stepName: Checkout Repository + name: ${{ env.stepName }} + uses: actions/checkout@v4.1.1 + with: + submodules: true + + - env: + stepName: Fetch FreeRTOS-Kernel + name: ${{ env.stepName }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + git submodule update --checkout --init --depth 1 FreeRTOS/Source + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + - env: + stepName: Install GNU ARM Toolchain + name: Install GNU ARM Toolchain + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + sudo apt-get -y update + sudo apt-get -y install gcc-arm-none-eabi build-essential cmake git ninja-build python3-minimal + echo -e "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + - env: + stepName: Build CORTEX R5 MPU Demo + name: ${{ env.stepName }} + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + cmake -S . -B build && make -j -C build all + echo -e "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + - env: + stepName: Build CORTEX R4 MPU Demo + name: ${{ env.stepName }} + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + cmake -S . -B build && make -j -C build all + echo -e "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" diff --git a/.github/workflows/freertos_plus_demos.yml b/.github/workflows/freertos_plus_demos.yml index 583b89193d0..95e819b8e1b 100644 --- a/.github/workflows/freertos_plus_demos.yml +++ b/.github/workflows/freertos_plus_demos.yml @@ -446,10 +446,20 @@ jobs: id: generate-credentials uses: FreeRTOS/CI-CD-GitHub-Actions/ssl-credential-creator@main + - name: Query CI host IP address + id: get-ip + run: | + # Query the device's IP address + $SERVER_IP = (Get-NetIPAddress -AddressFamily IPv4 | Where-Object { $_.IPAddress -notmatch '127.0.0.1' } | Select-Object -First 1 -ExpandProperty IPAddress) + Write-Host "Device IP address: $SERVER_IP" + echo "server_ip=$SERVER_IP" >> $env:GITHUB_ENV + shell: pwsh + - name: Start localhost MQTT broker id: mqtt-broker uses: FreeRTOS/CI-CD-GitHub-Actions/localhost-mqtt-broker@main with: + host_address: ${{ env.server_ip }} root-ca-cert-path: ${{ steps.generate-credentials.outputs.root-ca-cert-path }} server-priv-key-path: @@ -475,7 +485,7 @@ jobs: # ${{ env.stepName }} echo -e "::group::${{ env.stepName }}" echo '#define democonfigCLIENT_IDENTIFIER "mqtt_demo_test"' >> demo_config.h - echo '#define democonfigMQTT_BROKER_ENDPOINT "127.0.0.1"' >> demo_config.h + echo '#define democonfigMQTT_BROKER_ENDPOINT "${{ env.server_ip }}"' >> demo_config.h echo '#define democonfigMQTT_BROKER_PORT ( 1883 )' >> demo_config.h echo "::endgroup::" echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " @@ -521,7 +531,7 @@ jobs: sed 's/.*/"&\\n"\\/' ${{ steps.generate-credentials.outputs.root-ca-cert-path }} >> root_ca_cert.txt sed '$ s/.$//' root_ca_cert.txt >> demo_config.h echo '#define democonfigCLIENT_IDENTIFIER "mqtt_demo_test"' >> demo_config.h - echo '#define democonfigMQTT_BROKER_ENDPOINT "127.0.0.1"' >> demo_config.h + echo '#define democonfigMQTT_BROKER_ENDPOINT "${{ env.server_ip }}"' >> demo_config.h echo '#define democonfigMQTT_BROKER_PORT ( 8883 )' >> demo_config.h sed -i -z "s/define[[:space:]]*democonfigDISABLE_SNI[[:space:]]*([[:space:]]*[a-zA-Z0-9]\+[[:space:]]*)/define democonfigDISABLE_SNI ( pdTRUE )/g" demo_config.h exitStatus=$? @@ -575,7 +585,7 @@ jobs: sed 's/.*/"&\\n"\\/' ${{ steps.generate-credentials.outputs.device-priv-key-path }} >> device_priv_key.txt sed '$ s/.$//' device_priv_key.txt >> demo_config.h echo '#define democonfigCLIENT_IDENTIFIER "mqtt_demo_test"' >> demo_config.h - echo '#define democonfigMQTT_BROKER_ENDPOINT "127.0.0.1"' >> demo_config.h + echo '#define democonfigMQTT_BROKER_ENDPOINT "${{ env.server_ip }}"' >> demo_config.h echo '#define democonfigMQTT_BROKER_PORT ( 8883 )' >> demo_config.h sed -i -z "s/define[[:space:]]*democonfigDISABLE_SNI[[:space:]]*([[:space:]]*[a-zA-Z0-9]\+[[:space:]]*)/define democonfigDISABLE_SNI ( pdTRUE )/g" demo_config.h echo "::endgroup::" @@ -621,7 +631,7 @@ jobs: echo '#ifndef DEMO_CONFIG_H_TEST_BUILD' >> demo_config.h echo ' #define DEMO_CONFIG_H_TEST_BUILD' >> demo_config.h echo ' #define democonfigCLIENT_IDENTIFIER "mqtt_demo_test"' >> demo_config.h - echo ' #define democonfigMQTT_BROKER_ENDPOINT "127.0.0.1"' >> demo_config.h + echo ' #define democonfigMQTT_BROKER_ENDPOINT "${{ env.server_ip }}"' >> demo_config.h echo ' #define democonfigMQTT_BROKER_PORT ( 1883 )' >> demo_config.h echo '#endif /* DEMO_CONFIG_H_TEST_BUILD */' >> demo_config.h echo "::endgroup::" @@ -665,7 +675,7 @@ jobs: # ${{ env.stepName }} echo -e "::group::${{ env.stepName }}" echo '#define democonfigCLIENT_IDENTIFIER "mqtt_demo_test"' >> demo_config.h - echo '#define democonfigMQTT_BROKER_ENDPOINT "127.0.0.1"' >> demo_config.h + echo '#define democonfigMQTT_BROKER_ENDPOINT "${{ env.server_ip }}"' >> demo_config.h echo '#define democonfigMQTT_BROKER_PORT ( 1883 )' >> demo_config.h echo "::endgroup::" echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " @@ -710,7 +720,7 @@ jobs: sed 's/.*/"&\\n"\\/' ${{ steps.generate-credentials.outputs.device-priv-key-path }} >> device_priv_key.txt sed '$ s/.$//' device_priv_key.txt >> demo_config.h echo '#define democonfigCLIENT_IDENTIFIER "mqtt_demo_test"' >> demo_config.h - echo '#define democonfigMQTT_BROKER_ENDPOINT "127.0.0.1"' >> demo_config.h + echo '#define democonfigMQTT_BROKER_ENDPOINT "${{ env.server_ip }}"' >> demo_config.h echo '#define democonfigMQTT_BROKER_PORT ( 8883 )' >> demo_config.h echo "::endgroup::" echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " @@ -956,7 +966,7 @@ jobs: - env: stepName: Build AWS IoT Fleet Provisioning Demo name: ${{ env.stepName }} - working-directory: FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo + working-directory: FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo run: | # ${{ env.stepName }} echo "::group::${{ env.stepName }}" @@ -1051,10 +1061,19 @@ jobs: echo "::endgroup::" echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " + - name: Query CI host IP address + id: get-ip + run: | + # Query the device's IP address + SERVER_IP="$(ip addr show | grep "inet " | grep -v "127.0.0.1" | awk '{print $2}' | cut -d/ -f1 | head -n 1)" + echo "Device IP address: $SERVER_IP" + echo "server_ip=\"$SERVER_IP\"" >> $GITHUB_ENV + - name: Start localhost Echo server id: echo-server uses: FreeRTOS/CI-CD-GitHub-Actions/localhost-echo-server@main with: + host_address: ${{ env.server_ip }} port_number: 5000 - env: @@ -1067,6 +1086,8 @@ jobs: echo -e "::group::${{ env.stepName }}" sed -i -z "s/define[[:space:]]*echoECHO_PORT[[:space:]]*([[:space:]]*[0-9]\+[[:space:]]*)/define echoECHO_PORT ( 5000 )/g" TCPEchoClient_SingleTasks.c sed -i -z "s/int[[:space:]]*main[[:space:]]*([[:space:]]*void[[:space:]]*)\n{/int main( void ){setvbuf( stdout, NULL, _IONBF, 0 );/g" main.c + sed -i "s/^#define configECHO_SERVER_ADDR .*/#define configECHO_SERVER_ADDR \"${{ env.server_ip }}\"/" FreeRTOSConfig.h + git diff make -j TRACE_ON_ENTER=0 echo "::endgroup::" echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " @@ -1177,10 +1198,20 @@ jobs: exit 1 } + - name: Query CI host IP address + id: get-ip + run: | + # Query the device's IP address + $SERVER_IP = (Get-NetIPAddress -AddressFamily IPv4 | Where-Object { $_.IPAddress -notmatch '127.0.0.1' } | Select-Object -First 1 -ExpandProperty IPAddress) + Write-Host "Device IP address: $SERVER_IP" + echo "server_ip=$SERVER_IP" >> $env:GITHUB_ENV + shell: pwsh + - name: Start localhost Echo server id: echo-server uses: FreeRTOS/CI-CD-GitHub-Actions/localhost-echo-server@main with: + host_address: ${{ env.server_ip }} port_number: 5000 - env: @@ -1195,7 +1226,7 @@ jobs: $newContent = $content -replace '#define\s+echoECHO_PORT.*', '#define echoECHO_PORT ( 5000 )' $newContent | Set-Content -Path 'DemoTasks\TCPEchoClient_SingleTasks.c' $content = Get-Content -Path 'tcp_echo_config.h' -Raw - $newContent = $content -replace '#define\s+configECHO_SERVER_ADDR.*', '#define configECHO_SERVER_ADDR "127.0.0.1"' + $newContent = $content -replace '#define\s+configECHO_SERVER_ADDR.*', '#define configECHO_SERVER_ADDR "${{ env.server_ip }}"' $newContent | Set-Content -Path 'tcp_echo_config.h' $content = Get-Content -Path 'main.c' -Raw $newContent = $content -replace 'int\s+main(.*?)void(.*?)\r?\n\s*{', 'int main( void ){setvbuf( stdout, NULL, _IONBF, 0 );' diff --git a/.github/workflows/kernel-unit-tests.yml b/.github/workflows/kernel-unit-tests.yml index 46945c4eb6d..7fdf2bf865d 100644 --- a/.github/workflows/kernel-unit-tests.yml +++ b/.github/workflows/kernel-unit-tests.yml @@ -28,14 +28,14 @@ jobs: make -C FreeRTOS/Test/CMock lcovhtml lcov --config-file FreeRTOS/Test/CMock/lcovrc --summary FreeRTOS/Test/CMock/build/cmock_test.info > FreeRTOS/Test/CMock/build/cmock_test_summary.txt - name: Archive code coverage data - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: - name: coverage-data + name: submodule-coverage-data path: FreeRTOS/Test/CMock/build/cmock_test* - name: Archive code coverage html report - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: - name: coverage-report + name: submodule-coverage-report path: FreeRTOS/Test/CMock/build/coverage run-upstream: name: FreeRTOS-Kernel Main Branch @@ -69,12 +69,12 @@ jobs: make -C FreeRTOS/Test/CMock lcovhtml lcov --config-file FreeRTOS/Test/CMock/lcovrc --summary FreeRTOS/Test/CMock/build/cmock_test.info > FreeRTOS/Test/CMock/build/cmock_test_summary.txt - name: Archive code coverage data - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: - name: coverage-data + name: main-branch-coverage-data path: FreeRTOS/Test/CMock/build/cmock_test* - name: Archive code coverage html report - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: - name: coverage-report + name: main-branch-coverage-report path: FreeRTOS/Test/CMock/build/coverage diff --git a/.gitignore b/.gitignore index dc8dc7a25bd..d75ac31af2f 100644 --- a/.gitignore +++ b/.gitignore @@ -11,6 +11,7 @@ [Oo]bj/ [Ll]og/ [Ll]ogs/ +[Bb]uild/ # CodeWarrior temporary files *.tdt diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/DemoTasks/DefenderDemoExample.c b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/DemoTasks/DefenderDemoExample.c index 544f3f2e71a..e6a704975cb 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/DemoTasks/DefenderDemoExample.c +++ b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/DemoTasks/DefenderDemoExample.c @@ -219,6 +219,10 @@ static uint32_t ulReportId = 0UL; /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /** * @brief Callback to receive the incoming publish messages from the MQTT broker. * diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/Device_Defender_Demo.vcxproj b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/Device_Defender_Demo.vcxproj index 456fb7a0725..872babac07a 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/Device_Defender_Demo.vcxproj +++ b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/Device_Defender_Demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -31,26 +19,7 @@ true v142 Unicode - - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode + x86 @@ -60,85 +29,20 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\AWS\device-defender\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - WIN32;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\AWS\device-defender\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - _DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\AWS\device-defender\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="medtls_config_v3.2.1.h";%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";%(PreprocessorDefinitions) true .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\AWS\device-defender\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) Console - true - true true diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/defender_demo.sln b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/defender_demo.sln index 39db36bcd28..c596f0cdaeb 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/defender_demo.sln +++ b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/defender_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.31205.134 @@ -17,52 +16,19 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|x64 = Release|x64 - Release|x86 = Release|x86 + Debug|Win32 = Debug|Win32 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution - {6C548950-0BED-42EF-8039-95A2084A806D}.Debug|x64.ActiveCfg = Debug|x64 - {6C548950-0BED-42EF-8039-95A2084A806D}.Debug|x64.Build.0 = Debug|x64 - {6C548950-0BED-42EF-8039-95A2084A806D}.Debug|x86.ActiveCfg = Debug|Win32 - {6C548950-0BED-42EF-8039-95A2084A806D}.Debug|x86.Build.0 = Debug|Win32 - {6C548950-0BED-42EF-8039-95A2084A806D}.Release|x64.ActiveCfg = Release|x64 - {6C548950-0BED-42EF-8039-95A2084A806D}.Release|x64.Build.0 = Release|x64 - {6C548950-0BED-42EF-8039-95A2084A806D}.Release|x86.ActiveCfg = Release|Win32 - {6C548950-0BED-42EF-8039-95A2084A806D}.Release|x86.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 + {6C548950-0BED-42EF-8039-95A2084A806D}.Debug|Win32.ActiveCfg = Debug|Win32 + {6C548950-0BED-42EF-8039-95A2084A806D}.Debug|Win32.Build.0 = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/readme.url b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/readme.url new file mode 100644 index 00000000000..127ec1ee807 --- /dev/null +++ b/FreeRTOS-Plus/Demo/AWS/Device_Defender_Windows_Simulator/Device_Defender_Demo/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/iot-device-defender/index.html diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/DemoTasks/ShadowDemoMainExample.c b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/DemoTasks/ShadowDemoMainExample.c index e401b85b6d3..a611d3f175f 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/DemoTasks/ShadowDemoMainExample.c +++ b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/DemoTasks/ShadowDemoMainExample.c @@ -375,6 +375,10 @@ static BaseType_t prvWaitForDeleteResponse( MQTTContext_t * pxMQTTContext ); /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + static BaseType_t prvWaitForDeleteResponse( MQTTContext_t * pxMQTTContext ) { uint8_t ucCount = 0U; @@ -390,7 +394,7 @@ static BaseType_t prvWaitForDeleteResponse( MQTTContext_t * pxMQTTContext ) /* Event callback will set #xDeleteResponseReceived when receiving an * incoming publish on either `/delete/accepted` or `/delete/rejected` * Shadow topics. */ - xMQTTStatus = MQTT_ProcessLoop( pxMQTTContext, MQTT_PROCESS_LOOP_TIMEOUT_MS ); + xMQTTStatus = MQTT_ProcessLoop( pxMQTTContext ); } if( ( xMQTTStatus != MQTTSuccess ) || ( xDeleteResponseReceived != pdTRUE ) ) diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/Device_Shadow_Demo.vcxproj b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/Device_Shadow_Demo.vcxproj index 76926f452f3..41e2e81fe05 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/Device_Shadow_Demo.vcxproj +++ b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/Device_Shadow_Demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -31,26 +19,7 @@ true v142 Unicode - - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode + x86 @@ -60,85 +29,20 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\device-shadow\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - WIN32;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\device-shadow\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - _DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\device-shadow\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";%(PreprocessorDefinitions) true .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\device-shadow\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;%(AdditionalIncludeDirectories) Console - true - true true diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/READ_ME_INSTRUCTIONS.url b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/readme.url similarity index 99% rename from FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/READ_ME_INSTRUCTIONS.url rename to FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/readme.url index b9f4c099a53..f0bfbb594d6 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/READ_ME_INSTRUCTIONS.url +++ b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/readme.url @@ -3,4 +3,3 @@ Prop3=19,11 [InternetShortcut] IDList= URL=https://www.freertos.org/iot-device-shadow/index.html - diff --git a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/shadow_main_demo.sln b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/shadow_main_demo.sln index ff279cd1cb1..e3b2d7227bb 100644 --- a/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/shadow_main_demo.sln +++ b/FreeRTOS-Plus/Demo/AWS/Device_Shadow_Windows_Simulator/Device_Shadow_Demo/shadow_main_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.31205.134 @@ -17,52 +16,19 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|x64 = Release|x64 - Release|x86 = Release|x86 + Debug|Win32 = Debug|Win32 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Debug|x64.ActiveCfg = Debug|x64 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Debug|x64.Build.0 = Debug|x64 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Debug|x86.ActiveCfg = Debug|Win32 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Debug|x86.Build.0 = Debug|Win32 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Release|x64.ActiveCfg = Release|x64 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Release|x64.Build.0 = Release|x64 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Release|x86.ActiveCfg = Release|Win32 - {717F029B-ADE9-433A-9C05-3136171BEAEF}.Release|x86.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 + {717F029B-ADE9-433A-9C05-3136171BEAEF}.Debug|Win32.ActiveCfg = Debug|Win32 + {717F029B-ADE9-433A-9C05-3136171BEAEF}.Debug|Win32.Build.0 = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/cloudformation_template.json b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/cloudformation_template.json similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/cloudformation_template.json rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/cloudformation_template.json diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/convert_credentials_to_der.py b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/convert_credentials_to_der.py similarity index 75% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/convert_credentials_to_der.py rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/convert_credentials_to_der.py index d52dfef5afd..b696df0138c 100755 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/convert_credentials_to_der.py +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/convert_credentials_to_der.py @@ -6,11 +6,16 @@ from cryptography.hazmat.backends import default_backend from cryptography.hazmat.primitives import serialization -KEY_OUT_NAME = f"{os.getcwd()}\\corePKCS11_Claim_Key.dat" -CERT_OUT_NAME = f"{os.getcwd()}\\corePKCS11_Claim_Certificate.dat" - +# Get the absolute path of this script script_file_dir_abs_path = os.path.abspath(os.path.dirname(__file__)) +# Get the parent directory, as that is where the demo expects the keys to be placed +parent_abs_path = os.path.abspath(os.path.join(script_file_dir_abs_path, os.pardir)) + +KEY_OUT_NAME = os.path.join(parent_abs_path, 'corePKCS11_Claim_Key.dat') +CERT_OUT_NAME = os.path.join(parent_abs_path, 'corePKCS11_Claim_Certificate.dat') + + def convert_pem_to_der(cert_pem, key_pem): # Convert certificate from PEM to DER key = serialization.load_pem_private_key( @@ -22,19 +27,16 @@ def convert_pem_to_der(cert_pem, key_pem): ) with open(f"{KEY_OUT_NAME}", "wb") as key_out: key_out.write(key_der) - print( - f"Successfully converted key PEM to DER. Output file named: {KEY_OUT_NAME}" - ) + + print(f"Successfully converted key PEM to DER. Output file named:\n\t{KEY_OUT_NAME}") cert = x509.load_pem_x509_certificate( bytes(cert_pem, "utf-8"), default_backend()) + with open(f"{CERT_OUT_NAME}", "wb") as cert_out: cert_out.write(cert.public_bytes(serialization.Encoding.DER)) - print( - f"Successfully converted certificate PEM to DER. Output file named: {CERT_OUT_NAME}" - ) - + print(f"Successfully converted certificate PEM to DER. Output file named:\n\t{CERT_OUT_NAME}") def main(args): with open(args.cert_file, "r") as cert: diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_cleanup.py b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_cleanup.py similarity index 94% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_cleanup.py rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_cleanup.py index fc96943617a..ea16caac210 100755 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_cleanup.py +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_cleanup.py @@ -5,12 +5,12 @@ import botocore import argparse -KEY_OUT_NAME = f"{os.getcwd()}\\corePKCS11_Claim_Key.dat" -CERT_OUT_NAME = f"{os.getcwd()}\\corePKCS11_Claim_Certificate.dat" +KEY_OUT_NAME = os.path.join(os.getcwd(), "corePKCS11_Claim_Key.dat") +CERT_OUT_NAME = os.path.join(os.getcwd(), "corePKCS11_Claim_Certificate.dat") -THING_PRIVATE_KEY_NAME = f"{os.getcwd()}\\corePKCS11_Key.dat" -THING_PUBLIC_KEY_NAME = f"{os.getcwd()}\\corePKCS11_PubKey.dat" -THING_CERT_NAME = f"{os.getcwd()}\\corePKCS11_Certificate.dat" +THING_PRIVATE_KEY_NAME = os.path.join(os.getcwd(), "corePKCS11_Key.dat") +THING_PUBLIC_KEY_NAME = os.path.join(os.getcwd(), "corePKCS11_PubKey.dat") +THING_CERT_NAME = os.path.join(os.getcwd(), "corePKCS11_Certificate.dat") RESOURCE_STACK_NAME = "FPDemoStack" diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_config.templ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_config.templ similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_config.templ rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_config.templ diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_config_empty.templ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_config_empty.templ similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_config_empty.templ rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_config_empty.templ diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_setup.py b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_setup.py similarity index 59% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_setup.py rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_setup.py index fc95524148c..ad4886703bb 100755 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/demo_setup.py +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/demo_setup.py @@ -4,17 +4,98 @@ import argparse import boto3 import botocore +import random +import datetime +import subprocess +from cryptography import x509 +from cryptography.x509.oid import NameOID +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import serialization, hashes +from cryptography.hazmat.primitives.asymmetric import ec + +from generate_credentials import generate_priv_keys_and_certs from convert_credentials_to_der import convert_pem_to_der -KEY_OUT_NAME = f"{os.getcwd()}\\corePKCS11_Claim_Key.dat" -CERT_OUT_NAME = f"{os.getcwd()}\\corePKCS11_Claim_Certificate.dat" - RESOURCE_STACK_NAME = "FPDemoStack" script_file_dir_abs_path = os.path.abspath(os.path.dirname(__file__)) cf = boto3.client("cloudformation") iot = boto3.client("iot") +# Generate IoT credentials in DER format and save them in the demo directory +def create_credentials(): + print("Creating Certs and Credentials for the Fleet Provisioning Demo...") + # Verify that the stack exists (create_resources has been ran before somewhere) + stack_response = get_stack() + if stack_response == "STACK_NOT_FOUND": + raise Exception( + f"CloudFormation stack \"{RESOURCE_STACK_NAME}\" not found.") + elif stack_response["StackStatus"] != "CREATE_COMPLETE": + print("Error: Stack was not successfully created. View the stack in the CloudFormation console here:") + stack_link = convert_cf_arn_to_link(stack_response["StackId"]) + raise Exception( + "Stack was not successfully created. View the stack in the CloudFormation console here:\n" + stack_link) + + # Generate an ECDSA CA cert, and a ECDSA Cert and key to use for device provisioning + root_ca_cert, claim_cert = generate_priv_keys_and_certs(write_der_keys=True) + + if ( root_ca_cert is None ) or ( claim_cert is None ): + raise Exception(f"Failed to generate needed ECDSA Keypairs and Certificates") + + ca_cert_response = iot.register_ca_certificate( + caCertificate=root_ca_cert, + setAsActive=True, + allowAutoRegistration=True, + certificateMode='SNI_ONLY' + ) + + if "certificateArn" not in ca_cert_response.keys(): + raise Exception( "Failed to register the generated ECDSA CA Certificate" ) + else: + print("\nRegistered CA Cert\n\tARN:{0}\n\tCertID:{1}" + .format( + ca_cert_response["certificateArn"], + ca_cert_response["certificateId"] + ) + ) + + claim_cert_response = iot.register_certificate( + certificatePem=claim_cert, + caCertificatePem=root_ca_cert, + status='ACTIVE' + ) + + if "certificateArn" not in claim_cert_response.keys(): + raise Exception( + "Failed to register the generate CA Certificate" + ) + else: + print("\nRegistered Claim Cert\n\tARN:{0}\n\tCertID:{1}" + .format( + claim_cert_response["certificateArn"], + claim_cert_response["certificateId"] + ) + ) + + iot.attach_policy(policyName="CF_FleetProvisioningDemoClaimPolicy", + target=claim_cert_response["certificateArn"]) + +# Set the necessary fields in demo_config.h +def update_demo_config(): + print("Updating the demo config for the Fleet Provisioning Demo...") + endpoint = iot.describe_endpoint(endpointType='iot:Data-ATS') + + template_file = open(f"{script_file_dir_abs_path}/demo_config.templ", 'r') + file_text = template_file.read() + file_text = file_text.replace( + "", "\"" + endpoint["endpointAddress"] + "\"") + + header_file = open(f"{script_file_dir_abs_path}/../demo_config.h", "w") + header_file.write(file_text) + header_file.close() + template_file.close() + print("Successfully updated demo_config.h") + # Convert a CloudFormation arn into a link to the resource def convert_cf_arn_to_link(arn): region = arn.split(":")[3] @@ -43,8 +124,11 @@ def create_resources(): stack_response["StackStatus"]) print() if stack_response["StackStatus"] != "CREATE_COMPLETE": - raise Exception("Fleet Provisioning resource stack failed to create successfully. You may need to delete the stack and retry." - + "\nView the stack in the CloudFormation console here:\n" + convert_cf_arn_to_link(stack_response["StackId"])) + raise Exception( + "Fleet Provisioning resource stack failed to create successfully. " + + "You may need to delete the stack and retry. " + + "\nView the stack in the CloudFormation console here:\n " + + convert_cf_arn_to_link(stack_response["StackId"])) else: # Read the cloudformation template file contained in the same directory cf_template_file = open(f"{script_file_dir_abs_path}/cloudformation_template.json", "r") @@ -70,43 +154,6 @@ def create_resources(): "Error: Stack creation failed. You may need to delete_all and try again.") raise -# Generate IoT credentials in DER format and save them in the demo directory - - -def create_credentials(): - # Verify that the stack exists (create_resources has been ran before somewhere) - stack_response = get_stack() - if stack_response == "STACK_NOT_FOUND": - raise Exception( - f"CloudFormation stack \"{RESOURCE_STACK_NAME}\" not found.") - elif stack_response["StackStatus"] != "CREATE_COMPLETE": - print("Error: Stack was not successfully created. View the stack in the CloudFormation console here:") - stack_link = convert_cf_arn_to_link(stack_response["StackId"]) - raise Exception( - "Stack was not successfully created. View the stack in the CloudFormation console here:\n" + stack_link) - else: - credentials = iot.create_keys_and_certificate(setAsActive=True) - iot.attach_policy(policyName="CF_FleetProvisioningDemoClaimPolicy", - target=credentials["certificateArn"]) - convert_pem_to_der( - credentials["certificatePem"], credentials["keyPair"]["PrivateKey"]) - - -# Set the necessary fields in demo_config.h -def update_demo_config(): - endpoint = iot.describe_endpoint(endpointType='iot:Data-ATS') - - template_file = open(f"{script_file_dir_abs_path}/demo_config.templ", 'r') - file_text = template_file.read() - file_text = file_text.replace( - "", "\"" + endpoint["endpointAddress"] + "\"") - - header_file = open(f"{script_file_dir_abs_path}/../demo_config.h", "w") - header_file.write(file_text) - header_file.close() - template_file.close() - print("Successfully updated demo_config.h") - # Get arguments def get_args(): parser = argparse.ArgumentParser(description="Fleet Provisioning Demo setup script.") @@ -116,16 +163,29 @@ def get_args(): # Parse arguments and execute appropriate functions def main(): + # Check arguments and go appropriately args = get_args(); print("\nThis script will set up the AWS resources required for the Fleet Provisioning demo.") print("It may take several minutes for the resources to be provisioned.") if args.force or input("Are you sure you want to do this? (y/n) ") == "y": - print() + print("\n---------------------- Start Create Cloud Stack Resources ----------------------\n") create_resources() + print("\n----------------------- End Create Cloud Stack Resources -----------------------\n") + + print("\n-------------------------- Start Creating Credentials --------------------------\n") create_credentials() + print("\n--------------------------- End Creating Credentials ---------------------------\n") + + print("\n--------------------------- Start Update Demo Config ---------------------------\n") update_demo_config() - print("\nFleet Provisioning demo setup complete. Ensure that all generated files (key, certificate, demo_config.h) are in the same folder as \"fleet_provisioning_demo.sln\".") + print("\n---------------------------- End Update Demo Config ----------------------------\n") + + print( + "Fleet Provisioning demo setup complete. Ensure that all generated files " + + "(key, certificate, demo_config.h) are in the same folder as " + + "\"fleet_provisioning_demo.sln\"." + ) if __name__ == "__main__": diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/example_claim_policy.json b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/example_claim_policy.json similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/example_claim_policy.json rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/example_claim_policy.json diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/example_fleet_provisioning_template.json b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/example_fleet_provisioning_template.json similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/example_fleet_provisioning_template.json rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/example_fleet_provisioning_template.json diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/example_iot_thing_policy.json b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/example_iot_thing_policy.json similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/DemoSetup/example_iot_thing_policy.json rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/example_iot_thing_policy.json diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/generate_credentials.py b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/generate_credentials.py new file mode 100755 index 00000000000..ec04e0a80fe --- /dev/null +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/DemoSetup/generate_credentials.py @@ -0,0 +1,199 @@ +#!/usr/bin/env python + +import os +import argparse +import random +import datetime +import subprocess +from cryptography import x509 +from cryptography.x509.oid import NameOID +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import serialization, hashes +from cryptography.hazmat.primitives.asymmetric import ec + +# Helper scripts from this directory +from convert_credentials_to_der import convert_pem_to_der + +script_file_dir_abs_path = os.path.abspath(os.path.dirname(__file__)) + +# File names for generated credentials +ROOT_CA_PRIV_KEY_FILE = f"{script_file_dir_abs_path}{os.sep}ECDSA_root_priv_key.pem" +ROOT_CA_PUB_KEY_FILE = f"{script_file_dir_abs_path}{os.sep}ECDSA_root_pub_key.pem" +ROOT_CA_CERT_FILE = f"{script_file_dir_abs_path}{os.sep}ECDSA_root_ca_cert.pem" + +CLAIM_PRIV_KEY_FILE = f"{script_file_dir_abs_path}{os.sep}ECDSA_claim_priv_key.pem" +CLAIM_PUB_KEY_FILE = f"{script_file_dir_abs_path}{os.sep}ECDSA_claim_pub_key.pem" +CLAIM_CERT_FILE = f"{script_file_dir_abs_path}{os.sep}ECDSA_claim_device_cert.pem" + +# Use the current date and time to create a unique subject name +now = datetime.datetime.now() +dt_string = now.strftime("%d_%m_%Y_%H_%M_%S") + +# Default values for the CA cert +subject = issuer = x509.Name([ + x509.NameAttribute(NameOID.COUNTRY_NAME, "US"), + x509.NameAttribute(NameOID.STATE_OR_PROVINCE_NAME, "FP_State"), + x509.NameAttribute(NameOID.LOCALITY_NAME, "FP_Locality"), + x509.NameAttribute(NameOID.ORGANIZATION_NAME, "FP_Organization"), + x509.NameAttribute(NameOID.COMMON_NAME, f'FP_CN_{dt_string}'), +]) + +# Simple check of the generated keys. +# Documentation says if the operations fail an exception is thrown. +# https://cryptography.io/en/latest/hazmat/primitives/asymmetric/ec/#cryptography.hazmat.primitives.asymmetric.ec.ECDSA +def validate_keys(private_key, public_key): + # Verify the generated keys work correctly by signing a message and then verifying it + data = b"TEST DATA TO SIGN" + + # Sign the above message using the private key + signature = private_key.sign( + data, + ec.ECDSA(hashes.SHA256()) + ) + + # Verify the signature using the public key + public_key.verify( + signature, + data, + ec.ECDSA(hashes.SHA256()) + ) + + +def generate_priv_keys_and_certs(write_der_keys): + print("Generating ECDSA Root Keys\n") + # Generate an ECDSA Key Pair + # NOTE: At time of writing corePKCS11 only supports the prime256v1/secp256r1 keys + # If this changes then these keys should be changed to use a better alg. + root_prv_key = ec.generate_private_key( + ec.SECP256R1() + ) + + # Get the related public key + root_pub_key = root_prv_key.public_key() + + validate_keys( + private_key = root_prv_key, + public_key = root_pub_key + ) + + # Now that the public and private key have been validated, create a x509 Cert + root_ca_cert = x509.CertificateBuilder().subject_name( + subject + ).issuer_name( + issuer + ).public_key( + root_pub_key + ).serial_number( + x509.random_serial_number() + ).not_valid_before( + datetime.datetime.now(datetime.timezone.utc) + ).not_valid_after( + # Our certificate will be valid for 14 days + datetime.datetime.now(datetime.timezone.utc) + datetime.timedelta(days=14) + ).add_extension( + x509.BasicConstraints(ca=True, path_length=None), critical=True, + # Sign our certificate with our private key + ).sign(root_prv_key, hashes.SHA256()) + + # Check to make sure the cert generated correctly + isinstance(root_ca_cert, x509.Certificate) + + # Print out the generated ECDSA Keys and Certs + root_pub_key_pem = root_pub_key.public_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PublicFormat.SubjectPublicKeyInfo + ) + + root_prv_key_pem = root_prv_key.private_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PrivateFormat.TraditionalOpenSSL, + encryption_algorithm=serialization.NoEncryption() + ) + + root_ca_cert_pem = root_ca_cert.public_bytes(serialization.Encoding.PEM) + + print("Public Key Pem:\n{0}\n".format(root_pub_key_pem.decode("utf-8"))) + print("Private Key Pem:\n{0}\n".format(root_prv_key_pem.decode("utf-8"))) + print("Root CA Cert Pem:\n{0}\n".format(root_ca_cert_pem.decode("utf-8"))) + + open(ROOT_CA_PRIV_KEY_FILE, "wb").write(root_prv_key_pem) + open(ROOT_CA_PUB_KEY_FILE, "wb").write(root_pub_key_pem) + open(ROOT_CA_CERT_FILE, "wb").write(root_ca_cert_pem) + + print(f"Wrote PEM Encoded Root Private Key to:\n\t{ROOT_CA_PRIV_KEY_FILE}") + print(f"Wrote PEM Encoded Root Public Key to:\n\t{ROOT_CA_PUB_KEY_FILE}") + print(f"Wrote PEM Encoded Root CA Cert to:\n\t{ROOT_CA_CERT_FILE}") + + # Device credential generation + print("\n\nGenerating ECDSA Claim Keys\n") + # Generate a ECDSA Key Pair + claim_prv_key = ec.generate_private_key( + ec.SECP256R1() + ) + + # Get the related public key + claim_pub_key = claim_prv_key.public_key() + + # Simple check of the generated keys + validate_keys( + private_key = claim_prv_key, + public_key = claim_pub_key + ) + + # Now that the public and private key have been validated, create a x509 Cert + claim_cert = x509.CertificateBuilder().subject_name( + subject + ).issuer_name( + issuer + ).public_key( + claim_pub_key + ).serial_number( + x509.random_serial_number() + ).not_valid_before( + datetime.datetime.now(datetime.timezone.utc) + ).not_valid_after( + # Our certificate will be valid for 14 days + datetime.datetime.now(datetime.timezone.utc) + datetime.timedelta(days=14) + ).add_extension( + x509.BasicConstraints(ca=False, path_length=None), critical=True, + # Sign our certificate with the Root private key + ).sign(root_prv_key, hashes.SHA256()) + + # Check to make sure the cert generated correctly + isinstance(claim_cert, x509.Certificate) + + # Serialize the generated ECDSA Keys and Certs + claim_pub_key_pem = claim_pub_key.public_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PublicFormat.SubjectPublicKeyInfo + ) + + claim_prv_key_pem = claim_prv_key.private_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PrivateFormat.TraditionalOpenSSL, + encryption_algorithm=serialization.NoEncryption() + ) + + claim_cert_pem = claim_cert.public_bytes(serialization.Encoding.PEM) + + print("Claim Public Key Pem:\n{0}\n".format(claim_pub_key_pem.decode("utf-8"))) + print("Claim Private Key Pem:\n{0}\n".format(claim_prv_key_pem.decode("utf-8"))) + print("Claim Cert Pem:\n{0}\n".format(claim_cert_pem.decode("utf-8"))) + + open(CLAIM_PRIV_KEY_FILE, "wb").write(claim_pub_key_pem) + open(CLAIM_PUB_KEY_FILE, "wb").write(claim_prv_key_pem) + open(CLAIM_CERT_FILE, "wb").write(claim_cert_pem) + + print(f"Wrote PEM Encoded Claim Private Key to:\n\t{CLAIM_PRIV_KEY_FILE}") + print(f"Wrote PEM Encoded Claim Public Key to:\n\t{CLAIM_PUB_KEY_FILE}") + print(f"Wrote PEM Encoded Claim CA Cert to:\n\t{CLAIM_CERT_FILE}") + + if write_der_keys == True: + print("\nWrite DER Format Version of Claim Private Key and Cert") + # Use the helper function in convert_credentials_to_der to write out DER formatted keys + convert_pem_to_der( + cert_pem = claim_cert_pem.decode("utf-8"), + key_pem = claim_prv_key_pem.decode("utf-8") + ) + + return root_ca_cert_pem.decode("utf-8"), claim_cert_pem.decode("utf-8") diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/FleetProvisioningDemoExample.c b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/FleetProvisioningDemoExample.c similarity index 97% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/FleetProvisioningDemoExample.c rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/FleetProvisioningDemoExample.c index 39e3ebb0190..c8e75dd0a6c 100644 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/FleetProvisioningDemoExample.c +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/FleetProvisioningDemoExample.c @@ -124,29 +124,30 @@ * @brief Time in seconds to wait between retries of the demo loop if * demo loop fails. */ -#define fpdemoDELAY_BETWEEN_DEMO_RETRY_ITERATIONS_SECONDS ( 5 ) +#define fpdemoDELAY_BETWEEN_DEMO_RETRY_ITERATIONS_SECONDS ( 10 ) /** * @brief Size of buffer in which to hold the certificate signing request (CSR). */ -#define fpdemoCSR_BUFFER_LENGTH 2048 +#define fpdemoCSR_BUFFER_LENGTH 4096 /** * @brief Size of buffer in which to hold the certificate. */ -#define fpdemoCERT_BUFFER_LENGTH 2048 +#define fpdemoCERT_BUFFER_LENGTH 4096 /** * @brief Size of buffer in which to hold the certificate id. * - * See https://docs.aws.amazon.com/iot/latest/apireference/API_Certificate.html#iot-Type-Certificate-certificateId + * @note Has a maximum length of 64 for more information see the following link + * https://docs.aws.amazon.com/iot/latest/apireference/API_Certificate.html#iot-Type-Certificate-certificateId */ #define fpdemoCERT_ID_BUFFER_LENGTH 64 /** * @brief Size of buffer in which to hold the certificate ownership token. */ -#define fpdemoOWNERSHIP_TOKEN_BUFFER_LENGTH 512 +#define fpdemoOWNERSHIP_TOKEN_BUFFER_LENGTH 1024 /** * @brief Milliseconds per second. @@ -203,7 +204,7 @@ static size_t xThingNameLength; * APIs. When the MQTT publish callback receives an expected Fleet Provisioning * accepted payload, it copies it into this buffer. */ -static uint8_t pucPayloadBuffer[ democonfigNETWORK_BUFFER_SIZE ]; +static uint8_t pucPayloadBuffer[ democonfigNETWORK_BUFFER_SIZE * 2 ]; /** * @brief Length of the payload stored in #pucPayloadBuffer. This is set by the @@ -290,6 +291,10 @@ static bool prvUnsubscribeFromRegisterThingResponseTopics( void ); static int prvFleetProvisioningTask( void * pvParameters ); +/*-----------------------------------------------------------*/ + +BaseType_t xPlatformIsNetworkUp( void ); + /*-----------------------------------------------------------*/ static void prvProvisioningPublishCallback( MQTTContext_t * pxMqttContext, @@ -646,6 +651,12 @@ int prvFleetProvisioningTask( void * pvParameters ) * topics. In this demo we use CBOR encoding for the payloads, * so we use the CBOR variants of the topics. */ xStatus = prvSubscribeToCsrResponseTopics(); + + if( xStatus == true ) + { + /* Subscribe to the RegisterThing response topics. */ + xStatus = prvSubscribeToRegisterThingResponseTopics(); + } } if( xStatus == true ) @@ -727,12 +738,6 @@ int prvFleetProvisioningTask( void * pvParameters ) &xPayloadLength ); } - if( xStatus == true ) - { - /* Subscribe to the RegisterThing response topics. */ - xStatus = prvSubscribeToRegisterThingResponseTopics(); - } - if( xStatus == true ) { /* Publish the RegisterThing request. */ diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/core_mqtt_config.h b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/core_mqtt_config.h similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/core_mqtt_config.h rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/core_mqtt_config.h diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/demo_config.h b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/demo_config.h similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/demo_config.h rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/demo_config.h diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_config.h b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_config.h similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_config.h rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_config.h diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.sln b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.sln similarity index 54% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.sln rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.sln index cad1733c9ca..1398ad922bd 100644 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.sln +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Fleet Provisioning Demo", "fleet_provisioning_demo.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Fleet Provisioning Demo", "fleet_provisioning_demo.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.ActiveCfg = Debug|Win32 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.Build.0 = Debug|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.ActiveCfg = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.Build.0 = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.ActiveCfg = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.Build.0 = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.ActiveCfg = Release|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.vcxproj b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.vcxproj similarity index 54% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.vcxproj rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.vcxproj index 9f938a63564..8a8e9d64291 100644 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.vcxproj +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -33,26 +21,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -61,28 +29,10 @@ - - - - - - - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\AWS\fleet-provisioning\source\include;..\..\Mqtt_Demo_Helpers;$(IncludePath) - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\AWS\fleet-provisioning\source\include;..\..\Mqtt_Demo_Helpers;$(IncludePath) - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\AWS\fleet-provisioning\source\include;..\..\Mqtt_Demo_Helpers;$(IncludePath) - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\AWS\fleet-provisioning\source\include;..\..\Mqtt_Demo_Helpers;$(IncludePath) - false @@ -90,61 +40,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - true - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - true - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - true - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true @@ -152,8 +48,6 @@ Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.vcxproj.filters b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.vcxproj.filters similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/fleet_provisioning_demo.vcxproj.filters rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/fleet_provisioning_demo.vcxproj.filters diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/main.c b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/main.c similarity index 98% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/main.c rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/main.c index ba12350ac9a..7fc4756d971 100644 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/main.c +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/main.c @@ -54,6 +54,7 @@ /*-----------------------------------------------------------*/ extern void vStartFleetProvisioningDemo( void ); +extern void vPlatformInitIpStack( void ); /*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/pkcs11_operations.c b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/pkcs11_operations.c similarity index 98% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/pkcs11_operations.c rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/pkcs11_operations.c index 1e8037862e2..4cf1af25f49 100644 --- a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/pkcs11_operations.c +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/pkcs11_operations.c @@ -214,7 +214,6 @@ bool xGenerateKeyAndCsr( CK_SESSION_HANDLE xP11Session, CK_OBJECT_HANDLE xPubKeyHandle; CK_RV xPkcs11Ret = CKR_OK; mbedtls_pk_context xPrivKey; - mbedtls_ecdsa_context xEcdsaContext; mbedtls_x509write_csr xReq; int32_t ulMbedtlsRet = -1; const mbedtls_pk_info_t * pxHeader = mbedtls_pk_info_from_type( MBEDTLS_PK_ECKEY ); @@ -256,8 +255,10 @@ bool xGenerateKeyAndCsr( CK_SESSION_HANDLE xP11Session, { mbedtls_x509write_csr_set_key( &xReq, &xPrivKey ); - ulMbedtlsRet = mbedtls_x509write_csr_pem( &xReq, ( unsigned char * ) pcCsrBuffer, - xCsrBufferLength, &lMbedCryptoRngCallbackPKCS11, + ulMbedtlsRet = mbedtls_x509write_csr_pem( &xReq, + ( unsigned char * ) pcCsrBuffer, + xCsrBufferLength, + &lMbedCryptoRngCallbackPKCS11, &xP11Session ); } diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/pkcs11_operations.h b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/pkcs11_operations.h similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/pkcs11_operations.h rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/pkcs11_operations.h diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/readme.url b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/readme.url new file mode 100644 index 00000000000..73b39c4609d --- /dev/null +++ b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/04-AWS-libraries/06-AWS-IoT-Fleet-Provisioning/03-Fleet-provisioning-demo diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/tinycbor_serializer.c b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/tinycbor_serializer.c similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/tinycbor_serializer.c rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/tinycbor_serializer.c diff --git a/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/tinycbor_serializer.h b/FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/tinycbor_serializer.h similarity index 100% rename from FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/Fleet_Provisioning_With_CSR_Demo/tinycbor_serializer.h rename to FreeRTOS-Plus/Demo/AWS/Fleet_Provisioning_Windows_Simulator/CSR_Demo/tinycbor_serializer.h diff --git a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/DemoTasks/JobsDemoExample.c b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/DemoTasks/JobsDemoExample.c index 8b816c52173..950fe30d00e 100644 --- a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/DemoTasks/JobsDemoExample.c +++ b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/DemoTasks/JobsDemoExample.c @@ -388,7 +388,7 @@ static void prvSendUpdateForJob( char * pcJobId, static void prvProcessJobDocument( char * pcJobId, uint16_t usJobIdLength, char * pcJobDocument, - uint16_t jobDocumentLength ); + size_t uxJobDocumentLength ); /** * @brief The task used to demonstrate the Jobs library API. @@ -398,6 +398,9 @@ static void prvProcessJobDocument( char * pcJobId, */ void prvJobsDemoTask( void * pvParameters ); +/*-----------------------------------------------------------*/ + +extern BaseType_t xPlatformIsNetworkUp( void ); /*-----------------------------------------------------------*/ @@ -473,7 +476,7 @@ static void prvSendUpdateForJob( char * pcJobId, static void prvProcessJobDocument( char * pcJobId, uint16_t usJobIdLength, char * pcJobDocument, - uint16_t jobDocumentLength ) + size_t uxJobDocumentLength ) { char * pcAction = NULL; size_t uActionLength = 0U; @@ -482,10 +485,10 @@ static void prvProcessJobDocument( char * pcJobId, configASSERT( pcJobId != NULL ); configASSERT( usJobIdLength > 0 ); configASSERT( pcJobDocument != NULL ); - configASSERT( jobDocumentLength > 0 ); + configASSERT( uxJobDocumentLength > 0 ); xJsonStatus = JSON_Search( pcJobDocument, - jobDocumentLength, + uxJobDocumentLength, jobsexampleQUERY_KEY_FOR_ACTION, jobsexampleQUERY_KEY_FOR_ACTION_LENGTH, &pcAction, @@ -516,7 +519,7 @@ static void prvProcessJobDocument( char * pcJobId, LogInfo( ( "Received job contains \"print\" action." ) ); xJsonStatus = JSON_Search( pcJobDocument, - jobDocumentLength, + uxJobDocumentLength, jobsexampleQUERY_KEY_FOR_MESSAGE, jobsexampleQUERY_KEY_FOR_MESSAGE_LENGTH, &pcMessage, @@ -548,7 +551,7 @@ static void prvProcessJobDocument( char * pcJobId, size_t ulTopicLength = 0U; xJsonStatus = JSON_Search( pcJobDocument, - jobDocumentLength, + uxJobDocumentLength, jobsexampleQUERY_KEY_FOR_TOPIC, jobsexampleQUERY_KEY_FOR_TOPIC_LENGTH, &pcTopic, @@ -563,7 +566,7 @@ static void prvProcessJobDocument( char * pcJobId, else { xJsonStatus = JSON_Search( pcJobDocument, - jobDocumentLength, + uxJobDocumentLength, jobsexampleQUERY_KEY_FOR_MESSAGE, jobsexampleQUERY_KEY_FOR_MESSAGE_LENGTH, &pcMessage, @@ -968,8 +971,8 @@ void prvJobsDemoTask( void * pvParameters ) { /* Handler function to process Jobs message payload. */ prvNextJobHandler( pxJobMessagePublishInfo ); - vPortFree( pxJobMessagePublishInfo->pTopicName ); - vPortFree( pxJobMessagePublishInfo->pPayload ); + vPortFree( ( void * ) ( pxJobMessagePublishInfo->pTopicName ) ); + vPortFree( ( void * ) ( pxJobMessagePublishInfo->pPayload ) ); vPortFree( pxJobMessagePublishInfo ); } diff --git a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/Jobs_Demo.vcxproj b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/Jobs_Demo.vcxproj index d0ed4806a58..95aecf4e96b 100644 --- a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/Jobs_Demo.vcxproj +++ b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/Jobs_Demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -31,26 +19,7 @@ true v142 Unicode - - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode + x86 @@ -60,85 +29,20 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\AWS\jobs\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - WIN32;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\AWS\jobs\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - _DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\AWS\jobs\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";%(PreprocessorDefinitions) true .\;..\..\Mqtt_Demo_Helpers;..\..\..\..\Source\AWS\jobs\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\Application-Protocols\network_transport;%(AdditionalIncludeDirectories) Console - true - true true diff --git a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/jobs_demo.sln b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/jobs_demo.sln index 68540f05180..1ea316e1b12 100644 --- a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/jobs_demo.sln +++ b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/jobs_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.31205.134 @@ -17,52 +16,19 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|x64 = Release|x64 - Release|x86 = Release|x86 + Debug|Win32 = Debug|Win32 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Debug|x64.ActiveCfg = Debug|x64 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Debug|x64.Build.0 = Debug|x64 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Debug|x86.ActiveCfg = Debug|Win32 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Debug|x86.Build.0 = Debug|Win32 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Release|x64.ActiveCfg = Release|x64 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Release|x64.Build.0 = Release|x64 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Release|x86.ActiveCfg = Release|Win32 - {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Release|x86.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 + {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Debug|Win32.ActiveCfg = Debug|Win32 + {9A8FD41D-DD8D-42C0-825A-266AEBD15C99}.Debug|Win32.Build.0 = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/main.c b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/main.c index f8ac235246d..7a3ff3f2ef5 100644 --- a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/main.c +++ b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/main.c @@ -54,6 +54,7 @@ extern void prvJobsDemoTask( void * pvParameters ); extern void vPlatformInitLogging( void ); +extern void vPlatformInitIpStack( void ); /*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/readme.url b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/readme.url new file mode 100644 index 00000000000..dc5a00fe2fd --- /dev/null +++ b/FreeRTOS-Plus/Demo/AWS/Jobs_Windows_Simulator/Jobs_Demo/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/04-AWS-libraries/04-AWS-IoT-Jobs/03-Jobs-demo diff --git a/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_demo_helpers.c b/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_demo_helpers.c index c7dde38a961..77520b9c545 100644 --- a/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_demo_helpers.c +++ b/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_demo_helpers.c @@ -363,6 +363,10 @@ static MQTTStatus_t prvProcessLoopWithTimeout( MQTTContext_t * pMqttContext, /*-----------------------------------------------------------*/ +extern UBaseType_t uxRand( void ); + +/*-----------------------------------------------------------*/ + static int32_t prvGenerateRandomNumber() { return( uxRand() & INT32_MAX ); @@ -797,7 +801,7 @@ BaseType_t xEstablishMqttSession( MQTTContext_t * pxMqttContext, } } - if( xReturnStatus == pdFAIL ) + if( xReturnStatus != pdFAIL ) { /* Keep a flag for indicating if MQTT session is established. This * flag will mark that an MQTT DISCONNECT has to be sent at the end diff --git a/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_pkcs11_demo_helpers.c b/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_pkcs11_demo_helpers.c index 8d4d8b0a75f..e284a5df028 100644 --- a/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_pkcs11_demo_helpers.c +++ b/FreeRTOS-Plus/Demo/AWS/Mqtt_Demo_Helpers/mqtt_pkcs11_demo_helpers.c @@ -359,6 +359,10 @@ static MQTTStatus_t prvProcessLoopWithTimeout( MQTTContext_t * pMqttContext, /*-----------------------------------------------------------*/ +extern UBaseType_t uxRand( void ); + +/*-----------------------------------------------------------*/ + static int32_t prvGenerateRandomNumber() { return( uxRand() & INT32_MAX ); @@ -794,7 +798,7 @@ BaseType_t xEstablishMqttSession( MQTTContext_t * pxMqttContext, } } - if( xReturnStatus == pdFAIL ) + if( xReturnStatus != pdFAIL ) { /* Keep a flag for indicating if MQTT session is established. This * flag will mark that an MQTT DISCONNECT has to be sent at the end diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Common/Ota_PAL/Win32/Code_Signature_Verification/code_signature_verification_mbedtls.c b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Common/Ota_PAL/Win32/Code_Signature_Verification/code_signature_verification_mbedtls.c index c769485750a..105b6fef81c 100644 --- a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Common/Ota_PAL/Win32/Code_Signature_Verification/code_signature_verification_mbedtls.c +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Common/Ota_PAL/Win32/Code_Signature_Verification/code_signature_verification_mbedtls.c @@ -40,7 +40,7 @@ /* mbedTLS includes. */ #if !defined( MBEDTLS_CONFIG_FILE ) - #include "mbedtls_config_v3.2.1.h" + #include "mbedtls_config_v3.5.1.h" #else #include MBEDTLS_CONFIG_FILE #endif diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/Ota_Over_Http_Demo.vcxproj b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/Ota_Over_Http_Demo.vcxproj index 06d191f1f3a..cfd0151e944 100644 --- a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/Ota_Over_Http_Demo.vcxproj +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/Ota_Over_Http_Demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,89 +28,21 @@ - - - - - - - - - true RTOSDemo - - false - RTOSDemo - - - true - RTOSDemo - - - false - RTOSDemo - Level3 false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;_DEBUG;_CONSOLE;WIN32;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - ..\Common\HTTP_Utils;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;WIN32;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - ..\Common\HTTP_Utils;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - ..\Common\HTTP_Utils;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) + MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;WIN32_LEAN_AND_MEAN;__little_endian__=1;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";%(PreprocessorDefinitions) true ..\Common\HTTP_Utils;..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) Console - true - true true diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/ota_over_http_demo.sln b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/ota_over_http_demo.sln index 25e640edaeb..80daa76eef3 100644 --- a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/ota_over_http_demo.sln +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/ota_over_http_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.31205.134 @@ -9,7 +8,7 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ww", "..\..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" EndProject @@ -20,85 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|Win32.ActiveCfg = Debug|Win32 {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|Win32.Build.0 = Debug|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x64.ActiveCfg = Debug|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x64.Build.0 = Debug|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x86.ActiveCfg = Debug|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x86.Build.0 = Debug|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|Win32.ActiveCfg = Release|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|Win32.Build.0 = Release|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x64.ActiveCfg = Release|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x64.Build.0 = Release|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x86.ActiveCfg = Release|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - 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{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x86.ActiveCfg = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x86.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x86.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/readme.url b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/readme.url new file mode 100644 index 00000000000..3b99946a8ed --- /dev/null +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Http_Demo/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/04-AWS-libraries/02-AWS-IoT-OTA/04-HTTP-demo diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/Ota_Over_Mqtt_Demo.vcxproj b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/Ota_Over_Mqtt_Demo.vcxproj index 8a310744de9..c40dbd588d5 100644 --- a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/Ota_Over_Mqtt_Demo.vcxproj +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/Ota_Over_Mqtt_Demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -33,26 +21,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -61,89 +29,21 @@ - - - - - - - - - true RTOSDemo - - false - RTOSDemo - - - true - RTOSDemo - - - false - RTOSDemo - Level3 false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;_DEBUG;_CONSOLE;WIN32;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - ..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;WIN32;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - ..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - ..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - false - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;__little_endian__=1;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" + MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;WIN32;WIN32_LEAN_AND_MEAN;__little_endian__=1;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h" true ..\..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\..\Source\Application-Protocols\network_transport;..\..\..\Common\coreMQTT_Agent_Interface\include;..\..\..\..\ThirdParty\tinycbor\src;..\..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\..\Source\coreJSON\source\include;..\..\..\..\Source\AWS\ota\source\include;..\..\..\..\Source\AWS\ota\source\portable\os;..\..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\Common\Ota_PAL\Win32\Code_Signature_Verification;..\Common\Ota_PAL\Win32;..\Common\subscription-manager;.\;%(AdditionalIncludeDirectories) Console - true - true true diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/demo_config.h b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/demo_config.h index e8c38fe495f..99c071bf4a5 100644 --- a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/demo_config.h +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/demo_config.h @@ -43,11 +43,11 @@ /* Logging configuration for the Demo. */ #ifndef LIBRARY_LOG_NAME #define LIBRARY_LOG_NAME "OTADemo" -#endif +#endif /* LIBRARY_LOG_NAME */ #ifndef LIBRARY_LOG_LEVEL #define LIBRARY_LOG_LEVEL LOG_DEBUG -#endif +#endif /* LIBRARY_LOG_LEVEL */ /* Prototype for the function used to print to console on Windows simulator * of FreeRTOS. diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/ota_over_mqtt_demo.sln b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/ota_over_mqtt_demo.sln index 1bf519237d5..2089fce8c12 100644 --- a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/ota_over_mqtt_demo.sln +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/ota_over_mqtt_demo.sln @@ -1,8 +1,9 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.31205.134 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Ota_Over_Mqtt_Demo", "Ota_Over_Mqtt_Demo.vcxproj", "{4BE4E103-5BF4-4A85-9656-EC20852A2B8E}" +EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries", "Statically Linked Libraries", "{9799AFF4-25E2-43CD-8829-C066177E3748}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" @@ -13,56 +14,21 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\..\Visu EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Ota_Over_Mqtt_Demo", "Ota_Over_Mqtt_Demo.vcxproj", "{4BE4E103-5BF4-4A85-9656-EC20852A2B8E}" -EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|x64 = Release|x64 - Release|x86 = Release|x86 + Debug|Win32 = Debug|Win32 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x64.ActiveCfg = Debug|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x64.Build.0 = Debug|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x86.ActiveCfg = Debug|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|x86.Build.0 = Debug|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x64.ActiveCfg = Release|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x64.Build.0 = Release|x64 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x86.ActiveCfg = Release|Win32 - {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Release|x86.Build.0 = Release|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 + {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|Win32.ActiveCfg = Debug|Win32 + {4BE4E103-5BF4-4A85-9656-EC20852A2B8E}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/readme.url b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/readme.url new file mode 100644 index 00000000000..97e770d371a --- /dev/null +++ b/FreeRTOS-Plus/Demo/AWS/Ota_Windows_Simulator/Ota_Over_Mqtt_Demo/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/04-AWS-libraries/02-AWS-IoT-OTA/03-MQTT-demo diff --git a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c index 5249a0cad12..4b5c0c54d29 100644 --- a/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c +++ b/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c @@ -69,6 +69,7 @@ static void prvUARTCommandConsoleTask( void * pvParameters ); void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); +void vOutputString( const char * const pcMessage ); /*-----------------------------------------------------------*/ @@ -110,7 +111,6 @@ static void prvUARTCommandConsoleTask( void * pvParameters ) char * pcOutputString; static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ]; BaseType_t xReturned; - xComPortHandle xPort; ( void ) pvParameters; diff --git a/FreeRTOS-Plus/Demo/Common/Logging/windows/Logging_WinSim.c b/FreeRTOS-Plus/Demo/Common/Logging/windows/Logging_WinSim.c index dd0c9a60170..c2e2881ccd1 100644 --- a/FreeRTOS-Plus/Demo/Common/Logging/windows/Logging_WinSim.c +++ b/FreeRTOS-Plus/Demo/Common/Logging/windows/Logging_WinSim.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -148,6 +149,39 @@ static size_t ulSizeOfLoggingFile = 0ul; Socket_t xPrintSocket = FREERTOS_INVALID_SOCKET; struct freertos_sockaddr xPrintUDPAddress; +/* The logging thread handle. */ +HANDLE pvLoggingThread = NULL; + +/* Windows event used to stop the logging thread and flush the logging buffer. */ +static void * pvLoggingThreadExitEvent = NULL; + +/*-----------------------------------------------------------*/ + +static BaseType_t prvStrEndedWithLineBreak( const char * pcStr ) +{ + BaseType_t xReturn; + size_t uxStrLen = strnlen( pcStr, dlMAX_PRINT_STRING_LENGTH ); + + if( uxStrLen < 2 ) + { + xReturn = pdFALSE; + } + else if( pcStr[ uxStrLen - 2 ] != '\r' ) + { + xReturn = pdFALSE; + } + else if( pcStr[ uxStrLen - 1 ] != '\n' ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + /*-----------------------------------------------------------*/ void vLoggingInit( BaseType_t xLogToStdout, @@ -161,8 +195,6 @@ void vLoggingInit( BaseType_t xLogToStdout, #if ( ( ipconfigHAS_DEBUG_PRINTF == 1 ) || ( ipconfigHAS_PRINTF == 1 ) ) { - HANDLE Win32Thread; - /* Record which output methods are to be used. */ xStdoutLoggingUsed = xLogToStdout; xDiskFileLoggingUsed = xLogToFile; @@ -209,21 +241,27 @@ void vLoggingInit( BaseType_t xLogToStdout, xLogStreamBuffer->LENGTH = dlLOGGING_STREAM_BUFFER_SIZE + 1; /* Create the Windows event. */ - pvLoggingThreadEvent = CreateEvent( NULL, FALSE, TRUE, "StdoutLoggingEvent" ); + pvLoggingThreadEvent = CreateEvent( NULL, FALSE, TRUE, L"StdoutLoggingEvent" ); + configASSERT( pvLoggingThreadEvent != NULL ); + + /* Create logging thread exit event to notify the logging thread. */ + pvLoggingThreadExitEvent = CreateEvent( NULL, FALSE, TRUE, L"LoggingThreadExitEvent" ); + configASSERT( pvLoggingThreadExitEvent != NULL ); /* Create the thread itself. */ - Win32Thread = CreateThread( + pvLoggingThread = CreateThread( NULL, /* Pointer to thread security attributes. */ 0, /* Initial thread stack size, in bytes. */ prvWin32LoggingThread, /* Pointer to thread function. */ NULL, /* Argument for new thread. */ 0, /* Creation flags. */ NULL ); + configASSERT( pvLoggingThread != NULL ); /* Use the cores that are not used by the FreeRTOS tasks. */ - SetThreadAffinityMask( Win32Thread, ~0x01u ); - SetThreadPriorityBoost( Win32Thread, TRUE ); - SetThreadPriority( Win32Thread, THREAD_PRIORITY_IDLE ); + SetThreadAffinityMask( pvLoggingThread, ~0x01u ); + SetThreadPriorityBoost( pvLoggingThread, TRUE ); + SetThreadPriority( pvLoggingThread, THREAD_PRIORITY_IDLE ); } } #else /* if ( ( ipconfigHAS_DEBUG_PRINTF == 1 ) || ( ipconfigHAS_PRINTF == 1 ) ) */ @@ -297,19 +335,30 @@ void vLoggingPrintf( const char * pcFormat, pcTaskName = pcNoTask; } + /* Print metadata only after line break. Metadata won't be printed in string + * contains line break only. */ if( ( xAfterLineBreak == pdTRUE ) && ( strcmp( pcFormat, "\r\n" ) != 0 ) ) { xLength = snprintf( cPrintString, dlMAX_PRINT_STRING_LENGTH, "%lu %lu [%s] ", xMessageNumber++, ( unsigned long ) xTaskGetTickCount(), pcTaskName ); - xAfterLineBreak = pdFALSE; + + /* Print metadata for next message if this message ends with line + * break. */ + xAfterLineBreak = prvStrEndedWithLineBreak( pcFormat ); } else { xLength = 0; memset( cPrintString, 0x00, dlMAX_PRINT_STRING_LENGTH ); - xAfterLineBreak = pdTRUE; + + /* Continue to print without metadata if the string doesn't end with line + * break. */ + if( prvStrEndedWithLineBreak( pcFormat ) != pdFALSE ) + { + xAfterLineBreak = pdTRUE; + } } xLength2 = vsnprintf( cPrintString + xLength, dlMAX_PRINT_STRING_LENGTH - xLength, pcFormat, args ); @@ -348,7 +397,7 @@ void vLoggingPrintf( const char * pcFormat, pcTarget--; } - sscanf( pcTarget, "%8X", &ulIPAddress ); + ( void ) sscanf( pcTarget, "%8X", &ulIPAddress ); rc = sprintf( pcTarget, "%lu.%lu.%lu.%lu", ( unsigned long ) ( ulIPAddress >> 24UL ), ( unsigned long ) ( ( ulIPAddress >> 16UL ) & 0xffUL ), @@ -486,7 +535,18 @@ static DWORD WINAPI prvWin32LoggingThread( void * pvParameter ) /* Write out all waiting messages. */ prvLoggingFlushBuffer(); + + /* Check if the exit event is signaled. */ + if( WaitForSingleObject( pvLoggingThreadExitEvent, 0 ) == WAIT_OBJECT_0 ) + { + break; + } } + + /* Enable direct print after logging thread exit. */ + xDirectPrint = pdTRUE; + + return 0; } /*-----------------------------------------------------------*/ @@ -541,7 +601,7 @@ static void prvLogToFile( const char * pcMessage, remove( pcFullLogFileName ); } - rename( pcLogFileName, pcFullLogFileName ); + ( void ) rename( pcLogFileName, pcFullLogFileName ); ulSizeOfLoggingFile = 0; } } @@ -553,3 +613,18 @@ void vPlatformInitLogging( void ) vLoggingInit( pdTRUE, pdFALSE, pdFALSE, 0U, 0U ); } /*-----------------------------------------------------------*/ + +void vPlatformStopLoggingThreadAndFlush( void ) +{ + #if ( ( ipconfigHAS_DEBUG_PRINTF == 1 ) || ( ipconfigHAS_PRINTF == 1 ) ) + if( xLogStreamBuffer != NULL ) + { + SetEvent( pvLoggingThreadExitEvent ); + + WaitForSingleObject( pvLoggingThread, INFINITE ); + + prvLoggingFlushBuffer(); + } + #endif /* #if ( ( ipconfigHAS_DEBUG_PRINTF == 1 ) || ( ipconfigHAS_PRINTF == 1 ) ) */ +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Demo/Common/coreMQTT_Agent_Interface/freertos_command_pool.c b/FreeRTOS-Plus/Demo/Common/coreMQTT_Agent_Interface/freertos_command_pool.c index 153a18c4db2..ea4a69c0fe7 100644 --- a/FreeRTOS-Plus/Demo/Common/coreMQTT_Agent_Interface/freertos_command_pool.c +++ b/FreeRTOS-Plus/Demo/Common/coreMQTT_Agent_Interface/freertos_command_pool.c @@ -41,6 +41,9 @@ #include "freertos_command_pool.h" #include "freertos_agent_message.h" +/* Demo config include. */ +#include "demo_config.h" + /*-----------------------------------------------------------*/ #define QUEUE_NOT_INITIALIZED ( 0U ) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/MutualAuthMQTTExample.c b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/MutualAuthMQTTExample.c index 9d06bf8995b..e79d5bfa707 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/MutualAuthMQTTExample.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/MutualAuthMQTTExample.c @@ -213,11 +213,6 @@ */ #define mqttexampleTRANSPORT_SEND_RECV_TIMEOUT_MS ( 5000U ) -/** - * @brief Transport timeout in milliseconds for transport send and receive. - */ -#define mqttexampleTRANSPORT_SEND_RECV_TIMEOUT_MS ( 200U ) - /** * @brief The length of the outgoing publish records array used by the coreMQTT * library to track QoS > 0 packet ACKS for outgoing publishes. @@ -404,6 +399,10 @@ static MQTTStatus_t prvProcessLoopWithTimeout( MQTTContext_t * pMqttContext, /*-----------------------------------------------------------*/ +extern UBaseType_t uxRand(); + +/*-----------------------------------------------------------*/ + /** * @brief Static buffer used to hold MQTT messages being sent and received. */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/comm_if_windows.c b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/comm_if_windows.c index 4412df1d9d9..f3f6b691c5e 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/comm_if_windows.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/Common/comm_if_windows.c @@ -48,37 +48,23 @@ #ifndef CELLULAR_COMM_INTERFACE_PORT #error "Define CELLULAR_COMM_INTERFACE_PORT in cellular_config.h" #endif -#define CELLULAR_COMM_PATH "\\\\.\\"CELLULAR_COMM_INTERFACE_PORT +#define CELLULAR_COMM_PATH "\\\\.\\"CELLULAR_COMM_INTERFACE_PORT /* Define the simulated UART interrupt number. */ -#define portINTERRUPT_UART ( 2UL ) +#define appINTERRUPT_UART portINTERRUPT_APPLICATION_DEFINED_START /* Define the read write buffer size. */ -#define COMM_TX_BUFFER_SIZE ( 8192 ) -#define COMM_RX_BUFFER_SIZE ( 8192 ) +#define COMM_TX_BUFFER_SIZE ( 8192 ) +#define COMM_RX_BUFFER_SIZE ( 8192 ) /* Receive thread timeout in ms. */ -#define COMM_RECV_THREAD_TIMEOUT ( 5000 ) +#define COMM_RECV_THREAD_TIMEOUT ( 5000 ) /* Write operation timeout in ms. */ -#define COMM_WRITE_OPERATION_TIMEOUT ( 500 ) +#define COMM_WRITE_OPERATION_TIMEOUT ( 500 ) /* Comm status. */ -#define CELLULAR_COMM_OPEN_BIT ( 0x01U ) - -/* Comm task event. */ -#define COMMTASK_EVT_MASK_STARTED ( 0x0001UL ) -#define COMMTASK_EVT_MASK_ABORT ( 0x0002UL ) -#define COMMTASK_EVT_MASK_ABORTED ( 0x0004UL ) -#define COMMTASK_EVT_MASK_ALL_EVENTS \ - ( COMMTASK_EVT_MASK_STARTED \ - | COMMTASK_EVT_MASK_ABORT \ - | COMMTASK_EVT_MASK_ABORTED ) -#define COMMTASK_POLLING_TIME_MS ( 1UL ) - -/* Platform thread stack size and priority. */ -#define COMM_IF_THREAD_DEFAULT_STACK_SIZE ( 2048U ) -#define COMM_IF_THREAD_DEFAULT_PRIORITY ( tskIDLE_PRIORITY + 5U ) +#define CELLULAR_COMM_OPEN_BIT ( 0x01U ) /*-----------------------------------------------------------*/ @@ -91,7 +77,6 @@ typedef struct cellularCommContext HANDLE commFileHandle; CellularCommInterface_t * pCommInterface; bool commTaskThreadStarted; - EventGroupHandle_t pCommTaskEvent; } cellularCommContext_t; /*-----------------------------------------------------------*/ @@ -126,14 +111,6 @@ static CellularCommInterfaceError_t prvCommIntfReceive( CellularCommInterfaceHan */ static CellularCommInterfaceError_t prvCommIntfClose( CellularCommInterfaceHandle_t commInterfaceHandle ); -/** - * @brief Get default comm interface context. - * - * @return On success, SOCKETS_ERROR_NONE is returned. If an error occurred, error code defined - * in sockets_wrapper.h is returned. - */ -static cellularCommContext_t * prvGetCellularCommContext( void ); - /** * @brief UART interrupt handler. * @@ -168,34 +145,7 @@ static CellularCommInterfaceError_t prvSetupCommTimeout( HANDLE hComm ); * @return On success, IOT_COMM_INTERFACE_SUCCESS is returned. If an error occurred, error code defined * in CellularCommInterfaceError_t is returned. */ -static CellularCommInterfaceError_t prvSetupCommSettings( HANDLE hComm ); - -/** - * @brief Thread routine to generate simulated interrupt. - * - * @param[in] pUserData Pointer to cellularCommContext_t allocated in comm interface open. - */ -static void prvCommTaskThread( void * pUserData ); - -/** - * @brief Helper function to setup and create commTaskThread. - * - * @param[in] pCellularCommContext Cellular comm interface context allocated in open. - * - * @return On success, IOT_COMM_INTERFACE_SUCCESS is returned. If an error occurred, error code defined - * in CellularCommInterfaceError_t is returned. - */ -static CellularCommInterfaceError_t prvSetupCommTaskThread( cellularCommContext_t * pCellularCommContext ); - -/** - * @brief Helper function to clean commTaskThread. - * - * @param[in] pCellularCommContext Cellular comm interface context allocated in open. - * - * @return On success, IOT_COMM_INTERFACE_SUCCESS is returned. If an error occurred, error code defined - * in CellularCommInterfaceError_t is returned. - */ -static CellularCommInterfaceError_t prvCleanCommTaskThread( cellularCommContext_t * pCellularCommContext ); +static CellularCommInterfaceError_t prvSetupCommState( HANDLE hComm ); /*-----------------------------------------------------------*/ @@ -215,28 +165,14 @@ static cellularCommContext_t uxCellularCommContext = .commFileHandle = NULL, .pUserData = NULL, .commStatus = 0U, - .commTaskThreadStarted = false, - .pCommTaskEvent = NULL + .commTaskThreadStarted = false }; -/* Mutex used to protect rxEvent variables that are accessed by multiple threads. */ -static void * pvRxEventMutex = NULL; - -/* Indicate RX event is received in comm driver. */ -static bool rxEvent = false; - -/*-----------------------------------------------------------*/ - -static cellularCommContext_t * prvGetCellularCommContext( void ) -{ - return &uxCellularCommContext; -} - /*-----------------------------------------------------------*/ static uint32_t prvProcessUartInt( void ) { - cellularCommContext_t * pCellularCommContext = prvGetCellularCommContext(); + cellularCommContext_t * pCellularCommContext = &uxCellularCommContext; CellularCommInterfaceError_t callbackRet = IOT_COMM_INTERFACE_FAILURE; uint32_t retUartInt = pdTRUE; @@ -271,35 +207,35 @@ static DWORD WINAPI prvCellularCommReceiveCBThreadFunc( LPVOID pArgument ) { retValue = ERROR_INVALID_HANDLE; } - - while( retValue == 0 ) + else { - retWait = WaitCommEvent( hComm, &dwCommStatus, NULL ); - - if( ( retWait != FALSE ) && ( ( dwCommStatus & EV_RXCHAR ) != 0 ) ) - { - if( ( dwCommStatus & EV_RXCHAR ) != 0 ) - { - WaitForSingleObject( pvRxEventMutex, INFINITE ); - rxEvent = true; - ReleaseMutex( pvRxEventMutex ); - } - } - else + for( ; ; ) { - if( ( GetLastError() == ERROR_INVALID_HANDLE ) || ( GetLastError() == ERROR_OPERATION_ABORTED ) ) + retWait = WaitCommEvent( hComm, &dwCommStatus, NULL ); + + if( ( retWait != FALSE ) && ( ( dwCommStatus & EV_RXCHAR ) != 0 ) ) { - /* COM port closed. */ - LogInfo( ( "Cellular COM port %p closed", hComm ) ); + /* Generate a simulated interrupt when data is received in the input buffer in driver. + * The interrupt handler prvProcessUartInt() will be called in prvProcessSimulatedInterrupts(). + * This ensures no other task or ISR is running. */ + vPortGenerateSimulatedInterruptFromWindowsThread( appINTERRUPT_UART ); } else { - LogInfo( ( "Cellular receiver thread wait comm error %p %d", hComm, GetLastError() ) ); - } + retValue = GetLastError(); - retValue = GetLastError(); + if( ( retValue == ERROR_INVALID_HANDLE ) || ( retValue == ERROR_OPERATION_ABORTED ) ) + { + /* COM port closed. */ + LogInfo( ( "Cellular COM port %p closed", hComm ) ); + } + else + { + LogInfo( ( "Cellular receiver thread wait comm error %p %d", hComm, retValue ) ); + } - break; + break; + } } } @@ -335,7 +271,7 @@ static CellularCommInterfaceError_t prvSetupCommTimeout( HANDLE hComm ) /*-----------------------------------------------------------*/ -static CellularCommInterfaceError_t prvSetupCommSettings( HANDLE hComm ) +static CellularCommInterfaceError_t prvSetupCommState( HANDLE hComm ) { CellularCommInterfaceError_t commIntRet = IOT_COMM_INTERFACE_SUCCESS; DCB dcbSerialParams = { 0 }; @@ -367,146 +303,6 @@ static CellularCommInterfaceError_t prvSetupCommSettings( HANDLE hComm ) /*-----------------------------------------------------------*/ -static void prvCommTaskThread( void * pUserData ) -{ - cellularCommContext_t * pCellularCommContext = ( cellularCommContext_t * ) pUserData; - EventBits_t uxBits = 0; - - /* Inform thread ready. */ - LogInfo( ( "Cellular commTaskThread started" ) ); - - if( pCellularCommContext != NULL ) - { - ( void ) xEventGroupSetBits( pCellularCommContext->pCommTaskEvent, - COMMTASK_EVT_MASK_STARTED ); - } - - while( true ) - { - /* Wait for notification from eventqueue. */ - uxBits = xEventGroupWaitBits( ( pCellularCommContext->pCommTaskEvent ), - ( ( EventBits_t ) COMMTASK_EVT_MASK_ABORT ), - pdTRUE, - pdFALSE, - pdMS_TO_TICKS( COMMTASK_POLLING_TIME_MS ) ); - - if( ( uxBits & ( EventBits_t ) COMMTASK_EVT_MASK_ABORT ) != 0U ) - { - LogDebug( ( "Abort received, cleaning up!" ) ); - break; - } - else - { - /* Polling the global share variable to trigger the interrupt. */ - if( rxEvent == true ) - { - WaitForSingleObject( pvRxEventMutex, INFINITE ); - rxEvent = false; - ReleaseMutex( pvRxEventMutex ); - - vPortGenerateSimulatedInterrupt( portINTERRUPT_UART ); - } - } - } - - /* Inform thread ready. */ - if( pCellularCommContext != NULL ) - { - ( void ) xEventGroupSetBits( pCellularCommContext->pCommTaskEvent, COMMTASK_EVT_MASK_ABORTED ); - } - - LogInfo( ( "Cellular commTaskThread exit" ) ); -} - -/*-----------------------------------------------------------*/ - -static CellularCommInterfaceError_t prvSetupCommTaskThread( cellularCommContext_t * pCellularCommContext ) -{ - BOOL Status = TRUE; - EventBits_t uxBits = 0; - CellularCommInterfaceError_t commIntRet = IOT_COMM_INTERFACE_SUCCESS; - - pCellularCommContext->pCommTaskEvent = xEventGroupCreate(); - - if( pCellularCommContext->pCommTaskEvent != NULL ) - { - /* Create the FreeRTOS thread to generate the simulated interrupt. */ - Status = Platform_CreateDetachedThread( prvCommTaskThread, - ( void * ) pCellularCommContext, - COMM_IF_THREAD_DEFAULT_PRIORITY, - COMM_IF_THREAD_DEFAULT_STACK_SIZE ); - - if( Status != true ) - { - commIntRet = IOT_COMM_INTERFACE_FAILURE; - } - } - else - { - commIntRet = IOT_COMM_INTERFACE_FAILURE; - } - - if( commIntRet == IOT_COMM_INTERFACE_SUCCESS ) - { - uxBits = xEventGroupWaitBits( ( pCellularCommContext->pCommTaskEvent ), - ( ( EventBits_t ) COMMTASK_EVT_MASK_STARTED | ( EventBits_t ) COMMTASK_EVT_MASK_ABORTED ), - pdTRUE, - pdFALSE, - portMAX_DELAY ); - - if( ( uxBits & ( EventBits_t ) COMMTASK_EVT_MASK_STARTED ) == COMMTASK_EVT_MASK_STARTED ) - { - pCellularCommContext->commTaskThreadStarted = true; - } - else - { - commIntRet = IOT_COMM_INTERFACE_FAILURE; - pCellularCommContext->commTaskThreadStarted = false; - } - } - - return commIntRet; -} - -/*-----------------------------------------------------------*/ - -static CellularCommInterfaceError_t prvCleanCommTaskThread( cellularCommContext_t * pCellularCommContext ) -{ - EventBits_t uxBits = 0; - CellularCommInterfaceError_t commIntRet = IOT_COMM_INTERFACE_SUCCESS; - - /* Wait for the commTaskThreadStarted exit. */ - if( ( pCellularCommContext->commTaskThreadStarted == true ) && ( pCellularCommContext->pCommTaskEvent != NULL ) ) - { - ( void ) xEventGroupSetBits( pCellularCommContext->pCommTaskEvent, - COMMTASK_EVT_MASK_ABORT ); - uxBits = xEventGroupWaitBits( ( pCellularCommContext->pCommTaskEvent ), - ( ( EventBits_t ) COMMTASK_EVT_MASK_ABORTED ), - pdTRUE, - pdFALSE, - portMAX_DELAY ); - - if( ( uxBits & ( EventBits_t ) COMMTASK_EVT_MASK_ABORTED ) != COMMTASK_EVT_MASK_ABORTED ) - { - LogDebug( ( "Cellular close wait commTaskThread fail" ) ); - commIntRet = IOT_COMM_INTERFACE_FAILURE; - } - - pCellularCommContext->commTaskThreadStarted = false; - } - - /* Clean the event group. */ - if( pCellularCommContext->pCommTaskEvent != NULL ) - { - vEventGroupDelete( pCellularCommContext->pCommTaskEvent ); - pCellularCommContext->pCommTaskEvent = NULL; - } - - return commIntRet; -} - -/*-----------------------------------------------------------*/ - static CellularCommInterfaceError_t prvCommIntfOpen( CellularCommInterfaceReceiveCallback_t receiveCallback, void * pUserData, CellularCommInterfaceHandle_t * pCommInterfaceHandle ) @@ -514,7 +310,7 @@ static CellularCommInterfaceError_t prvCommIntfOpen( CellularCommInterfaceReceiv CellularCommInterfaceError_t commIntRet = IOT_COMM_INTERFACE_SUCCESS; HANDLE hComm = ( HANDLE ) INVALID_HANDLE_VALUE; BOOL Status = TRUE; - cellularCommContext_t * pCellularCommContext = prvGetCellularCommContext(); + cellularCommContext_t * pCellularCommContext = &uxCellularCommContext; DWORD dwRes = 0; if( pCellularCommContext == NULL ) @@ -543,7 +339,7 @@ static CellularCommInterfaceError_t prvCommIntfOpen( CellularCommInterfaceReceiv } /* Comm port is just closed. Wait 1 second and retry. */ - if( ( hComm == ( HANDLE ) INVALID_HANDLE_VALUE ) && ( GetLastError() == 5 ) ) + if( ( hComm == ( HANDLE ) INVALID_HANDLE_VALUE ) && ( GetLastError() == ERROR_ACCESS_DENIED ) ) { vTaskDelay( pdMS_TO_TICKS( 1000UL ) ); hComm = CreateFile( TEXT( CELLULAR_COMM_PATH ), @@ -578,7 +374,7 @@ static CellularCommInterfaceError_t prvCommIntfOpen( CellularCommInterfaceReceiv if( commIntRet == IOT_COMM_INTERFACE_SUCCESS ) { - commIntRet = prvSetupCommSettings( hComm ); + commIntRet = prvSetupCommState( hComm ); } if( commIntRet == IOT_COMM_INTERFACE_SUCCESS ) @@ -592,26 +388,11 @@ static CellularCommInterfaceError_t prvCommIntfOpen( CellularCommInterfaceReceiv } } - /* Create RX event mutex to protect rxEvent. */ - if( commIntRet == IOT_COMM_INTERFACE_SUCCESS ) - { - pvRxEventMutex = CreateMutex( NULL, FALSE, NULL ); - - if( pvRxEventMutex == NULL ) - { - commIntRet = IOT_COMM_INTERFACE_FAILURE; - } - } - if( commIntRet == IOT_COMM_INTERFACE_SUCCESS ) { pCellularCommContext->commReceiveCallback = receiveCallback; - commIntRet = prvSetupCommTaskThread( pCellularCommContext ); - } - if( commIntRet == IOT_COMM_INTERFACE_SUCCESS ) - { - vPortSetInterruptHandler( portINTERRUPT_UART, prvProcessUartInt ); + vPortSetInterruptHandler( appINTERRUPT_UART, prvProcessUartInt ); pCellularCommContext->commReceiveCallbackThread = CreateThread( NULL, 0, prvCellularCommReceiveCBThreadFunc, hComm, 0, NULL ); @@ -653,16 +434,6 @@ static CellularCommInterfaceError_t prvCommIntfOpen( CellularCommInterfaceReceiv } pCellularCommContext->commReceiveCallbackThread = NULL; - - /* Wait for the commTaskThreadStarted exit. */ - ( void ) prvCleanCommTaskThread( pCellularCommContext ); - - /* Clean the rxEvent mutex. */ - if( pvRxEventMutex != NULL ) - { - CloseHandle( pvRxEventMutex ); - pvRxEventMutex = NULL; - } } return commIntRet; @@ -731,16 +502,6 @@ static CellularCommInterfaceError_t prvCommIntfClose( CellularCommInterfaceHandl pCellularCommContext->commReceiveCallbackThread = NULL; - /* Clean the commTaskThread. */ - ( void ) prvCleanCommTaskThread( pCellularCommContext ); - - /* Clean the rxEvent mutex. */ - if( pvRxEventMutex != NULL ) - { - CloseHandle( pvRxEventMutex ); - pvRxEventMutex = NULL; - } - /* clean the data structure. */ pCellularCommContext->commStatus &= ~( CELLULAR_COMM_OPEN_BIT ); } diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.sln index 58c08157f3d..e13fc8208da 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -11,66 +10,36 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualS EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" +EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries", "Statically Linked Libraries", "{68385DE7-AC0F-4213-BEEA-D07E484C093E}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution + {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug_with_Libslirp|Win32.ActiveCfg = Debug|Win32 + {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug_with_Libslirp|Win32.Build.0 = Debug|Win32 {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|Win32.ActiveCfg = Debug|Win32 {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|Win32.Build.0 = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x64.ActiveCfg = Debug|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x64.Build.0 = Debug|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x86.ActiveCfg = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x86.Build.0 = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|Win32.ActiveCfg = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|Win32.Build.0 = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x64.ActiveCfg = Release|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x64.Build.0 = Release|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x86.ActiveCfg = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x86.Build.0 = Release|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE @@ -79,6 +48,7 @@ Global {72C209C4-49A4-4942-A201-44706C9D77EC} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} {BE362AC0-B10B-4276-B84E-6304652BA228} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} + {C90E6CC5-818B-4C97-8876-0986D989387C} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution SolutionGuid = {1D441E01-8E23-4433-9EF0-63467713C0F0} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.vcxproj index 6ff7568f44f..8f2a1b80c15 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_BG96/mqtt_mutual_auth_demo_with_bg96.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,90 +28,24 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - Bcrypt.lib;%(AdditionalDependencies) - - - - - Level3 - true - true - true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface Console - true - true true Bcrypt.lib;%(AdditionalDependencies) - - - Level3 - true - _DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.sln index ead372158a9..fd103c72fb7 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -11,66 +10,36 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualS EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" +EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries", "Statically Linked Libraries", "{68385DE7-AC0F-4213-BEEA-D07E484C093E}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution + {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug_with_Libslirp|Win32.ActiveCfg = Debug|Win32 + {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug_with_Libslirp|Win32.Build.0 = Debug|Win32 {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|Win32.ActiveCfg = Debug|Win32 {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|Win32.Build.0 = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x64.ActiveCfg = Debug|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x64.Build.0 = Debug|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x86.ActiveCfg = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x86.Build.0 = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|Win32.ActiveCfg = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|Win32.Build.0 = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x64.ActiveCfg = Release|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x64.Build.0 = Release|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x86.ActiveCfg = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x86.Build.0 = Release|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE @@ -79,6 +48,7 @@ Global {72C209C4-49A4-4942-A201-44706C9D77EC} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} {BE362AC0-B10B-4276-B84E-6304652BA228} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} + {C90E6CC5-818B-4C97-8876-0986D989387C} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution SolutionGuid = {1D441E01-8E23-4433-9EF0-63467713C0F0} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.vcxproj index 05788e49101..5d5775ec3c2 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_HL7802/mqtt_mutual_auth_demo_with_hl7802.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -33,26 +21,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -61,90 +29,24 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - Bcrypt.lib;%(AdditionalDependencies) - - - - - Level3 - true - true - true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface Console - true - true true Bcrypt.lib;%(AdditionalDependencies) - - - Level3 - true - _DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.sln index 0e190eb4c22..fe513cdea16 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -11,66 +10,36 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualS EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" +EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries", "Statically Linked Libraries", "{68385DE7-AC0F-4213-BEEA-D07E484C093E}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution + {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug_with_Libslirp|Win32.ActiveCfg = Debug|Win32 + {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug_with_Libslirp|Win32.Build.0 = Debug|Win32 {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|Win32.ActiveCfg = Debug|Win32 {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|Win32.Build.0 = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x64.ActiveCfg = Debug|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x64.Build.0 = Debug|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x86.ActiveCfg = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Debug|x86.Build.0 = Debug|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|Win32.ActiveCfg = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|Win32.Build.0 = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x64.ActiveCfg = Release|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x64.Build.0 = Release|x64 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x86.ActiveCfg = Release|Win32 - {D5CD24A7-76BA-41EA-AFD7-86DECF58FBC1}.Release|x86.Build.0 = Release|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE @@ -79,6 +48,7 @@ Global {72C209C4-49A4-4942-A201-44706C9D77EC} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} {BE362AC0-B10B-4276-B84E-6304652BA228} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} + {C90E6CC5-818B-4C97-8876-0986D989387C} = {68385DE7-AC0F-4213-BEEA-D07E484C093E} EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution SolutionGuid = {1D441E01-8E23-4433-9EF0-63467713C0F0} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.vcxproj index d54a6c9e2d6..c1fc78bd0bb 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/MQTT_Mutual_Auth_Demo_with_SARA_R4/mqtt_mutual_auth_demo_with_sara_r4.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,90 +28,24 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - Bcrypt.lib;%(AdditionalDependencies) - - - - - Level3 - true - true - true - WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface Console - true - true true Bcrypt.lib;%(AdditionalDependencies) - - - Level3 - true - _DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\common;..\..\..\Source\FreeRTOS-Cellular-Interface\source\include\private;..\..\..\Source\FreeRTOS-Cellular-Interface\source\interface - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/readme.url b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/readme.url new file mode 100644 index 00000000000..b5685f54de2 --- /dev/null +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Cellular_Interface_Windows_Simulator/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/03-FreeRTOS-core/09-Cellular-interface/03-Cellular-interface-demo diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln index a39dd12930a..48709010fdf 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -16,61 +15,16 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {F135BC22-C210-45F7-9973-119C839C46D4}.Debug|Win32.ActiveCfg = Debug|Win32 {F135BC22-C210-45F7-9973-119C839C46D4}.Debug|Win32.Build.0 = Debug|Win32 - {F135BC22-C210-45F7-9973-119C839C46D4}.Debug|x64.ActiveCfg = Debug|x64 - {F135BC22-C210-45F7-9973-119C839C46D4}.Debug|x64.Build.0 = Debug|x64 - {F135BC22-C210-45F7-9973-119C839C46D4}.Debug|x86.ActiveCfg = Debug|Win32 - {F135BC22-C210-45F7-9973-119C839C46D4}.Debug|x86.Build.0 = Debug|Win32 - {F135BC22-C210-45F7-9973-119C839C46D4}.Release|Win32.ActiveCfg = Release|Win32 - {F135BC22-C210-45F7-9973-119C839C46D4}.Release|Win32.Build.0 = Release|Win32 - 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- - Console - true - - - - - Level3 - true - true - true - _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - ..\..\Source\FreeRTOS-Plus-Trace\Include;..\..\Source\FreeRTOS-Plus-CLI;.\Trace_Recorder_Configuration;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - {c90e6cc5-818b-4c97-8876-0986d989387c} diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj deleted file mode 100644 index 9fd48a71d3b..00000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj +++ /dev/null @@ -1,162 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - - {C686325E-3261-42F7-AEB1-DDE5280E1CEB} - RTOSDemo - - - - Application - false - MultiByte - v142 - - - Application - false - MultiByte - v142 - - - - - - - - - - - - - - - <_ProjectFileVersion>10.0.30319.1 - .\Debug\ - .\Debug\ - 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Demo App Source\Trace Recorder Configuration - - - Demo App Source\Trace Recorder Configuration - - - \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.url similarity index 79% rename from FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url rename to FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.url index 382f920623d..03c4528ec9b 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.url @@ -1,5 +1,5 @@ -[InternetShortcut] -URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml -IDList= [{000214A0-0000-0000-C000-000000000046}] Prop3=19,2 +[InternetShortcut] +IDList= +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.html diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln index c5143a31ce9..9a23e577223 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln @@ -1,4 +1,3 @@ - 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{BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.vcxproj index 071d5de2db3..43e9139f43c 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,28 +28,10 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 @@ -95,50 +45,6 @@ true - - - Level3 - true - true - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - Console - true - true - true - - - - - Level3 - true - _DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSConfig.h index 7ec703eb811..9737440b5c9 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSConfig.h +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSConfig.h @@ -168,22 +168,19 @@ extern void vAssertCalled( const char * const pcFileName, * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/UDP_Echo_Clients.html */ -#define configECHO_SERVER_ADDR0 127 -#define configECHO_SERVER_ADDR1 0 -#define configECHO_SERVER_ADDR2 0 -#define configECHO_SERVER_ADDR3 1 +#define configECHO_SERVER_ADDR "172.31.69.236" /* Default MAC address configuration. The demo creates a virtual network * connection that uses this MAC address by accessing the raw Ethernet/WiFi data * to and from a real network connection on the host PC. See the * configNETWORK_INTERFACE_TO_USE definition above for information on how to * configure the real network connection to use. */ -#define configMAC_ADDR0 0x00 -#define configMAC_ADDR1 0x11 -#define configMAC_ADDR2 0x22 -#define configMAC_ADDR3 0x33 -#define configMAC_ADDR4 0x44 -#define configMAC_ADDR5 0x41 +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x11 +#define configMAC_ADDR2 0x22 +#define configMAC_ADDR3 0x33 +#define configMAC_ADDR4 0x44 +#define configMAC_ADDR5 0x41 /* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or * ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ @@ -205,19 +202,22 @@ extern void vAssertCalled( const char * const pcFileName, * 208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set * to 1 but a DNS server cannot be contacted.*/ -#define configDNS_SERVER_ADDR0 10 -#define configDNS_SERVER_ADDR1 4 -#define configDNS_SERVER_ADDR2 4 -#define configDNS_SERVER_ADDR3 10 +#define configDNS_SERVER_ADDR0 10 +#define configDNS_SERVER_ADDR1 4 +#define configDNS_SERVER_ADDR2 4 +#define configDNS_SERVER_ADDR3 10 /* Default netmask configuration. Used in ipconfigUSE_DNS is set to 0, or * ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ -#define configNET_MASK0 255 -#define configNET_MASK1 255 -#define configNET_MASK2 240 -#define configNET_MASK3 0 +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 240 +#define configNET_MASK3 0 /* The UDP port to which print messages are sent. */ -#define configPRINT_PORT ( 15000 ) +#define configPRINT_PORT ( 15000 ) + +/* Use kernel provided static memory for timer and idle tasks. */ +#define configKERNEL_PROVIDED_STATIC_MEMORY 1 #endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSIPConfig.h index 070ee6cc1db..cb9ef22a9e3 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/FreeRTOSIPConfig.h @@ -35,6 +35,11 @@ #ifndef FREERTOS_IP_CONFIG_H #define FREERTOS_IP_CONFIG_H +#ifdef HEAP3 + #define xPortGetMinimumEverFreeHeapSize( x ) 0 + #define xPortGetFreeHeapSize() 0 +#endif + /* Prototype for the function used to print out. In this case it prints to the * console before the network is connected then a UDP port after the network has * connected. */ @@ -67,33 +72,33 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOS_netstat() command, and ping replies. If ipconfigHAS_PRINTF is set to 1 * then FreeRTOS_printf should be set to the function used to print out the * messages. */ -#define ipconfigHAS_PRINTF 0 +#define ipconfigHAS_PRINTF 1 #if ( ipconfigHAS_PRINTF == 1 ) #define FreeRTOS_printf( X ) vLoggingPrintf X #endif /* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ -#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN /* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software * stack repeating the checksum calculations. */ -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 /* Several API's will block until the result is known, or the action has been * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be * set per socket, using setsockopt(). If not set, the times below will be * used as defaults. */ -#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) -#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) /* Include support for LLMNR: Link-local Multicast Name Resolution * (non-Microsoft) */ -#define ipconfigUSE_LLMNR ( 1 ) +#define ipconfigUSE_LLMNR ( 1 ) /* Include support for NBNS: NetBIOS Name Service (Microsoft) */ -#define ipconfigUSE_NBNS ( 1 ) +#define ipconfigUSE_NBNS ( 1 ) /* Include support for DNS caching. For TCP, having a small DNS cache is very * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low @@ -101,10 +106,10 @@ extern void vLoggingPrintf( const char * pcFormatString, * socket has been destroyed, the result will be stored into the cache. The next * call to FreeRTOS_gethostbyname() will return immediately, without even creating * a socket. */ -#define ipconfigUSE_DNS_CACHE ( 1 ) -#define ipconfigDNS_CACHE_NAME_LENGTH ( 16 ) -#define ipconfigDNS_CACHE_ENTRIES ( 4 ) -#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) +#define ipconfigUSE_DNS_CACHE ( 1 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 16 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) /* The IP stack executes it its own task (although any application task can make * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY @@ -115,22 +120,14 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to * the priority assigned to the task executing the IP stack relative to the * priority assigned to tasks that use the IP stack. */ -#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) /* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP * task. This setting is less important when the FreeRTOS Win32 simulator is used * as the Win32 simulator only stores a fixed amount of information on the task * stack. FreeRTOS includes optional stack overflow detection, see: * http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) - -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -extern UBaseType_t uxRand(); -#define ipconfigRAND32() uxRand() +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK @@ -320,7 +317,9 @@ extern UBaseType_t uxRand(); /* Set ipconfigBUFFER_PADDING on 64-bit platforms */ #if INTPTR_MAX == INT64_MAX - #define ipconfigBUFFER_PADDING ( 14U ) + #define ipconfigBUFFER_PADDING ( 14U ) #endif /* INTPTR_MAX == INT64_MAX */ +#define ipconfigETHERNET_DRIVER_FILTERS_PACKETS ( 1 ) + #endif /* FREERTOS_IP_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/Makefile b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/Makefile index e3753275045..d02fc2e1975 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/Makefile +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/Makefile @@ -66,6 +66,9 @@ LDFLAGS += $(shell pkg-config --libs slirp) CPPFLAGS = $(INCLUDE_DIRS) -DBUILD_DIR=\"$(BUILD_DIR_ABS)\" +DEFINES := -DHEAP3 +CPPFLAGS += $(DEFINES) + ifndef TRACE_ON_ENTER TRACE_ON_ENTER = 1 endif diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/TCPEchoClient_SingleTasks.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/TCPEchoClient_SingleTasks.c index b354ad9bdc4..a0bf8952365 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/TCPEchoClient_SingleTasks.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/TCPEchoClient_SingleTasks.c @@ -158,17 +158,11 @@ #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) { - xEchoServerAddress.sin_address.ulIP_IPv4 = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, - configECHO_SERVER_ADDR1, - configECHO_SERVER_ADDR2, - configECHO_SERVER_ADDR3 ); + xEchoServerAddress.sin_address.ulIP_IPv4 = FreeRTOS_inet_addr( configECHO_SERVER_ADDR ); } #else { - xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, - configECHO_SERVER_ADDR1, - configECHO_SERVER_ADDR2, - configECHO_SERVER_ADDR3 ); + xEchoServerAddress.sin_addr = FreeRTOS_inet_addr( configECHO_SERVER_ADDR ); } #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ @@ -189,8 +183,8 @@ FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_WIN_PROPERTIES, ( void * ) &xWinProps, sizeof( xWinProps ) ); /* Connect to the echo server. */ - printf( "\nConnecting to echo server %d.%d.%d.%d:%d....\n", - configECHO_SERVER_ADDR0, configECHO_SERVER_ADDR1, configECHO_SERVER_ADDR2, configECHO_SERVER_ADDR3, echoECHO_PORT ); + printf( "\nConnecting to echo server %s:%d....\n", + configECHO_SERVER_ADDR, echoECHO_PORT ); ret = FreeRTOS_connect( xSocket, &xEchoServerAddress, sizeof( xEchoServerAddress ) ); diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main.c index 66efef40fd7..ebaa23fd831 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main.c @@ -83,12 +83,6 @@ void vApplicationIdleHook( void ); void vApplicationStackOverflowHook( TaskHandle_t pxTask, char * pcTaskName ); void vApplicationTickHook( void ); -void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, - StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ); -void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, - StackType_t ** ppxTimerTaskStackBuffer, - uint32_t * pulTimerTaskStackSize ); /* * Writes trace data to a disk file when the trace recording is stopped. @@ -322,58 +316,6 @@ static void prvSaveTraceFile( void ) } /*-----------------------------------------------------------*/ -/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an - * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is - * used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, - StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ) -{ -/* If the buffers to be provided to the Idle task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xIdleTaskTCB; - static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - * state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - * Note that, as the array is necessarily of type StackType_t, - * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} -/*-----------------------------------------------------------*/ - -/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the - * application must provide an implementation of vApplicationGetTimerTaskMemory() - * to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, - StackType_t ** ppxTimerTaskStackBuffer, - uint32_t * pulTimerTaskStackSize ) -{ -/* If the buffers to be provided to the Timer task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xTimerTaskTCB; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - * task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - * Note that, as the array is necessarily of type StackType_t, - * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} - static uint32_t ulEntryTime = 0U; void vTraceTimerReset( void ) @@ -390,3 +332,5 @@ uint32_t uiTraceTimerGetValue( void ) { return( xTaskGetTickCount() - ulEntryTime ); } + +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c index 085f2950958..09ce8784f47 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c @@ -135,6 +135,7 @@ static UBaseType_t ulNextRand; void main_tcp_echo_client_tasks( void ) { + BaseType_t xResult; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -157,8 +158,6 @@ void main_tcp_echo_client_tasks( void ) /* Initialise the network interface.*/ FreeRTOS_debug_printf( ( "FreeRTOS_IPInit\r\n" ) ); - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) extern NetworkInterface_t * pxLibslirp_FillInterfaceDescriptor( BaseType_t xEMACIndex, NetworkInterface_t * pxInterface ); @@ -173,12 +172,14 @@ void main_tcp_echo_client_tasks( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - FreeRTOS_IPInit_Multi(); + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xResult = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xResult == pdTRUE ); + /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\n" ) ); vTaskStartScheduler(); @@ -251,7 +252,7 @@ void main_tcp_echo_client_tasks( void ) } else { - FreeRTOS_printf( "Application idle hook network down\n" ); + FreeRTOS_printf( ( "Application idle hook network down\n" ) ); } } /*-----------------------------------------------------------*/ @@ -288,6 +289,7 @@ static void prvMiscInitialisation( void ) ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 1 ] ); ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 2 ] ); ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 3 ] ); + FreeRTOS_debug_printf( ( "Random numbers: %08X %08X %08X %08X\n", ulRandomNumbers[ 0 ], ulRandomNumbers[ 1 ], diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h index 371b5f8dc1a..4636f4fd3ca 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h @@ -57,11 +57,8 @@ extern void vAssertCalled( void ); #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 0 #define configMAX_PRIORITIES ( 10 ) -#define configTIMER_QUEUE_LENGTH 20 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 3 ) #define configUSE_COUNTING_SEMAPHORES 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1 -#define configNUM_TX_DESCRIPTORS 15 /* Set the following definitions to 1 to include the API function, or zero * to exclude the API function. */ @@ -74,7 +71,7 @@ extern void vAssertCalled( void ); #define INCLUDE_vTaskDelete 0 #define INCLUDE_vTaskCleanUpResources 0 #define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelayUntil 0 #define INCLUDE_vTaskDelay 1 @@ -89,7 +86,6 @@ extern void vAssertCalled( void ); /* networking definitions */ #define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 2 ) #define ipconfigUSE_NETWORK_EVENT_HOOK 1 -/*#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME pdMS_TO_TICKS(5000) */ #define configNETWORK_INTERFACE_TO_USE 1L /* The address of an echo server that will be used by the two demo echo client @@ -97,10 +93,22 @@ extern void vAssertCalled( void ); * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/UDP_Echo_Clients.html */ +/* When the user uses User Mode Networking, the QEMU virtual machine + * automatically starts up an internal DHCP server on an internal + * network address in the subnet 10.0.2.0/24. This DHCP server allocates IPs to + * Guest OSes in the subnet 10.0.2.0/24 starting from 10.0.2.15. The QEMU VM + * also sets up 10.0.2.2 as the "gateway" IP address. Connecting to a port on + * this "gateway" IP address 10.0.2.2 from inside the guest connects to that + * port on the host machine. For example, connecting to the "gateway" IP address + * 10.0.2.2 on port 7 from inside the guest will connect to the host machine on + * port 7. See the following links for more details: + * https://wiki.qemu.org/Documentation/Networking + * http://bsdwiki.reedmedia.net/wiki/networking_qemu_virtual_bsd_systems.html */ + #define configECHO_SERVER_ADDR0 10 -#define configECHO_SERVER_ADDR1 136 -#define configECHO_SERVER_ADDR2 206 -#define configECHO_SERVER_ADDR3 133 +#define configECHO_SERVER_ADDR1 0 +#define configECHO_SERVER_ADDR2 2 +#define configECHO_SERVER_ADDR3 2 /* Default MAC address configuration. The demo creates a virtual network * connection that uses this MAC address by accessing the raw Ethernet/WiFi data @@ -115,16 +123,16 @@ extern void vAssertCalled( void ); #define configMAC_ADDR4 0x34 #define configMAC_ADDR5 0xAD -/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or - * ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +/* Default IP address configuration. Used if ipconfigUSE_DHCP is set to 0, or + * ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be contacted. */ #define configIP_ADDR0 10 #define configIP_ADDR1 211 #define configIP_ADDR2 55 #define configIP_ADDR3 5 -/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to - * 0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +/* Default gateway IP address configuration. Used if ipconfigUSE_DHCP is set to + * 0, or ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be contacted. */ #define configGATEWAY_ADDR0 10 #define configGATEWAY_ADDR1 211 @@ -132,16 +140,16 @@ extern void vAssertCalled( void ); #define configGATEWAY_ADDR3 1 /* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and - * 208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set - * to 1 but a DNS server cannot be contacted.*/ + * 208.67.220.220. Used if ipconfigUSE_DHCP is set to 0, or ipconfigUSE_DHCP is set + * to 1 but a DHCP server cannot be contacted.*/ #define configDNS_SERVER_ADDR0 127 #define configDNS_SERVER_ADDR1 0 #define configDNS_SERVER_ADDR2 0 #define configDNS_SERVER_ADDR3 53 -/* Default netmask configuration. Used in ipconfigUSE_DNS is set to 0, or - * ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +/* Default netmask configuration. Used if ipconfigUSE_DHCP is set to 0, or + * ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be contacted. */ #define configNET_MASK0 255 #define configNET_MASK1 255 #define configNET_MASK2 255 diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSIPConfig.h index 08550f8ec50..539dcc18037 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSIPConfig.h @@ -79,26 +79,26 @@ extern void vLoggingPrintf( const char * pcFormatString, /* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ -#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN /* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software * stack repeating the checksum calculations. */ -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 /* Several API's will block until the result is known, or the action has been * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be * set per socket, using setsockopt(). If not set, the times below will be * used as defaults. */ -#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) -#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) /* Include support for LLMNR: Link-local Multicast Name Resolution * (non-Microsoft) */ -#define ipconfigUSE_LLMNR ( 1 ) +#define ipconfigUSE_LLMNR ( 1 ) /* Include support for NBNS: NetBIOS Name Service (Microsoft) */ -#define ipconfigUSE_NBNS ( 1 ) +#define ipconfigUSE_NBNS ( 1 ) /* Include support for DNS caching. For TCP, having a small DNS cache is very * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low @@ -106,10 +106,10 @@ extern void vLoggingPrintf( const char * pcFormatString, * socket has been destroyed, the result will be stored into the cache. The next * call to FreeRTOS_gethostbyname() will return immediately, without even creating * a socket. */ -#define ipconfigUSE_DNS_CACHE ( 1 ) -#define ipconfigDNS_CACHE_NAME_LENGTH ( 16 ) -#define ipconfigDNS_CACHE_ENTRIES ( 4 ) -#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) +#define ipconfigUSE_DNS_CACHE ( 1 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 16 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) /* The IP stack executes it its own task (although any application task can make * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY @@ -120,22 +120,14 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to * the priority assigned to the task executing the IP stack relative to the * priority assigned to tasks that use the IP stack. */ -#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) /* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP * task. This setting is less important when the FreeRTOS Win32 simulator is used * as the Win32 simulator only stores a fixed amount of information on the task * stack. FreeRTOS includes optional stack overflow detection, see: * http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) - -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -extern UBaseType_t uxRand(); -#define ipconfigRAND32() uxRand() +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK @@ -165,7 +157,7 @@ extern UBaseType_t uxRand(); * set to 1 if a valid configuration cannot be obtained from a DHCP server for any * reason. The static configuration used is that passed into the stack by the * FreeRTOS_IPInit() function call. */ -#define ipconfigUSE_DHCP 0 +#define ipconfigUSE_DHCP 1 /* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at * increasing time intervals until either a reply is received from a DHCP server @@ -248,11 +240,10 @@ extern UBaseType_t uxRand(); #define ipconfigUSE_TCP_WIN ( 1 ) /* The MTU is the maximum number of bytes the payload of a network frame can - * contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a - * lower value can save RAM, depending on the buffer management scheme used. If - * ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must - * be divisible by 8. */ -#define ipconfigNETWORK_MTU 1200U + * contain. Setting this to a number lower than that of the network you are + * connecting to is likely to cause dropped packets. Do not set this parameter + * lower than 1500 unless you fully understand the consequences. */ +#define ipconfigNETWORK_MTU 1500U /* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used * through the FreeRTOS_gethostbyname() API function. */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile index fdfe7c74103..eb248d9a51a 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile @@ -1,4 +1,5 @@ CC = arm-none-eabi-gcc +SIZE = arm-none-eabi-size BIN := freertos_tcp_mps2_demo.axf BUILD_DIR := build @@ -29,7 +30,6 @@ INCLUDE_DIRS += -I$(KERNEL_DIR)/include SOURCE_FILES += $(KERNEL_DIR)/tasks.c SOURCE_FILES += $(KERNEL_DIR)/list.c SOURCE_FILES += $(KERNEL_DIR)/queue.c -SOURCE_FILES += $(KERNEL_DIR)/timers.c SOURCE_FILES += $(KERNEL_DIR)/event_groups.c # FreeRTOS Kernel ARM Cortex-M3 Port @@ -51,30 +51,33 @@ SOURCE_FILES += ${FREERTOS_TCP}/source/portable/BufferManagement/BufferAllocatio SOURCE_FILES += ${FREERTOS_TCP}/source/portable/NetworkInterface/MPS2_AN385/NetworkInterface.c SOURCE_FILES += ${FREERTOS_TCP}/source/portable/NetworkInterface/MPS2_AN385/ether_lan9118/smsc9220_eth_drv.c -DEFINES := -DQEMU_SOC_MPS2 -DHEAP3 - -LDFLAGS = -T mps2_m3.ld -specs=nano.specs --specs=rdimon.specs -lc -lrdimon -LDFLAGS += -Xlinker -Map=${BUILD_DIR}/output.map - -CFLAGS += -nostartfiles -mthumb -mcpu=cortex-m3 -Wno-error=implicit-function-declaration -CFLAGS += -Wno-builtin-declaration-mismatch -Werror +DEFINES := -DHEAP3 +CPPFLAGS += $(DEFINES) +CFLAGS += -mthumb -mcpu=cortex-m3 ifeq ($(DEBUG), 1) - CFLAGS += -ggdb3 -Og + CFLAGS += -g3 -Og -ffunction-sections -fdata-sections else - CFLAGS += -O3 + CFLAGS += -Os -ffunction-sections -fdata-sections endif - CFLAGS += -fstrict-aliasing -Wstrict-aliasing -Wno-error=address-of-packed-member +CFLAGS += -MMD +CFLAGS += -Wall -Wextra -Wshadow +#CFLAGS += -Wpedantic -fanalyzer +#CFLAGS += -flto +CFLAGS += $(INCLUDE_DIRS) -OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) +LDFLAGS = -T mps2_m3.ld +LDFLAGS += -Xlinker -Map=${BUILD_DIR}/output.map +LDFLAGS += -Xlinker --gc-sections +LDFLAGS += -nostartfiles -specs=nano.specs -specs=nosys.specs -specs=rdimon.specs -CPPFLAGS += $(DEFINES) -CFLAGS += $(INCLUDE_DIRS) +OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) .PHONY: clean $(BUILD_DIR)/$(BIN) : $(OBJ_FILES) - $(CC) -ffunction-sections -fdata-sections $(CFLAGS) $(LDFLAGS) $+ -o $(@) + $(CC) $(CFLAGS) $(LDFLAGS) $+ -o $(@) + $(SIZE) $(@) %.d: %.c @set -e; rm -f $@; \ @@ -87,7 +90,7 @@ INCLUDES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.d) ${BUILD_DIR}/%.o : %.c Makefile -mkdir -p $(@D) - $(CC) $(CPPFLAGS) $(CFLAGS) -MMD -c $< -o $@ + $(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@ clean: -rm -rf build diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme.md b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme.md index 2954fb78fbf..33fb4d60268 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme.md +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme.md @@ -3,370 +3,6 @@ This FreeRTOS+TCP example demonstrates a TCP Echo Client which sends echo requests to an Echo Server and then receives the echo reply. The Echo Client runs on the MPS2 Cortex-M3 AN385 platform emulated using QEMU. -## Setup Description -The demo requires 2 components - -1. Echo Client - The demo in this repository. -1. Echo Server - An external echo server. - -We need a Virtual Machine (VM) running Linux OS to run this demo. Echo Client -runs in the Virtual Machine (VM) and Echo Server runs on the host machine. -``` -+--------------------------------------------------------+ -| Host Machine | -| OS - Any | -| Runs - Echo Server | -| +--------------------------+ | -| | Virtual Machine (VM) | | -| | OS - Linux | | -| | Runs - Echo Client | | -| | | | -| +----------------+ | +----------------+ | | -| | | | | | | | -| | | | | | | | -| | Echo Server | <-------> | Echo Client | | | -| | | | | | | | -| | | | | | | | -| | | | | | | | -| +----------------+ | +----------------+ | | -| | | | -| +--------------------------+ | -+--------------------------------------------------------+ -``` - -## Setting up VM -1. Install a Virtual Machine software on your machine. On Windows you can use -[Oracle VirtualBox](https://www.virtualbox.org/) and on Mac you can use -[Parallels](https://www.parallels.com/products/desktop/). -2. Launch a Linux VM. We tested using Ubuntu 22.04. -3. Install the following tools in the VM: - * [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads). - * [qemu-arm-system](https://www.qemu.org/download). - * Make (Version 4.3): - ``` - sudo apt install make - ``` - * ipcalc: - ``` - sudo apt install ipcalc - ``` - * brctl: - ``` - sudo apt install bridge-utils - ``` -4. Clone the source code in the VM: - ```shell - git clone https://github.com/FreeRTOS/FreeRTOS.git --recurse-submodules --depth 1 - ``` - -## Launch Echo Server -Launch Echo Server on the host machine. -### Host OS is Linux -* Install `netcat`: - ``` - sudo apt install netcat - ``` -* Start an Echo Server on port 7: - ```shell - sudo nc -l 7 - ``` - -### Host OS is Windows -* Install [Npcap/Nmap](https://nmap.org/download.html#windows). -* Start an Echo Server on port 7: - ```shell - ncat -l 7 - ``` - -### Host OS is Mac -* Install `netcat`: - ```shell - brew install netcat - ``` -* Start an Echo Server on port 7: - ```shell - nc -l -p 7 - ``` - -## Enable Networking in QEMU -The Echo Client in this demo runs in QEMU inside the VM. We need to enable -networking in QEMU to enable the Echo Client to be able to reach the Echo -Server. Do the following steps in the VM: - - -1. Run the `ifconfig` command to find the VM's network interface details: -``` -enp0s3: flags=4163 mtu 9001 - inet 192.168.1.81 netmask 255.255.255.0 broadcast 192.168.15.255 - inet6 fe80::89c:55ff:fe3d:18ad prefixlen 64 scopeid 0x20 - ether 0a:9c:55:3d:18:ad txqueuelen 1000 (Ethernet) - RX packets 15001255 bytes 11443805826 (11.4 GB) - RX errors 0 dropped 0 overruns 0 frame 0 - TX packets 9248218 bytes 2080385000 (2.0 GB) - TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 - -``` - -2. Define a shell variable `VM_NETWORK_INTERFACE` and set its value to the -name of the network interface of the VM. For example, in the above output -of the `ifconfig` command, name of the the network interface is `enp0s3`: -```shell -export VM_NETWORK_INTERFACE=enp0s3 -``` - -3. Define a shell variable `VM_IP_ADDRESS` and set its value to the IP address -of the VM. For example, in the above output of the `ifconfig` command, IP -address of the VM is `192.168.1.81`: -```shell -export VM_IP_ADDRESS=192.168.1.81 -``` - -4. Define a shell variable `VM_NETMASK` and set its value to the netmask of -the VM. For example, in the above output of the `ifconfig` command, netmask -of the VM is `255.255.255.0`: -```shell -export VM_NETMASK=255.255.255.0 -``` - -5. Calculate the CIDR of the VM from the netmask: -```shell -$ ipcalc -b 1.1.1.1 $VM_NETMASK | grep Netmask -Netmask: 255.255.255.0 = 24 -``` -CIDR is `24` in the above output. - -6. Define a shell variable `VM_CIDR` and set its value to the CIDR of the VM -found in the above step. -```shell -export VM_CIDR=24 -``` - -7. Find the Default Gateway for the VM: -```shell -$ ip route show -default via 192.168.1.254 dev enp0s3 proto dhcp src 192.168.1.81 metric 100 -``` -Default Gateway is `192.168.1.254` in the above output. - -8. Define a shell variable `VM_DEFAULT_GATEWAY` and set its value to the -Default Gateway of the VM found in the above step. -```shell -export VM_DEFAULT_GATEWAY=192.168.1.254 -``` - -9. Find the DNS Server of the VM: -```shell -$ grep "nameserver" /etc/resolv.conf -nameserver 192.168.1.254 -``` - -10. Define a shell variable `VM_DNS_SERVER` and set its value to the -DNS Server of the host machine found in the above step. -```shell -export VM_DNS_SERVER=192.168.1.254 -``` - -11. Pick an IP address for the QEMU which is in the same network as the VM. -This IP address must not be in-use by any other machine on the same network. -Define a shell variable `QEMU_IP_ADDRESS` and set its value to the -picked IP Address. For example, run the following command if you picked -`192.168.1.80`: -```shell -export QEMU_IP_ADDRESS=192.168.1.80 -``` - -12. Pick a MAC address for the QEMU. Define a shell variable `QEMU_MAC_ADDRESS` -and set its value to the picked MAC Address. For example, run the following -command if you picked `52:54:00:12:34:AD`: -```shell -export QEMU_MAC_ADDRESS=52:54:00:12:34:AD -``` - -13. Define a shell variable `ECHO_SERVER_IP_ADDRESS` and set its value to the -IP address of the Echo Server which is running on the host. For example, -run the following command if the IP address of the Echo Server is -`192.168.1.204`: -```shell -export ECHO_SERVER_IP_ADDRESS=192.168.1.204 -``` - -14. Turn off firewall on the VM. -On Ubuntu run: -```shell -sudo ufw disable -sudo ufw status -``` -On RedHat/Fedora system run: -```shell -sudo systemctl status firewalld -sudo systemctl stop firewalld -``` - -15. Create virtual bridge (virbr0) and virtual NIC (virbr0-nic) to enable -networking in QEMU. -```shell -sudo ip link add virbr0 type bridge -sudo ip tuntap add dev virbr0-nic mode tap - -sudo ip addr add $VM_IP_ADDRESS/$VM_CIDR dev virbr0 - -sudo brctl addif virbr0 $VM_NETWORK_INTERFACE -sudo brctl addif virbr0 virbr0-nic - -sudo ip link set virbr0 up -sudo ip link set virbr0-nic up - -sudo ip route add default via $VM_DEFAULT_GATEWAY dev virbr0 -``` - -The following diagram shows the setup: -``` -+-------------------------------------------------------------------------+ -| Virtual Machine (VM) | -| | -| +-------------------------+ | VM NIC (enp0s3) -| | | Virtual NIC (virbr0-nic) +--+ -| | QEMU +--+ | | -| | | | +--------------+ | | -| | | +--------->| virbr0 | ---------->| +--------> Internet -| | | | +--------------+ | | -| | +--+ Virtual Bridge | | -| | | +--+ -| +-------------------------+ | -| | -| | -+-------------------------------------------------------------------------+ -``` - -## Build and Run -Do the following steps in the VM where you cloned the code: - -1. Set `configIP_ADDR0`-`configIP_ADDR3` in `FreeRTOSConfig.h` to the value -of `QEMU_IP_ADDRESS`: -```shell -echo $QEMU_IP_ADDRESS -``` -```c -#define configIP_ADDR0 192 -#define configIP_ADDR1 168 -#define configIP_ADDR2 1 -#define configIP_ADDR3 80 -``` - -2. Set `configNET_MASK0`-`configNET_MASK3` in `FreeRTOSConfig.h` to the value -of `VM_NETMASK`: -```shell -echo $VM_NETMASK -``` -```c -#define configNET_MASK0 255 -#define configNET_MASK1 255 -#define configNET_MASK2 255 -#define configNET_MASK3 0 -``` - -3. Set `configGATEWAY_ADDR0`-`configGATEWAY_ADDR3` in `FreeRTOSConfig.h` to -the value of `VM_DEFAULT_GATEWAY`: -```shell -echo $VM_DEFAULT_GATEWAY -``` -```c -#define configGATEWAY_ADDR0 192 -#define configGATEWAY_ADDR1 168 -#define configGATEWAY_ADDR2 1 -#define configGATEWAY_ADDR3 254 -``` - -4. Set `configDNS_SERVER_ADDR0`-`configDNS_SERVER_ADDR3` in `FreeRTOSConfig.h` -to the value of `VM_DNS_SERVER`: -```shell -echo $VM_DNS_SERVER -``` -```c -#define configDNS_SERVER_ADDR0 192 -#define configDNS_SERVER_ADDR1 168 -#define configDNS_SERVER_ADDR2 1 -#define configDNS_SERVER_ADDR3 254 -``` - -5. Set `configMAC_ADDR0`-`configMAC_ADDR5` in `FreeRTOSConfig.h` to the value -of `QEMU_MAC_ADDRESS`: -```shell -echo $QEMU_MAC_ADDRESS -``` -```c -#define configMAC_ADDR0 0x52 -#define configMAC_ADDR1 0x54 -#define configMAC_ADDR2 0x00 -#define configMAC_ADDR3 0x12 -#define configMAC_ADDR4 0x34 -#define configMAC_ADDR5 0xAD -``` - -6. Set `configECHO_SERVER_ADDR0`-`configECHO_SERVER_ADDR3` in `FreeRTOSConfig.h` -to the value of `ECHO_SERVER_IP_ADDRESS`: -```shell -echo $ECHO_SERVER_IP_ADDRESS -``` -```c -#define configECHO_SERVER_ADDR0 192 -#define configECHO_SERVER_ADDR1 168 -#define configECHO_SERVER_ADDR2 1 -#define configECHO_SERVER_ADDR3 204 -``` - -7. Build: -```shell -make -``` - -8. Run: -```shell -sudo qemu-system-arm -machine mps2-an385 -cpu cortex-m3 \ - -kernel ./build/freertos_tcp_mps2_demo.axf \ - -netdev tap,id=mynet0,ifname=virbr0-nic,script=no \ - -net nic,macaddr=$QEMU_MAC_ADDRESS,model=lan9118,netdev=mynet0 \ - -object filter-dump,id=tap_dump,netdev=mynet0,file=/tmp/qemu_tap_dump\ - -display gtk -m 16M -nographic -serial stdio \ - -monitor null -semihosting -semihosting-config enable=on,target=native -``` - -9. You should see that following output on the terminal of the Echo Server (which -is running `sudo nc -l 7` or `netcat -l 7` depending on your OS): -``` -0FGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=> ? -@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=>? -@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=>? -@ABCDEFGHIJKLM -``` - -## Debug -1. Build with debugging symbols: -``` -make DEBUG=1 -``` - -2. Start QEMU in the paused state waiting for GDB connection: -```shell -sudo qemu-system-arm -machine mps2-an385 -cpu cortex-m3 -s -S \ - -kernel ./build/freertos_tcp_mps2_demo.axf \ - -netdev tap,id=mynet0,ifname=virbr0-nic,script=no \ - -net nic,macaddr=$QEMU_MAC_ADDRESS,model=lan9118,netdev=mynet0 \ - -object filter-dump,id=tap_dump,netdev=mynet0,file=/tmp/qemu_tap_dump\ - -display gtk -m 16M -nographic -serial stdio \ - -monitor null -semihosting -semihosting-config enable=on,target=native -``` - -3. Run GDB: -```shell -$ arm-none-eabi-gdb -q ./build/freertos_tcp_mps2_demo.axf - -(gdb) target remote :1234 -(gdb) break main -(gdb) c -``` - -4. The above QEMU command creates a network packet dump in the file -`/tmp/qemu_tap_dump` which you can examine using `tcpdump` or WireShark: -```shell -sudo tcpdump -r /tmp/qemu_tap_dump | less -``` +The demo is being run using the following configurations: +1. [ User Networking (SLIRP) ](Readme_UserNetworking.md) +2. [ Tap Networking ](Readme_TapNetworking.md) \ No newline at end of file diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme_TapNetworking.md b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme_TapNetworking.md new file mode 100644 index 00000000000..fea183bdc3d --- /dev/null +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme_TapNetworking.md @@ -0,0 +1,380 @@ +# TCP Echo Client Demo for MPS2 Cortex-M3 AN385 emulated using QEMU with TAP Networking + +## Setup Description +The demo requires 2 components - +1. Echo Client - The demo in this repository. +1. Echo Server - An external echo server. + +We need a Virtual Machine (VM) running Linux OS to run this demo. Echo Client +runs in the Virtual Machine (VM) and Echo Server runs on the host machine. +``` ++--------------------------------------------------------+ +| Host Machine | +| OS - Any | +| Runs - Echo Server | +| +--------------------------+ | +| | Virtual Machine (VM) | | +| | OS - Linux | | +| | Runs - Echo Client | | +| | | | +| +----------------+ | +----------------+ | | +| | | | | | | | +| | | | | | | | +| | Echo Server | <-------> | Echo Client | | | +| | | | | | | | +| | | | | | | | +| | | | | | | | +| +----------------+ | +----------------+ | | +| | | | +| +--------------------------+ | ++--------------------------------------------------------+ +``` + +## Setting up VM +1. Install a Virtual Machine software on your machine. On Windows you can use +[Oracle VirtualBox](https://www.virtualbox.org/) and on Mac you can use +[Parallels](https://www.parallels.com/products/desktop/). +2. Launch a Linux VM. We tested using Ubuntu 22.04. +3. Install the following tools in the VM: + * [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads). + * [qemu-arm-system](https://www.qemu.org/download). + * Make (Version 4.3): + ``` + sudo apt install make + ``` + * ipcalc: + ``` + sudo apt install ipcalc + ``` + * brctl: + ``` + sudo apt install bridge-utils + ``` +4. Clone the source code in the VM: + ```shell + git clone https://github.com/FreeRTOS/FreeRTOS.git --recurse-submodules --depth 1 + ``` + +## Launch Echo Server +Launch Echo Server on the host machine. +### Host OS is Linux +* Install `netcat`: + ``` + sudo apt install netcat + ``` +* Start an Echo Server on port 7: + ```shell + sudo nc -l 7 + ``` + +### Host OS is Windows +* Install [Npcap/Nmap](https://nmap.org/download.html#windows). +* Start an Echo Server on port 7: + ```shell + ncat -l 7 + ``` + +### Host OS is Mac +* Install `netcat`: + ```shell + brew install netcat + ``` +* Start an Echo Server on port 7: + ```shell + nc -l -p 7 + ``` + +## Enable Tap Networking in QEMU + +The Tap Networking backend makes use of a tap networking device in the host. It offers very good performance and can be configured to create virtually any type of network topology. + +The Echo Client in this demo runs in QEMU inside the VM. We need to enable +tap networking in QEMU to enable the Echo Client to be able to reach the Echo +Server. Do the following steps in the VM: + + +1. Run the `ifconfig` command to find the VM's network interface details: +``` +enp0s3: flags=4163 mtu 9001 + inet 192.168.1.81 netmask 255.255.255.0 broadcast 192.168.15.255 + inet6 fe80::89c:55ff:fe3d:18ad prefixlen 64 scopeid 0x20 + ether 0a:9c:55:3d:18:ad txqueuelen 1000 (Ethernet) + RX packets 15001255 bytes 11443805826 (11.4 GB) + RX errors 0 dropped 0 overruns 0 frame 0 + TX packets 9248218 bytes 2080385000 (2.0 GB) + TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 + +``` + +2. Define a shell variable `VM_NETWORK_INTERFACE` and set its value to the +name of the network interface of the VM. For example, in the above output +of the `ifconfig` command, name of the the network interface is `enp0s3`: +```shell +export VM_NETWORK_INTERFACE=enp0s3 +``` + +3. Define a shell variable `VM_IP_ADDRESS` and set its value to the IP address +of the VM. For example, in the above output of the `ifconfig` command, IP +address of the VM is `192.168.1.81`: +```shell +export VM_IP_ADDRESS=192.168.1.81 +``` + +4. Define a shell variable `VM_NETMASK` and set its value to the netmask of +the VM. For example, in the above output of the `ifconfig` command, netmask +of the VM is `255.255.255.0`: +```shell +export VM_NETMASK=255.255.255.0 +``` + +5. Calculate the CIDR of the VM from the netmask: +```shell +$ ipcalc -b 1.1.1.1 $VM_NETMASK | grep Netmask +Netmask: 255.255.255.0 = 24 +``` +CIDR is `24` in the above output. + +6. Define a shell variable `VM_CIDR` and set its value to the CIDR of the VM +found in the above step. +```shell +export VM_CIDR=24 +``` + +7. Find the Default Gateway for the VM: +```shell +$ ip route show +default via 192.168.1.254 dev enp0s3 proto dhcp src 192.168.1.81 metric 100 +``` +Default Gateway is `192.168.1.254` in the above output. + +8. Define a shell variable `VM_DEFAULT_GATEWAY` and set its value to the +Default Gateway of the VM found in the above step. +```shell +export VM_DEFAULT_GATEWAY=192.168.1.254 +``` + +9. Find the DNS Server of the VM: +```shell +$ grep "nameserver" /etc/resolv.conf +nameserver 192.168.1.254 +``` + +10. Define a shell variable `VM_DNS_SERVER` and set its value to the +DNS Server of the host machine found in the above step. +```shell +export VM_DNS_SERVER=192.168.1.254 +``` + +11. Pick an IP address for the QEMU which is in the same network as the VM. +This IP address must not be in-use by any other machine on the same network. +Define a shell variable `QEMU_IP_ADDRESS` and set its value to the +picked IP Address. For example, run the following command if you picked +`192.168.1.80`: +```shell +export QEMU_IP_ADDRESS=192.168.1.80 +``` + +12. Pick a MAC address for the QEMU. Define a shell variable `QEMU_MAC_ADDRESS` +and set its value to the picked MAC Address. For example, run the following +command if you picked `52:54:00:12:34:AD`: +```shell +export QEMU_MAC_ADDRESS=52:54:00:12:34:AD +``` + +13. Define a shell variable `ECHO_SERVER_IP_ADDRESS` and set its value to the +IP address of the Echo Server which is running on the host. For example, +run the following command if the IP address of the Echo Server is +`192.168.1.204`: +```shell +export ECHO_SERVER_IP_ADDRESS=192.168.1.204 +``` + +14. Turn off firewall on the VM. +On Ubuntu run: +```shell +sudo ufw disable +sudo ufw status +``` +On RedHat/Fedora system run: +```shell +sudo systemctl status firewalld +sudo systemctl stop firewalld +``` + +15. Create virtual bridge (virbr0) and virtual NIC (virbr0-nic) to enable +networking in QEMU. +```shell +sudo ip link add virbr0 type bridge +sudo ip tuntap add dev virbr0-nic mode tap + +sudo ip addr add $VM_IP_ADDRESS/$VM_CIDR dev virbr0 + +sudo brctl addif virbr0 $VM_NETWORK_INTERFACE +sudo brctl addif virbr0 virbr0-nic + +sudo ip link set virbr0 up +sudo ip link set virbr0-nic up + +sudo ip route add default via $VM_DEFAULT_GATEWAY dev virbr0 +``` + +The following diagram shows the setup: +``` ++-------------------------------------------------------------------------+ +| Virtual Machine (VM) | +| | +| +-------------------------+ | VM NIC (enp0s3) +| | | Virtual NIC (virbr0-nic) +--+ +| | QEMU +--+ | | +| | | | +--------------+ | | +| | | +--------->| virbr0 | ---------->| +--------> Internet +| | | | +--------------+ | | +| | +--+ Virtual Bridge | | +| | | +--+ +| +-------------------------+ | +| | +| | ++-------------------------------------------------------------------------+ +``` + +## Build and Run +Do the following steps in the VM where you cloned the code: + +1. Set `configIP_ADDR0`-`configIP_ADDR3` in `FreeRTOSConfig.h` to the value +of `QEMU_IP_ADDRESS`: +```shell +echo $QEMU_IP_ADDRESS +``` +```c +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 1 +#define configIP_ADDR3 80 +``` + +2. Set `configNET_MASK0`-`configNET_MASK3` in `FreeRTOSConfig.h` to the value +of `VM_NETMASK`: +```shell +echo $VM_NETMASK +``` +```c +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 +``` + +3. Set `configGATEWAY_ADDR0`-`configGATEWAY_ADDR3` in `FreeRTOSConfig.h` to +the value of `VM_DEFAULT_GATEWAY`: +```shell +echo $VM_DEFAULT_GATEWAY +``` +```c +#define configGATEWAY_ADDR0 192 +#define configGATEWAY_ADDR1 168 +#define configGATEWAY_ADDR2 1 +#define configGATEWAY_ADDR3 254 +``` + +4. Set `configDNS_SERVER_ADDR0`-`configDNS_SERVER_ADDR3` in `FreeRTOSConfig.h` +to the value of `VM_DNS_SERVER`: +```shell +echo $VM_DNS_SERVER +``` +```c +#define configDNS_SERVER_ADDR0 192 +#define configDNS_SERVER_ADDR1 168 +#define configDNS_SERVER_ADDR2 1 +#define configDNS_SERVER_ADDR3 254 +``` + +5. Set `configMAC_ADDR0`-`configMAC_ADDR5` in `FreeRTOSConfig.h` to the value +of `QEMU_MAC_ADDRESS`: +```shell +echo $QEMU_MAC_ADDRESS +``` +```c +#define configMAC_ADDR0 0x52 +#define configMAC_ADDR1 0x54 +#define configMAC_ADDR2 0x00 +#define configMAC_ADDR3 0x12 +#define configMAC_ADDR4 0x34 +#define configMAC_ADDR5 0xAD +``` + +6. Set `configECHO_SERVER_ADDR0`-`configECHO_SERVER_ADDR3` in `FreeRTOSConfig.h` +to the value of `ECHO_SERVER_IP_ADDRESS`: +```shell +echo $ECHO_SERVER_IP_ADDRESS +``` +```c +#define configECHO_SERVER_ADDR0 192 +#define configECHO_SERVER_ADDR1 168 +#define configECHO_SERVER_ADDR2 1 +#define configECHO_SERVER_ADDR3 204 +``` + +7. The echo server is assumed to be on port 7, which is the standard echo +protocol port. You can change the port to any other listening port (e.g. 3682 ). +Set `echoECHO_PORT` to the value of this port. + +```c +#define echoECHO_PORT ( 7 ) +``` + +8. Build: +```shell +make +``` + +9. Run: +```shell +sudo qemu-system-arm -machine mps2-an385 -cpu cortex-m3 \ + -kernel ./build/freertos_tcp_mps2_demo.axf \ + -netdev tap,id=mynet0,ifname=virbr0-nic,script=no \ + -net nic,macaddr=$QEMU_MAC_ADDRESS,model=lan9118,netdev=mynet0 \ + -object filter-dump,id=tap_dump,netdev=mynet0,file=/tmp/qemu_tap_dump\ + -display gtk -m 16M -nographic -serial stdio \ + -monitor null -semihosting -semihosting-config enable=on,target=native +``` + +10. You should see that following output on the terminal of the Echo Server (which +is running `sudo nc -l 7` or `netcat -l 7` depending on your OS): +``` +0FGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=> ? +@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=>? +@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=>? +@ABCDEFGHIJKLM +``` + +## Debug +1. Build with debugging symbols: +``` +make DEBUG=1 +``` + +2. Start QEMU in the paused state waiting for GDB connection: +```shell +sudo qemu-system-arm -machine mps2-an385 -cpu cortex-m3 -s -S \ + -kernel ./build/freertos_tcp_mps2_demo.axf \ + -netdev tap,id=mynet0,ifname=virbr0-nic,script=no \ + -net nic,macaddr=$QEMU_MAC_ADDRESS,model=lan9118,netdev=mynet0 \ + -object filter-dump,id=tap_dump,netdev=mynet0,file=/tmp/qemu_tap_dump\ + -display gtk -m 16M -nographic -serial stdio \ + -monitor null -semihosting -semihosting-config enable=on,target=native +``` + +3. Run GDB: +```shell +$ arm-none-eabi-gdb -q ./build/freertos_tcp_mps2_demo.axf + +(gdb) target remote :1234 +(gdb) break main +(gdb) c +``` + +4. The above QEMU command creates a network packet dump in the file +`/tmp/qemu_tap_dump` which you can examine using `tcpdump` or WireShark: +```shell +sudo tcpdump -r /tmp/qemu_tap_dump | less +``` diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme_UserNetworking.md b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme_UserNetworking.md new file mode 100644 index 00000000000..ae3e5312ed8 --- /dev/null +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Readme_UserNetworking.md @@ -0,0 +1,152 @@ +# TCP Echo Client Demo for MPS2 Cortex-M3 AN385 emulated using QEMU with User Mode Networking + +## Setup Description +The demo requires 2 components - +1. Echo Client - The demo in this repository. +1. Echo Server - An echo server. + +``` ++--------------------------------------------------------+ +| Host Machine | +| OS - Any | +| Runs - Echo Server | +| +--------------------------+ | +| | | | +| | QEMU | | +| | Runs - Echo Client | | +| | | | +| +----------------+ | +----------------+ | | +| | | | | | | | +| | | | | | | | +| | Echo Server | <-------> | Echo Client | | | +| | | | | | | | +| | | | | | | | +| | | | | | | | +| +----------------+ | +----------------+ | | +| | | | +| +--------------------------+ | ++--------------------------------------------------------+ +``` + +## PreRequisites + +1. Install the following tools in the Host Machine: + * [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads). + * [qemu-arm-system](https://www.qemu.org/download). + * Make (Version 4.3): + ``` + sudo apt install make + ``` +2. Clone the source code: + ``` + git clone https://github.com/FreeRTOS/FreeRTOS.git --recurse-submodules --depth 1 + ``` + +## Launch Echo Server +Launch Echo Server on the host machine. + +### Host OS is Linux +* Install `netcat`: + ``` + sudo apt install netcat + ``` +* Start an Echo Server on port 7: + ```shell + sudo nc -l 7 + ``` + +### Host OS is Windows +* Install [Npcap/Nmap](https://nmap.org/download.html#windows). +* Start an Echo Server on port 7: + ```shell + ncat -l 7 + ``` + +### Host OS is Mac +* Install `netcat`: + ```shell + brew install netcat + ``` +* Start an Echo Server on port 7: + ```shell + nc -l -p 7 + ``` + +## Enable User Mode Networking in QEMU + +The User Mode Networking is implemented using *slirp*, which provides a full +TCP/IP stack within QEMU and uses it to implement a virtual NAT network. It does +not require Administrator privileges. + +User Mode Networking has the following limitations: + + - The performance is not very good because of the overhead involved.. + - ICMP does not work out of the box i.e. you cannot use ping within the guest. + Linux hosts require one time setup by root to make ICMP work within the + guest. + - The guest is not directly accessible from the host or the external network. + + +## Build and Run +Do the following steps on the host machine: + +1. The echo server is assumed to be on port 7, which is the standard echo +protocol port. You can change the port to any other listening port (e.g. 3682 ). +Set `echoECHO_PORT` to the value of this port. + +```c +#define echoECHO_PORT ( 7 ) +``` + +2. Build: +```shell + make +``` + +3. Run: +```shell + sudo qemu-system-arm -machine mps2-an385 -cpu cortex-m3 \ + -kernel ./build/freertos_tcp_mps2_demo.axf \ + -monitor null -semihosting -semihosting-config enable=on,target=native -serial stdio -nographic \ + -netdev user,id=mynet0, -net nic,model=lan9118,netdev=mynet0 + +``` + +6. You should see that following output on the terminal of the Echo Server (which +is running `sudo nc -l 7` or `netcat -l 7` or `nc -l -p 7` depending on your OS): +``` +0FGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=> ? +@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=>? +@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~0123456789:;<=>? +@ABCDEFGHIJKLM +``` + +## Debug +1. Build with debugging symbols: +``` + make DEBUG=1 +``` + +2. Start QEMU in the paused state waiting for GDB connection: +```shell + sudo qemu-system-arm -machine mps2-an385 -cpu cortex-m3 -s -S \ + -kernel ./build/freertos_tcp_mps2_demo.axf \ + -monitor null -semihosting -semihosting-config enable=on,target=native -serial stdio -nographic \ + -netdev user,id=mynet0, -net nic,model=lan9118,netdev=mynet0 \ + -object filter-dump,id=tap_dump,netdev=mynet0,file=/tmp/qemu_tap_dump +``` + +3. Run GDB: +```shell +sudo arm-none-eabi-gdb -q ./build/freertos_tcp_mps2_demo.axf + +(gdb) target remote :1234 +(gdb) break main +(gdb) c +``` + +4. The above QEMU command creates a network packet dump in the file +`/tmp/qemu_tap_dump` which you can examine using `tcpdump` or WireShark: +```shell +sudo tcpdump -r /tmp/qemu_tap_dump | less +``` diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c index 968e044e36e..477ba4c1c07 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c @@ -110,9 +110,6 @@ { BaseType_t x; - /* Set Ethernet interrupt priority to configMAC_INTERRUPT_PRIORITY. */ - NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); - /* Create the echo client tasks. */ for( x = 0; x < echoNUM_ECHO_CLIENTS; x++ ) { @@ -209,10 +206,10 @@ lStringLength = prvCreateTxData( pcTransmittedString, echoBUFFER_SIZES ); /* Add in some unique text at the front of the string. */ - sprintf( pcTransmittedString, "TxRx message number %u", ulTxCount ); + sprintf( pcTransmittedString, "TxRx message number %lu", ulTxCount ); ulTxCount++; - printf( "sending data to the echo server size %d original %d\n", + printf( "sending data to the echo server size %ld original %d\n", lStringLength, echoBUFFER_SIZES ); /* Send the string to the socket. */ @@ -220,7 +217,7 @@ ( void * ) pcTransmittedString, /* The data being sent. */ lStringLength, /* The length of the data being sent. */ 0 ); /* No flags. */ - printf( "FreeRTOS_send returned...transmitted %d\n", + printf( "FreeRTOS_send returned...transmitted %ld\n", lTransmitted ); if( lTransmitted < 0 ) @@ -401,15 +398,24 @@ #if ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) eDHCPCallbackAnswer_t xApplicationDHCPHook( eDHCPCallbackPhase_t eDHCPPhase, uint32_t ulIPAddress ) + { + ( void ) eDHCPPhase; + ( void ) ulIPAddress; + + return eDHCPContinue; + } #else /* ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) */ eDHCPCallbackAnswer_t xApplicationDHCPHook_Multi( eDHCPCallbackPhase_t eDHCPPhase, struct xNetworkEndPoint * pxEndPoint, IP_Address_t * pxIPAddress ) + { + ( void ) eDHCPPhase; + ( void ) pxEndPoint; + ( void ) pxIPAddress; + + return eDHCPContinue; + } #endif /* ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) */ - { - /* Provide a stub for this function. */ - return eDHCPContinue; - } #endif /* if ( ipconfigUSE_DHCP_HOOK != 0 )*/ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c index cb17a6bf47c..ec5f5650c85 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c @@ -40,9 +40,7 @@ void main_tcp_echo_client_tasks( void ); void vApplicationIdleHook( void ); void vApplicationTickHook( void ); -extern void initialise_monitor_handles( void ); - -int main() +int main( void ) { main_tcp_echo_client_tasks(); return 0; @@ -84,8 +82,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, void vApplicationIdleHook( void ) { - volatile size_t xFreeHeapSpace; - /* This is just a trivial example of an idle hook. It is called on each * cycle of the idle task. It must *NOT* attempt to block. In this case the * idle task just queries the amount of FreeRTOS heap that remains. See the diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c index 2c6ab1d853c..dd964506011 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c @@ -35,7 +35,6 @@ #include #include - /* FreeRTOS includes. */ #include #include "task.h" @@ -44,6 +43,7 @@ #include "FreeRTOS_IP.h" #include "FreeRTOS_Sockets.h" #include "TCPEchoClient_SingleTasks.h" +#include "CMSIS/CMSDK_CM3.h" /* Echo client task parameters */ #define mainECHO_CLIENT_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) /* Not used in the linux port. */ @@ -140,6 +140,7 @@ static UBaseType_t ulNextRand; void main_tcp_echo_client_tasks( void ) { + BaseType_t xReturn; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -162,6 +163,9 @@ void main_tcp_echo_client_tasks( void ) /* Initialise the network interface.*/ FreeRTOS_debug_printf( ( "FreeRTOS_IPInit\r\n" ) ); + /* Set Ethernet interrupt priority to configMAC_INTERRUPT_PRIORITY. */ + NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); + #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) /* Initialise the interface descriptor for WinPCap. */ extern NetworkInterface_t * pxMPS2_FillInterfaceDescriptor( BaseType_t xEMACIndex, @@ -177,14 +181,13 @@ void main_tcp_echo_client_tasks( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - - FreeRTOS_IPInit_Multi(); + xReturn = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xReturn = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xReturn == pdTRUE ); /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\n" ) ); @@ -221,6 +224,10 @@ BaseType_t xTasksAlreadyCreated = pdFALSE; uint32_t ulDNSServerAddress; char cBuffer[ 16 ]; + #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) + ( void ) pxEndPoint; + #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + /* If the network has just come up...*/ if( eNetworkEvent == eNetworkUp ) { @@ -332,6 +339,10 @@ static void prvMiscInitialisation( void ) { BaseType_t xReturn; + #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) + ( void ) pxEndPoint; + #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + /* Determine if a name lookup is for this node. Two names are given * to this node: that returned by pcApplicationHostnameHook() and that set * by mainDEVICE_NICK_NAME. */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld index 13b1a3d79f0..97089f3c4aa 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld @@ -128,7 +128,7 @@ SECTIONS _heap_top = .; . = . + _Min_Stack_Size; . = ALIGN(8); - } >RAM + } >RAM /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c index 3dcec37f443..f1495d6e6a7 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c @@ -28,15 +28,14 @@ #include #include #include -#include "CMSIS/CMSDK_CM3.h" -#include "CMSIS/core_cm3.h" extern void vPortSVCHandler( void ); extern void xPortPendSVHandler( void ); extern void xPortSysTickHandler( void ); -extern void uart_init(); -extern int main(); +extern void uart_init( void ); +extern int main( void ); +void _start( void ); void __attribute__( ( weak ) ) EthernetISR( void ); extern uint32_t _estack, _sidata, _sdata, _edata, _sbss, _ebss; @@ -63,7 +62,6 @@ void Reset_Handler( void ) } /* jump to board initialisation */ - void _start( void ); _start(); } @@ -96,6 +94,16 @@ void prvGetRegistersFromStack( uint32_t * pulFaultStackAddress ) for( ; ; ) { } + + /* Remove the warning about unused variables. */ + ( void ) r0; + ( void ) r1; + ( void ) r2; + ( void ) r3; + ( void ) r12; + ( void ) lr; + ( void ) pc; + ( void ) psr; } static void Default_Handler( void ) __attribute__( ( naked ) ); @@ -103,18 +111,18 @@ void Default_Handler( void ) { __asm volatile ( - "Default_Handler: \n" - " ldr r3, NVIC_INT_CTRL_CONST \n" + "Default_Handler:\n" + " ldr r3, =0xe000ed04\n" " ldr r2, [r3, #0]\n" " uxtb r2, r2\n" "Infinite_Loop:\n" " b Infinite_Loop\n" ".size Default_Handler, .-Default_Handler\n" - ".align 4\n" - "NVIC_INT_CTRL_CONST: .word 0xe000ed04\n" + ".ltorg\n" ); } -static void HardFault_Handler( void ) __attribute__( ( naked ) ); + +static void Default_Handler2( void ) __attribute__( ( naked ) ); void Default_Handler2( void ) { __asm volatile @@ -124,9 +132,9 @@ void Default_Handler2( void ) " mrseq r0, msp \n" " mrsne r0, psp \n" " ldr r1, [r0, #24] \n" - " ldr r2, handler2_address_const \n" + " ldr r2, =prvGetRegistersFromStack \n" " bx r2 \n" - " handler2_address_const: .word prvGetRegistersFromStack \n" + " .ltorg \n" ); } @@ -158,7 +166,7 @@ void Default_Handler6( void ) } } -const uint32_t * isr_vector[] __attribute__( ( section( ".isr_vector" ) ) ) = +const uint32_t * const isr_vector[] __attribute__( ( section( ".isr_vector" ) ) ) = { ( uint32_t * ) &_estack, ( uint32_t * ) &Reset_Handler, /* Reset -15 */ @@ -195,7 +203,7 @@ const uint32_t * isr_vector[] __attribute__( ( section( ".isr_vector" ) ) ) = void _start( void ) { uart_init(); - main( 0, 0 ); + main(); exit( 0 ); } @@ -211,5 +219,8 @@ __attribute__( ( naked ) ) void exit( int status ) "movs r0, #0x18\n" /* SYS_EXIT */ "bkpt 0xab\n" "end: b end\n" + ".ltorg" ); + + ( void ) status; } diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c index bfa97f3b8e8..6e5425db004 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c @@ -38,24 +38,21 @@ typedef struct UART_t volatile uint32_t BAUDDIV; } UART_t; -#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) +#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) #define UART_DR( baseaddr ) ( *( unsigned int * ) ( baseaddr ) ) -#define UART_STATE_TXFULL ( 1 << 0 ) -#define UART_CTRL_TX_EN ( 1 << 0 ) -#define UART_CTRL_RX_EN ( 1 << 1 ) +#define UART_CTRL_TX_EN ( 1 << 0 ) extern unsigned long _heap_bottom; extern unsigned long _heap_top; -extern unsigned long g_ulBase; -static void * heap_end = 0; +static char * heap_end = ( char * ) &_heap_bottom; /** * @brief initializes the UART emulated hardware */ -void uart_init() +void uart_init( void ) { UART0_ADDR->BAUDDIV = 16; UART0_ADDR->CTRL = UART_CTRL_TX_EN; @@ -68,6 +65,7 @@ void uart_init() */ int _fstat( int file ) { + ( void ) file; return 0; } @@ -80,6 +78,9 @@ int _read( int file, char * buf, int len ) { + ( void ) file; + ( void ) buf; + ( void ) len; return -1; } @@ -97,6 +98,8 @@ int _write( int file, { int todo; + ( void ) file; + for( todo = 0; todo < len; todo++ ) { UART_DR( UART0_ADDR ) = *buf++; @@ -113,16 +116,9 @@ int _write( int file, */ void * _sbrk( int incr ) { - char * prev_heap_end; - - if( heap_end == 0 ) - { - heap_end = ( void * ) &_heap_bottom; - } - - prev_heap_end = heap_end; + void * prev_heap_end = heap_end; - if( ( heap_end + incr ) > ( void * ) &_heap_top ) + if( ( heap_end + incr ) > ( char * ) &_heap_top ) { return ( void * ) -1; } diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOSIPConfig.h index 230cbf31f9c..acf4df5c185 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOSIPConfig.h @@ -60,26 +60,26 @@ extern void vLoggingPrintf( const char * pcFormatString, /* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ -#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN /* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software * stack repeating the checksum calculations. */ -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 /* Several API's will block until the result is known, or the action has been * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be * set per socket, using setsockopt(). If not set, the times below will be * used as defaults. */ -#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) -#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) /* Include support for LLMNR: Link-local Multicast Name Resolution * (non-Microsoft) */ -#define ipconfigUSE_LLMNR ( 1 ) +#define ipconfigUSE_LLMNR ( 1 ) /* Include support for NBNS: NetBIOS Name Service (Microsoft) */ -#define ipconfigUSE_NBNS ( 1 ) +#define ipconfigUSE_NBNS ( 1 ) /* Include support for DNS caching. For TCP, having a small DNS cache is very * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low @@ -87,13 +87,13 @@ extern void vLoggingPrintf( const char * pcFormatString, * socket has been destroyed, the result will be stored into the cache. The next * call to FreeRTOS_gethostbyname() will return immediately, without even creating * a socket. */ -#define ipconfigUSE_DNS_CACHE ( 1 ) -#define ipconfigDNS_CACHE_NAME_LENGTH ( 33 ) -#define ipconfigDNS_CACHE_ENTRIES ( 4 ) -#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) +#define ipconfigUSE_DNS_CACHE ( 1 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 33 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) /* Let DNS wait for 3 seconds for an answer. */ -#define ipconfigDNS_RECEIVE_BLOCK_TIME_TICKS pdMS_TO_TICKS( 3000U ) +#define ipconfigDNS_RECEIVE_BLOCK_TIME_TICKS pdMS_TO_TICKS( 3000U ) /* The IP stack executes it its own task (although any application task can make * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY @@ -104,22 +104,14 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to * the priority assigned to the task executing the IP stack relative to the * priority assigned to tasks that use the IP stack. */ -#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) /* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP * task. This setting is less important when the FreeRTOS Win32 simulator is used * as the Win32 simulator only stores a fixed amount of information on the task * stack. FreeRTOS includes optional stack overflow detection, see: * http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) - -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -extern UBaseType_t uxRand(); -#define ipconfigRAND32() uxRand() +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK @@ -232,11 +224,10 @@ extern UBaseType_t uxRand(); #define ipconfigUSE_TCP_WIN ( 1 ) /* The MTU is the maximum number of bytes the payload of a network frame can - * contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a - * lower value can save RAM, depending on the buffer management scheme used. If - * ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must - * be divisible by 8. */ -#define ipconfigNETWORK_MTU 1200U + * contain. Setting this to a number lower than that of the network you are + * connecting to is likely to cause dropped packets. Do not set this parameter + * lower than 1500 unless you fully understand the consequences. */ +#define ipconfigNETWORK_MTU 1500U /* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used * through the FreeRTOS_gethostbyname() API function. */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOS_Plus_TCP_IPv6_Multi.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOS_Plus_TCP_IPv6_Multi.sln index b19a0270296..a6f57ced640 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOS_Plus_TCP_IPv6_Multi.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/FreeRTOS_Plus_TCP_IPv6_Multi.sln @@ -1,12 +1,10 @@ - -Microsoft Visual Studio Solution File, Format Version 11.00 -# Visual Studio 2010 +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 16 +VisualStudioVersion = 16.0.34114.132 +MinimumVisualStudioVersion = 10.0.40219.1 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" EndProject Global - GlobalSection(TestCaseManagementSettings) = postSolution - CategoryFile = FreeRTOS_Plus_TCP_IPv6_Multi.vsmdi - EndGlobalSection GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 Release|Win32 = Release|Win32 @@ -14,10 +12,15 @@ Global GlobalSection(ProjectConfigurationPlatforms) = postSolution {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {7EDFF311-AEF8-4C06-8B4E-1A254FB878EC} + EndGlobalSection + GlobalSection(TestCaseManagementSettings) = postSolution + CategoryFile = FreeRTOS_Plus_TCP_IPv6_Multi.vsmdi + EndGlobalSection EndGlobal diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/TCPEchoClient_SingleTasks.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/TCPEchoClient_SingleTasks.c index 7b0569cea14..0f9dcc90828 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/TCPEchoClient_SingleTasks.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/TCPEchoClient_SingleTasks.c @@ -70,6 +70,9 @@ /* The number of instances of the echo client task to create. */ #define echoNUM_ECHO_CLIENTS ( 1 ) +/* To enable the use of zero copy interface of the TCP sockets */ + #define USE_TCP_ZERO_COPY ( 0 ) + /*-----------------------------------------------------------*/ /* @@ -151,6 +154,68 @@ return xReturn; } +/*-----------------------------------------------------------*/ + + static BaseType_t vTCPCreateAndSendData( Socket_t xSocket, + char * pcTransmitBuffer, + volatile uint32_t * pulTxCount, + uint32_t ulBufferLength ) + { + BaseType_t lStringLength; + BaseType_t lTransmitted; + char * pcDstBuffer; + + #if USE_TCP_ZERO_COPY + BaseType_t xStreamBufferLength; + char * pcBuffer; + #endif /* USE_TCP_ZERO_COPY */ + + pcDstBuffer = pcTransmitBuffer; + + #if USE_TCP_ZERO_COPY + /* Get a direct pointer to the TX head of the circular transmit buffer */ + pcBuffer = ( char * ) FreeRTOS_get_tx_head( xSocket, &xStreamBufferLength ); + + /* Check if sufficient space is there in the stream buffer. If there + * isn't enough size use application provided buffer */ + if( xStreamBufferLength >= ulBufferLength ) + { + /* Use the TCP stream buffer to directly create the TX data */ + pcDstBuffer = pcBuffer; + } + #endif /* USE_TCP_ZERO_COPY */ + + lStringLength = prvCreateTxData( pcDstBuffer, ulBufferLength ); + + /* Add in some unique text at the front of the string. */ + sprintf( pcDstBuffer, "TxRx message number %u", ( unsigned ) *pulTxCount ); + ( *pulTxCount )++; + + #if USE_TCP_ZERO_COPY + /* Check to see if zero copy is used */ + if( pcDstBuffer != pcTransmitBuffer ) + { + /* Save a copy of the data in pcTransmitBuffer + * which can be used to verify the echoed back data */ + memcpy( pcTransmitBuffer, pcDstBuffer, lStringLength ); + + /* Set the buffer pointer as NULL to let the stack know + * that its a zero copy */ + pcDstBuffer = NULL; + } + #endif /* USE_TCP_ZERO_COPY */ + + /* Send the string to the socket. */ + lTransmitted = FreeRTOS_send( xSocket, /* The socket being sent to. */ + ( void * ) pcDstBuffer, /* The data being sent. */ + lStringLength, /* The length of the data being sent. */ + 0 ); /* No flags. */ + + configPRINTF( ( "FreeRTOS_send: %u/%u\n", ( unsigned ) lTransmitted, ( unsigned ) lStringLength ) ); + + return lTransmitted; + } + /*-----------------------------------------------------------*/ static void prvEchoClientTask( void * pvParameters ) @@ -161,7 +226,7 @@ const int32_t lMaxLoopCount = 1; volatile uint32_t ulTxCount = 0UL; BaseType_t xReceivedBytes, xReturned = 0, xInstance; - BaseType_t lTransmitted, lStringLength; + BaseType_t lTransmitted; char * pcTransmittedString, * pcReceivedString; WinProperties_t xWinProps; TickType_t xTimeOnEntering; @@ -252,19 +317,7 @@ /* Send a number of echo requests. */ for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ ) { - /* Create the string that is sent to the echo server. */ - lStringLength = prvCreateTxData( pcTransmittedString, echoBUFFER_SIZES ); - - /* Add in some unique text at the front of the string. */ - sprintf( pcTransmittedString, "TxRx message number %u", ( unsigned ) ulTxCount ); - ulTxCount++; - - /* Send the string to the socket. */ - lTransmitted = FreeRTOS_send( xSocket, /* The socket being sent to. */ - ( void * ) pcTransmittedString, /* The data being sent. */ - lStringLength, /* The length of the data being sent. */ - 0 ); /* No flags. */ - configPRINTF( ( "FreeRTOS_send: %u/%u\n", ( unsigned ) lTransmitted, ( unsigned ) lStringLength ) ); + lTransmitted = vTCPCreateAndSendData( xSocket, pcTransmittedString, &ulTxCount, echoBUFFER_SIZES ); if( xIsFatalError( lTransmitted ) ) { @@ -282,10 +335,27 @@ /* Receive data echoed back to the socket. */ while( xReceivedBytes < lTransmitted ) { - xReturned = FreeRTOS_recv( xSocket, /* The socket being received from. */ - &( pcReceivedString[ xReceivedBytes ] ), /* The buffer into which the received data will be written. */ - lStringLength - xReceivedBytes, /* The size of the buffer provided to receive the data. */ - 0 ); /* No flags. */ + #if USE_TCP_ZERO_COPY + uint8_t * pucZeroCopyRxBuffPtr = NULL; + xReturned = FreeRTOS_recv( xSocket, /* The socket being received from. */ + &pucZeroCopyRxBuffPtr, /* While using FREERTOS_ZERO_COPY flag, pvBuffer is taken as a double pointer which will be updated with pointer to TCP RX stream buffer. */ + ipconfigTCP_MSS, /* The size of the buffer provided to receive the data. */ + FREERTOS_ZERO_COPY ); /* Use FREERTOS_ZERO_COPY flag to enable zero copy. */ + + if( pucZeroCopyRxBuffPtr != NULL ) + { + memcpy( &( pcReceivedString[ xReceivedBytes ] ), pucZeroCopyRxBuffPtr, xReturned ); + + /* Release the memory that was previously obtained by calling FreeRTOS_recv() + * with the flag 'FREERTOS_ZERO_COPY' */ + FreeRTOS_ReleaseTCPPayloadBuffer( xSocket, pucZeroCopyRxBuffPtr, xReturned ); + } + #else /* if USE_TCP_ZERO_COPY */ + xReturned = FreeRTOS_recv( xSocket, /* The socket being received from. */ + &( pcReceivedString[ xReceivedBytes ] ), /* The buffer into which the received data will be written. */ + lTransmitted - xReceivedBytes, /* The size of the buffer provided to receive the data. */ + 0 ); /* No flags. */ + #endif /* USE_TCP_ZERO_COPY */ if( xIsFatalError( xReturned ) ) { diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/WIN32.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/WIN32.vcxproj index e0ef59a3b30..20657cfb905 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/WIN32.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/WIN32.vcxproj @@ -5,10 +5,6 @@ Debug Win32 - - Release - Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB} @@ -16,12 +12,6 @@ 10.0 - - Application - false - MultiByte - v142 - Application false @@ -31,11 +21,6 @@ - - - - - @@ -47,9 +32,6 @@ .\Debug\ .\Debug\ true - .\Release\ - .\Release\ - false AllRules.ruleset @@ -74,7 +56,7 @@ $(DEMO_COMMON_SOURCE_DIR)\logging\include; .; ..\common\Logging\windows - WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;ipconfigUSE_PCAP=1;_NO_CRT_STDIO_INLINE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;ipconfigUSE_PCAP=1;_NO_CRT_STDIO_INLINE;%(PreprocessorDefinitions) false EnableFastChecks MultiThreadedDLL @@ -112,46 +94,6 @@ $(DEMO_COMMON_SOURCE_DIR)\logging\include; .\Debug/WIN32.bsc - - - .\Release/WIN32.tlb - - - - - MaxSpeed - OnlyExplicitInline - _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - MultiThreaded - true - .\Release/WIN32.pch - .\Release/ - .\Release/ - .\Release/ - Level3 - true - - - NDEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Release/RTOSDemo.exe - true - .\Release/WIN32.pdb - Console - MachineX86 - - - - - - - true - .\Release/WIN32.bsc - - @@ -217,7 +159,6 @@ $(DEMO_COMMON_SOURCE_DIR)\logging\include; %(AdditionalIncludeDirectories) %(PreprocessorDefinitions) - %(PreprocessorDefinitions) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c index b2fe91edc1c..d236e819da5 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c @@ -189,6 +189,7 @@ NetworkInterface_t * pxWinPcap_FillInterfaceDescriptor( BaseType_t xEMACIndex, int main( void ) { + BaseType_t xReturn; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -314,7 +315,9 @@ int main( void ) } #endif /* ( mainNETWORK_UP_COUNT >= 3U ) */ - FreeRTOS_IPInit_Multi(); + xReturn = FreeRTOS_IPInit_Multi(); + + configASSERT( xReturn == pdTRUE ); /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\r\n" ) ); @@ -431,7 +434,6 @@ void vApplicationIPNetworkEventHook_Multi( eIPCallbackEvent_t eNetworkEvent, if( pxEndPoint->bits.bIPv6 == 0U ) { - *ipLOCAL_IP_ADDRESS_POINTER = pxEndPoint->ipv4_settings.ulIPAddress; configPRINTF( ( "IPv4 address = %xip\n", FreeRTOS_ntohl( pxEndPoint->ipv4_settings.ulIPAddress ) ) ); } @@ -464,15 +466,6 @@ UBaseType_t uxRand( void ) } /*-----------------------------------------------------------*/ -uint32_t uxRand32( void ) -{ - /* uxRand only returns 15 random bits. Call it 3 times. */ - uint32_t ul[ 3 ] = { uxRand(), uxRand(), uxRand() }; - uint32_t uxReturn = ul[ 0 ] | ( ul[ 1 ] << 15 ) | ( ul[ 2 ] << 30 ); - - return uxReturn; -} - static void prvSRand( UBaseType_t ulSeed ) { /* Utility function to seed the pseudo random number generator. */ @@ -483,6 +476,7 @@ static void prvSRand( UBaseType_t ulSeed ) static void prvMiscInitialisation( void ) { time_t xTimeNow; + uint32_t ulRandomNumbers[ 4 ]; uint32_t ulLoggingIPAddress; ulLoggingIPAddress = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, configECHO_SERVER_ADDR1, configECHO_SERVER_ADDR2, configECHO_SERVER_ADDR3 ); @@ -492,7 +486,16 @@ static void prvMiscInitialisation( void ) time( &xTimeNow ); FreeRTOS_debug_printf( ( "Seed for randomiser: %lu\r\n", xTimeNow ) ); prvSRand( ( uint32_t ) xTimeNow ); - FreeRTOS_debug_printf( ( "Random numbers: %08X %08X %08X %08X\r\n", ipconfigRAND32(), ipconfigRAND32(), ipconfigRAND32(), ipconfigRAND32() ) ); + + ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 0 ] ); + ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 1 ] ); + ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 2 ] ); + ( void ) xApplicationGetRandomNumber( &ulRandomNumbers[ 3 ] ); + FreeRTOS_debug_printf( ( "Random numbers: %08X %08X %08X %08X\n", + ulRandomNumbers[ 0 ], + ulRandomNumbers[ 1 ], + ulRandomNumbers[ 2 ], + ulRandomNumbers[ 3 ] ) ); } /*-----------------------------------------------------------*/ @@ -637,12 +640,16 @@ extern uint32_t ulApplicationGetNextSequenceNumber( uint32_t ulSourceAddress, uint32_t ulDestinationAddress, uint16_t usDestinationPort ) { + uint32_t ulRandomNumber; + ( void ) ulSourceAddress; ( void ) usSourcePort; ( void ) ulDestinationAddress; ( void ) usDestinationPort; - return uxRand32(); + ( void ) xApplicationGetRandomNumber( &ulRandomNumber ); + + return ulRandomNumber; } /*-----------------------------------------------------------*/ @@ -930,34 +937,41 @@ static void vDNSEvent( const char * pcName, static void dns_test( const char * pcHostName ) { - uint32_t ulID = uxRand32(); + uint32_t ulID; BaseType_t rc; - FreeRTOS_dnsclear(); - - struct freertos_addrinfo xHints; - struct freertos_addrinfo * pxResult = NULL; - - memset( &xHints, 0, sizeof xHints ); - xHints.ai_family = FREERTOS_AF_INET6; - - rc = FreeRTOS_getaddrinfo( pcHostName, NULL, &xHints, &pxResult ); - - FreeRTOS_printf( ( "Lookup '%s': %d\n", pcHostName, rc ) ); - - FreeRTOS_dnsclear(); - xDNSResult = -2; - rc = FreeRTOS_getaddrinfo_a( pcHostName, - NULL, - &xHints, - &pxResult, /* An allocated struct, containing the results. */ - vDNSEvent, - ( void * ) ulID, - pdMS_TO_TICKS( 1000U ) ); - vTaskDelay( pdMS_TO_TICKS( 1000U ) ); - rc = xDNSResult; - FreeRTOS_printf( ( "Lookup '%s': %d\n", pcHostName, rc ) ); - /* FreeRTOS_gethostbyname( pcHostName ); */ + if( xApplicationGetRandomNumber( &( ulID ) ) != pdFALSE ) + { + FreeRTOS_dnsclear(); + + struct freertos_addrinfo xHints; + struct freertos_addrinfo * pxResult = NULL; + + memset( &xHints, 0, sizeof xHints ); + xHints.ai_family = FREERTOS_AF_INET6; + + rc = FreeRTOS_getaddrinfo( pcHostName, NULL, &xHints, &pxResult ); + + FreeRTOS_printf( ( "Lookup '%s': %d\n", pcHostName, rc ) ); + + FreeRTOS_dnsclear(); + xDNSResult = -2; + rc = FreeRTOS_getaddrinfo_a( pcHostName, + NULL, + &xHints, + &pxResult, /* An allocated struct, containing the results. */ + vDNSEvent, + ( void * ) ulID, + pdMS_TO_TICKS( 1000U ) ); + vTaskDelay( pdMS_TO_TICKS( 1000U ) ); + rc = xDNSResult; + FreeRTOS_printf( ( "Lookup '%s': %d\n", pcHostName, rc ) ); + /* FreeRTOS_gethostbyname( pcHostName ); */ + } + else + { + FreeRTOS_printf( ( "dns_test: Failed to generate a random SearchID\n" ) ); + } } void showAddressInfo( struct freertos_addrinfo * pxAddrInfo ) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln index d34259b1824..e01e8554a5b 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS_Plus_TCP_Minimal", "FreeRTOS_Plus_TCP_Minimal.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS_Plus_TCP_Minimal", "FreeRTOS_Plus_TCP_Minimal.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Statically Linked Libraries", "Statically Linked Libraries", "{190A6643-3DE4-49DC-96AA-7867C5E0A835}" @@ -16,61 +15,25 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.vcxproj index ed848dc8379..9439a6db6a6 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - false @@ -132,75 +78,6 @@ xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" " xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\..\Source\Utilities\logging;DemoTasks\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - _CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\..\Source\Utilities\logging;DemoTasks\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - ipconfigUSE_LIBSLIRP;_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\ThirdParty\glib;..\..\ThirdParty\glib\build;..\..\ThirdParty\glib\build\glib;..\..\ThirdParty\glib\build\subprojects\pcre2-10.42;..\..\ThirdParty\glib\subprojects\proxy-libintl;..\..\ThirdParty\libslirp\src;.;..\..\Source\Utilities\logging;DemoTasks\include;%(AdditionalIncludeDirectories) - - - Console - true - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\..\Source\Utilities\logging;DemoTasks\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt index 0eb0f7392f4..1e3ac06aa2b 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt @@ -23,6 +23,10 @@ The TCP client example included in the minimal project is described on the following URL: http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html +The TCP server example included in the minimal project is described on the +following URL: +https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Server.html + A description of the FreeRTOS+TCP source code directory is provided on the following URL: http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Networking_Tutorial_Source_Code_Organisation.html diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c index 126e7477696..3d4e285f1d6 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c @@ -145,6 +145,7 @@ static UBaseType_t ulNextRand; int main( void ) { + BaseType_t xResult; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -185,14 +186,14 @@ int main( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - - FreeRTOS_IPInit_Multi(); + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xResult = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xResult == pdTRUE ); + /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\r\n" ) ); vTaskStartScheduler(); diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln index 25ad69485af..9edb2080547 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -16,61 +15,16 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {66422066-D458-449A-AE2A-0A44D4BDE94B}.Debug|Win32.ActiveCfg = Debug|Win32 {66422066-D458-449A-AE2A-0A44D4BDE94B}.Debug|Win32.Build.0 = Debug|Win32 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Debug|x64.ActiveCfg = Debug|x64 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Debug|x64.Build.0 = Debug|x64 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Debug|x86.ActiveCfg = Debug|Win32 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Debug|x86.Build.0 = Debug|Win32 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Release|Win32.ActiveCfg = Release|Win32 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Release|Win32.Build.0 = Release|Win32 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Release|x64.ActiveCfg = Release|x64 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Release|x64.Build.0 = Release|x64 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Release|x86.ActiveCfg = Release|Win32 - {66422066-D458-449A-AE2A-0A44D4BDE94B}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.vcxproj index a7d666b0d53..2920afce055 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/FreeRTOS_Plus_UDP_with_CLI.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,28 +28,10 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 @@ -95,53 +45,6 @@ true - - - Level3 - true - true - true - _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\DemoTasks\include;..\Common\WinPCap;..\..\Source\FreeRTOS-Plus-CLI;.;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\DemoTasks\include;..\Common\WinPCap;..\..\Source\FreeRTOS-Plus-CLI;.;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - .\DemoTasks\include;..\Common\WinPCap;..\..\Source\FreeRTOS-Plus-CLI;.;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/README_FIRST.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/README_FIRST.txt index c184f495b6d..2aa80827559 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/README_FIRST.txt +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/README_FIRST.txt @@ -1,11 +1,10 @@ This demo is documented on the following web page: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_CLI_Windows_Simulator.shtml +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_CLI_Windows_Simulator.html The FreeRTOS+UDP API is documented on the following web page: -http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.html Other information, including a FreeRTOS+UDP primer, a description of the directory structure, and a glossary of networking terminology, can be found in the FreeRTOS+UDP portal: http://www.FreeRTOS.org/udp - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c index 1f7ff80b924..1626361c4a4 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c @@ -130,6 +130,7 @@ static UBaseType_t ulNextRand; int main( void ) { + BaseType_t xResult; const uint32_t ulLongTime_ms = 250UL; /* Create a mutex that is used to guard against the console being accessed @@ -157,13 +158,15 @@ int main( void ) xEndPoints[ 0 ].bits.bWantDHCP = pdTRUE; } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - FreeRTOS_IPInit_Multi(); + + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xResult = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xResult == pdTRUE ); + /* Initialise the logging. */ uint32_t ulLoggingIPAddress; diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln index 3b53adff60b..dbb6f73cba8 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -16,88 +15,25 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug|Win32.ActiveCfg = Debug|Win32 {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug|Win32.Build.0 = Debug|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug|x64.ActiveCfg = Debug|x64 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug|x64.Build.0 = Debug|x64 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug|x86.ActiveCfg = Debug|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Debug|x86.Build.0 = Debug|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Release|Win32.ActiveCfg = Release|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Release|Win32.Build.0 = Release|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Release|x64.ActiveCfg = Release|x64 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Release|x64.Build.0 = Release|x64 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Release|x86.ActiveCfg = Release|Win32 - {C8144D60-5005-4111-841E-FA3529F84A8B}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL_Windows_Simulator.vcxproj b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL_Windows_Simulator.vcxproj index 30167b9a7b3..60fdd042087 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL_Windows_Simulator.vcxproj +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL_Windows_Simulator.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - true @@ -102,23 +48,11 @@ true - - false - - - true - - - true - - - false - Level3 true - WOLFSSL_USER_SETTINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;WOLFSSL_IGNORE_FILE_WARN + WIN32;WIN32_LEAN_AND_MEAN;WOLFSSL_USER_SETTINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;WOLFSSL_IGNORE_FILE_WARN true ..\..\ThirdParty\WolfSSL;.;%(AdditionalIncludeDirectories) @@ -147,72 +81,6 @@ xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" " xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - WOLFSSL_USER_SETTINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;WOLFSSL_IGNORE_FILE_WARN - true - ..\..\ThirdParty\WolfSSL;.;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - WOLFSSL_USER_SETTINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;WOLFSSL_IGNORE_FILE_WARN - true - ..\..\ThirdParty\WolfSSL;.;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - WOLFSSL_USER_SETTINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;WOLFSSL_IGNORE_FILE_WARN - true - ..\..\ThirdParty\WolfSSL;.;%(AdditionalIncludeDirectories) - - - Console - true - Bcrypt.lib;Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - WOLFSSL_USER_SETTINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;WOLFSSL_IGNORE_FILE_WARN - true - ..\..\ThirdParty\WolfSSL;.;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/ca-cert.pem b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/ca-cert.pem deleted file mode 100644 index a72435e0f85..00000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/ca-cert.pem +++ /dev/null @@ -1,93 +0,0 @@ -Certificate: - Data: - Version: 3 (0x2) - Serial Number: - 5e:ba:a4:f4:b1:f7:48:25:e3:5f:9b:da:a1:13:ed:d5:2b:03:67:15 - Signature Algorithm: sha256WithRSAEncryption - Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com - Validity - Not Before: Jun 19 13:23:41 2020 GMT - Not After : Mar 16 13:23:41 2023 GMT - Subject: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com - Subject Public Key Info: - Public Key Algorithm: rsaEncryption - RSA Public-Key: (2048 bit) - Modulus: - 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a: - f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac: - de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98: - 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77: - 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1: - 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3: - a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed: - a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95: - 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c: - 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db: - 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc: - 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98: - de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68: - cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2: - b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3: - 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98: - ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed: - 36:79 - Exponent: 65537 (0x10001) - X509v3 extensions: - X509v3 Subject Key Identifier: - 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 - X509v3 Authority Key Identifier: - keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 - DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com - serial:5E:BA:A4:F4:B1:F7:48:25:E3:5F:9B:DA:A1:13:ED:D5:2B:03:67:15 - - X509v3 Basic Constraints: - CA:TRUE - X509v3 Subject Alternative Name: - DNS:example.com, IP Address:127.0.0.1 - X509v3 Extended Key Usage: - TLS Web Server Authentication, TLS Web Client Authentication - Signature Algorithm: sha256WithRSAEncryption - b9:ed:94:3e:00:73:2d:a5:d1:04:b3:fb:dc:f0:b7:0d:3d:ad: - 96:74:4c:92:67:ad:6d:7c:e2:99:6a:33:ca:b2:0f:04:5a:a5: - 67:f8:e3:0b:3d:f5:d0:5b:1e:20:52:12:92:28:ea:31:a3:51: - 9e:8b:d2:39:e4:25:ea:61:61:41:16:2d:54:50:d3:fb:d0:34: - 00:10:f1:7b:bc:f0:08:a7:f5:27:5e:7e:40:9d:99:b0:d3:31: - 11:c3:9d:a9:51:a0:17:cf:83:2c:55:84:e0:d5:92:a0:05:3a: - 9f:b8:75:f8:1b:e5:f7:a4:6c:e9:aa:25:8b:19:93:46:1f:3f: - 33:af:47:29:cf:7b:8b:59:27:eb:d7:4f:cb:33:19:fa:5f:ee: - d8:13:e9:0c:07:ad:3b:c0:7f:10:d7:e4:ed:e8:db:16:e1:1f: - a4:7f:16:3c:bd:d7:11:f2:d4:3a:a9:9b:95:e1:39:51:99:eb: - 5b:65:46:ef:63:84:73:95:23:b8:bf:b5:f6:4d:12:71:f7:ff: - 33:aa:4a:8c:65:73:73:89:69:df:a6:dc:a4:91:ff:ae:c7:28: - 93:b5:1a:de:a9:8f:2b:30:85:83:8b:99:82:ca:b3:7c:11:10: - 88:9d:8e:6c:2c:f3:05:6f:cb:80:85:16:b7:ed:e4:68:fb:b6: - b6:31:8a:7d ------BEGIN CERTIFICATE----- -MIIE/zCCA+egAwIBAgIUXrqk9LH3SCXjX5vaoRPt1SsDZxUwDQYJKoZIhvcNAQEL -BQAwgZQxCzAJBgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdC -b3plbWFuMREwDwYDVQQKDAhTYXd0b290aDETMBEGA1UECwwKQ29uc3VsdGluZzEY -MBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdv -bGZzc2wuY29tMB4XDTIwMDYxOTEzMjM0MVoXDTIzMDMxNjEzMjM0MVowgZQxCzAJ -BgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREw -DwYDVQQKDAhTYXd0b290aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwP -d3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29t -MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAvwzKLRSyHoRCW804H0ry -TXUQ8bY1n9/KfQOY06zeA2buKvHYsH1uB1QLEJghTYDLEiDnzE/eRX3Jcncy6sqQ -u2lSEAMvqPOVxfGLYlYb72dvpBBBla0Km+OlwLDScHZQMFuo6AgsfO2nonqNOCkc -rMft8nyVsJWCfUlcOM13Je+9gHVTlDw9ymNbnxW10x0TLxnRPNt2Osy4fcnlwtfa -QG/YIdxzG0ItU5z+Gvx9q3o2P5jehHwFZ85qFDiHqfGMtWjLaH9xICv1oGP1Vi+j -JtK3b7FaF9c4mQj+k1hv/sMTSQgWC6dNZwBSMWcjTpjtUUUduQTZC+zYKLNLve02 -eQIDAQABo4IBRTCCAUEwHQYDVR0OBBYEFCeOZxF0wyYdP+0zY7Ok2B0w5ejVMIHU -BgNVHSMEgcwwgcmAFCeOZxF0wyYdP+0zY7Ok2B0w5ejVoYGapIGXMIGUMQswCQYD -VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G -A1UECgwIU2F3dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3 -dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbYIU -Xrqk9LH3SCXjX5vaoRPt1SsDZxUwDAYDVR0TBAUwAwEB/zAcBgNVHREEFTATggtl -eGFtcGxlLmNvbYcEfwAAATAdBgNVHSUEFjAUBggrBgEFBQcDAQYIKwYBBQUHAwIw -DQYJKoZIhvcNAQELBQADggEBALntlD4Acy2l0QSz+9zwtw09rZZ0TJJnrW184plq -M8qyDwRapWf44ws99dBbHiBSEpIo6jGjUZ6L0jnkJephYUEWLVRQ0/vQNAAQ8Xu8 -8Ain9SdefkCdmbDTMRHDnalRoBfPgyxVhODVkqAFOp+4dfgb5fekbOmqJYsZk0Yf -PzOvRynPe4tZJ+vXT8szGfpf7tgT6QwHrTvAfxDX5O3o2xbhH6R/Fjy91xHy1Dqp -m5XhOVGZ61tlRu9jhHOVI7i/tfZNEnH3/zOqSoxlc3OJad+m3KSR/67HKJO1Gt6p -jyswhYOLmYLKs3wREIidjmws8wVvy4CFFrft5Gj7trYxin0= ------END CERTIFICATE----- diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/READ_ME.url b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/readme.url similarity index 89% rename from FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/READ_ME.url rename to FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/readme.url index 967308be8da..b7378da335f 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/READ_ME.url +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/readme.url @@ -1,5 +1,5 @@ -[InternetShortcut] -URL=http://www.freertos.org/FreeRTOS-Plus/WolfSSL/FreeRTOS_WolfSSL_Example.shtml -IDList= [{000214A0-0000-0000-C000-000000000046}] Prop3=19,2 +[InternetShortcut] +IDList= +URL=http://www.freertos.org/FreeRTOS-Plus/WolfSSL/FreeRTOS_WolfSSL_Example.html diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-cert.pem b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-cert.pem deleted file mode 100644 index bd6715b7406..00000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-cert.pem +++ /dev/null @@ -1,185 +0,0 @@ -Certificate: - Data: - Version: 3 (0x2) - Serial Number: 1 (0x1) - Signature Algorithm: sha256WithRSAEncryption - Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com - Validity - Not Before: Jun 19 13:23:41 2020 GMT - Not After : Mar 16 13:23:41 2023 GMT - Subject: C = US, ST = Montana, L = Bozeman, O = wolfSSL, OU = Support, CN = www.wolfssl.com, emailAddress = info@wolfssl.com - Subject Public Key Info: - Public Key Algorithm: rsaEncryption - RSA Public-Key: (2048 bit) - Modulus: - 00:c0:95:08:e1:57:41:f2:71:6d:b7:d2:45:41:27: - 01:65:c6:45:ae:f2:bc:24:30:b8:95:ce:2f:4e:d6: - f6:1c:88:bc:7c:9f:fb:a8:67:7f:fe:5c:9c:51:75: - f7:8a:ca:07:e7:35:2f:8f:e1:bd:7b:c0:2f:7c:ab: - 64:a8:17:fc:ca:5d:7b:ba:e0:21:e5:72:2e:6f:2e: - 86:d8:95:73:da:ac:1b:53:b9:5f:3f:d7:19:0d:25: - 4f:e1:63:63:51:8b:0b:64:3f:ad:43:b8:a5:1c:5c: - 34:b3:ae:00:a0:63:c5:f6:7f:0b:59:68:78:73:a6: - 8c:18:a9:02:6d:af:c3:19:01:2e:b8:10:e3:c6:cc: - 40:b4:69:a3:46:33:69:87:6e:c4:bb:17:a6:f3:e8: - dd:ad:73:bc:7b:2f:21:b5:fd:66:51:0c:bd:54:b3: - e1:6d:5f:1c:bc:23:73:d1:09:03:89:14:d2:10:b9: - 64:c3:2a:d0:a1:96:4a:bc:e1:d4:1a:5b:c7:a0:c0: - c1:63:78:0f:44:37:30:32:96:80:32:23:95:a1:77: - ba:13:d2:97:73:e2:5d:25:c9:6a:0d:c3:39:60:a4: - b4:b0:69:42:42:09:e9:d8:08:bc:33:20:b3:58:22: - a7:aa:eb:c4:e1:e6:61:83:c5:d2:96:df:d9:d0:4f: - ad:d7 - Exponent: 65537 (0x10001) - X509v3 extensions: - X509v3 Subject Key Identifier: - B3:11:32:C9:92:98:84:E2:C9:F8:D0:3B:6E:03:42:CA:1F:0E:8E:3C - X509v3 Authority Key Identifier: - keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 - DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com - serial:5E:BA:A4:F4:B1:F7:48:25:E3:5F:9B:DA:A1:13:ED:D5:2B:03:67:15 - - X509v3 Basic Constraints: - CA:TRUE - X509v3 Subject Alternative Name: - DNS:example.com, IP Address:127.0.0.1 - X509v3 Extended Key Usage: - TLS Web Server Authentication, TLS Web Client Authentication - Signature Algorithm: sha256WithRSAEncryption - 35:91:e6:72:cc:0b:f1:47:8f:3d:e3:5d:52:2f:83:b8:b1:3b: - 6d:d6:ac:13:79:74:14:ff:07:8d:ee:74:77:64:ff:b8:83:1d: - 81:80:84:bb:38:fa:8f:f3:75:29:23:ce:e5:09:a8:13:85:14: - b6:6a:35:30:2c:1c:c4:0f:23:67:ea:ed:cb:91:c4:05:e3:ec: - 6b:be:11:bf:d9:9a:ab:93:17:9f:e4:9a:59:d4:e7:cc:ce:dc: - 83:10:f5:cd:de:d7:35:75:4b:aa:7a:7a:ba:02:a0:b0:b5:c1: - 8a:6b:b1:72:cf:64:59:4e:d3:a4:a1:6c:64:4b:14:cf:a3:d6: - 37:0a:e6:f9:5b:21:be:de:0c:c1:cf:43:e1:18:0b:19:13:6b: - 8e:3d:df:0f:a7:43:fb:35:67:4a:50:e8:09:46:34:bd:f4:ab: - 1a:8f:bd:4d:1c:6b:20:be:1c:8c:ca:66:98:ba:03:67:f2:1c: - 3c:1e:01:f0:4d:c6:85:82:6f:a9:49:f7:1b:7d:6b:db:76:84: - 73:bb:16:c5:6e:74:ab:7b:fb:1c:e9:91:bb:29:73:1c:de:27: - b4:67:3b:10:51:f4:17:eb:b8:38:a0:9a:eb:37:5b:76:8f:39: - 12:39:35:d1:ca:fe:c0:26:fb:73:50:1e:2d:b9:d2:ba:e5:4c: - 35:bd:ed:7b ------BEGIN CERTIFICATE----- -MIIE6DCCA9CgAwIBAgIBATANBgkqhkiG9w0BAQsFADCBlDELMAkGA1UEBhMCVVMx -EDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNh -d3Rvb3RoMRMwEQYDVQQLDApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNz -bC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wHhcNMjAwNjE5 -MTMyMzQxWhcNMjMwMzE2MTMyMzQxWjCBkDELMAkGA1UEBhMCVVMxEDAOBgNVBAgM -B01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xEDAOBgNVBAoMB3dvbGZTU0wxEDAO -BgNVBAsMB1N1cHBvcnQxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqG -SIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZIhvcNAQEBBQADggEP -ADCCAQoCggEBAMCVCOFXQfJxbbfSRUEnAWXGRa7yvCQwuJXOL07W9hyIvHyf+6hn -f/5cnFF194rKB+c1L4/hvXvAL3yrZKgX/Mpde7rgIeVyLm8uhtiVc9qsG1O5Xz/X -GQ0lT+FjY1GLC2Q/rUO4pRxcNLOuAKBjxfZ/C1loeHOmjBipAm2vwxkBLrgQ48bM -QLRpo0YzaYduxLsXpvPo3a1zvHsvIbX9ZlEMvVSz4W1fHLwjc9EJA4kU0hC5ZMMq -0KGWSrzh1Bpbx6DAwWN4D0Q3MDKWgDIjlaF3uhPSl3PiXSXJag3DOWCktLBpQkIJ -6dgIvDMgs1gip6rrxOHmYYPF0pbf2dBPrdcCAwEAAaOCAUUwggFBMB0GA1UdDgQW -BBSzETLJkpiE4sn40DtuA0LKHw6OPDCB1AYDVR0jBIHMMIHJgBQnjmcRdMMmHT/t -M2OzpNgdMOXo1aGBmqSBlzCBlDELMAkGA1UEBhMCVVMxEDAOBgNVBAgMB01vbnRh -bmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNhd3Rvb3RoMRMwEQYDVQQL -DApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG -9w0BCQEWEGluZm9Ad29sZnNzbC5jb22CFF66pPSx90gl41+b2qET7dUrA2cVMAwG -A1UdEwQFMAMBAf8wHAYDVR0RBBUwE4ILZXhhbXBsZS5jb22HBH8AAAEwHQYDVR0l -BBYwFAYIKwYBBQUHAwEGCCsGAQUFBwMCMA0GCSqGSIb3DQEBCwUAA4IBAQA1keZy -zAvxR489411SL4O4sTtt1qwTeXQU/weN7nR3ZP+4gx2BgIS7OPqP83UpI87lCagT -hRS2ajUwLBzEDyNn6u3LkcQF4+xrvhG/2Zqrkxef5JpZ1OfMztyDEPXN3tc1dUuq -enq6AqCwtcGKa7Fyz2RZTtOkoWxkSxTPo9Y3Cub5WyG+3gzBz0PhGAsZE2uOPd8P -p0P7NWdKUOgJRjS99Ksaj71NHGsgvhyMymaYugNn8hw8HgHwTcaFgm+pSfcbfWvb -doRzuxbFbnSre/sc6ZG7KXMc3ie0ZzsQUfQX67g4oJrrN1t2jzkSOTXRyv7AJvtz -UB4tudK65Uw1ve17 ------END CERTIFICATE----- -Certificate: - Data: - Version: 3 (0x2) - Serial Number: - 5e:ba:a4:f4:b1:f7:48:25:e3:5f:9b:da:a1:13:ed:d5:2b:03:67:15 - Signature Algorithm: sha256WithRSAEncryption - Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com - Validity - Not Before: Jun 19 13:23:41 2020 GMT - Not After : Mar 16 13:23:41 2023 GMT - Subject: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com - Subject Public Key Info: - Public Key Algorithm: rsaEncryption - RSA Public-Key: (2048 bit) - Modulus: - 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a: - f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac: - de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98: - 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77: - 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1: - 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3: - a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed: - a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95: - 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c: - 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db: - 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc: - 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98: - de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68: - cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2: - b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3: - 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98: - ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed: - 36:79 - Exponent: 65537 (0x10001) - X509v3 extensions: - X509v3 Subject Key Identifier: - 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 - X509v3 Authority Key Identifier: - keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 - DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com - serial:5E:BA:A4:F4:B1:F7:48:25:E3:5F:9B:DA:A1:13:ED:D5:2B:03:67:15 - - X509v3 Basic Constraints: - CA:TRUE - X509v3 Subject Alternative Name: - DNS:example.com, IP Address:127.0.0.1 - X509v3 Extended Key Usage: - TLS Web Server Authentication, TLS Web Client Authentication - Signature Algorithm: sha256WithRSAEncryption - b9:ed:94:3e:00:73:2d:a5:d1:04:b3:fb:dc:f0:b7:0d:3d:ad: - 96:74:4c:92:67:ad:6d:7c:e2:99:6a:33:ca:b2:0f:04:5a:a5: - 67:f8:e3:0b:3d:f5:d0:5b:1e:20:52:12:92:28:ea:31:a3:51: - 9e:8b:d2:39:e4:25:ea:61:61:41:16:2d:54:50:d3:fb:d0:34: - 00:10:f1:7b:bc:f0:08:a7:f5:27:5e:7e:40:9d:99:b0:d3:31: - 11:c3:9d:a9:51:a0:17:cf:83:2c:55:84:e0:d5:92:a0:05:3a: - 9f:b8:75:f8:1b:e5:f7:a4:6c:e9:aa:25:8b:19:93:46:1f:3f: - 33:af:47:29:cf:7b:8b:59:27:eb:d7:4f:cb:33:19:fa:5f:ee: - d8:13:e9:0c:07:ad:3b:c0:7f:10:d7:e4:ed:e8:db:16:e1:1f: - a4:7f:16:3c:bd:d7:11:f2:d4:3a:a9:9b:95:e1:39:51:99:eb: - 5b:65:46:ef:63:84:73:95:23:b8:bf:b5:f6:4d:12:71:f7:ff: - 33:aa:4a:8c:65:73:73:89:69:df:a6:dc:a4:91:ff:ae:c7:28: - 93:b5:1a:de:a9:8f:2b:30:85:83:8b:99:82:ca:b3:7c:11:10: - 88:9d:8e:6c:2c:f3:05:6f:cb:80:85:16:b7:ed:e4:68:fb:b6: - b6:31:8a:7d ------BEGIN CERTIFICATE----- -MIIE/zCCA+egAwIBAgIUXrqk9LH3SCXjX5vaoRPt1SsDZxUwDQYJKoZIhvcNAQEL -BQAwgZQxCzAJBgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdC -b3plbWFuMREwDwYDVQQKDAhTYXd0b290aDETMBEGA1UECwwKQ29uc3VsdGluZzEY -MBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdv -bGZzc2wuY29tMB4XDTIwMDYxOTEzMjM0MVoXDTIzMDMxNjEzMjM0MVowgZQxCzAJ -BgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREw -DwYDVQQKDAhTYXd0b290aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwP -d3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29t -MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAvwzKLRSyHoRCW804H0ry -TXUQ8bY1n9/KfQOY06zeA2buKvHYsH1uB1QLEJghTYDLEiDnzE/eRX3Jcncy6sqQ -u2lSEAMvqPOVxfGLYlYb72dvpBBBla0Km+OlwLDScHZQMFuo6AgsfO2nonqNOCkc -rMft8nyVsJWCfUlcOM13Je+9gHVTlDw9ymNbnxW10x0TLxnRPNt2Osy4fcnlwtfa -QG/YIdxzG0ItU5z+Gvx9q3o2P5jehHwFZ85qFDiHqfGMtWjLaH9xICv1oGP1Vi+j -JtK3b7FaF9c4mQj+k1hv/sMTSQgWC6dNZwBSMWcjTpjtUUUduQTZC+zYKLNLve02 -eQIDAQABo4IBRTCCAUEwHQYDVR0OBBYEFCeOZxF0wyYdP+0zY7Ok2B0w5ejVMIHU -BgNVHSMEgcwwgcmAFCeOZxF0wyYdP+0zY7Ok2B0w5ejVoYGapIGXMIGUMQswCQYD -VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G -A1UECgwIU2F3dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3 -dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbYIU -Xrqk9LH3SCXjX5vaoRPt1SsDZxUwDAYDVR0TBAUwAwEB/zAcBgNVHREEFTATggtl -eGFtcGxlLmNvbYcEfwAAATAdBgNVHSUEFjAUBggrBgEFBQcDAQYIKwYBBQUHAwIw -DQYJKoZIhvcNAQELBQADggEBALntlD4Acy2l0QSz+9zwtw09rZZ0TJJnrW184plq -M8qyDwRapWf44ws99dBbHiBSEpIo6jGjUZ6L0jnkJephYUEWLVRQ0/vQNAAQ8Xu8 -8Ain9SdefkCdmbDTMRHDnalRoBfPgyxVhODVkqAFOp+4dfgb5fekbOmqJYsZk0Yf -PzOvRynPe4tZJ+vXT8szGfpf7tgT6QwHrTvAfxDX5O3o2xbhH6R/Fjy91xHy1Dqp -m5XhOVGZ61tlRu9jhHOVI7i/tfZNEnH3/zOqSoxlc3OJad+m3KSR/67HKJO1Gt6p -jyswhYOLmYLKs3wREIidjmws8wVvy4CFFrft5Gj7trYxin0= ------END CERTIFICATE----- diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-key.pem b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-key.pem deleted file mode 100644 index d1627f4d4a7..00000000000 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-key.pem +++ /dev/null @@ -1,27 +0,0 @@ ------BEGIN RSA PRIVATE KEY----- -MIIEpQIBAAKCAQEAwJUI4VdB8nFtt9JFQScBZcZFrvK8JDC4lc4vTtb2HIi8fJ/7 -qGd//lycUXX3isoH5zUvj+G9e8AvfKtkqBf8yl17uuAh5XIuby6G2JVz2qwbU7lf -P9cZDSVP4WNjUYsLZD+tQ7ilHFw0s64AoGPF9n8LWWh4c6aMGKkCba/DGQEuuBDj -xsxAtGmjRjNph27Euxem8+jdrXO8ey8htf1mUQy9VLPhbV8cvCNz0QkDiRTSELlk -wyrQoZZKvOHUGlvHoMDBY3gPRDcwMpaAMiOVoXe6E9KXc+JdJclqDcM5YKS0sGlC -Qgnp2Ai8MyCzWCKnquvE4eZhg8XSlt/Z0E+t1wIDAQABAoIBAQCa0DQPUmIFUAHv -n+1kbsLE2hryhNeSEEiSxOlq64t1bMZ5OPLJckqGZFSVd8vDmp231B2kAMieTuTd -x7pnFsF0vKnWlI8rMBr77d8hBSPZSjm9mGtlmrjcxH3upkMVLj2+HSJgKnMw1T7Y -oqyGQy7E9WReP4l1DxHYUSVOn9iqo85gs+KK2X4b8GTKmlsFC1uqy+XjP24yIgXz -0PrvdFKB4l90073/MYNFdfpjepcu1rYZxpIm5CgGUFAOeC6peA0Ul7QS2DFAq6EB -QcIw+AdfFuRhd9Jg8p+N6PS662PeKpeB70xs5lU0USsoNPRTHMRYCj+7r7X3SoVD -LTzxWFiBAoGBAPIsVHY5I2PJEDK3k62vvhl1loFk5rW4iUJB0W3QHBv4G6xpyzY8 -ZH3c9Bm4w2CxV0hfUk9ZOlV/MsAZQ1A/rs5vF/MOn0DKTq0VO8l56cBZOHNwnAp8 -yTpIMqfYSXUKhcLC/RVz2pkJKmmanwpxv7AEpox6Wm9IWlQ7xrFTF9/nAoGBAMuT -3ncVXbdcXHzYkKmYLdZpDmOzo9ymzItqpKISjI57SCyySzfcBhh96v52odSh6T8N -zRtfr1+elltbD6F8r7ObkNtXczrtsCNErkFPHwdCEyNMy/r0FKTV9542fFufqDzB -hV900jkt/9CE3/uzIHoumxeu5roLrl9TpFLtG8SRAoGBAOyY2rvV/vlSSn0CVUlv -VW5SL4SjK7OGYrNU0mNS2uOIdqDvixWl0xgUcndex6MEH54ZYrUbG57D8rUy+UzB -qusMJn3UX0pRXKRFBnBEp1bA1CIUdp7YY1CJkNPiv4GVkjFBhzkaQwsYpVMfORpf -H0O8h2rfbtMiAP4imHBOGhkpAoGBAIpBVihRnl/Ungs7mKNU8mxW1KrpaTOFJAza -1AwtxL9PAmk4fNTm3Ezt1xYRwz4A58MmwFEC3rt1nG9WnHrzju/PisUr0toGakTJ -c/5umYf4W77xfOZltU9s8MnF/xbKixsX4lg9ojerAby/QM5TjI7t7+5ZneBj5nxe -9Y5L8TvBAoGATUX5QIzFW/QqGoq08hysa+kMVja3TnKW1eWK0uL/8fEYEz2GCbjY -dqfJHHFSlDBD4PF4dP1hG0wJzOZoKnGtHN9DvFbbpaS+NXCkXs9P/ABVmTo9I89n -WvUi+LUp0EQR6zUuRr79jhiyX6i/GTKh9dwD5nyaHwx8qbAOITc78bA= ------END RSA PRIVATE KEY----- diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/CoreHTTP_Mutual_Auth.vcxproj b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/CoreHTTP_Mutual_Auth.vcxproj index 29d2f954b7b..39f1f2d0762 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/CoreHTTP_Mutual_Auth.vcxproj +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/CoreHTTP_Mutual_Auth.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,15 +28,6 @@ - - - - - - - - - false @@ -77,62 +36,12 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/DemoTasks/MutualAuthHTTPExample.c b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/DemoTasks/MutualAuthHTTPExample.c index eb652c3b954..9bd1f33ae89 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/DemoTasks/MutualAuthHTTPExample.c +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/DemoTasks/MutualAuthHTTPExample.c @@ -200,6 +200,10 @@ static BaseType_t prvSendHttpRequest( const TransportInterface_t * pxTransportIn /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /* * @brief Create the task that demonstrates the HTTP API Demo over a * mutually-authenticated network connection with an HTTP server. diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/http_mutual_auth_demo.sln b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/http_mutual_auth_demo.sln index 1245a8b484a..9f504014cfd 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/http_mutual_auth_demo.sln +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Mutual_Auth/http_mutual_auth_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_Mutual_Auth", "CoreHTTP_Mutual_Auth.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_Mutual_Auth", "CoreHTTP_Mutual_Auth.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreHTTP", "..\..\..\VisualStudio_StaticProjects\coreHTTP\coreHTTP.vcxproj", "{EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/CoreHTTP_Plaintext.vcxproj b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/CoreHTTP_Plaintext.vcxproj index 3694c5f200b..e9ecc0813e6 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/CoreHTTP_Plaintext.vcxproj +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/CoreHTTP_Plaintext.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,15 +28,6 @@ - - - - - - - - - false @@ -77,62 +36,12 @@ Level3 true - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - _CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + _CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/DemoTasks/PlainTextHTTPExample.c b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/DemoTasks/PlainTextHTTPExample.c index 52914bcd65a..039375be0fd 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/DemoTasks/PlainTextHTTPExample.c +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/DemoTasks/PlainTextHTTPExample.c @@ -260,6 +260,10 @@ static BaseType_t prvSendHttpRequest( const TransportInterface_t * pxTransportIn /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /* * @brief Create the task that demonstrates the HTTP API Demo over a * mutually-authenticated network connection with an HTTP server. diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/http_plain_text_demo.sln b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/http_plain_text_demo.sln index be872d883c0..1eebb7726b3 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/http_plain_text_demo.sln +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_Plaintext/http_plain_text_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_Plaintext", "CoreHTTP_Plaintext.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_Plaintext", "CoreHTTP_Plaintext.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreHTTP", "..\..\..\VisualStudio_StaticProjects\coreHTTP\coreHTTP.vcxproj", "{EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" @@ -18,51 +17,18 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/CoreHTTP_S3_Download.vcxproj b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/CoreHTTP_S3_Download.vcxproj index 29d4ecc5f15..98073796411 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/CoreHTTP_S3_Download.vcxproj +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/CoreHTTP_S3_Download.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,15 +28,6 @@ - - - - - - - - - false @@ -77,62 +36,12 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\coreJSON\source\include;..\..\..\Source\AWS\sigv4\source\include;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\coreJSON\source\include;..\..\..\Source\AWS\sigv4\source\include;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\coreJSON\source\include;..\..\..\Source\AWS\sigv4\source\include;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\coreJSON\source\include;..\..\..\Source\AWS\sigv4\source\include;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/DemoTasks/S3DownloadHTTPExample.c b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/DemoTasks/S3DownloadHTTPExample.c index ac78ccd2954..ca4b9e2dbf3 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/DemoTasks/S3DownloadHTTPExample.c +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/DemoTasks/S3DownloadHTTPExample.c @@ -476,7 +476,7 @@ static JSONStatus_t prvParseCredentials( HTTPResponse_t * pxResponse, * @return pdPASS on success, pdFAIL on failure. */ static BaseType_t prvGetTemporaryCredentials( TransportInterface_t * pxTransportInterface, - const char * pcDateISO8601, + char * pcDateISO8601, size_t xDateISO8601Len, HTTPResponse_t * pxResponse, SigV4Credentials_t * pxSigvCreds ); @@ -582,6 +582,10 @@ void vStartSimpleHTTPDemo( void ) /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /** * @brief Entry point of the demo. * @@ -1177,7 +1181,7 @@ static BaseType_t prvDownloadS3ObjectFile( const TransportInterface_t * pxTransp } static BaseType_t prvGetTemporaryCredentials( TransportInterface_t * pxTransportInterface, - const char * pcDateISO8601, + char * pcDateISO8601, size_t xDateISO8601Len, HTTPResponse_t * pxResponse, SigV4Credentials_t * pxSigvCreds ) diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/README.md b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/README.md index 4cbc2c1a352..df5690ae3d8 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/README.md +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/README.md @@ -1,13 +1,19 @@ -# Configure HTTP S3 Download Demo using SigV4 Library. +# Configure HTTP S3 Download Demo using SigV4 Library Following steps needs to be followed to configure HTTP S3 Download Demo to use SigV4 library for authenticating the requests sent to AWS S3. -### Prerequisites +## Prerequisites -1. You will need an AWS Account with S3 access before beginning. You must be familiar with AWS IoT and IAM to perform steps using the AWS CLI. You must install and configure the AWS CLI in order to follow the steps. - For information on AWS S3 please see: https://docs.aws.amazon.com/AmazonS3/latest/dev/Welcome.html - For AWS CLI installation information please see: https://docs.aws.amazon.com/cli/latest/userguide/cli-chap-install.html - For AWS CLI configuration information please see: https://docs.aws.amazon.com/cli/latest/userguide/cli-chap-configure.html +1. You will need an AWS Account with S3 access before beginning. You must be familiar with +AWS IoT and IAM to perform steps using the AWS CLI. You must install and configure the AWS +CLI in order to follow the steps. + + * For information on AWS S3 please refer to the +[Welcome Guide](https://docs.aws.amazon.com/AmazonS3/latest/dev/Welcome.html) + + * [AWS CLI Installation guide](https://docs.aws.amazon.com/cli/latest/userguide/cli-chap-install.html) + + * [AWS CLI Configuration Guide](https://docs.aws.amazon.com/cli/latest/userguide/cli-chap-configure.html) ```sh aws configure @@ -15,36 +21,58 @@ Following steps needs to be followed to configure HTTP S3 Download Demo to use S ### Detailed Steps -#### 1. Create an AWS IoT thing: +#### 1. Create an AWS IoT thing -You may utilize an already existing AWS IoT Thing or create a new one in the IoT Core section of the AWS Management Console UI. +You may utilize an already existing AWS IoT Thing or create a new one in the IoT Core +section of the AWS Management Console UI. + +You may also use the AWS CLI with the following command to create a Thing, +keeping track of its name: -You may also use the AWS CLI with the following command to create a Thing, keeping track of its name: ```sh aws iot create-thing --thing-name device_thing_name ``` -#### 2. Register a certificate: +#### 2. Register a certificate -If your AWS IoT Thing already has a certificate attached to it, then that certificate's ARN can be used in [step 5](#5. attach-a-policy). Otherwise, you can create a certificate and attach it to the thing through IoT Core in the AWS Management Console UI. By doing any of these, you may skip to [step 3](#3-configure-an-iam-role). +If your AWS IoT Thing already has a certificate attached to it, then that certificate's +ARN can be used in [step 5](#5-attach-a-policy). Otherwise, you can create a certificate +and attach it to the thing through IoT Core in the AWS Management Console UI. By doing +any of these, you may skip to [step 3](#3-configure-an-iam-role). -It is also possible to sign the Thing's certificate using your own Certificate Authority (CA) certificate, and register both certificates with AWS IoT before your device can authenticate to AWS IoT. If you do not already have a CA certificate, you can use OpenSSL to create a CA certificate, as described in [Use Your Own Certificate](https://docs.aws.amazon.com/iot/latest/developerguide/device-certs-your-own.html). To register your CA certificate with AWS IoT, follow the steps on [Registering Your CA Certificate](https://docs.aws.amazon.com/iot/latest/developerguide/device-certs-your-own.html#register-CA-cert). +It is also possible to sign the Thing's certificate using your own Certificate Authority +(CA) certificate, and register both certificates with AWS IoT before your device can +authenticate to AWS IoT. If you do not already have a CA certificate, you can use OpenSSL +to create a CA certificate, as described in +[Use Your Own Certificate](https://docs.aws.amazon.com/iot/latest/developerguide/device-certs-your-own.html). +To register your CA certificate with AWS IoT, follow the steps on +[Registering Your CA Certificate](https://docs.aws.amazon.com/iot/latest/developerguide/device-certs-your-own.html#register-CA-cert). -You then have to create a device certificate signed by the CA certificate and register it with AWS IoT, which you can do by following the steps on [Creating a Device Certificate Using Your CA Certificate](https://docs.aws.amazon.com/iot/latest/developerguide/device-certs-your-own.html#create-device-cert). Save the certificate and the corresponding key pair; you will use them when you request a security token later. Also, remember the password you provide when you create the certificate. +You then have to create a device certificate signed by the CA certificate and register it +with AWS IoT, which you can do by following the steps on +[Creating a Device Certificate Using Your CA Certificate](https://docs.aws.amazon.com/iot/latest/developerguide/device-certs-your-own.html#create-device-cert). +Save the certificate and the corresponding key pair; you will use them when you request a +security token later. Also, remember the password you provide when you create the + certificate. -Run the following command in the AWS CLI to attach the device certificate to your thing so that you can use thing attributes in policy variables. +Run the following command in the AWS CLI to attach the device certificate to your thing +so that you can use thing attributes in policy variables. ```sh aws iot attach-thing-principal --thing-name device_thing_name --principal ``` -#### 3. Configure an IAM role: +#### 3. Configure an IAM role -Next, configure an IAM role in your AWS account that will be assumed by the credentials provider on behalf of your device. You are required to associate two policies with the role: a trust policy that controls who can assume the role, and an access policy that controls which actions can be performed on which resources by assuming the role. +Next, configure an IAM role in your AWS account that will be assumed by the credentials +provider on behalf of your device. You are required to associate two policies with the +role: a trust policy that controls who can assume the role, and an access policy that +controls which actions can be performed on which resources by assuming the role. -The following trust policy grants the credentials provider permission to assume the role. Put it in a text document and save the document with the name, trustpolicyforiot.json. +The following trust policy grants the credentials provider permission to assume the role. +Put it in a text document and save the document with the name, trustpolicyforiot.json. -``` +```json { "Version": "2012-10-17", "Statement": { @@ -54,13 +82,20 @@ The following trust policy grants the credentials provider permission to assume } } ``` -Run the following command in the AWS CLI to create an IAM role with the preceding trust policy. + +Run the following command in the AWS CLI to create an IAM role with the preceding trust +policy. ```sh aws iam create-role --role-name s3-access-role --assume-role-policy-document file://trustpolicyforiot.json ``` -The following s3 access policy allows you to perform actions on S3. Put the following policy in a text document and save the document with the name `accesspolicyfors3.json`. -``` + +The following s3 access policy allows you to perform actions on S3. Put the +following policy in a text document and save the document with the name +`accesspolicyfors3.json`. Make Sure to replace "BUCKET_NAME" with the name +of the S3 bucket you are using for this demo. + +```json { "Version": "2012-10-17", "Statement": { @@ -72,19 +107,29 @@ The following s3 access policy allows you to perform actions on S3. Put the foll } } ``` + Run the following command in the AWS CLI to create the access policy. + ```sh aws iam create-policy --policy-name accesspolicyfors3 --policy-document file://accesspolicyfors3.json ``` + Finally, run the following command in the AWS CLI to attach the access policy to your role. + ```sh aws iam attach-role-policy --role-name s3-access-role --policy-arn arn:aws:iam:::policy/accesspolicyfors3 ``` Configure the PassRole permissions -The IAM role that you have created must be passed to AWS IoT to create a role alias, as described in Step 4. The IAM user who performs the operation requires `iam:PassRole` permission to authorize this action. You also should add permission for the `iam:GetRole` action to allow the IAM user to retrieve information about the specified role. Create the following policy to grant `iam:PassRole` and `iam:GetRole` permissions. Name this policy `passrolepermission.json`. -``` +The IAM role that you have created must be passed to AWS IoT to create a role alias, as +described in Step 4. The IAM user who performs the operation requires `iam:PassRole` +permission to authorize this action. You also should add permission for the `iam:GetRole` +action to allow the IAM user to retrieve information about the specified role. Create the +following policy to grant `iam:PassRole` and `iam:GetRole` permissions. Name this policy +`passrolepermission.json`. + +```json { "Version": "2012-10-17", "Statement": { @@ -99,33 +144,51 @@ The IAM role that you have created must be passed to AWS IoT to create a role al ``` Run the following command in the AWS CLI to create the policy in your AWS account. + ```sh aws iam create-policy --policy-name passrolepermission --policy-document file://passrolepermission.json ``` Now, run the following command to attach the policy to the IAM user. + ```sh aws iam attach-user-policy --policy-arn arn:aws:iam:::policy/passrolepermission --user-name ``` -#### 4. Create a role alias: +#### 4. Create a role alias + +Now that you have configured the IAM role, you will create a role alias with AWS IoT. +You must provide the following pieces of information when creating a role alias: + +RoleAlias: This is the primary key of the role alias data model and hence a mandatory +attribute. It is a string; the minimum length is 1 character, and the maximum length is +128 characters. -Now that you have configured the IAM role, you will create a role alias with AWS IoT. You must provide the following pieces of information when creating a role alias: +RoleArn: This is the +[Amazon Resource Name (ARN)](https://docs.aws.amazon.com/general/latest/gr/aws-arns-and-namespaces.html) + of the IAM role you have created. This is also a mandatory attribute. -RoleAlias: This is the primary key of the role alias data model and hence a mandatory attribute. It is a string; the minimum length is 1 character, and the maximum length is 128 characters. +CredentialDurationSeconds: This is an optional attribute specifying the validity +(in seconds) of the security token. The minimum value is 900 seconds (15 minutes), +and the maximum value is 43,200 seconds (12 hours); the default value is 3,600 seconds, +if not specified. -RoleArn: This is the [Amazon Resource Name (ARN)](https://docs.aws.amazon.com/general/latest/gr/aws-arns-and-namespaces.html) of the IAM role you have created. This is also a mandatory attribute. +**Note**: The credentialDurationSeconds value must be less than or equal to the + maximum session duration of the IAM role that the role alias references, + otherwise the request will be rejected by the credentials provider. -CredentialDurationSeconds: This is an optional attribute specifying the validity (in seconds) of the security token. The minimum value is 900 seconds (15 minutes), and the maximum value is 3,600 seconds (60 minutes); the default value is 3,600 seconds, if not specified. +Run the following command in the AWS CLI to create a role alias. Use the credentials of +the user to whom you have given the iam:PassRole permission. -Run the following command in the AWS CLI to create a role alias. Use the credentials of the user to whom you have given the iam:PassRole permission. ```sh aws iot create-role-alias --role-alias name-s3-access-role-alias --role-arn arn:aws:iam:::role/s3-access-role --credential-duration-seconds 3600 ``` -#### 5. Attach a policy: +#### 5. Attach a policy + You created and registered a certificate with AWS IoT earlier for successful authentication of your device. Now, you need to create and attach a policy to the certificate to authorize the request for the security token. -``` + +```json { "Version": "2012-10-17", "Statement": [ @@ -137,47 +200,46 @@ You created and registered a certificate with AWS IoT earlier for successful aut ] } ``` + Run the following command in the AWS CLI to create the policy in your AWS IoT database. + ```sh aws iot create-policy --policy-name Thing_Policy_Name --policy-document file://thingpolicy.json ``` + Use the following command to attach the policy with the certificate you registered earlier. + ```sh aws iot attach-policy --policy-name Thing_Policy_Name --target ``` -#### 6. Request a security token: - -Make an HTTPS request to the credentials provider to fetch a security token. You have to supply the following information: +#### 6. Obtain the Credentials Provider Endpoint -Certificate and key pair: Because this is an HTTP request over TLS mutual authentication, you have to provide the certificate and the corresponding key pair to your client while making the request. Use the same certificate and key pair that you used during certificate registration with AWS IoT. - -RoleAlias: Provide the role alias (in this example, Thermostat-dynamodb-access-role-alias) to be assumed in the request. - -ThingName: Provide the thing name that you created earlier in the AWS IoT thing registry database. This is passed as a header with the name, x-amzn-iot-thingname. Note that the thing name is mandatory only if you have thing attributes as policy variables in AWS IoT or IAM policies. - -Run the following command in the AWS CLI to obtain your AWS account-specific endpoint for the credentials provider. See the [DescribeEndpoint API documentation](https://docs.aws.amazon.com/iot/latest/apireference/API_DescribeEndpoint.html) for further details. +Run the following command in the AWS CLI to obtain your AWS account-specific +endpoint for the credentials provider. See the +[DescribeEndpoint API documentation](https://docs.aws.amazon.com/iot/latest/apireference/API_DescribeEndpoint.html) +for further details. ```sh aws iot describe-endpoint --endpoint-type iot:CredentialProvider ``` + The following is sample output of the describe-endpoint command. It contains the endpointAddress. -``` + +```json { "endpointAddress": ".credentials.iot.us-east-1.amazonaws.com" } ``` -#### 7. Copy and paste the output to `demo_config.h` for macros `democonfigIOT_CREDENTIAL_PROVIDER_ENDPOINT`. +Next, copy this endpoint to the macro below in `demo_config.h`. + ```c #define democonfigIOT_CREDENTIAL_PROVIDER_ENDPOINT ".credentials.iot.us-east-1.amazonaws.com" - -#define CLIENT_CERT_PATH "path of the client certificate downloaded when setting up the device certificate in AWS IoT Account Setup" - -#define CLIENT_PRIVATE_KEY_PATH "path of the private key downloaded when setting up the device certificate in AWS IoT Account Setup" ``` -#### 8. After the following the above steps, configure the below macros in `demo_config.h`. +#### 7. After the following the above steps, configure the below macros in `demo_config.h` + ```c #define democonfigIOT_THING_NAME "Name of IOT Thing that you provided in STEP 1" #define democonfigIOT_CREDENTIAL_PROVIDER_ROLE "Name of ROLE ALIAS that you provided in STEP 4" @@ -185,17 +247,3 @@ The following is sample output of the describe-endpoint command. It contains the #define democonfigS3_BUCKET_REGION "Region where Bucket is located" #define democonfigS3_OBJECT_NAME "Name of object that needs to be downloaded from AWS S3" ``` - -### Parameters - -#### device_thing_name -The name of the AWS IoT thing for your device registered with AWS IoT core. - -#### thing_name-s3-access-role-alias -The name for the role alias for S3. - -#### Thing_Policy_Name -The name of the policy attached to the device certificate in [step 5](#5-attach-a-policy). - -#### BUCKET_NAME -The name of the S3 bucket from which the demo will download. diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/demo_config.h b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/demo_config.h index f5695422aef..6cb0f0c0320 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/demo_config.h +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/demo_config.h @@ -79,13 +79,7 @@ extern void vLoggingPrintf( const char * pcFormatString, /** * @brief Server's root CA certificate for TLS authentication with S3. * - * The Baltimore Cybertrust root CA certificate is often used for authentication - * with S3. It can be found at: - * https://baltimore-cybertrust-root.chain-demos.digicert.com/info/index.html. - * - * S3 has started migrating certificates to Amazon Trust Services. If - * authentication errors persist, re-attempt the connection with an Amazon root - * CA certificate: https://www.amazontrust.com/repository. + * The CA can be found at https://www.amazontrust.com/repository. * * @note This certificate should be PEM-encoded. * @@ -207,7 +201,7 @@ extern void vLoggingPrintf( const char * pcFormatString, /** * @brief Transport timeout in milliseconds for transport send and receive. */ -#define democonfigTRANSPORT_SEND_RECV_TIMEOUT_MS ( 5000 ) +#define democonfigTRANSPORT_SEND_RECV_TIMEOUT_MS ( 10000 ) /** * @brief The length in bytes of the user buffer. diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/http_s3_download_demo.sln b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/http_s3_download_demo.sln index 40e731dc0bd..1322c1212e0 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/http_s3_download_demo.sln +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download/http_s3_download_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_S3_Download", "CoreHTTP_S3_Download.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_S3_Download", "CoreHTTP_S3_Download.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreHTTP", "..\..\..\VisualStudio_StaticProjects\coreHTTP\coreHTTP.vcxproj", "{EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/CoreHTTP_S3_Download_Multithreaded.vcxproj b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/CoreHTTP_S3_Download_Multithreaded.vcxproj index 4f370d56f73..d8bd532ea97 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/CoreHTTP_S3_Download_Multithreaded.vcxproj +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/CoreHTTP_S3_Download_Multithreaded.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,15 +28,6 @@ - - - - - - - - - false @@ -77,62 +36,12 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/DemoTasks/S3DownloadMultithreadedHTTPExample.c b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/DemoTasks/S3DownloadMultithreadedHTTPExample.c index cd8359627bd..e28bcc8a893 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/DemoTasks/S3DownloadMultithreadedHTTPExample.c +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/DemoTasks/S3DownloadMultithreadedHTTPExample.c @@ -429,6 +429,10 @@ static BaseType_t prvDownloadLoop( void ); /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /* * @brief Create task to demonstrate the HTTP API over a server-authenticated * network connection with a server. diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/demo_config.h b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/demo_config.h index 0013f75c74a..00e40e13c9e 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/demo_config.h +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/demo_config.h @@ -79,13 +79,7 @@ extern void vLoggingPrintf( const char * pcFormatString, /** * @brief Server's root CA certificate for TLS authentication with S3. * - * The Baltimore Cybertrust root CA certificate is often used for authentication - * with S3. It can be found at: - * https://baltimore-cybertrust-root.chain-demos.digicert.com/info/index.html. - * - * S3 has started migrating certificates to Amazon Trust Services. If - * authentication errors persist, re-attempt the connection with an Amazon root - * CA certificate: https://www.amazontrust.com/repository. + * The CA can be found at https://www.amazontrust.com/repository. * * @note This certificate should be PEM-encoded. * diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/http_s3_download_multithreaded_demo.sln b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/http_s3_download_multithreaded_demo.sln index 4a677fcfc58..35900706b0f 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/http_s3_download_multithreaded_demo.sln +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Download_Multithreaded/http_s3_download_multithreaded_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_S3_Download_Multithreaded", "CoreHTTP_S3_Download_Multithreaded.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_S3_Download_Multithreaded", "CoreHTTP_S3_Download_Multithreaded.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreHTTP", "..\..\..\VisualStudio_StaticProjects\coreHTTP\coreHTTP.vcxproj", "{EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/CoreHTTP_S3_Upload.vcxproj b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/CoreHTTP_S3_Upload.vcxproj index 41621afdf84..ffbda9c2312 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/CoreHTTP_S3_Upload.vcxproj +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/CoreHTTP_S3_Upload.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,15 +28,6 @@ - - - - - - - - - false @@ -77,62 +36,12 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/DemoTasks/S3UploadHTTPExample.c b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/DemoTasks/S3UploadHTTPExample.c index e4a50471fc1..e1bbc408c76 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/DemoTasks/S3UploadHTTPExample.c +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/DemoTasks/S3UploadHTTPExample.c @@ -295,6 +295,10 @@ static BaseType_t prvVerifyS3ObjectFileSize( const TransportInterface_t * pxTran /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /* * @brief Create the task that demonstrates the HTTP API Demo over a * server-authenticated network connection with an HTTP server. diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/demo_config.h b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/demo_config.h index a2d034fc16f..3bc1d594b3b 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/demo_config.h +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/demo_config.h @@ -79,13 +79,7 @@ extern void vLoggingPrintf( const char * pcFormatString, /** * @brief Server's root CA certificate for TLS authentication with S3. * - * The Baltimore Cybertrust root CA certificate is often used for authentication - * with S3. It can be found at: - * https://baltimore-cybertrust-root.chain-demos.digicert.com/info/index.html. - * - * S3 has started migrating certificates to Amazon Trust Services. If - * authentication errors persist, re-attempt the connection with an Amazon root - * CA certificate: https://www.amazontrust.com/repository. + * The CA can be found at https://www.amazontrust.com/repository. * * @note This certificate should be PEM-encoded. * diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/http_s3_upload_demo.sln b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/http_s3_upload_demo.sln index 7959e593d8f..adb6d8aec68 100644 --- a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/http_s3_upload_demo.sln +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/HTTP_S3_Upload/http_s3_upload_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_S3_Upload", "CoreHTTP_S3_Upload.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CoreHTTP_S3_Upload", "CoreHTTP_S3_Upload.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreHTTP", "..\..\..\VisualStudio_StaticProjects\coreHTTP\coreHTTP.vcxproj", "{EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|Win32.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/readme.url b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/readme.url new file mode 100644 index 00000000000..b7c2130af1b --- /dev/null +++ b/FreeRTOS-Plus/Demo/coreHTTP_Windows_Simulator/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/03-FreeRTOS-core/04-coreHTTP/03-coreHTTP-demos/01-coreHTTP-demo diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/DemoTasks/BasicTLSMQTTExample.c b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/DemoTasks/BasicTLSMQTTExample.c index 06470c3f28f..5f119afd810 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/DemoTasks/BasicTLSMQTTExample.c +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/DemoTasks/BasicTLSMQTTExample.c @@ -125,7 +125,7 @@ /** * @brief Timeout for receiving CONNACK packet in milliseconds. */ -#define mqttexampleCONNACK_RECV_TIMEOUT_MS ( 1000U ) +#define mqttexampleCONNACK_RECV_TIMEOUT_MS ( 2000U ) /** * @brief The prefix to the topic(s) subscribe(d) to and publish(ed) to in the example. @@ -160,7 +160,7 @@ * @brief Timeout for MQTT_ProcessLoop in milliseconds. * Refer to FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/readme.txt for more details. */ -#define mqttexamplePROCESS_LOOP_TIMEOUT_MS ( 2000U ) +#define mqttexamplePROCESS_LOOP_TIMEOUT_MS ( 5000U ) /** * @brief The keep-alive timeout period reported to the broker while establishing @@ -443,11 +443,12 @@ void vStartSimpleMQTTDemo( void ) * state or call the MQTT_ProcessLoop() API function. Using an agent task * also enables multiple application tasks to more easily share a single * MQTT connection. */ + xTaskCreate( prvMQTTDemoTask, /* Function that implements the task. */ "DemoTask", /* Text name for the task - only used for debugging. */ democonfigDEMO_STACKSIZE, /* Size of stack (in words, not bytes) to allocate for the task. */ NULL, /* Task parameter - not used in this case. */ - tskIDLE_PRIORITY, /* Task priority, must be between 0 and configMAX_PRIORITIES - 1. */ + tskIDLE_PRIORITY + 1, /* Task priority, must be between 0 and configMAX_PRIORITIES - 1. */ NULL ); /* Used to pass out a handle to the created task - not used in this case. */ } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/MQTT_Basic_TLS.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/MQTT_Basic_TLS.vcxproj index 3c5e4cdf683..730f72e709f 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/MQTT_Basic_TLS.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/MQTT_Basic_TLS.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - true @@ -102,23 +48,11 @@ true - - false - - - true - - - true - - - false - Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) @@ -131,7 +65,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) @@ -146,72 +80,6 @@ xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/mqtt_basic_tls_demo.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/mqtt_basic_tls_demo.sln index bc5aea730fa..59f4230d6df 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/mqtt_basic_tls_demo.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Basic_TLS/mqtt_basic_tls_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -18,106 +17,29 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug|Win32.ActiveCfg = Debug|Win32 {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug|Win32.Build.0 = Debug|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug|x64.ActiveCfg = Debug|x64 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug|x64.Build.0 = Debug|x64 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug|x86.ActiveCfg = Debug|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Debug|x86.Build.0 = Debug|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Release|Win32.ActiveCfg = Release|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Release|Win32.Build.0 = Release|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Release|x64.ActiveCfg = Release|x64 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Release|x64.Build.0 = Release|x64 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Release|x86.ActiveCfg = Release|Win32 - {0B57F66E-FFDB-430F-A28D-0D9F8062FAEB}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/DemoTasks/KeepAliveMQTTExample.c b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/DemoTasks/KeepAliveMQTTExample.c index b89bb644d80..95aa751c516 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/DemoTasks/KeepAliveMQTTExample.c +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/DemoTasks/KeepAliveMQTTExample.c @@ -71,6 +71,9 @@ /* Transport interface include. */ #include "transport_plaintext.h" +/* FreeRTOS+TCP IP config include. */ +#include "FreeRTOSIPConfig.h" + /*-----------------------------------------------------------*/ /* Compile time error for undefined configs. */ diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/MQTT_Keep_Alive.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/MQTT_Keep_Alive.vcxproj index 31a74313454..7853aa7e3d9 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/MQTT_Keep_Alive.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/MQTT_Keep_Alive.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -40,32 +24,9 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - v142 - - v142 - @@ -74,33 +35,15 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) @@ -109,66 +52,6 @@ true - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/mqtt_keep_alive_demo.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/mqtt_keep_alive_demo.sln index de868fe3069..2a2399a78cf 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/mqtt_keep_alive_demo.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Keep_Alive/mqtt_keep_alive_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -18,106 +17,29 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug|Win32.ActiveCfg = Debug|Win32 {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug|Win32.Build.0 = Debug|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug|x64.ActiveCfg = Debug|x64 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug|x64.Build.0 = Debug|x64 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug|x86.ActiveCfg = Debug|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Debug|x86.Build.0 = Debug|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Release|Win32.ActiveCfg = Release|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Release|Win32.Build.0 = Release|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Release|x64.ActiveCfg = Release|x64 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Release|x64.Build.0 = Release|x64 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Release|x86.ActiveCfg = Release|Win32 - {7260CB0D-0BBF-4DAC-91D9-D091022C1F9A}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - 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{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/MQTT_Multitask.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/MQTT_Multitask.vcxproj index bb04d00582e..f549609f906 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/MQTT_Multitask.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/MQTT_Multitask.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,85 +28,20 @@ - - - - - - - - - true - - false - - - true - - - false - Level3 true - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\Demo\Common\coreMQTT_Agent_Interface\include;.\subscription-manager;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\Demo\Common\coreMQTT_Agent_Interface\include;.\subscription-manager;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\Demo\Common\coreMQTT_Agent_Interface\include;.\subscription-manager;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - true - true - MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Application-Protocols\coreMQTT-Agent\source\include;..\..\..\Demo\Common\coreMQTT_Agent_Interface\include;.\subscription-manager;%(AdditionalIncludeDirectories) Console - true - true true diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/demo_config.h b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/demo_config.h index 5debbd328ea..35bd51f57f1 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/demo_config.h +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/demo_config.h @@ -293,4 +293,10 @@ extern void vLoggingPrintf( const char * pcFormatString, #define democonfigMQTT_LIB "core-mqtt@"MQTT_LIBRARY_VERSION #endif +/** + * @brief The number of command structures to allocate in the pool + * for the agent. + */ +#define MQTT_COMMAND_CONTEXTS_POOL_SIZE 10 + #endif /* DEMO_CONFIG_H */ diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_broker_setup.txt b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_broker_setup.txt index 5db8e918642..64f860654c8 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_broker_setup.txt +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_broker_setup.txt @@ -4,7 +4,7 @@ TLS mutual authentication for use with this MQTT demo. a. Download and install [Git For Windows](https://git-scm.com/download/win). Most of you may already have this installed. Git For Windows provides an OpenSSL binary for generating certificates. - b. Open PowerShell and enter the following commands to generate TLS certificates: + b. Open PowerShell and enter the following commands to generate TLS certificates [Note: While creating the certificates make sure to not use same organization name for all the certificates to prevent "self-signed certificate" error.]: i. cd "C:\Program Files\Git\usr\bin" # If Git is installed elsewhere, update the path. ii. mkdir $home\Documents\certs iii. .\openssl.exe req -x509 -nodes -sha256 -days 365 -newkey rsa:2048 -keyout $home\Documents\certs\ca.key -out $home\Documents\certs\ca.crt @@ -13,16 +13,19 @@ TLS mutual authentication for use with this MQTT demo. vi. .\openssl.exe genrsa -out $home\Documents\certs\client.key 2048 vii. .\openssl.exe req -new -out $home\Documents\certs\client.csr -key $home\Documents\certs\client.key viii. .\openssl.exe x509 -req -in $home\Documents\certs\client.csr -CA $home\Documents\certs\ca.crt -CAkey $home\Documents\certs\ca.key -CAcreateserial -out $home\Documents\certs\client.crt -days 365 + ix. [Optional] .\openssl.exe verify -CAfile $home\Documents\certs\ca.crt $home\Documents\certs\server.crt # verify the server certificate is correctly signed + x. [Optional] .\openssl.exe verify -CAfile $home\Documents\certs\ca.crt $home\Documents\certs\client.crt # verify the client certificate is correctly signed 2. Download Mosquitto from https://mosquitto.org/download/ 3. Install Mosquitto as a Windows service by running the installer. 4. Go to the path where Mosquitto was installed. The default path is C:\Program Files\mosquitto. -5. Update mosquitto.conf to have the following entries and don't forget to substitute your Windows username: - port 8883 +5. Update mosquitto.conf to have the following entries and don't forget to substitute your Windows username [Mosquitto Version 2.0.0 onwards]: + listener 8883 cafile C:\Users\%Substitute Windows username%\Documents\certs\ca.crt certfile C:\Users\%Substitute Windows username%\Documents\certs\server.crt keyfile C:\Users\%Substitute Windows username%\Documents\certs\server.key require_certificate true tls_version tlsv1.2 + allow_anonymous true 6. Start the Mosquitto service. More details about running Mosquitto as a Windows service can be found at https://github.com/eclipse/mosquitto/blob/master/readme-windows.txt and diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_multitask_demo.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_multitask_demo.sln index 96f752d3faf..4bfbfb52644 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_multitask_demo.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Multitask/mqtt_multitask_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -18,73 +17,18 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {C35A89CA-0A40-49FF-A7F8-6E6830809B26}.Debug|Win32.ActiveCfg = Debug|Win32 {C35A89CA-0A40-49FF-A7F8-6E6830809B26}.Debug|Win32.Build.0 = Debug|Win32 - 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{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/MQTT_Mutual_Auth.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/MQTT_Mutual_Auth.vcxproj index 8315c9c7f90..9ad54e38868 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/MQTT_Mutual_Auth.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/MQTT_Mutual_Auth.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - true @@ -102,25 +48,13 @@ true - - false - - - true - - - true - - - false - Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) + .\;..\..\..\VisualStudio_StaticProjects\MbedTLS;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) Console @@ -131,56 +65,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) @@ -195,23 +80,6 @@ xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/mqtt_mutual_auth_demo.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/mqtt_mutual_auth_demo.sln index c1dbf5726a2..5193beaef9f 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/mqtt_mutual_auth_demo.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth/mqtt_mutual_auth_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -18,106 +17,29 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug|Win32.ActiveCfg = Debug|Win32 {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug|Win32.Build.0 = Debug|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug|x64.ActiveCfg = Debug|x64 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug|x64.Build.0 = Debug|x64 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug|x86.ActiveCfg = Debug|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Debug|x86.Build.0 = Debug|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Release|Win32.ActiveCfg = Release|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Release|Win32.Build.0 = Release|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Release|x64.ActiveCfg = Release|x64 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Release|x64.Build.0 = Release|x64 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Release|x86.ActiveCfg = Release|Win32 - {DD2281B6-6D9B-4477-BA0A-8842F2E917C7}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/MQTT_Mutual_Auth_wolfSSL.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/MQTT_Mutual_Auth_wolfSSL.vcxproj index d91c84e5623..ab1b3d2517b 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/MQTT_Mutual_Auth_wolfSSL.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/MQTT_Mutual_Auth_wolfSSL.vcxproj @@ -60,7 +60,7 @@ Disabled .\;..\Common;..\..\..\..\FreeRTOS-Plus\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\FreeRTOS-Plus\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\FreeRTOS-Plus\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\wolfSSL_freertos;..\..\..\ThirdParty\wolfSSL;%(AdditionalIncludeDirectories) - WOLFSSL_USER_SETTINGS;WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) + WOLFSSL_USER_SETTINGS;WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";%(PreprocessorDefinitions) false EnableFastChecks MultiThreadedDLL @@ -109,7 +109,7 @@ Disabled .\;..\Common;..\..\..\..\FreeRTOS-Plus\Source\Application-Protocols\coreMQTT\source\include;..\..\..\..\FreeRTOS-Plus\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\..\FreeRTOS-Plus\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\wolfSSL_freertos;..\..\..\ThirdParty\wolfSSL;%(AdditionalIncludeDirectories) - WOLFSSL_USER_SETTINGS;WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";%(PreprocessorDefinitions) + WOLFSSL_USER_SETTINGS;WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";%(PreprocessorDefinitions) false EnableFastChecks MultiThreadedDLL diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/mqtt_mutual_auth_demo_wolfSSL.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/mqtt_mutual_auth_demo_wolfSSL.sln index 51e1d4b14de..4d1b980f5da 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/mqtt_mutual_auth_demo_wolfSSL.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/mqtt_mutual_auth_demo_wolfSSL.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.29215.179 @@ -18,71 +17,29 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|Win32 {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|x64.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|x64.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|x64.Build.0 = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/user_settings.h b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/user_settings.h index fc077b7a508..a95f37ed0cf 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/user_settings.h +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Mutual_Auth_wolfSSL/user_settings.h @@ -103,6 +103,8 @@ #define NO_MD4 #define NO_PWDBASED +#define WOLFSSL_ALT_CERT_CHAINS + /*-- Debugging options ------------------------------------------------------ * * "DEBUG_WOLFSSL" definition enables log to output into stdout. diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/MQTT_Plain_Text.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/MQTT_Plain_Text.vcxproj index 1ed1ae1e3ad..78c30175778 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/MQTT_Plain_Text.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/MQTT_Plain_Text.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - true @@ -102,23 +48,11 @@ true - - false - - - true - - - true - - - false - Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) @@ -131,7 +65,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) @@ -146,72 +80,6 @@ xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/mqtt_plain_text_demo.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/mqtt_plain_text_demo.sln index c57894f6651..3b35367f6e1 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/mqtt_plain_text_demo.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Plain_Text/mqtt_plain_text_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -18,106 +17,29 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug|Win32.ActiveCfg = Debug|Win32 {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug|Win32.Build.0 = Debug|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug|x64.ActiveCfg = Debug|x64 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug|x64.Build.0 = Debug|x64 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug|x86.ActiveCfg = Debug|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Debug|x86.Build.0 = Debug|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Release|Win32.ActiveCfg = Release|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Release|Win32.Build.0 = Release|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Release|x64.ActiveCfg = Release|x64 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Release|x64.Build.0 = Release|x64 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Release|x86.ActiveCfg = Release|Win32 - {95746A42-54E8-4A6C-AE5D-EE5CE3B086BD}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/MQTT_Serializer.vcxproj b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/MQTT_Serializer.vcxproj index d2ed2f7d27a..c056dba81a7 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/MQTT_Serializer.vcxproj +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/MQTT_Serializer.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - true @@ -102,23 +48,11 @@ true - - false - - - true - - - true - - - false - Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) @@ -131,7 +65,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) @@ -146,72 +80,6 @@ xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .\;..\Common;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\..\Source\Application-Protocols\coreMQTT\source\interface;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/mqtt_serializer_demo.sln b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/mqtt_serializer_demo.sln index 16a609a5c8c..81b5bcf50f3 100644 --- a/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/mqtt_serializer_demo.sln +++ b/FreeRTOS-Plus/Demo/coreMQTT_Windows_Simulator/MQTT_Serializer/mqtt_serializer_demo.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.32929.386 @@ -18,106 +17,29 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug|Win32.ActiveCfg = Debug|Win32 {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug|Win32.Build.0 = Debug|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug|x64.ActiveCfg = Debug|x64 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug|x64.Build.0 = Debug|x64 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug|x86.ActiveCfg = Debug|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Debug|x86.Build.0 = Debug|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Release|Win32.ActiveCfg = Release|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Release|Win32.Build.0 = Release|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Release|x64.ActiveCfg = Release|x64 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Release|x64.Build.0 = Release|x64 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Release|x86.ActiveCfg = Release|Win32 - {B7A01D2B-CF81-4A65-BC54-AF2185F6E51A}.Release|x86.Build.0 = Release|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - 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{72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/PKCS11_Mqtt_MutualAuthDemo.c b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/PKCS11_Mqtt_MutualAuthDemo.c index 2ecde1989e3..c403a6396eb 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/PKCS11_Mqtt_MutualAuthDemo.c +++ b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/PKCS11_Mqtt_MutualAuthDemo.c @@ -304,6 +304,10 @@ static MQTTStatus_t prvProcessLoopWithTimeout( MQTTContext_t * pMqttContext, /*-----------------------------------------------------------*/ +extern BaseType_t xPlatformIsNetworkUp( void ); + +/*-----------------------------------------------------------*/ + /* @brief Static buffer used to hold MQTT messages being sent and received. */ static uint8_t ucSharedBuffer[ democonfigNETWORK_BUFFER_SIZE ]; @@ -416,7 +420,18 @@ static void prvMQTTDemoTask( void * pvParameters ) for( ; ; ) { LogInfo( ( "---------STARTING DEMO---------\r\n" ) ); + /****************************** Connect. ******************************/ + /* Wait for Networking */ + if( xPlatformIsNetworkUp() == pdFALSE ) + { + LogInfo( ( "Waiting for the network link up event..." ) ); + + while( xPlatformIsNetworkUp() == pdFALSE ) + { + vTaskDelay( pdMS_TO_TICKS( 1000U ) ); + } + } /* Establish a TLS connection with the MQTT broker. This example connects * to the MQTT broker as specified by democonfigMQTT_BROKER_ENDPOINT and diff --git a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.sln b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.sln index 293f27e98e7..46e454a4586 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.sln +++ b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "corePKCS11_MQTT_Mutual_Auth", "corePKCS11_MQTT_Mutual_Auth.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "corePKCS11_MQTT_Mutual_Auth", "corePKCS11_MQTT_Mutual_Auth.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.ActiveCfg = Debug|Win32 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.Build.0 = Debug|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.ActiveCfg = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.Build.0 = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.ActiveCfg = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.Build.0 = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.ActiveCfg = Release|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj index d043acf3924..233b17f6b80 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj +++ b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,28 +28,10 @@ - - - - - - - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\Source\Application-Protocols\coreMQTT\source\interface;$(IncludePath) - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\Source\Application-Protocols\coreMQTT\source\interface;$(IncludePath) - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\Source\Application-Protocols\coreMQTT\source\interface;$(IncludePath) - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreMQTT\source\include;..\..\Source\Application-Protocols\coreMQTT\source\interface;$(IncludePath) - false @@ -89,66 +39,13 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - true - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - true - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) - true - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;..\Common;DemoTasks\include;..\..\..\Source\Application-Protocols\network_transport\tcp_sockets_wrapper\include;..\..\..\Source\Application-Protocols\network_transport;..\..\..\Source\Utilities\backoff_algorithm\source\include;%(AdditionalIncludeDirectories) true Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj.filters b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj.filters index 0cd220a2989..5671bff6c7d 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj.filters +++ b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/corePKCS11_MQTT_Mutual_Auth.vcxproj.filters @@ -72,6 +72,7 @@ Source + @@ -111,4 +112,4 @@ Config - \ No newline at end of file + diff --git a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/main.c index 5ac4da7cc6e..7c1e0b91c21 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/main.c +++ b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/main.c @@ -52,6 +52,8 @@ extern void vPlatformInitIpStack( void ); +extern void vStartPKCSMutualAuthDemo( void ); + /*-----------------------------------------------------------*/ int main( void ) diff --git a/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/readme.url b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/readme.url new file mode 100644 index 00000000000..78f349fe565 --- /dev/null +++ b/FreeRTOS-Plus/Demo/corePKCS11_MQTT_Mutual_Auth_Windows_Simulator/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/03-FreeRTOS-core/08-corePKCS11/03-corePKCS11-demos/01-Mutual-authentication-demo diff --git a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.sln b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.sln index 0c081943ef4..a1dee347c0f 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.sln +++ b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CorePKCS11_Demos", "CorePKCS11_Demos.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CorePKCS11_Demos", "CorePKCS11_Demos.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" @@ -20,85 +19,33 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.ActiveCfg = Debug|Win32 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.Build.0 = Debug|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.ActiveCfg = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.Build.0 = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.ActiveCfg = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.Build.0 = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.ActiveCfg = Release|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.vcxproj b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.vcxproj index 884af50514e..32431e717a7 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.vcxproj +++ b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/CorePKCS11_Demos.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - false @@ -103,7 +49,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;examples;%(AdditionalIncludeDirectories) @@ -117,58 +63,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;examples;%(AdditionalIncludeDirectories) - - - Console - true - Iphlpapi.lib;Ws2_32.lib;%(AdditionalDependencies) - - - xcopy /y /d "..\..\ThirdParty\glib\build\glib\glib-2.0-0.dll" "$(OutDir)" -xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" "$(OutDir)" -xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;examples;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;examples;%(AdditionalIncludeDirectories) - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .;examples;%(AdditionalIncludeDirectories) @@ -183,24 +78,6 @@ xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\proxy-libintl\intl-8.dll" " xcopy /y /d "..\..\ThirdParty\glib\build\subprojects\pcre2-10.42\pcre2-8-0.dll" "$(OutDir)" - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - .;examples;%(AdditionalIncludeDirectories) - - - Console - true - true - true - %(AdditionalDependencies) - - {19f0ff1a-3368-491a-9932-a2f089508f51} diff --git a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/main.c index 06be932930f..d15ce3059ba 100644 --- a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/main.c +++ b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/main.c @@ -51,6 +51,11 @@ /*-----------------------------------------------------------*/ +extern void vPlatformInitLogging( void ); +extern void vPlatformStopLoggingThreadAndFlush( void ); + +/*-----------------------------------------------------------*/ + static void prvPKCS11DemoTask( void * pvParameters ) { configPRINTF( ( "---------STARTING DEMO---------\r\n" ) ); @@ -68,6 +73,7 @@ static void prvPKCS11DemoTask( void * pvParameters ) #endif configPRINTF( ( "---------Finished DEMO---------\r\n" ) ); + vPlatformStopLoggingThreadAndFlush(); exit( 0 ); } diff --git a/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/readme.url b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/readme.url new file mode 100644 index 00000000000..b50ce962f61 --- /dev/null +++ b/FreeRTOS-Plus/Demo/corePKCS11_Windows_Simulator/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/03-FreeRTOS-core/08-corePKCS11/03-corePKCS11-demos/04-Objects-demo diff --git a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/SNTPClientTask.c b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/SNTPClientTask.c index 77a8ea09d88..17f8b528049 100644 --- a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/SNTPClientTask.c +++ b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/SNTPClientTask.c @@ -550,7 +550,7 @@ static void populateAuthContextForServer( const char * pServer, static SntpStatus_t addClientAuthCode( SntpAuthContext_t * pAuthContext, const SntpServerInfo_t * pTimeServer, void * pRequestBuffer, - uint16_t bufferSize, + size_t bufferSize, uint16_t * pAuthCodeSize ); @@ -586,7 +586,7 @@ static SntpStatus_t addClientAuthCode( SntpAuthContext_t * pAuthContext, static SntpStatus_t validateServerAuth( SntpAuthContext_t * pAuthContext, const SntpServerInfo_t * pTimeServer, const void * pResponseData, - size_t responseSize ); + uint16_t responseSize ); /** * @brief Generates a random number using PKCS#11. @@ -668,6 +668,7 @@ void calculateCurrentTime( UTCTime_t * pBaseTime, UTCTime_t * pCurrentTime ) { uint64_t msElapsedSinceLastSync = 0; + uint64_t currentTimeSecs; TickType_t ticksElapsedSinceLastSync = xTaskGetTickCount() - lastSyncTickCount; /* Calculate time elapsed since last synchronization according to the number @@ -686,13 +687,30 @@ void calculateCurrentTime( UTCTime_t * pBaseTime, /* Set the current UTC time in the output parameter. */ if( msElapsedSinceLastSync >= 1000 ) { - pCurrentTime->secs = pBaseTime->secs + msElapsedSinceLastSync / 1000; + currentTimeSecs = ( uint64_t ) ( pBaseTime->secs ) + ( msElapsedSinceLastSync / 1000 ); + + /* Support case of UTC timestamp rollover on 7 February 2038. */ + if( currentTimeSecs > UINT32_MAX ) + { + /* Assert when the UTC timestamp rollover. */ + configASSERT( !( currentTimeSecs > UINT32_MAX ) ); + + /* Subtract an extra second as timestamp 0 represents the epoch for + * UTC era 1. */ + LogWarn( ( "UTC timestamp rollover." ) ); + pCurrentTime->secs = ( uint32_t ) ( currentTimeSecs - UINT32_MAX - 1 ); + } + else + { + pCurrentTime->secs = ( uint32_t ) ( currentTimeSecs ); + } + pCurrentTime->msecs = msElapsedSinceLastSync % 1000; } else { pCurrentTime->secs = pBaseTime->secs; - pCurrentTime->msecs = msElapsedSinceLastSync; + pCurrentTime->msecs = ( uint32_t ) ( msElapsedSinceLastSync ); } } @@ -842,7 +860,7 @@ static int32_t UdpTransport_Recv( NetworkContext_t * pNetworkContext, static void sntpClient_GetTime( SntpTimestamp_t * pCurrentTime ) { UTCTime_t currentTime; - uint64_t ntpSecs; + uint32_t ntpSecs; /* Obtain mutex for accessing system clock variables */ xSemaphoreTake( xMutex, portMAX_DELAY ); @@ -862,8 +880,12 @@ static void sntpClient_GetTime( SntpTimestamp_t * pCurrentTime ) * converting from UNIX time to SNTP timestamp. */ if( ntpSecs > UINT32_MAX ) { + /* Assert when SNTP time rollover. */ + configASSERT( !( ntpSecs > UINT32_MAX ) ); + /* Subtract an extra second as timestamp 0 represents the epoch for * NTP era 1. */ + LogWarn( ( "SNTP timestamp rollover." ) ); pCurrentTime->seconds = ntpSecs - UINT32_MAX - 1; } else @@ -977,7 +999,7 @@ static void populateAuthContextForServer( const char * pServer, for( index = 0; index < strlen( pKeyHexString ); index += 2 ) { char byteString[ 3 ] = { pKeyHexString[ index ], pKeyHexString[ index + 1 ], '\0' }; - uint8_t byteVal = strtoul( byteString, NULL, 16 ); + uint8_t byteVal = ( uint8_t ) ( strtoul( byteString, NULL, 16 ) ); pAuthContext->pAuthKey[ index / 2 ] = byteVal; } } @@ -1014,7 +1036,7 @@ static CK_RV setupPkcs11ObjectForAesCmac( const SntpAuthContext_t * pAuthContext }; /* Update the attributes array with the key of AES-CMAC operation. */ - aes_cmac_template[ 6 ].pValue = pAuthContext->pAuthKey; + aes_cmac_template[ 6 ].pValue = ( uint8_t * ) ( pAuthContext->pAuthKey ); aes_cmac_template[ 6 ].ulValueLen = sizeof( pAuthContext->pAuthKey ); result = xInitializePkcs11Session( pPkcs11Session ); @@ -1056,7 +1078,7 @@ static CK_RV setupPkcs11ObjectForAesCmac( const SntpAuthContext_t * pAuthContext SntpStatus_t addClientAuthCode( SntpAuthContext_t * pAuthContext, const SntpServerInfo_t * pTimeServer, void * pRequestBuffer, - uint16_t bufferSize, + size_t bufferSize, uint16_t * pAuthCodeSize ) { CK_RV result = CKR_OK; @@ -1279,7 +1301,7 @@ static uint32_t generateRandomNumber() if( pkcs11Status == CKR_OK ) { if( pFunctionList->C_GenerateRandom( session, - &randomNum, + ( uint8_t * ) ( &randomNum ), sizeof( randomNum ) ) != CKR_OK ) { LogError( ( "Failed to generate random number. " @@ -1304,7 +1326,7 @@ static uint32_t generateRandomNumber() void initializeSystemClock( void ) { /* On boot-up initialize the system time as the first second in the configured year. */ - int64_t startupTimeInUnixSecs = translateYearToUnixSeconds( democonfigSYSTEM_START_YEAR ); + uint32_t startupTimeInUnixSecs = translateYearToUnixSeconds( democonfigSYSTEM_START_YEAR ); systemClock.baseTime.secs = startupTimeInUnixSecs; systemClock.baseTime.msecs = 0; @@ -1429,7 +1451,6 @@ static bool createUdpSocket( Socket_t * pSocket ) static void closeUdpSocket( Socket_t * pSocket ) { bool status = false; - struct freertos_sockaddr bindAddress; configASSERT( pSocket != NULL ); @@ -1455,7 +1476,7 @@ static bool calculateBackoffForNextPoll( BackoffAlgorithmContext_t * pBackoffCon if( shouldInitializeContext == true ) { /* Initialize reconnect attempts and interval.*/ - BackoffAlgorithm_InitializeParams( &pBackoffContext, + BackoffAlgorithm_InitializeParams( pBackoffContext, minPollPeriod, SNTP_DEMO_POLL_MAX_BACKOFF_DELAY_SEC, SNTP_DEMO_MAX_SERVER_BACKOFF_RETRIES ); @@ -1463,7 +1484,7 @@ static bool calculateBackoffForNextPoll( BackoffAlgorithmContext_t * pBackoffCon /* Generate a random number and calculate the new backoff poll period to wait before the next * time poll attempt. */ - status = BackoffAlgorithm_GetNextBackoff( &pBackoffContext, generateRandomNumber(), &newPollPeriod ); + status = BackoffAlgorithm_GetNextBackoff( pBackoffContext, generateRandomNumber(), &newPollPeriod ); if( status == BackoffAlgorithmRetriesExhausted ) { diff --git a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/coreSNTP_Demo.vcxproj b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/coreSNTP_Demo.vcxproj index ac3df6b6bd4..be3afcf4d8d 100644 --- a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/coreSNTP_Demo.vcxproj +++ b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/coreSNTP_Demo.vcxproj @@ -5,18 +5,6 @@ Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -32,26 +20,6 @@ v142 Unicode - - Application - false - v142 - true - Unicode - - - Application - true - v142 - Unicode - - - Application - false - v142 - true - Unicode - @@ -60,28 +28,10 @@ - - - - - - - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\sockets_wrapper\freertos_plus_tcp;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreSNTP\source\include;$(IncludePath) - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\sockets_wrapper\freertos_plus_tcp;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreSNTP\source\include;$(IncludePath) - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\sockets_wrapper\freertos_plus_tcp;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreSNTP\source\include;$(IncludePath) - - - $(VC_IncludePath);$(WindowsSDK_IncludePath);.;..\..\Source\Application-Protocols\network_transport\sockets_wrapper\freertos_plus_tcp;..\..\Source\Application-Protocols\network_transport;..\..\Source\Utilities\backoff_algorithm\source\include;..\..\Source\Application-Protocols\coreSNTP\source\include;$(IncludePath) - false @@ -89,61 +39,7 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - false - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - false - - - Console - true - true - true - %(AdditionalDependencies) - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - - - false - - - Console - true - %(AdditionalDependencies) - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true @@ -151,8 +47,6 @@ Console - true - true true %(AdditionalDependencies) diff --git a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/core_sntp_demo.sln b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/core_sntp_demo.sln index b02339b4af7..9e3a1323de2 100644 --- a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/core_sntp_demo.sln +++ b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/core_sntp_demo.sln @@ -1,14 +1,13 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33027.164 MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreSNTP_Demo", "coreSNTP_Demo.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS-Kernel", "..\..\VisualStudio_StaticProjects\FreeRTOS-Kernel\FreeRTOS-Kernel.vcxproj", "{72C209C4-49A4-4942-A201-44706C9D77EC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "FreeRTOS+TCP", "..\..\VisualStudio_StaticProjects\FreeRTOS+TCP\FreeRTOS+TCP.vcxproj", "{C90E6CC5-818B-4C97-8876-0986D989387C}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "coreSNTP_Demo", "coreSNTP_Demo.vcxproj", "{382DC80F-E278-4BC9-9DB6-59014486DA0F}" -EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Logging", "..\..\VisualStudio_StaticProjects\Logging\Logging.vcxproj", "{BE362AC0-B10B-4276-B84E-6304652BA228}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MbedTLS", "..\..\VisualStudio_StaticProjects\MbedTLS\MbedTLS.vcxproj", "{E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}" @@ -20,59 +19,20 @@ EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|Win32.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|Win32.Build.0 = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.ActiveCfg = Debug|Win32 {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|Win32.Build.0 = Debug|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.ActiveCfg = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Debug|x64.Build.0 = Debug|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.ActiveCfg = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|Win32.Build.0 = Release|Win32 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.ActiveCfg = Release|x64 - {382DC80F-E278-4BC9-9DB6-59014486DA0F}.Release|x64.Build.0 = Release|x64 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|Win32.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|Win32.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.ActiveCfg = Debug|Win32 {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.Build.0 = Debug|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.ActiveCfg = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.Build.0 = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.ActiveCfg = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|Win32.Build.0 = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.ActiveCfg = Release|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.Build.0 = Release|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/readme.url b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/readme.url new file mode 100644 index 00000000000..c47aacb5046 --- /dev/null +++ b/FreeRTOS-Plus/Demo/coreSNTP_Windows_Simulator/readme.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/Documentation/03-Libraries/03-FreeRTOS-core/05-coreSNTP/04-coreSNTP-demo diff --git a/FreeRTOS-Plus/Source/AWS/device-defender b/FreeRTOS-Plus/Source/AWS/device-defender index 747ae050e1d..9dbf7ba0d4b 160000 --- a/FreeRTOS-Plus/Source/AWS/device-defender +++ b/FreeRTOS-Plus/Source/AWS/device-defender @@ -1 +1 @@ -Subproject commit 747ae050e1d22682c8c757fff48dba2760094505 +Subproject commit 9dbf7ba0d4bae6c8cabdb7732289942f5a23507c diff --git a/FreeRTOS-Plus/Source/AWS/device-shadow b/FreeRTOS-Plus/Source/AWS/device-shadow index 0c17830735d..2f16e7c12d9 160000 --- a/FreeRTOS-Plus/Source/AWS/device-shadow +++ b/FreeRTOS-Plus/Source/AWS/device-shadow @@ -1 +1 @@ -Subproject commit 0c17830735d83fe1e399af056820de0f4666f43c +Subproject commit 2f16e7c12d9a585d2aa9071e53ed8a346d076005 diff --git a/FreeRTOS-Plus/Source/AWS/fleet-provisioning b/FreeRTOS-Plus/Source/AWS/fleet-provisioning index 8ce2b28325e..daf174d3b93 160000 --- a/FreeRTOS-Plus/Source/AWS/fleet-provisioning +++ b/FreeRTOS-Plus/Source/AWS/fleet-provisioning @@ -1 +1 @@ -Subproject commit 8ce2b28325efb917c2e357aed2361e3fa6162ecf +Subproject commit daf174d3b934d550492e775650137b8bb1b63545 diff --git a/FreeRTOS-Plus/Source/AWS/jobs b/FreeRTOS-Plus/Source/AWS/jobs index 3e33c6a0eea..f1c3bd68298 160000 --- a/FreeRTOS-Plus/Source/AWS/jobs +++ b/FreeRTOS-Plus/Source/AWS/jobs @@ -1 +1 @@ -Subproject commit 3e33c6a0eeaebb820a445a3d4b1a02896b3e557d +Subproject commit f1c3bd68298a9c997f1709f48e61ca3f22dc8ed0 diff --git a/FreeRTOS-Plus/Source/AWS/ota b/FreeRTOS-Plus/Source/AWS/ota index 0c46d6a6f77..9a8395beaf5 160000 --- a/FreeRTOS-Plus/Source/AWS/ota +++ b/FreeRTOS-Plus/Source/AWS/ota @@ -1 +1 @@ -Subproject commit 0c46d6a6f77414ed8d8a383d1a04d93dcc7e0f5c +Subproject commit 9a8395beaf52cfe5335f9a3b760b6e6743d0991e diff --git a/FreeRTOS-Plus/Source/AWS/sigv4 b/FreeRTOS-Plus/Source/AWS/sigv4 index 1e692f74f17..9d9f95a95ac 160000 --- a/FreeRTOS-Plus/Source/AWS/sigv4 +++ b/FreeRTOS-Plus/Source/AWS/sigv4 @@ -1 +1 @@ -Subproject commit 1e692f74f17c8ab9f8332cc2af37e283660bac03 +Subproject commit 9d9f95a95acdf3e1428df803cec79e65e2da81f0 diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP b/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP index 48ccceb4bc0..dc94df08e48 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP @@ -1 +1 @@ -Subproject commit 48ccceb4bc048a36012ff33a0adbb49bc891045f +Subproject commit dc94df08e4819471b73858b863fddd50c0ca38c6 diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT b/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT index 143a15eb111..238350a8443 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT @@ -1 +1 @@ -Subproject commit 143a15eb11124903e51ab3c0bba6234fbbe23f42 +Subproject commit 238350a844336c6dea7e3aa50ecab729bf27e288 diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent b/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent index 3b743173ddc..d3668a69bff 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent @@ -1 +1 @@ -Subproject commit 3b743173ddc7ec00d3073462847db15580a56617 +Subproject commit d3668a69bff0487f8964ad1de0fea0799ffe407c diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP b/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP index 3cb8ad937f7..c5face5fa3c 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP @@ -1 +1 @@ -Subproject commit 3cb8ad937f70516cb9f08a7d622cfa9195736d3b +Subproject commit c5face5fa3cc3c37b8216c35d03d323373e89a85 diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_bio_tcp_sockets_wrapper.c b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_bio_tcp_sockets_wrapper.c index f3f577b2165..f246465502c 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_bio_tcp_sockets_wrapper.c +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_bio_tcp_sockets_wrapper.c @@ -35,6 +35,7 @@ #else #include MBEDTLS_CONFIG_FILE #endif + #include "threading_alt.h" #include "mbedtls/entropy.h" #include "mbedtls/ssl.h" diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_pk_pkcs11.c b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_pk_pkcs11.c index 373a831c5ee..b352d26aa54 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_pk_pkcs11.c +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_pk_pkcs11.c @@ -40,7 +40,22 @@ #include /* Mbedtls Includes */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS +#ifndef MBEDTLS_ALLOW_PRIVATE_ACCESS + #define MBEDTLS_ALLOW_PRIVATE_ACCESS +#endif /* MBEDTLS_ALLOW_PRIVATE_ACCESS */ + +/* MBedTLS Includes */ +#if !defined( MBEDTLS_CONFIG_FILE ) + #include "mbedtls/mbedtls_config.h" +#else + #include MBEDTLS_CONFIG_FILE +#endif + +#ifdef MBEDTLS_PSA_CRYPTO_C + /* MbedTLS PSA Includes */ + #include "psa/crypto.h" + #include "psa/crypto_values.h" +#endif /* MBEDTLS_PSA_CRYPTO_C */ #include "mbedtls/pk.h" #include "mbedtls/asn1.h" @@ -53,6 +68,9 @@ #include "core_pkcs11_config.h" #include "core_pkcs11.h" +/* PKCS11 Includes */ +#include "pkcs11t.h" + /*-----------------------------------------------------------*/ typedef struct P11PkCtx @@ -92,7 +110,7 @@ static void * p11_ecdsa_ctx_alloc( void ); * @param xPkHandle The CK_OBJECT_HANDLE for the target private key. * @return CKR_OK on success */ -static CK_RV p11_ecdsa_ctx_init( void * pvCtx, +static CK_RV p11_ecdsa_ctx_init( mbedtls_pk_context * pxMbedtlsPkCtx, CK_FUNCTION_LIST_PTR pxFunctionList, CK_SESSION_HANDLE xSessionHandle, CK_OBJECT_HANDLE xPkHandle ); @@ -119,7 +137,7 @@ static void p11_ecdsa_ctx_free( void * pvCtx ); * @return 0 on success * @return A negative number on failure */ -static int p11_ecdsa_sign( void * pvCtx, +static int p11_ecdsa_sign( mbedtls_pk_context * pk, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, @@ -135,7 +153,7 @@ static int p11_ecdsa_sign( void * pvCtx, * @param pvCtx Void pointer to the relevant P11EcDsaCtx_t. * @return size_t Bit length of the key. */ -static size_t p11_ecdsa_get_bitlen( const void * pvCtx ); +static size_t p11_ecdsa_get_bitlen( const mbedtls_pk_context * pxMbedtlsPkCtx ); /** * @brief Returns true if the pk context can perform the given pk operation. @@ -148,7 +166,7 @@ static int p11_ecdsa_can_do( mbedtls_pk_type_t xType ); /** * @brief Perform an ECDSA verify operation with the given pk context. * - * Validates that the signature given in the pucSig and xSigLen arguments + * @note Validates that the signature given in the pucSig and xSigLen arguments * matches the hash given in pucHash and xSigLen for the P11EcDsaCtx_t * specified in pvCtx. * @@ -160,7 +178,7 @@ static int p11_ecdsa_can_do( mbedtls_pk_type_t xType ); * @param xSigLen Length of the signature given in pucSig * @return 0 on success */ -static int p11_ecdsa_verify( void * pvCtx, +static int p11_ecdsa_verify( mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, @@ -168,11 +186,11 @@ static int p11_ecdsa_verify( void * pvCtx, size_t xSigLen ); static int p11_ecdsa_check_pair( const void * pvPub, - const void * pvPrv, + const mbedtls_pk_context * pxMbedtlsPkCtx, int ( * lFRng )( void *, unsigned char *, size_t ), void * pvPRng ); -static void p11_ecdsa_debug( const void * pvCtx, +static void p11_ecdsa_debug( const mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_pk_debug_item * pxItems ); static int prvEcdsaSigToASN1InPlace( unsigned char * pucSig, @@ -213,18 +231,18 @@ mbedtls_pk_info_t mbedtls_pkcs11_pk_ecdsa = /*-----------------------------------------------------------*/ -static size_t p11_rsa_get_bitlen( const void * pvCtx ); +static size_t p11_rsa_get_bitlen( const mbedtls_pk_context * ctx ); static int p11_rsa_can_do( mbedtls_pk_type_t xType ); -static int p11_rsa_verify( void * pvCtx, +static int p11_rsa_verify( mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, const unsigned char * pucSig, size_t xSigLen ); -static int p11_rsa_sign( void * ctx, +static int p11_rsa_sign( mbedtls_pk_context * pk, mbedtls_md_type_t md_alg, const unsigned char * hash, size_t hash_len, @@ -235,20 +253,20 @@ static int p11_rsa_sign( void * ctx, void * p_rng ); static int p11_rsa_check_pair( const void * pvPub, - const void * pvPrv, + const mbedtls_pk_context * pxMbedtlsPkCtx, int ( * lFRng )( void *, unsigned char *, size_t ), void * pvPRng ); static void * p11_rsa_ctx_alloc( void ); -static CK_RV p11_rsa_ctx_init( void * pvCtx, +static CK_RV p11_rsa_ctx_init( mbedtls_pk_context * pk, CK_FUNCTION_LIST_PTR pxFunctionList, CK_SESSION_HANDLE xSessionHandle, CK_OBJECT_HANDLE xPkHandle ); static void p11_rsa_ctx_free( void * pvCtx ); -static void p11_rsa_debug( const void * pvCtx, +static void p11_rsa_debug( const mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_pk_debug_item * pxItems ); /*-----------------------------------------------------------*/ @@ -422,13 +440,13 @@ static void p11_ecdsa_ctx_free( void * pvCtx ) /*-----------------------------------------------------------*/ -static CK_RV p11_ecdsa_ctx_init( void * pvCtx, +static CK_RV p11_ecdsa_ctx_init( mbedtls_pk_context * pk, CK_FUNCTION_LIST_PTR pxFunctionList, CK_SESSION_HANDLE xSessionHandle, CK_OBJECT_HANDLE xPkHandle ) { CK_RV xResult = CKR_OK; - P11EcDsaCtx_t * pxP11EcDsaCtx = ( P11EcDsaCtx_t * ) pvCtx; + P11EcDsaCtx_t * pxP11EcDsaCtx = ( P11EcDsaCtx_t * ) pk; mbedtls_ecdsa_context * pxMbedEcDsaCtx = NULL; configASSERT( pxFunctionList != NULL ); @@ -441,95 +459,98 @@ static CK_RV p11_ecdsa_ctx_init( void * pvCtx, } else { + LogError( ( "Received a NULL mbedtls_pk_context" ) ); xResult = CKR_FUNCTION_FAILED; } - /* Initialize public EC parameter data from attributes */ - - CK_ATTRIBUTE pxAttrs[ 2 ] = - { - { .type = CKA_EC_PARAMS, .ulValueLen = 0, .pValue = NULL }, - { .type = CKA_EC_POINT, .ulValueLen = 0, .pValue = NULL } - }; - - /* Determine necessary size */ - xResult = pxFunctionList->C_GetAttributeValue( xSessionHandle, - xPkHandle, - pxAttrs, - sizeof( pxAttrs ) / sizeof( CK_ATTRIBUTE ) ); - if( xResult == CKR_OK ) { - if( pxAttrs[ 0 ].ulValueLen > 0 ) + /* Initialize public EC parameter data from attributes */ + CK_ATTRIBUTE pxAttrs[ 2 ] = { - pxAttrs[ 0 ].pValue = pvPortMalloc( pxAttrs[ 0 ].ulValueLen ); - } - - if( pxAttrs[ 1 ].ulValueLen > 0 ) - { - pxAttrs[ 1 ].pValue = pvPortMalloc( pxAttrs[ 1 ].ulValueLen ); - } + { .type = CKA_EC_PARAMS, .ulValueLen = 0, .pValue = NULL }, + { .type = CKA_EC_POINT, .ulValueLen = 0, .pValue = NULL } + }; + /* Determine necessary size */ xResult = pxFunctionList->C_GetAttributeValue( xSessionHandle, xPkHandle, pxAttrs, - 2 ); - } + sizeof( pxAttrs ) / sizeof( CK_ATTRIBUTE ) ); - /* Parse EC Group */ - if( xResult == CKR_OK ) - { - /*TODO: Parse the ECParameters object */ - int lResult = mbedtls_ecp_group_load( &( pxMbedEcDsaCtx->grp ), MBEDTLS_ECP_DP_SECP256R1 ); - - if( lResult != 0 ) + if( xResult == CKR_OK ) { - xResult = CKR_FUNCTION_FAILED; + if( pxAttrs[ 0 ].ulValueLen > 0 ) + { + pxAttrs[ 0 ].pValue = pvPortMalloc( pxAttrs[ 0 ].ulValueLen ); + } + + if( pxAttrs[ 1 ].ulValueLen > 0 ) + { + pxAttrs[ 1 ].pValue = pvPortMalloc( pxAttrs[ 1 ].ulValueLen ); + } + + xResult = pxFunctionList->C_GetAttributeValue( xSessionHandle, + xPkHandle, + pxAttrs, + 2 ); } - } - /* Parse ECPoint */ - if( xResult == CKR_OK ) - { - unsigned char * pucIterator = pxAttrs[ 1 ].pValue; - size_t uxLen = pxAttrs[ 1 ].ulValueLen; - int lResult = 0; + /* Parse EC Group */ + if( xResult == CKR_OK ) + { + /*TODO: Parse the ECParameters object */ + int lResult = mbedtls_ecp_group_load( &( pxMbedEcDsaCtx->grp ), MBEDTLS_ECP_DP_SECP256R1 ); - lResult = mbedtls_asn1_get_tag( &pucIterator, &( pucIterator[ uxLen ] ), &uxLen, MBEDTLS_ASN1_OCTET_STRING ); + if( lResult != 0 ) + { + xResult = CKR_FUNCTION_FAILED; + } + } - if( lResult != 0 ) + /* Parse ECPoint */ + if( xResult == CKR_OK ) { - xResult = CKR_GENERAL_ERROR; + unsigned char * pucIterator = pxAttrs[ 1 ].pValue; + size_t uxLen = pxAttrs[ 1 ].ulValueLen; + int lResult = 0; + + lResult = mbedtls_asn1_get_tag( &pucIterator, &( pucIterator[ uxLen ] ), &uxLen, MBEDTLS_ASN1_OCTET_STRING ); + + if( lResult != 0 ) + { + xResult = CKR_GENERAL_ERROR; + } + else + { + lResult = mbedtls_ecp_point_read_binary( &( pxMbedEcDsaCtx->grp ), + &( pxMbedEcDsaCtx->Q ), + pucIterator, + uxLen ); + } + + if( lResult != 0 ) + { + xResult = CKR_GENERAL_ERROR; + } } - else + + if( pxAttrs[ 0 ].pValue != NULL ) { - lResult = mbedtls_ecp_point_read_binary( &( pxMbedEcDsaCtx->grp ), - &( pxMbedEcDsaCtx->Q ), - pucIterator, - uxLen ); + vPortFree( pxAttrs[ 0 ].pValue ); } - if( lResult != 0 ) + if( pxAttrs[ 1 ].pValue != NULL ) { - xResult = CKR_GENERAL_ERROR; + vPortFree( pxAttrs[ 1 ].pValue ); } - } - - if( pxAttrs[ 0 ].pValue != NULL ) - { - vPortFree( pxAttrs[ 0 ].pValue ); - } - - if( pxAttrs[ 1 ].pValue != NULL ) - { - vPortFree( pxAttrs[ 1 ].pValue ); - } - if( xResult == CKR_OK ) - { - pxP11EcDsaCtx->xP11PkCtx.pxFunctionList = pxFunctionList; - pxP11EcDsaCtx->xP11PkCtx.xSessionHandle = xSessionHandle; - pxP11EcDsaCtx->xP11PkCtx.xPkHandle = xPkHandle; + if( xResult == CKR_OK ) + { + pxP11EcDsaCtx->xP11PkCtx.pxFunctionList = pxFunctionList; + pxP11EcDsaCtx->xP11PkCtx.xSessionHandle = xSessionHandle; + pxP11EcDsaCtx->xP11PkCtx.xPkHandle = xPkHandle; + } } return xResult; @@ -656,7 +677,7 @@ static int prvEcdsaSigToASN1InPlace( unsigned char * pucSig, /*-----------------------------------------------------------*/ -static int p11_ecdsa_sign( void * pvCtx, +static int p11_ecdsa_sign( mbedtls_pk_context * pk, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, @@ -668,7 +689,7 @@ static int p11_ecdsa_sign( void * pvCtx, { CK_RV xResult = CKR_OK; int32_t lFinalResult = 0; - const P11EcDsaCtx_t * pxEcDsaCtx = NULL; + const P11EcDsaCtx_t * pxEcDsaCtx = ( P11EcDsaCtx_t * ) pk->pk_ctx; const P11PkCtx_t * pxP11Ctx = NULL; unsigned char pucHashCopy[ MBEDTLS_MD_MAX_SIZE ]; @@ -690,9 +711,8 @@ static int p11_ecdsa_sign( void * pvCtx, configASSERT( pucHash != NULL ); configASSERT( xHashLen > 0 ); - if( pvCtx != NULL ) + if( pxEcDsaCtx != NULL ) { - pxEcDsaCtx = ( P11EcDsaCtx_t * ) pvCtx; pxP11Ctx = &( pxEcDsaCtx->xP11PkCtx ); } else @@ -739,13 +759,11 @@ static int p11_ecdsa_sign( void * pvCtx, /*-----------------------------------------------------------*/ -static size_t p11_ecdsa_get_bitlen( const void * pvCtx ) +static size_t p11_ecdsa_get_bitlen( const mbedtls_pk_context * pxMbedtlsPkCtx ) { - P11EcDsaCtx_t * pxEcDsaCtx = ( P11EcDsaCtx_t * ) pvCtx; - configASSERT( mbedtls_ecdsa_info.get_bitlen ); - return mbedtls_ecdsa_info.get_bitlen( &( pxEcDsaCtx->xMbedEcDsaCtx ) ); + return mbedtls_ecdsa_info.get_bitlen( ( mbedtls_pk_context * ) pxMbedtlsPkCtx ); } /*-----------------------------------------------------------*/ @@ -757,18 +775,16 @@ static int p11_ecdsa_can_do( mbedtls_pk_type_t xType ) /*-----------------------------------------------------------*/ -static int p11_ecdsa_verify( void * pvCtx, +static int p11_ecdsa_verify( mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, const unsigned char * pucSig, size_t xSigLen ) { - P11EcDsaCtx_t * pxEcDsaCtx = ( P11EcDsaCtx_t * ) pvCtx; - configASSERT( mbedtls_ecdsa_info.verify_func ); - return mbedtls_ecdsa_info.verify_func( &( pxEcDsaCtx->xMbedEcDsaCtx ), + return mbedtls_ecdsa_info.verify_func( pxMbedtlsPkCtx, xMdAlg, pucHash, xHashLen, pucSig, xSigLen ); @@ -777,14 +793,15 @@ static int p11_ecdsa_verify( void * pvCtx, /*-----------------------------------------------------------*/ static int p11_ecdsa_check_pair( const void * pvPub, - const void * pvPrv, + const mbedtls_pk_context * pxMbedtlsPkCtx, int ( * lFRng )( void *, unsigned char *, size_t ), void * pvPRng ) { + P11EcDsaCtx_t * pxP11PrvKey = ( P11EcDsaCtx_t * ) pxMbedtlsPkCtx->pk_ctx; + mbedtls_ecp_keypair * pxPubKey = ( mbedtls_ecp_keypair * ) pvPub; - mbedtls_ecp_keypair * pxPrvKey = ( mbedtls_ecp_keypair * ) pvPrv; + mbedtls_ecp_keypair * pxPrvKey = &( pxP11PrvKey->xMbedEcDsaCtx ); - P11EcDsaCtx_t * pxP11PrvKey = ( P11EcDsaCtx_t * ) pvPrv; int lResult = 0; ( void ) lFRng; @@ -832,7 +849,7 @@ static int p11_ecdsa_check_pair( const void * pvPub, }; unsigned char pucTestSignature[ MBEDTLS_ECDSA_MAX_SIG_LEN( 256 ) ] = { 0 }; size_t uxSigLen = 0; - lResult = p11_ecdsa_sign( ( void * ) ( void * ) pvPrv, MBEDTLS_MD_SHA256, + lResult = p11_ecdsa_sign( ( mbedtls_pk_context * ) pxMbedtlsPkCtx, MBEDTLS_MD_SHA256, pucTestHash, sizeof( pucTestHash ), pucTestSignature, sizeof( pucTestSignature ), &uxSigLen, NULL, NULL ); @@ -850,48 +867,44 @@ static int p11_ecdsa_check_pair( const void * pvPub, /*-----------------------------------------------------------*/ -static void p11_ecdsa_debug( const void * pvCtx, +static void p11_ecdsa_debug( const mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_pk_debug_item * pxItems ) { - P11EcDsaCtx_t * pxEcDsaCtx = ( P11EcDsaCtx_t * ) pvCtx; - configASSERT( mbedtls_ecdsa_info.debug_func ); - mbedtls_ecdsa_info.debug_func( &( pxEcDsaCtx->xMbedEcDsaCtx ), pxItems ); + mbedtls_ecdsa_info.debug_func( ( mbedtls_pk_context * ) pxMbedtlsPkCtx, pxItems ); } /*-----------------------------------------------------------*/ -static size_t p11_rsa_get_bitlen( const void * pvCtx ) +static size_t p11_rsa_get_bitlen( const mbedtls_pk_context * pxMbedtlsPkCtx ) { - P11RsaCtx_t * pxRsaCtx = ( P11RsaCtx_t * ) pvCtx; + mbedtls_rsa_context * pxRsaCtx = ( mbedtls_rsa_context * ) pxMbedtlsPkCtx->pk_ctx; configASSERT( mbedtls_rsa_info.get_bitlen ); - return mbedtls_rsa_info.get_bitlen( &( pxRsaCtx->xMbedRsaCtx ) ); + return mbedtls_rsa_info.get_bitlen( ( mbedtls_pk_context * ) pxMbedtlsPkCtx ); } /*-----------------------------------------------------------*/ static int p11_rsa_can_do( mbedtls_pk_type_t xType ) { - return( xType == MBEDTLS_PK_RSA ); + return( ( xType == MBEDTLS_PK_RSA ) || ( xType == MBEDTLS_PK_RSASSA_PSS ) ); } /*-----------------------------------------------------------*/ -static int p11_rsa_verify( void * pvCtx, +static int p11_rsa_verify( mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, const unsigned char * pucSig, size_t xSigLen ) { - P11RsaCtx_t * pxRsaCtx = ( P11RsaCtx_t * ) pvCtx; - configASSERT( mbedtls_rsa_info.verify_func ); - return mbedtls_rsa_info.verify_func( &( pxRsaCtx->xMbedRsaCtx ), + return mbedtls_rsa_info.verify_func( pxMbedtlsPkCtx, xMdAlg, pucHash, xHashLen, pucSig, xSigLen ); @@ -899,7 +912,7 @@ static int p11_rsa_verify( void * pvCtx, /*-----------------------------------------------------------*/ -static int p11_rsa_sign( void * pvCtx, +static int p11_rsa_sign( mbedtls_pk_context * pk, mbedtls_md_type_t xMdAlg, const unsigned char * pucHash, size_t xHashLen, @@ -942,9 +955,9 @@ static int p11_rsa_sign( void * pvCtx, { xResult = CKR_ARGUMENTS_BAD; } - else if( pvCtx != NULL ) + else if( pk != NULL ) { - pxP11RsaCtx = ( P11RsaCtx_t * ) pvCtx; + pxP11RsaCtx = ( P11RsaCtx_t * ) pk->pk_ctx; pxP11Ctx = &( pxP11RsaCtx->xP11PkCtx ); } else @@ -990,16 +1003,16 @@ static int p11_rsa_sign( void * pvCtx, /*-----------------------------------------------------------*/ static int p11_rsa_check_pair( const void * pvPub, - const void * pvPrv, + const mbedtls_pk_context * pxMbedtlsPkCtx, int ( * lFRng )( void *, unsigned char *, size_t ), void * pvPRng ) { - P11RsaCtx_t * pxP11RsaCtx = ( P11RsaCtx_t * ) pvPrv; - configASSERT( mbedtls_rsa_info.check_pair_func ); - return mbedtls_rsa_info.check_pair_func( pvPub, &( pxP11RsaCtx->xMbedRsaCtx ), - lFRng, pvPRng ); + return mbedtls_rsa_info.check_pair_func( ( void * ) pvPub, + ( mbedtls_pk_context * ) pxMbedtlsPkCtx, + lFRng, + pvPRng ); } /*-----------------------------------------------------------*/ @@ -1012,14 +1025,14 @@ static void * p11_rsa_ctx_alloc( void ) if( pvCtx != NULL ) { - P11RsaCtx_t * pxP11Rsa = ( P11RsaCtx_t * ) pvCtx; + P11RsaCtx_t * pxRsaCtx = ( P11RsaCtx_t * ) pvCtx; /* Initialize other fields */ - pxP11Rsa->xP11PkCtx.pxFunctionList = NULL; - pxP11Rsa->xP11PkCtx.xSessionHandle = CK_INVALID_HANDLE; - pxP11Rsa->xP11PkCtx.xPkHandle = CK_INVALID_HANDLE; + pxRsaCtx->xP11PkCtx.pxFunctionList = NULL; + pxRsaCtx->xP11PkCtx.xSessionHandle = CK_INVALID_HANDLE; + pxRsaCtx->xP11PkCtx.xPkHandle = CK_INVALID_HANDLE; - mbedtls_rsa_init( &( pxP11Rsa->xMbedRsaCtx ) ); + mbedtls_rsa_init( &( pxRsaCtx->xMbedRsaCtx ) ); } return pvCtx; @@ -1027,13 +1040,13 @@ static void * p11_rsa_ctx_alloc( void ) /*-----------------------------------------------------------*/ -static CK_RV p11_rsa_ctx_init( void * pvCtx, +static CK_RV p11_rsa_ctx_init( mbedtls_pk_context * pk, CK_FUNCTION_LIST_PTR pxFunctionList, CK_SESSION_HANDLE xSessionHandle, CK_OBJECT_HANDLE xPkHandle ) { CK_RV xResult = CKR_OK; - P11RsaCtx_t * pxP11RsaCtx = ( P11RsaCtx_t * ) pvCtx; + P11RsaCtx_t * pxP11RsaCtx = ( P11RsaCtx_t * ) pk; mbedtls_rsa_context * pxMbedRsaCtx = NULL; configASSERT( pxFunctionList != NULL ); @@ -1049,24 +1062,22 @@ static CK_RV p11_rsa_ctx_init( void * pvCtx, xResult = CKR_FUNCTION_FAILED; } - /* - * TODO: corePKCS11 does not allow exporting RSA public attributes. - * This function should be updated to properly initialize the - * mbedtls_rsa_context when this is addressed. - */ - - /* CK_ATTRIBUTE pxAttrs[ 2 ] = */ - /* { */ - /* { .type = CKA_MODULUS, .ulValueLen = 0, .pValue = NULL }, */ - /* { .type = CKA_PUBLIC_EXPONENT, .ulValueLen = 0, .pValue = NULL }, */ - /* { .type = CKA_PRIME_1, .ulValueLen = 0, .pValue = NULL }, */ - /* { .type = CKA_PRIME_2, .ulValueLen = 0, .pValue = NULL }, */ - /* { .type = CKA_EXPONENT_1, .ulValueLen = 0, .pValue = NULL }, */ - /* { .type = CKA_EXPONENT_2, .ulValueLen = 0, .pValue = NULL }, */ - /* { .type = CKA_COEFFICIENT, .ulValueLen = 0, .pValue = NULL }, */ - /* }; */ - - ( void ) pxMbedRsaCtx; + CK_ATTRIBUTE pxAttrs[ 8 ] = + { + { .type = CKA_MODULUS, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->N ) }, + { .type = CKA_PUBLIC_EXPONENT, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->E ) }, + { .type = CKA_PRIME_1, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->P ) }, + { .type = CKA_PRIME_2, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->Q ) }, + { .type = CKA_PRIVATE_EXPONENT, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->D ) }, + { .type = CKA_EXPONENT_1, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->DP ) }, + { .type = CKA_EXPONENT_2, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->DQ ) }, + { .type = CKA_COEFFICIENT, .ulValueLen = sizeof( mbedtls_mpi ), .pValue = &( pxMbedRsaCtx->QP ) }, + }; + + xResult = pxFunctionList->C_GetAttributeValue( xSessionHandle, + xPkHandle, + pxAttrs, + sizeof( pxAttrs ) / sizeof( CK_ATTRIBUTE ) ); if( xResult == CKR_OK ) { @@ -1094,14 +1105,12 @@ static void p11_rsa_ctx_free( void * pvCtx ) /*-----------------------------------------------------------*/ -static void p11_rsa_debug( const void * pvCtx, +static void p11_rsa_debug( const mbedtls_pk_context * pxMbedtlsPkCtx, mbedtls_pk_debug_item * pxItems ) { - P11RsaCtx_t * pxP11RsaCtx = ( P11RsaCtx_t * ) pvCtx; - configASSERT( mbedtls_rsa_info.debug_func ); - mbedtls_rsa_info.debug_func( &( pxP11RsaCtx->xMbedRsaCtx ), pxItems ); + mbedtls_rsa_info.debug_func( ( mbedtls_pk_context * ) pxMbedtlsPkCtx, pxItems ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_rng_pkcs11.c b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_rng_pkcs11.c index 04e877f73db..5dbb1beac71 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_rng_pkcs11.c +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/mbedtls_rng_pkcs11.c @@ -26,8 +26,13 @@ #include "logging_levels.h" -#define LIBRARY_LOG_NAME "MbedTLSRNGP11" -#define LIBRARY_LOG_LEVEL LOG_ERROR +#ifndef LIBRARY_LOG_NAME + #define LIBRARY_LOG_NAME "MbedTLSRNGP11" +#endif /* LIBRARY_LOG_NAME */ + +#ifndef LIBRARY_LOG_LEVEL + #define LIBRARY_LOG_LEVEL LOG_ERROR +#endif /* LIBRARY_LOG_LEVEL */ #include "logging_stack.h" diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.c b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.c index 0b8008e34c8..a0798e9e444 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.c +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.c @@ -25,15 +25,20 @@ */ /** - * @file tls_freertos.c + * @file transport_mbedtls.c * @brief TLS transport interface implementations. This implementation uses * mbedTLS. */ #include "logging_levels.h" -#define LIBRARY_LOG_NAME "MbedtlsTransport" -#define LIBRARY_LOG_LEVEL LOG_INFO +#ifndef LIBRARY_LOG_NAME + #define LIBRARY_LOG_NAME "MbedtlsTransport" +#endif /* LIBRARY_LOG_NAME */ + +#ifndef LIBRARY_LOG_LEVEL + #define LIBRARY_LOG_LEVEL LOG_INFO +#endif /* LIBRARY_LOG_LEVEL*/ #include "logging_stack.h" @@ -43,7 +48,24 @@ /* FreeRTOS includes. */ #include "FreeRTOS.h" -/* MbedTLS Bio TCP sockets wrapper include. */ +/* MBedTLS Includes */ +#if !defined( MBEDTLS_CONFIG_FILE ) + #include "mbedtls/mbedtls_config.h" +#else + #include MBEDTLS_CONFIG_FILE +#endif + +#ifdef MBEDTLS_PSA_CRYPTO_C + /* MbedTLS PSA Includes */ + #include "psa/crypto.h" + #include "psa/crypto_values.h" +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +#ifdef MBEDTLS_DEBUG_C + #include "mbedtls/debug.h" +#endif /* MBEDTLS_DEBUG_C */ + +/* MBedTLS Bio TCP sockets wrapper include. */ #include "mbedtls_bio_tcp_sockets_wrapper.h" /* TLS transport header. */ @@ -219,6 +241,22 @@ static TlsTransportStatus_t initMbedtls( mbedtls_entropy_context * pEntropyConte /*-----------------------------------------------------------*/ +#ifdef MBEDTLS_DEBUG_C + void mbedtls_string_printf( void * sslContext, + int level, + const char * file, + int line, + const char * str ) + { + if( ( str != NULL ) && ( file != NULL ) ) + { + LogDebug( ( "%s:%d: [%d] %s", file, line, level, str ) ); + } + } +#endif /* MBEDTLS_DEBUG_C */ + +/*-----------------------------------------------------------*/ + static void sslContextInit( SSLContext_t * pSslContext ) { configASSERT( pSslContext != NULL ); @@ -228,6 +266,12 @@ static void sslContextInit( SSLContext_t * pSslContext ) mbedtls_pk_init( &( pSslContext->privKey ) ); mbedtls_x509_crt_init( &( pSslContext->clientCert ) ); mbedtls_ssl_init( &( pSslContext->context ) ); + #ifdef MBEDTLS_DEBUG_C + mbedtls_debug_set_threshold( LIBRARY_LOG_LEVEL + 1U ); + mbedtls_ssl_conf_dbg( &( pSslContext->config ), + mbedtls_string_printf, + NULL ); + #endif /* MBEDTLS_DEBUG_C */ } /*-----------------------------------------------------------*/ @@ -597,6 +641,19 @@ static TlsTransportStatus_t initMbedtls( mbedtls_entropy_context * pEntropyConte returnStatus = TLS_TRANSPORT_INTERNAL_ERROR; } + #ifdef MBEDTLS_PSA_CRYPTO_C + if( returnStatus == TLS_TRANSPORT_SUCCESS ) + { + mbedtlsError = psa_crypto_init(); + + if( mbedtlsError != PSA_SUCCESS ) + { + LogError( ( "Failed to initialize PSA Crypto implementation: %s", ( int ) mbedtlsError ) ); + returnStatus = TLS_TRANSPORT_INTERNAL_ERROR; + } + } + #endif /* MBEDTLS_PSA_CRYPTO_C */ + if( returnStatus == TLS_TRANSPORT_SUCCESS ) { /* Seed the random number generator. */ @@ -809,8 +866,14 @@ int32_t TLS_FreeRTOS_recv( NetworkContext_t * pNetworkContext, if( ( tlsStatus == MBEDTLS_ERR_SSL_TIMEOUT ) || ( tlsStatus == MBEDTLS_ERR_SSL_WANT_READ ) || - ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) ) + ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) || + ( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) ) { + if( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) + { + LogDebug( ( "Received a MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET return code from mbedtls_ssl_read." ) ); + } + LogDebug( ( "Failed to read data. However, a read can be retried on this error. " "mbedTLSError= %s : %s.", mbedtlsHighLevelCodeOrDefault( tlsStatus ), @@ -868,8 +931,14 @@ int32_t TLS_FreeRTOS_send( NetworkContext_t * pNetworkContext, if( ( tlsStatus == MBEDTLS_ERR_SSL_TIMEOUT ) || ( tlsStatus == MBEDTLS_ERR_SSL_WANT_READ ) || - ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) ) + ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) || + ( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) ) { + if( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) + { + LogDebug( ( "Received a MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET return code from mbedtls_ssl_write." ) ); + } + LogDebug( ( "Failed to send data. However, send can be retried on this error. " "mbedTLSError= %s : %s.", mbedtlsHighLevelCodeOrDefault( tlsStatus ), diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.h b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.h index 99e1b66e359..f2f1931709a 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.h +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls.h @@ -32,6 +32,22 @@ #ifndef USING_MBEDTLS #define USING_MBEDTLS +/* MBed TLS includes. */ +#if !defined( MBEDTLS_CONFIG_FILE ) + #include "mbedtls/mbedtls_config.h" +#else + #include MBEDTLS_CONFIG_FILE +#endif + +#include "mbedtls/build_info.h" +#include "mbedtls/ctr_drbg.h" +#include "mbedtls/entropy.h" +#include "mbedtls/ssl.h" +#include "mbedtls/threading.h" +#include "mbedtls/x509.h" +#include "mbedtls/error.h" + + /**************************************************/ /******* DO NOT CHANGE the following order ********/ /**************************************************/ @@ -53,9 +69,10 @@ #define LIBRARY_LOG_LEVEL LOG_ERROR #endif -/* Prototype for the function used to print to console on Windows simulator - * of FreeRTOS. - * The function prints to the console before the network is connected; +/** @brief Prototype for the function used to print to console on Windows + * simulator of FreeRTOS. + * + * @note The function prints to the console before the network is connected; * then a UDP port after the network has connected. */ extern void vLoggingPrintf( const char * pcFormatString, ... ); @@ -76,15 +93,6 @@ extern void vLoggingPrintf( const char * pcFormatString, /* Transport interface include. */ #include "transport_interface.h" -/* mbed TLS includes. */ -#include "mbedtls/ctr_drbg.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ssl.h" -#include "mbedtls/threading.h" -#include "mbedtls/x509.h" -#include "mbedtls/error.h" -#include "mbedtls/build_info.h" - /** * @brief Secured connection context. */ @@ -183,7 +191,7 @@ void TLS_FreeRTOS_Disconnect( NetworkContext_t * pNetworkContext ); /** * @brief Receives data from an established TLS connection. * - * This is the TLS version of the transport interface's + * @note This is the TLS version of the transport interface's * #TransportRecv_t function. * * @param[in] pNetworkContext The Network context. @@ -201,7 +209,7 @@ int32_t TLS_FreeRTOS_recv( NetworkContext_t * pNetworkContext, /** * @brief Sends data over an established TLS connection. * - * This is the TLS version of the transport interface's + * @note This is the TLS version of the transport interface's * #TransportSend_t function. * * @param[in] pNetworkContext The network context. @@ -216,4 +224,25 @@ int32_t TLS_FreeRTOS_send( NetworkContext_t * pNetworkContext, const void * pBuffer, size_t bytesToSend ); + +#ifdef MBEDTLS_DEBUG_C + +/** + * @brief Write an MBedTLS Debug message to the LogDebug() function + * + * @param[in] sslContext Pointer of the SSL Context that is being used + * @param[in] level The severity level of the debug message from MBedTLS + * @param[in] file Name of the file that the debug message is from + * @param[in] line The line number that the debug message is from + * @param[in] str The full string debug message from MBedTLS + * + * @return void + */ + void mbedtls_string_printf( void * sslContext, + int level, + const char * file, + int line, + const char * str ); +#endif /* MBEDTLS_DEBUG_C */ + #endif /* ifndef USING_MBEDTLS */ diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.c b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.c index 01342eb0cde..10d826c6570 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.c +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.c @@ -30,19 +30,38 @@ * mbedTLS. */ +/* Standard includes. */ +#include + #include "logging_levels.h" -#define LIBRARY_LOG_NAME "PkcsTlsTransport" -#define LIBRARY_LOG_LEVEL LOG_INFO +#define LIBRARY_LOG_NAME "PkcsTlsTransport" + +#ifndef LIBRARY_LOG_LEVEL + #define LIBRARY_LOG_LEVEL LOG_INFO +#endif /* LIBRARY_LOG_LEVEL */ #include "logging_stack.h" -#define MBEDTLS_ALLOW_PRIVATE_ACCESS +#ifndef MBEDTLS_ALLOW_PRIVATE_ACCESS + #define MBEDTLS_ALLOW_PRIVATE_ACCESS + #include "mbedtls/private_access.h" +#endif /* MBEDTLS_ALLOW_PRIVATE_ACCESS */ -#include "mbedtls/private_access.h" +/* MBedTLS Includes */ +#if !defined( MBEDTLS_CONFIG_FILE ) + #include "mbedtls/mbedtls_config.h" +#else + #include MBEDTLS_CONFIG_FILE +#endif -/* Standard includes. */ -#include +#ifdef MBEDTLS_PSA_CRYPTO_C + /* MbedTLS PSA Includes */ + #include "psa/crypto.h" + #include "psa/crypto_values.h" +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +#include "mbedtls/debug.h" /* FreeRTOS includes. */ #include "FreeRTOS.h" @@ -205,6 +224,22 @@ static int32_t privateKeySigningCallback( void * pvContext, void * pvRng ); +/*-----------------------------------------------------------*/ + +#ifdef MBEDTLS_DEBUG_C + void mbedtls_string_printf( void * sslContext, + int level, + const char * file, + int line, + const char * str ) + { + if( ( str != NULL ) && ( file != NULL ) ) + { + LogDebug( ( "%s:%d: [%d] %s", file, line, level, str ) ); + } + } +#endif /* MBEDTLS_DEBUG_C */ + /*-----------------------------------------------------------*/ static void sslContextInit( SSLContext_t * pSslContext ) @@ -215,6 +250,12 @@ static void sslContextInit( SSLContext_t * pSslContext ) mbedtls_x509_crt_init( &( pSslContext->rootCa ) ); mbedtls_x509_crt_init( &( pSslContext->clientCert ) ); mbedtls_ssl_init( &( pSslContext->context ) ); + #ifdef MBEDTLS_DEBUG_C + mbedtls_debug_set_threshold( LIBRARY_LOG_LEVEL + 1U ); + mbedtls_ssl_conf_dbg( &( pSslContext->config ), + mbedtls_string_printf, + NULL ); + #endif /* MBEDTLS_DEBUG_C */ xInitializePkcs11Session( &( pSslContext->xP11Session ) ); C_GetFunctionList( &( pSslContext->pxP11FunctionList ) ); @@ -274,6 +315,20 @@ static TlsTransportStatus_t tlsSetup( NetworkContext_t * pNetworkContext, returnStatus = TLS_TRANSPORT_INSUFFICIENT_MEMORY; } + #ifdef MBEDTLS_PSA_CRYPTO_C + mbedtlsError = psa_crypto_init(); + + if( mbedtlsError != PSA_SUCCESS ) + { + LogError( ( "Failed to initialize PSA Crypto implementation: %s", ( int ) mbedtlsError ) ); + returnStatus = TLS_TRANSPORT_INVALID_PARAMETER; + } + else + { + LogDebug( ( "Initialized the PSA Crypto Engine" ) ); + } + #endif /* MBEDTLS_PSA_CRYPTO_C */ + if( returnStatus == TLS_TRANSPORT_SUCCESS ) { /* Set up the certificate security profile, starting from the default value. */ @@ -448,15 +503,23 @@ static TlsTransportStatus_t tlsSetup( NetworkContext_t * pNetworkContext, { mbedtlsError = mbedtls_ssl_handshake( &( pTlsTransportParams->sslContext.context ) ); } while( ( mbedtlsError == MBEDTLS_ERR_SSL_WANT_READ ) || - ( mbedtlsError == MBEDTLS_ERR_SSL_WANT_WRITE ) ); + ( mbedtlsError == MBEDTLS_ERR_SSL_WANT_WRITE ) || + ( mbedtlsError == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) ); if( mbedtlsError != 0 ) { - LogError( ( "Failed to perform TLS handshake: mbedTLSError= %s : %s.", - mbedtlsHighLevelCodeOrDefault( mbedtlsError ), - mbedtlsLowLevelCodeOrDefault( mbedtlsError ) ) ); + if( mbedtlsError == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) + { + LogDebug( ( "Received a MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET return code from mbedtls_ssl_handshake." ) ); + } + else + { + LogError( ( "Failed to perform TLS handshake: mbedTLSError= %s : %s.", + mbedtlsHighLevelCodeOrDefault( mbedtlsError ), + mbedtlsLowLevelCodeOrDefault( mbedtlsError ) ) ); - returnStatus = TLS_TRANSPORT_HANDSHAKE_FAILED; + returnStatus = TLS_TRANSPORT_HANDSHAKE_FAILED; + } } } @@ -506,7 +569,7 @@ static CK_RV readCertificateIntoContext( SSLContext_t * pSslContext, /* Get the handle of the certificate. */ xResult = xFindObjectWithLabelAndClass( pSslContext->xP11Session, - pcLabelName, + ( char * ) pcLabelName, strnlen( pcLabelName, pkcs11configMAX_LABEL_LENGTH ), xClass, @@ -580,7 +643,6 @@ static CK_RV initializeClientKeys( SSLContext_t * pxCtx, CK_RV xResult = CKR_OK; CK_SLOT_ID * pxSlotIds = NULL; CK_ULONG xCount = 0; - CK_ATTRIBUTE xTemplate[ 2 ]; mbedtls_pk_type_t xKeyAlgo = ( mbedtls_pk_type_t ) ~0; /* Get the PKCS #11 module/token slot count. */ @@ -623,7 +685,7 @@ static CK_RV initializeClientKeys( SSLContext_t * pxCtx, { /* Get the handle of the device private key. */ xResult = xFindObjectWithLabelAndClass( pxCtx->xP11Session, - pcLabelName, + ( char * ) pcLabelName, strnlen( pcLabelName, pkcs11configMAX_LABEL_LENGTH ), CKO_PRIVATE_KEY, @@ -633,7 +695,7 @@ static CK_RV initializeClientKeys( SSLContext_t * pxCtx, if( ( CKR_OK == xResult ) && ( pxCtx->xP11PrivateKey == CK_INVALID_HANDLE ) ) { xResult = CK_INVALID_HANDLE; - LogError( ( "Could not find private key." ) ); + LogError( ( "Could not find private key: %s", pcLabelName ) ); } if( xResult == CKR_OK ) @@ -808,8 +870,14 @@ int32_t TLS_FreeRTOS_recv( NetworkContext_t * pNetworkContext, if( ( tlsStatus == MBEDTLS_ERR_SSL_TIMEOUT ) || ( tlsStatus == MBEDTLS_ERR_SSL_WANT_READ ) || - ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) ) + ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) || + ( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) ) { + if( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) + { + LogDebug( ( "Received a MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET return code from mbedtls_ssl_read." ) ); + } + LogDebug( ( "Failed to read data. However, a read can be retried on this error. " "mbedTLSError= %s : %s.", mbedtlsHighLevelCodeOrDefault( tlsStatus ), @@ -867,8 +935,14 @@ int32_t TLS_FreeRTOS_send( NetworkContext_t * pNetworkContext, if( ( tlsStatus == MBEDTLS_ERR_SSL_TIMEOUT ) || ( tlsStatus == MBEDTLS_ERR_SSL_WANT_READ ) || - ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) ) + ( tlsStatus == MBEDTLS_ERR_SSL_WANT_WRITE ) || + ( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) ) { + if( tlsStatus == MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET ) + { + LogDebug( ( "Received a MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET return code from mbedtls_ssl_write." ) ); + } + LogDebug( ( "Failed to send data. However, send can be retried on this error. " "mbedTLSError= %s : %s.", mbedtlsHighLevelCodeOrDefault( tlsStatus ), diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.h b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.h index 27d1b094829..1c4fe54d2e4 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.h +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_mbedtls_pkcs11.h @@ -37,6 +37,12 @@ #define MBEDTLS_ALLOW_PRIVATE_ACCESS +#if !defined( MBEDTLS_CONFIG_FILE ) + #include "mbedtls/mbedtls_config.h" +#else + #include MBEDTLS_CONFIG_FILE +#endif + #include "mbedtls/private_access.h" /* TCP Sockets Wrapper include.*/ @@ -46,6 +52,7 @@ #include "transport_interface.h" /* mbed TLS includes. */ +#include "mbedtls/build_info.h" #include "mbedtls/ctr_drbg.h" #include "mbedtls/entropy.h" #include "mbedtls/ssl.h" @@ -181,7 +188,7 @@ int32_t TLS_FreeRTOS_recv( NetworkContext_t * pNetworkContext, /** * @brief Sends data over an established TLS connection. * - * This is the TLS version of the transport interface's + * @note This is the TLS version of the transport interface's * #TransportSend_t function. * * @param[in] pNetworkContext The network context. @@ -196,4 +203,25 @@ int32_t TLS_FreeRTOS_send( NetworkContext_t * pNetworkContext, const void * pBuffer, size_t bytesToSend ); + +#ifdef MBEDTLS_DEBUG_C + +/** + * @brief Write an MBedTLS Debug message to the LogDebug() function + * + * @param[in] sslContext Pointer of the SSL Context that is being used + * @param[in] level The severity level of the debug message from MBedTLS + * @param[in] file Name of the file that the debug message is from + * @param[in] line The line number that the debug message is from + * @param[in] str The full string debug message from MBedTLS + * + * @return void + */ + void mbedtls_string_printf( void * sslContext, + int level, + const char * file, + int line, + const char * str ); +#endif /* MBEDTLS_DEBUG_C */ + #endif /* ifndef TRANSPORT_MBEDTLS_PKCS11 */ diff --git a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_wolfSSL.c b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_wolfSSL.c index 847dcf0382d..d5d70da1098 100644 --- a/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_wolfSSL.c +++ b/FreeRTOS-Plus/Source/Application-Protocols/network_transport/transport_wolfSSL.c @@ -143,11 +143,11 @@ static int wolfSSL_IORecvGlue( WOLFSSL * ssl, read = TCP_Sockets_Recv( xSocket, ( void * ) buf, ( size_t ) sz ); if( ( read == 0 ) || - ( read == -TCP_SOCKETS_ERRNO_EWOULDBLOCK ) ) + ( read == TCP_SOCKETS_ERRNO_EWOULDBLOCK ) ) { read = WOLFSSL_CBIO_ERR_WANT_READ; } - else if( read == -TCP_SOCKETS_ERRNO_ENOTCONN ) + else if( read == TCP_SOCKETS_ERRNO_ENOTCONN ) { read = WOLFSSL_CBIO_ERR_CONN_CLOSE; } @@ -169,11 +169,11 @@ static int wolfSSL_IOSendGlue( WOLFSSL * ssl, Socket_t xSocket = ( Socket_t ) context; BaseType_t sent = TCP_Sockets_Send( xSocket, ( void * ) buf, ( size_t ) sz ); - if( sent == -TCP_SOCKETS_ERRNO_EWOULDBLOCK ) + if( sent == TCP_SOCKETS_ERRNO_EWOULDBLOCK ) { sent = WOLFSSL_CBIO_ERR_WANT_WRITE; } - else if( sent == -TCP_SOCKETS_ERRNO_ENOTCONN ) + else if( sent == TCP_SOCKETS_ERRNO_ENOTCONN ) { sent = WOLFSSL_CBIO_ERR_CONN_CLOSE; } diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface index e5862bdaf6b..f1097fb3b1c 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface +++ b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface @@ -1 +1 @@ -Subproject commit e5862bdaf6b643840491af8ffeb0a0a366eff665 +Subproject commit f1097fb3b1c69120a0a0541c6a858830b3f4e762 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/bg96 b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/bg96 index c33a3628e01..f61fc4c9b23 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/bg96 +++ b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/bg96 @@ -1 +1 @@ -Subproject commit c33a3628e015f88df24b21160ba9dbdabc781da1 +Subproject commit f61fc4c9b23668a72868c02f7e77829037e4d7f2 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/hl7802 b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/hl7802 index 6893670f0f4..7d6393a00a0 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/hl7802 +++ b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/hl7802 @@ -1 +1 @@ -Subproject commit 6893670f0f4a46c459b2b6e9e4381c53fc92b1b0 +Subproject commit 7d6393a00a0dc64cbaa6cf360c9f01552e34a966 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/sara-r4 b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/sara-r4 index a2d84ffe95e..dcdae990a19 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/sara-r4 +++ b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/sara-r4 @@ -1 +1 @@ -Subproject commit a2d84ffe95e5eea0f98e53c305b7cef38b3ff6b6 +Subproject commit dcdae990a197c80a49450d801aeeec72863d9da9 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP index 40c16fef7b3..fbb668ac778 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP @@ -1 +1 @@ -Subproject commit 40c16fef7b3380982a8e6517654272cca5a9dc0a +Subproject commit fbb668ac7786c6f4ea8f2a60bfa2ae63c0b43863 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace b/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace index 3aa03556bdb..45086cef5c8 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace @@ -1 +1 @@ -Subproject commit 3aa03556bdb47641d6ff0c95416d16e42a8cdc02 +Subproject commit 45086cef5c85ab01526a811d0dc2880fad3e384f diff --git a/FreeRTOS-Plus/Source/Utilities/backoff_algorithm b/FreeRTOS-Plus/Source/Utilities/backoff_algorithm index f4b3fcfe920..0b4f9920fa2 160000 --- a/FreeRTOS-Plus/Source/Utilities/backoff_algorithm +++ b/FreeRTOS-Plus/Source/Utilities/backoff_algorithm @@ -1 +1 @@ -Subproject commit f4b3fcfe92002a3a7609e511fd05361b9e812021 +Subproject commit 0b4f9920fa28faba02815521f10b31a3443eaf59 diff --git a/FreeRTOS-Plus/Source/coreJSON b/FreeRTOS-Plus/Source/coreJSON index 360cfcd8eac..b92c8cd9cdb 160000 --- a/FreeRTOS-Plus/Source/coreJSON +++ b/FreeRTOS-Plus/Source/coreJSON @@ -1 +1 @@ -Subproject commit 360cfcd8eac76737cddab9be6c4eb057446b1ec0 +Subproject commit b92c8cd9cdba790e46eab05f7a620b0f15c5be69 diff --git a/FreeRTOS-Plus/Source/corePKCS11 b/FreeRTOS-Plus/Source/corePKCS11 index 6ddc35ebdcd..59875a9aa3f 160000 --- a/FreeRTOS-Plus/Source/corePKCS11 +++ b/FreeRTOS-Plus/Source/corePKCS11 @@ -1 +1 @@ -Subproject commit 6ddc35ebdcd97a74d39a9c00e9bfa9a6b0febe4e +Subproject commit 59875a9aa3f08a95eb8cdc0ba345b38dc49134ab diff --git a/FreeRTOS-Plus/Test/FreeRTOS-Cellular-Interface/Integration/Config/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Test/FreeRTOS-Cellular-Interface/Integration/Config/FreeRTOSIPConfig.h index 86573f18eb8..f9a9982a3ec 100644 --- a/FreeRTOS-Plus/Test/FreeRTOS-Cellular-Interface/Integration/Config/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/Test/FreeRTOS-Cellular-Interface/Integration/Config/FreeRTOSIPConfig.h @@ -60,26 +60,26 @@ extern void vLoggingPrintf( const char * pcFormatString, /* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ -#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN /* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software * stack repeating the checksum calculations. */ -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 /* Several API's will block until the result is known, or the action has been * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be * set per socket, using setsockopt(). If not set, the times below will be * used as defaults. */ -#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 2000 ) -#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 2000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) /* Include support for LLMNR: Link-local Multicast Name Resolution * (non-Microsoft) */ -#define ipconfigUSE_LLMNR ( 0 ) +#define ipconfigUSE_LLMNR ( 0 ) /* Include support for NBNS: NetBIOS Name Service (Microsoft) */ -#define ipconfigUSE_NBNS ( 0 ) +#define ipconfigUSE_NBNS ( 0 ) /* Include support for DNS caching. For TCP, having a small DNS cache is very * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low @@ -87,10 +87,10 @@ extern void vLoggingPrintf( const char * pcFormatString, * socket has been destroyed, the result will be stored into the cache. The next * call to FreeRTOS_gethostbyname() will return immediately, without even creating * a socket. */ -#define ipconfigUSE_DNS_CACHE ( 1 ) -#define ipconfigDNS_CACHE_NAME_LENGTH ( 64 ) -#define ipconfigDNS_CACHE_ENTRIES ( 4 ) -#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) +#define ipconfigUSE_DNS_CACHE ( 1 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 64 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) /* The IP stack executes it its own task (although any application task can make * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY @@ -101,22 +101,14 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to * the priority assigned to the task executing the IP stack relative to the * priority assigned to tasks that use the IP stack. */ -#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) /* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP * task. This setting is less important when the FreeRTOS Win32 simulator is used * as the Win32 simulator only stores a fixed amount of information on the task * stack. FreeRTOS includes optional stack overflow detection, see: * https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) - -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -extern UBaseType_t uxRand(); -#define ipconfigRAND32() uxRand() +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK diff --git a/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Networkless/Config/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Networkless/Config/FreeRTOSIPConfig.h index ff15e6c113e..a6d1283a011 100644 --- a/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Networkless/Config/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Networkless/Config/FreeRTOSIPConfig.h @@ -62,26 +62,26 @@ extern void vLoggingPrintf( const char * pcFormatString, /* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ -#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN /* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software * stack repeating the checksum calculations. */ -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 /* Several API's will block until the result is known, or the action has been * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be * set per socket, using setsockopt(). If not set, the times below will be * used as defaults. */ -#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) -#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) /* Include support for LLMNR: Link-local Multicast Name Resolution * (non-Microsoft) */ -#define ipconfigUSE_LLMNR ( 0 ) +#define ipconfigUSE_LLMNR ( 0 ) /* Include support for NBNS: NetBIOS Name Service (Microsoft) */ -#define ipconfigUSE_NBNS ( 1 ) +#define ipconfigUSE_NBNS ( 1 ) /* Include support for DNS caching. For TCP, having a small DNS cache is very * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low @@ -89,11 +89,11 @@ extern void vLoggingPrintf( const char * pcFormatString, * socket has been destroyed, the result will be stored into the cache. The next * call to FreeRTOS_gethostbyname() will return immediately, without even creating * a socket. */ -#define ipconfigUSE_DNS_CACHE ( 1 ) -#define ipconfigDNS_CACHE_NAME_LENGTH ( 254 ) -#define ipconfigDNS_CACHE_ENTRIES ( 4 ) -#define ipconfigDNS_CACHE_ADDRESSES_PER_ENTRY ( 6 ) -#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) +#define ipconfigUSE_DNS_CACHE ( 1 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 254 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_CACHE_ADDRESSES_PER_ENTRY ( 6 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) /* The IP stack executes it its own task (although any application task can make * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY @@ -104,22 +104,14 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to * the priority assigned to the task executing the IP stack relative to the * priority assigned to tasks that use the IP stack. */ -#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) /* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP * task. This setting is less important when the FreeRTOS Win32 simulator is used * as the Win32 simulator only stores a fixed amount of information on the task * stack. FreeRTOS includes optional stack overflow detection, see: * http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) - -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -/*extern UBaseType_t rand(); */ -#define ipconfigRAND32() rand() +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK @@ -232,11 +224,10 @@ extern void vLoggingPrintf( const char * pcFormatString, #define ipconfigUSE_TCP_WIN ( 1 ) /* The MTU is the maximum number of bytes the payload of a network frame can - * contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a - * lower value can save RAM, depending on the buffer management scheme used. If - * ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must - * be divisible by 8. */ -#define ipconfigNETWORK_MTU 1200U + * contain. Setting this to a number lower than that of the network you are + * connecting to is likely to cause dropped packets. Do not set this parameter + * lower than 1500 unless you fully understand the consequences. */ +#define ipconfigNETWORK_MTU 1500U /* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used * through the FreeRTOS_gethostbyname() API function. */ diff --git a/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Suite/Config/FreeRTOSIPConfig.h b/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Suite/Config/FreeRTOSIPConfig.h index 5bda6652855..2ce3b83167a 100644 --- a/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Suite/Config/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/Test/FreeRTOS-Plus-TCP/Integration/Full-TCP-Suite/Config/FreeRTOSIPConfig.h @@ -97,20 +97,12 @@ * https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html. */ #define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -extern uint32_t ulRand(); -#define ipconfigRAND32() ulRand() - /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK * is not set to 1 then the network event hook will never be called. See: * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml. */ -#define ipconfigUSE_NETWORK_EVENT_HOOK 1 +#define ipconfigUSE_NETWORK_EVENT_HOOK 1 /* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but * a network buffer cannot be obtained then the calling task is held in the Blocked @@ -124,7 +116,7 @@ extern uint32_t ulRand(); * ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in * milliseconds can be converted to a time in ticks by dividing the time in * milliseconds by portTICK_PERIOD_MS. */ -#define ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ( 5000U / portTICK_PERIOD_MS ) +#define ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ( 5000U / portTICK_PERIOD_MS ) /* If ipconfigUSE_DHCP is 1 then FreeRTOS+TCP will attempt to retrieve an IP * address, netmask, DNS server address and gateway address from a DHCP server. If @@ -133,14 +125,14 @@ extern uint32_t ulRand(); * set to 1 if a valid configuration cannot be obtained from a DHCP server for any * reason. The static configuration used is that passed into the stack by the * FreeRTOS_IPInit() function call. */ -#define ipconfigUSE_DHCP 1 -#define ipconfigDHCP_REGISTER_HOSTNAME 1 -#define ipconfigDHCP_USES_UNICAST 1 +#define ipconfigUSE_DHCP 1 +#define ipconfigDHCP_REGISTER_HOSTNAME 1 +#define ipconfigDHCP_USES_UNICAST 1 /* If ipconfigDHCP_USES_USER_HOOK is set to 1 then the application writer must * provide an implementation of the DHCP callback function, * xApplicationDHCPUserHook(). */ -#define ipconfigUSE_DHCP_HOOK 0 +#define ipconfigUSE_DHCP_HOOK 0 /* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at * increasing time intervals until either a reply is received from a DHCP server @@ -226,11 +218,10 @@ extern uint32_t ulRand(); #define ipconfigUSE_TCP_WIN ( 1 ) /* The MTU is the maximum number of bytes the payload of a network frame can - * contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a - * lower value can save RAM, depending on the buffer management scheme used. If - * ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must - * be divisible by 8. */ -#define ipconfigNETWORK_MTU 1200U + * contain. Setting this to a number lower than that of the network you are + * connecting to is likely to cause dropped packets. Do not set this parameter + * lower than 1500 unless you fully understand the consequences. */ +#define ipconfigNETWORK_MTU 1500U /* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used * through the FreeRTOS_gethostbyname() API function. */ diff --git a/FreeRTOS-Plus/ThirdParty/mbedtls b/FreeRTOS-Plus/ThirdParty/mbedtls index 869298bffee..edb8fec9882 160000 --- a/FreeRTOS-Plus/ThirdParty/mbedtls +++ b/FreeRTOS-Plus/ThirdParty/mbedtls @@ -1 +1 @@ -Subproject commit 869298bffeea13b205343361b7a7daf2b210e33d +Subproject commit edb8fec9882084344a314368ac7fd957a187519c diff --git a/FreeRTOS-Plus/ThirdParty/winpcap/include/ip6_misc.h b/FreeRTOS-Plus/ThirdParty/winpcap/include/ip6_misc.h index 1b2e4337b55..f31c4e9b762 100644 --- a/FreeRTOS-Plus/ThirdParty/winpcap/include/ip6_misc.h +++ b/FreeRTOS-Plus/ThirdParty/winpcap/include/ip6_misc.h @@ -29,11 +29,13 @@ #include -#ifndef __MINGW32__ - #define IN_MULTICAST( a ) IN_CLASSD( a ) -#endif +#ifndef IN_MULTICAST + #ifndef __MINGW32__ + #define IN_MULTICAST( a ) IN_CLASSD( a ) + #endif +#endif /* IN_MULTICAST */ -#define IN_EXPERIMENTAL( a ) ( ( ( ( u_int32_t ) ( a ) ) & 0xf0000000 ) == 0xf0000000 ) +#define IN_EXPERIMENTAL( a ) ( ( ( ( u_int32_t ) ( a ) ) & 0xf0000000 ) == 0xf0000000 ) #define IN_LOOPBACKNET 127 diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOS+TCP.vcxproj b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOS+TCP.vcxproj index eb370fbd38a..03ced5ca0bc 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOS+TCP.vcxproj +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOS+TCP.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 17.0 @@ -44,26 +28,6 @@ true v142 - - StaticLibrary - false - v142 - - - StaticLibrary - true - v142 - - - StaticLibrary - true - v142 - - - StaticLibrary - false - v142 - @@ -75,55 +39,10 @@ - - - - - - - - - - - - true - - true - - - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\;$(PublicIncludeDirectories) - true - build\$(ProjectName)\$(Platform)\$(Configuration)\ - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_LibraryPath_x64);$(WindowsSDK_LibraryPath_x64);..\..\ThirdParty\winpcap\lib\x64 - $(IncludePath) - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\ - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools;$(SourcePath) - - - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\;$(PublicIncludeDirectories) - true - build\$(ProjectName)\$(Platform)\$(Configuration)\ - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_LibraryPath_x64);$(WindowsSDK_LibraryPath_x64);..\..\ThirdParty\winpcap\lib\x64 - $(IncludePath) - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\ - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools;$(SourcePath) - - - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\;$(PublicIncludeDirectories) - true - build\$(ProjectName)\$(Platform)\$(Configuration)\ - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_LibraryPath_x64);$(WindowsSDK_LibraryPath_x64);..\..\ThirdParty\winpcap\lib\x64 - $(IncludePath) - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\ - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools;$(SourcePath) - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\;$(PublicIncludeDirectories) true @@ -144,27 +63,17 @@ ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\ ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools;$(SourcePath) - - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\;$(PublicIncludeDirectories) - true - build\$(ProjectName)\$(Platform)\$(Configuration)\ - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_LibraryPath_x86);$(WindowsSDK_LibraryPath_x86);..\..\ThirdParty\winpcap\lib\x86 - $(IncludePath) - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;.\ - ..\..\Source\FreeRTOS-Plus-TCP\source;..\..\Source\FreeRTOS-Plus-TCP\tools;$(SourcePath) - false - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_CRT_SECURE_NO_WARNINGS;_DEBUG;_LIB;%(PreprocessorDefinitions) MultiThreadedDebugDLL Level3 ProgramDatabase Disabled - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\ThirdParty\winpcap\include;..\..\ThirdParty\winpcap\include\pcap;.\;%(AdditionalIncludeDirectories) + ..\ThirdParty\MbedTLS;..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\ThirdParty\winpcap\include;..\..\ThirdParty\winpcap\include\pcap;.\;%(AdditionalIncludeDirectories) MachineX86 @@ -177,7 +86,7 @@ - BUILDING_LIBSLIRP;_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;BUILDING_LIBSLIRP;_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) MultiThreadedDebugDLL Level3 ProgramDatabase @@ -193,54 +102,6 @@ wpcap.lib;%(AdditionalDependencies) - - - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - MultiThreadedDLL - Level3 - ProgramDatabase - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\ThirdParty\winpcap\include;..\..\ThirdParty\winpcap\include\pcap;.\;%(AdditionalIncludeDirectories) - - - MachineX86 - true - Windows - true - true - - - wpcap.lib;%(AdditionalDependencies) - - - - - - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\ThirdParty\winpcap\include;..\..\ThirdParty\winpcap\include\pcap;.\;%(AdditionalIncludeDirectories) - - - wpcap.lib;%(AdditionalDependencies) - - - - - - BUILDING_LIBSLIRP;_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - ..\..\ThirdParty\glib;..\..\ThirdParty\glib\glib;..\..\ThirdParty\glib\build\;..\..\ThirdParty\glib\build\glib;..\..\ThirdParty\glib\build\subprojects\pcre2-10.42;..\..\ThirdParty\glib\subprojects\proxy-libintl;..\..\ThirdParty\libslirp\src;..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\ThirdParty\winpcap\include;..\..\ThirdParty\winpcap\include\pcap;.\;%(AdditionalIncludeDirectories) - - - wpcap.lib;%(AdditionalDependencies) - - - - - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - ..\..\Source\FreeRTOS-Plus-TCP\source\include;..\..\Source\FreeRTOS-Plus-TCP\source\portable\Compiler\MSVC;..\..\Source\FreeRTOS-Plus-TCP\tools\tcp_utilities\include;..\..\ThirdParty\winpcap\include;..\..\ThirdParty\winpcap\include\pcap;.\;%(AdditionalIncludeDirectories) - - - wpcap.lib;%(AdditionalDependencies) - - @@ -288,18 +149,10 @@ false true - true - false - true - true false true - true - false - true - true @@ -307,262 +160,134 @@ false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false false true - true - true - true - false true - true - - ipconfigUSE_LIBSLIRP;BUILDING_LIBSLIRP;_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - ipconfigUSE_LIBSLIRP;BUILDING_LIBSLIRP;_CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) @@ -613,1243 +338,639 @@ false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true - true true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true false - false - true true - true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true true - true @@ -1864,27 +985,15 @@ false - false true - true - true - true false - false true - true - true - true false - false true - true - true - true diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOSIPConfig.h b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOSIPConfig.h index bb372e016ed..d0b547748bc 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOSIPConfig.h +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/FreeRTOSIPConfig.h @@ -63,26 +63,26 @@ extern void vLoggingPrintf( const char * pcFormatString, /* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing * on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ -#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN /* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) * then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software * stack repeating the checksum calculations. */ -#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 /* Several API's will block until the result is known, or the action has been * performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be * set per socket, using setsockopt(). If not set, the times below will be * used as defaults. */ -#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) -#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) /* Include support for LLMNR: Link-local Multicast Name Resolution * (non-Microsoft) */ -#define ipconfigUSE_LLMNR ( 0 ) +#define ipconfigUSE_LLMNR ( 0 ) /* Include support for NBNS: NetBIOS Name Service (Microsoft) */ -#define ipconfigUSE_NBNS ( 0 ) +#define ipconfigUSE_NBNS ( 0 ) /* Include support for DNS caching. For TCP, having a small DNS cache is very * useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low @@ -90,10 +90,10 @@ extern void vLoggingPrintf( const char * pcFormatString, * socket has been destroyed, the result will be stored into the cache. The next * call to FreeRTOS_gethostbyname() will return immediately, without even creating * a socket. */ -#define ipconfigUSE_DNS_CACHE 1 -#define ipconfigDNS_CACHE_NAME_LENGTH ( 64U ) -#define ipconfigDNS_CACHE_ENTRIES ( 4U ) -#define ipconfigDNS_REQUEST_ATTEMPTS ( 2U ) +#define ipconfigUSE_DNS_CACHE 1 +#define ipconfigDNS_CACHE_NAME_LENGTH ( 64U ) +#define ipconfigDNS_CACHE_ENTRIES ( 4U ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2U ) /* The IP stack executes it its own task (although any application task can make * use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY @@ -104,22 +104,14 @@ extern void vLoggingPrintf( const char * pcFormatString, * FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to * the priority assigned to the task executing the IP stack relative to the * priority assigned to tasks that use the IP stack. */ -#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2U ) +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2U ) /* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP * task. This setting is less important when the FreeRTOS Win32 simulator is used * as the Win32 simulator only stores a fixed amount of information on the task * stack. FreeRTOS includes optional stack overflow detection, see: * https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html */ -#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5U ) - -/* ipconfigRAND32() is called by the IP stack to generate random numbers for - * things such as a DHCP transaction number or initial sequence number. Random - * number generation is performed via this macro to allow applications to use their - * own random number generation method. For example, it might be possible to - * generate a random number by sampling noise on an analogue input. */ -extern UBaseType_t uxRand(); -#define ipconfigRAND32() uxRand() +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5U ) /* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the * network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK @@ -314,9 +306,10 @@ extern UBaseType_t uxRand(); /* Set ipconfigBUFFER_PADDING on 64-bit platforms */ #if INTPTR_MAX == INT64_MAX - #define ipconfigBUFFER_PADDING ( 14U ) + #define ipconfigBUFFER_PADDING ( 14U ) #endif /* INTPTR_MAX == INT64_MAX */ +#define ipconfigETHERNET_DRIVER_FILTERS_PACKETS ( 1 ) #define configMAC diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c index d3790851aec..92d08fc5d7f 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c @@ -35,6 +35,8 @@ #include "FreeRTOS_IP.h" #include "FreeRTOS_Sockets.h" +/* Function from freertos_hooks_winsim.c */ +extern UBaseType_t uxRand( void ); /*-----------------------------------------------------------*/ #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) @@ -51,6 +53,10 @@ /*-----------------------------------------------------------*/ +extern UBaseType_t uxRand(); + +/*-----------------------------------------------------------*/ + #if ( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_NBNS != 0 ) || ( ipconfigDHCP_REGISTER_HOSTNAME == 1 ) const char * pcApplicationHostnameHook( void ) @@ -209,6 +215,8 @@ void vPlatformInitIpStack( void ) NetworkInterface_t * pxInterface ); pxLibslirp_FillInterfaceDescriptor( 0, &( xInterfaces[ 0 ] ) ); #else + extern NetworkInterface_t * pxWinPcap_FillInterfaceDescriptor( BaseType_t xEMACIndex, + NetworkInterface_t * pxInterface ); pxWinPcap_FillInterfaceDescriptor( 0, &( xInterfaces[ 0 ] ) ); #endif @@ -220,7 +228,7 @@ void vPlatformInitIpStack( void ) xEndPoints[ 0 ].bits.bWantDHCP = pdTRUE; } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOS-Kernel.vcxproj b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOS-Kernel.vcxproj index 604bf2d32c5..bea5ef250db 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOS-Kernel.vcxproj +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOS-Kernel.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 17.0 @@ -44,26 +28,6 @@ true v142 - - StaticLibrary - false - v142 - - - StaticLibrary - true - v142 - - - StaticLibrary - true - v142 - - - StaticLibrary - false - v142 - @@ -75,18 +39,6 @@ - - - - - - - - - - - - true @@ -102,42 +54,17 @@ ..\..\..\FreeRTOS\Source;$(SourcePath) ..\..\..\FreeRTOS\Source;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\portable\MemMang;$(PublicModuleDirectories) - - true - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_IncludePath);$(WindowsSDK_IncludePath);$(IncludePath) - ..\..\..\FreeRTOS\Source;$(SourcePath) - ..\..\..\FreeRTOS\Source;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\portable\MemMang;$(PublicModuleDirectories) - build\$(ProjectName)\$(Platform)\$(Configuration)\ ..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\include;.\;$(PublicIncludeDirectories) true - - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_IncludePath);$(WindowsSDK_IncludePath);$(IncludePath) - ..\..\..\FreeRTOS\Source;$(SourcePath) - ..\..\..\FreeRTOS\Source;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\portable\MemMang;$(PublicModuleDirectories) - - - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_IncludePath);$(WindowsSDK_IncludePath);$(IncludePath) - ..\..\..\FreeRTOS\Source;$(SourcePath) - ..\..\..\FreeRTOS\Source;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\portable\MemMang;$(PublicModuleDirectories) - - - build\$(ProjectName)\$(Platform)\$(Configuration)\ - $(VC_IncludePath);$(WindowsSDK_IncludePath);$(IncludePath) - ..\..\..\FreeRTOS\Source;$(SourcePath) - ..\..\..\FreeRTOS\Source;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\portable\MemMang;$(PublicModuleDirectories) - false - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_CRT_SECURE_NO_WARNINGS;_DEBUG;_LIB;%(PreprocessorDefinitions) MultiThreadedDebugDLL Level3 ProgramDatabase @@ -151,7 +78,7 @@ - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_CRT_SECURE_NO_WARNINGS;_DEBUG;_LIB;%(PreprocessorDefinitions) MultiThreadedDebugDLL Level3 ProgramDatabase @@ -163,27 +90,9 @@ Windows - - - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - MultiThreadedDLL - Level3 - ProgramDatabase - - - MachineX86 - true - Windows - true - true - - ..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\..\FreeRTOS\Source\include;.\;%(AdditionalIncludeDirectories) - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOSConfig.h b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOSConfig.h index 6bc03048fb9..de14ea07cdf 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOSConfig.h +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/FreeRTOSConfig.h @@ -139,7 +139,7 @@ void vConfigureTimerForRunTimeStats( void ); * results in the wired network being used, while setting * configNETWORK_INTERFACE_TO_USE to 2 results in the wireless network being * used. */ -#define configNETWORK_INTERFACE_TO_USE ( 1L ) +#define configNETWORK_INTERFACE_TO_USE ( 0L ) /* The address to which logging is sent should UDP logging be enabled. */ #define configUDP_LOGGING_ADDR0 192 diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/freertos_hooks_winsim.c b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/freertos_hooks_winsim.c index 65e351f40cf..7c74e0ead67 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/freertos_hooks_winsim.c +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/freertos_hooks_winsim.c @@ -32,8 +32,16 @@ * should an assert get hit. */ #include -/* Windows Crypt api for uxRand() */ + +#ifdef WIN32_LEAN_AND_MEAN + #include +#else + #include +#endif /* WIN32_LEAN_AND_MEAN */ + #include + +/* Windows Crypt api for uxRand() */ #include /* FreeRTOS includes. */ @@ -42,6 +50,10 @@ /*-----------------------------------------------------------*/ +extern void vPlatformStopLoggingThreadAndFlush( void ); + +/*-----------------------------------------------------------*/ + void vAssertCalled( const char * pcFile, uint32_t ulLine ) { @@ -52,7 +64,11 @@ void vAssertCalled( const char * pcFile, ( void ) pcFileName; ( void ) ulLineNumber; - printf( "vAssertCalled( %s, %u\n", pcFile, ulLine ); + /* Stop the windows logging thread and flush the log buffer. This function does + * nothing if the logging is not initialized before. */ + vPlatformStopLoggingThreadAndFlush(); + + printf( "vAssertCalled( %s, %u )\n", pcFile, ulLine ); /* Setting ulBlockVariable to a non-zero value in the debugger will allow * this function to be exited. */ diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/runtime_stats_winsim.c b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/runtime_stats_winsim.c index 58d8cc843d2..fcf00411a2e 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/runtime_stats_winsim.c +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS-Kernel/runtime_stats_winsim.c @@ -37,7 +37,14 @@ */ #include -#include + +#ifdef WIN32_LEAN_AND_MEAN + #include +#else + #include +#endif /* WIN32_LEAN_AND_MEAN */ + +#include /* FreeRTOS includes. */ #include "FreeRTOS.h" diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS_Plus_Libs.sln b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS_Plus_Libs.sln index 1b678f14c90..3dd0390f842 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS_Plus_Libs.sln +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS_Plus_Libs.sln @@ -1,4 +1,3 @@ - Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio Version 16 VisualStudioVersion = 16.0.33529.622 @@ -17,86 +16,34 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "corePKCS11", "corePKCS11\co EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug_with_Libslirp|x64 = Debug_with_Libslirp|x64 - Debug_with_Libslirp|x86 = Debug_with_Libslirp|x86 - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|x64 = Release|x64 - Release|x86 = Release|x86 + Debug_with_Libslirp|Win32 = Debug_with_Libslirp|Win32 + Debug|Win32 = Debug|Win32 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.ActiveCfg = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x64.Build.0 = Debug|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.ActiveCfg = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|x86.Build.0 = Debug|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.ActiveCfg = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x64.Build.0 = Release|x64 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.ActiveCfg = Release|Win32 - {C90E6CC5-818B-4C97-8876-0986D989387C}.Release|x86.Build.0 = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.ActiveCfg = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x64.Build.0 = Debug|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.ActiveCfg = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|x86.Build.0 = Debug|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.ActiveCfg = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x64.Build.0 = Release|x64 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.ActiveCfg = Release|Win32 - {72C209C4-49A4-4942-A201-44706C9D77EC}.Release|x86.Build.0 = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.ActiveCfg = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x64.Build.0 = Debug|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.ActiveCfg = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|x86.Build.0 = Debug|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.ActiveCfg = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x64.Build.0 = Release|x64 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.ActiveCfg = Release|Win32 - {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Release|x86.Build.0 = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.ActiveCfg = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x64.Build.0 = Debug|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x86.ActiveCfg = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|x86.Build.0 = Debug|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.ActiveCfg = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x64.Build.0 = Release|x64 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x86.ActiveCfg = Release|Win32 - {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Release|x86.Build.0 = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.ActiveCfg = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x64.Build.0 = Debug|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.ActiveCfg = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|x86.Build.0 = Debug|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.ActiveCfg = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x64.Build.0 = Release|x64 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.ActiveCfg = Release|Win32 - {BE362AC0-B10B-4276-B84E-6304652BA228}.Release|x86.Build.0 = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|x64.ActiveCfg = Debug_with_Libslirp|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|x64.Build.0 = Debug_with_Libslirp|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|x86.ActiveCfg = Debug_with_Libslirp|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|x86.Build.0 = Debug_with_Libslirp|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.ActiveCfg = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x64.Build.0 = Debug|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x86.ActiveCfg = Debug|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|x86.Build.0 = Debug|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.ActiveCfg = Release|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x64.Build.0 = Release|x64 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x86.ActiveCfg = Release|Win32 - {19F0FF1A-3368-491A-9932-A2F089508F51}.Release|x86.Build.0 = Release|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.ActiveCfg = Debug|Win32 + {C90E6CC5-818B-4C97-8876-0986D989387C}.Debug|Win32.Build.0 = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.ActiveCfg = Debug|Win32 + {72C209C4-49A4-4942-A201-44706C9D77EC}.Debug|Win32.Build.0 = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.ActiveCfg = Debug|Win32 + {E1016F3E-94E9-4864-9FD8-1D7C1FEFBFD7}.Debug|Win32.Build.0 = Debug|Win32 + {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.ActiveCfg = Debug|Win32 + {EE39FA0F-CEFB-4C29-A571-05A28FDD47FD}.Debug|Win32.Build.0 = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.ActiveCfg = Debug|Win32 + {BE362AC0-B10B-4276-B84E-6304652BA228}.Debug|Win32.Build.0 = Debug|Win32 + {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|Win32.ActiveCfg = Debug_with_Libslirp|Win32 + {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug_with_Libslirp|Win32.Build.0 = Debug_with_Libslirp|Win32 + {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.ActiveCfg = Debug|Win32 + {19F0FF1A-3368-491A-9932-A2F089508F51}.Debug|Win32.Build.0 = Debug|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/Logging/Logging.vcxproj b/FreeRTOS-Plus/VisualStudio_StaticProjects/Logging/Logging.vcxproj index b88ba8dbb64..acac089ec3b 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/Logging/Logging.vcxproj +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/Logging/Logging.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - StaticLibrary - false - v142 - true - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - ..\..\Source\Utilities\logging;$(PublicIncludeDirectories) @@ -104,27 +50,11 @@ ..\..\Source\Utilities\logging;$(PublicIncludeDirectories) true - - ..\..\Source\Utilities\logging;$(PublicIncludeDirectories) - true - - - ..\..\Source\Utilities\logging;$(PublicIncludeDirectories) - true - - - ..\..\Source\Utilities\logging;$(PublicIncludeDirectories) - true - - - ..\..\Source\Utilities\logging;$(PublicIncludeDirectories) - true - Level3 true - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true $(PublicIncludeDirectories) true @@ -138,77 +68,13 @@ Level3 true - _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - $(PublicIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - $(PublicIncludeDirectories) - true - - - Console - true - true - true - - - - - Level3 - true - _CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - $(PublicIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - _CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - $(PublicIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;_CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true $(PublicIncludeDirectories) true Console - true - true true diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj b/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj index d5ad906da17..9449cc88758 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - @@ -42,6 +26,12 @@ + + + + + + @@ -57,6 +47,7 @@ + @@ -68,6 +59,7 @@ + @@ -78,6 +70,7 @@ + @@ -91,32 +84,47 @@ + + + + + + + + - + + + + + + + - + + @@ -124,39 +132,49 @@ + + + + + + - + + + + + @@ -174,12 +192,15 @@ + + + @@ -193,6 +214,7 @@ + @@ -203,20 +225,24 @@ - + + + + + @@ -237,6 +263,7 @@ + @@ -272,32 +299,6 @@ v142 Unicode - - StaticLibrary - false - v142 - true - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - false - v142 - true - Unicode - @@ -309,18 +310,6 @@ - - - - - - - - - - - - build\$(ProjectName)\$(Platform)\$(Configuration)\ @@ -335,7 +324,7 @@ Level3 true - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\..\ThirdParty\mbedtls\library;..\..\ThirdParty\mbedtls\include true @@ -349,77 +338,13 @@ Level3 true - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - .\;..\..\ThirdParty\mbedtls\library;..\..\ThirdParty\mbedtls\include - true - - - Console - true - - - - - Level3 - true - true - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - .\;..\..\ThirdParty\mbedtls\library;..\..\ThirdParty\mbedtls\include - true - - - Console - true - true - true - - - - - Level3 - true - _DEBUG;_CONSOLE;%(PreprocessorDefinitions);MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - .\;..\..\ThirdParty\mbedtls\library;..\..\ThirdParty\mbedtls\include - true - - - Console - true - - - - - Level3 - true - _DEBUG;_CONSOLE;%(PreprocessorDefinitions);MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" - true - .\;..\..\ThirdParty\mbedtls\library;..\..\ThirdParty\mbedtls\include - true - - - Console - true - - - - - Level3 - true - true - true - NDEBUG;_CONSOLE;%(PreprocessorDefinitions);MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h" + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true .\;..\..\ThirdParty\mbedtls\library;..\..\ThirdParty\mbedtls\include true Console - true - true true diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj.filters b/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj.filters index 75a2f69aa8f..d39f9b09250 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj.filters +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/MbedTLS.vcxproj.filters @@ -21,396 +21,460 @@ - + + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + + MbedTLS Headers\mbedtls + + MbedTLS Headers\mbedtls MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + + MbedTLS Headers\mbedtls + + + MbedTLS Headers\mbedtls + + + MbedTLS Headers\mbedtls + + + MbedTLS Headers\mbedtls + + MbedTLS Headers\mbedtls MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + + MbedTLS Headers\mbedtls + + MbedTLS Headers\mbedtls MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - + MbedTLS Headers\mbedtls - - MbedTLS Headers\psa + + MbedTLS Headers\mbedtls - - MbedTLS Headers\psa + + MbedTLS Headers\mbedtls - - MbedTLS Headers\psa + + MbedTLS Headers\mbedtls - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa - + MbedTLS Headers\psa MbedTLS Headers\psa - + MbedTLS Headers\psa - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - MbedTLS Source + + MbedTLS Headers\psa - - - + - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - - MbedTLS Source - - + + MbedTLS Source - + MbedTLS Source @@ -431,6 +495,15 @@ MbedTLS Source + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + MbedTLS Source @@ -482,6 +555,9 @@ MbedTLS Source + + MbedTLS Source + MbedTLS Source @@ -500,6 +576,12 @@ MbedTLS Source + + MbedTLS Source + + + MbedTLS Source + MbedTLS Source @@ -539,6 +621,9 @@ MbedTLS Source + + MbedTLS Source + MbedTLS Source @@ -569,18 +654,24 @@ MbedTLS Source - + MbedTLS Source MbedTLS Source + + MbedTLS Source + MbedTLS Source MbedTLS Source + + MbedTLS Source + MbedTLS Source @@ -596,6 +687,9 @@ MbedTLS Source + + MbedTLS Source + MbedTLS Source @@ -608,6 +702,9 @@ MbedTLS Source + + MbedTLS Source + MbedTLS Source @@ -659,6 +756,38 @@ MbedTLS Source - + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + + + MbedTLS Source + \ No newline at end of file diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/mbedtls_config_v3.2.1.h b/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/mbedtls_config_v3.5.1.h similarity index 69% rename from FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/mbedtls_config_v3.2.1.h rename to FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/mbedtls_config_v3.5.1.h index 7d5dedc5a39..f3bfdc80920 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/mbedtls_config_v3.2.1.h +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/MbedTLS/mbedtls_config_v3.5.1.h @@ -25,6 +25,9 @@ * limitations under the License. */ +#ifndef __FREERTOS_MBEDTLS_CONFIG__ +#define __FREERTOS_MBEDTLS_CONFIG__ + /** * This is an optional version symbol that enables compatibility handling of * config files. @@ -32,7 +35,7 @@ * It is equal to the #MBEDTLS_VERSION_NUMBER of the Mbed TLS version that * introduced the config format we want to be compatible with. */ -/*#define MBEDTLS_CONFIG_VERSION 0x03000000 */ +/* #define MBEDTLS_CONFIG_VERSION 0x03000000 */ /** * \name SECTION: System support @@ -49,11 +52,15 @@ * Requires support for asm() in compiler. * * Used in: + * library/aesni.h * library/aria.c * library/bn_mul.h + * library/constant_time.c + * library/padlock.h * * Required by: - * MBEDTLS_AESNI_C + * MBEDTLS_AESCE_C + * MBEDTLS_AESNI_C (on some platforms) * MBEDTLS_PADLOCK_C * * Comment to disable the use of assembly code. @@ -86,7 +93,7 @@ * example, if double-width division is implemented in software, disabling * it can reduce code size in some embedded targets. */ -/*#define MBEDTLS_NO_UDBL_DIVISION */ +/* #define MBEDTLS_NO_UDBL_DIVISION */ /** * \def MBEDTLS_NO_64BIT_MULTIPLICATION @@ -108,7 +115,7 @@ * Note that depending on the compiler, this may decrease performance compared * to using the library function provided by the toolchain. */ -/*#define MBEDTLS_NO_64BIT_MULTIPLICATION */ +/* #define MBEDTLS_NO_64BIT_MULTIPLICATION */ /** * \def MBEDTLS_HAVE_SSE2 @@ -117,7 +124,7 @@ * * Uncomment if the CPU supports SSE2 (IA-32 specific). */ -/*#define MBEDTLS_HAVE_SSE2 */ +/* #define MBEDTLS_HAVE_SSE2 */ /** * \def MBEDTLS_HAVE_TIME @@ -137,7 +144,7 @@ * regardless of the setting of MBEDTLS_HAVE_TIME, unless * MBEDTLS_TIMING_ALT is used. See timing.c for more information. */ -/*#define MBEDTLS_HAVE_TIME */ +/* #define MBEDTLS_HAVE_TIME */ /** * \def MBEDTLS_HAVE_TIME_DATE @@ -158,26 +165,58 @@ * mbedtls_platform_gmtime_r() at compile-time by using the macro * MBEDTLS_PLATFORM_GMTIME_R_ALT. */ -/*#define MBEDTLS_HAVE_TIME_DATE */ +/* #define MBEDTLS_HAVE_TIME_DATE */ /** * \def MBEDTLS_PLATFORM_MEMORY * * Enable the memory allocation layer. * - * By default mbed TLS uses the system-provided calloc() and free(). + * By default Mbed TLS uses the system-provided calloc() and free(). * This allows different allocators (self-implemented or provided) to be * provided to the platform abstraction layer. * - * Enabling MBEDTLS_PLATFORM_MEMORY without the + * Enabling #MBEDTLS_PLATFORM_MEMORY without the * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and * free() function pointer at runtime. * - * Enabling MBEDTLS_PLATFORM_MEMORY and specifying + * Enabling #MBEDTLS_PLATFORM_MEMORY and specifying * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the * alternate function at compile time. * + * An overview of how the value of mbedtls_calloc is determined: + * + * - if !MBEDTLS_PLATFORM_MEMORY + * - mbedtls_calloc = calloc + * - if MBEDTLS_PLATFORM_MEMORY + * - if (MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): + * - mbedtls_calloc = MBEDTLS_PLATFORM_CALLOC_MACRO + * - if !(MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): + * - Dynamic setup via mbedtls_platform_set_calloc_free is now possible with a default value MBEDTLS_PLATFORM_STD_CALLOC. + * - How is MBEDTLS_PLATFORM_STD_CALLOC handled? + * - if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: + * - MBEDTLS_PLATFORM_STD_CALLOC is not set to anything; + * - MBEDTLS_PLATFORM_STD_MEM_HDR can be included if present; + * - if !MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: + * - if MBEDTLS_PLATFORM_STD_CALLOC is present: + * - User-defined MBEDTLS_PLATFORM_STD_CALLOC is respected; + * - if !MBEDTLS_PLATFORM_STD_CALLOC: + * - MBEDTLS_PLATFORM_STD_CALLOC = calloc + * + * - At this point the presence of MBEDTLS_PLATFORM_STD_CALLOC is checked. + * - if !MBEDTLS_PLATFORM_STD_CALLOC + * - MBEDTLS_PLATFORM_STD_CALLOC = uninitialized_calloc + * + * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. + * + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. + * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. + * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they are used, + * dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. + * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. + * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * * Requires: MBEDTLS_PLATFORM_C * * Enable this layer to allow use of alternative memory allocators. @@ -206,15 +245,15 @@ void mbedtls_platform_free( void * ptr ); * Uncomment to prevent default assignment of standard functions in the * platform layer. */ -/*#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ +/* #define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ /** * \def MBEDTLS_PLATFORM_EXIT_ALT * - * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the + * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let Mbed TLS support the * function in the platform abstraction layer. * - * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will + * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, Mbed TLS will * provide a function "mbedtls_platform_set_printf()" that allows you to set an * alternative printf function pointer. * @@ -231,15 +270,58 @@ void mbedtls_platform_free( void * ptr ); * Uncomment a macro to enable alternate implementation of specific base * platform function */ -/*#define MBEDTLS_PLATFORM_SETBUF_ALT */ -/*#define MBEDTLS_PLATFORM_EXIT_ALT */ -/*#define MBEDTLS_PLATFORM_TIME_ALT */ -/*#define MBEDTLS_PLATFORM_FPRINTF_ALT */ -/*#define MBEDTLS_PLATFORM_PRINTF_ALT */ -/*#define MBEDTLS_PLATFORM_SNPRINTF_ALT */ -/*#define MBEDTLS_PLATFORM_VSNPRINTF_ALT */ -/*#define MBEDTLS_PLATFORM_NV_SEED_ALT */ -/*#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ +/* #define MBEDTLS_PLATFORM_SETBUF_ALT */ +/* #define MBEDTLS_PLATFORM_EXIT_ALT */ +/* #define MBEDTLS_PLATFORM_TIME_ALT */ +/* #define MBEDTLS_PLATFORM_FPRINTF_ALT */ +/* #define MBEDTLS_PLATFORM_PRINTF_ALT */ +/* #define MBEDTLS_PLATFORM_SNPRINTF_ALT */ +/* #define MBEDTLS_PLATFORM_VSNPRINTF_ALT */ +/* #define MBEDTLS_PLATFORM_NV_SEED_ALT */ +/* #define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ +/* #define MBEDTLS_PLATFORM_MS_TIME_ALT */ + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_gmtime_r(). This replaces the default implementation in + * platform_util.c. + * + * gmtime() is not a thread-safe function as defined in the C standard. The + * library will try to use safer implementations of this function, such as + * gmtime_r() when available. However, if Mbed TLS cannot identify the target + * system, the implementation of mbedtls_platform_gmtime_r() will default to + * using the standard gmtime(). In this case, calls from the library to + * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex + * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the + * library are also guarded with this mutex to avoid race conditions. However, + * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will + * unconditionally use the implementation for mbedtls_platform_gmtime_r() + * supplied at compile time. + */ +/* #define MBEDTLS_PLATFORM_GMTIME_R_ALT */ + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_zeroize(), to wipe sensitive data in memory. This replaces + * the default implementation in platform_util.c. + * + * By default, the library uses a system function such as memset_s() + * (optional feature of C11), explicit_bzero() (BSD and compatible), or + * SecureZeroMemory (Windows). If no such function is detected, the library + * falls back to a plain C implementation. Compilers are technically + * permitted to optimize this implementation out, meaning that the memory is + * not actually wiped. The library tries to prevent that, but the C language + * makes it impossible to guarantee that the memory will always be wiped. + * + * If your platform provides a guaranteed method to wipe memory which + * `platform_util.c` does not detect, define this macro to the name of + * a function that takes two arguments, a `void *` pointer and a length, + * and wipes that many bytes starting at the specified address. For example, + * if your platform has explicit_bzero() but `platform_util.c` does not + * detect its presence, define `MBEDTLS_PLATFORM_ZEROIZE_ALT` to be + * `explicit_bzero` to use that function as mbedtls_platform_zeroize(). + */ +/* #define MBEDTLS_PLATFORM_ZEROIZE_ALT */ /** * \def MBEDTLS_DEPRECATED_WARNING @@ -268,12 +350,12 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to get errors on using deprecated functions and features. */ -/*#define MBEDTLS_DEPRECATED_REMOVED */ +/* #define MBEDTLS_DEPRECATED_REMOVED */ /** \} name SECTION: System support */ /** - * \name SECTION: mbed TLS feature support + * \name SECTION: Mbed TLS feature support * * This section sets support for features that are or are not needed * within the modules that are enabled. @@ -291,12 +373,12 @@ void mbedtls_platform_free( void * ptr ); * You will need to provide a header "timing_alt.h" and an implementation at * compile time. */ -/*#define MBEDTLS_TIMING_ALT */ +/* #define MBEDTLS_TIMING_ALT */ /** * \def MBEDTLS_AES_ALT * - * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your + * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let Mbed TLS use your * alternate core implementation of a symmetric crypto, an arithmetic or hash * module (e.g. platform specific assembly optimized implementations). Keep * in mind that the function prototypes should remain the same. @@ -304,7 +386,7 @@ void mbedtls_platform_free( void * ptr ); * This replaces the whole module. If you only want to replace one of the * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags. * - * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer + * Example: In case you uncomment MBEDTLS_AES_ALT, Mbed TLS will no longer * provide the "struct mbedtls_aes_context" definition and omit the base * function declarations and implementations. "aes_alt.h" will be included from * "aes.h" to include the new function definitions. @@ -318,25 +400,25 @@ void mbedtls_platform_free( void * ptr ); * digests and ciphers instead. * */ -/*#define MBEDTLS_AES_ALT */ -/*#define MBEDTLS_ARIA_ALT */ -/*#define MBEDTLS_CAMELLIA_ALT */ -/*#define MBEDTLS_CCM_ALT */ -/*#define MBEDTLS_CHACHA20_ALT */ -/*#define MBEDTLS_CHACHAPOLY_ALT */ -/*#define MBEDTLS_CMAC_ALT */ -/*#define MBEDTLS_DES_ALT */ -/*#define MBEDTLS_DHM_ALT */ -/*#define MBEDTLS_ECJPAKE_ALT */ -/*#define MBEDTLS_GCM_ALT */ -/*#define MBEDTLS_NIST_KW_ALT */ -/*#define MBEDTLS_MD5_ALT */ -/*#define MBEDTLS_POLY1305_ALT */ -/*#define MBEDTLS_RIPEMD160_ALT */ -/*#define MBEDTLS_RSA_ALT */ -/*#define MBEDTLS_SHA1_ALT */ -/*#define MBEDTLS_SHA256_ALT */ -/*#define MBEDTLS_SHA512_ALT */ +/* #define MBEDTLS_AES_ALT */ +/* #define MBEDTLS_ARIA_ALT */ +/* #define MBEDTLS_CAMELLIA_ALT */ +/* #define MBEDTLS_CCM_ALT */ +/* #define MBEDTLS_CHACHA20_ALT */ +/* #define MBEDTLS_CHACHAPOLY_ALT */ +/* #define MBEDTLS_CMAC_ALT */ +/* #define MBEDTLS_DES_ALT */ +/* #define MBEDTLS_DHM_ALT */ +/* #define MBEDTLS_ECJPAKE_ALT */ +/* #define MBEDTLS_GCM_ALT */ +/* #define MBEDTLS_NIST_KW_ALT */ +/* #define MBEDTLS_MD5_ALT */ +/* #define MBEDTLS_POLY1305_ALT */ +/* #define MBEDTLS_RIPEMD160_ALT */ +/* #define MBEDTLS_RSA_ALT */ +/* #define MBEDTLS_SHA1_ALT */ +/* #define MBEDTLS_SHA256_ALT */ +/* #define MBEDTLS_SHA512_ALT */ /* * When replacing the elliptic curve module, please consider, that it is @@ -347,19 +429,19 @@ void mbedtls_platform_free( void * ptr ); * macros as described above. The only difference is that you have to make sure * that you provide functionality for both .c files. */ -/*#define MBEDTLS_ECP_ALT */ +/* #define MBEDTLS_ECP_ALT */ /** * \def MBEDTLS_SHA256_PROCESS_ALT * - * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you + * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let Mbed TLS use you * alternate core implementation of symmetric crypto or hash function. Keep in * mind that function prototypes should remain the same. * - * This replaces only one function. The header file from mbed TLS is still + * This replaces only one function. The header file from Mbed TLS is still * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags. * - * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will + * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, Mbed TLS will * no longer provide the mbedtls_sha1_process() function, but it will still provide * the other function (using your mbedtls_sha1_process() function) and the definition * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible @@ -386,34 +468,34 @@ void mbedtls_platform_free( void * ptr ); * implementation should be provided for mbedtls_ecdsa_sign_det_ext(). * */ -/*#define MBEDTLS_MD5_PROCESS_ALT */ -/*#define MBEDTLS_RIPEMD160_PROCESS_ALT */ -/*#define MBEDTLS_SHA1_PROCESS_ALT */ -/*#define MBEDTLS_SHA256_PROCESS_ALT */ -/*#define MBEDTLS_SHA512_PROCESS_ALT */ -/*#define MBEDTLS_DES_SETKEY_ALT */ -/*#define MBEDTLS_DES_CRYPT_ECB_ALT */ -/*#define MBEDTLS_DES3_CRYPT_ECB_ALT */ -/*#define MBEDTLS_AES_SETKEY_ENC_ALT */ -/*#define MBEDTLS_AES_SETKEY_DEC_ALT */ -/*#define MBEDTLS_AES_ENCRYPT_ALT */ -/*#define MBEDTLS_AES_DECRYPT_ALT */ -/*#define MBEDTLS_ECDH_GEN_PUBLIC_ALT */ -/*#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT */ -/*#define MBEDTLS_ECDSA_VERIFY_ALT */ -/*#define MBEDTLS_ECDSA_SIGN_ALT */ -/*#define MBEDTLS_ECDSA_GENKEY_ALT */ +/* #define MBEDTLS_MD5_PROCESS_ALT */ +/* #define MBEDTLS_RIPEMD160_PROCESS_ALT */ +/* #define MBEDTLS_SHA1_PROCESS_ALT */ +/* #define MBEDTLS_SHA256_PROCESS_ALT */ +/* #define MBEDTLS_SHA512_PROCESS_ALT */ +/* #define MBEDTLS_DES_SETKEY_ALT */ +/* #define MBEDTLS_DES_CRYPT_ECB_ALT */ +/* #define MBEDTLS_DES3_CRYPT_ECB_ALT */ +/* #define MBEDTLS_AES_SETKEY_ENC_ALT */ +/* #define MBEDTLS_AES_SETKEY_DEC_ALT */ +/* #define MBEDTLS_AES_ENCRYPT_ALT */ +/* #define MBEDTLS_AES_DECRYPT_ALT */ +/* #define MBEDTLS_ECDH_GEN_PUBLIC_ALT */ +/* #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT */ +/* #define MBEDTLS_ECDSA_VERIFY_ALT */ +/* #define MBEDTLS_ECDSA_SIGN_ALT */ +/* #define MBEDTLS_ECDSA_GENKEY_ALT */ /** * \def MBEDTLS_ECP_INTERNAL_ALT * * Expose a part of the internal interface of the Elliptic Curve Point module. * - * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your + * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let Mbed TLS use your * alternative core implementation of elliptic curve arithmetic. Keep in mind * that function prototypes should remain the same. * - * This partially replaces one function. The header file from mbed TLS is still + * This partially replaces one function. The header file from Mbed TLS is still * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation * is still present and it is used for group structures not supported by the * alternative. @@ -437,11 +519,11 @@ void mbedtls_platform_free( void * ptr ); * implement optimized set up and tear down instructions. * * Example: In case you set MBEDTLS_ECP_INTERNAL_ALT and - * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac() + * MBEDTLS_ECP_DOUBLE_JAC_ALT, Mbed TLS will still provide the ecp_double_jac() * function, but will use your mbedtls_internal_ecp_double_jac() if the group * for the operation is supported by your implementation (i.e. your * mbedtls_internal_ecp_grp_capable() function returns 1 for this group). If the - * group is not supported by your implementation, then the original mbed TLS + * group is not supported by your implementation, then the original Mbed TLS * implementation of ecp_double_jac() is used instead, unless this fallback * behaviour is disabled by setting MBEDTLS_ECP_NO_FALLBACK (in which case * ecp_double_jac() will return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE). @@ -455,24 +537,24 @@ void mbedtls_platform_free( void * ptr ); * function. */ /* Required for all the functions in this section */ -/*#define MBEDTLS_ECP_INTERNAL_ALT */ +/* #define MBEDTLS_ECP_INTERNAL_ALT */ /* Turn off software fallback for curves not supported in hardware */ -/*#define MBEDTLS_ECP_NO_FALLBACK */ +/* #define MBEDTLS_ECP_NO_FALLBACK */ /* Support for Weierstrass curves with Jacobi representation */ -/*#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ -/*#define MBEDTLS_ECP_ADD_MIXED_ALT */ -/*#define MBEDTLS_ECP_DOUBLE_JAC_ALT */ -/*#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT */ -/*#define MBEDTLS_ECP_NORMALIZE_JAC_ALT */ +/* #define MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ +/* #define MBEDTLS_ECP_ADD_MIXED_ALT */ +/* #define MBEDTLS_ECP_DOUBLE_JAC_ALT */ +/* #define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT */ +/* #define MBEDTLS_ECP_NORMALIZE_JAC_ALT */ /* Support for curves with Montgomery arithmetic */ -/*#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ -/*#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ -/*#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ +/* #define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ +/* #define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ +/* #define MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ /** * \def MBEDTLS_ENTROPY_HARDWARE_ALT * - * Uncomment this macro to let mbed TLS use your own implementation of a + * Uncomment this macro to let Mbed TLS use your own implementation of a * hardware entropy collector. * * Your function must be called \c mbedtls_hardware_poll(), have the same @@ -499,7 +581,6 @@ void mbedtls_platform_free( void * ptr ); * performance if ROM access is slower than RAM access. * * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. - * */ #define MBEDTLS_AES_ROM_TABLES @@ -521,9 +602,39 @@ void mbedtls_platform_free( void * ptr ); * depends on the system and memory details. * * This option is independent of \c MBEDTLS_AES_ROM_TABLES. + */ +/* #define MBEDTLS_AES_FEWER_TABLES */ + +/** + * \def MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH + * + * Use only 128-bit keys in AES operations to save ROM. + * + * Uncomment this macro to remove support for AES operations that use 192- + * or 256-bit keys. * + * Uncommenting this macro reduces the size of AES code by ~300 bytes + * on v8-M/Thumb2. + * + * Module: library/aes.c + * + * Requires: MBEDTLS_AES_C */ -/*#define MBEDTLS_AES_FEWER_TABLES */ +/* #define MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ + +/* + * Disable plain C implementation for AES. + * + * When the plain C implementation is enabled, and an implementation using a + * special CPU feature (such as MBEDTLS_AESCE_C) is also enabled, runtime + * detection will be used to select between them. + * + * If only one implementation is present, runtime detection will not be used. + * This configuration will crash at runtime if running on a CPU without the + * necessary features. It will not build unless at least one of MBEDTLS_AESCE_C + * and/or MBEDTLS_AESNI_C is enabled & present in the build. + */ +/* #define MBEDTLS_AES_USE_HARDWARE_ONLY */ /** * \def MBEDTLS_CAMELLIA_SMALL_MEMORY @@ -532,7 +643,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this macro to use less memory for Camellia. */ -/*#define MBEDTLS_CAMELLIA_SMALL_MEMORY */ +/* #define MBEDTLS_CAMELLIA_SMALL_MEMORY */ /** * \def MBEDTLS_CHECK_RETURN_WARNING @@ -555,7 +666,7 @@ void mbedtls_platform_free( void * ptr ); * macro is not defined. To completely disable return value check * warnings, define #MBEDTLS_CHECK_RETURN with an empty expansion. */ -/*#define MBEDTLS_CHECK_RETURN_WARNING */ +/* #define MBEDTLS_CHECK_RETURN_WARNING */ /** * \def MBEDTLS_CIPHER_MODE_CBC @@ -622,7 +733,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this macro to enable the NULL cipher and ciphersuites */ -/*#define MBEDTLS_CIPHER_NULL_CIPHER */ +/* #define MBEDTLS_CIPHER_NULL_CIPHER */ /** * \def MBEDTLS_CIPHER_PADDING_PKCS7 @@ -643,9 +754,19 @@ void mbedtls_platform_free( void * ptr ); /** \def MBEDTLS_CTR_DRBG_USE_128_BIT_KEY * * Uncomment this macro to use a 128-bit key in the CTR_DRBG module. - * By default, CTR_DRBG uses a 256-bit key. + * Without this, CTR_DRBG uses a 256-bit key + * unless \c MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH is set. + */ +/* #define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ + +/** + * Enable the verified implementations of ECDH primitives from Project Everest + * (currently only Curve25519). This feature changes the layout of ECDH + * contexts and therefore is a compatibility break for applications that access + * fields of a mbedtls_ecdh_context structure directly. See also + * MBEDTLS_ECDH_LEGACY_CONTEXT in include/mbedtls/ecdh.h. */ -/*#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ +/* #define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED */ /** * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED @@ -656,17 +777,17 @@ void mbedtls_platform_free( void * ptr ); * Comment macros to disable the curve and functions for it */ /* Short Weierstrass curves (supporting ECP, ECDH, ECDSA) */ -/*#define MBEDTLS_ECP_DP_SECP192R1_ENABLED */ -/*#define MBEDTLS_ECP_DP_SECP224R1_ENABLED */ +/* #define MBEDTLS_ECP_DP_SECP192R1_ENABLED */ +/* #define MBEDTLS_ECP_DP_SECP224R1_ENABLED */ #define MBEDTLS_ECP_DP_SECP256R1_ENABLED #define MBEDTLS_ECP_DP_SECP384R1_ENABLED #define MBEDTLS_ECP_DP_SECP521R1_ENABLED -/*#define MBEDTLS_ECP_DP_SECP192K1_ENABLED */ -/*#define MBEDTLS_ECP_DP_SECP224K1_ENABLED */ -/*#define MBEDTLS_ECP_DP_SECP256K1_ENABLED */ -/*#define MBEDTLS_ECP_DP_BP256R1_ENABLED */ -/*#define MBEDTLS_ECP_DP_BP384R1_ENABLED */ -/*#define MBEDTLS_ECP_DP_BP512R1_ENABLED */ +/* #define MBEDTLS_ECP_DP_SECP192K1_ENABLED */ +/* #define MBEDTLS_ECP_DP_SECP224K1_ENABLED */ +/* #define MBEDTLS_ECP_DP_SECP256K1_ENABLED */ +/* #define MBEDTLS_ECP_DP_BP256R1_ENABLED */ +/* #define MBEDTLS_ECP_DP_BP384R1_ENABLED */ +/* #define MBEDTLS_ECP_DP_BP512R1_ENABLED */ /* Montgomery curves (supporting ECP) */ #define MBEDTLS_ECP_DP_CURVE25519_ENABLED #define MBEDTLS_ECP_DP_CURVE448_ENABLED @@ -698,13 +819,52 @@ void mbedtls_platform_free( void * ptr ); * This is useful in non-threaded environments if you want to avoid blocking * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. * - * Uncomment this macro to enable restartable ECC computations. + * This option: + * - Adds xxx_restartable() variants of existing operations in the + * following modules, with corresponding restart context types: + * - ECP (for Short Weierstrass curves only): scalar multiplication (mul), + * linear combination (muladd); + * - ECDSA: signature generation & verification; + * - PK: signature generation & verification; + * - X509: certificate chain verification. + * - Adds mbedtls_ecdh_enable_restart() in the ECDH module. + * - Changes the behaviour of TLS 1.2 clients (not servers) when using the + * ECDHE-ECDSA key exchange (not other key exchanges) to make all ECC + * computations restartable: + * - ECDH operations from the key exchange, only for Short Weierstrass + * curves, only when MBEDTLS_USE_PSA_CRYPTO is not enabled. + * - verification of the server's key exchange signature; + * - verification of the server's certificate chain; + * - generation of the client's signature if client authentication is used, + * with an ECC key/certificate. + * + * \note In the cases above, the usual SSL/TLS functions, such as + * mbedtls_ssl_handshake(), can now return + * MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS. + * + * \note When this option and MBEDTLS_USE_PSA_CRYPTO are both enabled, + * restartable operations in PK, X.509 and TLS (see above) are not + * using PSA. On the other hand, ECDH computations in TLS are using + * PSA, and are not restartable. These are temporary limitations that + * should be lifted in the future. * * \note This option only works with the default software implementation of * elliptic curve functionality. It is incompatible with * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT, MBEDTLS_ECDSA_XXX_ALT. + * + * Requires: MBEDTLS_ECP_C + * + * Uncomment this macro to enable restartable ECC computations. */ -/*#define MBEDTLS_ECP_RESTARTABLE */ +/* #define MBEDTLS_ECP_RESTARTABLE */ + +/** + * Uncomment to enable using new bignum code in the ECC modules. + * + * \warning This is currently experimental, incomplete and therefore should not + * be used in production. + */ +/* #define MBEDTLS_ECP_WITH_MPI_UINT */ /** * \def MBEDTLS_ECDSA_DETERMINISTIC @@ -738,7 +898,7 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 */ -/*#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED @@ -767,14 +927,14 @@ void mbedtls_platform_free( void * ptr ); * See dhm.h for more details. * */ -/*#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED */ +/* #define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED */ /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED * * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. * - * Requires: MBEDTLS_ECDH_C + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) * * This enables the following ciphersuites (if other requisites are * enabled as well): @@ -785,7 +945,7 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 */ -/*#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED @@ -808,7 +968,7 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 */ -/*#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED */ +#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED @@ -865,14 +1025,16 @@ void mbedtls_platform_free( void * ptr ); * See dhm.h for more details. * */ -/*#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED */ +/* #define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED */ /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED * * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. * - * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_RSA_C + * MBEDTLS_PKCS1_V15 * MBEDTLS_X509_CRT_PARSE_C * * This enables the following ciphersuites (if other requisites are @@ -895,7 +1057,9 @@ void mbedtls_platform_free( void * ptr ); * * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. * - * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C, + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) + * MBEDTLS_X509_CRT_PARSE_C * * This enables the following ciphersuites (if other requisites are * enabled as well): @@ -917,7 +1081,9 @@ void mbedtls_platform_free( void * ptr ); * * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. * - * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) + * MBEDTLS_X509_CRT_PARSE_C * * This enables the following ciphersuites (if other requisites are * enabled as well): @@ -932,14 +1098,16 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 */ -/*#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED */ +/* #define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED */ /** * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED * * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS. * - * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_X509_CRT_PARSE_C + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_RSA_C + * MBEDTLS_X509_CRT_PARSE_C * * This enables the following ciphersuites (if other requisites are * enabled as well): @@ -954,7 +1122,7 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 */ -/*#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED @@ -965,15 +1133,19 @@ void mbedtls_platform_free( void * ptr ); * Thread v1.0.0 specification; incompatible changes to the specification * might still happen. For this reason, this is disabled by default. * - * Requires: MBEDTLS_ECJPAKE_C - * MBEDTLS_SHA256_C + * Requires: MBEDTLS_ECJPAKE_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_JPAKE) + * SHA-256 (via MBEDTLS_SHA256_C or a PSA driver) * MBEDTLS_ECP_DP_SECP256R1_ENABLED * + * \warning If SHA-256 is provided only by a PSA driver, you must call + * psa_crypto_init() before the first hanshake (even if + * MBEDTLS_USE_PSA_CRYPTO is disabled). + * * This enables the following ciphersuites (if other requisites are * enabled as well): * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 */ -/*#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ +/* #define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ /** * \def MBEDTLS_PK_PARSE_EC_EXTENDED @@ -989,6 +1161,19 @@ void mbedtls_platform_free( void * ptr ); */ #define MBEDTLS_PK_PARSE_EC_EXTENDED +/** + * \def MBEDTLS_PK_PARSE_EC_COMPRESSED + * + * Enable the support for parsing public keys of type Short Weierstrass + * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX) which are using the + * compressed point format. This parsing is done through ECP module's functions. + * + * \note As explained in the description of MBEDTLS_ECP_PF_COMPRESSED (in ecp.h) + * the only unsupported curves are MBEDTLS_ECP_DP_SECP224R1 and + * MBEDTLS_ECP_DP_SECP224K1. + */ +#define MBEDTLS_PK_PARSE_EC_COMPRESSED + /** * \def MBEDTLS_ERROR_STRERROR_DUMMY * @@ -1018,7 +1203,7 @@ void mbedtls_platform_free( void * ptr ); * * Enable functions that use the filesystem. */ -/*#define MBEDTLS_FS_IO */ +/* #define MBEDTLS_FS_IO */ /** * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES @@ -1030,7 +1215,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this macro to prevent loading of default entropy functions. */ -/*#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES */ +/* #define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES */ /** * \def MBEDTLS_NO_PLATFORM_ENTROPY @@ -1057,7 +1242,7 @@ void mbedtls_platform_free( void * ptr ); * This option is only useful if both MBEDTLS_SHA256_C and * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used. */ -/*#define MBEDTLS_ENTROPY_FORCE_SHA256 */ +/* #define MBEDTLS_ENTROPY_FORCE_SHA256 */ /** * \def MBEDTLS_ENTROPY_NV_SEED @@ -1085,7 +1270,7 @@ void mbedtls_platform_free( void * ptr ); * \note The entropy collector will write to the seed file before entropy is * given to an external source, to update it. */ -/*#define MBEDTLS_ENTROPY_NV_SEED */ +/* #define MBEDTLS_ENTROPY_NV_SEED */ /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER * @@ -1097,7 +1282,7 @@ void mbedtls_platform_free( void * ptr ); * Note that this option is meant for internal use only and may be removed * without notice. */ -/*#define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ +/* #define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ /** * \def MBEDTLS_MEMORY_DEBUG @@ -1110,7 +1295,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this macro to let the buffer allocator print out error messages. */ -/*#define MBEDTLS_MEMORY_DEBUG */ +/* #define MBEDTLS_MEMORY_DEBUG */ /** * \def MBEDTLS_MEMORY_BACKTRACE @@ -1118,11 +1303,11 @@ void mbedtls_platform_free( void * ptr ); * Include backtrace information with each allocated block. * * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C - * GLIBC-compatible backtrace() an backtrace_symbols() support + * GLIBC-compatible backtrace() and backtrace_symbols() support * * Uncomment this macro to include backtrace information */ -/*#define MBEDTLS_MEMORY_BACKTRACE */ +/* #define MBEDTLS_MEMORY_BACKTRACE */ /** * \def MBEDTLS_PK_RSA_ALT_SUPPORT @@ -1131,14 +1316,14 @@ void mbedtls_platform_free( void * ptr ); * * Comment this macro to disable support for external private RSA keys. */ -/*#define MBEDTLS_PK_RSA_ALT_SUPPORT */ +/* #define MBEDTLS_PK_RSA_ALT_SUPPORT */ /** * \def MBEDTLS_PKCS1_V15 * * Enable support for PKCS#1 v1.5 encoding. * - * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C + * Requires: MBEDTLS_RSA_C * * This enables support for PKCS#1 v1.5 operations. */ @@ -1149,7 +1334,10 @@ void mbedtls_platform_free( void * ptr ); * * Enable support for PKCS#1 v2.1 encoding. * - * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C + * Requires: MBEDTLS_RSA_C + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any PKCS#1 v2.1 operation. * * This enables support for RSAES-OAEP and RSASSA-PSS operations. */ @@ -1169,7 +1357,7 @@ void mbedtls_platform_free( void * ptr ); * \warning This interface is experimental and may change or be removed * without notice. */ -/*#define MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ +/* #define MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ /** \def MBEDTLS_PSA_CRYPTO_CLIENT * @@ -1185,19 +1373,7 @@ void mbedtls_platform_free( void * ptr ); * \warning This interface is experimental and may change or be removed * without notice. */ -/*#define MBEDTLS_PSA_CRYPTO_CLIENT */ - -/** \def MBEDTLS_PSA_CRYPTO_DRIVERS - * - * Enable support for the experimental PSA crypto driver interface. - * - * Requires: MBEDTLS_PSA_CRYPTO_C - * - * \warning This interface is experimental. We intend to maintain backward - * compatibility with application code that relies on drivers, - * but the driver interfaces may change without notice. - */ -/*#define MBEDTLS_PSA_CRYPTO_DRIVERS */ +/* #define MBEDTLS_PSA_CRYPTO_CLIENT */ /** \def MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG * @@ -1223,8 +1399,8 @@ void mbedtls_platform_free( void * ptr ); * ); * ``` * The \c context value is initialized to 0 before the first call. - * The function must fill the \c output buffer with \p output_size bytes - * of random data and set \c *output_length to \p output_size. + * The function must fill the \c output buffer with \c output_size bytes + * of random data and set \c *output_length to \c output_size. * * Requires: MBEDTLS_PSA_CRYPTO_C * @@ -1235,7 +1411,7 @@ void mbedtls_platform_free( void * ptr ); * * \note This option is experimental and may be removed without notice. */ -/*#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ +/* #define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ /** * \def MBEDTLS_PSA_CRYPTO_SPM @@ -1245,11 +1421,59 @@ void mbedtls_platform_free( void * ptr ); * NSPE (Non-Secure Process Environment) and an SPE (Secure Process * Environment). * + * If you enable this option, your build environment must include a header + * file `"crypto_spe.h"` (either in the `psa` subdirectory of the Mbed TLS + * header files, or in another directory on the compiler's include search + * path). Alternatively, your platform may customize the header + * `psa/crypto_platform.h`, in which case it can skip or replace the + * inclusion of `"crypto_spe.h"`. + * * Module: library/psa_crypto.c * Requires: MBEDTLS_PSA_CRYPTO_C * */ -/*#define MBEDTLS_PSA_CRYPTO_SPM */ +/* #define MBEDTLS_PSA_CRYPTO_SPM */ + +/** + * Uncomment to enable p256-m. This is an alternative implementation of + * key generation, ECDH and (randomized) ECDSA on the curve SECP256R1. + * Compared to the default implementation: + * + * - p256-m has a much smaller code size and RAM footprint. + * - p256-m is only available via the PSA API. This includes the pk module + * when #MBEDTLS_USE_PSA_CRYPTO is enabled. + * - p256-m does not support deterministic ECDSA, EC-JPAKE, custom protocols + * over the core arithmetic, or deterministic derivation of keys. + * + * We recommend enabling this option if your application uses the PSA API + * and the only elliptic curve support it needs is ECDH and ECDSA over + * SECP256R1. + * + * If you enable this option, you do not need to enable any ECC-related + * MBEDTLS_xxx option. You do need to separately request support for the + * cryptographic mechanisms through the PSA API: + * - #MBEDTLS_PSA_CRYPTO_C and #MBEDTLS_PSA_CRYPTO_CONFIG for PSA-based + * configuration; + * - #MBEDTLS_USE_PSA_CRYPTO if you want to use p256-m from PK, X.509 or TLS; + * - #PSA_WANT_ECC_SECP_R1_256; + * - #PSA_WANT_ALG_ECDH and/or #PSA_WANT_ALG_ECDSA as needed; + * - #PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY, #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC, + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT, + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT and/or + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE as needed. + * + * \note To benefit from the smaller code size of p256-m, make sure that you + * do not enable any ECC-related option not supported by p256-m: this + * would cause the built-in ECC implementation to be built as well, in + * order to provide the required option. + * Make sure #PSA_WANT_ALG_DETERMINISTIC_ECDSA, #PSA_WANT_ALG_JPAKE and + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE, and curves other than + * SECP256R1 are disabled as they are not supported by this driver. + * Also, avoid defining #MBEDTLS_PK_PARSE_EC_COMPRESSED or + * #MBEDTLS_PK_PARSE_EC_EXTENDED as those currently require a subset of + * the built-in ECC implementation, see docs/driver-only-builds.md. + */ +/* #define MBEDTLS_PSA_P256M_DRIVER_ENABLED */ /** * \def MBEDTLS_PSA_INJECT_ENTROPY @@ -1262,7 +1486,7 @@ void mbedtls_platform_free( void * ptr ); * Requires: MBEDTLS_PSA_CRYPTO_STORAGE_C, MBEDTLS_ENTROPY_NV_SEED * */ -/*#define MBEDTLS_PSA_INJECT_ENTROPY */ +/* #define MBEDTLS_PSA_INJECT_ENTROPY */ /** * \def MBEDTLS_RSA_NO_CRT @@ -1273,14 +1497,14 @@ void mbedtls_platform_free( void * ptr ); * Uncomment this macro to disable the use of CRT in RSA. * */ -/*#define MBEDTLS_RSA_NO_CRT */ +/* #define MBEDTLS_RSA_NO_CRT */ /** * \def MBEDTLS_SELF_TEST * * Enable the checkup functions (*_self_test). */ -/*#define MBEDTLS_SELF_TEST */ +/* #define MBEDTLS_SELF_TEST */ /** * \def MBEDTLS_SHA256_SMALLER @@ -1296,7 +1520,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to enable the smaller implementation of SHA256. */ -/*#define MBEDTLS_SHA256_SMALLER */ +/* #define MBEDTLS_SHA256_SMALLER */ /** * \def MBEDTLS_SHA512_SMALLER @@ -1306,13 +1530,13 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to enable the smaller implementation of SHA512. */ -/*#define MBEDTLS_SHA512_SMALLER */ +/* #define MBEDTLS_SHA512_SMALLER */ /** * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES * * Enable sending of alert messages in case of encountered errors as per RFC. - * If you choose not to send the alert messages, mbed TLS can still communicate + * If you choose not to send the alert messages, Mbed TLS can still communicate * with other servers, only debugging of failures is harder. * * The advantage of not sending alert messages, is that no information is given @@ -1325,21 +1549,16 @@ void mbedtls_platform_free( void * ptr ); /** * \def MBEDTLS_SSL_DTLS_CONNECTION_ID * - * Enable support for the DTLS Connection ID extension - * (version draft-ietf-tls-dtls-connection-id-05, - * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05) + * Enable support for the DTLS Connection ID (CID) extension, * which allows to identify DTLS connections across changes - * in the underlying transport. + * in the underlying transport. The CID functionality is described + * in RFC 9146. * * Setting this option enables the SSL APIs `mbedtls_ssl_set_cid()`, * mbedtls_ssl_get_own_cid()`, `mbedtls_ssl_get_peer_cid()` and * `mbedtls_ssl_conf_cid()`. See the corresponding documentation for * more information. * - * \warning The Connection ID extension is still in draft state. - * We make no stability promises for the availability - * or the shape of the API controlled by this option. - * * The maximum lengths of outgoing and incoming CIDs can be configured * through the options * - MBEDTLS_SSL_CID_OUT_LEN_MAX @@ -1349,7 +1568,30 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to enable the Connection ID extension. */ -/*#define MBEDTLS_SSL_DTLS_CONNECTION_ID */ +/* #define MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + +/** + * \def MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT + * + * Defines whether RFC 9146 (default) or the legacy version + * (version draft-ietf-tls-dtls-connection-id-05, + * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05) + * is used. + * + * Set the value to 0 for the standard version, and + * 1 for the legacy draft version. + * + * \deprecated Support for the legacy version of the DTLS + * Connection ID feature is deprecated. Please + * switch to the standardized version defined + * in RFC 9146 enabled by utilizing + * MBEDTLS_SSL_DTLS_CONNECTION_ID without use + * of MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT. + * + * Requires: MBEDTLS_SSL_DTLS_CONNECTION_ID + */ +/* #define MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT 0 */ /** * \def MBEDTLS_SSL_ASYNC_PRIVATE @@ -1359,8 +1601,9 @@ void mbedtls_platform_free( void * ptr ); * module to perform private key operations instead of performing the * operation inside the library. * + * Requires: MBEDTLS_X509_CRT_PARSE_C */ -/*#define MBEDTLS_SSL_ASYNC_PRIVATE */ +/* #define MBEDTLS_SSL_ASYNC_PRIVATE */ /** * \def MBEDTLS_SSL_CONTEXT_SERIALIZATION @@ -1385,9 +1628,11 @@ void mbedtls_platform_free( void * ptr ); * saved after the handshake to allow for more efficient serialization, so if * you don't need this feature you'll save RAM by disabling it. * + * Requires: MBEDTLS_GCM_C or MBEDTLS_CCM_C or MBEDTLS_CHACHAPOLY_C + * * Comment to disable the context serialization APIs. */ -/*#define MBEDTLS_SSL_CONTEXT_SERIALIZATION */ +/* #define MBEDTLS_SSL_CONTEXT_SERIALIZATION */ /** * \def MBEDTLS_SSL_DEBUG_ALL @@ -1403,7 +1648,7 @@ void mbedtls_platform_free( void * ptr ); * a timing side-channel. * */ -/*#define MBEDTLS_SSL_DEBUG_ALL */ +/* #define MBEDTLS_SSL_DEBUG_ALL */ /** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC * @@ -1419,7 +1664,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this macro to disable support for Encrypt-then-MAC */ -#define MBEDTLS_SSL_ENCRYPT_THEN_MAC +/* #define MBEDTLS_SSL_ENCRYPT_THEN_MAC */ /** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET * @@ -1435,7 +1680,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this macro to disable support for Extended Master Secret. */ -#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET +/* #define MBEDTLS_SSL_EXTENDED_MASTER_SECRET */ /** * \def MBEDTLS_SSL_KEEP_PEER_CERTIFICATE @@ -1472,6 +1717,8 @@ void mbedtls_platform_free( void * ptr ); * it has been associated with security issues in the past and is easy to * misuse/misunderstand. * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * * Comment this to disable support for renegotiation. * * \note Even if this option is disabled, both client and server are aware @@ -1481,7 +1728,7 @@ void mbedtls_platform_free( void * ptr ); * configuration of this extension). * */ -/*#define MBEDTLS_SSL_RENEGOTIATION */ +/* #define MBEDTLS_SSL_RENEGOTIATION */ /** * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH @@ -1490,14 +1737,36 @@ void mbedtls_platform_free( void * ptr ); * * Comment this macro to disable support for the max_fragment_length extension */ +/* #define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ + +/** + * \def MBEDTLS_SSL_RECORD_SIZE_LIMIT + * + * Enable support for RFC 8449 record_size_limit extension in SSL (TLS 1.3 only). + * + * \warning This extension is currently in development and must NOT be used except + * for testing purposes. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_3 + * + * Uncomment this macro to enable support for the record_size_limit extension + */ +/* #define MBEDTLS_SSL_RECORD_SIZE_LIMIT */ /** * \def MBEDTLS_SSL_PROTO_TLS1_2 * * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). * - * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C - * (Depends on ciphersuites) + * Requires: Without MBEDTLS_USE_PSA_CRYPTO: MBEDTLS_MD_C and + * (MBEDTLS_SHA256_C or MBEDTLS_SHA384_C or + * SHA-256 or SHA-512 provided by a PSA driver) + * With MBEDTLS_USE_PSA_CRYPTO: + * PSA_WANT_ALG_SHA_256 or PSA_WANT_ALG_SHA_384 + * + * \warning If building with MBEDTLS_USE_PSA_CRYPTO, or if the hash(es) used + * are only provided by PSA drivers, you must call psa_crypto_init() before + * doing any TLS operations. * * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 */ @@ -1508,23 +1777,24 @@ void mbedtls_platform_free( void * ptr ); * * Enable support for TLS 1.3. * - * \note The support for TLS 1.3 is not comprehensive yet, in particular - * pre-shared keys are not supported. - * See docs/architecture/tls13-support.md for a description of the TLS + * \note See docs/architecture/tls13-support.md for a description of the TLS * 1.3 support that this option enables. * * Requires: MBEDTLS_SSL_KEEP_PEER_CERTIFICATE * Requires: MBEDTLS_PSA_CRYPTO_C * - * Note: even though TLS 1.3 depends on PSA Crypto, if you want it to only use - * PSA for all crypto operations, you need to also enable - * MBEDTLS_USE_PSA_CRYPTO; otherwise X.509 operations, and functions that are - * common with TLS 1.2 (record protection, running handshake hash) will still - * use non-PSA crypto. + * \note TLS 1.3 uses PSA crypto for cryptographic operations that are + * directly performed by TLS 1.3 code. As a consequence, you must + * call psa_crypto_init() before the first TLS 1.3 handshake. + * + * \note Cryptographic operations performed indirectly via another module + * (X.509, PK) or by code shared with TLS 1.2 (record protection, + * running handshake hash) only use PSA crypto if + * #MBEDTLS_USE_PSA_CRYPTO is enabled. * * Uncomment this macro to enable the support for TLS 1.3. */ -/*#define MBEDTLS_SSL_PROTO_TLS1_3 */ +#define MBEDTLS_SSL_PROTO_TLS1_3 /** * \def MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE @@ -1546,7 +1816,72 @@ void mbedtls_platform_free( void * ptr ); * effect on the build. * */ -/*#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE */ +#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED + * + * Enable TLS 1.3 PSK key exchange mode. + * + * Comment to disable support for the PSK key exchange mode in TLS 1.3. If + * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED + * + * Enable TLS 1.3 ephemeral key exchange mode. + * + * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH + * MBEDTLS_X509_CRT_PARSE_C + * and at least one of: + * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) + * MBEDTLS_PKCS1_V21 + * + * Comment to disable support for the ephemeral key exchange mode in TLS 1.3. + * If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + * + * Enable TLS 1.3 PSK ephemeral key exchange mode. + * + * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH + * + * Comment to disable support for the PSK ephemeral key exchange mode in + * TLS 1.3. If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not + * have any effect on the build. + * + */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + +/** + * \def MBEDTLS_SSL_EARLY_DATA + * + * Enable support for RFC 8446 TLS 1.3 early data. + * + * Requires: MBEDTLS_SSL_SESSION_TICKETS and either + * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED or + * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + * + * Comment this to disable support for early data. If MBEDTLS_SSL_PROTO_TLS1_3 + * is not enabled, this option does not have any effect on the build. + * + * This feature is experimental, not completed and thus not ready for + * production. + * + * \note The maximum amount of early data can be set with + * MBEDTLS_SSL_MAX_EARLY_DATA_SIZE. + * + */ +/* #define MBEDTLS_SSL_EARLY_DATA */ /** * \def MBEDTLS_SSL_PROTO_DTLS @@ -1559,7 +1894,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this macro to disable support for DTLS */ -#define MBEDTLS_SSL_PROTO_DTLS +/* #define MBEDTLS_SSL_PROTO_DTLS */ /** * \def MBEDTLS_SSL_ALPN @@ -1583,7 +1918,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this to disable anti-replay in DTLS. */ -#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +/* #define MBEDTLS_SSL_DTLS_ANTI_REPLAY */ /** * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY @@ -1601,7 +1936,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this to disable support for HelloVerifyRequest. */ -#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +/* #define MBEDTLS_SSL_DTLS_HELLO_VERIFY */ /** * \def MBEDTLS_SSL_DTLS_SRTP @@ -1632,7 +1967,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this to enable support for use_srtp extension. */ -/*#define MBEDTLS_SSL_DTLS_SRTP */ +/* #define MBEDTLS_SSL_DTLS_SRTP */ /** * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE @@ -1648,7 +1983,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this to disable support for clients reusing the source port. */ -#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +/* #define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE */ /** * \def MBEDTLS_SSL_SESSION_TICKETS @@ -1683,6 +2018,7 @@ void mbedtls_platform_free( void * ptr ); * * Requires: MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ +/* #define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH */ /** * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN @@ -1699,7 +2035,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to enable testing of the constant-flow nature of selected code. */ -/*#define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN */ +/* #define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN */ /** * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND @@ -1718,7 +2054,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to enable testing of the constant-flow nature of selected code. */ -/*#define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND */ +/* #define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND */ /** * \def MBEDTLS_TEST_HOOKS @@ -1738,7 +2074,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to enable invasive tests. */ -/*#define MBEDTLS_TEST_HOOKS */ +/* #define MBEDTLS_TEST_HOOKS */ /** * \def MBEDTLS_THREADING_ALT @@ -1749,7 +2085,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this to allow your own alternate threading implementation. */ -/*#define MBEDTLS_THREADING_ALT */ +/* #define MBEDTLS_THREADING_ALT */ /** * \def MBEDTLS_THREADING_PTHREAD @@ -1760,31 +2096,37 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment this to enable pthread mutexes. */ -/*#define MBEDTLS_THREADING_PTHREAD */ +/* #define MBEDTLS_THREADING_PTHREAD */ /** * \def MBEDTLS_USE_PSA_CRYPTO * - * Make the X.509 and TLS library use PSA for cryptographic operations, and - * enable new APIs for using keys handled by PSA Crypto. + * Make the X.509 and TLS libraries use PSA for cryptographic operations as + * much as possible, and enable new APIs for using keys handled by PSA Crypto. * * \note Development of this option is currently in progress, and parts of Mbed * TLS's X.509 and TLS modules are not ported to PSA yet. However, these parts * will still continue to work as usual, so enabling this option should not * break backwards compatibility. * - * \note See docs/use-psa-crypto.md for a complete description of what this - * option currently does, and of parts that are not affected by it so far. - * * \warning If you enable this option, you need to call `psa_crypto_init()` - * before calling any function from the SSL/TLS, X.509 or PK modules. + * before calling any function from the SSL/TLS, X.509 or PK modules, except + * for the various mbedtls_xxx_init() functions which can be called at any time. + * + * \note An important and desirable effect of this option is that it allows + * PK, X.509 and TLS to take advantage of PSA drivers. For example, enabling + * this option is what allows use of drivers for ECDSA, ECDH and EC J-PAKE in + * those modules. However, note that even with this option disabled, some code + * in PK, X.509, TLS or the crypto library might still use PSA drivers, if it + * can determine it's safe to do so; currently that's the case for hashes. + * + * \note See docs/use-psa-crypto.md for a complete description this option. * * Requires: MBEDTLS_PSA_CRYPTO_C. - * Conflicts with: MBEDTLS_ECP_RESTARTABLE * * Uncomment this to enable internal use of PSA Crypto and new associated APIs. */ -/*#define MBEDTLS_USE_PSA_CRYPTO */ +#define MBEDTLS_USE_PSA_CRYPTO /** * \def MBEDTLS_PSA_CRYPTO_CONFIG @@ -1806,10 +2148,17 @@ void mbedtls_platform_free( void * ptr ); * If the symbol #MBEDTLS_PSA_CRYPTO_CONFIG_FILE is defined, it specifies * an alternative header to include instead of include/psa/crypto_config.h. * - * This feature is still experimental and is not ready for production since - * it is not completed. + * \warning This option is experimental, in that the set of `PSA_WANT_XXX` + * symbols is not completely finalized yet, and the configuration + * tooling is not ideally adapted to having two separate configuration + * files. + * Future minor releases of Mbed TLS may make minor changes to those + * symbols, but we will endeavor to provide a transition path. + * Nonetheless, this option is considered mature enough to use in + * production, as long as you accept that you may need to make + * minor changes to psa/crypto_config.h when upgrading Mbed TLS. */ -/*#define MBEDTLS_PSA_CRYPTO_CONFIG */ +/* #define MBEDTLS_PSA_CRYPTO_CONFIG */ /** * \def MBEDTLS_VERSION_FEATURES @@ -1822,7 +2171,7 @@ void mbedtls_platform_free( void * ptr ); * * Comment this to disable run-time checking and save ROM space */ -/*#define MBEDTLS_VERSION_FEATURES */ +#define MBEDTLS_VERSION_FEATURES /** * \def MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK @@ -1839,9 +2188,11 @@ void mbedtls_platform_free( void * ptr ); * See the documentation of `mbedtls_x509_crt_verify_with_ca_cb()` and * `mbedtls_ssl_conf_ca_cb()` for more information. * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * * Uncomment to enable trusted certificate callbacks. */ -#define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK +/* #define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ /** * \def MBEDTLS_X509_REMOVE_INFO @@ -1852,7 +2203,7 @@ void mbedtls_platform_free( void * ptr ); * and other functions/constants only used by these functions, thus reducing * the code footprint by several KB. */ -/*#define MBEDTLS_X509_REMOVE_INFO */ +/* #define MBEDTLS_X509_REMOVE_INFO */ /** * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT @@ -1863,28 +2214,70 @@ void mbedtls_platform_free( void * ptr ); * Comment this macro to disallow using RSASSA-PSS in certificates. */ #define MBEDTLS_X509_RSASSA_PSS_SUPPORT -/** \} name SECTION: mbed TLS feature support */ +/** \} name SECTION: Mbed TLS feature support */ /** - * \name SECTION: mbed TLS modules + * \name SECTION: Mbed TLS modules * - * This section enables or disables entire modules in mbed TLS + * This section enables or disables entire modules in Mbed TLS * \{ */ /** * \def MBEDTLS_AESNI_C * - * Enable AES-NI support on x86-64. + * Enable AES-NI support on x86-64 or x86-32. + * + * \note AESNI is only supported with certain compilers and target options: + * - Visual Studio 2013: supported. + * - GCC, x86-64, target not explicitly supporting AESNI: + * requires MBEDTLS_HAVE_ASM. + * - GCC, x86-32, target not explicitly supporting AESNI: + * not supported. + * - GCC, x86-64 or x86-32, target supporting AESNI: supported. + * For this assembly-less implementation, you must currently compile + * `library/aesni.c` and `library/aes.c` with machine options to enable + * SSE2 and AESNI instructions: `gcc -msse2 -maes -mpclmul` or + * `clang -maes -mpclmul`. + * - Non-x86 targets: this option is silently ignored. + * - Other compilers: this option is silently ignored. + * + * \note + * Above, "GCC" includes compatible compilers such as Clang. + * The limitations on target support are likely to be relaxed in the future. * * Module: library/aesni.c * Caller: library/aes.c * - * Requires: MBEDTLS_HAVE_ASM + * Requires: MBEDTLS_HAVE_ASM (on some platforms, see note) + * + * This modules adds support for the AES-NI instructions on x86. + */ +/* #define MBEDTLS_AESNI_C */ + +/** + * \def MBEDTLS_AESCE_C + * + * Enable AES cryptographic extension support on 64-bit Arm. + * + * Module: library/aesce.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_AES_C + * + * \warning Runtime detection only works on Linux. For non-Linux operating + * system, Armv8-A Cryptographic Extensions must be supported by + * the CPU when this option is enabled. + * + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6, GCC 6.0 or MSVC 2019 version 16.11.2. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 * - * This modules adds support for the AES-NI instructions on x86-64 + * This module adds support for the AES Armv8-A Cryptographic Extensions on Aarch64 systems. */ -/*#define MBEDTLS_AESNI_C */ +/* #define MBEDTLS_AESCE_C */ /** * \def MBEDTLS_AES_C @@ -2007,6 +2400,9 @@ void mbedtls_platform_free( void * ptr ); * Enable the multi-precision integer library. * * Module: library/bignum.c + * library/bignum_core.c + * library/bignum_mod.c + * library/bignum_mod_raw.c * Caller: library/dhm.c * library/ecp.c * library/ecdsa.c @@ -2071,7 +2467,7 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 */ -/*#define MBEDTLS_CAMELLIA_C */ +/* #define MBEDTLS_CAMELLIA_C */ /** * \def MBEDTLS_ARIA_C @@ -2123,7 +2519,7 @@ void mbedtls_platform_free( void * ptr ); * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 */ -/*#define MBEDTLS_ARIA_C */ +/* #define MBEDTLS_ARIA_C */ /** * \def MBEDTLS_CCM_C @@ -2138,7 +2534,7 @@ void mbedtls_platform_free( void * ptr ); * This module enables the AES-CCM ciphersuites, if other requisites are * enabled as well. */ -/*#define MBEDTLS_CCM_C */ +/* #define MBEDTLS_CCM_C */ /** * \def MBEDTLS_CHACHA20_C @@ -2207,6 +2603,8 @@ void mbedtls_platform_free( void * ptr ); * The CTR_DRBG generator uses AES-256 by default. * To use AES-128 instead, enable \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY above. * + * \note AES-128 will be used if \c MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH is set. + * * \note To achieve a 256-bit security strength with CTR_DRBG, * you must use AES-256 *and* use sufficient entropy. * See ctr_drbg.h for more details. @@ -2233,7 +2631,7 @@ void mbedtls_platform_free( void * ptr ); * * This module provides debugging functions. */ -/*#define MBEDTLS_DEBUG_C */ +/* #define MBEDTLS_DEBUG_C */ /** * \def MBEDTLS_DES_C @@ -2246,10 +2644,10 @@ void mbedtls_platform_free( void * ptr ); * * PEM_PARSE uses DES/3DES for decrypting encrypted keys. * - * \warning DES is considered a weak cipher and its use constitutes a + * \warning DES/3DES are considered weak ciphers and their use constitutes a * security risk. We recommend considering stronger ciphers instead. */ -/*#define MBEDTLS_DES_C */ +/* #define MBEDTLS_DES_C */ /** * \def MBEDTLS_DHM_C @@ -2323,9 +2721,12 @@ void mbedtls_platform_free( void * ptr ); * This module is used by the following key exchanges: * ECJPAKE * - * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C + * Requires: MBEDTLS_ECP_C and either MBEDTLS_MD_C or MBEDTLS_PSA_CRYPTO_C + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any EC J-PAKE operations. */ -/*#define MBEDTLS_ECJPAKE_C */ +/* #define MBEDTLS_ECJPAKE_C */ /** * \def MBEDTLS_ECP_C @@ -2411,6 +2812,32 @@ void mbedtls_platform_free( void * ptr ); */ #define MBEDTLS_HMAC_DRBG_C +/** + * \def MBEDTLS_LMS_C + * + * Enable the LMS stateful-hash asymmetric signature algorithm. + * + * Module: library/lms.c + * Caller: + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * Uncomment to enable the LMS verification algorithm and public key operations. + */ +#define MBEDTLS_LMS_C + +/** + * \def MBEDTLS_LMS_PRIVATE + * + * Enable LMS private-key operations and signing code. Functions enabled by this + * option are experimental, and should not be used in production. + * + * Requires: MBEDTLS_LMS_C + * + * Uncomment to enable the LMS signature algorithm and private key operations. + */ +/* #define MBEDTLS_LMS_PRIVATE */ + /** * \def MBEDTLS_NIST_KW_C * @@ -2427,8 +2854,12 @@ void mbedtls_platform_free( void * ptr ); /** * \def MBEDTLS_MD_C * - * Enable the generic message digest layer. + * Enable the generic layer for message digest (hashing) and HMAC. * + * Requires: one of: MBEDTLS_MD5_C, MBEDTLS_RIPEMD160_C, MBEDTLS_SHA1_C, + * MBEDTLS_SHA224_C, MBEDTLS_SHA256_C, MBEDTLS_SHA384_C, + * MBEDTLS_SHA512_C, or MBEDTLS_PSA_CRYPTO_C with at least + * one hash. * Module: library/md.c * Caller: library/constant_time.c * library/ecdsa.c @@ -2484,11 +2915,11 @@ void mbedtls_platform_free( void * ptr ); * Module: library/memory_buffer_alloc.c * * Requires: MBEDTLS_PLATFORM_C - * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS) + * MBEDTLS_PLATFORM_MEMORY (to use it within Mbed TLS) * * Enable this module to enable the buffer memory allocator. */ -/*#define MBEDTLS_MEMORY_BUFFER_ALLOC_C */ +/* #define MBEDTLS_MEMORY_BUFFER_ALLOC_C */ /** * \def MBEDTLS_NET_C @@ -2501,13 +2932,13 @@ void mbedtls_platform_free( void * ptr ); * * \note See also our Knowledge Base article about porting to a new * environment: - * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS * * Module: library/net_sockets.c * * This module provides networking routines. */ -/*#define MBEDTLS_NET_C */ +/* #define MBEDTLS_NET_C */ /** * \def MBEDTLS_OID_C @@ -2544,7 +2975,7 @@ void mbedtls_platform_free( void * ptr ); * * This modules adds support for the VIA PadLock on x86. */ -/*#define MBEDTLS_PADLOCK_C */ +/* #define MBEDTLS_PADLOCK_C */ /** * \def MBEDTLS_PEM_PARSE_C @@ -2559,6 +2990,10 @@ void mbedtls_platform_free( void * ptr ); * library/x509_csr.c * * Requires: MBEDTLS_BASE64_C + * optionally MBEDTLS_MD5_C, or PSA Crypto with MD5 (see below) + * + * \warning When parsing password-protected files, if MD5 is provided only by + * a PSA driver, you must call psa_crypto_init() before the first file. * * This modules adds support for decoding / parsing PEM files. */ @@ -2634,12 +3069,32 @@ void mbedtls_platform_free( void * ptr ); * * Module: library/pkcs5.c * - * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * Requires: MBEDTLS_CIPHER_C + * Auto-enables: MBEDTLS_MD_C + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any PKCS5 operations. * * This module adds support for the PKCS#5 functions. */ #define MBEDTLS_PKCS5_C +/** + * \def MBEDTLS_PKCS7_C + * + * Enable PKCS #7 core for using PKCS #7-formatted signatures. + * RFC Link - https://tools.ietf.org/html/rfc2315 + * + * Module: library/pkcs7.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, + * MBEDTLS_X509_CRT_PARSE_C MBEDTLS_X509_CRL_PARSE_C, + * MBEDTLS_BIGNUM_C, MBEDTLS_MD_C + * + * This module is required for the PKCS #7 parsing modules. + */ +/* #define MBEDTLS_PKCS7_C */ + /** * \def MBEDTLS_PKCS12_C * @@ -2649,7 +3104,11 @@ void mbedtls_platform_free( void * ptr ); * Module: library/pkcs12.c * Caller: library/pkparse.c * - * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C and either + * MBEDTLS_MD_C or MBEDTLS_PSA_CRYPTO_C. + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any PKCS12 operations. * * This module enables PKCS#12 functions. */ @@ -2666,7 +3125,7 @@ void mbedtls_platform_free( void * ptr ); * above to be specified at runtime or compile time respectively. * * \note This abstraction layer must be enabled on Windows (including MSYS2) - * as other module rely on it for a fixed snprintf implementation. + * as other modules rely on it for a fixed snprintf implementation. * * Module: library/platform.c * Caller: Most other .c files @@ -2698,7 +3157,7 @@ void mbedtls_platform_free( void * ptr ); * or MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG. * */ -/*#define MBEDTLS_PSA_CRYPTO_C */ +#define MBEDTLS_PSA_CRYPTO_C /** * \def MBEDTLS_PSA_CRYPTO_SE_C @@ -2706,15 +3165,15 @@ void mbedtls_platform_free( void * ptr ); * Enable dynamic secure element support in the Platform Security Architecture * cryptography API. * - * \deprecated This feature is deprecated. Please switch to the driver - * interface enabled by #MBEDTLS_PSA_CRYPTO_DRIVERS. + * \deprecated This feature is deprecated. Please switch to the PSA driver + * interface. * * Module: library/psa_crypto_se.c * * Requires: MBEDTLS_PSA_CRYPTO_C, MBEDTLS_PSA_CRYPTO_STORAGE_C * */ -/*#define MBEDTLS_PSA_CRYPTO_SE_C */ +/* #define MBEDTLS_PSA_CRYPTO_SE_C */ /** * \def MBEDTLS_PSA_CRYPTO_STORAGE_C @@ -2727,7 +3186,7 @@ void mbedtls_platform_free( void * ptr ); * either MBEDTLS_PSA_ITS_FILE_C or a native implementation of * the PSA ITS interface */ -/*#define MBEDTLS_PSA_CRYPTO_STORAGE_C */ +/* #define MBEDTLS_PSA_CRYPTO_STORAGE_C */ /** * \def MBEDTLS_PSA_ITS_FILE_C @@ -2739,7 +3198,7 @@ void mbedtls_platform_free( void * ptr ); * * Requires: MBEDTLS_FS_IO */ -/*#define MBEDTLS_PSA_ITS_FILE_C */ +/* #define MBEDTLS_PSA_ITS_FILE_C */ /** * \def MBEDTLS_RIPEMD160_C @@ -2796,9 +3255,6 @@ void mbedtls_platform_free( void * ptr ); * * Enable the SHA-224 cryptographic hash algorithm. * - * Requires: MBEDTLS_SHA256_C. The library does not currently support enabling - * SHA-224 without SHA-256. - * * Module: library/sha256.c * Caller: library/md.c * library/ssl_cookie.c @@ -2812,9 +3268,6 @@ void mbedtls_platform_free( void * ptr ); * * Enable the SHA-256 cryptographic hash algorithm. * - * Requires: MBEDTLS_SHA224_C. The library does not currently support enabling - * SHA-256 without SHA-224. - * * Module: library/sha256.c * Caller: library/entropy.c * library/md.c @@ -2837,8 +3290,11 @@ void mbedtls_platform_free( void * ptr ); * \note If MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT is defined when building * for a non-Aarch64 build it will be silently ignored. * - * \note The code uses Neon intrinsics, so \c CFLAGS must be set to a minimum - * of \c -march=armv8-a+crypto. + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6 or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 * * \warning MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the * same time as MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY. @@ -2850,7 +3306,7 @@ void mbedtls_platform_free( void * ptr ); * Uncomment to have the library check for the A64 SHA-256 crypto extensions * and use them if available. */ -/*#define MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT */ +/* #define MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT */ /** * \def MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY @@ -2862,8 +3318,11 @@ void mbedtls_platform_free( void * ptr ); * \note This allows builds with a smaller code size than with * MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT * - * \note The code uses Neon intrinsics, so \c CFLAGS must be set to a minimum - * of \c -march=armv8-a+crypto. + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6 or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 * * \warning MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY cannot be defined at the same * time as MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT. @@ -2875,15 +3334,13 @@ void mbedtls_platform_free( void * ptr ); * Uncomment to have the library use the A64 SHA-256 crypto extensions * unconditionally. */ -/*#define MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ +/* #define MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ /** * \def MBEDTLS_SHA384_C * * Enable the SHA-384 cryptographic hash algorithm. * - * Requires: MBEDTLS_SHA512_C - * * Module: library/sha512.c * Caller: library/md.c * library/psa_crypto_hash.c @@ -2910,6 +3367,17 @@ void mbedtls_platform_free( void * ptr ); */ #define MBEDTLS_SHA512_C +/** + * \def MBEDTLS_SHA3_C + * + * Enable the SHA3 cryptographic hash algorithm. + * + * Module: library/sha3.c + * + * This module adds support for SHA3. + */ +#define MBEDTLS_SHA3_C + /** * \def MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT * @@ -2920,10 +3388,11 @@ void mbedtls_platform_free( void * ptr ); * \note If MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT is defined when building * for a non-Aarch64 build it will be silently ignored. * - * \note The code uses the SHA-512 Neon intrinsics, so requires GCC >= 8 or - * Clang >= 7, and \c CFLAGS must be set to a minimum of - * \c -march=armv8.2-a+sha3. An optimisation level of \c -O3 generates the - * fastest code. + * \note Minimum compiler versions for this feature are Clang 7.0, + * armclang 6.9 or GCC 8.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for + * armclang 6.9 * * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the * same time as MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY. @@ -2935,7 +3404,7 @@ void mbedtls_platform_free( void * ptr ); * Uncomment to have the library check for the A64 SHA-512 crypto extensions * and use them if available. */ -/*#define MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ +/* #define MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ /** * \def MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY @@ -2947,10 +3416,11 @@ void mbedtls_platform_free( void * ptr ); * \note This allows builds with a smaller code size than with * MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT * - * \note The code uses the SHA-512 Neon intrinsics, so requires GCC >= 8 or - * Clang >= 7, and \c CFLAGS must be set to a minimum of - * \c -march=armv8.2-a+sha3. An optimisation level of \c -O3 generates the - * fastest code. + * \note Minimum compiler versions for this feature are Clang 7.0, + * armclang 6.9 or GCC 8.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for + * armclang 6.9 * * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY cannot be defined at the same * time as MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT. @@ -2962,7 +3432,7 @@ void mbedtls_platform_free( void * ptr ); * Uncomment to have the library use the A64 SHA-512 crypto extensions * unconditionally. */ -/*#define MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ +/* #define MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ /** * \def MBEDTLS_SSL_CACHE_C @@ -2994,7 +3464,8 @@ void mbedtls_platform_free( void * ptr ); * Module: library/ssl_ticket.c * Caller: * - * Requires: MBEDTLS_CIPHER_C || MBEDTLS_USE_PSA_CRYPTO + * Requires: (MBEDTLS_CIPHER_C || MBEDTLS_USE_PSA_CRYPTO) && + * (MBEDTLS_GCM_C || MBEDTLS_CCM_C || MBEDTLS_CHACHAPOLY_C) */ #define MBEDTLS_SSL_TICKET_C @@ -3024,7 +3495,7 @@ void mbedtls_platform_free( void * ptr ); * * This module is required for SSL/TLS server support. */ -/*#define MBEDTLS_SSL_SRV */ +/* #define MBEDTLS_SSL_SRV */ /** * \def MBEDTLS_SSL_TLS_C @@ -3046,11 +3517,11 @@ void mbedtls_platform_free( void * ptr ); * \def MBEDTLS_THREADING_C * * Enable the threading abstraction layer. - * By default mbed TLS assumes it is used in a non-threaded environment or that + * By default Mbed TLS assumes it is used in a non-threaded environment or that * contexts are not shared between threads. If you do intend to use contexts * between threads, you will need to enable this layer to prevent race * conditions. See also our Knowledge Base article about threading: - * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading + * https://mbed-tls.readthedocs.io/en/latest/kb/development/thread-safety-and-multi-threading * * Module: library/threading.c * @@ -3060,7 +3531,7 @@ void mbedtls_platform_free( void * ptr ); * You will have to enable either MBEDTLS_THREADING_ALT or * MBEDTLS_THREADING_PTHREAD. * - * Enable this layer to allow use of mutexes within mbed TLS + * Enable this layer to allow use of mutexes within Mbed TLS */ #define MBEDTLS_THREADING_C #define MBEDTLS_THREADING_IMPL @@ -3084,11 +3555,11 @@ void mbedtls_platform_free( void * ptr ); * * \note See also our Knowledge Base article about porting to a new * environment: - * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS * * Module: library/timing.c */ -/*#define MBEDTLS_TIMING_C */ +/* #define MBEDTLS_TIMING_C */ /** * \def MBEDTLS_VERSION_C @@ -3099,7 +3570,7 @@ void mbedtls_platform_free( void * ptr ); * * This module provides run-time version information. */ -/*#define MBEDTLS_VERSION_C */ +#define MBEDTLS_VERSION_C /** * \def MBEDTLS_X509_USE_C @@ -3111,8 +3582,11 @@ void mbedtls_platform_free( void * ptr ); * library/x509_crt.c * library/x509_csr.c * - * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, - * MBEDTLS_PK_PARSE_C + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, + * (MBEDTLS_MD_C or MBEDTLS_USE_PSA_CRYPTO) + * + * \warning If building with MBEDTLS_USE_PSA_CRYPTO, you must call + * psa_crypto_init() before doing any X.509 operation. * * This module is required for the X.509 parsing modules. */ @@ -3169,7 +3643,11 @@ void mbedtls_platform_free( void * ptr ); * * Module: library/x509_create.c * - * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, + * (MBEDTLS_MD_C or MBEDTLS_USE_PSA_CRYPTO) + * + * \warning If building with MBEDTLS_USE_PSA_CRYPTO, you must call + * psa_crypto_init() before doing any X.509 create operation. * * This module is the basis for creating X.509 certificates and CSRs. */ @@ -3201,7 +3679,7 @@ void mbedtls_platform_free( void * ptr ); */ #define MBEDTLS_X509_CSR_WRITE_C -/** \} name SECTION: mbed TLS modules */ +/** \} name SECTION: Mbed TLS modules */ /** * \name SECTION: General configuration options @@ -3229,7 +3707,9 @@ void mbedtls_platform_free( void * ptr ); * The value of this symbol is typically a path in double quotes, either * absolute or relative to a directory on the include search path. */ -/*#define MBEDTLS_CONFIG_FILE "mbedtls/mbedtls_config.h" */ +#ifndef MBEDTLS_CONFIG_FILE + #define MBEDTLS_CONFIG_FILE "mbedtls_config_v3.5.1.h" +#endif /* MBEDTLS_CONFIG_FILE */ /** * \def MBEDTLS_USER_CONFIG_FILE @@ -3246,7 +3726,7 @@ void mbedtls_platform_free( void * ptr ); * The value of this symbol is typically a path in double quotes, either * absolute or relative to a directory on the include search path. */ -/*#define MBEDTLS_USER_CONFIG_FILE "/dev/null" */ +/* #define MBEDTLS_USER_CONFIG_FILE "/dev/null" */ /** * \def MBEDTLS_PSA_CRYPTO_CONFIG_FILE @@ -3264,7 +3744,7 @@ void mbedtls_platform_free( void * ptr ); * The value of this symbol is typically a path in double quotes, either * absolute or relative to a directory on the include search path. */ -/*#define MBEDTLS_PSA_CRYPTO_CONFIG_FILE "psa/crypto_config.h" */ +/* #define MBEDTLS_PSA_CRYPTO_CONFIG_FILE "psa/crypto_config.h" */ /** * \def MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE @@ -3281,7 +3761,54 @@ void mbedtls_platform_free( void * ptr ); * The value of this symbol is typically a path in double quotes, either * absolute or relative to a directory on the include search path. */ -/*#define MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE "/dev/null" */ +/* #define MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE "/dev/null" */ + +/** + * \def MBEDTLS_PSA_CRYPTO_PLATFORM_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_platform.h"`. This file should declare the same identifiers + * as the one in Mbed TLS, but with definitions adapted to the platform on + * which the library code will run. + * + * \note The required content of this header can vary from one version of + * Mbed TLS to the next. Integrators who provide an alternative file + * should review the changes in the original file whenever they + * upgrade Mbed TLS. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +/* #define MBEDTLS_PSA_CRYPTO_PLATFORM_FILE "psa/crypto_platform_alt.h" */ + +/** + * \def MBEDTLS_PSA_CRYPTO_STRUCT_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_struct.h"`. This file should declare the same identifiers + * as the one in Mbed TLS, but with definitions adapted to the environment + * in which the library code will run. The typical use for this feature + * is to provide alternative type definitions on the client side in + * client-server integrations of PSA crypto, where operation structures + * contain handles instead of cryptographic data. + * + * \note The required content of this header can vary from one version of + * Mbed TLS to the next. Integrators who provide an alternative file + * should review the changes in the original file whenever they + * upgrade Mbed TLS. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +/* #define MBEDTLS_PSA_CRYPTO_STRUCT_FILE "psa/crypto_struct_alt.h" */ /** \} name SECTION: General configuration options */ @@ -3306,66 +3833,89 @@ void mbedtls_platform_free( void * ptr ); * comment in the specific module. */ /* MPI / BIGNUM options */ -/*#define MBEDTLS_MPI_WINDOW_SIZE 6 / **< Maximum window size used. * / */ -/*#define MBEDTLS_MPI_MAX_SIZE 1024 / **< Maximum number of bytes for usable MPIs. * / */ +/* #define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ +/* #define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ /* CTR_DRBG options */ -/*#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 / **< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) * / */ -/*#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 / **< Interval before reseed is performed by default * / */ -/*#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 / **< Maximum number of additional input bytes * / */ -/*#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 / **< Maximum number of requested bytes per call * / */ -/*#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 / **< Maximum size of (re)seed buffer * / */ +/* #define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */ +/* #define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +/* #define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +/* #define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +/* #define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ /* HMAC_DRBG options */ -/*#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 / **< Interval before reseed is performed by default * / */ -/*#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 / **< Maximum number of additional input bytes * / */ -/*#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 / **< Maximum number of requested bytes per call * / */ -/*#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 / **< Maximum size of (re)seed buffer * / */ +/* #define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +/* #define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +/* #define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +/* #define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ /* ECP options */ -/*#define MBEDTLS_ECP_WINDOW_SIZE 4 / **< Maximum window size used * / */ -/*#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 / **< Enable fixed-point speed-up * / */ +/* #define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */ +/* #define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ /* Entropy options */ -/*#define MBEDTLS_ENTROPY_MAX_SOURCES 20 / **< Maximum number of sources supported * / */ -/*#define MBEDTLS_ENTROPY_MAX_GATHER 128 / **< Maximum amount requested from entropy sources * / */ -/*#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 / **< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released * / */ +/* #define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +/* #define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +/* #define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */ /* Memory buffer allocator options */ -/*#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 / **< Align on multiples of this value * / */ +/* #define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ /* Platform options */ -/*#define MBEDTLS_PLATFORM_STD_MEM_HDR / **< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. * / */ -/*#define MBEDTLS_PLATFORM_STD_CALLOC calloc / **< Default allocator to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_FREE free / **< Default free to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_SETBUF setbuf / **< Default setbuf to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_EXIT exit / **< Default exit to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_TIME time / **< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled * / */ -/*#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf / **< Default fprintf to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_PRINTF printf / **< Default printf to use, can be undefined * / */ +/* #define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ + +/** \def MBEDTLS_PLATFORM_STD_CALLOC + * + * Default allocator to use, can be undefined. + * It must initialize the allocated buffer memory to zeroes. + * The size of the buffer is the product of the two parameters. + * The calloc function returns either a null pointer or a pointer to the allocated space. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid input to the deallocation function. + * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. + * See the description of #MBEDTLS_PLATFORM_MEMORY for more details. + * The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. + */ +/* #define MBEDTLS_PLATFORM_STD_CALLOC calloc */ + +/** \def MBEDTLS_PLATFORM_STD_FREE + * + * Default free to use, can be undefined. + * NULL is a valid parameter, and the function must do nothing. + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. + * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC apply). + */ +/* #define MBEDTLS_PLATFORM_STD_FREE free */ +/* #define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +/* #define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -/*#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf / **< Default snprintf to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 / **< Default exit value to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 / **< Default exit value to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read / **< Default nv_seed_read function to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write / **< Default nv_seed_write function to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" / **< Seed file to read/write with default implementation * / */ - -/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */ +/* #define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */ + +/* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ /* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -#define MBEDTLS_PLATFORM_CALLOC_MACRO mbedtls_platform_calloc /**< Default allocator macro to use, can be undefined */ -#define MBEDTLS_PLATFORM_FREE_MACRO mbedtls_platform_free /**< Default free macro to use, can be undefined */ -/*#define MBEDTLS_PLATFORM_EXIT_MACRO exit / **< Default exit macro to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf / **< Default setbuf macro to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_TIME_MACRO time / **< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled * / */ -/*#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t / **< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled * / */ -/*#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf / **< Default fprintf macro to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_PRINTF_MACRO printf / **< Default printf macro to use, can be undefined * / */ +#define MBEDTLS_PLATFORM_CALLOC_MACRO mbedtls_platform_calloc /**< Default allocator macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ +#define MBEDTLS_PLATFORM_FREE_MACRO mbedtls_platform_free /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +/* #define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +/* #define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +/* #define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */ /* Note: your snprintf must correctly zero-terminate the buffer! */ -/*#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf / **< Default snprintf macro to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf / **< Default vsnprintf macro to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read / **< Default nv_seed_read function to use, can be undefined * / */ -/*#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write / **< Default nv_seed_write function to use, can be undefined * / */ +/* #define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf /**< Default vsnprintf macro to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +/* #define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ +/* #define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ /** \def MBEDTLS_CHECK_RETURN * @@ -3380,7 +3930,7 @@ void mbedtls_platform_free( void * ptr ); * If the implementation here is empty, this will effectively disable the * checking of functions' return values. */ -/*#define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) */ +/* #define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) */ /** \def MBEDTLS_IGNORE_RETURN * @@ -3388,7 +3938,7 @@ void mbedtls_platform_free( void * ptr ); * If that function call would cause a #MBEDTLS_CHECK_RETURN warning, this * warning is suppressed. */ -/*#define MBEDTLS_IGNORE_RETURN( result ) ((void) !(result)) */ +/* #define MBEDTLS_IGNORE_RETURN( result ) ((void) !(result)) */ /* PSA options */ @@ -3402,7 +3952,7 @@ void mbedtls_platform_free( void * ptr ); * #MBEDTLS_MD_SHA512 or #MBEDTLS_MD_SHA256 based on availability and * on unspecified heuristics. */ -/*#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 */ +/* #define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 */ /** \def MBEDTLS_PSA_KEY_SLOT_COUNT * Restrict the PSA library to supporting a maximum amount of simultaneously @@ -3413,11 +3963,14 @@ void mbedtls_platform_free( void * ptr ); * If this option is unset, the library will fall back to a default value of * 32 keys. */ -/*#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 */ +/* #define MBEDTLS_PSA_KEY_SLOT_COUNT 32 */ + +/* RSA OPTIONS */ +/* #define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits (Minimum possible value is 128 bits) */ /* SSL Cache options */ -/*#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 / **< 1 day * / */ -/*#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 / **< Maximum entries in cache * / */ +/* #define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ +/* #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ /* SSL options */ @@ -3440,21 +3993,21 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to set the maximum plaintext size of the incoming I/O buffer. */ -/*#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 */ +/* #define MBEDTLS_SSL_IN_CONTENT_LEN 16384 */ /** \def MBEDTLS_SSL_CID_IN_LEN_MAX * * The maximum length of CIDs used for incoming DTLS messages. * */ -/*#define MBEDTLS_SSL_CID_IN_LEN_MAX 32 */ +/* #define MBEDTLS_SSL_CID_IN_LEN_MAX 32 */ /** \def MBEDTLS_SSL_CID_OUT_LEN_MAX * * The maximum length of CIDs used for outgoing DTLS messages. * */ -/*#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 */ +/* #define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 */ /** \def MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY * @@ -3470,7 +4023,7 @@ void mbedtls_platform_free( void * ptr ); * Note: On systems lacking division instructions, * a power of two should be preferred. */ -/*#define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 */ +/* #define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 */ /** \def MBEDTLS_SSL_OUT_CONTENT_LEN * @@ -3490,7 +4043,7 @@ void mbedtls_platform_free( void * ptr ); * * Uncomment to set the maximum plaintext size of the outgoing I/O buffer. */ -/*#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 */ +/* #define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 */ /** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING * @@ -3507,21 +4060,10 @@ void mbedtls_platform_free( void * ptr ); * while buffering multiple smaller handshake messages. * */ -/*#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 */ +/* #define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 */ -/*#define MBEDTLS_PSK_MAX_LEN 32 / **< Max size of TLS pre-shared keys, in bytes (default 256 bits) * / */ -/*#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 / **< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued * / */ - -/** \def MBEDTLS_TLS_EXT_CID - * - * At the time of writing, the CID extension has not been assigned its - * final value. Set this configuration option to make Mbed TLS use a - * different value. - * - * A future minor revision of Mbed TLS may change the default value of - * this option to match evolving standards and usage. - */ -/*#define MBEDTLS_TLS_EXT_CID 254 */ +/* #define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) */ +/* #define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ /** * Complete list of ciphersuites to use, in order of preference. @@ -3535,58 +4077,128 @@ void mbedtls_platform_free( void * ptr ); * * The value below is only an example, not the default. */ -/*#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 */ +/* #define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 */ -/* X509 options */ -/*#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 / **< Maximum number of intermediate CAs in a verification chain. * / */ -/*#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 / **< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). * / */ +/** + * \def MBEDTLS_SSL_MAX_EARLY_DATA_SIZE + * + * The default maximum amount of 0-RTT data. See the documentation of + * \c mbedtls_ssl_tls13_conf_max_early_data_size() for more information. + * + * It must be positive and smaller than UINT32_MAX. + * + * If MBEDTLS_SSL_EARLY_DATA is not defined, this default value does not + * have any impact on the build. + * + * This feature is experimental, not completed and thus not ready for + * production. + * + */ +/* #define MBEDTLS_SSL_MAX_EARLY_DATA_SIZE 1024 */ /** - * Uncomment the macro to let mbed TLS use your alternate implementation of - * mbedtls_platform_zeroize(). This replaces the default implementation in - * platform_util.c. + * \def MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE + * + * Maximum time difference in milliseconds tolerated between the age of a + * ticket from the server and client point of view. + * From the client point of view, the age of a ticket is the time difference + * between the time when the client proposes to the server to use the ticket + * (time of writing of the Pre-Shared Key Extension including the ticket) and + * the time the client received the ticket from the server. + * From the server point of view, the age of a ticket is the time difference + * between the time when the server receives a proposition from the client + * to use the ticket and the time when the ticket was created by the server. + * The server age is expected to be always greater than the client one and + * MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE defines the + * maximum difference tolerated for the server to accept the ticket. + * This is not used in TLS 1.2. * - * mbedtls_platform_zeroize() is a widely used function across the library to - * zero a block of memory. The implementation is expected to be secure in the - * sense that it has been written to prevent the compiler from removing calls - * to mbedtls_platform_zeroize() as part of redundant code elimination - * optimizations. However, it is difficult to guarantee that calls to - * mbedtls_platform_zeroize() will not be optimized by the compiler as older - * versions of the C language standards do not provide a secure implementation - * of memset(). Therefore, MBEDTLS_PLATFORM_ZEROIZE_ALT enables users to - * configure their own implementation of mbedtls_platform_zeroize(), for - * example by using directives specific to their compiler, features from newer - * C standards (e.g using memset_s() in C11) or calling a secure memset() from - * their system (e.g explicit_bzero() in BSD). */ -/*#define MBEDTLS_PLATFORM_ZEROIZE_ALT */ +/* #define MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE 6000 */ /** - * Uncomment the macro to let Mbed TLS use your alternate implementation of - * mbedtls_platform_gmtime_r(). This replaces the default implementation in - * platform_util.c. + * \def MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH * - * gmtime() is not a thread-safe function as defined in the C standard. The - * library will try to use safer implementations of this function, such as - * gmtime_r() when available. However, if Mbed TLS cannot identify the target - * system, the implementation of mbedtls_platform_gmtime_r() will default to - * using the standard gmtime(). In this case, calls from the library to - * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex - * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the - * library are also guarded with this mutex to avoid race conditions. However, - * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will - * unconditionally use the implementation for mbedtls_platform_gmtime_r() - * supplied at compile time. + * Size in bytes of a ticket nonce. This is not used in TLS 1.2. + * + * This must be less than 256. */ -/*#define MBEDTLS_PLATFORM_GMTIME_R_ALT */ +/* #define MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH 32 */ /** - * Enable the verified implementations of ECDH primitives from Project Everest - * (currently only Curve25519). This feature changes the layout of ECDH - * contexts and therefore is a compatibility break for applications that access - * fields of a mbedtls_ecdh_context structure directly. See also - * MBEDTLS_ECDH_LEGACY_CONTEXT in include/mbedtls/ecdh.h. + * \def MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS + * + * Default number of NewSessionTicket messages to be sent by a TLS 1.3 server + * after handshake completion. This is not used in TLS 1.2 and relevant only if + * the MBEDTLS_SSL_SESSION_TICKETS option is enabled. + * */ -/*#define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED */ +/* #define MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS 1 */ + +/* X509 options */ +/* #define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */ +/* #define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */ /** \} name SECTION: Module configuration options */ + +#if 0 + #ifndef MBEDTLS_SSL_PROTO_TLS1_2 + #ifdef MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_RSA_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_PSK_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED */ + + #ifdef MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + #error This option is undef'd in build_info.h + #endif /* MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ + #endif /* MBEDTLS_SSL_PROTO_TLS1_2*/ +#endif /* if 0 */ + +#ifdef MBEDTLS_USE_PSA_CRYPTO + #ifdef MBEDTLS_PSA_CRYPTO_CONFIG + #include MBEDTLS_PSA_CRYPTO_CONFIG + #else + #include "mbedtls/config_psa.h" + #endif /* MBEDTLS_PSA_CRYPTO_CONFIG */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#include "mbedtls/config_adjust_legacy_crypto.h" + +#include "mbedtls/check_config.h" + +#endif /* __FREERTOS_MBEDTLS_CONFIG__*/ diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/coreHTTP/coreHTTP.vcxproj b/FreeRTOS-Plus/VisualStudio_StaticProjects/coreHTTP/coreHTTP.vcxproj index 8f0b76ce500..b1010322563 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/coreHTTP/coreHTTP.vcxproj +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/coreHTTP/coreHTTP.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - StaticLibrary - false - v142 - true - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - false - v142 - true - Unicode - @@ -83,18 +41,6 @@ - - - - - - - - - - - - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories);$(PublicIncludeDirectories) @@ -104,22 +50,6 @@ ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories);$(PublicIncludeDirectories) true - - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories);$(PublicIncludeDirectories) - true - - - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories);$(PublicIncludeDirectories) - true - - - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories);$(PublicIncludeDirectories) - true - - - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories);$(PublicIncludeDirectories) - true - false @@ -151,70 +81,6 @@ true - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - true - true - - - - - Level3 - true - _CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - _CRT_SECURE_NO_WARNINGS;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - true - true - _CRT_SECURE_NO_WARNINGS;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\Application-Protocols\coreHTTP\source\include;..\..\Source\Application-Protocols\coreHTTP\source\dependency\3rdparty\llhttp\include;..\..\Source\Application-Protocols\coreHTTP\source\interface;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - true - true - - diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/corePKCS11/corePKCS11.vcxproj b/FreeRTOS-Plus/VisualStudio_StaticProjects/corePKCS11/corePKCS11.vcxproj index e28c2d72cc7..00cd8b5bf4a 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/corePKCS11/corePKCS11.vcxproj +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/corePKCS11/corePKCS11.vcxproj @@ -5,26 +5,10 @@ Debug_with_Libslirp Win32 - - Debug_with_Libslirp - x64 - Debug Win32 - - Release - Win32 - - - Debug - x64 - - - Release - x64 - 16.0 @@ -46,32 +30,6 @@ v142 Unicode - - StaticLibrary - false - v142 - true - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - true - v142 - Unicode - - - StaticLibrary - false - v142 - true - Unicode - @@ -83,50 +41,22 @@ - - - - - - - - - - - - - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\ + ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11\published\2-40-errata-1;.\ true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\ - true - - - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\ - true - - - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\ - true - - - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\ - true - - - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\ + ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11\published\2-40-errata-1;.\ true Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + WIN32;WIN32_LEAN_AND_MEAN;MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\;%(AdditionalIncludeDirectories) + ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11\published\2-40-errata-1;.\;%(AdditionalIncludeDirectories) true @@ -138,77 +68,13 @@ Level3 true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - true - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\;%(AdditionalIncludeDirectories) - true - - - Console - true - - - - - Level3 - true - true - true - MBEDTLS_CONFIG_FILE="mbedtls_config_v3.2.1.h";NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MBEDTLS_CONFIG_FILE="mbedtls_config_v3.5.1.h";WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) true - ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11;.\;%(AdditionalIncludeDirectories) + ..\..\Source\corePKCS11\source\include;..\..\Source\corePKCS11\source\portable\os;..\..\Source\corePKCS11\source\portable\os\freertos_winsim;..\..\Source\corePKCS11\source\dependency\3rdparty\mbedtls_utils;..\..\Source\corePKCS11\source\dependency\3rdparty\pkcs11\published\2-40-errata-1;.\;%(AdditionalIncludeDirectories) true Console - true - true true diff --git a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h index 1f9cca0f2ab..e979be9430d 100644 --- a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c index c6701927082..710fe151b72 100644 --- a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/main.c b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/main.c index 062680c3e93..646fbe323c3 100644 --- a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/main.c +++ b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -25,12 +25,12 @@ */ /* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used. + */ /* @@ -84,44 +84,44 @@ /*-----------------------------------------------------------*/ /* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) -#define mainCOM_TEST_LED ( 5 ) +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 5 ) /* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainON_BOARD_LED_BIT ( ( unsigned long ) 7 ) + * error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned long ) 7 ) /* Constants used by the vMemCheckTask() task. */ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) -#define mainNO_TASK ( 0 ) +#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) +#define mainNO_TASK ( 0 ) /* The size of the memory blocks allocated by the vMemCheckTask() task. */ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) -#define MAX_WAIT_STATES 8 +#define MAX_WAIT_STATES 8 static const unsigned long ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] = { - WaitState1,/* There is no "zero wait state" value, so use one wait state */ - WaitState1, - WaitState2, - WaitState3, - WaitState4, - WaitState5, - WaitState6, - WaitState7, - WaitState8 + WaitState1, /* There is no "zero wait state" value, so use one wait state */ + WaitState1, + WaitState2, + WaitState3, + WaitState4, + WaitState5, + WaitState6, + WaitState7, + WaitState8 }; /*-----------------------------------------------------------*/ @@ -136,14 +136,14 @@ static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Dynamically created and deleted during each cycle of the vErrorChecks() * task. This is done to check the operation of the memory allocator. * See the top of vErrorChecks for more details. */ -static void vMemCheckTask( void *pvParameters ); +static void vMemCheckTask( void * pvParameters ); /* * Configure the processor for use with the Olimex demo board. This includes @@ -158,309 +158,312 @@ static void prvSetupHardware( void ); */ int main( void ) { - /* Setup the hardware for use with the Olimex demo board. */ - prvSetupHardware(); - - /* Start the demo/test application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + * + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -unsigned long ulMemCheckTaskRunningCount; -TaskHandle_t xCreatedTask; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. - - In addition to the standard tests the memory allocator is tested through - the dynamic creation and deletion of a task each cycle. Each time the - task is created memory must be allocated for its stack. When the task is - deleted this memory is returned to the heap. If the task cannot be created - then it is likely that the memory allocation failed. */ - - for( ;; ) - { - /* Reset xCreatedTask. This is modified by the task about to be - created so we can tell if it is executing correctly or not. */ - xCreatedTask = mainNO_TASK; - - /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a - parameter. */ - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - if( xTaskCreate( vMemCheckTask, "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - /* Could not create the task - we have probably run out of heap. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - /* Check all the standard demo application tasks are executing without - error. ulMemCheckTaskRunningCount is checked to ensure it was - modified by the task just deleted. */ - if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* The toggle rate of the LED depends on how long this task delays for. - An error reduces the delay period and so increases the toggle rate. */ - vParTestToggleLED( mainON_BOARD_LED_BIT ); - } + TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + unsigned long ulMemCheckTaskRunningCount; + TaskHandle_t xCreatedTask; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + * the on board LED flash rate will increase. + * + * In addition to the standard tests the memory allocator is tested through + * the dynamic creation and deletion of a task each cycle. Each time the + * task is created memory must be allocated for its stack. When the task is + * deleted this memory is returned to the heap. If the task cannot be created + * then it is likely that the memory allocation failed. */ + + for( ; ; ) + { + /* Reset xCreatedTask. This is modified by the task about to be + * created so we can tell if it is executing correctly or not. */ + xCreatedTask = mainNO_TASK; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + * parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + + if( xTaskCreate( vMemCheckTask, "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + * error. ulMemCheckTaskRunningCount is checked to ensure it was + * modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* The toggle rate of the LED depends on how long this task delays for. + * An error reduces the delay period and so increases the toggle rate. */ + vParTestToggleLED( mainON_BOARD_LED_BIT ); + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -long lCount; - - #ifdef RUN_FROM_ROM - { - portFLOAT nsecsPerClockTick; - long lNumWaitStates; - unsigned long ulCSRWaitValue; - - /* We are compiling to run from ROM (either on-chip or off-chip flash). - Leave the RAM/flash mapped the way they are on reset - (flash @ 0x00000000, RAM @ 0x00300000), and set up the - proper flash wait states (starts out at the maximum number - of wait states on reset, so we should be able to reduce it). - Most of this code will probably get removed by the compiler - if optimization is enabled, since these calculations are - based on constants. But the compiler should still produce - a correct wait state register value. */ - nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ; - lNumWaitStates = ( long )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1; - - if( lNumWaitStates < 0 ) - { - lNumWaitStates = 0; - } - - if( lNumWaitStates > MAX_WAIT_STATES ) - { - lNumWaitStates = MAX_WAIT_STATES; - } - - ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ]; - ulCSRWaitValue = WaitState5; - - AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable - | PageSize1M | tDF_0cycle - | ByteWriteAccessType | CSEnable - | 0x00000000 /* Base Address */; - } - #else /* else we are compiling to run from on-chip RAM */ - { - /* If compiling to run from RAM, we expect the on-chip RAM to already - be mapped at 0x00000000. This is typically done with an initialization - script for the JTAG emulator you are using to download and run the - demo application. So there is nothing to do here in this case. */ - } - #endif - - /* Disable all interrupts at the AIC level initially... */ - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - - /* Set all SVR and SMR entries to default values (start with a clean slate)... */ - for( lCount = 0; lCount < 32; lCount++ ) - { - AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0; - AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED; - } - - /* Disable clocks to all peripherals initially... */ - AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF; - - /* Clear all interrupts at the AIC level initially... */ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - - /* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out - nIRQ */ - for( lCount = 0; lCount < 8; lCount++ ) - { - AT91C_BASE_AIC->AIC_EOICR = 0; - } - - /* Initialise LED outputs. */ - vParTestInitialise(); + long lCount; + + #ifdef RUN_FROM_ROM + { + portFLOAT nsecsPerClockTick; + long lNumWaitStates; + unsigned long ulCSRWaitValue; + + /* We are compiling to run from ROM (either on-chip or off-chip flash). + * Leave the RAM/flash mapped the way they are on reset + * (flash @ 0x00000000, RAM @ 0x00300000), and set up the + * proper flash wait states (starts out at the maximum number + * of wait states on reset, so we should be able to reduce it). + * Most of this code will probably get removed by the compiler + * if optimization is enabled, since these calculations are + * based on constants. But the compiler should still produce + * a correct wait state register value. */ + nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ; + lNumWaitStates = ( long ) ( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1; + + if( lNumWaitStates < 0 ) + { + lNumWaitStates = 0; + } + + if( lNumWaitStates > MAX_WAIT_STATES ) + { + lNumWaitStates = MAX_WAIT_STATES; + } + + ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ]; + ulCSRWaitValue = WaitState5; + + AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable + | PageSize1M | tDF_0cycle + | ByteWriteAccessType | CSEnable + | 0x00000000 /* Base Address */; + } + #else /* else we are compiling to run from on-chip RAM */ + { + /* If compiling to run from RAM, we expect the on-chip RAM to already + * be mapped at 0x00000000. This is typically done with an initialization + * script for the JTAG emulator you are using to download and run the + * demo application. So there is nothing to do here in this case. */ + } + #endif /* ifdef RUN_FROM_ROM */ + + /* Disable all interrupts at the AIC level initially... */ + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + + /* Set all SVR and SMR entries to default values (start with a clean slate)... */ + for( lCount = 0; lCount < 32; lCount++ ) + { + AT91C_BASE_AIC->AIC_SVR[ lCount ] = ( unsigned long ) 0; + AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED; + } + + /* Disable clocks to all peripherals initially... */ + AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF; + + /* Clear all interrupts at the AIC level initially... */ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + + /* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out + * nIRQ */ + for( lCount = 0; lCount < 8; lCount++ ) + { + AT91C_BASE_AIC->AIC_EOICR = 0; + } + + /* Initialise LED outputs. */ + vParTestInitialise(); } /*-----------------------------------------------------------*/ static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount ) { -long lReturn = ( long ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) - { - /* The vMemCheckTask did not increment the counter - it must - have failed. */ - lReturn = ( long ) pdFAIL; - } - - return lReturn; + long lReturn = ( long ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + * have failed. */ + lReturn = ( long ) pdFAIL; + } + + return lReturn; } /*-----------------------------------------------------------*/ -static void vMemCheckTask( void *pvParameters ) +static void vMemCheckTask( void * pvParameters ) { -unsigned long *pulMemCheckTaskRunningCounter; -void *pvMem1, *pvMem2, *pvMem3; -static long lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - else - { - /* There has been an error so reset the counter so the check task - can tell that an error occurred. */ - *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - vTaskSuspendAll(); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll(); - } + unsigned long * pulMemCheckTaskRunningCounter; + void * pvMem1, * pvMem2, * pvMem3; + static long lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + * vErrorChecks task to check the operation of the memory allocator. Each time + * the task is created memory is allocated for the stack and TCB. Each time + * the task is deleted this memory is returned to the heap. This task itself + * exercises the allocator by allocating and freeing blocks. + * + * The task executes at the idle priority so does not require a delay. + * + * pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + * vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; + + for( ; ; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* There has been an error so reset the counter so the check task + * can tell that an error occurred. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + * exercise. This has to be in a critical section to ensure the + * task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } } - diff --git a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serial.c b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serial.c index 38472470f73..deec31e5480 100644 --- a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c index 0c1b521ed23..07bb9308f18 100644 --- a/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c +++ b/FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h index 3c89e24db8e..6d6c531c6dc 100644 --- a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c index b116faff9de..3572266264f 100644 --- a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c index 927f28e1044..52097be1ee9 100644 --- a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c +++ b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/main.c b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/main.c index 92bfa084d97..abcf19d3e0a 100644 --- a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/main.c +++ b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -24,29 +24,29 @@ * */ -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ +/* + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used. + */ /* * Creates all the demo application tasks, then starts the scheduler. The WEB * documentation provides more details of the demo application tasks. The SAM7 * includes a sample USB that emulates a Joystick input to a USB host. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have + * the last time the check task executed. If all the count variables have * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time + * toggles the onboard LED. Should any task contain an error at any time * the LED toggle rate will change from 3 seconds to 500ms. * */ @@ -70,29 +70,29 @@ #include "USB/USBSample.h" /* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Constants required by the 'Check' task. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainCHECK_TASK_LED ( 3 ) +#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) +#define mainCHECK_TASK_LED ( 3 ) /* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) -#define mainCOM_TEST_LED ( 4 ) /* Off the board. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 4 ) /* Off the board. */ /* - * The task that executes at the highest priority and calls + * The task that executes at the highest priority and calls * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Configure the processor for use with the Atmel demo board. Setup is minimal @@ -111,136 +111,133 @@ static long prvCheckOtherTasksAreStillRunning( void ); /*-----------------------------------------------------------*/ /* - * Starts all the other tasks, then starts the scheduler. + * Starts all the other tasks, then starts the scheduler. */ void main( void ) { - /* Setup any hardware that has not already been configured by the low - level init routines. */ - prvSetupHardware(); - - /* Initialise the LED outputs for use by the demo application tasks. */ - vParTestInitialise(); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Also start the USB demo which is just for the SAM7. */ - xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - return; + /* Setup any hardware that has not already been configured by the low + * level init routines. */ + prvSetupHardware(); + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Also start the USB demo which is just for the SAM7. */ + xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + * + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* When using the JTAG debugger the hardware is not always initialised to - the correct default state. This line just ensures that this does not - cause all interrupts to be masked at the start. */ - AT91C_BASE_AIC->AIC_EOICR = 0; - - /* Most setup is performed by the low level init function called from the - startup asm file. */ - - /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as - well as the UART Tx line. */ - AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ); - - /* Enable the peripheral clock. */ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ); + /* When using the JTAG debugger the hardware is not always initialised to + * the correct default state. This line just ensures that this does not + * cause all interrupts to be masked at the start. */ + AT91C_BASE_AIC->AIC_EOICR = 0; + + /* Most setup is performed by the low level init function called from the + * startup asm file. */ + + /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as + * well as the UART Tx line. */ + AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ); + + /* Enable the peripheral clock. */ + AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ); } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } + TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + * the on board LED flash rate will increase. */ + + for( ; ; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + * error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } } /*-----------------------------------------------------------*/ static long prvCheckOtherTasksAreStillRunning( void ) { -long lReturn = ( long ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - return lReturn; + long lReturn = ( long ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + return lReturn; } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c index d777cf6b750..2aa6ed50d35 100644 --- a/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h index 27e1e9c55be..e384a613b05 100644 --- a/FreeRTOS/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c index 0a91c7e9e4d..0cc79a5dd91 100644 --- a/FreeRTOS/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2106_GCC/main.c b/FreeRTOS/Demo/ARM7_LPC2106_GCC/main.c index 01b78ec963a..14b71173ae8 100644 --- a/FreeRTOS/Demo/ARM7_LPC2106_GCC/main.c +++ b/FreeRTOS/Demo/ARM7_LPC2106_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -25,12 +25,12 @@ */ /* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used. + */ /* @@ -58,16 +58,16 @@ */ /* - Changes from V2.4.2 - - + The vErrorChecks() task now dynamically creates then deletes a task each - cycle. This tests the operation of the memory allocator. - - Changes from V2.5.2 - - + vParTestInitialise() is called during initialisation to ensure all the - LED's start off. -*/ + * Changes from V2.4.2 + * + + The vErrorChecks() task now dynamically creates then deletes a task each + + cycle. This tests the operation of the memory allocator. + + + + Changes from V2.5.2 + + + + vParTestInitialise() is called during initialisation to ensure all the + + LED's start off. + */ /* Standard includes. */ @@ -93,53 +93,53 @@ /*-----------------------------------------------------------*/ /* Constants to setup I/O. */ -#define mainTX_ENABLE ( ( unsigned long ) 0x0001 ) -#define mainRX_ENABLE ( ( unsigned long ) 0x0004 ) -#define mainP0_14 ( ( unsigned long ) 0x4000 ) -#define mainJTAG_PORT ( ( unsigned long ) 0x3E0000UL ) +#define mainTX_ENABLE ( ( unsigned long ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned long ) 0x0004 ) +#define mainP0_14 ( ( unsigned long ) 0x4000 ) +#define mainJTAG_PORT ( ( unsigned long ) 0x3E0000UL ) /* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned char ) 0x0003 ) -#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned long ) 0x0400 ) +#define mainPLL_MUL_4 ( ( unsigned char ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned long ) 0x0400 ) /* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 ) +#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 ) /* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) +#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) /* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) -#define mainCOM_TEST_LED ( 3 ) +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) /* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainON_BOARD_LED_BIT ( ( unsigned long ) 0x80 ) + * error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned long ) 0x80 ) /* Constants used by the vMemCheckTask() task. */ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) -#define mainNO_TASK ( 0 ) +#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) +#define mainNO_TASK ( 0 ) /* The size of the memory blocks allocated by the vMemCheckTask() task. */ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) /*-----------------------------------------------------------*/ @@ -160,14 +160,14 @@ static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Dynamically created and deleted during each cycle of the vErrorChecks() * task. This is done to check the operation of the memory allocator. * See the top of vErrorChecks for more details. */ -static void vMemCheckTask( void *pvParameters ); +static void vMemCheckTask( void * pvParameters ); /* * Configure the processor for use with the Olimex demo board. This includes @@ -182,288 +182,291 @@ static void prvSetupHardware( void ); */ int main( void ) { - /* Setup the hardware for use with the Olimex demo board. */ - prvSetupHardware(); - - /* Start the demo/test application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + * + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -unsigned long ulMemCheckTaskRunningCount; -TaskHandle_t xCreatedTask; - - /* The parameters are not used in this function. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. - - In addition to the standard tests the memory allocator is tested through - the dynamic creation and deletion of a task each cycle. Each time the - task is created memory must be allocated for its stack. When the task is - deleted this memory is returned to the heap. If the task cannot be created - then it is likely that the memory allocation failed. */ - - for( ;; ) - { - /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a - parameter. */ - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - xCreatedTask = mainNO_TASK; - - if( xTaskCreate( vMemCheckTask, "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - /* Could not create the task - we have probably run out of heap. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - /* Check all the standard demo application tasks are executing without - error. ulMemCheckTaskRunningCount is checked to ensure it was - modified by the task just deleted. */ - if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - prvToggleOnBoardLED(); - } + TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + unsigned long ulMemCheckTaskRunningCount; + TaskHandle_t xCreatedTask; + + /* The parameters are not used in this function. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + * the on board LED flash rate will increase. + * + * In addition to the standard tests the memory allocator is tested through + * the dynamic creation and deletion of a task each cycle. Each time the + * task is created memory must be allocated for its stack. When the task is + * deleted this memory is returned to the heap. If the task cannot be created + * then it is likely that the memory allocation failed. */ + + for( ; ; ) + { + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + * parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + xCreatedTask = mainNO_TASK; + + if( xTaskCreate( vMemCheckTask, "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + * error. ulMemCheckTaskRunningCount is checked to ensure it was + * modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + prvToggleOnBoardLED(); + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - #ifdef RUN_FROM_RAM - /* Remap the interrupt vectors to RAM if we are are running from RAM. */ - SCB_MEMMAP = 2; - #endif - - /* Configure the RS2332 pins. All other pins remain at their default of 0. */ - PCB_PINSEL0 |= mainTX_ENABLE; - PCB_PINSEL0 |= mainRX_ENABLE; - - /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. - The JTAG pins are left as input as I'm not sure what will happen if the - Wiggler is connected after powerup - not that it would be a good idea to - do that anyway. */ - GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT ); - - /* Setup the PLL to multiply the XTAL input by 4. */ - SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - SCB_PLLCON = mainPLL_ENABLE; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - SCB_PLLCON = mainPLL_CONNECT; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAM_TIM = mainMAM_TIM_3; - MAM_CR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - SCB_VPBDIV = mainBUS_CLK_FULL; - - /* Initialise LED outputs. */ - vParTestInitialise(); + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PCB_PINSEL0 |= mainTX_ENABLE; + PCB_PINSEL0 |= mainRX_ENABLE; + + /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. + * The JTAG pins are left as input as I'm not sure what will happen if the + * Wiggler is connected after powerup - not that it would be a good idea to + * do that anyway. */ + GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT ); + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + * bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ) + { + } + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + * PLL used. It is possible faster overall performance could be obtained by + * tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; + + /* Initialise LED outputs. */ + vParTestInitialise(); } /*-----------------------------------------------------------*/ void prvToggleOnBoardLED( void ) { -unsigned long ulState; - - ulState = GPIO0_IOPIN; - if( ulState & mainON_BOARD_LED_BIT ) - { - GPIO_IOCLR = mainON_BOARD_LED_BIT; - } - else - { - GPIO_IOSET = mainON_BOARD_LED_BIT; - } + unsigned long ulState; + + ulState = GPIO0_IOPIN; + + if( ulState & mainON_BOARD_LED_BIT ) + { + GPIO_IOCLR = mainON_BOARD_LED_BIT; + } + else + { + GPIO_IOSET = mainON_BOARD_LED_BIT; + } } /*-----------------------------------------------------------*/ static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount ) { -long lReturn = ( long ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) - { - /* The vMemCheckTask did not increment the counter - it must - have failed. */ - lReturn = ( long ) pdFAIL; - } - - return lReturn; + long lReturn = ( long ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + * have failed. */ + lReturn = ( long ) pdFAIL; + } + + return lReturn; } /*-----------------------------------------------------------*/ -static void vMemCheckTask( void *pvParameters ) +static void vMemCheckTask( void * pvParameters ) { -unsigned long *pulMemCheckTaskRunningCounter; -void *pvMem1, *pvMem2, *pvMem3; -static long lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - vTaskSuspendAll(); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll(); - } + unsigned long * pulMemCheckTaskRunningCounter; + void * pvMem1, * pvMem2, * pvMem3; + static long lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + * vErrorChecks task to check the operation of the memory allocator. Each time + * the task is created memory is allocated for the stack and TCB. Each time + * the task is deleted this memory is returned to the heap. This task itself + * exercises the allocator by allocating and freeing blocks. + * + * The task executes at the idle priority so does not require a delay. + * + * pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + * vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; + + for( ; ; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + + /* Allocate some memory - just to give the allocator some extra + * exercise. This has to be in a critical section to ensure the + * task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } } - - - diff --git a/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serial.c b/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serial.c index c5a7eaca8d0..2fad57072aa 100644 --- a/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serialISR.c b/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serialISR.c index 1a4762fbe93..baa625ea136 100644 --- a/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serialISR.c +++ b/FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serialISR.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h index 2402ab62750..1afd1f50ace 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c index 2097204e99d..ea1bc0892d7 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2129_IAR/main.c b/FreeRTOS/Demo/ARM7_LPC2129_IAR/main.c index 7bb5f826cd4..a0954a8c672 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_IAR/main.c +++ b/FreeRTOS/Demo/ARM7_LPC2129_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -26,12 +26,12 @@ /* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used. + */ /* @@ -70,49 +70,49 @@ #include "comtest2.h" /* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Constants required by the 'Check' task. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainCHECK_TASK_LED ( 7 ) +#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) +#define mainCHECK_TASK_LED ( 7 ) /* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) -#define mainCOM_TEST_LED ( 4 ) -#define mainTX_ENABLE ( ( unsigned long ) 0x0001 ) -#define mainRX_ENABLE ( ( unsigned long ) 0x0004 ) +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 4 ) +#define mainTX_ENABLE ( ( unsigned long ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned long ) 0x0004 ) /* Constants to setup the PLL. */ -#define mainPLL_MUL_5 ( ( unsigned char ) 0x0004 ) -#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned long ) 0x0400 ) +#define mainPLL_MUL_5 ( ( unsigned char ) 0x0004 ) +#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned long ) 0x0400 ) /* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 ) +#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 ) /* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) +#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) /* And finally, constant to setup the port for the LED's. */ -#define mainLED_TO_OUTPUT ( ( unsigned long ) 0xff0000 ) +#define mainLED_TO_OUTPUT ( ( unsigned long ) 0xff0000 ) /* * The task that executes at the highest priority and calls * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Configures the processor for use with this demo. @@ -133,146 +133,145 @@ static long prvCheckOtherTasksAreStillRunning( void ); */ void main( void ) { - /* Setup the processor. */ - prvSetupHardware(); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. - */ - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - return; + /* Setup the processor. */ + prvSetupHardware(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + * + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used here. + */ + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup the PLL to multiply the XTAL input by 5. */ - PLLCFG = ( mainPLL_MUL_5 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - PLLCON = mainPLL_ENABLE; - PLLFEED = mainPLL_FEED_BYTE1; - PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - PLLCON = mainPLL_CONNECT; - PLLFEED = mainPLL_FEED_BYTE1; - PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAMTIM = mainMAM_TIM_3; - MAMCR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - APBDIV = mainBUS_CLK_FULL; - - /* Configure the RS2332 pins. All other pins remain at their default of 0. */ - PINSEL0 |= mainTX_ENABLE; - PINSEL0 |= mainRX_ENABLE; - - /* LED pins need to be output. */ - IO1DIR = mainLED_TO_OUTPUT; - - /* Setup the peripheral bus to be the same as the PLL output. */ - APBDIV = mainBUS_CLK_FULL; + /* Setup the PLL to multiply the XTAL input by 5. */ + PLLCFG = ( mainPLL_MUL_5 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + * bytes. */ + PLLCON = mainPLL_ENABLE; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( PLLSTAT & mainPLL_LOCK ) ) + { + } + + /* ...before connecting it using the feed sequence again. */ + PLLCON = mainPLL_CONNECT; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + * PLL used. It is possible faster overall performance could be obtained by + * tuning the MAM and PLL settings. */ + MAMTIM = mainMAM_TIM_3; + MAMCR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + APBDIV = mainBUS_CLK_FULL; + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PINSEL0 |= mainTX_ENABLE; + PINSEL0 |= mainRX_ENABLE; + + /* LED pins need to be output. */ + IO1DIR = mainLED_TO_OUTPUT; + + /* Setup the peripheral bus to be the same as the PLL output. */ + APBDIV = mainBUS_CLK_FULL; } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } + TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + * the on board LED flash rate will increase. */ + + for( ; ; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + * error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } } /*-----------------------------------------------------------*/ static long prvCheckOtherTasksAreStillRunning( void ) { -long lReturn = ( long ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - return lReturn; + long lReturn = ( long ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + return lReturn; } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/ARM7_LPC2129_IAR/serial/serial.c b/FreeRTOS/Demo/ARM7_LPC2129_IAR/serial/serial.c index 8485c962c1c..3820f6e1364 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_IAR/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_LPC2129_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/FreeRTOSConfig.h index 4c1cd9d0819..a1c46f1ff5c 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/ParTest/ParTest.c index 7c9b057abbd..056418c3151 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/main.c b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/main.c index 386a6fcfab6..30632d37e72 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/main.c +++ b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -24,29 +24,29 @@ * */ -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ +/* + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used. + */ /* * Creates all the demo application tasks, then starts the scheduler. The WEB * documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have + * the last time the check task executed. If all the count variables have * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time + * toggles the onboard LED. Should any task contain an error at any time * the LED toggle rate will change from 3 seconds to 500ms. * */ @@ -71,31 +71,31 @@ /*-----------------------------------------------------------*/ /* Constants to setup I/O and processor. */ -#define mainTX_ENABLE ( ( unsigned long ) 0x00010000 ) /* UART1. */ -#define mainRX_ENABLE ( ( unsigned long ) 0x00040000 ) /* UART1. */ -#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) -#define mainLED_TO_OUTPUT ( ( unsigned long ) 0xff0000 ) +#define mainTX_ENABLE ( ( unsigned long ) 0x00010000 ) /* UART1. */ +#define mainRX_ENABLE ( ( unsigned long ) 0x00040000 ) /* UART1. */ +#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) +#define mainLED_TO_OUTPUT ( ( unsigned long ) 0xff0000 ) /* Constants for the ComTest demo application tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) -#define mainCOM_TEST_LED ( 3 ) +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) /* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) /* Constants used by the "check" task. As described at the head of this file -the check task toggles an LED. The rate at which the LED flashes is used to -indicate whether an error has been detected or not. If the LED toggles every -3 seconds then no errors have been detected. If the rate increases to 500ms -then an error has been detected in at least one of the demo application tasks. */ -#define mainCHECK_LED ( 7 ) -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) + * the check task toggles an LED. The rate at which the LED flashes is used to + * indicate whether an error has been detected or not. If the LED toggles every + * 3 seconds then no errors have been detected. If the rate increases to 500ms + * then an error has been detected in at least one of the demo application tasks. */ +#define mainCHECK_LED ( 7 ) +#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) /*-----------------------------------------------------------*/ @@ -106,11 +106,11 @@ then an error has been detected in at least one of the demo application tasks. * static long prvCheckOtherTasksAreStillRunning( void ); /* - * The task that executes at the highest priority and calls + * The task that executes at the highest priority and calls * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Configure the processor for use with the Keil demo board. This is very @@ -125,125 +125,125 @@ static void prvSetupHardware( void ); /* * Application entry point: - * Starts all the other tasks, then starts the scheduler. + * Starts all the other tasks, then starts the scheduler. */ int main( void ) { - /* Setup the hardware for use with the Keil demo board. */ - prvSetupHardware(); - - /* Start the demo/test application tasks. */ - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - - /* Start the check task - which is defined in this file. This is the task - that periodically checks to see that all the other tasks are executing - without error. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! If you do then there was not enough heap - available for the idle task to be created. */ - for( ;; ); + /* Setup the hardware for use with the Keil demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + + /* Start the check task - which is defined in this file. This is the task + * that periodically checks to see that all the other tasks are executing + * without error. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + * + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! If you do then there was not enough heap + * available for the idle task to be created. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* Parameters are not used. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. - - This task runs at the highest priority. */ - - for( ;; ) - { - /* The period of the delay depends on whether an error has been - detected or not. If an error has been detected then the period - is reduced to increase the LED flash rate. */ - vTaskDelay( xDelayPeriod ); - - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* Toggle the LED before going back to wait for the next cycle. */ - vParTestToggleLED( mainCHECK_LED ); - } + TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* Parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + * the on board LED flash rate will increase. + * + * This task runs at the highest priority. */ + + for( ; ; ) + { + /* The period of the delay depends on whether an error has been + * detected or not. If an error has been detected then the period + * is reduced to increase the LED flash rate. */ + vTaskDelay( xDelayPeriod ); + + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Toggle the LED before going back to wait for the next cycle. */ + vParTestToggleLED( mainCHECK_LED ); + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Perform the hardware setup required. This is minimal as most of the - setup is managed by the settings in the project file. */ + /* Perform the hardware setup required. This is minimal as most of the + * setup is managed by the settings in the project file. */ - /* Configure the UART1 pins. All other pins remain at their default of 0. */ - PINSEL0 |= mainTX_ENABLE; - PINSEL0 |= mainRX_ENABLE; + /* Configure the UART1 pins. All other pins remain at their default of 0. */ + PINSEL0 |= mainTX_ENABLE; + PINSEL0 |= mainRX_ENABLE; - /* LED pins need to be output. */ - IODIR1 = mainLED_TO_OUTPUT; + /* LED pins need to be output. */ + IODIR1 = mainLED_TO_OUTPUT; - /* Setup the peripheral bus to be the same as the PLL output. */ - VPBDIV = mainBUS_CLK_FULL; + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; } /*-----------------------------------------------------------*/ static long prvCheckOtherTasksAreStillRunning( void ) { -long lReturn = pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - if( xAreComTestTasksStillRunning() != pdPASS ) - { - lReturn = pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - return lReturn; + long lReturn = pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. */ + if( xAreComTestTasksStillRunning() != pdPASS ) + { + lReturn = pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + return lReturn; } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c index 74a7bd75291..a155913f0da 100644 --- a/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h index 3c5e696f2f0..d712fbd6c0a 100644 --- a/FreeRTOS/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_LPC2138_Rowley/main.c b/FreeRTOS/Demo/ARM7_LPC2138_Rowley/main.c index 6c8b9d4456e..6970901982a 100644 --- a/FreeRTOS/Demo/ARM7_LPC2138_Rowley/main.c +++ b/FreeRTOS/Demo/ARM7_LPC2138_Rowley/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -75,51 +75,51 @@ #include "semtest.h" /* Hardware configuration definitions. */ -#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) -#define mainLED_BIT 0x80000000 -#define mainP0_14__EINT_1 ( 2 << 28 ) -#define mainEINT_1_EDGE_SENSITIVE 2 -#define mainEINT_1_FALLING_EDGE_SENSITIVE 0 -#define mainEINT_1_CHANNEL 15 -#define mainEINT_1_VIC_CHANNEL_BIT ( 1 << mainEINT_1_CHANNEL ) -#define mainEINT_1_ENABLE_BIT ( 1 << 5 ) +#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) +#define mainLED_BIT 0x80000000 +#define mainP0_14__EINT_1 ( 2 << 28 ) +#define mainEINT_1_EDGE_SENSITIVE 2 +#define mainEINT_1_FALLING_EDGE_SENSITIVE 0 +#define mainEINT_1_CHANNEL 15 +#define mainEINT_1_VIC_CHANNEL_BIT ( 1 << mainEINT_1_CHANNEL ) +#define mainEINT_1_ENABLE_BIT ( 1 << 5 ) /* Demo application definitions. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainLED_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainERROR_LED_DELAY ( ( TickType_t ) 50 / portTICK_PERIOD_MS ) -#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) -#define mainLIST_BUFFER_SIZE 2048 -#define mainNO_DELAY ( 0 ) -#define mainSHORT_DELAY ( 150 / portTICK_PERIOD_MS ) +#define mainQUEUE_SIZE ( 3 ) +#define mainLED_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) +#define mainERROR_LED_DELAY ( ( TickType_t ) 50 / portTICK_PERIOD_MS ) +#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) +#define mainLIST_BUFFER_SIZE 2048 +#define mainNO_DELAY ( 0 ) +#define mainSHORT_DELAY ( 150 / portTICK_PERIOD_MS ) /* Task priorities. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) /*-----------------------------------------------------------*/ /* The semaphore used to wake the button task from within the external interrupt -handler. */ + * handler. */ SemaphoreHandle_t xButtonSemaphore; /* The queue that is used to send message to vPrintTask for display in the -terminal output window. */ + * terminal output window. */ QueueHandle_t xPrintQueue; /* The rate at which the LED will toggle. The toggle rate increases if an -error is detected in any task. */ + * error is detected in any task. */ static TickType_t xLED_Delay = mainLED_DELAY; /*-----------------------------------------------------------*/ /* * Simply flashes the on board LED every mainLED_DELAY milliseconds. */ -static void vLEDTask( void *pvParameters ); +static void vLEDTask( void * pvParameters ); /* * Checks the status of all the demo tasks then prints a message to the @@ -130,250 +130,251 @@ static void vLEDTask( void *pvParameters ); * Messages are not written directly to the terminal, but passed to vPrintTask * via a queue. */ -static void vCheckTask( void *pvParameters ); +static void vCheckTask( void * pvParameters ); /* * Controls all terminal output. If a task wants to send a message to the * terminal IO it posts a pointer to the text to vPrintTask via a queue. This * ensures serial access to the terminal IO. */ -static void vPrintTask( void *pvParameter ); +static void vPrintTask( void * pvParameter ); /* * Simply waits for an interrupt to be generated from the built in button, then * generates a table of tasks states that is then written by vPrintTask to the * terminal output window within CrossStudio. */ -static void vButtonHandlerTask( void *pvParameters ); +static void vButtonHandlerTask( void * pvParameters ); /*-----------------------------------------------------------*/ int main( void ) { - /* Setup the peripheral bus to be the same as the PLL output. */ - VPBDIV = mainBUS_CLK_FULL; - - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); - - /* Create the semaphore used to wake vButtonHandlerTask(). */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); - - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - #if configUSE_PREEMPTION == 1 - { - /* The timing of console output when not using the preemptive - scheduler causes the block time tests to detect a timing problem. */ - vCreateBlockTimeTasks(); - } - #endif + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); + + /* Create the semaphore used to wake vButtonHandlerTask(). */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + #if configUSE_PREEMPTION == 1 + { + /* The timing of console output when not using the preemptive + * scheduler causes the block time tests to detect a timing problem. */ + vCreateBlockTimeTasks(); + } + #endif vStartRecursiveMutexTasks(); - /* Start the tasks defined within this file. */ - xTaskCreate( vLEDTask, "LED", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL ); + /* Start the tasks defined within this file. */ + xTaskCreate( vLEDTask, "LED", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL ); xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); xTaskCreate( vButtonHandlerTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - /* Start the scheduler. */ - vTaskStartScheduler(); + /* Start the scheduler. */ + vTaskStartScheduler(); - /* The scheduler should now be running, so we will only ever reach here if we - ran out of heap space. */ + /* The scheduler should now be running, so we will only ever reach here if we + * ran out of heap space. */ - return 0; + return 0; } /*-----------------------------------------------------------*/ -static void vLEDTask( void *pvParameters ) +static void vLEDTask( void * pvParameters ) { - /* Just to remove compiler warnings. */ - ( void ) pvParameters; + /* Just to remove compiler warnings. */ + ( void ) pvParameters; - /* Configure IO. */ - IO0DIR |= mainLED_BIT; - IO0SET = mainLED_BIT; + /* Configure IO. */ + IO0DIR |= mainLED_BIT; + IO0SET = mainLED_BIT; - for( ;; ) - { - /* Not very exiting - just delay... */ - vTaskDelay( xLED_Delay ); + for( ; ; ) + { + /* Not very exiting - just delay... */ + vTaskDelay( xLED_Delay ); - /* ...set the IO ... */ + /* ...set the IO ... */ IO0CLR = mainLED_BIT; - /* ...delay again... */ - vTaskDelay( xLED_Delay ); + /* ...delay again... */ + vTaskDelay( xLED_Delay ); - /* ...then clear the IO. */ - IO0SET = mainLED_BIT; - } + /* ...then clear the IO. */ + IO0SET = mainLED_BIT; + } } /*-----------------------------------------------------------*/ -static void vCheckTask( void *pvParameters ) +static void vCheckTask( void * pvParameters ) { -portBASE_TYPE xErrorOccurred = pdFALSE; -TickType_t xLastExecutionTime; -const char * const pcPassMessage = "PASS\n"; -const char * const pcFailMessage = "FAIL\n"; - - /* Just to remove compiler warnings. */ - ( void ) pvParameters; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - #if configUSE_PREEMPTION == 1 - { - /* The timing of console output when not using the preemptive - scheduler causes the block time tests to detect a timing problem. */ - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - } - #endif - - if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. */ - if( xErrorOccurred == pdTRUE ) - { - xLED_Delay = mainERROR_LED_DELAY; - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } + portBASE_TYPE xErrorOccurred = pdFALSE; + TickType_t xLastExecutionTime; + const char * const pcPassMessage = "PASS\n"; + const char * const pcFailMessage = "FAIL\n"; + + /* Just to remove compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + #if configUSE_PREEMPTION == 1 + { + /* The timing of console output when not using the preemptive + * scheduler causes the block time tests to detect a timing problem. */ + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + } + #endif + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + * never cleared again. */ + if( xErrorOccurred == pdTRUE ) + { + xLED_Delay = mainERROR_LED_DELAY; + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } } /*-----------------------------------------------------------*/ -static void vPrintTask( void *pvParameters ) +static void vPrintTask( void * pvParameters ) { -char *pcMessage; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait for a message to arrive. */ - while( xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ) != pdPASS ); - - /* Write the message to the terminal IO. */ - #ifndef NDEBUG - debug_printf( "%s", pcMessage ); - #endif - } + char * pcMessage; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait for a message to arrive. */ + while( xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ) != pdPASS ) + { + } + + /* Write the message to the terminal IO. */ + #ifndef NDEBUG + debug_printf( "%s", pcMessage ); + #endif + } } /*-----------------------------------------------------------*/ -static void vButtonHandlerTask( void *pvParameters ) +static void vButtonHandlerTask( void * pvParameters ) { -static char cListBuffer[ mainLIST_BUFFER_SIZE ]; -const char *pcList = &( cListBuffer[ 0 ] ); -const char * const pcHeader = "\nTask State Priority Stack #\n************************************************"; -extern void (vButtonISRWrapper) ( void ); - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - /* Configure the interrupt. */ - portENTER_CRITICAL(); - { - /* Configure P0.14 to generate interrupts. */ - PINSEL0 |= mainP0_14__EINT_1; - EXTMODE = mainEINT_1_EDGE_SENSITIVE; - EXTPOLAR = mainEINT_1_FALLING_EDGE_SENSITIVE; - - /* Setup the VIC for EINT 1. */ - VICIntSelect &= ~mainEINT_1_VIC_CHANNEL_BIT; - VICIntEnable |= mainEINT_1_VIC_CHANNEL_BIT; - VICVectAddr1 = ( long ) vButtonISRWrapper; - VICVectCntl1 = mainEINT_1_ENABLE_BIT | mainEINT_1_CHANNEL; - } - portEXIT_CRITICAL(); - - for( ;; ) - { - /* For debouncing, wait a while then clear the semaphore. */ - vTaskDelay( mainSHORT_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - - /* Wait for an interrupt. */ - xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ); - - /* Send the column headers to the print task for display. */ - xQueueSend( xPrintQueue, &pcHeader, portMAX_DELAY ); - - /* Create the list of task states. */ - vTaskList( cListBuffer ); - - /* Send the task status information to the print task for display. */ - xQueueSend( xPrintQueue, &pcList, portMAX_DELAY ); - } + static char cListBuffer[ mainLIST_BUFFER_SIZE ]; + const char * pcList = &( cListBuffer[ 0 ] ); + const char * const pcHeader = "\nTask State Priority Stack #\n************************************************"; + + extern void( vButtonISRWrapper ) ( void ); + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Configure the interrupt. */ + portENTER_CRITICAL(); + { + /* Configure P0.14 to generate interrupts. */ + PINSEL0 |= mainP0_14__EINT_1; + EXTMODE = mainEINT_1_EDGE_SENSITIVE; + EXTPOLAR = mainEINT_1_FALLING_EDGE_SENSITIVE; + + /* Setup the VIC for EINT 1. */ + VICIntSelect &= ~mainEINT_1_VIC_CHANNEL_BIT; + VICIntEnable |= mainEINT_1_VIC_CHANNEL_BIT; + VICVectAddr1 = ( long ) vButtonISRWrapper; + VICVectCntl1 = mainEINT_1_ENABLE_BIT | mainEINT_1_CHANNEL; + } + portEXIT_CRITICAL(); + + for( ; ; ) + { + /* For debouncing, wait a while then clear the semaphore. */ + vTaskDelay( mainSHORT_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + + /* Wait for an interrupt. */ + xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ); + + /* Send the column headers to the print task for display. */ + xQueueSend( xPrintQueue, &pcHeader, portMAX_DELAY ); + + /* Create the list of task states. */ + vTaskList( cListBuffer ); + + /* Send the task status information to the print task for display. */ + xQueueSend( xPrintQueue, &pcList, portMAX_DELAY ); + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - /* Check pcTaskName for the name of the offending task, or pxCurrentTCB - if pcTaskName has itself been corrupted. */ - ( void ) pxTask; - ( void ) pcTaskName; - for( ;; ); + /* Check pcTaskName for the name of the offending task, or pxCurrentTCB + * if pcTaskName has itself been corrupted. */ + ( void ) pxTask; + ( void ) pcTaskName; + + for( ; ; ) + { + } } - - - - - - diff --git a/FreeRTOS/Demo/ARM7_LPC2138_Rowley/mainISR.c b/FreeRTOS/Demo/ARM7_LPC2138_Rowley/mainISR.c index a914b50dbf1..020ac8e9b71 100644 --- a/FreeRTOS/Demo/ARM7_LPC2138_Rowley/mainISR.c +++ b/FreeRTOS/Demo/ARM7_LPC2138_Rowley/mainISR.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -26,32 +26,32 @@ #include "FreeRTOS.h" #include "semphr.h" -#define isrCLEAR_EINT_1 2 +#define isrCLEAR_EINT_1 2 /* - * Interrupt routine that simply wakes vButtonHandlerTask on each interrupt + * Interrupt routine that simply wakes vButtonHandlerTask on each interrupt * generated by a push of the built in button. The wrapper takes care of * the ISR entry. This then calls the actual handler function to perform * the work. This work should not be done in the wrapper itself unless * you are absolutely sure that no stack space is used. */ -void vButtonISRWrapper( void ) __attribute__ ((naked)); -void vButtonHandler( void ) __attribute__ ((noinline)); +void vButtonISRWrapper( void ) __attribute__( ( naked ) ); +void vButtonHandler( void ) __attribute__( ( noinline ) ); void vButtonHandler( void ) { -extern SemaphoreHandle_t xButtonSemaphore; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + extern SemaphoreHandle_t xButtonSemaphore; + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); - if( xHigherPriorityTaskWoken ) - { - /* We have woken a task. Calling "yield from ISR" here will ensure - the interrupt returns to the woken task if it has a priority higher - than the interrupted task. */ - portYIELD_FROM_ISR(); - } + if( xHigherPriorityTaskWoken ) + { + /* We have woken a task. Calling "yield from ISR" here will ensure + * the interrupt returns to the woken task if it has a priority higher + * than the interrupted task. */ + portYIELD_FROM_ISR(); + } EXTINT = isrCLEAR_EINT_1; VICVectAddr = 0; @@ -60,17 +60,14 @@ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; void vButtonISRWrapper( void ) { - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT(); + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); - /* Call the handler to do the work. This must be a separate function to - the wrapper to ensure the correct stack frame is set up. */ - __asm volatile( "bl vButtonHandler" ); + /* Call the handler to do the work. This must be a separate function to + * the wrapper to ensure the correct stack frame is set up. */ + __asm volatile ( "bl vButtonHandler" ); - /* Restore the context of whichever task is going to run once the interrupt - completes. */ - portRESTORE_CONTEXT(); + /* Restore the context of whichever task is going to run once the interrupt + * completes. */ + portRESTORE_CONTEXT(); } - - - diff --git a/FreeRTOS/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h index a9a8d463f0b..8a16eaa1a81 100644 --- a/FreeRTOS/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c index a093ec87b35..ae7b9e2da93 100644 --- a/FreeRTOS/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR71x_IAR/main.c b/FreeRTOS/Demo/ARM7_STR71x_IAR/main.c index 633ba37d971..8f3db9cac4a 100644 --- a/FreeRTOS/Demo/ARM7_STR71x_IAR/main.c +++ b/FreeRTOS/Demo/ARM7_STR71x_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -25,12 +25,12 @@ */ /* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used. + */ /* * Creates all the demo application tasks, then starts the scheduler. The WEB @@ -69,28 +69,28 @@ #include "comtest2.h" /* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Constants required by the 'Check' task. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) -#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) -#define mainCHECK_TASK_LED ( 4 ) +#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) +#define mainCHECK_TASK_LED ( 4 ) /* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) -#define mainCOM_TEST_LED ( 6 ) /* The LED built onto the kickstart board. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 6 ) /* The LED built onto the kickstart board. */ /* * The task that executes at the highest priority and calls * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Configure the processor for use with the IAR STR71x demo board. This @@ -112,37 +112,36 @@ static long prvCheckOtherTasksAreStillRunning( void ); */ void main( void ) { - /* Setup any hardware that has not already been configured by the low - level init routines. */ - prvSetupHardware(); - - /* Initialise the LED outputs for use by the demo application tasks. */ - vParTestInitialise(); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - return; + /* Setup any hardware that has not already been configured by the low + * level init routines. */ + prvSetupHardware(); + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + * + * NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + * The processor MUST be in supervisor mode when vTaskStartScheduler is + * called. The demo applications included in the FreeRTOS.org download switch + * to supervisor mode prior to main being called. If you are not using one of + * these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ } /*-----------------------------------------------------------*/ @@ -151,90 +150,88 @@ static void prvSetupHardware( void ) /* Setup the PLL to generate a 48MHz clock from the 4MHz CLK. */ /* Turn of the div by two. */ - RCCU_Div2Config( DISABLE ); + RCCU_Div2Config( DISABLE ); /* 48MHz = ( 4MHz * 12 ) / 1 */ - RCCU_PLL1Config( RCCU_PLL1_Mul_12, RCCU_Div_1 ); + RCCU_PLL1Config( RCCU_PLL1_Mul_12, RCCU_Div_1 ); RCCU_RCLKSourceConfig( RCCU_PLL1_Output ); } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -TickType_t xLastWakeTime; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - - for( ;; ) - { - /* Delay until it is time to execute again. The delay period is - shorter following an error so the LED flashes faster. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } + TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + TickType_t xLastWakeTime; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + * functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + * the on board LED flash rate will increase. */ + + for( ; ; ) + { + /* Delay until it is time to execute again. The delay period is + * shorter following an error so the LED flashes faster. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + * error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } } /*-----------------------------------------------------------*/ static long prvCheckOtherTasksAreStillRunning( void ) { -long lReturn = ( long ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( long ) pdFAIL; - } - - return lReturn; + long lReturn = ( long ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + return lReturn; } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/ARM7_STR71x_IAR/serial/serial.c b/FreeRTOS/Demo/ARM7_STR71x_IAR/serial/serial.c index 9f83338d651..60a1e336823 100644 --- a/FreeRTOS/Demo/ARM7_STR71x_IAR/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_STR71x_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h index 8f985233586..0bc2e7ec268 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c index f6ccae65974..8f21857f92d 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_GCC/main.c b/FreeRTOS/Demo/ARM7_STR75x_GCC/main.c index ba65d49cd9f..6e5323719f8 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_GCC/main.c +++ b/FreeRTOS/Demo/ARM7_STR75x_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -66,41 +66,41 @@ #include "dynamic.h" /* Demo application task priorities. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* How often should we check the other tasks? */ -#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) +#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) /* The maximum offset into the pass and fail strings sent to the LCD. An -offset is used a simple method of using a different column each time a message -is written to the LCD. */ -#define mainMAX_WRITE_COLUMN ( 14 ) + * offset is used a simple method of using a different column each time a message + * is written to the LCD. */ +#define mainMAX_WRITE_COLUMN ( 14 ) /* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 19200 ) +#define mainCOM_TEST_BAUD_RATE ( 19200 ) /* The LED used by the comtest tasks. See the comtest.c file for more -information. */ -#define mainCOM_TEST_LED ( 3 ) + * information. */ +#define mainCOM_TEST_LED ( 3 ) /* The number of messages that can be queued for display on the LCD at any one -time. */ -#define mainLCD_QUEUE_LENGTH ( 2 ) + * time. */ +#define mainLCD_QUEUE_LENGTH ( 2 ) /* The time to wait when sending to mainLCD_QUEUE_LENGTH. */ -#define mainNO_DELAY ( 0 ) +#define mainNO_DELAY ( 0 ) /*-----------------------------------------------------------*/ /* The type that is posted to the LCD queue. */ typedef struct LCD_MESSAGE { - unsigned char *pucString; /* Points to the string to be displayed. */ - unsigned char ucLine; /* The line of the LCD that should be used. */ + unsigned char * pucString; /* Points to the string to be displayed. */ + unsigned char ucLine; /* The line of the LCD that should be used. */ } LCDMessage; /*-----------------------------------------------------------*/ @@ -110,12 +110,12 @@ typedef struct LCD_MESSAGE * all the other tasks in the system. See the description at the top of the * file. */ -static void vCheckTask( void *pvParameters ); +static void vCheckTask( void * pvParameters ); /* * ST provided routine to configure the processor. */ -static void prvSetupHardware(void); +static void prvSetupHardware( void ); /* * The only task that should access the LCD. Other tasks wanting to write @@ -124,7 +124,7 @@ static void prvSetupHardware(void); * waiting for the arrival of such messages, displays the message, then blocks * again. */ -static void vPrintTask( void *pvParameters ); +static void vPrintTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -136,177 +136,179 @@ static QueueHandle_t xLCDQueue; /* Create all the demo application tasks, then start the scheduler. */ int main( void ) { - /* Perform any hardware setup necessary. */ - prvSetupHardware(); - vParTestInitialise(); - - /* Create the queue used to communicate with the LCD print task. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); - - /* Create the standard demo application tasks. See the WEB documentation - for more information on these tasks. */ - vCreateBlockTimeTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartDynamicPriorityTasks(); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Create the tasks defined within this file. */ - xTaskCreate( vPrintTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - vTaskStartScheduler(); - - /* Execution will only reach here if there was insufficient heap to - start the scheduler. */ - return 0; + /* Perform any hardware setup necessary. */ + prvSetupHardware(); + vParTestInitialise(); + + /* Create the queue used to communicate with the LCD print task. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); + + /* Create the standard demo application tasks. See the WEB documentation + * for more information on these tasks. */ + vCreateBlockTimeTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartDynamicPriorityTasks(); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Create the tasks defined within this file. */ + xTaskCreate( vPrintTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + vTaskStartScheduler(); + + /* Execution will only reach here if there was insufficient heap to + * start the scheduler. */ + return 0; } /*-----------------------------------------------------------*/ -static void vCheckTask( void *pvParameters ) +static void vCheckTask( void * pvParameters ) { -static unsigned long ulErrorDetected = pdFALSE; -TickType_t xLastExecutionTime; -unsigned char *ucErrorMessage = ( unsigned char * )" FAIL"; -unsigned char *ucSuccessMessage = ( unsigned char * )" PASS"; -unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; -LCDMessage xMessage; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); - - /* Has an error been found in any of the standard demo tasks? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - /* Calculate the LCD line on which we would like the message to - be displayed. The column variable is used for convenience as - it is incremented each cycle anyway. */ - xMessage.ucLine = ( unsigned char ) ( uxColumn & 0x01 ); - - /* The message displayed depends on whether an error was found or - not. Any discovered error is latched. Here the column variable - is used as an index into the text string as a simple way of moving - the text from column to column. */ - if( ulErrorDetected == pdFALSE ) - { - xMessage.pucString = ucSuccessMessage + uxColumn; - } - else - { - xMessage.pucString = ucErrorMessage + uxColumn; - } - - /* Send the message to the print task for display. */ - xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); - - /* Make sure the message is printed in a different column the next - time around. */ - uxColumn--; - if( uxColumn == 0 ) - { - uxColumn = mainMAX_WRITE_COLUMN; - } - } + static unsigned long ulErrorDetected = pdFALSE; + TickType_t xLastExecutionTime; + unsigned char * ucErrorMessage = ( unsigned char * ) " FAIL"; + unsigned char * ucSuccessMessage = ( unsigned char * ) " PASS"; + unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; + LCDMessage xMessage; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Wait until it is time for the next cycle. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); + + /* Has an error been found in any of the standard demo tasks? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + /* Calculate the LCD line on which we would like the message to + * be displayed. The column variable is used for convenience as + * it is incremented each cycle anyway. */ + xMessage.ucLine = ( unsigned char ) ( uxColumn & 0x01 ); + + /* The message displayed depends on whether an error was found or + * not. Any discovered error is latched. Here the column variable + * is used as an index into the text string as a simple way of moving + * the text from column to column. */ + if( ulErrorDetected == pdFALSE ) + { + xMessage.pucString = ucSuccessMessage + uxColumn; + } + else + { + xMessage.pucString = ucErrorMessage + uxColumn; + } + + /* Send the message to the print task for display. */ + xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); + + /* Make sure the message is printed in a different column the next + * time around. */ + uxColumn--; + + if( uxColumn == 0 ) + { + uxColumn = mainMAX_WRITE_COLUMN; + } + } } /*-----------------------------------------------------------*/ -static void vPrintTask( void *pvParameters ) +static void vPrintTask( void * pvParameters ) { -LCDMessage xMessage; - - for( ;; ) - { - /* Wait until a message arrives. */ - while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ); - - /* The message contains the text to display, and the line on which the - text should be displayed. */ - LCD_Clear(); - LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); - } + LCDMessage xMessage; + + for( ; ; ) + { + /* Wait until a message arrives. */ + while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ) + { + } + + /* The message contains the text to display, and the line on which the + * text should be displayed. */ + LCD_Clear(); + LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); + } } /*-----------------------------------------------------------*/ -static void prvSetupHardware(void) +static void prvSetupHardware( void ) { -ErrorStatus OSC4MStartUpStatus01; + ErrorStatus OSC4MStartUpStatus01; - /* ST provided routine. */ + /* ST provided routine. */ - /* MRCC system reset */ - MRCC_DeInit(); + /* MRCC system reset */ + MRCC_DeInit(); - /* Wait for OSC4M start-up */ - OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); + /* Wait for OSC4M start-up */ + OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); - if(OSC4MStartUpStatus01 == SUCCESS) - { - /* Set HCLK to 60MHz */ - MRCC_HCLKConfig(MRCC_CKSYS_Div1); + if( OSC4MStartUpStatus01 == SUCCESS ) + { + /* Set HCLK to 60MHz */ + MRCC_HCLKConfig( MRCC_CKSYS_Div1 ); - /* Set CKTIM to 60MHz */ - MRCC_CKTIMConfig(MRCC_HCLK_Div1); + /* Set CKTIM to 60MHz */ + MRCC_CKTIMConfig( MRCC_HCLK_Div1 ); - /* Set PCLK to 30MHz */ - MRCC_PCLKConfig(MRCC_CKTIM_Div2); + /* Set PCLK to 30MHz */ + MRCC_PCLKConfig( MRCC_CKTIM_Div2 ); - /* Enable Flash Burst mode */ - CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable); + /* Enable Flash Burst mode */ + CFG_FLASHBurstConfig( CFG_FLASHBurst_Enable ); - /* Set CK_SYS to 60 MHz */ - MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15); - } + /* Set CK_SYS to 60 MHz */ + MRCC_CKSYSConfig( MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15 ); + } - /* GPIO pins optimized for 3V3 operation */ - MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3); + /* GPIO pins optimized for 3V3 operation */ + MRCC_IOVoltageRangeConfig( MRCC_IOVoltageRange_3V3 ); - /* GPIO clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); + /* GPIO clock source enable */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_GPIO, ENABLE ); - /* EXTIT clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE); - /* TB clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE); + /* EXTIT clock source enable */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_EXTIT, ENABLE ); + /* TB clock source enable */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_TB, ENABLE ); - /* Initialize the demonstration menu */ - LCD_Init(); + /* Initialize the demonstration menu */ + LCD_Init(); - LCD_DisplayString(Line1, ( unsigned char * ) "www.FreeRTOS.org", BlackText); - LCD_DisplayString(Line2, ( unsigned char * ) " STR750 Demo ", BlackText); + LCD_DisplayString( Line1, ( unsigned char * ) "www.FreeRTOS.org", BlackText ); + LCD_DisplayString( Line2, ( unsigned char * ) " STR750 Demo ", BlackText ); - EIC_IRQCmd(ENABLE); + EIC_IRQCmd( ENABLE ); } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serial.c b/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serial.c index 55b9d45afa6..92aca62c1fd 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serialISR.c b/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serialISR.c index b3d58168fd4..ab00a72ea34 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serialISR.c +++ b/FreeRTOS/Demo/ARM7_STR75x_GCC/serial/serialISR.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h index 8fbdf7ace32..7ad6a92e008 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c index f6ccae65974..8f21857f92d 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM7_STR75x_IAR/main.c b/FreeRTOS/Demo/ARM7_STR75x_IAR/main.c index ebab686636d..b769de5b69d 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_IAR/main.c +++ b/FreeRTOS/Demo/ARM7_STR75x_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -66,41 +66,41 @@ #include "dynamic.h" /* Demo application task priorities. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* How often should we check the other tasks? */ -#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) +#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) /* The maximum offset into the pass and fail strings sent to the LCD. An -offset is used a simple method of using a different column each time a message -is written to the LCD. */ -#define mainMAX_WRITE_COLUMN ( 14 ) + * offset is used a simple method of using a different column each time a message + * is written to the LCD. */ +#define mainMAX_WRITE_COLUMN ( 14 ) /* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 19200 ) +#define mainCOM_TEST_BAUD_RATE ( 19200 ) /* The LED used by the comtest tasks. See the comtest.c file for more -information. */ -#define mainCOM_TEST_LED ( 3 ) + * information. */ +#define mainCOM_TEST_LED ( 3 ) /* The number of messages that can be queued for display on the LCD at any one -time. */ -#define mainLCD_QUEUE_LENGTH ( 2 ) + * time. */ +#define mainLCD_QUEUE_LENGTH ( 2 ) /* The time to wait when sending to mainLCD_QUEUE_LENGTH. */ -#define mainNO_DELAY ( 0 ) +#define mainNO_DELAY ( 0 ) /*-----------------------------------------------------------*/ /* The type that is posted to the LCD queue. */ typedef struct LCD_MESSAGE { - unsigned char *pucString; /* Points to the string to be displayed. */ - unsigned char ucLine; /* The line of the LCD that should be used. */ + unsigned char * pucString; /* Points to the string to be displayed. */ + unsigned char ucLine; /* The line of the LCD that should be used. */ } LCDMessage; /*-----------------------------------------------------------*/ @@ -110,12 +110,12 @@ typedef struct LCD_MESSAGE * all the other tasks in the system. See the description at the top of the * file. */ -static void vCheckTask( void *pvParameters ); +static void vCheckTask( void * pvParameters ); /* * ST provided routine to configure the processor. */ -static void prvSetupHardware(void); +static void prvSetupHardware( void ); /* * The only task that should access the LCD. Other tasks wanting to write @@ -124,7 +124,7 @@ static void prvSetupHardware(void); * waiting for the arrival of such messages, displays the message, then blocks * again. */ -static void vPrintTask( void *pvParameters ); +static void vPrintTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -136,174 +136,177 @@ static QueueHandle_t xLCDQueue; /* Create all the demo application tasks, then start the scheduler. */ void main( void ) { - /* Perform any hardware setup necessary. */ - prvSetupHardware(); - vParTestInitialise(); - - /* Create the queue used to communicate with the LCD print task. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); - - /* Create the standard demo application tasks. See the WEB documentation - for more information on these tasks. */ - vCreateBlockTimeTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartDynamicPriorityTasks(); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Create the tasks defined within this file. */ - xTaskCreate( vPrintTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - vTaskStartScheduler(); - - /* Execution will only reach here if there was insufficient heap to - start the scheduler. */ + /* Perform any hardware setup necessary. */ + prvSetupHardware(); + vParTestInitialise(); + + /* Create the queue used to communicate with the LCD print task. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); + + /* Create the standard demo application tasks. See the WEB documentation + * for more information on these tasks. */ + vCreateBlockTimeTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartDynamicPriorityTasks(); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Create the tasks defined within this file. */ + xTaskCreate( vPrintTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + vTaskStartScheduler(); + + /* Execution will only reach here if there was insufficient heap to + * start the scheduler. */ } /*-----------------------------------------------------------*/ -static void vCheckTask( void *pvParameters ) +static void vCheckTask( void * pvParameters ) { -static unsigned long ulErrorDetected = pdFALSE; -TickType_t xLastExecutionTime; -unsigned char *cErrorMessage = " FAIL"; -unsigned char *cSuccessMessage = " PASS"; -unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; -LCDMessage xMessage; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); - - /* Has an error been found in any of the standard demo tasks? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - /* Calculate the LCD line on which we would like the message to - be displayed. The column variable is used for convenience as - it is incremented each cycle anyway. */ - xMessage.ucLine = ( unsigned char ) ( uxColumn & 0x01 ); - - /* The message displayed depends on whether an error was found or - not. Any discovered error is latched. Here the column variable - is used as an index into the text string as a simple way of moving - the text from column to column. */ - if( ulErrorDetected == pdFALSE ) - { - xMessage.pucString = cSuccessMessage + uxColumn; - } - else - { - xMessage.pucString = cErrorMessage + uxColumn; - } - - /* Send the message to the print task for display. */ - xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); - - /* Make sure the message is printed in a different column the next - time around. */ - uxColumn--; - if( uxColumn == 0 ) - { - uxColumn = mainMAX_WRITE_COLUMN; - } - } + static unsigned long ulErrorDetected = pdFALSE; + TickType_t xLastExecutionTime; + unsigned char * cErrorMessage = " FAIL"; + unsigned char * cSuccessMessage = " PASS"; + unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; + LCDMessage xMessage; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Wait until it is time for the next cycle. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); + + /* Has an error been found in any of the standard demo tasks? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + /* Calculate the LCD line on which we would like the message to + * be displayed. The column variable is used for convenience as + * it is incremented each cycle anyway. */ + xMessage.ucLine = ( unsigned char ) ( uxColumn & 0x01 ); + + /* The message displayed depends on whether an error was found or + * not. Any discovered error is latched. Here the column variable + * is used as an index into the text string as a simple way of moving + * the text from column to column. */ + if( ulErrorDetected == pdFALSE ) + { + xMessage.pucString = cSuccessMessage + uxColumn; + } + else + { + xMessage.pucString = cErrorMessage + uxColumn; + } + + /* Send the message to the print task for display. */ + xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); + + /* Make sure the message is printed in a different column the next + * time around. */ + uxColumn--; + + if( uxColumn == 0 ) + { + uxColumn = mainMAX_WRITE_COLUMN; + } + } } /*-----------------------------------------------------------*/ -static void vPrintTask( void *pvParameters ) +static void vPrintTask( void * pvParameters ) { -LCDMessage xMessage; - - for( ;; ) - { - /* Wait until a message arrives. */ - while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ); - - /* The message contains the text to display, and the line on which the - text should be displayed. */ - LCD_Clear(); - LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); - } + LCDMessage xMessage; + + for( ; ; ) + { + /* Wait until a message arrives. */ + while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ) + { + } + + /* The message contains the text to display, and the line on which the + * text should be displayed. */ + LCD_Clear(); + LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); + } } /*-----------------------------------------------------------*/ -static void prvSetupHardware(void) +static void prvSetupHardware( void ) { -ErrorStatus OSC4MStartUpStatus01; + ErrorStatus OSC4MStartUpStatus01; - /* ST provided routine. */ + /* ST provided routine. */ - /* MRCC system reset */ - MRCC_DeInit(); + /* MRCC system reset */ + MRCC_DeInit(); - /* Wait for OSC4M start-up */ - OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); + /* Wait for OSC4M start-up */ + OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); - if(OSC4MStartUpStatus01 == SUCCESS) - { - /* Set HCLK to 60MHz */ - MRCC_HCLKConfig(MRCC_CKSYS_Div1); + if( OSC4MStartUpStatus01 == SUCCESS ) + { + /* Set HCLK to 60MHz */ + MRCC_HCLKConfig( MRCC_CKSYS_Div1 ); - /* Set CKTIM to 60MHz */ - MRCC_CKTIMConfig(MRCC_HCLK_Div1); + /* Set CKTIM to 60MHz */ + MRCC_CKTIMConfig( MRCC_HCLK_Div1 ); - /* Set PCLK to 30MHz */ - MRCC_PCLKConfig(MRCC_CKTIM_Div2); + /* Set PCLK to 30MHz */ + MRCC_PCLKConfig( MRCC_CKTIM_Div2 ); - /* Enable Flash Burst mode */ - CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable); + /* Enable Flash Burst mode */ + CFG_FLASHBurstConfig( CFG_FLASHBurst_Enable ); - /* Set CK_SYS to 60 MHz */ - MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15); - } + /* Set CK_SYS to 60 MHz */ + MRCC_CKSYSConfig( MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15 ); + } - /* GPIO pins optimized for 3V3 operation */ - MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3); + /* GPIO pins optimized for 3V3 operation */ + MRCC_IOVoltageRangeConfig( MRCC_IOVoltageRange_3V3 ); - /* GPIO clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); + /* GPIO clock source enable */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_GPIO, ENABLE ); - /* EXTIT clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE); - /* TB clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE); + /* EXTIT clock source enable */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_EXTIT, ENABLE ); + /* TB clock source enable */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_TB, ENABLE ); - /* Initialize the demonstration menu */ - LCD_Init(); + /* Initialize the demonstration menu */ + LCD_Init(); - LCD_DisplayString(Line1, "www.FreeRTOS.org", BlackText); - LCD_DisplayString(Line2, " STR750 Demo ", BlackText); + LCD_DisplayString( Line1, "www.FreeRTOS.org", BlackText ); + LCD_DisplayString( Line2, " STR750 Demo ", BlackText ); - EIC_IRQCmd(ENABLE); + EIC_IRQCmd( ENABLE ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/ARM7_STR75x_IAR/serial/serial.c b/FreeRTOS/Demo/ARM7_STR75x_IAR/serial/serial.c index 457bb5a6bc4..532eaea92ed 100644 --- a/FreeRTOS/Demo/ARM7_STR75x_IAR/serial/serial.c +++ b/FreeRTOS/Demo/ARM7_STR75x_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h index cb5fe4de83d..b78ddf31479 100644 --- a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ParTest/ParTest.c index b986496b812..f1aa95e9bb2 100644 --- a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/main.c b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/main.c index fa299644d1b..56d4225ae11 100644 --- a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/main.c +++ b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -63,21 +63,21 @@ #include /* Priorities for the demo application tasks. */ -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) /* The period of the check task both in and out of the presense of an error. */ -#define mainNO_ERROR_PERIOD ( 5000 / portTICK_PERIOD_MS ) -#define mainERROR_PERIOD ( 500 / portTICK_PERIOD_MS ); +#define mainNO_ERROR_PERIOD ( 5000 / portTICK_PERIOD_MS ) +#define mainERROR_PERIOD ( 500 / portTICK_PERIOD_MS ); /* Constants used by the ComTest task. */ -#define mainCOM_TEST_BAUD_RATE ( 38400 ) -#define mainCOM_TEST_LED ( LED_DS1 ) +#define mainCOM_TEST_BAUD_RATE ( 38400 ) +#define mainCOM_TEST_LED ( LED_DS1 ) /*-----------------------------------------------------------*/ @@ -85,148 +85,150 @@ static void prvSetupHardware( void ); /* The check task as described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); /*-----------------------------------------------------------*/ int main() { - /* Perform any hardware setup necessary to run the demo. */ - prvSetupHardware(); - - /* First create the 'standard demo' tasks. These exist just to to - demonstrate API functions being used and test the kernel port. More - information is provided on the FreeRTOS.org WEB site. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartQueuePeekTasks(); - vStartRecursiveMutexTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Create the check task - this is the task that checks all the other tasks - are executing as expected and without reporting any errors. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - - /* The death demo tasks must be started last as the sanity checks performed - require knowledge of the number of other tasks in the system. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the scheduler. From this point on the execution will be under - the control of the kernel. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient heap available for the - idle task to be created. */ - for( ;; ); + /* Perform any hardware setup necessary to run the demo. */ + prvSetupHardware(); + + /* First create the 'standard demo' tasks. These exist just to to + * demonstrate API functions being used and test the kernel port. More + * information is provided on the FreeRTOS.org WEB site. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Create the check task - this is the task that checks all the other tasks + * are executing as expected and without reporting any errors. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* The death demo tasks must be started last as the sanity checks performed + * require knowledge of the number of other tasks in the system. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. From this point on the execution will be under + * the control of the kernel. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap available for the + * idle task to be created. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTask( void * pvParameters ) { -TickType_t xNextWakeTime, xPeriod = mainNO_ERROR_PERIOD; -static volatile unsigned long ulErrorCode = 0UL; - - /* Just to remove the compiler warning. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime prior to its first use. From this point on - the value of the variable is handled automatically by the kernel. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Delay until it is time for this task to execute again. */ - vTaskDelayUntil( &xNextWakeTime, xPeriod ); - - /* Check all the other tasks in the system - latch any reported errors - into the ulErrorCode variable. */ - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x01UL; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x02UL; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x04UL; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x08UL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x10UL; - } - - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x20UL; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x40UL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x80UL; - } - - if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x100UL; - } - - if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x200UL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x400UL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - ulErrorCode |= 0x800UL; - } - - /* Reduce the block period and in so doing increase the frequency at - which this task executes if any errors have been latched. The increased - frequency causes the LED toggle rate to increase and so gives some - visual feedback that an error has occurred. */ - if( ulErrorCode != 0x00 ) - { - xPeriod = mainERROR_PERIOD; - } - - /* Finally toggle the LED. */ - vParTestToggleLED( LED_POWER ); - } + TickType_t xNextWakeTime, xPeriod = mainNO_ERROR_PERIOD; + static volatile unsigned long ulErrorCode = 0UL; + + /* Just to remove the compiler warning. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime prior to its first use. From this point on + * the value of the variable is handled automatically by the kernel. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Delay until it is time for this task to execute again. */ + vTaskDelayUntil( &xNextWakeTime, xPeriod ); + + /* Check all the other tasks in the system - latch any reported errors + * into the ulErrorCode variable. */ + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x01UL; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x02UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x04UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x08UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x10UL; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x20UL; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x40UL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x80UL; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x100UL; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x200UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x400UL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulErrorCode |= 0x800UL; + } + + /* Reduce the block period and in so doing increase the frequency at + * which this task executes if any errors have been latched. The increased + * frequency causes the LED toggle rate to increase and so gives some + * visual feedback that an error has occurred. */ + if( ulErrorCode != 0x00 ) + { + xPeriod = mainERROR_PERIOD; + } + + /* Finally toggle the LED. */ + vParTestToggleLED( LED_POWER ); + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -const Pin xPins[] = { PIN_USART0_RXD, PIN_USART0_TXD }; + const Pin xPins[] = { PIN_USART0_RXD, PIN_USART0_TXD }; - /* Setup the LED outputs. */ - vParTestInitialise(); - - /* Setup the pins for the UART. */ - PIO_Configure( xPins, PIO_LISTSIZE( xPins ) ); + /* Setup the LED outputs. */ + vParTestInitialise(); + + /* Setup the pins for the UART. */ + PIO_Configure( xPins, PIO_LISTSIZE( xPins ) ); } diff --git a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/serial/serial.c b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/serial/serial.c index 7c85386e872..67fa79c9dd2 100644 --- a/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/serial/serial.c +++ b/FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR32_UC3/main.c b/FreeRTOS/Demo/AVR32_UC3/main.c index 97a4d36099a..2524785fd31 100644 --- a/FreeRTOS/Demo/AVR32_UC3/main.c +++ b/FreeRTOS/Demo/AVR32_UC3/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -25,7 +25,8 @@ */ /*This file has been prepared for Doxygen automatic documentation generation.*/ -/*! \file ********************************************************************* + +/* \file ********************************************************************* * * \brief FreeRTOS Real Time Kernel example. * @@ -79,56 +80,48 @@ #include "death.h" #include "flop.h" -/*! \name Priority definitions for most of the tasks in the demo application. +/* Priority definitions for most of the tasks in the demo application. * Some tasks just use the idle priority. */ -//! @{ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -//! @} - -//! Baud rate used by the serial port tasks. -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 57600 ) - -//! LED used by the serial port tasks. This is toggled on each character Tx, -//! and mainCOM_TEST_LED + 1 is toggled on each character Rx. -#define mainCOM_TEST_LED ( 3 ) - -//! LED that is toggled by the check task. The check task periodically checks -//! that all the other tasks are operating without error. If no errors are found -//! the LED is toggled. If an error is found at any time the LED toggles faster. -#define mainCHECK_TASK_LED ( 6 ) - -//! LED that is set upon error. -#define mainERROR_LED ( 7 ) - -//! The period between executions of the check task. -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) - -//! If an error is detected in a task, the vErrorChecks task will enter in an -//! infinite loop flashing the LED at this rate. -#define mainERROR_FLASH_RATE ( (TickType_t) 500 / portTICK_PERIOD_MS ) - -/*! \name Constants used by the vMemCheckTask() task. +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 57600 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, + * and mainCOM_TEST_LED + 1 is toggled on each character Rx. */ +#define mainCOM_TEST_LED ( 3 ) + +/* LED that is toggled by the check task. The check task periodically checks + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED toggles faster. */ -//! @{ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) -#define mainNO_TASK ( 0 ) -//! @} +#define mainCHECK_TASK_LED ( 6 ) -/*! \name The size of the memory blocks allocated by the vMemCheckTask() task. - */ -//! @{ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 15 ) -//! @} +/* LED that is set upon error. */ +#define mainERROR_LED ( 7 ) + +/* The period between executions of the check task. */ +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) + +/* If an error is detected in a task, the vErrorChecks task will enter in an + * infinite loop flashing the LED at this rate. */ +#define mainERROR_FLASH_RATE ( ( TickType_t ) 500 / portTICK_PERIOD_MS ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) +#define mainNO_TASK ( 0 ) +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 15 ) /*-----------------------------------------------------------*/ @@ -137,7 +130,7 @@ * prvCheckOtherTasksAreStillRunning(). See the description at the top * of the file. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks that all the demo application tasks are still executing without error @@ -148,7 +141,7 @@ static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); /* * A task that exercises the memory allocator. */ -static void vMemCheckTask( void *pvParameters ); +static void vMemCheckTask( void * pvParameters ); /* * Called by the check task following the detection of an error to set the @@ -160,305 +153,305 @@ static void prvIndicateError( void ); int main( void ) { - /* Start the crystal oscillator 0 and switch the main clock to it. */ - pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP); - - portDBG_TRACE("Starting the FreeRTOS AVR32 UC3 Demo..."); - - /* Setup the LED's for output. */ - vParTestInitialise(); - - /* Start the standard demo tasks. See the WEB documentation for more - information. */ - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - - /* Start the demo tasks defined within this file, specifically the check - task as described at the top of this file. */ - xTaskCreate( - vErrorChecks - , "ErrCheck" - , configMINIMAL_STACK_SIZE - , NULL - , mainCHECK_TASK_PRIORITY - , NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - - return 0; + /* Start the crystal oscillator 0 and switch the main clock to it. */ + pm_switch_to_osc0( &AVR32_PM, FOSC0, OSC0_STARTUP ); + + portDBG_TRACE( "Starting the FreeRTOS AVR32 UC3 Demo..." ); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Start the standard demo tasks. See the WEB documentation for more + * information. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + + /* Start the demo tasks defined within this file, specifically the check + * task as described at the top of this file. */ + xTaskCreate( + vErrorChecks + , "ErrCheck" + , configMINIMAL_STACK_SIZE + , NULL + , mainCHECK_TASK_PRIORITY + , NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + * task. */ + + return 0; } /*-----------------------------------------------------------*/ -/*! - * \brief The task function for the "Check" task. +/* + * @brief The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; -unsigned long ulMemCheckTaskRunningCount; -TaskHandle_t xCreatedTask; -portBASE_TYPE bSuicidalTask = 0; - - /* The parameters are not used. Prevent compiler warnings. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. - - In addition to the standard tests the memory allocator is tested through - the dynamic creation and deletion of a task each cycle. Each time the - task is created memory must be allocated for its stack. When the task is - deleted this memory is returned to the heap. If the task cannot be created - then it is likely that the memory allocation failed. */ - - for( ;; ) - { - /* Do this only once. */ - if( bSuicidalTask == 0 ) - { - bSuicidalTask++; - - /* This task has to be created last as it keeps account of the number of - tasks it expects to see running. However its implementation expects - to be called before vTaskStartScheduler(). We're in the case here where - vTaskStartScheduler() has already been called (thus the hidden IDLE task - has already been spawned). Since vCreateSuicidalTask() supposes that the - IDLE task isn't included in the response from uxTaskGetNumberOfTasks(), - let the MEM_CHECK task play that role. => this is why vCreateSuicidalTasks() - is not called as the last task. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - } - - /* Reset xCreatedTask. This is modified by the task about to be - created so we can tell if it is executing correctly or not. */ - xCreatedTask = mainNO_TASK; - - /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a - parameter. */ - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - - if( xTaskCreate( vMemCheckTask, - "MEM_CHECK", - configMINIMAL_STACK_SIZE, - ( void * ) &ulMemCheckTaskRunningCount, - tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - /* Could not create the task - we have probably run out of heap. - Don't go any further and flash the LED faster to provide visual - feedback of the error. */ - prvIndicateError(); - } - - /* Delay until it is time to execute again. */ - vTaskDelay( mainCHECK_PERIOD ); - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ - ulDummyVariable *= 3; - - /* Check all other tasks are still operating without error. - Check that vMemCheckTask did increment the counter. */ - if( ( prvCheckOtherTasksAreStillRunning() != pdFALSE ) - || ( ulMemCheckTaskRunningCount == mainCOUNT_INITIAL_VALUE ) ) - { - /* An error has occurred in one of the tasks. - Don't go any further and flash the LED faster to give visual - feedback of the error. */ - prvIndicateError(); - } - else - { - /* Toggle the LED if everything is okay. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } - } + static volatile unsigned long ulDummyVariable = 3UL; + unsigned long ulMemCheckTaskRunningCount; + TaskHandle_t xCreatedTask; + portBASE_TYPE bSuicidalTask = 0; + + /* The parameters are not used. Prevent compiler warnings. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. + * + * In addition to the standard tests the memory allocator is tested through + * the dynamic creation and deletion of a task each cycle. Each time the + * task is created memory must be allocated for its stack. When the task is + * deleted this memory is returned to the heap. If the task cannot be created + * then it is likely that the memory allocation failed. */ + + for( ; ; ) + { + /* Do this only once. */ + if( bSuicidalTask == 0 ) + { + bSuicidalTask++; + + /* This task has to be created last as it keeps account of the number of + * tasks it expects to see running. However its implementation expects + * to be called before vTaskStartScheduler(). We're in the case here where + * vTaskStartScheduler() has already been called (thus the hidden IDLE task + * has already been spawned). Since vCreateSuicidalTask() supposes that the + * IDLE task isn't included in the response from uxTaskGetNumberOfTasks(), + * let the MEM_CHECK task play that role. => this is why vCreateSuicidalTasks() + * is not called as the last task. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + } + + /* Reset xCreatedTask. This is modified by the task about to be + * created so we can tell if it is executing correctly or not. */ + xCreatedTask = mainNO_TASK; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + * parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + + if( xTaskCreate( vMemCheckTask, + "MEM_CHECK", + configMINIMAL_STACK_SIZE, + ( void * ) &ulMemCheckTaskRunningCount, + tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. + * Don't go any further and flash the LED faster to provide visual + * feedback of the error. */ + prvIndicateError(); + } + + /* Delay until it is time to execute again. */ + vTaskDelay( mainCHECK_PERIOD ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Perform a bit of 32bit maths to ensure the registers used by the + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + /* Check all other tasks are still operating without error. + * Check that vMemCheckTask did increment the counter. */ + if( ( prvCheckOtherTasksAreStillRunning() != pdFALSE ) || + ( ulMemCheckTaskRunningCount == mainCOUNT_INITIAL_VALUE ) ) + { + /* An error has occurred in one of the tasks. + * Don't go any further and flash the LED faster to give visual + * feedback of the error. */ + prvIndicateError(); + } + else + { + /* Toggle the LED if everything is okay. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } + } } /*-----------------------------------------------------------*/ -/*! - * \brief Checks that all the demo application tasks are still executing without error. +/* + * @brief Checks that all the demo application tasks are still executing without error. */ static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - return ( xErrorHasOccurred ); + static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + return( xErrorHasOccurred ); } /*-----------------------------------------------------------*/ -/*! - * \brief Dynamically created and deleted during each cycle of the vErrorChecks() - * task. This is done to check the operation of the memory allocator. +/* + * @brief Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. * See the top of vErrorChecks for more details. * - * \param *pvParameters Parameters for the task (can be of any kind) + * @param pvParameters Parameters for the task (can be of any kind) */ -static void vMemCheckTask( void *pvParameters ) +static void vMemCheckTask( void * pvParameters ) { -unsigned long *pulMemCheckTaskRunningCounter; -void *pvMem1, *pvMem2, *pvMem3; -static long lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - else - { - /* There has been an error so reset the counter so the check task - can tell that an error occurred. */ - *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - - vTaskSuspendAll(); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll(); - } + unsigned long * pulMemCheckTaskRunningCounter; + void * pvMem1, * pvMem2, * pvMem3; + static long lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + * vErrorChecks task to check the operation of the memory allocator. Each time + * the task is created memory is allocated for the stack and TCB. Each time + * the task is deleted this memory is returned to the heap. This task itself + * exercises the allocator by allocating and freeing blocks. + * + * The task executes at the idle priority so does not require a delay. + * + * pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + * vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; + + for( ; ; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* There has been an error so reset the counter so the check task + * can tell that an error occurred. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + * exercise. This has to be in a critical section to ensure the + * task does not get deleted while it has memory allocated. */ + + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } } /*-----------------------------------------------------------*/ static void prvIndicateError( void ) { - /* The check task has found an error in one of the other tasks. - Set the LEDs to a state that indicates this. */ - vParTestSetLED(mainERROR_LED,pdTRUE); - - for(;;) - { - #if( BOARD==EVK1100 ) - vParTestToggleLED( mainCHECK_TASK_LED ); - vTaskDelay( mainERROR_FLASH_RATE ); - #endif - #if ( BOARD==EVK1101 ) - vParTestSetLED( 0, pdTRUE ); - vParTestSetLED( 1, pdTRUE ); - vParTestSetLED( 2, pdTRUE ); - vParTestSetLED( 3, pdTRUE ); - #endif - } -} - + /* The check task has found an error in one of the other tasks. + * Set the LEDs to a state that indicates this. */ + vParTestSetLED( mainERROR_LED, pdTRUE ); + + for( ; ; ) + { + #if ( BOARD == EVK1100 ) + vParTestToggleLED( mainCHECK_TASK_LED ); + vTaskDelay( mainERROR_FLASH_RATE ); + #endif + #if ( BOARD == EVK1101 ) + vParTestSetLED( 0, pdTRUE ); + vParTestSetLED( 1, pdTRUE ); + vParTestSetLED( 2, pdTRUE ); + vParTestSetLED( 3, pdTRUE ); + #endif + } +} \ No newline at end of file diff --git a/FreeRTOS/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h index 9f14b996fe5..7786d90e392 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c index 3ba67e40ae6..dae0bbeb8ab 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_IAR/main.c b/FreeRTOS/Demo/AVR_ATMega323_IAR/main.c index 4e4e75d0154..8739651b78d 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_IAR/main.c +++ b/FreeRTOS/Demo/AVR_ATMega323_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -44,45 +44,45 @@ */ /* -Changes from V1.2.0 - - + Changed the baud rate for the serial test from 19200 to 57600. - -Changes from V1.2.3 - - + The integer and comtest tasks are now used when the cooperative scheduler - is being used. Previously they were only used with the preemptive - scheduler. - -Changes from V1.2.5 - - + Set the baud rate to 38400. This has a smaller error percentage with an - 8MHz clock (according to the manual). - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - TickType_t rather than unsigned long. - -Changes from V2.2.0 - - + File can now be built using either the IAR or WinAVR compiler. - -Changes from V2.6.1 - - + The IAR and WinAVR AVR ports are now maintained separately. - -Changes from V4.0.5 - - + Modified to demonstrate the use of co-routines. -*/ + * Changes from V1.2.0 + * + + Changed the baud rate for the serial test from 19200 to 57600. + + + + Changes from V1.2.3 + + + + The integer and comtest tasks are now used when the cooperative scheduler + + is being used. Previously they were only used with the preemptive + + scheduler. + + + + Changes from V1.2.5 + + + + Set the baud rate to 38400. This has a smaller error percentage with an + + 8MHz clock (according to the manual). + + + + Changes from V2.0.0 + + + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + + + Changes from V2.2.0 + + + + File can now be built using either the IAR or WinAVR compiler. + + + + Changes from V2.6.1 + + + + The IAR and WinAVR AVR ports are now maintained separately. + + + + Changes from V4.0.5 + + + + Modified to demonstrate the use of co-routines. + */ #include #include #ifdef GCC_MEGA_AVR - /* EEPROM routines used only with the WinAVR compiler. */ - #include + /* EEPROM routines used only with the WinAVR compiler. */ + #include #endif /* Scheduler include files. */ @@ -101,39 +101,39 @@ Changes from V4.0.5 #include "regtest.h" /* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + * tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) /* Baud rate used by the serial port tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 38400 ) +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 38400 ) /* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 4 ) + * and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 4 ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 7 ) + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ +#define mainCHECK_TASK_LED ( 7 ) /* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) /* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ -#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) + * the demo application is not unexpectedly resetting. */ +#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) /* The number of coroutines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) +#define mainNUM_FLASH_COROUTINES ( 3 ) /* * The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks the unique counts of other tasks to ensure they are still operational. @@ -150,124 +150,125 @@ static void prvIncrementResetCount( void ); /* * Idle hook is used to scheduler co-routines. */ -void vApplicationIdleHook( void ); +void vApplicationIdleHook( void ); short main( void ) { - prvIncrementResetCount(); - - /* Setup the LED's for output. */ - vParTestInitialise(); - - /* Create the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartRegTestTasks(); - - /* Create the tasks defined within this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - - /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ - vTaskStartScheduler(); - - return 0; + prvIncrementResetCount(); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Create the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartRegTestTasks(); + + /* Create the tasks defined within this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + * as 1 in portmacro.h. To use the cooperative scheduler define + * configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + return 0; } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; - - /* The parameters are not used. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - vTaskDelay( mainCHECK_PERIOD ); - - /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ - ulDummyVariable *= 3; - - prvCheckOtherTasksAreStillRunning(); - } + static volatile unsigned long ulDummyVariable = 3UL; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. */ + for( ; ; ) + { + vTaskDelay( mainCHECK_PERIOD ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + prvCheckOtherTasksAreStillRunning(); + } } /*-----------------------------------------------------------*/ static void prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreRegTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xErrorHasOccurred == pdFALSE ) - { - /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } + static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreRegTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xErrorHasOccurred == pdFALSE ) + { + /* Toggle the LED if everything is okay so we know if an error occurs even if not + * using console IO. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } } /*-----------------------------------------------------------*/ static void prvIncrementResetCount( void ) { -unsigned char ucCount; -const unsigned char ucReadBit = ( unsigned char ) 0x01; -const unsigned char ucWrite1 = ( unsigned char ) 0x04; -const unsigned char ucWrite2 = ( unsigned char ) 0x02; - - /* Increment the EEPROM value at 0x00. - - Setup the EEPROM address. */ - EEARH = 0x00; - EEARL = 0x00; - - /* Set the read enable bit. */ - EECR |= ucReadBit; - - /* Wait for the read. */ - while( EECR & ucReadBit ); - - /* The byte is ready. */ - ucCount = EEDR; - - /* Increment the reset count, then write the byte back. */ - ucCount++; - EEDR = ucCount; - EECR = ucWrite1; - EECR = ( ucWrite1 | ucWrite2 ); + unsigned char ucCount; + const unsigned char ucReadBit = ( unsigned char ) 0x01; + const unsigned char ucWrite1 = ( unsigned char ) 0x04; + const unsigned char ucWrite2 = ( unsigned char ) 0x02; + + /* Increment the EEPROM value at 0x00. + * + * Setup the EEPROM address. */ + EEARH = 0x00; + EEARL = 0x00; + + /* Set the read enable bit. */ + EECR |= ucReadBit; + + /* Wait for the read. */ + while( EECR & ucReadBit ) + { + } + + /* The byte is ready. */ + ucCount = EEDR; + + /* Increment the reset count, then write the byte back. */ + ucCount++; + EEDR = ucCount; + EECR = ucWrite1; + EECR = ( ucWrite1 | ucWrite2 ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - vCoRoutineSchedule(); + vCoRoutineSchedule(); } - diff --git a/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.c b/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.c index a0f43976d44..14f050f6752 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.c +++ b/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.h b/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.h index b9a15760ff1..ee2817bc752 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.h +++ b/FreeRTOS/Demo/AVR_ATMega323_IAR/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_IAR/serial/serial.c b/FreeRTOS/Demo/AVR_ATMega323_IAR/serial/serial.c index 2a5a448c308..a12dca9189a 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_IAR/serial/serial.c +++ b/FreeRTOS/Demo/AVR_ATMega323_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h index 55538b9a8cc..cf851169806 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c index 34a57d42889..a6bf87e5971 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/main.c b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/main.c index 4221e680b85..a57ff0374cf 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/main.c +++ b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -44,42 +44,42 @@ */ /* -Changes from V1.2.0 - - + Changed the baud rate for the serial test from 19200 to 57600. - -Changes from V1.2.3 - - + The integer and comtest tasks are now used when the cooperative scheduler - is being used. Previously they were only used with the preemptive - scheduler. - -Changes from V1.2.5 - - + Set the baud rate to 38400. This has a smaller error percentage with an - 8MHz clock (according to the manual). - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - TickType_t rather than unsigned long. - -Changes from V2.6.1 - - + The IAR and WinAVR AVR ports are now maintained separately. - -Changes from V4.0.5 - - + Modified to demonstrate the use of co-routines. - -*/ + * Changes from V1.2.0 + * + + Changed the baud rate for the serial test from 19200 to 57600. + + + + Changes from V1.2.3 + + + + The integer and comtest tasks are now used when the cooperative scheduler + + is being used. Previously they were only used with the preemptive + + scheduler. + + + + Changes from V1.2.5 + + + + Set the baud rate to 38400. This has a smaller error percentage with an + + 8MHz clock (according to the manual). + + + + Changes from V2.0.0 + + + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + + + Changes from V2.6.1 + + + + The IAR and WinAVR AVR ports are now maintained separately. + + + + Changes from V4.0.5 + + + + Modified to demonstrate the use of co-routines. + + + */ #include #include #ifdef GCC_MEGA_AVR - /* EEPROM routines used only with the WinAVR compiler. */ - #include + /* EEPROM routines used only with the WinAVR compiler. */ + #include #endif /* Scheduler include files. */ @@ -98,39 +98,39 @@ Changes from V4.0.5 #include "regtest.h" /* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + * tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) /* Baud rate used by the serial port tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 38400 ) +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 38400 ) /* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 4 ) + * and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 4 ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 7 ) + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ +#define mainCHECK_TASK_LED ( 7 ) /* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) /* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ -#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) + * the demo application is not unexpectedly resetting. */ +#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) /* The number of coroutines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) +#define mainNUM_FLASH_COROUTINES ( 3 ) /* * The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks the unique counts of other tasks to ensure they are still operational. @@ -153,100 +153,99 @@ void vApplicationIdleHook( void ); short main( void ) { - prvIncrementResetCount(); + prvIncrementResetCount(); - /* Setup the LED's for output. */ - vParTestInitialise(); + /* Setup the LED's for output. */ + vParTestInitialise(); - /* Create the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartRegTestTasks(); + /* Create the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartRegTestTasks(); - /* Create the tasks defined within this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + /* Create the tasks defined within this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ - vTaskStartScheduler(); + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + * as 1 in portmacro.h. To use the cooperative scheduler define + * configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); - return 0; + return 0; } /*-----------------------------------------------------------*/ -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; + static volatile unsigned long ulDummyVariable = 3UL; - /* The parameters are not used. */ - ( void ) pvParameters; + /* The parameters are not used. */ + ( void ) pvParameters; - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - vTaskDelay( mainCHECK_PERIOD ); + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. */ + for( ; ; ) + { + vTaskDelay( mainCHECK_PERIOD ); - /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ - ulDummyVariable *= 3; + /* Perform a bit of 32bit maths to ensure the registers used by the + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ + ulDummyVariable *= 3; - prvCheckOtherTasksAreStillRunning(); - } + prvCheckOtherTasksAreStillRunning(); + } } /*-----------------------------------------------------------*/ static void prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreRegTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xErrorHasOccurred == pdFALSE ) - { - /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } + static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreRegTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xErrorHasOccurred == pdFALSE ) + { + /* Toggle the LED if everything is okay so we know if an error occurs even if not + * using console IO. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } } /*-----------------------------------------------------------*/ static void prvIncrementResetCount( void ) { -unsigned char ucCount; + unsigned char ucCount; - eeprom_read_block( &ucCount, mainRESET_COUNT_ADDRESS, sizeof( ucCount ) ); - ucCount++; - eeprom_write_byte( mainRESET_COUNT_ADDRESS, ucCount ); + eeprom_read_block( &ucCount, mainRESET_COUNT_ADDRESS, sizeof( ucCount ) ); + ucCount++; + eeprom_write_byte( mainRESET_COUNT_ADDRESS, ucCount ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - vCoRoutineSchedule(); + vCoRoutineSchedule(); } - diff --git a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.c b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.c index 0834b1a6714..c64decc318e 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.c +++ b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.h b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.h index b9a15760ff1..ee2817bc752 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.h +++ b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/serial/serial.c b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/serial/serial.c index 788cd51c0c6..9941e76d1e9 100644 --- a/FreeRTOS/Demo/AVR_ATMega323_WinAVR/serial/serial.c +++ b/FreeRTOS/Demo/AVR_ATMega323_WinAVR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h index 5a52f70e584..88ed213382d 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/ParTest/ParTest.c b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/ParTest/ParTest.c index 49b8bf36216..e1f465090ea 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/ParTest/ParTest.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_blinky.c b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_blinky.c index bc457b262a4..d078e23bc68 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_blinky.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_minimal.c b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_minimal.c index 9593b042501..95a202e87c7 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_minimal.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/main_minimal.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.c b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.c index 83acef7057a..a6e5aa56b8b 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.h b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.h index e883ac7287c..fc3e57c1dc9 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.h +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/serial/serial.c b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/serial/serial.c index 16ba888cf87..da33f2846d4 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/serial/serial.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_ATMega4809_IAR/FreeRTOSConfig.h index e0519588ac7..39a5ada1738 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/ParTest/ParTest.c index 49b8bf36216..e1f465090ea 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main.c index a19870dc52c..450efe8785c 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main.c @@ -1,22 +1,22 @@ /* -(C) 2020 Microchip Technology Inc. and its subsidiaries. - -Subject to your compliance with these terms, you may use Microchip software and -any derivatives exclusively with Microchip products. It is your responsibility -to comply with third party license terms applicable to your use of third party -software (including open source software) that may accompany Microchip software. - -THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, -IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES -OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. -IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER -RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF -THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED -BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS -SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY -TO MICROCHIP FOR THIS SOFTWARE. -*/ + * (C) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and + * any derivatives exclusively with Microchip products. It is your responsibility + * to comply with third party license terms applicable to your use of third party + * software (including open source software) that may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, + * IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES + * OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, + * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER + * RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF + * THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED + * BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS + * SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY + * TO MICROCHIP FOR THIS SOFTWARE. + */ #include #include "FreeRTOS.h" @@ -28,29 +28,29 @@ TO MICROCHIP FOR THIS SOFTWARE. static void prvSetupHardware( void ); #if ( mainSELECTED_APPLICATION == 0 ) -extern void main_blinky( void ); -extern void init_blinky( void ); + extern void main_blinky( void ); + extern void init_blinky( void ); #elif ( mainSELECTED_APPLICATION == 1 ) -extern void main_minimal( void ); -extern void init_minimal( void ); + extern void main_minimal( void ); + extern void init_minimal( void ); #elif ( mainSELECTED_APPLICATION == 2 ) -extern void main_full( void ); -extern void init_full( void ); + extern void main_full( void ); + extern void init_full( void ); #else -#error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. #endif int main( void ) { prvSetupHardware(); -#if ( mainSELECTED_APPLICATION == 0 ) - main_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - main_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - main_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + main_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + main_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + main_full(); + #endif return 0; } @@ -58,37 +58,37 @@ int main( void ) static void prvSetupHardware( void ) { /* Ensure no interrupts execute while the scheduler is in an inconsistent - state. Interrupts are automatically enabled when the scheduler is - started. */ + * state. Interrupts are automatically enabled when the scheduler is + * started. */ portDISABLE_INTERRUPTS(); CLK_init(); -#if ( mainSELECTED_APPLICATION == 0 ) - init_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - init_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - init_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + init_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + init_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + init_full(); + #endif } /* vApplicationStackOverflowHook is called when a stack overflow occurs. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in -"FreeRTOSConfig.h" header file. */ + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in + * "FreeRTOSConfig.h" header file. */ -// void vApplicationStackOverflowHook(TaskHandle_t *pxTask, char *pcTaskName ) -// { -// for( ;; ); -// } +/* void vApplicationStackOverflowHook(TaskHandle_t *pxTask, char *pcTaskName ) */ +/* { */ +/* for( ;; ); */ +/* } */ /* vApplicationMallocFailedHook is called when memorry allocation fails. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in -"FreeRTOSConfig.h" header file. */ - -// void vApplicationMallocFailedHook( void ) -// { -// for( ;; ); -// } + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in + * "FreeRTOSConfig.h" header file. */ + +/* void vApplicationMallocFailedHook( void ) */ +/* { */ +/* for( ;; ); */ +/* } */ diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_blinky.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_blinky.c index 9c10ef24250..7b9f14c716c 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_blinky.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -59,25 +59,25 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -87,18 +87,18 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + if( xQueue != NULL ) { /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); @@ -107,14 +107,16 @@ void main_blinky( void ) } /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_blinky( void ) @@ -123,10 +125,10 @@ void init_blinky( void ) PORTF.DIRSET = PIN5_bm; } -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; @@ -134,37 +136,37 @@ const unsigned long ulValueToSend = 100UL; /* Initialise xNextWakeTime - this only needs to be done once. */ xNextWakeTime = xTaskGetTickCount(); - for( ;; ) + for( ; ; ) { /* Place this task in the blocked state until it is time to run again. */ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ xQueueSend( xQueue, &ulValueToSend, 0U ); } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; + unsigned long ulReceivedValue; + const unsigned long ulExpectedValue = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; - for( ;; ) + for( ; ; ) { /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ + * is it the expected value? If it is, toggle the LED. */ if( ulReceivedValue == ulExpectedValue ) { /* Toggle LED on pin PF5. */ @@ -173,4 +175,3 @@ const unsigned long ulExpectedValue = 100UL; } } } - diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_full.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_full.c index 97de9502f96..d1606a8cd35 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_full.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_full.c @@ -7,46 +7,47 @@ #include "regtest.h" #include "recmutex.h" -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 5 ) + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ +#define mainCHECK_TASK_LED ( 5 ) /* * The check task, as described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); void main_full( void ) { - - vStartSemaphoreTasks(mainSEM_TEST_PRIORITY); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); vStartTaskNotifyTask(); vStartRegTestTasks(); vStartRecursiveMutexTasks(); - + /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ + * the top of this file. */ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); vTaskStartScheduler(); - + /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_full( void ) @@ -54,52 +55,52 @@ void init_full( void ) vParTestInitialise(); } -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -TickType_t xLastExecutionTime; -unsigned long ulErrorFound = pdFALSE; + TickType_t xLastExecutionTime; + unsigned long ulErrorFound = pdFALSE; /* Just to stop compiler warnings. */ ( void ) pvParameters; /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ + * works correctly. */ xLastExecutionTime = xTaskGetTickCount(); /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration - unless an error occurred. */ - for( ;; ) + * operating without error. The onboard LED is toggled on each iteration + * unless an error occurred. */ + for( ; ; ) { /* Delay until it is time to execute again. */ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_PERIOD ); /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ + * that they are all still running, and that none have detected an error. */ if( xAreSemaphoreTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 0UL; } - + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 1UL; } - + if( xAreRegTestTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 2UL; } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 3UL; } - + if( ulErrorFound == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_minimal.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_minimal.c index 21860a96ec5..27f6b00d7aa 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_minimal.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/main_minimal.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,7 +37,7 @@ #include "regtest.h" /* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ + * tasks just use the idle priority. */ #define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) @@ -46,20 +46,20 @@ tasks just use the idle priority. */ #define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 9600 ) /* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ + * and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ #define mainCOM_TEST_LED ( 6 ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ #define mainCHECK_TASK_LED ( 5 ) /* The period between executions of the check task. */ #define mainCHECK_PERIOD ( ( TickType_t ) 1000 / portTICK_PERIOD_MS ) /* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ + * the demo application is not unexpectedly resetting. */ #define mainRESET_COUNT_ADDRESS ( 0x1400 ) /* The number of coroutines to create. */ @@ -68,7 +68,7 @@ the demo application is not unexpectedly resetting. */ /* * The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks the unique counts of other tasks to ensure they are still operational. @@ -91,16 +91,16 @@ void main_minimal( void ) vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); vStartRegTestTasks(); - + /* Create the tasks defined within this file. */ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); /* Create the co-routines that flash the LED's. */ vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ + * as 1 in portmacro.h. To use the cooperative scheduler define + * configUSE_PREEMPTION as 0. */ vTaskStartScheduler(); } @@ -109,28 +109,28 @@ void init_minimal( void ) /* Configure UART pins: PB0 Rx, PB1 Tx */ PORTB.DIR &= ~PIN1_bm; PORTB.DIR |= PIN0_bm; - + vParTestInitialise(); } -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; + static volatile unsigned long ulDummyVariable = 3UL; /* The parameters are not used. */ ( void ) pvParameters; /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) + * operating without error. */ + for( ; ; ) { vTaskDelay( mainCHECK_PERIOD ); /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ ulDummyVariable *= 3; - + prvCheckOtherTasksAreStillRunning(); } } @@ -138,7 +138,7 @@ static volatile unsigned long ulDummyVariable = 3UL; static void prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; + static portBASE_TYPE xErrorHasOccurred = pdFALSE; if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) { @@ -159,11 +159,11 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; { xErrorHasOccurred = pdTRUE; } - + if( xErrorHasOccurred == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } @@ -171,7 +171,7 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; static void prvIncrementResetCount( void ) { -static unsigned char __eeprom ucResetCount @ mainRESET_COUNT_ADDRESS; + static unsigned char __eeprom ucResetCount @ mainRESET_COUNT_ADDRESS; ucResetCount++; } diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.c index c159de453e3..220298db620 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.h b/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.h index e883ac7287c..fc3e57c1dc9 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.h +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_IAR/serial/serial.c b/FreeRTOS/Demo/AVR_ATMega4809_IAR/serial/serial.c index 69eb3138daa..683266ef297 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_IAR/serial/serial.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/FreeRTOSConfig.h index 09084506b79..61704f8d69c 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/ParTest/ParTest.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/ParTest/ParTest.c index 49b8bf36216..e1f465090ea 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/ParTest/ParTest.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main.c index e7e32f0943d..1088b1f7835 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main.c @@ -1,22 +1,22 @@ /* -(C) 2020 Microchip Technology Inc. and its subsidiaries. - -Subject to your compliance with these terms, you may use Microchip software and -any derivatives exclusively with Microchip products. It is your responsibility -to comply with third party license terms applicable to your use of third party -software (including open source software) that may accompany Microchip software. - -THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, -IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES -OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. -IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER -RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF -THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED -BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS -SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY -TO MICROCHIP FOR THIS SOFTWARE. -*/ + * (C) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and + * any derivatives exclusively with Microchip products. It is your responsibility + * to comply with third party license terms applicable to your use of third party + * software (including open source software) that may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, + * IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES + * OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, + * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER + * RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF + * THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED + * BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS + * SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY + * TO MICROCHIP FOR THIS SOFTWARE. + */ #include #include "FreeRTOS.h" @@ -28,29 +28,29 @@ TO MICROCHIP FOR THIS SOFTWARE. static void prvSetupHardware( void ); #if ( mainSELECTED_APPLICATION == 0 ) -extern void main_blinky( void ); -extern void init_blinky( void ); + extern void main_blinky( void ); + extern void init_blinky( void ); #elif ( mainSELECTED_APPLICATION == 1 ) -extern void main_minimal( void ); -extern void init_minimal( void ); + extern void main_minimal( void ); + extern void init_minimal( void ); #elif ( mainSELECTED_APPLICATION == 2 ) -extern void main_full( void ); -extern void init_full( void ); + extern void main_full( void ); + extern void init_full( void ); #else -#error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. #endif int main( void ) { prvSetupHardware(); -#if ( mainSELECTED_APPLICATION == 0 ) - main_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - main_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - main_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + main_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + main_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + main_full(); + #endif return 0; } @@ -58,37 +58,58 @@ int main( void ) static void prvSetupHardware( void ) { /* Ensure no interrupts execute while the scheduler is in an inconsistent - state. Interrupts are automatically enabled when the scheduler is - started. */ + * state. Interrupts are automatically enabled when the scheduler is + * started. */ portDISABLE_INTERRUPTS(); CLK_init(); -#if ( mainSELECTED_APPLICATION == 0 ) - init_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - init_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - init_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + init_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + init_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + init_full(); + #endif } /* vApplicationStackOverflowHook is called when a stack overflow occurs. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in -"FreeRTOSConfig.h" header file. */ - -// void vApplicationStackOverflowHook(TaskHandle_t *pxTask, char *pcTaskName ) -// { -// for( ;; ); -// } + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in + * "FreeRTOSConfig.h" header file. */ + +#if ( portHAS_STACK_OVERFLOW_CHECKING != 0 ) && ( configCHECK_FOR_STACK_OVERFLOW != 0 ) + void vApplicationStackOverflowHook( void ) + { + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + taskENTER_CRITICAL(); + /* To debug this failure set ulSetToNonZeroInDebuggerToContinue + * to a non-zero value using a debugger. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + portNOP(); + } + taskEXIT_CRITICAL(); + } +#endif /* ( portHAS_STACK_OVERFLOW_CHECKING != 0 ) && ( configCHECK_FOR_STACK_OVERFLOW != 0 ) */ /* vApplicationMallocFailedHook is called when memorry allocation fails. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in -"FreeRTOSConfig.h" header file. */ - -// void vApplicationMallocFailedHook( void ) -// { -// for( ;; ); -// } + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in + * "FreeRTOSConfig.h" header file. */ + +#if ( configUSE_MALLOC_FAILED_HOOK != 0 ) + void vApplicationMallocFailedHook( void ) + { + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + taskENTER_CRITICAL(); + /* To debug this failure set ulSetToNonZeroInDebuggerToContinue + * to a non-zero value using a debugger. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + /* No-Op */ + portNOP(); + } + taskEXIT_CRITICAL(); + } +#endif /* configUSE_MALLOC_FAILED_HOOK */ diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_blinky.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_blinky.c index bc457b262a4..8c2567f6175 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_blinky.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -59,25 +59,25 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -87,18 +87,18 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + if( xQueue != NULL ) { /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); @@ -107,14 +107,16 @@ void main_blinky( void ) } /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_blinky( void ) @@ -123,10 +125,10 @@ void init_blinky( void ) PORTF.DIRSET = PIN5_bm; } -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; @@ -134,37 +136,37 @@ const unsigned long ulValueToSend = 100UL; /* Initialise xNextWakeTime - this only needs to be done once. */ xNextWakeTime = xTaskGetTickCount(); - for( ;; ) + for( ; ; ) { /* Place this task in the blocked state until it is time to run again. */ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ xQueueSend( xQueue, &ulValueToSend, 0U ); } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; + unsigned long ulReceivedValue; + const unsigned long ulExpectedValue = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; - for( ;; ) + for( ; ; ) { /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ + * is it the expected value? If it is, toggle the LED. */ if( ulReceivedValue == ulExpectedValue ) { /* Toggle LED on pin PF5. */ diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_full.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_full.c index 5bd35b256eb..8cf20a53c10 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_full.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_full.c @@ -6,43 +6,45 @@ #include "regtest.h" #include "recmutex.h" -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 5 ) + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ +#define mainCHECK_TASK_LED ( 5 ) /* The check task, as described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); void main_full( void ) { - vStartSemaphoreTasks(mainSEM_TEST_PRIORITY); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); vStartTaskNotifyTask(); vStartRegTestTasks(); vStartRecursiveMutexTasks(); /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ + * the top of this file. */ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); vTaskStartScheduler(); - + /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_full( void ) @@ -50,52 +52,52 @@ void init_full( void ) vParTestInitialise(); } -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -TickType_t xLastExecutionTime; -unsigned long ulErrorFound = pdFALSE; + TickType_t xLastExecutionTime; + unsigned long ulErrorFound = pdFALSE; /* Just to stop compiler warnings. */ ( void ) pvParameters; /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ + * works correctly. */ xLastExecutionTime = xTaskGetTickCount(); /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration - unless an error occurred. */ - for( ;; ) + * operating without error. The onboard LED is toggled on each iteration + * unless an error occurred. */ + for( ; ; ) { /* Delay until it is time to execute again. */ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_PERIOD ); /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ + * that they are all still running, and that none have detected an error. */ if( xAreSemaphoreTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 0UL; } - + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 1UL; } - + if( xAreRegTestTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 2UL; } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 3UL; } - + if( ulErrorFound == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_minimal.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_minimal.c index 9593b042501..5b9bb8123ca 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_minimal.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/main_minimal.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -38,7 +38,7 @@ #include "regtest.h" /* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ + * tasks just use the idle priority. */ #define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) @@ -47,20 +47,20 @@ tasks just use the idle priority. */ #define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 9600 ) /* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ + * and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ #define mainCOM_TEST_LED ( 6 ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ #define mainCHECK_TASK_LED ( 5 ) /* The period between executions of the check task. */ #define mainCHECK_PERIOD ( ( TickType_t ) 1000 / portTICK_PERIOD_MS ) /* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ + * the demo application is not unexpectedly resetting. */ #define mainRESET_COUNT_ADDRESS ( 0x1400 ) /* The number of coroutines to create. */ @@ -69,7 +69,7 @@ the demo application is not unexpectedly resetting. */ /* * The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks the unique counts of other tasks to ensure they are still operational. @@ -92,16 +92,16 @@ void main_minimal( void ) vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); vStartRegTestTasks(); - + /* Create the tasks defined within this file. */ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); /* Create the co-routines that flash the LED's. */ vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ + * as 1 in portmacro.h. To use the cooperative scheduler define + * configUSE_PREEMPTION as 0. */ vTaskStartScheduler(); } @@ -110,28 +110,28 @@ void init_minimal( void ) /* Configure UART pins: PB0 Rx, PB1 Tx */ PORTB.DIR &= ~PIN1_bm; PORTB.DIR |= PIN0_bm; - + vParTestInitialise(); } -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; + static volatile unsigned long ulDummyVariable = 3UL; /* The parameters are not used. */ ( void ) pvParameters; /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) + * operating without error. */ + for( ; ; ) { vTaskDelay( mainCHECK_PERIOD ); /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ ulDummyVariable *= 3; - + prvCheckOtherTasksAreStillRunning(); } } @@ -139,7 +139,7 @@ static volatile unsigned long ulDummyVariable = 3UL; static void prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; + static portBASE_TYPE xErrorHasOccurred = pdFALSE; if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) { @@ -160,11 +160,11 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; { xErrorHasOccurred = pdTRUE; } - + if( xErrorHasOccurred == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } @@ -172,7 +172,7 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; static void prvIncrementResetCount( void ) { -unsigned char ucResetCount; + unsigned char ucResetCount; eeprom_read_block( &ucResetCount, ( void * ) mainRESET_COUNT_ADDRESS, sizeof( ucResetCount ) ); ucResetCount++; diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.c index 7e01a663d46..7d0251059ec 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.h b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.h index e883ac7287c..fc3e57c1dc9 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.h +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/serial/serial.c b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/serial/serial.c index 16ba888cf87..da33f2846d4 100644 --- a/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/serial/serial.c +++ b/FreeRTOS/Demo/AVR_ATMega4809_MPLAB.X/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/FreeRTOSConfig.h index f69f5a1ab7c..bace37cc4a4 100644 --- a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/ParTest.c b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/ParTest.c index 240a339b3fc..e67841722e9 100644 --- a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/ParTest.c +++ b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/main.c b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/main.c index 53497f92303..90103f2802f 100644 --- a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/main.c +++ b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.c b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.c index a57fe8b368e..55ae7e9b1d8 100644 --- a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.c +++ b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.h b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.h index 146591586b7..076808cca69 100644 --- a/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.h +++ b/FreeRTOS/Demo/AVR_ATmega328PB_Xplained_mini_GCC/RTOSDemo/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h index 544b54eaeb4..e0f4321e5d4 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/ParTest/partest.c b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/ParTest/partest.c index 27a269c0368..e5a1b69ee99 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/ParTest/partest.c +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/ParTest/partest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_blinky.c b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_blinky.c index b941f928a17..db9fb594460 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_blinky.c +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_minimal.c b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_minimal.c index bf54d4b5c0d..8cbf2b0b02b 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_minimal.c +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/main_minimal.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.c b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.c index 83acef7057a..a6e5aa56b8b 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.c +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.h b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.h index fbaa9534de8..8d28ee9ad25 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.h +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/regtest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/serial/serial.c b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/serial/serial.c index efda48f84e2..5b10c28e2f5 100644 --- a/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/serial/serial.c +++ b/FreeRTOS/Demo/AVR_Dx_Atmel_Studio/RTOSDemo/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_Dx_IAR/FreeRTOSConfig.h index b38ad18cdd2..d61870e8835 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_Dx_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/ParTest/partest.c b/FreeRTOS/Demo/AVR_Dx_IAR/ParTest/partest.c index 27a269c0368..e5a1b69ee99 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/ParTest/partest.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/ParTest/partest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.c b/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.c index c159de453e3..220298db620 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.h b/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.h index e883ac7287c..fc3e57c1dc9 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.h +++ b/FreeRTOS/Demo/AVR_Dx_IAR/RegTest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/main.c b/FreeRTOS/Demo/AVR_Dx_IAR/main.c index a19870dc52c..b2fc4894249 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/main.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/main.c @@ -1,22 +1,22 @@ /* -(C) 2020 Microchip Technology Inc. and its subsidiaries. - -Subject to your compliance with these terms, you may use Microchip software and -any derivatives exclusively with Microchip products. It is your responsibility -to comply with third party license terms applicable to your use of third party -software (including open source software) that may accompany Microchip software. - -THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, -IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES -OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. -IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER -RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF -THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED -BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS -SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY -TO MICROCHIP FOR THIS SOFTWARE. -*/ + * (C) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and + * any derivatives exclusively with Microchip products. It is your responsibility + * to comply with third party license terms applicable to your use of third party + * software (including open source software) that may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, + * IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES + * OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, + * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER + * RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF + * THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED + * BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS + * SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY + * TO MICROCHIP FOR THIS SOFTWARE. + */ #include #include "FreeRTOS.h" @@ -28,29 +28,29 @@ TO MICROCHIP FOR THIS SOFTWARE. static void prvSetupHardware( void ); #if ( mainSELECTED_APPLICATION == 0 ) -extern void main_blinky( void ); -extern void init_blinky( void ); + extern void main_blinky( void ); + extern void init_blinky( void ); #elif ( mainSELECTED_APPLICATION == 1 ) -extern void main_minimal( void ); -extern void init_minimal( void ); + extern void main_minimal( void ); + extern void init_minimal( void ); #elif ( mainSELECTED_APPLICATION == 2 ) -extern void main_full( void ); -extern void init_full( void ); + extern void main_full( void ); + extern void init_full( void ); #else -#error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. #endif int main( void ) { prvSetupHardware(); -#if ( mainSELECTED_APPLICATION == 0 ) - main_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - main_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - main_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + main_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + main_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + main_full(); + #endif return 0; } @@ -58,37 +58,58 @@ int main( void ) static void prvSetupHardware( void ) { /* Ensure no interrupts execute while the scheduler is in an inconsistent - state. Interrupts are automatically enabled when the scheduler is - started. */ + * state. Interrupts are automatically enabled when the scheduler is + * started. */ portDISABLE_INTERRUPTS(); CLK_init(); -#if ( mainSELECTED_APPLICATION == 0 ) - init_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - init_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - init_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + init_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + init_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + init_full(); + #endif } /* vApplicationStackOverflowHook is called when a stack overflow occurs. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in -"FreeRTOSConfig.h" header file. */ - -// void vApplicationStackOverflowHook(TaskHandle_t *pxTask, char *pcTaskName ) -// { -// for( ;; ); -// } + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in + * "FreeRTOSConfig.h" header file. */ + +#if ( portHAS_STACK_OVERFLOW_CHECKING != 0 ) && ( configCHECK_FOR_STACK_OVERFLOW != 0 ) + void vApplicationStackOverflowHook( void ) + { + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + taskENTER_CRITICAL(); + /* To debug this failure set ulSetToNonZeroInDebuggerToContinue + * to a non-zero value using a debugger. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + portNOP(); + } + taskEXIT_CRITICAL(); + } +#endif /* ( portHAS_STACK_OVERFLOW_CHECKING != 0 ) && ( configCHECK_FOR_STACK_OVERFLOW != 0 ) */ /* vApplicationMallocFailedHook is called when memorry allocation fails. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in -"FreeRTOSConfig.h" header file. */ - -// void vApplicationMallocFailedHook( void ) -// { -// for( ;; ); -// } + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in + * "FreeRTOSConfig.h" header file. */ + +#if ( configUSE_MALLOC_FAILED_HOOK != 0 ) + void vApplicationMallocFailedHook( void ) + { + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + taskENTER_CRITICAL(); + /* To debug this failure set ulSetToNonZeroInDebuggerToContinue + * to a non-zero value using a debugger. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + /* No-Op */ + portNOP(); + } + taskEXIT_CRITICAL(); + } +#endif /* configUSE_MALLOC_FAILED_HOOK */ diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/main_blinky.c b/FreeRTOS/Demo/AVR_Dx_IAR/main_blinky.c index 5a2fac95f58..76640b9a41d 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/main_blinky.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -59,25 +59,25 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -87,18 +87,18 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + if( xQueue != NULL ) { /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); @@ -107,14 +107,16 @@ void main_blinky( void ) } /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_blinky( void ) @@ -123,10 +125,10 @@ void init_blinky( void ) PORTC.DIRSET = PIN6_bm; } -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; @@ -134,37 +136,37 @@ const unsigned long ulValueToSend = 100UL; /* Initialise xNextWakeTime - this only needs to be done once. */ xNextWakeTime = xTaskGetTickCount(); - for( ;; ) + for( ; ; ) { /* Place this task in the blocked state until it is time to run again. */ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ xQueueSend( xQueue, &ulValueToSend, 0U ); } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; + unsigned long ulReceivedValue; + const unsigned long ulExpectedValue = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; - for( ;; ) + for( ; ; ) { /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ + * is it the expected value? If it is, toggle the LED. */ if( ulReceivedValue == ulExpectedValue ) { /* Toggle LED on pin PC6. */ @@ -173,4 +175,3 @@ const unsigned long ulExpectedValue = 100UL; } } } - diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/main_full.c b/FreeRTOS/Demo/AVR_Dx_IAR/main_full.c index 7759a6fae63..d64cfa693bd 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/main_full.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/main_full.c @@ -7,46 +7,47 @@ #include "regtest.h" #include "recmutex.h" -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 6 ) + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ +#define mainCHECK_TASK_LED ( 6 ) /* * The check task, as described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); void main_full( void ) { - - vStartSemaphoreTasks(mainSEM_TEST_PRIORITY); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); vStartTaskNotifyTask(); vStartRegTestTasks(); vStartRecursiveMutexTasks(); - + /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ + * the top of this file. */ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); vTaskStartScheduler(); - + /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_full( void ) @@ -54,52 +55,52 @@ void init_full( void ) vParTestInitialise(); } -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -TickType_t xLastExecutionTime; -unsigned long ulErrorFound = pdFALSE; + TickType_t xLastExecutionTime; + unsigned long ulErrorFound = pdFALSE; /* Just to stop compiler warnings. */ ( void ) pvParameters; /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ + * works correctly. */ xLastExecutionTime = xTaskGetTickCount(); /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration - unless an error occurred. */ - for( ;; ) + * operating without error. The onboard LED is toggled on each iteration + * unless an error occurred. */ + for( ; ; ) { /* Delay until it is time to execute again. */ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_PERIOD ); /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ + * that they are all still running, and that none have detected an error. */ if( xAreSemaphoreTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 0UL; } - + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 1UL; } - + if( xAreRegTestTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 2UL; } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 3UL; } - + if( ulErrorFound == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/main_minimal.c b/FreeRTOS/Demo/AVR_Dx_IAR/main_minimal.c index 60999311ba8..9e489795125 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/main_minimal.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/main_minimal.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,7 +37,7 @@ #include "regtest.h" /* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ + * tasks just use the idle priority. */ #define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) @@ -46,20 +46,20 @@ tasks just use the idle priority. */ #define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 9600 ) /* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ + * and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ #define mainCOM_TEST_LED ( 7 ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ #define mainCHECK_TASK_LED ( 6 ) /* The period between executions of the check task. */ #define mainCHECK_PERIOD ( ( TickType_t ) 1000 / portTICK_PERIOD_MS ) /* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ + * the demo application is not unexpectedly resetting. */ #define mainRESET_COUNT_ADDRESS ( 0x1400 ) /* The number of coroutines to create. */ @@ -68,7 +68,7 @@ the demo application is not unexpectedly resetting. */ /* * The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks the unique counts of other tasks to ensure they are still operational. @@ -91,16 +91,16 @@ void main_minimal( void ) vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); vStartRegTestTasks(); - + /* Create the tasks defined within this file. */ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); /* Create the co-routines that flash the LED's. */ vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ + * as 1 in portmacro.h. To use the cooperative scheduler define + * configUSE_PREEMPTION as 0. */ vTaskStartScheduler(); } @@ -109,28 +109,28 @@ void init_minimal( void ) /* Configure UART pins: PC1 Rx, PC0 Tx */ PORTC.DIR &= ~PIN0_bm; PORTC.DIR |= PIN1_bm; - + vParTestInitialise(); } -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; + static volatile unsigned long ulDummyVariable = 3UL; /* The parameters are not used. */ ( void ) pvParameters; /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) + * operating without error. */ + for( ; ; ) { vTaskDelay( mainCHECK_PERIOD ); /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ ulDummyVariable *= 3; - + prvCheckOtherTasksAreStillRunning(); } } @@ -138,7 +138,7 @@ static volatile unsigned long ulDummyVariable = 3UL; static void prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; + static portBASE_TYPE xErrorHasOccurred = pdFALSE; if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) { @@ -159,11 +159,11 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; { xErrorHasOccurred = pdTRUE; } - + if( xErrorHasOccurred == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } @@ -171,7 +171,7 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; static void prvIncrementResetCount( void ) { -static unsigned char __eeprom ucResetCount @ mainRESET_COUNT_ADDRESS; + static unsigned char __eeprom ucResetCount @ mainRESET_COUNT_ADDRESS; ucResetCount++; } diff --git a/FreeRTOS/Demo/AVR_Dx_IAR/serial/serial.c b/FreeRTOS/Demo/AVR_Dx_IAR/serial/serial.c index 996315edddb..8bba640d9dd 100644 --- a/FreeRTOS/Demo/AVR_Dx_IAR/serial/serial.c +++ b/FreeRTOS/Demo/AVR_Dx_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/FreeRTOSConfig.h b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/FreeRTOSConfig.h index 87f8ec46084..47487f492e6 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/ParTest/partest.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/ParTest/partest.c index 27a269c0368..e5a1b69ee99 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/ParTest/partest.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/ParTest/partest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.c index 7e01a663d46..7d0251059ec 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.h b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.h index fbaa9534de8..8d28ee9ad25 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.h +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/RegTest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main.c index 8d7412fe11c..1088b1f7835 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main.c @@ -1,22 +1,22 @@ /* -(C) 2020 Microchip Technology Inc. and its subsidiaries. - -Subject to your compliance with these terms, you may use Microchip software and -any derivatives exclusively with Microchip products. It is your responsibility -to comply with third party license terms applicable to your use of third party -software (including open source software) that may accompany Microchip software. - -THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, -IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES -OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. -IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER -RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF -THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED -BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS -SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY -TO MICROCHIP FOR THIS SOFTWARE. -*/ + * (C) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and + * any derivatives exclusively with Microchip products. It is your responsibility + * to comply with third party license terms applicable to your use of third party + * software (including open source software) that may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, + * IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES + * OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, + * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER + * RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF + * THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED + * BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS + * SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY + * TO MICROCHIP FOR THIS SOFTWARE. + */ #include #include "FreeRTOS.h" @@ -28,67 +28,88 @@ TO MICROCHIP FOR THIS SOFTWARE. static void prvSetupHardware( void ); #if ( mainSELECTED_APPLICATION == 0 ) -extern void main_blinky( void ); -extern void init_blinky( void ); + extern void main_blinky( void ); + extern void init_blinky( void ); #elif ( mainSELECTED_APPLICATION == 1 ) -extern void main_minimal( void ); -extern void init_minimal( void ); + extern void main_minimal( void ); + extern void init_minimal( void ); #elif ( mainSELECTED_APPLICATION == 2 ) -extern void main_full( void ); -extern void init_full( void ); + extern void main_full( void ); + extern void init_full( void ); #else -#error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. #endif int main( void ) { prvSetupHardware(); -#if ( mainSELECTED_APPLICATION == 0 ) - main_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - main_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - main_full(); -#endif - + #if ( mainSELECTED_APPLICATION == 0 ) + main_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + main_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + main_full(); + #endif + return 0; } static void prvSetupHardware( void ) { /* Ensure no interrupts execute while the scheduler is in an inconsistent - state. Interrupts are automatically enabled when the scheduler is - started. */ + * state. Interrupts are automatically enabled when the scheduler is + * started. */ portDISABLE_INTERRUPTS(); CLK_init(); -#if ( mainSELECTED_APPLICATION == 0 ) - init_blinky(); -#elif ( mainSELECTED_APPLICATION == 1 ) - init_minimal(); -#elif ( mainSELECTED_APPLICATION == 2 ) - init_full(); -#endif + #if ( mainSELECTED_APPLICATION == 0 ) + init_blinky(); + #elif ( mainSELECTED_APPLICATION == 1 ) + init_minimal(); + #elif ( mainSELECTED_APPLICATION == 2 ) + init_full(); + #endif } /* vApplicationStackOverflowHook is called when a stack overflow occurs. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in -"FreeRTOSConfig.h" header file. */ + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configCHECK_FOR_STACK_OVERFLOW to 1 in + * "FreeRTOSConfig.h" header file. */ -// void vApplicationStackOverflowHook(TaskHandle_t *pxTask, char *pcTaskName ) -// { -// for( ;; ); -// } +#if ( portHAS_STACK_OVERFLOW_CHECKING != 0 ) && ( configCHECK_FOR_STACK_OVERFLOW != 0 ) + void vApplicationStackOverflowHook( void ) + { + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + taskENTER_CRITICAL(); + /* To debug this failure set ulSetToNonZeroInDebuggerToContinue + * to a non-zero value using a debugger. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + portNOP(); + } + taskEXIT_CRITICAL(); + } +#endif /* ( portHAS_STACK_OVERFLOW_CHECKING != 0 ) && ( configCHECK_FOR_STACK_OVERFLOW != 0 ) */ /* vApplicationMallocFailedHook is called when memorry allocation fails. -This is usefull in application development, for debugging. To use this -hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in -"FreeRTOSConfig.h" header file. */ + * This is usefull in application development, for debugging. To use this + * hook, uncomment it, and set configUSE_MALLOC_FAILED_HOOK to 1 in + * "FreeRTOSConfig.h" header file. */ -// void vApplicationMallocFailedHook( void ) -// { -// for( ;; ); -// } +#if ( configUSE_MALLOC_FAILED_HOOK != 0 ) + void vApplicationMallocFailedHook( void ) + { + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + taskENTER_CRITICAL(); + /* To debug this failure set ulSetToNonZeroInDebuggerToContinue + * to a non-zero value using a debugger. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + /* No-Op */ + portNOP(); + } + taskEXIT_CRITICAL(); + } +#endif /* configUSE_MALLOC_FAILED_HOOK */ diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_blinky.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_blinky.c index 8e4c7f3a307..f436ca8bac7 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_blinky.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -59,25 +59,25 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -87,18 +87,18 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + if( xQueue != NULL ) { /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); @@ -107,14 +107,16 @@ void main_blinky( void ) } /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_blinky( void ) @@ -123,10 +125,10 @@ void init_blinky( void ) PORTC.DIRSET = PIN6_bm; } -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; @@ -134,37 +136,37 @@ const unsigned long ulValueToSend = 100UL; /* Initialise xNextWakeTime - this only needs to be done once. */ xNextWakeTime = xTaskGetTickCount(); - for( ;; ) + for( ; ; ) { /* Place this task in the blocked state until it is time to run again. */ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ xQueueSend( xQueue, &ulValueToSend, 0U ); } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; + unsigned long ulReceivedValue; + const unsigned long ulExpectedValue = 100UL; /* Remove compiler warning about unused parameter. */ ( void ) pvParameters; - for( ;; ) + for( ; ; ) { /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ + * is it the expected value? If it is, toggle the LED. */ if( ulReceivedValue == ulExpectedValue ) { /* Toggle LED on pin PC6. */ diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_full.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_full.c index 8f18a0c335e..027293c2a5d 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_full.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_full.c @@ -6,43 +6,45 @@ #include "regtest.h" #include "recmutex.h" -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) +#define mainCHECK_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 6 ) + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ +#define mainCHECK_TASK_LED ( 6 ) /* The check task, as described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); void main_full( void ) { - vStartSemaphoreTasks(mainSEM_TEST_PRIORITY); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); vStartTaskNotifyTask(); vStartRegTestTasks(); vStartRecursiveMutexTasks(); /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ + * the top of this file. */ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); vTaskStartScheduler(); - + /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } void init_full( void ) @@ -50,52 +52,52 @@ void init_full( void ) vParTestInitialise(); } -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -TickType_t xLastExecutionTime; -unsigned long ulErrorFound = pdFALSE; + TickType_t xLastExecutionTime; + unsigned long ulErrorFound = pdFALSE; /* Just to stop compiler warnings. */ ( void ) pvParameters; /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ + * works correctly. */ xLastExecutionTime = xTaskGetTickCount(); /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration - unless an error occurred. */ - for( ;; ) + * operating without error. The onboard LED is toggled on each iteration + * unless an error occurred. */ + for( ; ; ) { /* Delay until it is time to execute again. */ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_PERIOD ); /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ + * that they are all still running, and that none have detected an error. */ if( xAreSemaphoreTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 0UL; } - + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 1UL; } - + if( xAreRegTestTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 2UL; } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) { ulErrorFound |= 1UL << 3UL; } - + if( ulErrorFound == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_minimal.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_minimal.c index bf54d4b5c0d..9969396b3ed 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_minimal.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/main_minimal.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,7 +37,7 @@ #include "regtest.h" /* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ + * tasks just use the idle priority. */ #define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) @@ -46,20 +46,20 @@ tasks just use the idle priority. */ #define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 9600 ) /* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ + * and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ #define mainCOM_TEST_LED ( 7 ) /* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ + * that all the other tasks are operating without error. If no errors are found + * the LED is toggled. If an error is found at any time the LED is never toggles + * again. */ #define mainCHECK_TASK_LED ( 6 ) /* The period between executions of the check task. */ #define mainCHECK_PERIOD ( ( TickType_t ) 1000 / portTICK_PERIOD_MS ) /* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ + * the demo application is not unexpectedly resetting. */ #define mainRESET_COUNT_ADDRESS ( 0x1400 ) /* The number of coroutines to create. */ @@ -68,7 +68,7 @@ the demo application is not unexpectedly resetting. */ /* * The task function for the "Check" task. */ -static void vErrorChecks( void *pvParameters ); +static void vErrorChecks( void * pvParameters ); /* * Checks the unique counts of other tasks to ensure they are still operational. @@ -91,16 +91,16 @@ void main_minimal( void ) vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); vStartRegTestTasks(); - + /* Create the tasks defined within this file. */ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); /* Create the co-routines that flash the LED's. */ vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ + * as 1 in portmacro.h. To use the cooperative scheduler define + * configUSE_PREEMPTION as 0. */ vTaskStartScheduler(); } @@ -109,28 +109,28 @@ void init_minimal( void ) /* Configure UART pins: PC1 Rx, PC0 Tx */ PORTC.DIR &= ~PIN0_bm; PORTC.DIR |= PIN1_bm; - + vParTestInitialise(); } -static void vErrorChecks( void *pvParameters ) +static void vErrorChecks( void * pvParameters ) { -static volatile unsigned long ulDummyVariable = 3UL; + static volatile unsigned long ulDummyVariable = 3UL; /* The parameters are not used. */ ( void ) pvParameters; /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) + * operating without error. */ + for( ; ; ) { vTaskDelay( mainCHECK_PERIOD ); /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ + * integer tasks get some exercise. The result here is not important - + * see the demo application documentation for more info. */ ulDummyVariable *= 3; - + prvCheckOtherTasksAreStillRunning(); } } @@ -138,7 +138,7 @@ static volatile unsigned long ulDummyVariable = 3UL; static void prvCheckOtherTasksAreStillRunning( void ) { -static portBASE_TYPE xErrorHasOccurred = pdFALSE; + static portBASE_TYPE xErrorHasOccurred = pdFALSE; if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) { @@ -159,11 +159,11 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; { xErrorHasOccurred = pdTRUE; } - + if( xErrorHasOccurred == pdFALSE ) { /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ + * using console IO. */ vParTestToggleLED( mainCHECK_TASK_LED ); } } @@ -171,7 +171,7 @@ static portBASE_TYPE xErrorHasOccurred = pdFALSE; static void prvIncrementResetCount( void ) { -unsigned char ucResetCount; + unsigned char ucResetCount; eeprom_read_block( &ucResetCount, ( void * ) mainRESET_COUNT_ADDRESS, sizeof( ucResetCount ) ); ucResetCount++; diff --git a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/serial/serial.c b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/serial/serial.c index e981bb92d24..af7f428598a 100644 --- a/FreeRTOS/Demo/AVR_Dx_MPLAB.X/serial/serial.c +++ b/FreeRTOS/Demo/AVR_Dx_MPLAB.X/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c index 5890eb98a19..ecb52e5193b 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h index 48f59c00be2..b5ac001b2c6 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c index de84f5623ac..7d3b23bd0d6 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c index c4302b01a42..8e30980d2d5 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c index 80ffe6bc09b..550bebbb1b6 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c index 6304d1cab4c..193623920e7 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOSConfig.h index 2b94c6aa689..db628e4ddbc 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOS_tick_config.c index a3249b49d73..ccee8ccb48a 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.c index 19501f59f51..7f67e372b98 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/main_full.c index 9e3952e17b1..53c02bdc8cd 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/LEDs.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/LEDs.c index 6739572e86c..cc7d928629f 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/LEDs.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/LEDs.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/blinky_demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/blinky_demo/main_blinky.c index 2da0eee0b5e..597eebc6b6d 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/main.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/main.c index d60af191c46..6ac05433e27 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -82,8 +82,8 @@ #include "chip.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -97,182 +97,186 @@ static void prvSetupHardware( void ); * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port -layer. */ + * layer. */ void vApplicationIRQHandler( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Disable watchdog */ - wdt_disable( ); + /* Disable watchdog */ + wdt_disable(); - /* Set protect mode in the AIC for easier debugging. */ - AIC->AIC_DCR |= AIC_DCR_PROT; + /* Set protect mode in the AIC for easier debugging. */ + AIC->AIC_DCR |= AIC_DCR_PROT; - /* Configure ports used by LEDs. */ - vParTestInitialise(); + /* Configure ports used by LEDs. */ + vParTestInitialise(); - #if defined (ddram) - MMU_Initialize( ( uint32_t * ) 0x30C000 ); - CP15_EnableMMU(); - CP15_EnableDcache(); - CP15_EnableIcache(); - #endif + #if defined( ddram ) + MMU_Initialize( ( uint32_t * ) 0x30C000 ); + CP15_EnableMMU(); + CP15_EnableDcache(); + CP15_EnableIcache(); + #endif } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ -void vAssertCalled( const char * pcFile, unsigned long ulLine ) +void vAssertCalled( const char * pcFile, + unsigned long ulLine ) { -volatile unsigned long ul = 0; - - ( void ) pcFile; - ( void ) ulLine; - - taskENTER_CRITICAL(); - { - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - portNOP(); - } - } - taskEXIT_CRITICAL(); + volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + * function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - } - #endif + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + } + #endif /* if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 */ } /*-----------------------------------------------------------*/ /* The function called by the RTOS port layer after it has managed interrupt -entry. */ + * entry. */ void vApplicationIRQHandler( void ) { -typedef void (*ISRFunction_t)( void ); -ISRFunction_t pxISRFunction; -volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS; + typedef void (* ISRFunction_t)( void ); + ISRFunction_t pxISRFunction; + volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS; - /* Obtain the address of the interrupt handler from the AIR. */ - pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR; + /* Obtain the address of the interrupt handler from the AIR. */ + pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR; - /* Write back to the SAMA5's interrupt controller's IVR register in case the - CPU is in protect mode. If the interrupt controller is not in protect mode - then this write is not necessary. */ - *pulAIC_IVR = ( uint32_t ) pxISRFunction; + /* Write back to the SAMA5's interrupt controller's IVR register in case the + * CPU is in protect mode. If the interrupt controller is not in protect mode + * then this write is not necessary. */ + *pulAIC_IVR = ( uint32_t ) pxISRFunction; - /* Ensure the write takes before re-enabling interrupts. */ - __DSB(); - __ISB(); - __enable_irq(); + /* Ensure the write takes before re-enabling interrupts. */ + __DSB(); + __ISB(); + __enable_irq(); - /* Call the installed ISR. */ - pxISRFunction(); + /* Call the installed ISR. */ + pxISRFunction(); } /* Keep the linker quiet. */ -size_t __write(int, const unsigned char *, size_t); -size_t __write(int f, const unsigned char *p, size_t s) +size_t __write( int, + const unsigned char *, + size_t ); +size_t __write( int f, + const unsigned char * p, + size_t s ) { - (void) f; - (void) p; - (void) s; - return 0; + ( void ) f; + ( void ) p; + ( void ) s; + return 0; } - - - diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c index f083c3c7f2d..d35023d3a9a 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h index 6d5e0a0b2ad..c577dff1066 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c index 1b6e366aa14..e33c581aea8 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c index 5b28777546d..2090a977758 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c index 78e9c37db8f..92a00a68dae 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c index 7b54889ff20..77874fa1d83 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/blinky_demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/blinky_demo/main_blinky.c index d286160518b..3a8342d836c 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c index 60a7b55d011..fabec33cc5b 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,8 +57,8 @@ #include "chip.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -72,42 +72,43 @@ static void prvSetupHardware( void ); * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port -layer. */ + * layer. */ void vApplicationIRQHandler( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ @@ -116,127 +117,127 @@ static void prvSetupHardware( void ) /* Disable watchdog */ WDT_Disable( WDT ); - /* Set protect mode in the AIC for easier debugging. */ - AIC->AIC_DCR |= AIC_DCR_PROT; + /* Set protect mode in the AIC for easier debugging. */ + AIC->AIC_DCR |= AIC_DCR_PROT; - /* Configure ports used by LEDs. */ - vParTestInitialise(); + /* Configure ports used by LEDs. */ + vParTestInitialise(); - #if defined (ddram) - MMU_Initialize( ( uint32_t * ) 0x30C000 ); - CP15_EnableMMU(); - CP15_EnableDcache(); - CP15_EnableIcache(); - #endif + #if defined( ddram ) + MMU_Initialize( ( uint32_t * ) 0x30C000 ); + CP15_EnableMMU(); + CP15_EnableDcache(); + CP15_EnableIcache(); + #endif } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ -void vAssertCalled( const char * pcFile, unsigned long ulLine ) +void vAssertCalled( const char * pcFile, + unsigned long ulLine ) { -volatile unsigned long ul = 0; - - ( void ) pcFile; - ( void ) ulLine; - - taskENTER_CRITICAL(); - { - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - portNOP(); - } - } - taskEXIT_CRITICAL(); + volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + * function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - } - #endif + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + } + #endif /* if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 */ } /*-----------------------------------------------------------*/ /* The function called by the RTOS port layer after it has managed interrupt -entry. */ + * entry. */ void vApplicationIRQHandler( void ) { -typedef void (*ISRFunction_t)( void ); -ISRFunction_t pxISRFunction; -volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS; + typedef void (* ISRFunction_t)( void ); + ISRFunction_t pxISRFunction; + volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS; - /* Obtain the address of the interrupt handler from the AIR. */ - pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR; + /* Obtain the address of the interrupt handler from the AIR. */ + pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR; - /* Write back to the SAMA5's interrupt controller's IVR register in case the - CPU is in protect mode. If the interrupt controller is not in protect mode - then this write is not necessary. */ - *pulAIC_IVR = ( uint32_t ) pxISRFunction; + /* Write back to the SAMA5's interrupt controller's IVR register in case the + * CPU is in protect mode. If the interrupt controller is not in protect mode + * then this write is not necessary. */ + *pulAIC_IVR = ( uint32_t ) pxISRFunction; - /* Ensure the write takes before re-enabling interrupts. */ - __DSB(); - __ISB(); + /* Ensure the write takes before re-enabling interrupts. */ + __DSB(); + __ISB(); __enable_irq(); - /* Call the installed ISR. */ - pxISRFunction(); + /* Call the installed ISR. */ + pxISRFunction(); } - - diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Blinky_Demo/main_blinky.c index d286160518b..3a8342d836c 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/CDCCommandConsole.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/CDCCommandConsole.c index 9aec09aa131..6e6e46a5916 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/CDCCommandConsole.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/CDCCommandConsole.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOSConfig.h index c50a3c4645e..7d578e38ee8 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOS_tick_config.c index 8dfa832ed06..f3807c8b5e7 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.c index cea2ced4b60..ac708723204 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/main_full.c index 78aa7ccb414..b27306143e5 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/LEDs.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/LEDs.c index 7b54889ff20..77874fa1d83 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/LEDs.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/LEDs.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/main.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/main.c index 97d3ed999fd..5dc48a24cb1 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,8 +57,8 @@ #include "chip.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -71,43 +71,44 @@ static void prvSetupHardware( void ); * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ -#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - extern void main_blinky( void ); +#if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port -layer. */ + * layer. */ void vApplicationIRQHandler( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ @@ -116,129 +117,130 @@ static void prvSetupHardware( void ) /* Disable watchdog */ WDT_Disable( WDT ); - /* Set protect mode in the AIC for easier debugging. THIS IS COMMENTED OUT - AS IT RESULTS IN SPURIOUS INTERRUPTS. - AIC->AIC_DCR |= AIC_DCR_PROT; */ - - /* Configure ports used by LEDs. */ - vParTestInitialise(); - - #if defined (ddram) - { - MMU_Initialize( ( uint32_t * ) 0x20C000 ); - CP15_EnableMMU(); - CP15_EnableDcache(); - CP15_EnableIcache(); - } - #endif + /* Set protect mode in the AIC for easier debugging. THIS IS COMMENTED OUT + * AS IT RESULTS IN SPURIOUS INTERRUPTS. + * AIC->AIC_DCR |= AIC_DCR_PROT; */ + + /* Configure ports used by LEDs. */ + vParTestInitialise(); + + #if defined( ddram ) + { + MMU_Initialize( ( uint32_t * ) 0x20C000 ); + CP15_EnableMMU(); + CP15_EnableDcache(); + CP15_EnableIcache(); + } + #endif } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ -void vAssertCalled( const char * pcFile, unsigned long ulLine ) +void vAssertCalled( const char * pcFile, + unsigned long ulLine ) { -volatile unsigned long ul = 0; - - ( void ) pcFile; - ( void ) ulLine; - - taskENTER_CRITICAL(); - { - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - portNOP(); - } - } - taskEXIT_CRITICAL(); + volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + * function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - } - #endif + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + } + #endif /* if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 */ } /*-----------------------------------------------------------*/ /* The function called by the RTOS port layer after it has managed interrupt -entry. */ + * entry. */ void vApplicationIRQHandler( void ) { -typedef void (*ISRFunction_t)( void ); -ISRFunction_t pxISRFunction; -volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS; + typedef void (* ISRFunction_t)( void ); + ISRFunction_t pxISRFunction; + volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS; - /* Obtain the address of the interrupt handler from the AIR. */ - pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR; + /* Obtain the address of the interrupt handler from the AIR. */ + pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR; - /* Write back to the SAMA5's interrupt controller's IVR register in case the - CPU is in protect mode. If the interrupt controller is not in protect mode - then this write is not necessary. */ - *pulAIC_IVR = ( uint32_t ) pxISRFunction; + /* Write back to the SAMA5's interrupt controller's IVR register in case the + * CPU is in protect mode. If the interrupt controller is not in protect mode + * then this write is not necessary. */ + *pulAIC_IVR = ( uint32_t ) pxISRFunction; - /* Ensure the write takes before re-enabling interrupts. */ - __DSB(); - __ISB(); + /* Ensure the write takes before re-enabling interrupts. */ + __DSB(); + __ISB(); __enable_irq(); - /* Call the installed ISR. */ - pxISRFunction(); + /* Call the installed ISR. */ + pxISRFunction(); } - diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h index b3565b1f38d..14a27e82c31 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/LEDs.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/LEDs.c index ff40ed78cce..ba0adf521a2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/LEDs.c +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/LEDs.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c index 28bcbaec492..ee8892aa38f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -75,7 +75,7 @@ * When mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0 the comprehensive test * and demo application will be run. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -89,240 +89,250 @@ static void prvSetupHardware( void ); * mainSELECTED_APPLICATION definition. */ #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ /* configAPPLICATION_ALLOCATED_HEAP is set to 1 in FreeRTOSConfig.h so the -application can define the array used as the FreeRTOS heap. This is done so the -heap can be forced into fast internal RAM - useful because the stacks used by -the tasks come from this space. */ -uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] __attribute__ ( ( section( ".oc_ram" ) ) ); + * application can define the array used as the FreeRTOS heap. This is done so the + * heap can be forced into fast internal RAM - useful because the stacks used by + * the tasks come from this space. */ +uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] __attribute__( ( section( ".oc_ram" ) ) ); /* FreeRTOS uses its own interrupt handler code. This code cannot use the array -of handlers defined by the Altera drivers because the array is declared static, -and so not accessible outside of the dirver's source file. Instead declare an -array for use by the FreeRTOS handler. See: -http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html. */ + * of handlers defined by the Altera drivers because the array is declared static, + * and so not accessible outside of the dirver's source file. Instead declare an + * array for use by the FreeRTOS handler. See: + * http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html. */ static INT_DISPATCH_t xISRHandlers[ ALT_INT_PROVISION_INT_COUNT ]; /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainSELECTED_APPLICATION setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - /* Don't expect to reach here. */ - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainSELECTED_APPLICATION setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + /* Don't expect to reach here. */ + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -extern uint8_t __cs3_interrupt_vector; -uint32_t ulSCTLR, ulVectorTable = ( uint32_t ) &__cs3_interrupt_vector; -const uint32_t ulVBit = 13U; - - alt_int_global_init(); - alt_int_cpu_binary_point_set( 0 ); - - /* Clear SCTLR.V for low vectors and map the vector table to the beginning - of the code. */ - __asm( "MRC p15, 0, %0, c1, c0, 0" : "=r" ( ulSCTLR ) ); - ulSCTLR &= ~( 1 << ulVBit ); - __asm( "MCR p15, 0, %0, c1, c0, 0" : : "r" ( ulSCTLR ) ); - __asm( "MCR p15, 0, %0, c12, c0, 0" : : "r" ( ulVectorTable ) ); - - cache_init(); - mmu_init(); - - /* GPIO for LEDs. ParTest is a historic name which used to stand for - parallel port test. */ - vParTestInitialise(); + extern uint8_t __cs3_interrupt_vector; + uint32_t ulSCTLR, ulVectorTable = ( uint32_t ) &__cs3_interrupt_vector; + const uint32_t ulVBit = 13U; + + alt_int_global_init(); + alt_int_cpu_binary_point_set( 0 ); + + /* Clear SCTLR.V for low vectors and map the vector table to the beginning + * of the code. */ + __asm( "MRC p15, 0, %0, c1, c0, 0" : "=r" ( ulSCTLR ) ); + ulSCTLR &= ~( 1 << ulVBit ); + __asm( "MCR p15, 0, %0, c1, c0, 0" : : "r" ( ulSCTLR ) ); + __asm( "MCR p15, 0, %0, c12, c0, 0" : : "r" ( ulVectorTable ) ); + + cache_init(); + mmu_init(); + + /* GPIO for LEDs. ParTest is a historic name which used to stand for + * parallel port test. */ + vParTestInitialise(); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ -void vAssertCalled( const char * pcFile, unsigned long ulLine ) +void vAssertCalled( const char * pcFile, + unsigned long ulLine ) { -volatile unsigned long ul = 0; - - ( void ) pcFile; - ( void ) ulLine; - - taskENTER_CRITICAL(); - { - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - portNOP(); - } - } - taskEXIT_CRITICAL(); + volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + * function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - - /* Call the periodic test that uses mutexes form an interrupt. */ - vInterruptSemaphorePeriodicTest(); - } - #endif + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Call the periodic test that uses mutexes form an interrupt. */ + vInterruptSemaphorePeriodicTest(); + } + #endif /* if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) */ } /*-----------------------------------------------------------*/ void vConfigureTickInterrupt( void ) { -alt_freq_t ulTempFrequency; -const alt_freq_t ulMicroSecondsPerSecond = 1000000UL; -void FreeRTOS_Tick_Handler( void ); + alt_freq_t ulTempFrequency; + const alt_freq_t ulMicroSecondsPerSecond = 1000000UL; + + void FreeRTOS_Tick_Handler( void ); - /* Interrupts are disabled when this function is called. */ + /* Interrupts are disabled when this function is called. */ - /* Initialise the general purpose timer modules. */ - alt_gpt_all_tmr_init(); + /* Initialise the general purpose timer modules. */ + alt_gpt_all_tmr_init(); - /* ALT_CLK_MPU_PERIPH = mpu_periph_clk */ - alt_clk_freq_get( ALT_CLK_MPU_PERIPH, &ulTempFrequency ); + /* ALT_CLK_MPU_PERIPH = mpu_periph_clk */ + alt_clk_freq_get( ALT_CLK_MPU_PERIPH, &ulTempFrequency ); - /* Use the local private timer. */ - alt_gpt_counter_set( ALT_GPT_CPU_PRIVATE_TMR, ulTempFrequency / configTICK_RATE_HZ ); + /* Use the local private timer. */ + alt_gpt_counter_set( ALT_GPT_CPU_PRIVATE_TMR, ulTempFrequency / configTICK_RATE_HZ ); - /* Sanity check. */ - configASSERT( alt_gpt_time_microsecs_get( ALT_GPT_CPU_PRIVATE_TMR ) == ( ulMicroSecondsPerSecond / configTICK_RATE_HZ ) ); + /* Sanity check. */ + configASSERT( alt_gpt_time_microsecs_get( ALT_GPT_CPU_PRIVATE_TMR ) == ( ulMicroSecondsPerSecond / configTICK_RATE_HZ ) ); - /* Set to periodic mode. */ - alt_gpt_mode_set( ALT_GPT_CPU_PRIVATE_TMR, ALT_GPT_RESTART_MODE_PERIODIC ); + /* Set to periodic mode. */ + alt_gpt_mode_set( ALT_GPT_CPU_PRIVATE_TMR, ALT_GPT_RESTART_MODE_PERIODIC ); - /* The timer can be started here as interrupts are disabled. */ - alt_gpt_tmr_start( ALT_GPT_CPU_PRIVATE_TMR ); + /* The timer can be started here as interrupts are disabled. */ + alt_gpt_tmr_start( ALT_GPT_CPU_PRIVATE_TMR ); - /* Register the standard FreeRTOS Cortex-A tick handler as the timer's - interrupt handler. The handler clears the interrupt using the - configCLEAR_TICK_INTERRUPT() macro, which is defined in FreeRTOSConfig.h. */ - vRegisterIRQHandler( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE, ( alt_int_callback_t ) FreeRTOS_Tick_Handler, NULL ); + /* Register the standard FreeRTOS Cortex-A tick handler as the timer's + * interrupt handler. The handler clears the interrupt using the + * configCLEAR_TICK_INTERRUPT() macro, which is defined in FreeRTOSConfig.h. */ + vRegisterIRQHandler( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE, ( alt_int_callback_t ) FreeRTOS_Tick_Handler, NULL ); - /* This tick interrupt must run at the lowest priority. */ - alt_int_dist_priority_set( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + /* This tick interrupt must run at the lowest priority. */ + alt_int_dist_priority_set( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - /* Ensure the interrupt is forwarded to the CPU. */ + /* Ensure the interrupt is forwarded to the CPU. */ alt_int_dist_enable( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE ); /* Finally, enable the interrupt. */ - alt_gpt_int_clear_pending( ALT_GPT_CPU_PRIVATE_TMR ); - alt_gpt_int_enable( ALT_GPT_CPU_PRIVATE_TMR ); - + alt_gpt_int_clear_pending( ALT_GPT_CPU_PRIVATE_TMR ); + alt_gpt_int_enable( ALT_GPT_CPU_PRIVATE_TMR ); } /*-----------------------------------------------------------*/ -void vRegisterIRQHandler( uint32_t ulID, alt_int_callback_t pxHandlerFunction, void *pvContext ) +void vRegisterIRQHandler( uint32_t ulID, + alt_int_callback_t pxHandlerFunction, + void * pvContext ) { - if( ulID < ALT_INT_PROVISION_INT_COUNT ) - { - xISRHandlers[ ulID ].pxISR = pxHandlerFunction; - xISRHandlers[ ulID ].pvContext = pvContext; - } + if( ulID < ALT_INT_PROVISION_INT_COUNT ) + { + xISRHandlers[ ulID ].pxISR = pxHandlerFunction; + xISRHandlers[ ulID ].pvContext = pvContext; + } } /*-----------------------------------------------------------*/ void vApplicationIRQHandler( uint32_t ulICCIAR ) { -uint32_t ulInterruptID; -void *pvContext; -alt_int_callback_t pxISR; - - /* Re-enable interrupts. */ - __asm ( "cpsie i" ); - - /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value - with 0x3FF. */ - ulInterruptID = ulICCIAR & 0x3FFUL; - - if( ulInterruptID < ALT_INT_PROVISION_INT_COUNT ) - { - /* Call the function installed in the array of installed handler - functions. */ - pxISR = xISRHandlers[ ulInterruptID ].pxISR; - pvContext = xISRHandlers[ ulInterruptID ].pvContext; - pxISR( ulICCIAR, pvContext ); - } + uint32_t ulInterruptID; + void * pvContext; + alt_int_callback_t pxISR; + + /* Re-enable interrupts. */ + __asm( "cpsie i" ); + + /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value + * with 0x3FF. */ + ulInterruptID = ulICCIAR & 0x3FFUL; + + if( ulInterruptID < ALT_INT_PROVISION_INT_COUNT ) + { + /* Call the function installed in the array of installed handler + * functions. */ + pxISR = xISRHandlers[ ulInterruptID ].pxISR; + pvContext = xISRHandlers[ ulInterruptID ].pvContext; + pxISR( ulICCIAR, pvContext ); + } } - diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_blinky.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_blinky.c index 6296a61f02b..7519cbf3917 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -26,8 +26,8 @@ /****************************************************************************** * NOTE 1: This project provides two demo applications. A simple blinky - * style project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY * in main.c. This file implements the simply blinky style version. * @@ -70,28 +70,28 @@ #include "partest.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* The LED toggled by the Rx task. */ -#define mainTASK_LED ( 0 ) +#define mainTASK_LED ( 0 ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /*-----------------------------------------------------------*/ @@ -102,86 +102,87 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == ulExpectedValue ) - { - vParTestToggleLED( mainTASK_LED ); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + vParTestToggleLED( mainTASK_LED ); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_full.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_full.c index 03c522d9e0d..d6eeaa01046 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -92,42 +92,42 @@ #include "IntSemTest.h" /* Priorities for the demo application tasks. */ -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) -#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) /* The priority used by the UART command console task. This is very basic and -uses the Altera polling UART driver - so *must* run at the idle priority. */ -#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +* uses the Altera polling UART driver - so *must* run at the idle priority. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* The LED used by the check task. */ -#define mainCHECK_LED ( 0 ) +#define mainCHECK_LED ( 0 ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The period of the check task, in ms, provided no errors have been reported by -any of the standard demo tasks. ms are converted to the equivalent in ticks -using the pdMS_TO_TICKS() macro constant. */ -#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) + * any of the standard demo tasks. ms are converted to the equivalent in ticks + * using the pdMS_TO_TICKS() macro constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) /* The period of the check task, in ms, if an error has been reported in one of -the standard demo tasks. ms are converted to the equivalent in ticks using the -pdMS_TO_TICKS() macro. */ -#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) + * the standard demo tasks. ms are converted to the equivalent in ticks using the + * pdMS_TO_TICKS() macro. */ +#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) /* Parameters that are passed into the register check tasks solely for the -purpose of ensuring parameters are passed into tasks correctly. */ -#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) -#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) /* The base period used by the timer test tasks. */ -#define mainTIMER_TEST_PERIOD ( 50 ) +#define mainTIMER_TEST_PERIOD ( 50 ) /*-----------------------------------------------------------*/ @@ -135,7 +135,7 @@ purpose of ensuring parameters are passed into tasks correctly. */ /* * The check task, as described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); /* * Register check tasks, and the tasks used to write over and check the contents @@ -144,9 +144,9 @@ static void prvCheckTask( void *pvParameters ); * entry points are kept in the C file for the convenience of checking the task * parameter. */ -static void prvRegTestTaskEntry1( void *pvParameters ); +static void prvRegTestTaskEntry1( void * pvParameters ); extern void vRegTest1Implementation( void ); -static void prvRegTestTaskEntry2( void *pvParameters ); +static void prvRegTestTaskEntry2( void * pvParameters ); extern void vRegTest2Implementation( void ); /* @@ -158,285 +158,284 @@ extern void vRegisterSampleCLICommands( void ); /* * The task that manages the FreeRTOS+CLI input and output. */ -extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); +extern void vUARTCommandConsoleStart( uint16_t usStackSize, + UBaseType_t uxPriority ); /* * A high priority task that does nothing other than execute at a pseudo random * time to ensure the other test tasks don't just execute in a repeating * pattern. */ -static void prvPseudoRandomiser( void *pvParameters ); +static void prvPseudoRandomiser( void * pvParameters ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check task. If the variables keep incrementing, -then the register check tasks have not discovered any errors. If a variable -stops incrementing, then an error has been found. */ + * register check tasks to the check task. If the variables keep incrementing, + * then the register check tasks have not discovered any errors. If a variable + * stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { - /* Start all the other standard demo/test tasks. They have no particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); - vStartEventGroupTasks(); - vStartInterruptSemaphoreTasks(); - - /* Start the tasks that implements the command console on the UART, as - described above. */ - vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); - - /* Register the standard CLI commands. */ - vRegisterSampleCLICommands(); - - /* Create the register check tasks, as described at the top of this file */ - xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* Create the task that just adds a little random behaviour. */ - xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - - /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* The set of tasks created by the following function call have to be - created last as they keep account of the number of tasks they expect to see - running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); + /* Start all the other standard demo/test tasks. They have no particular + * functionality, but do demonstrate how to use the FreeRTOS API and test the + * kernel port. */ + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartInterruptSemaphoreTasks(); + + /* Start the tasks that implements the command console on the UART, as + * described above. */ + vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); + + /* Register the standard CLI commands. */ + vRegisterSampleCLICommands(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + * the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + * created last as they keep account of the number of tasks they expect to see + * running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was either insufficient FreeRTOS heap memory available for the idle + * and/or timer tasks to be created, or vTaskStartScheduler() was called from + * User mode. See the memory management section on the FreeRTOS web site for + * more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + * mode from which main() is called is set in the C start up code and must be + * a privileged mode (not user mode). */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; -TickType_t xLastExecutionTime; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration. - If an error is detected then the delay period is decreased from - mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the - effect of increasing the rate at which the onboard LED toggles, and in so - doing gives visual feedback of the system status. */ - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 1; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 2; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 3; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 4; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 5; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 6; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 7; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 8; - } - - if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) - { - ulErrorFound = 1 << 9; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1 << 10; - } - - if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) - { - ulErrorFound = 1 << 11; - } - - if( xAreEventGroupTasksStillRunning() != pdPASS ) - { - ulErrorFound = 1 << 12; - } - - if( xAreInterruptSemaphoreTasksStillRunning() != pdPASS ) - { - ulErrorFound = 1 << 13; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = 1 << 14; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = 1 << 15; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then - everything is ok. A faster toggle indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - if( ulErrorFound != pdFALSE ) - { - /* An error has been detected in one of the tasks - flash the LED - at a higher frequency to give visible feedback that something has - gone wrong (it might just be that the loop back connector required - by the comtest tasks has not been fitted). */ - xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; - } - } + TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; + TickType_t xLastExecutionTime; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + * operating without error. The onboard LED is toggled on each iteration. + * If an error is detected then the delay period is decreased from + * mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + * effect of increasing the rate at which the onboard LED toggles, and in so + * doing gives visual feedback of the system status. */ + for( ; ; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none have detected an error. */ + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 1; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 2; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 3; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 4; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 5; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 6; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 7; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 8; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound = 1 << 9; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1 << 10; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound = 1 << 11; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1 << 12; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1 << 13; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = 1 << 14; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = 1 << 15; + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + * everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + * at a higher frequency to give visible feedback that something has + * gone wrong (it might just be that the loop back connector required + * by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + } } /*-----------------------------------------------------------*/ -static void prvRegTestTaskEntry1( void *pvParameters ) +static void prvRegTestTaskEntry1( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) - { - /* The reg test task also tests the floating point registers. Tasks - that use the floating point unit must call vPortTaskUsesFPU() before - any floating point instructions are executed. */ - vPortTaskUsesFPU(); - - /* Start the part of the test that is written in assembler. */ - vRegTest1Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + * that use the floating point unit must call vPortTaskUsesFPU() before + * any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -static void prvRegTestTaskEntry2( void *pvParameters ) +static void prvRegTestTaskEntry2( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) - { - /* The reg test task also tests the floating point registers. Tasks - that use the floating point unit must call vPortTaskUsesFPU() before - any floating point instructions are executed. */ - vPortTaskUsesFPU(); - - /* Start the part of the test that is written in assembler. */ - vRegTest2Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + * that use the floating point unit must call vPortTaskUsesFPU() before + * any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -static void prvPseudoRandomiser( void *pvParameters ) +static void prvPseudoRandomiser( void * pvParameters ) { -const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); -volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; - - - /* This task does nothing other than ensure there is a little bit of - disruption in the scheduling pattern of the other tasks. Normally this is - done by generating interrupts at pseudo random times. */ - for( ;; ) - { - ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; - ulValue = ( ulNextRand >> 16UL ) & 0xffUL; - - if( ulValue < ulMinDelay ) - { - ulValue = ulMinDelay; - } - - vTaskDelay( ulValue ); - - while( ulValue > 0 ) - { - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - - ulValue--; - } - } + const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); + volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + + /* This task does nothing other than ensure there is a little bit of + * disruption in the scheduling pattern of the other tasks. Normally this is + * done by generating interrupts at pseudo random times. */ + for( ; ; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + + ulValue--; + } + } } - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/serial.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/serial.c index 143f15d1192..f26fc67060b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/serial.c +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c index 6ac9446f534..3da0782cc79 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h index 053bf406bb8..ee95b54ae42 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c index 2ca9e73edac..b4f6d764a7c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c index e2d3350aa29..939af919c2e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c index a92578dd0a6..2a3bfbee7a7 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c index 62792513dcd..4f631097f01 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c index a31aa57367b..770de736ac8 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c index b7adfe51b42..7bb2ddf9b57 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c index 00effb7fab5..d201bcbf210 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h index 0c7e833879d..678e49232ac 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c index cdd4399f2f0..b72080b6f4f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c index 17bf5454e43..9e02c4637e2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOSConfig.h index d10defcbf45..b07f4057e60 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOS_tick_config.c index 2ca9e73edac..b4f6d764a7c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/ParTest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/ParTest.c index 047a698f0ec..df1cbc46d68 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/blinky_demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/blinky_demo/main_blinky.c index 1dabbe3ef73..e2150b37ef4 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.c index 2185476a454..d61a038b020 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/main_full.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/main_full.c index 4b8a0a8f17d..31a1c4c897a 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/serial.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/serial.c index 62792513dcd..4f631097f01 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/serial.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/full_demo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/main.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/main.c index 16d7036ccba..9de4c276d72 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/main.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/zc702 Configuration QEMU.launch b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/zc702 Configuration QEMU.launch index 3b8bdebbbd9..77ba94a495f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/zc702 Configuration QEMU.launch +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702_Vitis_QEMU/RTOSDemo/zc702 Configuration QEMU.launch @@ -29,7 +29,7 @@ - + diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h index e2375916d90..13945fa4c24 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c index b85c654aa3b..f9253e0dca0 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h index 4c17ce9baa7..2fbe9293ccd 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/main.c b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/main.c index 93799d9bc03..b3a2a4aa44e 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -83,29 +83,29 @@ /*-----------------------------------------------------------*/ /* The time between cycles of the 'check' functionality (defined within the -tick hook). */ -#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) + * tick hook). */ +#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) /* The LCD task uses the sprintf function so requires a little more stack too. */ -#define mainLCD_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) +#define mainLCD_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) /* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* The maximum number of message that can be waiting for display at any one -time. */ -#define mainLCD_QUEUE_SIZE ( 3 ) + * time. */ +#define mainLCD_QUEUE_SIZE ( 3 ) /* Constants used by the comtest tasks. There isn't a spare LED so an invalid -LED is specified. */ -#define mainBAUD_RATE ( 115200 ) -#define mainCOM_TEST_LED ( 10 ) + * LED is specified. */ +#define mainBAUD_RATE ( 115200 ) +#define mainCOM_TEST_LED ( 10 ) /*-----------------------------------------------------------*/ @@ -118,13 +118,14 @@ static void prvSetupHardware( void ); * The LCD gatekeeper task. Tasks wishing to write to the LCD do not access * the LCD directly, but instead send the message to the LCD gatekeeper task. */ -static void prvLCDTask( void *pvParameters ); +static void prvLCDTask( void * pvParameters ); /* * Hook functions that can get called by the kernel. The 'check' functionality * is implemented within the tick hook. */ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); /* * The tick hook function as described in the comments at the top of this file. @@ -144,149 +145,154 @@ static QueueHandle_t xLCDQueue; int main( void ) { - /* Prepare the hardware. */ - prvSetupHardware(); + /* Prepare the hardware. */ + prvSetupHardware(); - /* Create the queue used by the LCD task. Messages for display on the LCD - are received via this queue. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_SIZE, sizeof( xLCDMessage ) ); + /* Create the queue used by the LCD task. Messages for display on the LCD + * are received via this queue. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_SIZE, sizeof( xLCDMessage ) ); - /* Start the standard demo tasks. These do nothing other than test the - port and provide some APU usage examples. */ + /* Start the standard demo tasks. These do nothing other than test the + * port and provide some APU usage examples. */ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartQueuePeekTasks(); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED ); + vStartRecursiveMutexTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartQueuePeekTasks(); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED ); - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( prvLCDTask, "LCD", mainLCD_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( prvLCDTask, "LCD", mainLCD_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - /* Start the scheduler. */ - vTaskStartScheduler(); + /* Start the scheduler. */ + vTaskStartScheduler(); /* Will only get here if there was insufficient memory to create the idle - task. */ - return 0; + * task. */ + return 0; } /*-----------------------------------------------------------*/ void prvSetupHardware( void ) { - /* Initialise the port used for the LED outputs. */ - vParTestInitialise(); + /* Initialise the port used for the LED outputs. */ + vParTestInitialise(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { -static xLCDMessage xMessage = { "PASS" }; -static unsigned long ulTicksSinceLastDisplay = 0; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* Called from every tick interrupt. Have enough ticks passed to make it - time to perform our health status check again? */ - ulTicksSinceLastDisplay++; - if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) - { - ulTicksSinceLastDisplay = 0; - - /* Has an error been found in any task? */ - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN GEN Q"; - } - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN MATH"; - } - else if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK Q"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN POLL Q"; - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN PEEK Q"; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN REC MUTEX"; - } - else if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xMessage.pcMessage = "ERROR IN COMTEST"; - } - - /* Send the message to the LCD gatekeeper for display. */ - xHigherPriorityTaskWoken = pdFALSE; - xQueueSendFromISR( xLCDQueue, &xMessage, &xHigherPriorityTaskWoken ); - } + static xLCDMessage xMessage = { "PASS" }; + static unsigned long ulTicksSinceLastDisplay = 0; + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* Called from every tick interrupt. Have enough ticks passed to make it + * time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN REC MUTEX"; + } + else if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN COMTEST"; + } + + /* Send the message to the LCD gatekeeper for display. */ + xHigherPriorityTaskWoken = pdFALSE; + xQueueSendFromISR( xLCDQueue, &xMessage, &xHigherPriorityTaskWoken ); + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pxTask; - ( void ) pcTaskName; - - /* If the parameters have been corrupted then inspect pxCurrentTCB to - identify which task has overflowed its stack. */ - for( ;; ); + ( void ) pxTask; + ( void ) pcTaskName; + + /* If the parameters have been corrupted then inspect pxCurrentTCB to + * identify which task has overflowed its stack. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvLCDTask( void *pvParameters ) +static void prvLCDTask( void * pvParameters ) { -xLCDMessage xMessage; -unsigned long ulY = 0; -const unsigned long ulX = 5; -const unsigned long ulMaxY = 250, ulYIncrement = 22, ulWidth = 250, ulHeight = 20;; + xLCDMessage xMessage; + unsigned long ulY = 0; + const unsigned long ulX = 5; + const unsigned long ulMaxY = 250, ulYIncrement = 22, ulWidth = 250, ulHeight = 20; /* Initialize LCD. */ LCDD_Initialize(); LCDD_Start(); - LCDD_Fill( ( void * ) BOARD_LCD_BASE, COLOR_WHITE ); - LCDD_DrawString( ( void * ) BOARD_LCD_BASE, 1, ulY + 3, " www.FreeRTOS.org", COLOR_BLACK ); + LCDD_Fill( ( void * ) BOARD_LCD_BASE, COLOR_WHITE ); + LCDD_DrawString( ( void * ) BOARD_LCD_BASE, 1, ulY + 3, " www.FreeRTOS.org", COLOR_BLACK ); - for( ;; ) - { - /* Wait for a message from the check function (which is executed in - the tick hook). */ - xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ); + for( ; ; ) + { + /* Wait for a message from the check function (which is executed in + * the tick hook). */ + xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ); - /* Clear the space where the old message was. */ + /* Clear the space where the old message was. */ LCDD_DrawRectangle( ( void * ) BOARD_LCD_BASE, 0, ulY, ulWidth, ulHeight, COLOR_WHITE ); - /* Increment to the next drawing position. */ - ulY += ulYIncrement; + /* Increment to the next drawing position. */ + ulY += ulYIncrement; - /* Have the Y position moved past the end of the LCD? */ - if( ulY >= ulMaxY ) - { - ulY = 0; - } + /* Have the Y position moved past the end of the LCD? */ + if( ulY >= ulMaxY ) + { + ulY = 0; + } - /* Draw a new rectangle, in which the message will be written. */ + /* Draw a new rectangle, in which the message will be written. */ LCDD_DrawRectangle( ( void * ) BOARD_LCD_BASE, 0, ulY, ulWidth, ulHeight, COLOR_GREEN ); - /* Write the message. */ + /* Write the message. */ LCDD_DrawString( ( void * ) BOARD_LCD_BASE, ulX, ulY + 3, xMessage.pcMessage, COLOR_BLACK ); - } + } } diff --git a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c index e07c45409a6..c976ac17505 100644 --- a/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c +++ b/FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/comtest.c b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/comtest.c index c8084146fef..b57e2d94fe3 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/comtest.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/comtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h index 2c7134c8d2d..4aa2e649ca7 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/FreeRTOSConfig.h index 8de086ea862..3ea9591b625 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/ParTest.c b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/ParTest.c index 93f2f72e5f5..a8586f8113a 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main.c b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main.c index b0ef27147eb..7dffbb10eb9 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_blinky.c b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_blinky.c index a75c9f0ff99..0a1d346db0c 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_full.c b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_full.c index f07bb9e44eb..4403c98bed0 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_full.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/serial.c b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/serial.c index 4a56a7c174a..435f76a014f 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/serial.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/src/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/comtest.c b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/comtest.c index c8084146fef..b57e2d94fe3 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/comtest.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/comtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h index 2c7134c8d2d..4aa2e649ca7 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/FreeRTOSConfig.h index 8de086ea862..3ea9591b625 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/ParTest.c b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/ParTest.c index 93f2f72e5f5..a8586f8113a 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main.c b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main.c index b0ef27147eb..7dffbb10eb9 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_blinky.c b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_blinky.c index a75c9f0ff99..0a1d346db0c 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_full.c b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_full.c index f07bb9e44eb..4403c98bed0 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_full.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/serial.c b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/serial.c index b71b7a5f236..f5e0545e1cb 100644 --- a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/serial.c +++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h index 3ebda65edc5..0f41ba971c8 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.c index b5786d89339..2847ed69fb4 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.h index 45f68d036ec..4d703b80f0a 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/ParTest.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/ParTest.c index 9bc3bbeddde..35a3ee88394 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/Serial.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/Serial.c index 1e48d161169..480d5179892 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/Serial.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/Serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/TimerTest.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/TimerTest.c index e9fa6dc20a9..854f076a9bf 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/TimerTest.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/TimerTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/main.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/main.c index 41246c17e95..fb9beb573af 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/main.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_GCC/FreeRTOS_Demo.cydsn/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h index 3ebda65edc5..0f41ba971c8 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.c index b5786d89339..2847ed69fb4 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.h index 45f68d036ec..4d703b80f0a 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/ParTest.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/ParTest.c index 9bc3bbeddde..35a3ee88394 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/Serial.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/Serial.c index 1e48d161169..480d5179892 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/Serial.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/Serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/TimerTest.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/TimerTest.c index e9fa6dc20a9..854f076a9bf 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/TimerTest.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/TimerTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/main.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/main.c index 41246c17e95..fb9beb573af 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/main.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_Keil/FreeRTOS_Demo.cydsn/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h index 3ebda65edc5..0f41ba971c8 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.c index b5786d89339..2847ed69fb4 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.h index 45f68d036ec..4d703b80f0a 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/ParTest.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/ParTest.c index 9bc3bbeddde..35a3ee88394 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/Serial.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/Serial.c index 1e48d161169..480d5179892 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/Serial.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/Serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/TimerTest.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/TimerTest.c index e9fa6dc20a9..854f076a9bf 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/TimerTest.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/TimerTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/main.c b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/main.c index 41246c17e95..fb9beb573af 100644 --- a/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/main.c +++ b/FreeRTOS/Demo/CORTEX_CY8C5588_PSoC_Creator_RVDS/FreeRTOS_Demo.cydsn/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h index d70bbff55e3..3cc1fcb59eb 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/RegTest.c index e28d66f64b6..6ab001d2747 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/main_full.c index 1b0e0b92c88..2d2abd7cf86 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_BURTC.c b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_BURTC.c index f4410f9ebba..2275cb307a4 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_BURTC.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_BURTC.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTC.c b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTC.c index 7e68fa77c93..fbd277f1b32 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTC.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTC.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c index 7cc9e8460af..d21fafe3d9b 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/main.c b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/main.c index da2b41a0247..90d42496b2d 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/main.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -67,167 +67,172 @@ static void prvSetupHardware( void ); * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1. * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0. */ -#if( configCREATE_LOW_POWER_DEMO != 0 ) - extern void main_low_power( void ); +#if ( configCREATE_LOW_POWER_DEMO != 0 ) + extern void main_low_power( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if configCREATE_LOW_POWER_DEMO == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* - * See the following link for instructions: - * https://www.FreeRTOS.org/EFM32-Giant-Gecko-Pearl-Gecko-tickless-RTOS-demo.html - */ - - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_LOW_POWER_DEMO setting is described at the top - of this file. */ - #if( configCREATE_LOW_POWER_DEMO != 0 ) - { - main_low_power(); - } - #else - { - main_full(); - } - #endif - - /* Should not get here. */ - return 0; + /* + * See the following link for instructions: + * https://www.FreeRTOS.org/EFM32-Giant-Gecko-Pearl-Gecko-tickless-RTOS-demo.html + */ + + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_LOW_POWER_DEMO setting is described at the top + * of this file. */ + #if ( configCREATE_LOW_POWER_DEMO != 0 ) + { + main_low_power(); + } + #else + { + main_full(); + } + #endif + + /* Should not get here. */ + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Library initialisation routines. */ - CHIP_Init(); - BSP_TraceProfilerSetup(); - SLEEP_Init( NULL, NULL ); - BSP_LedsInit(); + /* Library initialisation routines. */ + CHIP_Init(); + BSP_TraceProfilerSetup(); + SLEEP_Init( NULL, NULL ); + BSP_LedsInit(); - SLEEP_SleepBlockBegin( configENERGY_MODE ); + SLEEP_SleepBlockBegin( configENERGY_MODE ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* The full demo includes tests that run from the tick hook. */ - #if( configCREATE_LOW_POWER_DEMO == 0 ) - { - extern void vFullDemoTickHook( void ); - - /* Some of the tests and demo tasks executed by the full demo include - interaction from an interrupt - for which the tick interrupt is used - via the tick hook function. */ - vFullDemoTickHook(); - } - #endif + /* The full demo includes tests that run from the tick hook. */ + #if ( configCREATE_LOW_POWER_DEMO == 0 ) + { + extern void vFullDemoTickHook( void ); + + /* Some of the tests and demo tasks executed by the full demo include + * interaction from an interrupt - for which the tick interrupt is used + * via the tick hook function. */ + vFullDemoTickHook(); + } + #endif } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } - diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h index 9b39c760d4a..6c1996eb87c 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/RegTest.c index e4742d5c46e..9a4222de530 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/main_full.c index 1b0e0b92c88..2d2abd7cf86 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTCC.c b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTCC.c index 39f0eb0d4f2..fb2eeed24b2 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTCC.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/low_power_tick_management_RTCC.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c index 7cc9e8460af..d21fafe3d9b 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/Low_Power_Demo/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/main.c b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/main.c index d292fa97960..67bc62f00e7 100644 --- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/main.c +++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -67,177 +67,183 @@ static void prvSetupHardware( void ); * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1. * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0. */ -#if( configCREATE_LOW_POWER_DEMO != 0 ) - extern void main_low_power( void ); +#if ( configCREATE_LOW_POWER_DEMO != 0 ) + extern void main_low_power( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if configCREATE_LOW_POWER_DEMO == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* - * See the following link for instructions: - * https://www.FreeRTOS.org/EFM32-Giant-Gecko-Pearl-Gecko-tickless-RTOS-demo.html - */ - - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_LOW_POWER_DEMO setting is described at the top - of this file. */ - #if( configCREATE_LOW_POWER_DEMO != 0 ) - { - main_low_power(); - } - #else - { - main_full(); - } - #endif - - /* Should not get here. */ - return 0; + /* + * See the following link for instructions: + * https://www.FreeRTOS.org/EFM32-Giant-Gecko-Pearl-Gecko-tickless-RTOS-demo.html + */ + + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_LOW_POWER_DEMO setting is described at the top + * of this file. */ + #if ( configCREATE_LOW_POWER_DEMO != 0 ) + { + main_low_power(); + } + #else + { + main_full(); + } + #endif + + /* Should not get here. */ + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -EMU_DCDCInit_TypeDef xDCDInit = EMU_DCDCINIT_STK_DEFAULT; -CMU_HFXOInit_TypeDef xHFXOInit = CMU_HFXOINIT_STK_DEFAULT; + EMU_DCDCInit_TypeDef xDCDInit = EMU_DCDCINIT_STK_DEFAULT; + CMU_HFXOInit_TypeDef xHFXOInit = CMU_HFXOINIT_STK_DEFAULT; - /* Chip errata */ - CHIP_Init(); + /* Chip errata */ + CHIP_Init(); - /* Init DCDC regulator and HFXO with kit specific parameters */ - EMU_DCDCInit( &xDCDInit ); - CMU_HFXOInit( &xHFXOInit ); + /* Init DCDC regulator and HFXO with kit specific parameters */ + EMU_DCDCInit( &xDCDInit ); + CMU_HFXOInit( &xHFXOInit ); - /* Switch HFCLK to HFXO and disable HFRCO */ - CMU_ClockSelectSet( cmuClock_HF, cmuSelect_HFXO ); - CMU_OscillatorEnable( cmuOsc_HFRCO, false, false ); + /* Switch HFCLK to HFXO and disable HFRCO */ + CMU_ClockSelectSet( cmuClock_HF, cmuSelect_HFXO ); + CMU_OscillatorEnable( cmuOsc_HFRCO, false, false ); - /* Initialize LED driver. */ - BSP_LedsInit(); - BSP_LedSet( 0 ); - BSP_LedClear( 1 ); + /* Initialize LED driver. */ + BSP_LedsInit(); + BSP_LedSet( 0 ); + BSP_LedClear( 1 ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* The full demo includes tests that run from the tick hook. */ - #if( configCREATE_LOW_POWER_DEMO == 0 ) - { - extern void vFullDemoTickHook( void ); - - /* Some of the tests and demo tasks executed by the full demo include - interaction from an interrupt - for which the tick interrupt is used - via the tick hook function. */ - vFullDemoTickHook(); - } - #endif + /* The full demo includes tests that run from the tick hook. */ + #if ( configCREATE_LOW_POWER_DEMO == 0 ) + { + extern void vFullDemoTickHook( void ); + + /* Some of the tests and demo tasks executed by the full demo include + * interaction from an interrupt - for which the tick interrupt is used + * via the tick hook function. */ + vFullDemoTickHook(); + } + #endif } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h index af5a23973b8..53e2bdc88e9 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c index 6afe63bea2a..54815fdda22 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo1/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h index 61088db8a26..0383a2abc3f 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c index f51cc09f1d4..7cd8e26e799 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/Demo2/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h index f40fc8b4c6a..b0fcdfa7082 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c index d5da78b98ce..3e9d9f87067 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c index 6afe63bea2a..79095decd6b 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -24,31 +24,31 @@ * */ -/* - * This demo application creates six co-routines and two tasks (three including +/* + * This demo application creates six co-routines and two tasks (three including * the idle task). The co-routines execute as part of the idle task hook. * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. * * The 'LCD Task' rotates a string on the LCD, delaying between each character * as necessitated by the slow interface, and delaying between each string just * long enough to enable the text to be read. * * The sixth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first + * of a string to UART 0. The co-routine periodically sends the first * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. * - * A loopback connector is required to ensure that each character transmitted + * A loopback connector is required to ensure that each character transmitted * on the UART is also received on the same UART. For test purposes the UART * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and * therefore more likely to highlight any problems. * * The flash co-routines control LED's zero to four. LED five is toggled each @@ -56,12 +56,12 @@ * the string is CORRECTLY received on the UART. LED seven is latched on should * an error be detected in any task or co-routine. * - * In addition the idle task makes repetitive calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching + * In addition the idle task makes repetitive calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching * mechansim. * */ @@ -80,68 +80,68 @@ #include "DriverLib.h" /* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_PERIOD_MS ) +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_PERIOD_MS ) /* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_PERIOD_MS ) +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_PERIOD_MS ) /* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) /* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) + * task. */ +#define mainRX_QUEUE_LEN ( 5 ) -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) +/* The priority of the co-routine used to initiate the transmission of the + * string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) /* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainTX_CO_ROUTINE_INDEX ( 0 ) /* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_PERIOD_MS ) -#define mainMAX_TX_DELAY ( ( TickType_t ) 0x7f ) -#define mainOFFSET_TIME ( ( TickType_t ) 3 ) + * random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_PERIOD_MS ) +#define mainMAX_TX_DELAY ( ( TickType_t ) 0x7f ) +#define mainOFFSET_TIME ( ( TickType_t ) 3 ) /* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + * be slightly longer than the time between transmissions. If we do not receive + * a character after this time then there must be an error in the transmission or + * the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) /* The task priorities. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) /* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) +#define mainBAUD_RATE ( 57600 ) /* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) +#define mainFIFO_SET ( 0x10 ) -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' +/* The string that is transmitted on the UART contains sequentially the + * characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' /* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) + * can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 ) /* The error routine that is called if the driver library encounters an error. */ #ifdef DEBUG -void -__error__(char *pcFilename, unsigned long ulLine) -{ -} + void __error__( char * pcFilename, + unsigned long ulLine ) + { + } #endif /*-----------------------------------------------------------*/ @@ -160,12 +160,13 @@ static void vCommsRxTask( void * pvParameters ); * The co-routine that periodically initiates the transmission of the string on * the UART. */ -static void vSerialTxCoRoutine( CoRoutineHandle_t xHandle, unsigned portBASE_TYPE uxIndex ); +static void vSerialTxCoRoutine( CoRoutineHandle_t xHandle, + unsigned portBASE_TYPE uxIndex ); -/* +/* * Writes a string the the LCD. */ -static void prvWriteString( const char *pcString ); +static void prvWriteString( const char * pcString ); /* * Initialisation routine for the UART. @@ -175,7 +176,8 @@ static void vSerialInit( void ); /* * Thread safe write to the PDC. */ -static void prvPDCWrite( char cAddress, char cData ); +static void prvPDCWrite( char cAddress, + char cData ); /* * Function to simply set a known value into the general purpose registers @@ -185,7 +187,7 @@ static void prvPDCWrite( char cAddress, char cData ); void prvSetAndCheckRegisters( void ); /* - * Latch the LED that indicates that an error has occurred. + * Latch the LED that indicates that an error has occurred. */ void vSetErrorLED( void ); @@ -197,399 +199,413 @@ static void prvSetupHardware( void ); /*-----------------------------------------------------------*/ /* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ + * defined within this file. */ unsigned portBASE_TYPE uxErrorStatus = pdPASS; /* The next character to transmit. */ static char cNextChar; /* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ + * task. */ static QueueHandle_t xCommsQueue; /*-----------------------------------------------------------*/ void Main( void ) { - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); + /* Create the queue used to communicate between the UART ISR and the Comms + * Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) ); - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + /* Create the co-routine that initiates the transmission of characters + * on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - /* Create the LCD and Comms Rx tasks. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); + /* Should not get here unless we did not have enough memory to start the + * scheduler. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } + /* The co-routines are executed in the idle task using the idle task + * hook. */ + for( ; ; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } } /*-----------------------------------------------------------*/ -static void prvWriteString( const char *pcString ) +static void prvWriteString( const char * pcString ) { - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } } /*-----------------------------------------------------------*/ void vLCDTask( void * pvParameters ) { -unsigned portBASE_TYPE uxIndex; -const unsigned char ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; + unsigned portBASE_TYPE uxIndex; + const unsigned char ucCFGData[] = + { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; /* The strings that are written to the LCD. */ -const char *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "One", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } + const char * pcStringsToDisplay[] = + { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + + for( ; ; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } } /*-----------------------------------------------------------*/ static void vCommsRxTask( void * pvParameters ) { -static char cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = mainFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); - - /* Was the character received (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART registers. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } + static char cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ; ; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character received (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + * reseting the system using the debugger leaving characters already + * in the UART registers. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ) + { + } + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + * receive the first character in the string again. The LED is + * toggled to indicate that the entire string was received without + * error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + * next character in the string. */ + cExpectedChar++; + } + } + } } /*-----------------------------------------------------------*/ -static void vSerialTxCoRoutine( CoRoutineHandle_t xHandle, unsigned portBASE_TYPE uxIndex ) +static void vSerialTxCoRoutine( CoRoutineHandle_t xHandle, + unsigned portBASE_TYPE uxIndex ) { -TickType_t xDelayPeriod; -static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ + TickType_t xDelayPeriod; + static unsigned long * pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ; ; ) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + * the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable( UART0_BASE, UART_INT_TX ); + + /* Toggle the LED to show a new string is being transmitted. */ vParTestToggleLED( mainCOMMS_TX_LED ); - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + /* Delay before we start the string off again. A pseudo-random delay + * is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } + pulRandomBytes++; - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); } - /* Co-routine MUST end with a call to crEND. */ - crEND(); + /* Co-routine MUST end with a call to crEND. */ + crEND(); } /*-----------------------------------------------------------*/ static void vSerialInit( void ) { - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_UART0 ); - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + * UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + /* We dont want to use the fifo. This is for test purposes to generate + * as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); } /*-----------------------------------------------------------*/ -void vUART_ISR(void) +void vUART_ISR( void ) { -unsigned long ulStatus; -char cRxedChar; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrupt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); - xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + unsigned long ulStatus; + char cRxedChar; + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrupt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + * Rxed chars. Posting the character should wake the task that is + * blocked on the queue waiting for characters. */ + cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR ); + xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + cNextChar++; + } + } + + /* If a task was woken by the character being received then we force + * a context switch to occur in case the task is of higher priority than + * the currently executing task (i.e. the task that this interrupt + * interrupted.) */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void prvPDCWrite( char cAddress, char cData ) +static void prvPDCWrite( char cAddress, + char cData ) { - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); } /*-----------------------------------------------------------*/ void vSetErrorLED( void ) { - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); } /*-----------------------------------------------------------*/ void prvSetAndCheckRegisters( void ) { - /* Fill the general purpose registers with known values. */ - __asm volatile( " mov r11, #10\n" - " add r0, r11, #1\n" - " add r1, r11, #2\n" - " add r2, r11, #3\n" - " add r3, r11, #4\n" - " add r4, r11, #5\n" - " add r5, r11, #6\n" - " add r6, r11, #7\n" - " add r7, r11, #8\n" - " add r8, r11, #9\n" - " add r9, r11, #10\n" - " add r10, r11, #11\n" - " add r12, r11, #12" ); - - /* Check the values are as expected. */ - __asm volatile( " cmp r11, #10\n" - " bne set_error_led\n" - " cmp r0, #11\n" - " bne set_error_led\n" - " cmp r1, #12\n" - " bne set_error_led\n" - " cmp r2, #13\n" - " bne set_error_led\n" - " cmp r3, #14\n" - " bne set_error_led\n" - " cmp r4, #15\n" - " bne set_error_led\n" - " cmp r5, #16\n" - " bne set_error_led\n" - " cmp r6, #17\n" - " bne set_error_led\n" - " cmp r7, #18\n" - " bne set_error_led\n" - " cmp r8, #19\n" - " bne set_error_led\n" - " cmp r9, #20\n" - " bne set_error_led\n" - " cmp r10, #21\n" - " bne set_error_led\n" - " cmp r12, #22\n" - " bne set_error_led\n" - " bx lr" ); - - __asm volatile( "set_error_led:\n" - " push {r14}\n" - " ldr r1, =vSetErrorLED\n" - " blx r1\n" - " pop {r14}\n" - " bx lr" ); + /* Fill the general purpose registers with known values. */ + __asm volatile ( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile ( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile ( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h index f40fc8b4c6a..b0fcdfa7082 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c index d5da78b98ce..3e9d9f87067 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c index a2396ef463e..7cd2f38888a 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h index 2e47fc415a6..a11b7bc853e 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c index d5da78b98ce..3e9d9f87067 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c index 57964efbd2d..5eda934131d 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h index 03625393592..20af123ec8e 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c index 0a9c463029c..480e35f7c46 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c index e962859e177..f83f82b783e 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h index d072f6355a3..feb90263231 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c index d5da78b98ce..3e9d9f87067 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c index 8642c37437b..6a19353684e 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h index da5ed000ec0..112bf83b693 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h +++ b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/commstest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c index 548bfa4e0ee..18540370e42 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S316_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -24,15 +24,15 @@ * */ -/* - * This demo application creates eight co-routines and four tasks (five - * including the idle task). The co-routines execute as part of the idle task +/* + * This demo application creates eight co-routines and four tasks (five + * including the idle task). The co-routines execute as part of the idle task * hook. The application is limited in size to allow its compilation using * the KickStart version of the IAR compiler. * - * Six of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. + * Six of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. * * The 'LCD Task' waits on a message queue for messages informing it what and * where to display text. This is the only task that accesses the LCD @@ -45,34 +45,34 @@ * The 'ADC Co-routine' periodically reads the ADC input that is connected to * the light sensor, forms a short message from the value, and then sends this * message to the LCD Task using the same message queue. The ADC readings are - * displayed on the bottom row of the LCD. + * displayed on the bottom row of the LCD. * * The eighth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first + * of a string to UART 0. The co-routine periodically sends the first * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. * - * A loopback connector is required to ensure that each character transmitted + * A loopback connector is required to ensure that each character transmitted * on the UART is also received on the same UART. For test purposes the UART * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and * therefore more likely to highlight any problems. * * The flash co-routines control LED's zero to four. LED five is toggled each * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on + * the string is CORRECTLY received on the UART. LED seven is latched on * should an error be detected in any task or co-routine. * - * In addition the idle task makes repetitive calls to - * vSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching + * In addition the idle task makes repetitive calls to + * vSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching * mechanism. * */ @@ -95,43 +95,43 @@ #include "DriverLib.h" /* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_PERIOD_MS ) +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_PERIOD_MS ) /* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_PERIOD_MS ) +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_PERIOD_MS ) -#define mainADC_DELAY ( 200 / portTICK_PERIOD_MS ) +#define mainADC_DELAY ( 200 / portTICK_PERIOD_MS ) /* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) /* The length of the queue used to send messages to the LCD task. */ -#define mainLCD_QUEUE_LEN ( 3 ) +#define mainLCD_QUEUE_LEN ( 3 ) -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) -#define mainADC_CO_ROUTINE_PRIORITY ( 2 ) +/* The priority of the co-routine used to initiate the transmission of the + * string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) +#define mainADC_CO_ROUTINE_PRIORITY ( 2 ) /* Only one of each co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) -#define mainADC_CO_ROUTINE_INDEX ( 0 ) +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainADC_CO_ROUTINE_INDEX ( 0 ) /* The task priorities. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainMSG_TASK_PRIORITY ( mainLCD_TASK_PRIORITY - 1 ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainMSG_TASK_PRIORITY ( mainLCD_TASK_PRIORITY - 1 ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The LCD had two rows. */ -#define mainTOP_ROW 0 -#define mainBOTTOM_ROW 1 +#define mainTOP_ROW 0 +#define mainBOTTOM_ROW 1 /* Dimension for the buffer into which the ADC value string is written. */ -#define mainMAX_ADC_STRING_LEN 20 +#define mainMAX_ADC_STRING_LEN 20 /* The LED that is lit should an error be detected in any of the tasks or -co-routines. */ -#define mainFAIL_LED ( 7 ) + * co-routines. */ +#define mainFAIL_LED ( 7 ) /*-----------------------------------------------------------*/ @@ -149,7 +149,8 @@ static void prvLCDMessageTask( void * pvParameters ); * The co-routine that reads the ADC and sends messages for display on the * bottom row of the LCD. */ -static void prvADCCoRoutine( CoRoutineHandle_t xHandle, unsigned portBASE_TYPE uxIndex ); +static void prvADCCoRoutine( CoRoutineHandle_t xHandle, + unsigned portBASE_TYPE uxIndex ); /* * Function to simply set a known value into the general purpose registers @@ -159,14 +160,15 @@ static void prvADCCoRoutine( CoRoutineHandle_t xHandle, unsigned portBASE_TYPE u extern void vSetAndCheckRegisters( void ); /* - * Latch the LED that indicates that an error has occurred. + * Latch the LED that indicates that an error has occurred. */ void vSetErrorLED( void ); /* * Thread safe write to the PDC. */ -static void prvPDCWrite( char cAddress, char cData ); +static void prvPDCWrite( char cAddress, + char cData ); /* * Sets up the hardware used by the demo. @@ -179,12 +181,12 @@ static void prvSetupHardware( void ); /* The structure that is passed on the LCD message queue. */ typedef struct { - char **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ - portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ + char ** ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ + portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ } xLCDMessage; /* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ + * defined within this file. */ unsigned portBASE_TYPE uxErrorStatus = pdPASS; /* The queue used to transmit messages to the LCD task. */ @@ -197,242 +199,250 @@ static QueueHandle_t xLCDQueue; */ void main( void ) { - /* Create the queue used by tasks wanting to write to the LCD. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART and the task that receives them, as described at the top of - this file. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Create the task that waits for messages to display on the LCD, plus the - task and co-routine that send messages for display (as described at the top - of this file. */ - xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); - xCoRoutineCreate( prvADCCoRoutine, mainADC_CO_ROUTINE_PRIORITY, mainADC_CO_ROUTINE_INDEX ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); + /* Create the queue used by tasks wanting to write to the LCD. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + * on the UART and the task that receives them, as described at the top of + * this file. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Create the task that waits for messages to display on the LCD, plus the + * task and co-routine that send messages for display (as described at the top + * of this file. */ + xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); + xCoRoutineCreate( prvADCCoRoutine, mainADC_CO_ROUTINE_PRIORITY, mainADC_CO_ROUTINE_INDEX ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + * scheduler. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvLCDMessageTask( void * pvParameters ) { /* The strings that are written to the LCD. */ -char *pcStringsToDisplay[] = { - "IAR ", - "Stellaris ", - "Demo ", - "www.FreeRTOS.org", - "" - }; - -QueueHandle_t *pxLCDQueue; -xLCDMessage xMessageToSend; -portBASE_TYPE xIndex = 0; - - /* To test the parameter passing mechanism, the queue on which messages are - posted is passed in as a parameter even though it is available as a file - scope variable anyway. */ - pxLCDQueue = ( QueueHandle_t * ) pvParameters; - - for( ;; ) - { - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - - /* Create the message object to send to the LCD task. */ - xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; - xMessageToSend.xRow = mainTOP_ROW; - - /* Post the message to be displayed. */ - if( !xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ) ) - { - uxErrorStatus = pdFAIL; - } - - /* Move onto the next message, wrapping when necessary. */ - xIndex++; - if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) - { - xIndex = 0; - - /* Delay longer before going back to the start of the messages. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - } + char * pcStringsToDisplay[] = + { + "IAR ", + "Stellaris ", + "Demo ", + "www.FreeRTOS.org", + "" + }; + + QueueHandle_t * pxLCDQueue; + xLCDMessage xMessageToSend; + portBASE_TYPE xIndex = 0; + + /* To test the parameter passing mechanism, the queue on which messages are + * posted is passed in as a parameter even though it is available as a file + * scope variable anyway. */ + pxLCDQueue = ( QueueHandle_t * ) pvParameters; + + for( ; ; ) + { + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + + /* Create the message object to send to the LCD task. */ + xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; + xMessageToSend.xRow = mainTOP_ROW; + + /* Post the message to be displayed. */ + if( !xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ) ) + { + uxErrorStatus = pdFAIL; + } + + /* Move onto the next message, wrapping when necessary. */ + xIndex++; + + if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) + { + xIndex = 0; + + /* Delay longer before going back to the start of the messages. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + } } /*-----------------------------------------------------------*/ void prvLCDTask( void * pvParameters ) { -unsigned portBASE_TYPE uxIndex; -QueueHandle_t *pxLCDQueue; -xLCDMessage xReceivedMessage; -char *pcString; -const unsigned char ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - - /* To test the parameter passing mechanism, the queue on which messages are - received is passed in as a parameter even though it is available as a file - scope variable anyway. */ - pxLCDQueue = ( QueueHandle_t * ) pvParameters; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Wait for a message to arrive. */ - if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) - { - /* Which row does the received message say to write to? */ - PDCLCDSetPos( 0, xReceivedMessage.xRow ); - - /* Where is the string we are going to display? */ - pcString = *xReceivedMessage.ppcMessageToDisplay; - - while( *pcString ) - { - /* Don't write out the string too quickly as LCD's are usually - pretty slow devices. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } - } - } + unsigned portBASE_TYPE uxIndex; + QueueHandle_t * pxLCDQueue; + xLCDMessage xReceivedMessage; + char * pcString; + const unsigned char ucCFGData[] = + { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + + /* To test the parameter passing mechanism, the queue on which messages are + * received is passed in as a parameter even though it is available as a file + * scope variable anyway. */ + pxLCDQueue = ( QueueHandle_t * ) pvParameters; + + /* Configure the LCD. */ + uxIndex = 0; + + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + + for( ; ; ) + { + /* Wait for a message to arrive. */ + if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) + { + /* Which row does the received message say to write to? */ + PDCLCDSetPos( 0, xReceivedMessage.xRow ); + + /* Where is the string we are going to display? */ + pcString = *xReceivedMessage.ppcMessageToDisplay; + + while( *pcString ) + { + /* Don't write out the string too quickly as LCD's are usually + * pretty slow devices. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } + } + } } /*-----------------------------------------------------------*/ -static void prvADCCoRoutine( CoRoutineHandle_t xHandle, unsigned portBASE_TYPE uxIndex ) +static void prvADCCoRoutine( CoRoutineHandle_t xHandle, + unsigned portBASE_TYPE uxIndex ) { -static unsigned long ulADCValue; -static char cMessageBuffer[ mainMAX_ADC_STRING_LEN ]; -static char *pcMessage; -static xLCDMessage xMessageToSend; - - /* Co-routines MUST start with a call to crSTART(). */ - crSTART( xHandle ); - - for( ;; ) - { - /* Start an ADC conversion. */ - ADCProcessorTrigger( ADC_BASE, 0 ); - - /* Simply delay - when we unblock the result should be available */ - crDELAY( xHandle, mainADC_DELAY ); - - /* Get the ADC result. */ - ADCSequenceDataGet( ADC_BASE, 0, &ulADCValue ); - - /* Create a string with the result. */ - sprintf( cMessageBuffer, "ADC = %d ", ulADCValue ); - pcMessage = cMessageBuffer; - - /* Configure the message we are going to send for display. */ - xMessageToSend.ppcMessageToDisplay = ( char** ) &pcMessage; - xMessageToSend.xRow = mainBOTTOM_ROW; - - /* Send the string to the LCD task for display. We are sending - on a task queue so do not have the option to block. */ - if( !xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ) ) - { - uxErrorStatus = pdFAIL; - } - } - - /* Co-routines MUST end with a call to crEND(). */ - crEND(); + static unsigned long ulADCValue; + static char cMessageBuffer[ mainMAX_ADC_STRING_LEN ]; + static char * pcMessage; + static xLCDMessage xMessageToSend; + + /* Co-routines MUST start with a call to crSTART(). */ + crSTART( xHandle ); + + for( ; ; ) + { + /* Start an ADC conversion. */ + ADCProcessorTrigger( ADC_BASE, 0 ); + + /* Simply delay - when we unblock the result should be available */ + crDELAY( xHandle, mainADC_DELAY ); + + /* Get the ADC result. */ + ADCSequenceDataGet( ADC_BASE, 0, &ulADCValue ); + + /* Create a string with the result. */ + sprintf( cMessageBuffer, "ADC = %d ", ulADCValue ); + pcMessage = cMessageBuffer; + + /* Configure the message we are going to send for display. */ + xMessageToSend.ppcMessageToDisplay = ( char ** ) &pcMessage; + xMessageToSend.xRow = mainBOTTOM_ROW; + + /* Send the string to the LCD task for display. We are sending + * on a task queue so do not have the option to block. */ + if( !xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ) ) + { + uxErrorStatus = pdFAIL; + } + } + + /* Co-routines MUST end with a call to crEND(). */ + crEND(); } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); - - /* The ADC is used to read the light sensor. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC ); - ADCSequenceConfigure( ADC_BASE, 3, ADC_TRIGGER_PROCESSOR, 0); + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); + + /* The ADC is used to read the light sensor. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC ); + ADCSequenceConfigure( ADC_BASE, 3, ADC_TRIGGER_PROCESSOR, 0 ); ADCSequenceStepConfigure( ADC_BASE, 0, 0, ADC_CTL_CH0 | ADC_CTL_END ); ADCSequenceEnable( ADC_BASE, 0 ); - } /*-----------------------------------------------------------*/ -static void prvPDCWrite( char cAddress, char cData ) +static void prvPDCWrite( char cAddress, + char cData ) { - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); } /*-----------------------------------------------------------*/ void vSetErrorLED( void ) { - vParTestSetLED( mainFAIL_LED, pdTRUE ); + vParTestSetLED( mainFAIL_LED, pdTRUE ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - vSetAndCheckRegisters(); - - /* See if the comms task and co-routine has found any errors. */ - if( uxGetCommsStatus() != pdPASS ) - { - vParTestSetLED( mainFAIL_LED, pdTRUE ); - } - } + /* The co-routines are executed in the idle task using the idle task + * hook. */ + for( ; ; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + vSetAndCheckRegisters(); + + /* See if the comms task and co-routine has found any errors. */ + if( uxGetCommsStatus() != pdPASS ) + { + vParTestSetLED( mainFAIL_LED, pdTRUE ); + } + } } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/FreeRTOSConfig.h index 94dc2edb1c9..ab1923b6c60 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.c index 879de40e1f6..a410a401d9f 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.h index 8b6b382c6dd..17320c8902f 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/timertest.c b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/timertest.c index e2aa5f26082..bc756b01299 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/timertest.c +++ b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/LocalDemoFiles/timertest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/main.c b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/main.c index 5d79c25e139..0ad6eb0684b 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S6965_GCC_QEMU/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -49,10 +49,10 @@ * "qemu-system-arm -machine lm3s6965evb -s -S -kernel [pat_to]\RTOSDemo.elf" * * To enable FreeRTOS+Trace: - * 1) Add #include "trcRecorder.h" to the bottom of FreeRTOSConfig.h. - * 2) Call vTraceEnable( TRC_START ); at the top of main. - * 3) Ensure the "FreeRTOS+Trace Recorder" folder in the Project Explorer - * window is not excluded from the build. + * 1) Add #include "trcRecorder.h" to the bottom of FreeRTOSConfig.h. + * 2) Call vTraceEnable( TRC_START ); at the top of main. + * 3) Ensure the "FreeRTOS+Trace Recorder" folder in the Project Explorer + * window is not excluded from the build. * * To retrieve the trace files: * 1) Use the Memory windows in the Debug perspective to dump RAM from the @@ -60,10 +60,10 @@ */ /************************************************************************* - * Please ensure to read http://www.freertos.org/portlm3sx965.html - * which provides information on configuring and running this demo for the - * various Luminary Micro EKs. - *************************************************************************/ +* Please ensure to read http://www.freertos.org/portlm3sx965.html +* which provides information on configuring and running this demo for the +* various Luminary Micro EKs. +*************************************************************************/ /* Standard includes. */ #include @@ -101,37 +101,37 @@ /*-----------------------------------------------------------*/ /* The time between cycles of the 'check' functionality (defined within the -tick hook. */ -#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) + * tick hook. */ +#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) /* Task stack sizes. */ -#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 40 ) -#define mainMESSAGE_BUFFER_TASKS_STACK_SIZE ( 100 ) +#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 40 ) +#define mainMESSAGE_BUFFER_TASKS_STACK_SIZE ( 100 ) /* Task priorities. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* The maximum number of message that can be waiting for display at any one -time. */ -#define mainOLED_QUEUE_SIZE ( 3 ) + * time. */ +#define mainOLED_QUEUE_SIZE ( 3 ) /* Dimensions the buffer into which the jitter time is written. */ -#define mainMAX_MSG_LEN 25 +#define mainMAX_MSG_LEN 25 /* The period of the system clock in nano seconds. This is used to calculate -the jitter time in nano seconds. */ -#define mainNS_PER_CLOCK ( ( uint32_t ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + * the jitter time in nano seconds. */ +#define mainNS_PER_CLOCK ( ( uint32_t ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) /* Constants used when writing strings to the display. */ -#define mainCHARACTER_HEIGHT ( 9 ) -#define mainMAX_ROWS_128 ( mainCHARACTER_HEIGHT * 14 ) -#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) -#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) -#define mainFULL_SCALE ( 15 ) -#define ulSSI_FREQUENCY ( 3500000UL ) +#define mainCHARACTER_HEIGHT ( 9 ) +#define mainMAX_ROWS_128 ( mainCHARACTER_HEIGHT * 14 ) +#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) +#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) +#define mainFULL_SCALE ( 15 ) +#define ulSSI_FREQUENCY ( 3500000UL ) /*-----------------------------------------------------------*/ @@ -141,7 +141,7 @@ the jitter time in nano seconds. */ * access the display directly. Other tasks wanting to display a message send * the message to the gatekeeper. */ -static void prvOLEDTask( void *pvParameters ); +static void prvOLEDTask( void * pvParameters ); /* * Configure the hardware for the demo. @@ -157,7 +157,8 @@ extern void vSetupHighFrequencyTimer( void ); /* * Hook functions that can get called by the kernel. */ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* @@ -176,294 +177,315 @@ const char * const pcWelcomeMessage = " www.FreeRTOS.org"; /*-----------------------------------------------------------*/ /************************************************************************* - * Please ensure to read http://www.freertos.org/portlm3sx965.html - * which provides information on configuring and running this demo for the - * various Luminary Micro EKs. - *************************************************************************/ +* Please ensure to read http://www.freertos.org/portlm3sx965.html +* which provides information on configuring and running this demo for the +* various Luminary Micro EKs. +*************************************************************************/ int main( void ) { - /* Initialise the trace recorder. Use of the trace recorder is optional. - See http://www.FreeRTOS.org/trace for more information and the comments at - the top of this file regarding enabling trace in this demo. - vTraceEnable( TRC_START ); */ - - prvSetupHardware(); - - /* Create the queue used by the OLED task. Messages for display on the OLED - are received via this queue. */ - xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( char * ) ); - - /* Start the standard demo tasks. */ - vStartRecursiveMutexTasks(); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartQueuePeekTasks(); - vStartQueueSetTasks(); - vStartEventGroupTasks(); - vStartMessageBufferTasks( mainMESSAGE_BUFFER_TASKS_STACK_SIZE ); - vStartStreamBufferTasks(); - - /* Start the tasks defined within this file/specific to this demo. */ - xTaskCreate( prvOLEDTask, "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Uncomment the following line to configure the high frequency interrupt - used to measure the interrupt jitter time. - vSetupHighFrequencyTimer(); */ - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - for( ;; ); + /* Initialise the trace recorder. Use of the trace recorder is optional. + * See http://www.FreeRTOS.org/trace for more information and the comments at + * the top of this file regarding enabling trace in this demo. + * vTraceEnable( TRC_START ); */ + + prvSetupHardware(); + + /* Create the queue used by the OLED task. Messages for display on the OLED + * are received via this queue. */ + xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( char * ) ); + + /* Start the standard demo tasks. */ + vStartRecursiveMutexTasks(); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartQueuePeekTasks(); + vStartQueueSetTasks(); + vStartEventGroupTasks(); + vStartMessageBufferTasks( mainMESSAGE_BUFFER_TASKS_STACK_SIZE ); + vStartStreamBufferTasks(); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( prvOLEDTask, "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + * tasks were running prior to their creation in order to ascertain whether + * or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Uncomment the following line to configure the high frequency interrupt + * used to measure the interrupt jitter time. + * vSetupHighFrequencyTimer(); */ + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + * task. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void prvSetupHardware( void ) { /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is - a workaround to allow the PLL to operate reliably. */ + * a workaround to allow the PLL to operate reliably. */ if( DEVICE_IS_REVA2 ) { SysCtlLDOSet( SYSCTL_LDO_2_75V ); } - /* Set the clocking to run from the PLL at 50 MHz */ - SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); - /* Initialise the UART - QEMU usage does not seem to require this - initialisation. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_UART0 ); - UARTEnable( UART0_BASE ); + /* Initialise the UART - QEMU usage does not seem to require this + * initialisation. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_UART0 ); + UARTEnable( UART0_BASE ); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { -static const char * pcMessage = "PASS"; -static uint32_t ulTicksSinceLastDisplay = 0; -BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - /* Called from every tick interrupt. Have enough ticks passed to make it - time to perform our health status check again? */ - ulTicksSinceLastDisplay++; - if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) - { - ulTicksSinceLastDisplay = 0; - - /* Has an error been found in any task? */ - if( xAreStreamBufferTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN STRM"; - } - else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN MSG"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN CREATE"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN BLOCK TIME"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN SEMAPHORE"; - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN PEEK Q"; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN REC MUTEX"; - } - else if( xAreQueueSetTasksStillRunning() != pdPASS ) - { - pcMessage = "ERROR IN Q SET"; - } - else if( xAreEventGroupTasksStillRunning() != pdTRUE ) - { - pcMessage = "ERROR IN EVNT GRP"; - } - - /* Send the message to the OLED gatekeeper for display. */ - xHigherPriorityTaskWoken = pdFALSE; - xQueueSendFromISR( xOLEDQueue, &pcMessage, &xHigherPriorityTaskWoken ); - } - - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - - /* Call the event group ISR tests. */ - vPeriodicEventGroupsProcessing(); - - /* Exercise stream buffers from interrupts. */ - vPeriodicStreamBufferProcessing(); + static const char * pcMessage = "PASS"; + static uint32_t ulTicksSinceLastDisplay = 0; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* Called from every tick interrupt. Have enough ticks passed to make it + * time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreStreamBufferTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN STRM"; + } + else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN MSG"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN CREATE"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN REC MUTEX"; + } + else if( xAreQueueSetTasksStillRunning() != pdPASS ) + { + pcMessage = "ERROR IN Q SET"; + } + else if( xAreEventGroupTasksStillRunning() != pdTRUE ) + { + pcMessage = "ERROR IN EVNT GRP"; + } + + /* Send the message to the OLED gatekeeper for display. */ + xHigherPriorityTaskWoken = pdFALSE; + xQueueSendFromISR( xOLEDQueue, &pcMessage, &xHigherPriorityTaskWoken ); + } + + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + + /* Call the event group ISR tests. */ + vPeriodicEventGroupsProcessing(); + + /* Exercise stream buffers from interrupts. */ + vPeriodicStreamBufferProcessing(); } /*-----------------------------------------------------------*/ static void prvPrintString( const char * pcString ) { - while( *pcString != 0x00 ) - { - UARTCharPut( UART0_BASE, *pcString ); - pcString++; - } + while( *pcString != 0x00 ) + { + UARTCharPut( UART0_BASE, *pcString ); + pcString++; + } } /*-----------------------------------------------------------*/ -void prvOLEDTask( void *pvParameters ) +void prvOLEDTask( void * pvParameters ) { -const char *pcMessage; -uint32_t ulY, ulMaxY; -static char cMessage[ mainMAX_MSG_LEN ]; -const unsigned char *pucImage; + const char * pcMessage; + uint32_t ulY, ulMaxY; + static char cMessage[ mainMAX_MSG_LEN ]; + const unsigned char * pucImage; /* Functions to access the OLED. The one used depends on the dev kit -being used. */ -void ( *vOLEDInit )( uint32_t ) = NULL; -void ( *vOLEDStringDraw )( const char *, uint32_t, uint32_t, unsigned char ) = NULL; -void ( *vOLEDImageDraw )( const unsigned char *, uint32_t, uint32_t, uint32_t, uint32_t ) = NULL; -void ( *vOLEDClear )( void ) = NULL; - - /* Prevent warnings about unused parameters. */ - ( void ) pvParameters; - - /* Map the OLED access functions to the driver functions that are appropriate - for the evaluation kit being used. */ - configASSERT( ( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) == SYSCTL_DID1_PRTNO_6965 ); - vOLEDInit = OSRAM128x64x4Init; - vOLEDStringDraw = OSRAM128x64x4StringDraw; - vOLEDImageDraw = OSRAM128x64x4ImageDraw; - vOLEDClear = OSRAM128x64x4Clear; - ulMaxY = mainMAX_ROWS_64; - pucImage = pucBasicBitmap; - ulY = ulMaxY; - - /* Initialise the OLED and display a startup message. */ - vOLEDInit( ulSSI_FREQUENCY ); - vOLEDStringDraw( "POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); - vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); - - for( ;; ) - { - /* Wait for a message to arrive that requires displaying. */ - xQueueReceive( xOLEDQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message on the next available row. */ - ulY += mainCHARACTER_HEIGHT; - if( ulY >= ulMaxY ) - { - ulY = mainCHARACTER_HEIGHT; - vOLEDClear(); - vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); - } - - /* Display the message along with the maximum jitter time from the - high priority time test. */ - sprintf( cMessage, "%s %u", pcMessage, ( unsigned int ) xTaskGetTickCount() ); - vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); - prvPrintString( cMessage ); - prvPrintString( "\r\n" ); - } + * being used. */ + void ( * vOLEDInit )( uint32_t ) = NULL; + void ( * vOLEDStringDraw )( const char *, + uint32_t, + uint32_t, + unsigned char ) = NULL; + void ( * vOLEDImageDraw )( const unsigned char *, + uint32_t, + uint32_t, + uint32_t, + uint32_t ) = NULL; + void ( * vOLEDClear )( void ) = NULL; + + /* Prevent warnings about unused parameters. */ + ( void ) pvParameters; + + /* Map the OLED access functions to the driver functions that are appropriate + * for the evaluation kit being used. */ + configASSERT( ( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) == SYSCTL_DID1_PRTNO_6965 ); + vOLEDInit = OSRAM128x64x4Init; + vOLEDStringDraw = OSRAM128x64x4StringDraw; + vOLEDImageDraw = OSRAM128x64x4ImageDraw; + vOLEDClear = OSRAM128x64x4Clear; + ulMaxY = mainMAX_ROWS_64; + pucImage = pucBasicBitmap; + ulY = ulMaxY; + + /* Initialise the OLED and display a startup message. */ + vOLEDInit( ulSSI_FREQUENCY ); + vOLEDStringDraw( "POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); + vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); + + for( ; ; ) + { + /* Wait for a message to arrive that requires displaying. */ + xQueueReceive( xOLEDQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message on the next available row. */ + ulY += mainCHARACTER_HEIGHT; + + if( ulY >= ulMaxY ) + { + ulY = mainCHARACTER_HEIGHT; + vOLEDClear(); + vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); + } + + /* Display the message along with the maximum jitter time from the + * high priority time test. */ + sprintf( cMessage, "%s %u", pcMessage, ( unsigned int ) xTaskGetTickCount() ); + vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); + prvPrintString( cMessage ); + prvPrintString( "\r\n" ); + } } /*-----------------------------------------------------------*/ -volatile char *pcOverflowedTask = NULL; /* Prevent task name being optimised away. */ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +volatile char * pcOverflowedTask = NULL; /* Prevent task name being optimised away. */ +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pxTask; - pcOverflowedTask = pcTaskName; - vAssertCalled( __FILE__, __LINE__ ); - for( ;; ); + ( void ) pxTask; + pcOverflowedTask = pcTaskName; + vAssertCalled( __FILE__, __LINE__ ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vAssertCalled( const char *pcFile, uint32_t ulLine ) +void vAssertCalled( const char * pcFile, + uint32_t ulLine ) { -volatile uint32_t ulSetTo1InDebuggerToExit = 0; - - taskENTER_CRITICAL(); - { - while( ulSetTo1InDebuggerToExit == 0 ) - { - /* Nothing to do here. Set the loop variable to a non zero value in - the debugger to step out of this function to the point that caused - the assertion. */ - ( void ) pcFile; - ( void ) ulLine; - } - } - taskEXIT_CRITICAL(); + volatile uint32_t ulSetTo1InDebuggerToExit = 0; + + taskENTER_CRITICAL(); + { + while( ulSetTo1InDebuggerToExit == 0 ) + { + /* Nothing to do here. Set the loop variable to a non zero value in + * the debugger to step out of this function to the point that caused + * the assertion. */ + ( void ) pcFile; + ( void ) ulLine; + } + } + taskEXIT_CRITICAL(); } /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ -char * _sbrk_r (struct _reent *r, int incr) +char * _sbrk_r( struct _reent * r, + int incr ) { - /* Just to keep the linker quiet. */ - ( void ) r; - ( void ) incr; + /* Just to keep the linker quiet. */ + ( void ) r; + ( void ) incr; - /* Check this function is never called by forcing an assert() if it is. */ - configASSERT( incr == -1 ); + /* Check this function is never called by forcing an assert() if it is. */ + configASSERT( incr == -1 ); - return NULL; + return NULL; } diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h index 51a78debfb4..e8fb43c297a 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c b/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c index c0e29d0ff7b..530dd4b5d71 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S811_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -80,26 +80,27 @@ #include "BlockQ.h" /* Delay between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) +#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) /* UART configuration - note this does not use the FIFO so is not very -efficient. */ -#define mainBAUD_RATE ( 19200 ) -#define mainFIFO_SET ( 0x10 ) + * efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) /* Demo task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Demo board specifics. */ -#define mainPUSH_BUTTON GPIO_PIN_4 +#define mainPUSH_BUTTON GPIO_PIN_4 /* Misc. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainDEBOUNCE_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) -#define mainNO_DELAY ( ( TickType_t ) 0 ) +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) +#define mainNO_DELAY ( ( TickType_t ) 0 ) + /* * Configure the processor and peripherals for this demo. */ @@ -108,25 +109,25 @@ static void prvSetupHardware( void ); /* * The 'check' task, as described at the top of this file. */ -static void vCheckTask( void *pvParameters ); +static void vCheckTask( void * pvParameters ); /* * The task that is woken by the ISR that processes GPIO interrupts originating * from the push button. */ -static void vButtonHandlerTask( void *pvParameters ); +static void vButtonHandlerTask( void * pvParameters ); /* * The task that controls access to the LCD. */ -static void vPrintTask( void *pvParameter ); +static void vPrintTask( void * pvParameter ); /* String that is transmitted on the UART. */ -static char *cMessage = "Task woken by button interrupt! --- "; -static volatile char *pcNextChar; +static char * cMessage = "Task woken by button interrupt! --- "; +static volatile char * pcNextChar; /* The semaphore used to wake the button handler task from within the GPIO -interrupt handler. */ + * interrupt handler. */ SemaphoreHandle_t xButtonSemaphore; /* The queue used to send strings to the print task for display on the LCD. */ @@ -136,224 +137,226 @@ QueueHandle_t xPrintQueue; int main( void ) { - /* Configure the clocks, UART and GPIO. */ - prvSetupHardware(); + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); - /* Create the semaphore used to wake the button handler task from the GPIO - ISR. */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); + /* Create the semaphore used to wake the button handler task from the GPIO + * ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - /* Start the tasks defined within the file. */ - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - /* Start the scheduler. */ - vTaskStartScheduler(); + /* Start the scheduler. */ + vTaskStartScheduler(); - /* Will only get here if there was insufficient heap to start the - scheduler. */ + /* Will only get here if there was insufficient heap to start the + * scheduler. */ - return 0; + return 0; } /*-----------------------------------------------------------*/ -static void vCheckTask( void *pvParameters ) +static void vCheckTask( void * pvParameters ) { -portBASE_TYPE xErrorOccurred = pdFALSE; -TickType_t xLastExecutionTime; -const char *pcPassMessage = "PASS"; -const char *pcFailMessage = "FAIL"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. We do not write directly to the LCD, but instead - queue a message for display by the print task. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } + portBASE_TYPE xErrorOccurred = pdFALSE; + TickType_t xLastExecutionTime; + const char * pcPassMessage = "PASS"; + const char * pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + * never cleared again. We do not write directly to the LCD, but instead + * queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - /* Setup the push button. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); - GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); - IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); - GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - IntEnable( INT_GPIOC ); + /* Setup the push button. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOC ); + GPIODirModeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN ); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); - /* Enable the UART. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + /* Enable the UART. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_UART0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOA ); - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + * UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - /* We don't want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + /* We don't want to use the fifo. This is for test purposes to generate + * as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - /* Enable Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; - IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); - IntEnable( INT_UART0 ); + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); - /* Initialise the LCD> */ + /* Initialise the LCD> */ OSRAMInit( false ); - OSRAMStringDraw("www.FreeRTOS.org", 0, 0); - OSRAMStringDraw("LM3S811 demo", 16, 1); + OSRAMStringDraw( "www.FreeRTOS.org", 0, 0 ); + OSRAMStringDraw( "LM3S811 demo", 16, 1 ); } /*-----------------------------------------------------------*/ -static void vButtonHandlerTask( void *pvParameters ) +static void vButtonHandlerTask( void * pvParameters ) { -const char *pcInterruptMessage = "Int"; - - for( ;; ) - { - /* Wait for a GPIO interrupt to wake this task. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Start the Tx of the message on the UART. */ - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - pcNextChar = cMessage; - - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - - pcNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Queue a message for the print task to display on the LCD. */ - xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); - - /* Make sure we don't process bounces. */ - vTaskDelay( mainDEBOUNCE_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - } + const char * pcInterruptMessage = "Int"; + + for( ; ; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ) + { + } + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable( UART0_BASE, UART_INT_TX ); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } } /*-----------------------------------------------------------*/ -void vUART_ISR(void) +void vUART_ISR( void ) { -unsigned long ulStatus; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( *pcNextChar != 0 ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - pcNextChar++; - } - } + unsigned long ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != 0 ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + } } /*-----------------------------------------------------------*/ void vGPIO_ISR( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - /* Clear the interrupt. */ - GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + /* Clear the interrupt. */ + GPIOPinIntClear( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - /* Wake the button handler task. */ - xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + /* Wake the button handler task. */ + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void vPrintTask( void *pvParameters ) +static void vPrintTask( void * pvParameters ) { -char *pcMessage; -unsigned portBASE_TYPE uxLine = 0, uxRow = 0; - - for( ;; ) - { - /* Wait for a message to arrive. */ - xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message to the LCD. */ - uxRow++; - uxLine++; - OSRAMClear(); - OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); - } + char * pcMessage; + unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ; ; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01 ); + } } - diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h index 3b70ce5063b..4b65e3c2291 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c b/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c index 21d881556f5..73f89ceee6f 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S811_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -80,26 +80,27 @@ #include "BlockQ.h" /* Delay between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) +#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) /* UART configuration - note this does not use the FIFO so is not very -efficient. */ -#define mainBAUD_RATE ( 19200 ) -#define mainFIFO_SET ( 0x10 ) + * efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) /* Demo task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Demo board specifics. */ -#define mainPUSH_BUTTON GPIO_PIN_4 +#define mainPUSH_BUTTON GPIO_PIN_4 /* Misc. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainDEBOUNCE_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) -#define mainNO_DELAY ( ( TickType_t ) 0 ) +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) +#define mainNO_DELAY ( ( TickType_t ) 0 ) + /* * Configure the processor and peripherals for this demo. */ @@ -108,25 +109,25 @@ static void prvSetupHardware( void ); /* * The 'check' task, as described at the top of this file. */ -static void vCheckTask( void *pvParameters ); +static void vCheckTask( void * pvParameters ); /* * The task that is woken by the ISR that processes GPIO interrupts originating * from the push button. */ -static void vButtonHandlerTask( void *pvParameters ); +static void vButtonHandlerTask( void * pvParameters ); /* * The task that controls access to the LCD. */ -static void vPrintTask( void *pvParameter ); +static void vPrintTask( void * pvParameter ); /* String that is transmitted on the UART. */ -static char *cMessage = "Task woken by button interrupt! --- "; -static volatile char *pcNextChar; +static char * cMessage = "Task woken by button interrupt! --- "; +static volatile char * pcNextChar; /* The semaphore used to wake the button handler task from within the GPIO -interrupt handler. */ + * interrupt handler. */ SemaphoreHandle_t xButtonSemaphore; /* The queue used to send strings to the print task for display on the LCD. */ @@ -136,223 +137,225 @@ QueueHandle_t xPrintQueue; int main( void ) { - /* Configure the clocks, UART and GPIO. */ - prvSetupHardware(); + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); - /* Create the semaphore used to wake the button handler task from the GPIO - ISR. */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); + /* Create the semaphore used to wake the button handler task from the GPIO + * ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - /* Start the tasks defined within the file. */ - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - /* Start the scheduler. */ - vTaskStartScheduler(); + /* Start the scheduler. */ + vTaskStartScheduler(); - /* Will only get here if there was insufficient heap to start the - scheduler. */ + /* Will only get here if there was insufficient heap to start the + * scheduler. */ - return 0; + return 0; } /*-----------------------------------------------------------*/ -static void vCheckTask( void *pvParameters ) +static void vCheckTask( void * pvParameters ) { -portBASE_TYPE xErrorOccurred = pdFALSE; -TickType_t xLastExecutionTime; -const char *pcPassMessage = "PASS"; -const char *pcFailMessage = "FAIL"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. We do not write directly to the LCD, but instead - queue a message for display by the print task. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } + portBASE_TYPE xErrorOccurred = pdFALSE; + TickType_t xLastExecutionTime; + const char * pcPassMessage = "PASS"; + const char * pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + * never cleared again. We do not write directly to the LCD, but instead + * queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - /* Setup the push button. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); - GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); - IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); - GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - IntEnable( INT_GPIOC ); + /* Setup the push button. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOC ); + GPIODirModeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN ); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); - /* Enable the UART. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + /* Enable the UART. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_UART0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOA ); - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + * UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - /* We don't want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + /* We don't want to use the fifo. This is for test purposes to generate + * as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - /* Enable Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; - IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); - IntEnable( INT_UART0 ); + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); - /* Initialise the LCD> */ + /* Initialise the LCD> */ OSRAMInit( false ); - OSRAMStringDraw("www.FreeRTOS.org", 0, 0); - OSRAMStringDraw("LM3S811 demo", 16, 1); + OSRAMStringDraw( "www.FreeRTOS.org", 0, 0 ); + OSRAMStringDraw( "LM3S811 demo", 16, 1 ); } /*-----------------------------------------------------------*/ -static void vButtonHandlerTask( void *pvParameters ) +static void vButtonHandlerTask( void * pvParameters ) { -const char *pcInterruptMessage = "Int"; - - for( ;; ) - { - /* Wait for a GPIO interrupt to wake this task. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Start the Tx of the message on the UART. */ - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - pcNextChar = cMessage; - - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - - pcNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Queue a message for the print task to display on the LCD. */ - xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); - - /* Make sure we don't process bounces. */ - vTaskDelay( mainDEBOUNCE_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - } + const char * pcInterruptMessage = "Int"; + + for( ; ; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ) + { + } + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable( UART0_BASE, UART_INT_TX ); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } } /*-----------------------------------------------------------*/ -void vUART_ISR(void) +void vUART_ISR( void ) { -unsigned long ulStatus; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( *pcNextChar != NULL ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - pcNextChar++; - } - } + unsigned long ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != NULL ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + } } /*-----------------------------------------------------------*/ void vGPIO_ISR( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - /* Clear the interrupt. */ - GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + /* Clear the interrupt. */ + GPIOPinIntClear( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - /* Wake the button handler task. */ - xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + /* Wake the button handler task. */ + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void vPrintTask( void *pvParameters ) +static void vPrintTask( void * pvParameters ) { -char *pcMessage; -unsigned portBASE_TYPE uxLine = 0, uxRow = 0; - - for( ;; ) - { - /* Wait for a message to arrive. */ - xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message to the LCD. */ - uxRow++; - uxLine++; - OSRAMClear(); - OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); - } + char * pcMessage; + unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ; ; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01 ); + } } - diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h index 618834c6299..fe6f0b34add 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c b/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c index e4dc81721bd..0665e863cd2 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c +++ b/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c b/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c index f9df97d52a3..b063d868912 100644 --- a/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c +++ b/FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -26,16 +26,16 @@ /* - * This project contains an application demonstrating the use of the + * This project contains an application demonstrating the use of the * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval * board. See http://www.FreeRTOS.org for more information. * - * main() simply sets up the hardware, creates all the demo application tasks, + * main() simply sets up the hardware, creates all the demo application tasks, * then starts the scheduler. http://www.freertos.org/a00102.html provides - * more information on the standard demo tasks. + * more information on the standard demo tasks. * * In addition to a subset of the standard demo application tasks, main.c also - * defines the following tasks: + * defines the following tasks: * * + A 'Print' task. The print task is the only task permitted to access the * LCD - thus ensuring mutual exclusion and consistent access to the resource. @@ -44,12 +44,12 @@ * blocked - only waking when a message is queued for display. * * + A 'Button handler' task. The eval board contains a user push button that - * is configured to generate interrupts. The interrupt handler uses a - * semaphore to wake the button handler task - demonstrating how the priority + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority * mechanism can be used to defer interrupt processing to the task level. The * button handler task sends a message both to the LCD (via the print task) and * the UART where it can be viewed using a dumb terminal (via the UART to USB - * converter on the eval board). NOTES: The dumb terminal must be closed in + * converter on the eval board). NOTES: The dumb terminal must be closed in * order to reflash the microcontroller. A very basic interrupt driven UART * driver is used that does not use the FIFO. 19200 baud is used. * @@ -80,281 +80,287 @@ #include "BlockQ.h" /* Delay between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) +#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS ) -/* UART configuration - note this does not use the FIFO so is not very -efficient. */ -#define mainBAUD_RATE ( 19200 ) -#define mainFIFO_SET ( 0x10 ) +/* UART configuration - note this does not use the FIFO so is not very + * efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) /* Demo task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Demo board specifics. */ -#define mainPUSH_BUTTON GPIO_PIN_4 +#define mainPUSH_BUTTON GPIO_PIN_4 /* Misc. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainDEBOUNCE_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) -#define mainNO_DELAY ( ( TickType_t ) 0 ) +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) +#define mainNO_DELAY ( ( TickType_t ) 0 ) + /* - * Configure the processor and peripherals for this demo. + * Configure the processor and peripherals for this demo. */ static void prvSetupHardware( void ); /* * The 'check' task, as described at the top of this file. */ -static void vCheckTask( void *pvParameters ); +static void vCheckTask( void * pvParameters ); /* * The task that is woken by the ISR that processes GPIO interrupts originating * from the push button. */ -static void vButtonHandlerTask( void *pvParameters ); +static void vButtonHandlerTask( void * pvParameters ); /* * The task that controls access to the LCD. */ -static void vPrintTask( void *pvParameter ); +static void vPrintTask( void * pvParameter ); /* String that is transmitted on the UART. */ -static char *cMessage = "Task woken by button interrupt! --- "; -static volatile char *pcNextChar; +static char * cMessage = "Task woken by button interrupt! --- "; +static volatile char * pcNextChar; /* The semaphore used to wake the button handler task from within the GPIO -interrupt handler. */ + * interrupt handler. */ SemaphoreHandle_t xButtonSemaphore; /* The queue used to send strings to the print task for display on the LCD. */ QueueHandle_t xPrintQueue; /* Newer library version. */ -extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigSetExpClk( unsigned long ulBase, + unsigned long ulUARTClk, + unsigned long ulBaud, + unsigned long ulConfig ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the clocks, UART and GPIO. */ - prvSetupHardware(); + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); - /* Create the semaphore used to wake the button handler task from the GPIO - ISR. */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); + /* Create the semaphore used to wake the button handler task from the GPIO + * ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) ); - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - /* Start the tasks defined within the file. */ - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - /* Start the scheduler. */ - vTaskStartScheduler(); + /* Start the scheduler. */ + vTaskStartScheduler(); - /* Will only get here if there was insufficient heap to start the - scheduler. */ + /* Will only get here if there was insufficient heap to start the + * scheduler. */ - return 0; + return 0; } /*-----------------------------------------------------------*/ -static void vCheckTask( void *pvParameters ) +static void vCheckTask( void * pvParameters ) { -portBASE_TYPE xErrorOccurred = pdFALSE; -TickType_t xLastExecutionTime; -const char *pcPassMessage = "PASS"; -const char *pcFailMessage = "FAIL"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. We do not write directly to the LCD, but instead - queue a message for display by the print task. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } + portBASE_TYPE xErrorOccurred = pdFALSE; + TickType_t xLastExecutionTime; + const char * pcPassMessage = "PASS"; + const char * pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + * works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + * never cleared again. We do not write directly to the LCD, but instead + * queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - /* Setup the push button. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); - GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); - IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); - GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - IntEnable( INT_GPIOC ); + /* Setup the push button. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOC ); + GPIODirModeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN ); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); - /* Enable the UART. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + /* Enable the UART. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_UART0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOA ); - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + * UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - /* We don't want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + /* We don't want to use the fifo. This is for test purposes to generate + * as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - /* Enable Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; - IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); - IntEnable( INT_UART0 ); + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); - /* Initialise the LCD> */ + /* Initialise the LCD> */ OSRAMInit( false ); - OSRAMStringDraw("www.FreeRTOS.org", 0, 0); - OSRAMStringDraw("LM3S811 demo", 16, 1); + OSRAMStringDraw( "www.FreeRTOS.org", 0, 0 ); + OSRAMStringDraw( "LM3S811 demo", 16, 1 ); } /*-----------------------------------------------------------*/ -static void vButtonHandlerTask( void *pvParameters ) +static void vButtonHandlerTask( void * pvParameters ) { -const char *pcInterruptMessage = "Int"; - - for( ;; ) - { - /* Wait for a GPIO interrupt to wake this task. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Start the Tx of the message on the UART. */ - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - pcNextChar = cMessage; - - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - - pcNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Queue a message for the print task to display on the LCD. */ - xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); - - /* Make sure we don't process bounces. */ - vTaskDelay( mainDEBOUNCE_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - } + const char * pcInterruptMessage = "Int"; + + for( ; ; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ) + { + } + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable( UART0_BASE, UART_INT_TX ); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } } /*-----------------------------------------------------------*/ -void vUART_ISR(void) +void vUART_ISR( void ) { -unsigned long ulStatus; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( *pcNextChar != NULL ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - pcNextChar++; - } - } + unsigned long ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != NULL ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + } } /*-----------------------------------------------------------*/ void vGPIO_ISR( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - /* Clear the interrupt. */ - GPIOPinIntClear( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + /* Clear the interrupt. */ + GPIOPinIntClear( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - /* Wake the button handler task. */ - xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + /* Wake the button handler task. */ + xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken ); + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void vPrintTask( void *pvParameters ) +static void vPrintTask( void * pvParameters ) { -char *pcMessage; -unsigned portBASE_TYPE uxLine = 0, uxRow = 0; - - for( ;; ) - { - /* Wait for a message to arrive. */ - xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message to the LCD. */ - uxRow++; - uxLine++; - OSRAMClear(); - OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); - } + char * pcMessage; + unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ; ; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01 ); + } } - diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/RegTest.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/RegTest.c index b586e787f96..67decbd4367 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/Sample-CLI-commands.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/Sample-CLI-commands.c index 7cec93be492..2b1330073d6 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/Sample-CLI-commands.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/Sample-CLI-commands.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.c index 121dd82b79c..4e5c71178b5 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.h index c3f7ae9b0ca..9308b9d5e4c 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.h +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/UARTCommandConsole.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/config/FreeRTOSConfig.h index 7dc4074e6aa..f881546b622 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-blinky.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-blinky.c index 5ffeccd0565..9debd95da44 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-full.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-full.c index 07e968a3422..ac29b69cd1c 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-full.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c index fc898ba7467..67634647549 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c index d30016443e3..b7c5ed68951 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h index 93072195267..ac3a0735bfd 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h index 1bbd07079b3..8f4cb190eb6 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h index cd466aec9ff..81babfbc207 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h index 0921050794e..a0fbe27d722 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c index be20e5693d8..b253f6e2122 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c index 7af0f79c6c1..0571629af4a 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c index 02afdb276a8..b7610e633df 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Config/FreeRTOSConfig.h index 447dc868a3e..b8866b443d2 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/GCC/RegTestsAsm.c b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/GCC/RegTestsAsm.c index 00582f8a71e..9522a872f21 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/GCC/RegTestsAsm.c +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/GCC/RegTestsAsm.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.c b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.c index a0f38f25c4b..60d05a6419d 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.c +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.h b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.h index 5b5dffe9785..260603083d9 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.h +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/RegTests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.c index d22febf0a02..bd00a879215 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.c +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.h b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.h index ec3f68f3427..24cdd99b367 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.h +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/app_main.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_blinky.c index c74f52f6964..f1567ad0f79 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_full.c index 4e9e752388c..f61378a7cbb 100644 --- a/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M0+_NUCLEO_L010RB_GCC_IAR/Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c index 3abe65c1ee2..cdad1036b54 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Atollic_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h index 5868a2b5d10..e3a1cbd6f52 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -93,6 +93,12 @@ to exclude the API function. */ header file. */ #define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +/* Disable the runtime check on the installation of the FreeRTOS handlers. The +port code that performs the check expects the handlers to be installed directly +into the vector table. However, XMC1000 has a ROM-based vector table, so it does +not contain the OS handler vectors directly. */ +#define configCHECK_HANDLER_INSTALLATION 0 + /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS standard names - or at least those used in the unmodified vector table. */ #define xPortPendSVHandler PendSV_Handler diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1100.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1100.c index da473014e6a..b948ffdb117 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1100.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1100.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c index d8fde20516d..8c88ae9308c 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1200.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1300.c index fc2d2c3ca48..ef04cce9d12 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1300.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/ParTest_XMC1300.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-blinky.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-blinky.c index 0e34d7fe02b..30a5bf011d1 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -70,32 +70,32 @@ #include "partest.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + * functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) /* The number of the LED that is toggled. */ -#define mainLED_TO_TOGGLE ( 0 ) +#define mainLED_TO_TOGGLE ( 0 ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -117,85 +117,86 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - vParTestToggleLED( mainLED_TO_TOGGLE ); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( mainLED_TO_TOGGLE ); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c index f542efeda5f..3568197cc61 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -91,28 +91,28 @@ #include "QueueSet.h" /* The period after which the check timer will expire provided no errors have -been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The base toggle rate used by the flash timers. Each toggle rate is a -multiple of this. */ -#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_PERIOD_MS ) + * multiple of this. */ +#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_PERIOD_MS ) /* The LED toggle by the check timer. */ -#define mainCHECK_LED ( 4 ) +#define mainCHECK_LED ( 4 ) /* The LED toggled each time the task implemented by the prvSemaphoreTakeTask() -function takes the semaphore that is given by the tick hook function. */ -#define mainSEMAPHORE_LED ( 3 ) + * function takes the semaphore that is given by the tick hook function. */ +#define mainSEMAPHORE_LED ( 3 ) /*-----------------------------------------------------------*/ @@ -120,8 +120,8 @@ function takes the semaphore that is given by the tick hook function. */ * Register check tasks, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly. */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); +extern void vRegTest1Task( void * pvParameters ); +extern void vRegTest2Task( void * pvParameters ); /* * The hardware only has a single LED. Simply toggle it. @@ -143,7 +143,7 @@ static void prvFlashTimerCallback( TimerHandle_t xTimer ); * The task that toggles an LED each time the semaphore 'given' by the tick * hook function (which is defined in main.c) is 'taken' in the task. */ -static void prvSemaphoreTakeTask( void *pvParameters ); +static void prvSemaphoreTakeTask( void * pvParameters ); /* * Called by main() to create the comprehensive test/demo application if @@ -154,210 +154,214 @@ void main_full( void ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /* The semaphore that is given by the tick hook function (defined in main.c) -and taken by the task implemented by the prvSemaphoreTakeTask() function. The -task toggles LED mainSEMAPHORE_LED each time the semaphore is taken. */ + * and taken by the task implemented by the prvSemaphoreTakeTask() function. The + * task toggles LED mainSEMAPHORE_LED each time the semaphore is taken. */ SemaphoreHandle_t xLEDSemaphore = NULL; /*-----------------------------------------------------------*/ void main_full( void ) { -TimerHandle_t xTimer = NULL; -unsigned long ulTimer; -const unsigned long ulTimersToCreate = 3L; + TimerHandle_t xTimer = NULL; + unsigned long ulTimer; + const unsigned long ulTimersToCreate = 3L; + /* The register test tasks are asm functions that don't use a stack. The -stack allocated just has to be large enough to hold the task context, and -for the additional required for the stack overflow checking to work (if -configured). */ -const size_t xRegTestStackSize = 25U; - - /* Create the standard demo tasks */ - vCreateBlockTimeTasks(); - vStartDynamicPriorityTasks(); - vStartCountingSemaphoreTasks(); - vStartRecursiveMutexTasks(); - vStartQueueOverwriteTask( tskIDLE_PRIORITY ); - vStartQueueSetTasks(); - - /* Create that is given from the tick hook function, and the task that - toggles an LED each time the semaphore is given. */ - vSemaphoreCreateBinary( xLEDSemaphore ); - xTaskCreate( prvSemaphoreTakeTask, /* Function that implements the task. */ - "Sem", /* Text name of the task. */ - configMINIMAL_STACK_SIZE, /* Stack allocated to the task (in words). */ - NULL, /* The task parameter is not used. */ - configMAX_PRIORITIES - 2, /* The priority of the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ - - /* Create the register test tasks as described at the top of this file. - These are naked functions that don't use any stack. A stack still has - to be allocated to hold the task context. */ - xTaskCreate( vRegTest1Task, /* Function that implements the task. */ - "Reg1", /* Text name of the task. */ - xRegTestStackSize, /* Stack allocated to the task. */ - NULL, /* The task parameter is not used. */ - tskIDLE_PRIORITY, /* The priority to assign to the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ - - xTaskCreate( vRegTest2Task, /* Function that implements the task. */ - "Reg2", /* Text name of the task. */ - xRegTestStackSize, /* Stack allocated to the task. */ - NULL, /* The task parameter is not used. */ - tskIDLE_PRIORITY, /* The priority to assign to the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ - - /* Create the three flash timers. */ - for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ ) - { - xTimer = xTimerCreate( "FlashTimer", /* A text name, purely to help debugging. */ - ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */ - prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xTimer != NULL ) - { - xTimerStart( xTimer, mainDONT_BLOCK ); - } - } - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* If the software timer was created successfully, start it. It won't - actually start running until the scheduler starts. A block time of - zero is used in this call, although any value could be used as the block - time will be ignored because the scheduler has not started yet. */ - if( xTimer != NULL ) - { - xTimerStart( xTimer, mainDONT_BLOCK ); - } - - /* Start the kernel. From here on, only tasks and interrupts will run. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then there - was insufficient FreeRTOS heap memory available for the idle and/or timer - tasks to be created. See the memory management section on the FreeRTOS web - site, or the FreeRTOS tutorial books for more details. */ - for( ;; ); + * stack allocated just has to be large enough to hold the task context, and + * for the additional required for the stack overflow checking to work (if + * configured). */ + const size_t xRegTestStackSize = 25U; + + /* Create the standard demo tasks */ + vCreateBlockTimeTasks(); + vStartDynamicPriorityTasks(); + vStartCountingSemaphoreTasks(); + vStartRecursiveMutexTasks(); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); + vStartQueueSetTasks(); + + /* Create that is given from the tick hook function, and the task that + * toggles an LED each time the semaphore is given. */ + vSemaphoreCreateBinary( xLEDSemaphore ); + xTaskCreate( prvSemaphoreTakeTask, /* Function that implements the task. */ + "Sem", /* Text name of the task. */ + configMINIMAL_STACK_SIZE, /* Stack allocated to the task (in words). */ + NULL, /* The task parameter is not used. */ + configMAX_PRIORITIES - 2, /* The priority of the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ + + /* Create the register test tasks as described at the top of this file. + * These are naked functions that don't use any stack. A stack still has + * to be allocated to hold the task context. */ + xTaskCreate( vRegTest1Task, /* Function that implements the task. */ + "Reg1", /* Text name of the task. */ + xRegTestStackSize, /* Stack allocated to the task. */ + NULL, /* The task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority to assign to the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ + + xTaskCreate( vRegTest2Task, /* Function that implements the task. */ + "Reg2", /* Text name of the task. */ + xRegTestStackSize, /* Stack allocated to the task. */ + NULL, /* The task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority to assign to the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ + + /* Create the three flash timers. */ + for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ ) + { + xTimer = xTimerCreate( "FlashTimer", /* A text name, purely to help debugging. */ + ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */ + prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xTimer != NULL ) + { + xTimerStart( xTimer, mainDONT_BLOCK ); + } + } + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* If the software timer was created successfully, start it. It won't + * actually start running until the scheduler starts. A block time of + * zero is used in this call, although any value could be used as the block + * time will be ignored because the scheduler has not started yet. */ + if( xTimer != NULL ) + { + xTimerStart( xTimer, mainDONT_BLOCK ); + } + + /* Start the kernel. From here on, only tasks and interrupts will run. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then there + * was insufficient FreeRTOS heap memory available for the idle and/or timer + * tasks to be created. See the memory management section on the FreeRTOS web + * site, or the FreeRTOS tutorial books for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ /* See the description at the top of this file. */ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo and test tasks to ensure that they are all still - running, and that none have detected an error. */ - if( xAreDynamicPriorityTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 0UL ); - } - - if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 1UL ); - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 2UL ); - } - - if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 3UL ); - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound |= ( 0x01UL << 4UL ); - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound |= ( 0x01UL << 5UL ); - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - if( xAreQueueSetTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 6UL ); - } - - if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 7UL ); - } - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - /* Have any errors been latched in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo and test tasks to ensure that they are all still + * running, and that none have detected an error. */ + if( xAreDynamicPriorityTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 0UL ); + } + + if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 1UL ); + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 2UL ); + } + + if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 3UL ); + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= ( 0x01UL << 4UL ); + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= ( 0x01UL << 5UL ); + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + if( xAreQueueSetTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 6UL ); + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 7UL ); + } + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Have any errors been latched in ulErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ -static void prvSemaphoreTakeTask( void *pvParameters ) +static void prvSemaphoreTakeTask( void * pvParameters ) { - configASSERT( xLEDSemaphore ); - - for( ;; ) - { - /* Wait to obtain the semaphore - which is given by the tick hook - function every 50ms. */ - xSemaphoreTake( xLEDSemaphore, portMAX_DELAY ); - vParTestToggleLED( mainSEMAPHORE_LED ); - } + configASSERT( xLEDSemaphore ); + + for( ; ; ) + { + /* Wait to obtain the semaphore - which is given by the tick hook + * function every 50ms. */ + xSemaphoreTake( xLEDSemaphore, portMAX_DELAY ); + vParTestToggleLED( mainSEMAPHORE_LED ); + } } /*-----------------------------------------------------------*/ static void prvFlashTimerCallback( TimerHandle_t xTimer ) { -unsigned long ulLED; + unsigned long ulLED; - /* This callback function is assigned to three separate software timers. - Each timer toggles a different LED. Obtain the number of the LED that - this timer is toggling. */ - ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer ); + /* This callback function is assigned to three separate software timers. + * Each timer toggles a different LED. Obtain the number of the LED that + * this timer is toggling. */ + ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer ); - /* Toggle the LED. */ - vParTestToggleLED( ulLED ); + /* Toggle the LED. */ + vParTestToggleLED( ulLED ); } - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c index 3d1a747b83b..2ccca66e118 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -54,8 +54,8 @@ #include "QueueSet.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -82,146 +82,149 @@ extern void SystemCoreClockUpdate( void ); int main( void ) { - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - SystemCoreClockUpdate(); - vParTestInitialise(); + SystemCoreClockUpdate(); + vParTestInitialise(); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). The code in this - tick hook implementation is for demonstration only - it has no real - purpose. It just gives a semaphore every 50ms. The semaphore unblocks a - task that then toggles an LED. Additionally, the call to - vQueueSetAccessQueueSetFromISR() is part of the "standard demo tasks" - functionality. */ - - /* The semaphore and associated task are not created when the simple blinky - demo is used. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - static unsigned long ulLastGiveTime = 0UL; - const unsigned long ulRate = 50UL / portTICK_PERIOD_MS; - extern SemaphoreHandle_t xLEDSemaphore; - - configASSERT( xLEDSemaphore ); - - if( ( xTaskGetTickCountFromISR() - ulLastGiveTime ) > ulRate ) - { - /* The second parameter is normally used to determine if a context - switch should be performed or not. In this case the function is - being performed from the tick hook, so the scheduler will make that - assessment before returning to a task anyway - so the parameter is - not needed and is just set to NULL. */ - xSemaphoreGiveFromISR( xLEDSemaphore, NULL ); - ulLastGiveTime += ulRate; - } - - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). The code in this + * tick hook implementation is for demonstration only - it has no real + * purpose. It just gives a semaphore every 50ms. The semaphore unblocks a + * task that then toggles an LED. Additionally, the call to + * vQueueSetAccessQueueSetFromISR() is part of the "standard demo tasks" + * functionality. */ + + /* The semaphore and associated task are not created when the simple blinky + * demo is used. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + static unsigned long ulLastGiveTime = 0UL; + const unsigned long ulRate = 50UL / portTICK_PERIOD_MS; + extern SemaphoreHandle_t xLEDSemaphore; + + configASSERT( xLEDSemaphore ); + + if( ( xTaskGetTickCountFromISR() - ulLastGiveTime ) > ulRate ) + { + /* The second parameter is normally used to determine if a context + * switch should be performed or not. In this case the function is + * being performed from the tick hook, so the scheduler will make that + * assessment before returning to a task anyway - so the parameter is + * not needed and is just set to NULL. */ + xSemaphoreGiveFromISR( xLEDSemaphore, NULL ); + ulLastGiveTime += ulRate; + } + + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ } /*-----------------------------------------------------------*/ #ifdef JUST_AN_EXAMPLE_ISR -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions - that end in "FromISR" can be called from an ISR. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} + void Dummy_IRQHandler( void ) + { + long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. A semaphore is used for this purpose. Note + * lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions + * that end in "FromISR" can be called from an ISR. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the current Running state task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + * internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + * portEND_SWITCHING_ISR() macro will result in a context switch being pended to + * ensure this interrupt returns directly to the unblocked, higher priority, + * task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + } #endif /* JUST_AN_EXAMPLE_ISR */ - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/FreeRTOSConfig.h index 2f6a9f1aa08..87c66963579 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.c index 74d0a46a2d8..8f9b18a4b21 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/RegTest.c b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/RegTest.c index d30016443e3..b7c5ed68951 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-blinky.c b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-blinky.c index 820c640a04f..cd1a8069ab7 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-full.c b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-full.c index 1c5c271c0ce..d04270fd48b 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-full.c +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main.c b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main.c index 435b1611a5c..dceda6c78ce 100644 --- a/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main.c +++ b/FreeRTOS/Demo/CORTEX_M0_LPC1114_LPCXpresso/RTOSDemo/Source/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/FreeRTOSConfig.h index 16842cc05ce..02d3a2fc3d0 100644 --- a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/ParTest.c b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/ParTest.c index c1d215fd849..2e64f513ade 100644 --- a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-blinky.c b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-blinky.c index e57c70ec77b..56de5f45d3c 100644 --- a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -73,29 +73,29 @@ #include "stm320518_eval.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + * functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -117,85 +117,86 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - vParTestToggleLED( LED1 ); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( LED1 ); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-full.c b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-full.c index 01c369cfc8d..e65dbe8bf39 100644 --- a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-full.c +++ b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -87,32 +87,32 @@ #include "stm320518_eval.h" /* The period after which the check timer will expire provided no errors have -been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The base toggle rate used by the flash timers. Each toggle rate is a -multiple of this. */ -#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_PERIOD_MS ) + * multiple of this. */ +#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_PERIOD_MS ) /* The LED toggle by the check timer. */ -#define mainCHECK_LED ( 3 ) +#define mainCHECK_LED ( 3 ) /*-----------------------------------------------------------*/ /* * Register check tasks, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly. */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); +extern void vRegTest1Task( void * pvParameters ); +extern void vRegTest2Task( void * pvParameters ); /* * The hardware only has a single LED. Simply toggle it. @@ -139,170 +139,174 @@ void main_full( void ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { -TimerHandle_t xTimer = NULL; -unsigned long ulTimer; -const unsigned long ulTimersToCreate = 3L; + TimerHandle_t xTimer = NULL; + unsigned long ulTimer; + const unsigned long ulTimersToCreate = 3L; + /* The register test tasks are asm functions that don't use a stack. The -stack allocated just has to be large enough to hold the task context, and -for the additional required for the stack overflow checking to work (if -configured). */ -const size_t xRegTestStackSize = 25U; - - /* Create the standard demo tasks */ - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartRecursiveMutexTasks(); - vStartDynamicPriorityTasks(); - - /* Create the register test tasks as described at the top of this file. - These are naked functions that don't use any stack. A stack still has - to be allocated to hold the task context. */ - xTaskCreate( vRegTest1Task, /* Function that implements the task. */ - "Reg1", /* Text name of the task. */ - xRegTestStackSize, /* Stack allocated to the task. */ - NULL, /* The task parameter is not used. */ - tskIDLE_PRIORITY, /* The priority to assign to the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ - - xTaskCreate( vRegTest2Task, /* Function that implements the task. */ - "Reg2", /* Text name of the task. */ - xRegTestStackSize, /* Stack allocated to the task. */ - NULL, /* The task parameter is not used. */ - tskIDLE_PRIORITY, /* The priority to assign to the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ - - /* Create the three flash timers. */ - for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ ) - { - xTimer = xTimerCreate( "FlashTimer", /* A text name, purely to help debugging. */ - ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */ - prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xTimer != NULL ) - { - xTimerStart( xTimer, mainDONT_BLOCK ); - } - } - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* If the software timer was created successfully, start it. It won't - actually start running until the scheduler starts. A block time of - zero is used in this call, although any value could be used as the block - time will be ignored because the scheduler has not started yet. */ - if( xTimer != NULL ) - { - xTimerStart( xTimer, mainDONT_BLOCK ); - } - - /* Start the kernel. From here on, only tasks and interrupts will run. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then there - was insufficient FreeRTOS heap memory available for the idle and/or timer - tasks to be created. See the memory management section on the FreeRTOS web - site, or the FreeRTOS tutorial books for more details. */ - for( ;; ); + * stack allocated just has to be large enough to hold the task context, and + * for the additional required for the stack overflow checking to work (if + * configured). */ + const size_t xRegTestStackSize = 25U; + + /* Create the standard demo tasks */ + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartRecursiveMutexTasks(); + vStartDynamicPriorityTasks(); + + /* Create the register test tasks as described at the top of this file. + * These are naked functions that don't use any stack. A stack still has + * to be allocated to hold the task context. */ + xTaskCreate( vRegTest1Task, /* Function that implements the task. */ + "Reg1", /* Text name of the task. */ + xRegTestStackSize, /* Stack allocated to the task. */ + NULL, /* The task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority to assign to the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ + + xTaskCreate( vRegTest2Task, /* Function that implements the task. */ + "Reg2", /* Text name of the task. */ + xRegTestStackSize, /* Stack allocated to the task. */ + NULL, /* The task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority to assign to the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ + + /* Create the three flash timers. */ + for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ ) + { + xTimer = xTimerCreate( "FlashTimer", /* A text name, purely to help debugging. */ + ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */ + prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xTimer != NULL ) + { + xTimerStart( xTimer, mainDONT_BLOCK ); + } + } + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* If the software timer was created successfully, start it. It won't + * actually start running until the scheduler starts. A block time of + * zero is used in this call, although any value could be used as the block + * time will be ignored because the scheduler has not started yet. */ + if( xTimer != NULL ) + { + xTimerStart( xTimer, mainDONT_BLOCK ); + } + + /* Start the kernel. From here on, only tasks and interrupts will run. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then there + * was insufficient FreeRTOS heap memory available for the idle and/or timer + * tasks to be created. See the memory management section on the FreeRTOS web + * site, or the FreeRTOS tutorial books for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ /* See the description at the top of this file. */ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo and test tasks to ensure that they are all still - running, and that none have detected an error. */ - if( xAreDynamicPriorityTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 0UL ); - } - - if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 1UL ); - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 2UL ); - } - - if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 3UL ); - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound |= ( 0x01UL << 4UL ); - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound |= ( 0x01UL << 5UL ); - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - /* Have any errors been latched in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo and test tasks to ensure that they are all still + * running, and that none have detected an error. */ + if( xAreDynamicPriorityTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 0UL ); + } + + if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 1UL ); + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 2UL ); + } + + if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 3UL ); + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= ( 0x01UL << 4UL ); + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= ( 0x01UL << 5UL ); + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Have any errors been latched in ulErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ static void prvFlashTimerCallback( TimerHandle_t xTimer ) { -unsigned long ulLED; + unsigned long ulLED; - /* This callback function is assigned to three separate software timers. - Each timer toggles a different LED. Obtain the number of the LED that - this timer is toggling. */ - ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer ); + /* This callback function is assigned to three separate software timers. + * Each timer toggles a different LED. Obtain the number of the LED that + * this timer is toggling. */ + ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer ); - /* Toggle the LED. */ - vParTestToggleLED( ulLED ); + /* Toggle the LED. */ + vParTestToggleLED( ulLED ); } - diff --git a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main.c b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main.c index 8ef2e5d12d8..49f2293565b 100644 --- a/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -52,8 +52,8 @@ #include "ParTest.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -65,7 +65,7 @@ or 0 to run the more comprehensive test and demo application. */ static void prvSetupHardware( void ); /* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. -main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ +* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ extern void main_blinky( void ); extern void main_full( void ); @@ -73,113 +73,116 @@ extern void main_full( void ); int main( void ) { - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - vParTestInitialise(); + vParTestInitialise(); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ } /*-----------------------------------------------------------*/ #ifdef JUST_AN_EXAMPLE_ISR -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions - that end in "FromISR" can be called from an ISR. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} + void Dummy_IRQHandler( void ) + { + long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. A semaphore is used for this purpose. Note + * lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions + * that end in "FromISR" can be called from an ISR. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the current Running state task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + * internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + * portEND_SWITCHING_ISR() macro will result in a context switch being pended to + * ensure this interrupt returns directly to the unblocked, higher priority, + * task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + } #endif /* JUST_AN_EXAMPLE_ISR */ - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h index a33a6d57252..d6e3ed498dc 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c index 482e67d665c..1a723787285 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c index 9420227f298..f7d1be225a3 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c index 6776e320967..c0c1f176245 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -52,9 +52,9 @@ #include "task.h" /* Hardware register addresses. */ -#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 ) -#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 ) -#define mainEC_INTERRUPT_CONTROL ( * ( volatile uint32_t * ) 0x4000FC18 ) +#define mainVTOR ( *( uint32_t * ) 0xE000ED08 ) +#define mainNVIC_AUX_ACTLR ( *( uint32_t * ) 0xE000E008 ) +#define mainEC_INTERRUPT_CONTROL ( *( volatile uint32_t * ) 0x4000FC18 ) /*-----------------------------------------------------------*/ @@ -67,193 +67,197 @@ static void prvSetupHardware( void ); * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1. * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0. */ -#if( configCREATE_LOW_POWER_DEMO == 1 ) +#if ( configCREATE_LOW_POWER_DEMO == 1 ) - extern void main_low_power( void ); + extern void main_low_power( void ); #else - extern void main_full( void ); + extern void main_full( void ); - /* Some of the tests and examples executed as part of the full demo make use - of the tick hook to call API functions from an interrupt context. */ - extern void vFullDemoTickHook( void ); +/* Some of the tests and examples executed as part of the full demo make use + * of the tick hook to call API functions from an interrupt context. */ + extern void vFullDemoTickHook( void ); #endif /* #if configCREATE_LOW_POWER_DEMO == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ /* The variable that is incremented to represent each LED toggle. On the -clicker hardware the LED state is set to the value of the least significant bit -of this variable. On other hardware, where an LED is not used, the LED just -keeps a count of the number of times the LED would otherwise have been toggled. -See the comments in main_low_power.c and main_full.c for information on the -expected LED toggle rate). */ + * clicker hardware the LED state is set to the value of the least significant bit + * of this variable. On other hardware, where an LED is not used, the LED just + * keeps a count of the number of times the LED would otherwise have been toggled. + * See the comments in main_low_power.c and main_full.c for information on the + * expected LED toggle rate). */ volatile uint32_t ulLED = 0; /*-----------------------------------------------------------*/ int main( void ) { - /* See http://www.freertos.org/Microchip_CEC1302_ARM_Cortex-M4F_Low_Power_Demo.html */ - - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The configCREATE_LOW_POWER_DEMO setting is described at the top - of this file. */ - #if( configCREATE_LOW_POWER_DEMO == 1 ) - { - /* The low power demo also demonstrated aggregated interrupts, so clear - the interrupt control register to disable the alternative NVIC vectors. */ - mainEC_INTERRUPT_CONTROL = pdFALSE; - - main_low_power(); - } - #else - { - /* The full demo also demonstrated disaggregated interrupts, so set the - interrupt control register to enable the alternative NVIC vectors. */ - mainEC_INTERRUPT_CONTROL = pdTRUE; - - main_full(); - } - #endif - - /* Should not get here. */ - return 0; + /* See http://www.freertos.org/Microchip_CEC1302_ARM_Cortex-M4F_Low_Power_Demo.html */ + + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The configCREATE_LOW_POWER_DEMO setting is described at the top + * of this file. */ + #if ( configCREATE_LOW_POWER_DEMO == 1 ) + { + /* The low power demo also demonstrated aggregated interrupts, so clear + * the interrupt control register to disable the alternative NVIC vectors. */ + mainEC_INTERRUPT_CONTROL = pdFALSE; + + main_low_power(); + } + #else + { + /* The full demo also demonstrated disaggregated interrupts, so set the + * interrupt control register to enable the alternative NVIC vectors. */ + mainEC_INTERRUPT_CONTROL = pdTRUE; + + main_full(); + } + #endif /* if ( configCREATE_LOW_POWER_DEMO == 1 ) */ + + /* Should not get here. */ + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -extern void system_set_ec_clock( void ); -extern unsigned long __Vectors[]; + extern void system_set_ec_clock( void ); + extern unsigned long __Vectors[]; - /* Disable M4 write buffer: fix CEC1302 hardware bug. */ - mainNVIC_AUX_ACTLR |= 0x07; + /* Disable M4 write buffer: fix CEC1302 hardware bug. */ + mainNVIC_AUX_ACTLR |= 0x07; - system_set_ec_clock(); + system_set_ec_clock(); - /* Assuming downloading code via the debugger - so ensure the hardware - is using the vector table downloaded with the application. */ - mainVTOR = ( uint32_t ) __Vectors; + /* Assuming downloading code via the debugger - so ensure the hardware + * is using the vector table downloaded with the application. */ + mainVTOR = ( uint32_t ) __Vectors; } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* The full demo includes tests that run from the tick hook. */ - #if( configCREATE_LOW_POWER_DEMO == 0 ) - { - /* Some of the tests and demo tasks executed by the full demo include - interaction from an interrupt - for which the tick interrupt is used - via the tick hook function. */ - vFullDemoTickHook(); - } - #endif + /* The full demo includes tests that run from the tick hook. */ + #if ( configCREATE_LOW_POWER_DEMO == 0 ) + { + /* Some of the tests and demo tasks executed by the full demo include + * interaction from an interrupt - for which the tick interrupt is used + * via the tick hook function. */ + vFullDemoTickHook(); + } + #endif } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c index 9b85da82024..346b13f56dc 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c index 3566e3592ca..8a2b05a68d9 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c index f8c47508a2e..feee7668cd2 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c index 0d0b4d3c39a..718844f39a5 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/FreeRTOSConfig.h index da54c2eac91..866bc2dbbe8 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/MikroC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/MikroC_Specific/RegTest.c index bc559cbf0ba..e3b8362adae 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/MikroC_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/MikroC_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main.c index 15bda9aab3e..9ccd54252e0 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -47,11 +47,11 @@ #include "task.h" /* Hardware register addresses and value. */ -#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 ) -#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 ) -#define mainEC_INTERRUPT_CONTROL ( * ( volatile uint32_t * ) 0x4000FC18 ) -#define mainMMCR_PCR_PROCESSOR_CLOCK_CONTROL ( * ( volatile uint32_t * )( 0x40080120 ) ) -#define mainCPU_CLOCK_DIVIDER 1 +#define mainVTOR ( *( uint32_t * ) 0xE000ED08 ) +#define mainNVIC_AUX_ACTLR ( *( uint32_t * ) 0xE000E008 ) +#define mainEC_INTERRUPT_CONTROL ( *( volatile uint32_t * ) 0x4000FC18 ) +#define mainMMCR_PCR_PROCESSOR_CLOCK_CONTROL ( *( volatile uint32_t * ) ( 0x40080120 ) ) +#define mainCPU_CLOCK_DIVIDER 1 /*-----------------------------------------------------------*/ @@ -64,186 +64,190 @@ static void prvSetupHardware( void ); * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1. * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0. */ -#if( configCREATE_LOW_POWER_DEMO == 1 ) +#if ( configCREATE_LOW_POWER_DEMO == 1 ) - extern void main_low_power( void ); + extern void main_low_power( void ); #else - extern void main_full( void ); + extern void main_full( void ); - /* Some of the tests and examples executed as part of the full demo make use - of the tick hook to call API functions from an interrupt context. */ - extern void vFullDemoTickHook( void ); +/* Some of the tests and examples executed as part of the full demo make use + * of the tick hook to call API functions from an interrupt context. */ + extern void vFullDemoTickHook( void ); #endif /* #if configCREATE_LOW_POWER_DEMO == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ /* The variable that is incremented to represent each LED toggle. On the -clicker hardware the LED state is set to the value of the least significant bit -of this variable. On other hardware, where an LED is not used, the LED just -keeps a count of the number of times the LED would otherwise have been toggled. -See the comments in main_low_power.c and main_full.c for information on the -expected LED toggle rate). */ + * clicker hardware the LED state is set to the value of the least significant bit + * of this variable. On other hardware, where an LED is not used, the LED just + * keeps a count of the number of times the LED would otherwise have been toggled. + * See the comments in main_low_power.c and main_full.c for information on the + * expected LED toggle rate). */ volatile uint32_t ulLED = 0; /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The configCREATE_LOW_POWER_DEMO setting is described at the top - of this file. */ - #if( configCREATE_LOW_POWER_DEMO == 1 ) - { - main_low_power(); - } - #else - { - main_full(); - } - #endif - - /* Should not get here. */ - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The configCREATE_LOW_POWER_DEMO setting is described at the top + * of this file. */ + #if ( configCREATE_LOW_POWER_DEMO == 1 ) + { + main_low_power(); + } + #else + { + main_full(); + } + #endif + + /* Should not get here. */ + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Disable M4 write buffer: fix MEC1322 hardware bug. */ - mainNVIC_AUX_ACTLR |= 0x07; + /* Disable M4 write buffer: fix MEC1322 hardware bug. */ + mainNVIC_AUX_ACTLR |= 0x07; - /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, - CPU=MCLK/Divider. */ - mainMMCR_PCR_PROCESSOR_CLOCK_CONTROL = mainCPU_CLOCK_DIVIDER; + /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, + * CPU=MCLK/Divider. */ + mainMMCR_PCR_PROCESSOR_CLOCK_CONTROL = mainCPU_CLOCK_DIVIDER; - /* Enable alternative NVIC vectors. */ - mainEC_INTERRUPT_CONTROL = pdTRUE; + /* Enable alternative NVIC vectors. */ + mainEC_INTERRUPT_CONTROL = pdTRUE; - /* Initialise the LED on the clicker board. */ - GPIO_Digital_Output( &GPIO_PORT_150_157, _GPIO_PINMASK_4 | _GPIO_PINMASK_5 ); - GPIO_OUTPUT_PIN_154_bit = 0; - GPIO_OUTPUT_PIN_155_bit = 0; + /* Initialise the LED on the clicker board. */ + GPIO_Digital_Output( &GPIO_PORT_150_157, _GPIO_PINMASK_4 | _GPIO_PINMASK_5 ); + GPIO_OUTPUT_PIN_154_bit = 0; + GPIO_OUTPUT_PIN_155_bit = 0; } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* The full demo includes tests that run from the tick hook. */ - #if( configCREATE_LOW_POWER_DEMO == 0 ) - { - /* Some of the tests and demo tasks executed by the full demo include - interaction from an interrupt - for which the tick interrupt is used - via the tick hook function. */ - vFullDemoTickHook(); - } - #endif + /* The full demo includes tests that run from the tick hook. */ + #if ( configCREATE_LOW_POWER_DEMO == 0 ) + { + /* Some of the tests and demo tasks executed by the full demo include + * interaction from an interrupt - for which the tick interrupt is used + * via the tick hook function. */ + vFullDemoTickHook(); + } + #endif } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.c index 99006b97198..8ea7f5c99d8 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/main_full.c index 88fe4e1438f..5d48a47f8c8 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_full/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/low_power_tick_config.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/low_power_tick_config.c index e21486bdb3c..c4ab6a97e9d 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/low_power_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/low_power_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/main_low_power.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/main_low_power.c index e4aa0a84808..a1c47d5a02f 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/main_low_power.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_MikroC/main_low_power/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h index 92c3851a670..29b7c47de25 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/main.c index 309c3a164da..626794a19e3 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC_MEC_17xx_51xx_Keil_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -44,17 +44,17 @@ #include "queue.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 1000UL ) ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 1000UL ) ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH_IN_ITEMS ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH_IN_ITEMS ( 1 ) /*-----------------------------------------------------------*/ @@ -67,20 +67,20 @@ static void prvSetupHardware( void ); * Simple routine to print a string to ITM for viewing in the Keil serial debug * viewer. */ -static void prvITMPrintString( const char *pcString ); +static void prvITMPrintString( const char * pcString ); /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /*-----------------------------------------------------------*/ /* configSUPPORT_STATIC_ALLOCATION is 1 and configSUPPORT_DYNAMIC_ALLOCATION is -0 so the queue structure and the queue storage area can only be statically -allocated. See http://TBD for more information. -The queue storage area is dimensioned to hold just one 32-bit value. */ + * 0 so the queue structure and the queue storage area can only be statically + * allocated. See http://TBD for more information. + * The queue storage area is dimensioned to hold just one 32-bit value. */ static StaticQueue_t xStaticQueue; static uint8_t ucQueueStorageArea[ mainQUEUE_LENGTH_IN_ITEMS * sizeof( uint32_t ) ]; @@ -88,8 +88,8 @@ static uint8_t ucQueueStorageArea[ mainQUEUE_LENGTH_IN_ITEMS * sizeof( uint32_t static QueueHandle_t xQueue = NULL; /* configSUPPORT_STATIC_ALLOCATION is 1 and configSUPPORT_DYNAMIC_ALLOCATION is -0 so the task structure and the stacks used by the tasks can only be statically -allocated. See http://TBD for more information. */ + * 0 so the task structure and the stacks used by the tasks can only be statically + * allocated. See http://TBD for more information. */ StaticTask_t xRxTCBBuffer, xTxTCBBuffer; static StackType_t uxRxStackBuffer[ configMINIMAL_STACK_SIZE ], uxTxStackBuffer[ configMINIMAL_STACK_SIZE ]; @@ -97,170 +97,179 @@ static StackType_t uxRxStackBuffer[ configMINIMAL_STACK_SIZE ], uxTxStackBuffer[ int main( void ) { - /* Set up the hardware ready to run the demo. */ - prvSetupHardware(); - prvITMPrintString( "Starting\r\n" ); - - /* Create the queue. xQueueCreateStatic() has two more parameters than the - xQueueCreate() function. The first new parameter is a pointer to the - pre-allocated queue storage area. The second new parameter is a pointer to - the StaticQueue_t structure that will hold the queue state information in - an anonymous way. */ - xQueue = xQueueCreateStatic( mainQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */ - sizeof( uint32_t ), /* The size of each item. */ - ucQueueStorageArea, /* The buffer used to hold items within the queue. */ - &xStaticQueue ); /* The static queue structure that will hold the state of the queue. */ - - /* Create the two tasks as described in the comments at the top of this - file. */ - xTaskCreateStatic( prvQueueReceiveTask, /* Function that implements the task. */ - "Rx", /* Human readable name for the task. */ - configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ - NULL, /* Parameter to pass into the task. */ - mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority of the task. */ - &( uxRxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ - &xRxTCBBuffer ); /* The variable that will hold that task's TCB. */ - - xTaskCreateStatic( prvQueueSendTask, /* Function that implements the task. */ - "Tx", /* Human readable name for the task. */ - configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ - NULL, /* Parameter to pass into the task. */ - mainQUEUE_SEND_TASK_PRIORITY, /* The priority of the task. */ - &( uxTxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ - &xTxTCBBuffer ); /* The variable that will hold that task's TCB. */ - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If dynamic memory allocation was used then the following code line would - be reached if there was insufficient heap memory available to create either - the timer or idle tasks. As this project is using static memory allocation - then the following line should never be reached. */ - for( ;; ); + /* Set up the hardware ready to run the demo. */ + prvSetupHardware(); + prvITMPrintString( "Starting\r\n" ); + + /* Create the queue. xQueueCreateStatic() has two more parameters than the + * xQueueCreate() function. The first new parameter is a pointer to the + * pre-allocated queue storage area. The second new parameter is a pointer to + * the StaticQueue_t structure that will hold the queue state information in + * an anonymous way. */ + xQueue = xQueueCreateStatic( mainQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */ + sizeof( uint32_t ), /* The size of each item. */ + ucQueueStorageArea, /* The buffer used to hold items within the queue. */ + &xStaticQueue ); /* The static queue structure that will hold the state of the queue. */ + + /* Create the two tasks as described in the comments at the top of this + * file. */ + xTaskCreateStatic( prvQueueReceiveTask, /* Function that implements the task. */ + "Rx", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ + NULL, /* Parameter to pass into the task. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority of the task. */ + &( uxRxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ + &xRxTCBBuffer ); /* The variable that will hold that task's TCB. */ + + xTaskCreateStatic( prvQueueSendTask, /* Function that implements the task. */ + "Tx", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ + NULL, /* Parameter to pass into the task. */ + mainQUEUE_SEND_TASK_PRIORITY, /* The priority of the task. */ + &( uxTxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ + &xTxTCBBuffer ); /* The variable that will hold that task's TCB. */ + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If dynamic memory allocation was used then the following code line would + * be reached if there was insufficient heap memory available to create either + * the timer or idle tasks. As this project is using static memory allocation + * then the following line should never be reached. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - /* Output a string in lieu of using an LED. */ - prvITMPrintString( "Toggle!\r\n" ); - } - } + unsigned long ulReceivedValue; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + /* Output a string in lieu of using an LED. */ + prvITMPrintString( "Toggle!\r\n" ); + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - SystemInit(); - SystemCoreClockUpdate(); + SystemInit(); + SystemCoreClockUpdate(); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this - function will automatically get called if a task overflows its stack. */ - ( void ) pxTask; - ( void ) pcTaskName; - for( ;; ); + /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this + * function will automatically get called if a task overflows its stack. */ + ( void ) pxTask; + ( void ) pcTaskName; + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ -static void prvITMPrintString( const char *pcString ) +static void prvITMPrintString( const char * pcString ) { - while( *pcString != 0x00 ) - { - ITM_SendChar( *pcString ); - pcString++; - } + while( *pcString != 0x00 ) + { + ITM_SendChar( *pcString ); + pcString++; + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h index f70d68fbe2f..fcf6bf2e888 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main.c index c88c8bd3c82..4e4d5aae3ea 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -62,8 +62,8 @@ #include "task.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -83,111 +83,118 @@ extern void main_full( void ); int main( void ) { - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - configCONFIGURE_LED(); + configCONFIGURE_LED(); - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_SetPriorityGrouping( 0 ); + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ } /*-----------------------------------------------------------*/ #ifdef JUST_AN_EXAMPLE_ISR -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} + void Dummy_IRQHandler( void ) + { + long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. A semaphore is used for this purpose. Note + * lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the current Running state task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + * internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + * portEND_SWITCHING_ISR() macro will result in a context switch being pended to + * ensure this interrupt returns directly to the unblocked, higher priority, + * task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + } #endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_blinky.c index 9840f5aad2c..5994c0986fe 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -70,30 +70,30 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + * functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -110,85 +110,86 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - configTOGGLE_LED(); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + configTOGGLE_LED(); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c index e68a8bc5213..1cc02a43909 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -83,24 +83,24 @@ #include "recmutex.h" /* Priorities for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /*-----------------------------------------------------------*/ @@ -114,514 +114,518 @@ static void prvCheckTimerCallback( TimerHandle_t xTimer ); * of the FPU registers, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly file. */ -static void prvRegTest1Task( void *pvParameters ) __attribute__((naked)); -static void prvRegTest2Task( void *pvParameters ) __attribute__((naked)); +static void prvRegTest1Task( void * pvParameters ) __attribute__( ( naked ) ); +static void prvRegTest2Task( void * pvParameters ) __attribute__( ( naked ) ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { -TimerHandle_t xCheckTimer = NULL; - - /* Start all the other standard demo/test tasks. The have not particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( prvRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + TimerHandle_t xCheckTimer = NULL; + + /* Start all the other standard demo/test tasks. The have not particular + * functionality, but do demonstrate how to use the FreeRTOS API and test the + * kernel port. */ + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + * file */ + xTaskCreate( prvRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - /* Have any errors been latch in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ /* This is a naked function. */ -static void prvRegTest1Task( void *pvParameters ) +static void prvRegTest1Task( void * pvParameters ) { - __asm volatile - ( - " /* Fill the core registers with known values. */ \n" - " mov r0, #100 \n" - " mov r1, #101 \n" - " mov r2, #102 \n" - " mov r3, #103 \n" - " mov r4, #104 \n" - " mov r5, #105 \n" - " mov r6, #106 \n" - " mov r7, #107 \n" - " mov r8, #108 \n" - " mov r9, #109 \n" - " mov r10, #110 \n" - " mov r11, #111 \n" - " mov r12, #112 \n" - " \n" - " /* Fill the VFP registers with known values. */ \n" - " vmov d0, r0, r1 \n" - " vmov d1, r2, r3 \n" - " vmov d2, r4, r5 \n" - " vmov d3, r6, r7 \n" - " vmov d4, r8, r9 \n" - " vmov d5, r10, r11 \n" - " vmov d6, r0, r1 \n" - " vmov d7, r2, r3 \n" - " vmov d8, r4, r5 \n" - " vmov d9, r6, r7 \n" - " vmov d10, r8, r9 \n" - " vmov d11, r10, r11 \n" - " vmov d12, r0, r1 \n" - " vmov d13, r2, r3 \n" - " vmov d14, r4, r5 \n" - " vmov d15, r6, r7 \n" - " \n" - "reg1_loop: \n" - " /* Check all the VFP registers still contain the values set above.\n" - " First save registers that are clobbered by the test. */ \n" - " push { r0-r1 } \n" - " \n" - " vmov r0, r1, d0 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d1 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d2 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d3 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d4 \n" - " cmp r0, #108 \n" - " bne reg1_error_loopf \n" - " cmp r1, #109 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d5 \n" - " cmp r0, #110 \n" - " bne reg1_error_loopf \n" - " cmp r1, #111 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d6 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d7 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d8 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d9 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d10 \n" - " cmp r0, #108 \n" - " bne reg1_error_loopf \n" - " cmp r1, #109 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d11 \n" - " cmp r0, #110 \n" - " bne reg1_error_loopf \n" - " cmp r1, #111 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d12 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d13 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d14 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d15 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " \n" - " /* Restore the registers that were clobbered by the test. */\n" - " pop {r0-r1} \n" - " \n" - " /* VFP register test passed. Jump to the core register test. */\n" - " b reg1_loopf_pass \n" - " \n" - "reg1_error_loopf: \n" - " /* If this line is hit then a VFP register value was found to be\n" - " incorrect. */ \n" - " b reg1_error_loopf \n" - " \n" - "reg1_loopf_pass: \n" - " \n" - " cmp r0, #100 \n" - " bne reg1_error_loop \n" - " cmp r1, #101 \n" - " bne reg1_error_loop \n" - " cmp r2, #102 \n" - " bne reg1_error_loop \n" - " cmp r3, #103 \n" - " bne reg1_error_loop \n" - " cmp r4, #104 \n" - " bne reg1_error_loop \n" - " cmp r5, #105 \n" - " bne reg1_error_loop \n" - " cmp r6, #106 \n" - " bne reg1_error_loop \n" - " cmp r7, #107 \n" - " bne reg1_error_loop \n" - " cmp r8, #108 \n" - " bne reg1_error_loop \n" - " cmp r9, #109 \n" - " bne reg1_error_loop \n" - " cmp r10, #110 \n" - " bne reg1_error_loop \n" - " cmp r11, #111 \n" - " bne reg1_error_loop \n" - " cmp r12, #112 \n" - " bne reg1_error_loop \n" - " \n" - " /* Everything passed, increment the loop counter. */ \n" - " push { r0-r1 } \n" - " ldr r0, =ulRegTest1LoopCounter \n" - " ldr r1, [r0] \n" - " adds r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r0-r1 } \n" - " \n" - " /* Start again. */ \n" - " b reg1_loop \n" - " \n" - "reg1_error_loop: \n" - " /* If this line is hit then there was an error in a core register value.\n" - " The loop ensures the loop counter stops incrementing. */\n" - " b reg1_error_loop \n" - " nop " - ); + __asm volatile + ( + " /* Fill the core registers with known values. */ \n" + " mov r0, #100 \n" + " mov r1, #101 \n" + " mov r2, #102 \n" + " mov r3, #103 \n" + " mov r4, #104 \n" + " mov r5, #105 \n" + " mov r6, #106 \n" + " mov r7, #107 \n" + " mov r8, #108 \n" + " mov r9, #109 \n" + " mov r10, #110 \n" + " mov r11, #111 \n" + " mov r12, #112 \n" + " \n" + " /* Fill the VFP registers with known values. */ \n" + " vmov d0, r0, r1 \n" + " vmov d1, r2, r3 \n" + " vmov d2, r4, r5 \n" + " vmov d3, r6, r7 \n" + " vmov d4, r8, r9 \n" + " vmov d5, r10, r11 \n" + " vmov d6, r0, r1 \n" + " vmov d7, r2, r3 \n" + " vmov d8, r4, r5 \n" + " vmov d9, r6, r7 \n" + " vmov d10, r8, r9 \n" + " vmov d11, r10, r11 \n" + " vmov d12, r0, r1 \n" + " vmov d13, r2, r3 \n" + " vmov d14, r4, r5 \n" + " vmov d15, r6, r7 \n" + " \n" + "reg1_loop: \n" + " /* Check all the VFP registers still contain the values set above.\n" + " First save registers that are clobbered by the test. */ \n" + " push { r0-r1 } \n" + " \n" + " vmov r0, r1, d0 \n" + " cmp r0, #100 \n" + " bne reg1_error_loopf \n" + " cmp r1, #101 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d1 \n" + " cmp r0, #102 \n" + " bne reg1_error_loopf \n" + " cmp r1, #103 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d2 \n" + " cmp r0, #104 \n" + " bne reg1_error_loopf \n" + " cmp r1, #105 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d3 \n" + " cmp r0, #106 \n" + " bne reg1_error_loopf \n" + " cmp r1, #107 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d4 \n" + " cmp r0, #108 \n" + " bne reg1_error_loopf \n" + " cmp r1, #109 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d5 \n" + " cmp r0, #110 \n" + " bne reg1_error_loopf \n" + " cmp r1, #111 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d6 \n" + " cmp r0, #100 \n" + " bne reg1_error_loopf \n" + " cmp r1, #101 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d7 \n" + " cmp r0, #102 \n" + " bne reg1_error_loopf \n" + " cmp r1, #103 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d8 \n" + " cmp r0, #104 \n" + " bne reg1_error_loopf \n" + " cmp r1, #105 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d9 \n" + " cmp r0, #106 \n" + " bne reg1_error_loopf \n" + " cmp r1, #107 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d10 \n" + " cmp r0, #108 \n" + " bne reg1_error_loopf \n" + " cmp r1, #109 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d11 \n" + " cmp r0, #110 \n" + " bne reg1_error_loopf \n" + " cmp r1, #111 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d12 \n" + " cmp r0, #100 \n" + " bne reg1_error_loopf \n" + " cmp r1, #101 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d13 \n" + " cmp r0, #102 \n" + " bne reg1_error_loopf \n" + " cmp r1, #103 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d14 \n" + " cmp r0, #104 \n" + " bne reg1_error_loopf \n" + " cmp r1, #105 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d15 \n" + " cmp r0, #106 \n" + " bne reg1_error_loopf \n" + " cmp r1, #107 \n" + " bne reg1_error_loopf \n" + " \n" + " /* Restore the registers that were clobbered by the test. */\n" + " pop {r0-r1} \n" + " \n" + " /* VFP register test passed. Jump to the core register test. */\n" + " b reg1_loopf_pass \n" + " \n" + "reg1_error_loopf: \n" + " /* If this line is hit then a VFP register value was found to be\n" + " incorrect. */ \n" + " b reg1_error_loopf \n" + " \n" + "reg1_loopf_pass: \n" + " \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " cmp r8, #108 \n" + " bne reg1_error_loop \n" + " cmp r9, #109 \n" + " bne reg1_error_loop \n" + " cmp r10, #110 \n" + " bne reg1_error_loop \n" + " cmp r11, #111 \n" + " bne reg1_error_loop \n" + " cmp r12, #112 \n" + " bne reg1_error_loop \n" + " \n" + " /* Everything passed, increment the loop counter. */ \n" + " push { r0-r1 } \n" + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r0-r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg1_loop \n" + " \n" + "reg1_error_loop: \n" + " /* If this line is hit then there was an error in a core register value.\n" + " The loop ensures the loop counter stops incrementing. */\n" + " b reg1_error_loop \n" + " nop " + ); } /*-----------------------------------------------------------*/ /* This is a naked function. */ -static void prvRegTest2Task( void *pvParameters ) +static void prvRegTest2Task( void * pvParameters ) { - __asm volatile - ( - " /* Set all the core registers to known values. */ \n" - " mov r0, #-1 \n" - " mov r1, #1 \n" - " mov r2, #2 \n" - " mov r3, #3 \n" - " mov r4, #4 \n" - " mov r5, #5 \n" - " mov r6, #6 \n" - " mov r7, #7 \n" - " mov r8, #8 \n" - " mov r9, #9 \n" - " mov r10, #10 \n" - " mov r11, #11 \n" - " mov r12, #12 \n" - " \n" - " /* Set all the VFP to known values. */ \n" - " vmov d0, r0, r1 \n" - " vmov d1, r2, r3 \n" - " vmov d2, r4, r5 \n" - " vmov d3, r6, r7 \n" - " vmov d4, r8, r9 \n" - " vmov d5, r10, r11 \n" - " vmov d6, r0, r1 \n" - " vmov d7, r2, r3 \n" - " vmov d8, r4, r5 \n" - " vmov d9, r6, r7 \n" - " vmov d10, r8, r9 \n" - " vmov d11, r10, r11 \n" - " vmov d12, r0, r1 \n" - " vmov d13, r2, r3 \n" - " vmov d14, r4, r5 \n" - " vmov d15, r6, r7 \n" - " \n" - "reg2_loop: \n" - " \n" - " /* Check all the VFP registers still contain the values set above.\n" - " First save registers that are clobbered by the test. */ \n" - " push { r0-r1 } \n" - " \n" - " vmov r0, r1, d0 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d1 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d2 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d3 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d4 \n" - " cmp r0, #8 \n" - " bne reg2_error_loopf \n" - " cmp r1, #9 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d5 \n" - " cmp r0, #10 \n" - " bne reg2_error_loopf \n" - " cmp r1, #11 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d6 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d7 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d8 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d9 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d10 \n" - " cmp r0, #8 \n" - " bne reg2_error_loopf \n" - " cmp r1, #9 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d11 \n" - " cmp r0, #10 \n" - " bne reg2_error_loopf \n" - " cmp r1, #11 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d12 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d13 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d14 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d15 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " \n" - " /* Restore the registers that were clobbered by the test. */\n" - " pop {r0-r1} \n" - " \n" - " /* VFP register test passed. Jump to the core register test. */\n" - " b reg2_loopf_pass \n" - " \n" - "reg2_error_loopf: \n" - " /* If this line is hit then a VFP register value was found to be\n" - " incorrect. */ \n" - " b reg2_error_loopf \n" - " \n" - "reg2_loopf_pass: \n" - " \n" - " cmp r0, #-1 \n" - " bne reg2_error_loop \n" - " cmp r1, #1 \n" - " bne reg2_error_loop \n" - " cmp r2, #2 \n" - " bne reg2_error_loop \n" - " cmp r3, #3 \n" - " bne reg2_error_loop \n" - " cmp r4, #4 \n" - " bne reg2_error_loop \n" - " cmp r5, #5 \n" - " bne reg2_error_loop \n" - " cmp r6, #6 \n" - " bne reg2_error_loop \n" - " cmp r7, #7 \n" - " bne reg2_error_loop \n" - " cmp r8, #8 \n" - " bne reg2_error_loop \n" - " cmp r9, #9 \n" - " bne reg2_error_loop \n" - " cmp r10, #10 \n" - " bne reg2_error_loop \n" - " cmp r11, #11 \n" - " bne reg2_error_loop \n" - " cmp r12, #12 \n" - " bne reg2_error_loop \n" - " \n" - " /* Increment the loop counter to indicate this test is still functioning\n" - " correctly. */ \n" - " push { r0-r1 } \n" - " ldr r0, =ulRegTest2LoopCounter \n" - " ldr r1, [r0] \n" - " adds r1, r1, #1 \n" - " str r1, [r0] \n" - " \n" - " /* Yield to increase test coverage. */ \n" - " movs r0, #0x01 \n" - " ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */ - " lsl r0, #28 \n" /* Shift to PendSV bit */ - " str r0, [r1] \n" - " dsb \n" - " pop { r0-r1 } \n" - " \n" - " /* Start again. */ \n" - " b reg2_loop \n" - " \n" - "reg2_error_loop: \n" - " /* If this line is hit then there was an error in a core register value.\n" - " This loop ensures the loop counter variable stops incrementing. */\n" - " b reg2_error_loop \n" - " nop \n" - ); + __asm volatile + ( + " /* Set all the core registers to known values. */ \n" + " mov r0, #-1 \n" + " mov r1, #1 \n" + " mov r2, #2 \n" + " mov r3, #3 \n" + " mov r4, #4 \n" + " mov r5, #5 \n" + " mov r6, #6 \n" + " mov r7, #7 \n" + " mov r8, #8 \n" + " mov r9, #9 \n" + " mov r10, #10 \n" + " mov r11, #11 \n" + " mov r12, #12 \n" + " \n" + " /* Set all the VFP to known values. */ \n" + " vmov d0, r0, r1 \n" + " vmov d1, r2, r3 \n" + " vmov d2, r4, r5 \n" + " vmov d3, r6, r7 \n" + " vmov d4, r8, r9 \n" + " vmov d5, r10, r11 \n" + " vmov d6, r0, r1 \n" + " vmov d7, r2, r3 \n" + " vmov d8, r4, r5 \n" + " vmov d9, r6, r7 \n" + " vmov d10, r8, r9 \n" + " vmov d11, r10, r11 \n" + " vmov d12, r0, r1 \n" + " vmov d13, r2, r3 \n" + " vmov d14, r4, r5 \n" + " vmov d15, r6, r7 \n" + " \n" + "reg2_loop: \n" + " \n" + " /* Check all the VFP registers still contain the values set above.\n" + " First save registers that are clobbered by the test. */ \n" + " push { r0-r1 } \n" + " \n" + " vmov r0, r1, d0 \n" + " cmp r0, #-1 \n" + " bne reg2_error_loopf \n" + " cmp r1, #1 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d1 \n" + " cmp r0, #2 \n" + " bne reg2_error_loopf \n" + " cmp r1, #3 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d2 \n" + " cmp r0, #4 \n" + " bne reg2_error_loopf \n" + " cmp r1, #5 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d3 \n" + " cmp r0, #6 \n" + " bne reg2_error_loopf \n" + " cmp r1, #7 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d4 \n" + " cmp r0, #8 \n" + " bne reg2_error_loopf \n" + " cmp r1, #9 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d5 \n" + " cmp r0, #10 \n" + " bne reg2_error_loopf \n" + " cmp r1, #11 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d6 \n" + " cmp r0, #-1 \n" + " bne reg2_error_loopf \n" + " cmp r1, #1 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d7 \n" + " cmp r0, #2 \n" + " bne reg2_error_loopf \n" + " cmp r1, #3 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d8 \n" + " cmp r0, #4 \n" + " bne reg2_error_loopf \n" + " cmp r1, #5 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d9 \n" + " cmp r0, #6 \n" + " bne reg2_error_loopf \n" + " cmp r1, #7 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d10 \n" + " cmp r0, #8 \n" + " bne reg2_error_loopf \n" + " cmp r1, #9 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d11 \n" + " cmp r0, #10 \n" + " bne reg2_error_loopf \n" + " cmp r1, #11 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d12 \n" + " cmp r0, #-1 \n" + " bne reg2_error_loopf \n" + " cmp r1, #1 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d13 \n" + " cmp r0, #2 \n" + " bne reg2_error_loopf \n" + " cmp r1, #3 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d14 \n" + " cmp r0, #4 \n" + " bne reg2_error_loopf \n" + " cmp r1, #5 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d15 \n" + " cmp r0, #6 \n" + " bne reg2_error_loopf \n" + " cmp r1, #7 \n" + " bne reg2_error_loopf \n" + " \n" + " /* Restore the registers that were clobbered by the test. */\n" + " pop {r0-r1} \n" + " \n" + " /* VFP register test passed. Jump to the core register test. */\n" + " b reg2_loopf_pass \n" + " \n" + "reg2_error_loopf: \n" + " /* If this line is hit then a VFP register value was found to be\n" + " incorrect. */ \n" + " b reg2_error_loopf \n" + " \n" + "reg2_loopf_pass: \n" + " \n" + " cmp r0, #-1 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " cmp r8, #8 \n" + " bne reg2_error_loop \n" + " cmp r9, #9 \n" + " bne reg2_error_loop \n" + " cmp r10, #10 \n" + " bne reg2_error_loop \n" + " cmp r11, #11 \n" + " bne reg2_error_loop \n" + " cmp r12, #12 \n" + " bne reg2_error_loop \n" + " \n" + " /* Increment the loop counter to indicate this test is still functioning\n" + " correctly. */ \n" + " push { r0-r1 } \n" + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n"/*NVIC_INT_CTRL */ + " lsl r0, #28 \n"/* Shift to PendSV bit */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0-r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg2_loop \n" + " \n" + "reg2_error_loop: \n" + " /* If this line is hit then there was an error in a core register value.\n" + " This loop ensures the loop counter variable stops incrementing. */\n" + " b reg2_error_loop \n" + " nop \n" + ); } diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h index ee26f774d79..539760ac729 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c index 900dbdf0619..13a72681040 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -59,8 +59,8 @@ #include "QueueOverwrite.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /*-----------------------------------------------------------*/ @@ -80,122 +80,129 @@ extern void main_full( void ); int main( void ) { - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - configCONFIGURE_LED(); + configCONFIGURE_LED(); - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_SetPriorityGrouping( 0 ); + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - - /* Test the ISR safe queue overwrite functions. */ - vQueueOverwritePeriodicISRDemo(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ + + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + + /* Test the ISR safe queue overwrite functions. */ + vQueueOverwritePeriodicISRDemo(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ } /*-----------------------------------------------------------*/ #ifdef JUST_AN_EXAMPLE_ISR -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} + void Dummy_IRQHandler( void ) + { + long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. A semaphore is used for this purpose. Note + * lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the current Running state task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + * internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + * portEND_SWITCHING_ISR() macro will result in a context switch being pended to + * ensure this interrupt returns directly to the unblocked, higher priority, + * task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + } #endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c index 9840f5aad2c..5994c0986fe 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -70,30 +70,30 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + * functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -110,85 +110,86 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - configTOGGLE_LED(); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + configTOGGLE_LED(); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c index 34d02cc8472..2c290d7aba2 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -85,24 +85,24 @@ #include "QueueOverwrite.h" /* Priorities for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /*-----------------------------------------------------------*/ @@ -116,144 +116,147 @@ static void prvCheckTimerCallback( TimerHandle_t xTimer ); * of the FPU registers, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly file. */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); +extern void vRegTest1Task( void * pvParameters ); +extern void vRegTest2Task( void * pvParameters ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { -TimerHandle_t xCheckTimer = NULL; - - /* Start all the other standard demo/test tasks. The have not particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartQueueSetTasks(); - vStartQueueOverwriteTask( tskIDLE_PRIORITY ); - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + TimerHandle_t xCheckTimer = NULL; + + /* Start all the other standard demo/test tasks. The have not particular + * functionality, but do demonstrate how to use the FreeRTOS API and test the + * kernel port. */ + vStartQueueSetTasks(); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + * file */ + xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreQueueSetTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - /* Have any errors been latch in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreQueueSetTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h index 709a9415005..09b12ed166f 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c index bc1813c1192..7aacf425da4 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c index 92609f51783..baea7446573 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -35,9 +35,9 @@ * This file implements the code that is not demo specific, including the * hardware setup and FreeRTOS hook functions. * - * + * * Additional code: - * + * * This demo does not contain a non-kernel interrupt service routine that * can be used as an example for application writers to use as a reference. * Therefore, the framework of a dummy (not installed) handler is provided @@ -55,8 +55,8 @@ #include "task.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -65,9 +65,9 @@ or 0 to run the more comprehensive test and demo application. */ */ static void prvSetupHardware( void ); -/* +/* * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ extern void main_blinky( void ); extern void main_full( void ); @@ -76,111 +76,118 @@ extern void main_full( void ); int main( void ) { - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - configCONFIGURE_LED(); - - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_SetPriorityGrouping( 0 ); + configCONFIGURE_LED(); + + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ } /*-----------------------------------------------------------*/ #ifdef JUST_AN_EXAMPLE_ISR -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} + void Dummy_IRQHandler( void ) + { + long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. A semaphore is used for this purpose. Note + * lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the current Running state task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + * internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + * portEND_SWITCHING_ISR() macro will result in a context switch being pended to + * ensure this interrupt returns directly to the unblocked, higher priority, + * task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + } #endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c index 9840f5aad2c..5994c0986fe 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -70,30 +70,30 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + * functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -110,85 +110,86 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - configTOGGLE_LED(); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + configTOGGLE_LED(); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c index a26e429dba9..7f6c3a5959c 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -83,24 +83,24 @@ #include "recmutex.h" /* Priorities for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /*-----------------------------------------------------------*/ @@ -114,139 +114,142 @@ static void prvCheckTimerCallback( TimerHandle_t xTimer ); * of the FPU registers, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly file. */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); +extern void vRegTest1Task( void * pvParameters ); +extern void vRegTest2Task( void * pvParameters ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { -TimerHandle_t xCheckTimer = NULL; - - /* Start all the other standard demo/test tasks. The have not particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + TimerHandle_t xCheckTimer = NULL; + + /* Start all the other standard demo/test tasks. The have not particular + * functionality, but do demonstrate how to use the FreeRTOS API and test the + * kernel port. */ + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + * file */ + xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - /* Have any errors been latch in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/FreeRTOSConfig.h index ad800272095..ff4498b539c 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main.c index 1400b86d118..5181d741659 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -47,10 +47,10 @@ * that is found on the FreeRTOS.org web site. */ -/* +/* * The following #error directive is to remind users that a batch file must be - * executed prior to this project being built. The batch file *cannot* be - * executed from within the IDE! Once it has been executed, re-open or refresh + * executed prior to this project being built. The batch file *cannot* be + * executed from within the IDE! Once it has been executed, re-open or refresh * the Eclipse project and remove the #error line below. */ #error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above. @@ -68,8 +68,8 @@ #include "QueueOverwrite.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -89,128 +89,131 @@ extern void main_full( void ); int main( void ) { - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - configCONFIGURE_LED(); + configCONFIGURE_LED(); - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_SetPriorityGrouping( 0 ); + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ) - { - __asm volatile( "NOP" ); - }; + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + __asm volatile ( "NOP" ); + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ) - { - __asm volatile( "NOP" ); - } + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + __asm volatile ( "NOP" ); + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - - /* Test the ISR safe queue overwrite functions. */ - vQueueOverwritePeriodicISRDemo(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ + + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + + /* Test the ISR safe queue overwrite functions. */ + vQueueOverwritePeriodicISRDemo(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ } /*-----------------------------------------------------------*/ #ifdef JUST_AN_EXAMPLE_ISR -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} + void Dummy_IRQHandler( void ) + { + long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. A semaphore is used for this purpose. Note + * lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the current Running state task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + * internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + * portEND_SWITCHING_ISR() macro will result in a context switch being pended to + * ensure this interrupt returns directly to the unblocked, higher priority, + * task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + } #endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_blinky.c index e32fb48780c..8b4a91fd8dd 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -70,30 +70,30 @@ #include "semphr.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + * functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -110,88 +110,87 @@ static QueueHandle_t xQueue = NULL; void main_blinky( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ) - { - __asm volatile( "NOP" ); - } + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + __asm volatile ( "NOP" ); + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle the LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - configTOGGLE_LED(); - ulReceivedValue = 0U; - } - } + unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + configTOGGLE_LED(); + ulReceivedValue = 0U; + } + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_full.c index 3c0694dd1f2..c749c29b0c5 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Tasking/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -85,24 +85,24 @@ #include "QueueOverwrite.h" /* Priorities for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /*-----------------------------------------------------------*/ @@ -116,499 +116,498 @@ static void prvCheckTimerCallback( TimerHandle_t xTimer ); * of the FPU registers, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly file. */ -static void vRegTest1Task( void *pvParameters ); -static void vRegTest2Task( void *pvParameters ); +static void vRegTest1Task( void * pvParameters ); +static void vRegTest2Task( void * pvParameters ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { -TimerHandle_t xCheckTimer = NULL; - - /* Start all the other standard demo/test tasks. The have not particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartQueueSetTasks(); - vStartQueueOverwriteTask( tskIDLE_PRIORITY ); - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ) - { - __asm volatile( "NOP" ); - } + TimerHandle_t xCheckTimer = NULL; + + /* Start all the other standard demo/test tasks. The have not particular + * functionality, but do demonstrate how to use the FreeRTOS API and test the + * kernel port. */ + vStartQueueSetTasks(); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + * file */ + xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + __asm volatile ( "NOP" ); + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreQueueSetTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - /* Have any errors been latch in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreQueueSetTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ /* This is a naked function. */ -static void vRegTest1Task( void *pvParameters ) +static void vRegTest1Task( void * pvParameters ) { - __asm volatile - ( - " \n" /* Fill the core registers with known values. */ - " mov r0, #100 \n" - " mov r1, #101 \n" - " mov r2, #102 \n" - " mov r3, #103 \n" - " mov r4, #104 \n" - " mov r5, #105 \n" - " mov r6, #106 \n" - " mov r7, #107 \n" - " mov r8, #108 \n" - " mov r9, #109 \n" - " mov r10, #110 \n" - " mov r11, #111 \n" - " mov r12, #112 \n" - " \n" - " vmov d0, r0, r1 \n" /* Fill the VFP registers with known values. */ - " vmov d1, r2, r3 \n" - " vmov d2, r4, r5 \n" - " vmov d3, r6, r7 \n" - " vmov d4, r8, r9 \n" - " vmov d5, r10, r11 \n" - " vmov d6, r0, r1 \n" - " vmov d7, r2, r3 \n" - " vmov d8, r4, r5 \n" - " vmov d9, r6, r7 \n" - " vmov d10, r8, r9 \n" - " vmov d11, r10, r11 \n" - " vmov d12, r0, r1 \n" - " vmov d13, r2, r3 \n" - " vmov d14, r4, r5 \n" - " vmov d15, r6, r7 \n" - " \n" - "reg1_loop: \n" /* Check all the VFP registers still contain the values set above." */ - " push { r0-r1 } \n" /* First save registers that are clobbered by the test. */ - " \n" - " vmov r0, r1, d0 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d1 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d2 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d3 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d4 \n" - " cmp r0, #108 \n" - " bne reg1_error_loopf \n" - " cmp r1, #109 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d5 \n" - " cmp r0, #110 \n" - " bne reg1_error_loopf \n" - " cmp r1, #111 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d6 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d7 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d8 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d9 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d10 \n" - " cmp r0, #108 \n" - " bne reg1_error_loopf \n" - " cmp r1, #109 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d11 \n" - " cmp r0, #110 \n" - " bne reg1_error_loopf \n" - " cmp r1, #111 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d12 \n" - " cmp r0, #100 \n" - " bne reg1_error_loopf \n" - " cmp r1, #101 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d13 \n" - " cmp r0, #102 \n" - " bne reg1_error_loopf \n" - " cmp r1, #103 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d14 \n" - " cmp r0, #104 \n" - " bne reg1_error_loopf \n" - " cmp r1, #105 \n" - " bne reg1_error_loopf \n" - " vmov r0, r1, d15 \n" - " cmp r0, #106 \n" - " bne reg1_error_loopf \n" - " cmp r1, #107 \n" - " bne reg1_error_loopf \n" - " \n" - " pop {r0-r1} \n" /* Restore the registers that were clobbered by the test. */ - " \n" - " b reg1_loopf_pass \n" /* VFP register test passed. Jump to the core register test. */ - " \n" - "reg1_error_loopf: \n" - " b reg1_error_loopf \n" /* If this line is hit then a VFP register value was found to be\n incorrect. */ - " \n" - "reg1_loopf_pass: \n" - " \n" - " cmp r0, #100 \n" - " bne reg1_error_loop \n" - " cmp r1, #101 \n" - " bne reg1_error_loop \n" - " cmp r2, #102 \n" - " bne reg1_error_loop \n" - " cmp r3, #103 \n" - " bne reg1_error_loop \n" - " cmp r4, #104 \n" - " bne reg1_error_loop \n" - " cmp r5, #105 \n" - " bne reg1_error_loop \n" - " cmp r6, #106 \n" - " bne reg1_error_loop \n" - " cmp r7, #107 \n" - " bne reg1_error_loop \n" - " cmp r8, #108 \n" - " bne reg1_error_loop \n" - " cmp r9, #109 \n" - " bne reg1_error_loop \n" - " cmp r10, #110 \n" - " bne reg1_error_loop \n" - " cmp r11, #111 \n" - " bne reg1_error_loop \n" - " cmp r12, #112 \n" - " bne reg1_error_loop \n" - " \n" - " push { r0-r1 } \n" /* Everything passed, increment the loop counter. */ - " ldr r0, =ulRegTest1LoopCounter \n" - " ldr r1, [r0] \n" - " adds r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r0-r1 } \n" - " \n" - " b reg1_loop \n" /* Start again. */ - " \n" - "reg1_error_loop: \n" /* If this line is hit then there was an error in a core register value. */ - " b reg1_error_loop \n" /* The loop ensures the loop counter stops incrementing. */ - " nop " - ); + __asm volatile + ( + " \n"/* Fill the core registers with known values. */ + " mov r0, #100 \n" + " mov r1, #101 \n" + " mov r2, #102 \n" + " mov r3, #103 \n" + " mov r4, #104 \n" + " mov r5, #105 \n" + " mov r6, #106 \n" + " mov r7, #107 \n" + " mov r8, #108 \n" + " mov r9, #109 \n" + " mov r10, #110 \n" + " mov r11, #111 \n" + " mov r12, #112 \n" + " \n" + " vmov d0, r0, r1 \n"/* Fill the VFP registers with known values. */ + " vmov d1, r2, r3 \n" + " vmov d2, r4, r5 \n" + " vmov d3, r6, r7 \n" + " vmov d4, r8, r9 \n" + " vmov d5, r10, r11 \n" + " vmov d6, r0, r1 \n" + " vmov d7, r2, r3 \n" + " vmov d8, r4, r5 \n" + " vmov d9, r6, r7 \n" + " vmov d10, r8, r9 \n" + " vmov d11, r10, r11 \n" + " vmov d12, r0, r1 \n" + " vmov d13, r2, r3 \n" + " vmov d14, r4, r5 \n" + " vmov d15, r6, r7 \n" + " \n" + "reg1_loop: \n"/* Check all the VFP registers still contain the values set above." */ + " push { r0-r1 } \n"/* First save registers that are clobbered by the test. */ + " \n" + " vmov r0, r1, d0 \n" + " cmp r0, #100 \n" + " bne reg1_error_loopf \n" + " cmp r1, #101 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d1 \n" + " cmp r0, #102 \n" + " bne reg1_error_loopf \n" + " cmp r1, #103 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d2 \n" + " cmp r0, #104 \n" + " bne reg1_error_loopf \n" + " cmp r1, #105 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d3 \n" + " cmp r0, #106 \n" + " bne reg1_error_loopf \n" + " cmp r1, #107 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d4 \n" + " cmp r0, #108 \n" + " bne reg1_error_loopf \n" + " cmp r1, #109 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d5 \n" + " cmp r0, #110 \n" + " bne reg1_error_loopf \n" + " cmp r1, #111 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d6 \n" + " cmp r0, #100 \n" + " bne reg1_error_loopf \n" + " cmp r1, #101 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d7 \n" + " cmp r0, #102 \n" + " bne reg1_error_loopf \n" + " cmp r1, #103 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d8 \n" + " cmp r0, #104 \n" + " bne reg1_error_loopf \n" + " cmp r1, #105 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d9 \n" + " cmp r0, #106 \n" + " bne reg1_error_loopf \n" + " cmp r1, #107 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d10 \n" + " cmp r0, #108 \n" + " bne reg1_error_loopf \n" + " cmp r1, #109 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d11 \n" + " cmp r0, #110 \n" + " bne reg1_error_loopf \n" + " cmp r1, #111 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d12 \n" + " cmp r0, #100 \n" + " bne reg1_error_loopf \n" + " cmp r1, #101 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d13 \n" + " cmp r0, #102 \n" + " bne reg1_error_loopf \n" + " cmp r1, #103 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d14 \n" + " cmp r0, #104 \n" + " bne reg1_error_loopf \n" + " cmp r1, #105 \n" + " bne reg1_error_loopf \n" + " vmov r0, r1, d15 \n" + " cmp r0, #106 \n" + " bne reg1_error_loopf \n" + " cmp r1, #107 \n" + " bne reg1_error_loopf \n" + " \n" + " pop {r0-r1} \n"/* Restore the registers that were clobbered by the test. */ + " \n" + " b reg1_loopf_pass \n"/* VFP register test passed. Jump to the core register test. */ + " \n" + "reg1_error_loopf: \n" + " b reg1_error_loopf \n"/* If this line is hit then a VFP register value was found to be\n incorrect. */ + " \n" + "reg1_loopf_pass: \n" + " \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " cmp r8, #108 \n" + " bne reg1_error_loop \n" + " cmp r9, #109 \n" + " bne reg1_error_loop \n" + " cmp r10, #110 \n" + " bne reg1_error_loop \n" + " cmp r11, #111 \n" + " bne reg1_error_loop \n" + " cmp r12, #112 \n" + " bne reg1_error_loop \n" + " \n" + " push { r0-r1 } \n"/* Everything passed, increment the loop counter. */ + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r0-r1 } \n" + " \n" + " b reg1_loop \n"/* Start again. */ + " \n" + "reg1_error_loop: \n"/* If this line is hit then there was an error in a core register value. */ + " b reg1_error_loop \n"/* The loop ensures the loop counter stops incrementing. */ + " nop " + ); } /*-----------------------------------------------------------*/ /* This is a naked function. */ -static void vRegTest2Task( void *pvParameters ) +static void vRegTest2Task( void * pvParameters ) { - __asm volatile - ( - " mov r0, #-1 \n" /* Set all the core registers to known values. */ - " mov r1, #1 \n" - " mov r2, #2 \n" - " mov r3, #3 \n" - " mov r4, #4 \n" - " mov r5, #5 \n" - " mov r6, #6 \n" - " mov r7, #7 \n" - " mov r8, #8 \n" - " mov r9, #9 \n" - " mov r10, #10 \n" - " mov r11, #11 \n" - " mov r12, #12 \n" - " \n" - " vmov d0, r0, r1 \n" /* Set all the VFP to known values. */ - " vmov d1, r2, r3 \n" - " vmov d2, r4, r5 \n" - " vmov d3, r6, r7 \n" - " vmov d4, r8, r9 \n" - " vmov d5, r10, r11 \n" - " vmov d6, r0, r1 \n" - " vmov d7, r2, r3 \n" - " vmov d8, r4, r5 \n" - " vmov d9, r6, r7 \n" - " vmov d10, r8, r9 \n" - " vmov d11, r10, r11 \n" - " vmov d12, r0, r1 \n" - " vmov d13, r2, r3 \n" - " vmov d14, r4, r5 \n" - " vmov d15, r6, r7 \n" - " \n" - "reg2_loop: \n" - " \n" - " push { r0-r1 } \n" /* Check all the VFP registers still contain the values set above. */ - " vmov r0, r1, d0 \n" /*First save registers that are clobbered by the test. */ - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d1 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d2 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d3 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d4 \n" - " cmp r0, #8 \n" - " bne reg2_error_loopf \n" - " cmp r1, #9 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d5 \n" - " cmp r0, #10 \n" - " bne reg2_error_loopf \n" - " cmp r1, #11 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d6 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d7 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d8 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d9 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d10 \n" - " cmp r0, #8 \n" - " bne reg2_error_loopf \n" - " cmp r1, #9 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d11 \n" - " cmp r0, #10 \n" - " bne reg2_error_loopf \n" - " cmp r1, #11 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d12 \n" - " cmp r0, #-1 \n" - " bne reg2_error_loopf \n" - " cmp r1, #1 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d13 \n" - " cmp r0, #2 \n" - " bne reg2_error_loopf \n" - " cmp r1, #3 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d14 \n" - " cmp r0, #4 \n" - " bne reg2_error_loopf \n" - " cmp r1, #5 \n" - " bne reg2_error_loopf \n" - " vmov r0, r1, d15 \n" - " cmp r0, #6 \n" - " bne reg2_error_loopf \n" - " cmp r1, #7 \n" - " bne reg2_error_loopf \n" - " \n" - " pop {r0-r1} \n" /* Restore the registers that were clobbered by the test. */ - " \n" - " b reg2_loopf_pass \n" /* VFP register test passed. Jump to the core register test. */ - " \n" - "reg2_error_loopf: \n" - " b reg2_error_loopf \n" /* If this line is hit then a VFP register value was found to be incorrect. */ - " \n" - "reg2_loopf_pass: \n" - " \n" - " cmp r0, #-1 \n" - " bne reg2_error_loop \n" - " cmp r1, #1 \n" - " bne reg2_error_loop \n" - " cmp r2, #2 \n" - " bne reg2_error_loop \n" - " cmp r3, #3 \n" - " bne reg2_error_loop \n" - " cmp r4, #4 \n" - " bne reg2_error_loop \n" - " cmp r5, #5 \n" - " bne reg2_error_loop \n" - " cmp r6, #6 \n" - " bne reg2_error_loop \n" - " cmp r7, #7 \n" - " bne reg2_error_loop \n" - " cmp r8, #8 \n" - " bne reg2_error_loop \n" - " cmp r9, #9 \n" - " bne reg2_error_loop \n" - " cmp r10, #10 \n" - " bne reg2_error_loop \n" - " cmp r11, #11 \n" - " bne reg2_error_loop \n" - " cmp r12, #12 \n" - " bne reg2_error_loop \n" - " \n" - " push { r0-r1 } \n" /* Increment the loop counter to indicate this test is still functioning correctly. */ - " ldr r0, =ulRegTest2LoopCounter \n" - " ldr r1, [r0] \n" - " adds r1, r1, #1 \n" - " str r1, [r0] \n" - " \n" - " movs r0, #0x01 \n" /* Yield to increase test coverage. */ - " ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */ - " lsl r0, r0, #28 \n" /* Shift to PendSV bit */ - " str r0, [r1] \n" - " dsb \n" - " pop { r0-r1 } \n" - " \n" - " b reg2_loop \n" /* Start again. */ - " \n" - "reg2_error_loop: \n" /* If this line is hit then there was an error in a core register value. */ - " b reg2_error_loop \n" /* This loop ensures the loop counter variable stops incrementing. */ - " nop \n" - ); + __asm volatile + ( + " mov r0, #-1 \n"/* Set all the core registers to known values. */ + " mov r1, #1 \n" + " mov r2, #2 \n" + " mov r3, #3 \n" + " mov r4, #4 \n" + " mov r5, #5 \n" + " mov r6, #6 \n" + " mov r7, #7 \n" + " mov r8, #8 \n" + " mov r9, #9 \n" + " mov r10, #10 \n" + " mov r11, #11 \n" + " mov r12, #12 \n" + " \n" + " vmov d0, r0, r1 \n"/* Set all the VFP to known values. */ + " vmov d1, r2, r3 \n" + " vmov d2, r4, r5 \n" + " vmov d3, r6, r7 \n" + " vmov d4, r8, r9 \n" + " vmov d5, r10, r11 \n" + " vmov d6, r0, r1 \n" + " vmov d7, r2, r3 \n" + " vmov d8, r4, r5 \n" + " vmov d9, r6, r7 \n" + " vmov d10, r8, r9 \n" + " vmov d11, r10, r11 \n" + " vmov d12, r0, r1 \n" + " vmov d13, r2, r3 \n" + " vmov d14, r4, r5 \n" + " vmov d15, r6, r7 \n" + " \n" + "reg2_loop: \n" + " \n" + " push { r0-r1 } \n"/* Check all the VFP registers still contain the values set above. */ + " vmov r0, r1, d0 \n"/*First save registers that are clobbered by the test. */ + " cmp r0, #-1 \n" + " bne reg2_error_loopf \n" + " cmp r1, #1 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d1 \n" + " cmp r0, #2 \n" + " bne reg2_error_loopf \n" + " cmp r1, #3 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d2 \n" + " cmp r0, #4 \n" + " bne reg2_error_loopf \n" + " cmp r1, #5 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d3 \n" + " cmp r0, #6 \n" + " bne reg2_error_loopf \n" + " cmp r1, #7 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d4 \n" + " cmp r0, #8 \n" + " bne reg2_error_loopf \n" + " cmp r1, #9 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d5 \n" + " cmp r0, #10 \n" + " bne reg2_error_loopf \n" + " cmp r1, #11 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d6 \n" + " cmp r0, #-1 \n" + " bne reg2_error_loopf \n" + " cmp r1, #1 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d7 \n" + " cmp r0, #2 \n" + " bne reg2_error_loopf \n" + " cmp r1, #3 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d8 \n" + " cmp r0, #4 \n" + " bne reg2_error_loopf \n" + " cmp r1, #5 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d9 \n" + " cmp r0, #6 \n" + " bne reg2_error_loopf \n" + " cmp r1, #7 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d10 \n" + " cmp r0, #8 \n" + " bne reg2_error_loopf \n" + " cmp r1, #9 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d11 \n" + " cmp r0, #10 \n" + " bne reg2_error_loopf \n" + " cmp r1, #11 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d12 \n" + " cmp r0, #-1 \n" + " bne reg2_error_loopf \n" + " cmp r1, #1 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d13 \n" + " cmp r0, #2 \n" + " bne reg2_error_loopf \n" + " cmp r1, #3 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d14 \n" + " cmp r0, #4 \n" + " bne reg2_error_loopf \n" + " cmp r1, #5 \n" + " bne reg2_error_loopf \n" + " vmov r0, r1, d15 \n" + " cmp r0, #6 \n" + " bne reg2_error_loopf \n" + " cmp r1, #7 \n" + " bne reg2_error_loopf \n" + " \n" + " pop {r0-r1} \n"/* Restore the registers that were clobbered by the test. */ + " \n" + " b reg2_loopf_pass \n"/* VFP register test passed. Jump to the core register test. */ + " \n" + "reg2_error_loopf: \n" + " b reg2_error_loopf \n"/* If this line is hit then a VFP register value was found to be incorrect. */ + " \n" + "reg2_loopf_pass: \n" + " \n" + " cmp r0, #-1 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " cmp r8, #8 \n" + " bne reg2_error_loop \n" + " cmp r9, #9 \n" + " bne reg2_error_loop \n" + " cmp r10, #10 \n" + " bne reg2_error_loop \n" + " cmp r11, #11 \n" + " bne reg2_error_loop \n" + " cmp r12, #12 \n" + " bne reg2_error_loop \n" + " \n" + " push { r0-r1 } \n"/* Increment the loop counter to indicate this test is still functioning correctly. */ + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " movs r0, #0x01 \n"/* Yield to increase test coverage. */ + " ldr r1, =0xe000ed04 \n"/*NVIC_INT_CTRL */ + " lsl r0, r0, #28 \n"/* Shift to PendSV bit */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0-r1 } \n" + " \n" + " b reg2_loop \n"/* Start again. */ + " \n" + "reg2_error_loop: \n"/* If this line is hit then there was an error in a core register value. */ + " b reg2_error_loop \n"/* This loop ensures the loop counter variable stops incrementing. */ + " nop \n" + ); } - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/FreeRTOSConfig.h index ab48d59d0ae..a88e6060788 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main.c index 2533b196dec..6aeecbfd782 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_blinky.c index 6bc71e54b00..111355d3ce7 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_full.c index f27a01f3b22..fed47ebe7cf 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_GCC_Atollic/src/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/FreeRTOSConfig.h index a6b183c4b04..0d5e57261f5 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/ParTest.c b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/ParTest.c index afb7941f381..bfc4086970e 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/RegTest.c index d77cd279ecb..44b4a3950d9 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/main.c b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/main.c index d47e418ec8d..156c82ab68f 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h index a3f89533b13..1f2637a1db6 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c index cbdb78d7815..0a624dde752 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c index 9bf2730e56a..fa7df389c61 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c index f489b004a7d..93626766142 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c index 66eff7fcc90..6540c64efcf 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c index 43b818db0d6..ffab414d684 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c index fc7c3929a91..0fbd8822b67 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c index 92fab1043c9..d38fbf2d5a8 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,8 +57,8 @@ /*-----------------------------------------------------------*/ /* NOTE: If an IAR build results in an undefined "reference to __write" linker -error then set the printf formatter project option to "tiny" and the scanf -formatter project option to "small". */ + * error then set the printf formatter project option to "tiny" and the scanf + * formatter project option to "small". */ /* * Set up the hardware ready to run this demo. @@ -76,99 +76,107 @@ extern void main_full( void ); int main( void ) { - /* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions. */ - - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top - of this file. */ - #if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions. */ + + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top + * of this file. */ + #if ( configCREATE_SIMPLE_TICKLESS_DEMO == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -extern void FPU_enableModule( void ); + extern void FPU_enableModule( void ); - /* The clocks are not configured here, but inside main_full() and - main_blinky() as the full demo uses a fast clock and the blinky demo uses - a slow clock. */ + /* The clocks are not configured here, but inside main_full() and + * main_blinky() as the full demo uses a fast clock and the blinky demo uses + * a slow clock. */ - /* Stop the watchdog timer. */ - MAP_WDT_A_holdTimer(); + /* Stop the watchdog timer. */ + MAP_WDT_A_holdTimer(); - /* Ensure the FPU is enabled. */ - FPU_enableModule(); + /* Ensure the FPU is enabled. */ + FPU_enableModule(); - /* Selecting P1.2 and P1.3 in UART mode and P1.0 as output (LED) */ - MAP_GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_P1, GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION ); - MAP_GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 ); - MAP_GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 ); + /* Selecting P1.2 and P1.3 in UART mode and P1.0 as output (LED) */ + MAP_GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_P1, GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION ); + MAP_GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 ); + MAP_GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void *malloc( size_t xSize ) +void * malloc( size_t xSize ) { - /* There should not be a heap defined, so trap any attempts to call - malloc. */ - Interrupt_disableMaster(); - for( ;; ); + /* There should not be a heap defined, so trap any attempts to call + * malloc. */ + Interrupt_disableMaster(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/FreeRTOSConfig.h index 7ce23d402a7..e4f63745f2f 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/ParTest.c b/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/ParTest.c index fdfdb753327..46f9cbaf342 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/main.c b/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/main.c index 7ae4290edae..f21d4b4aac4 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_STM32F407ZG-SK/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -129,35 +129,35 @@ #include "stm32f4xx_conf.h" /* Priorities for the demo application tasks. */ -#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* The LED used by the check timer. */ -#define mainCHECK_LED ( 3UL ) +#define mainCHECK_LED ( 3UL ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /* Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 1 to create a simple demo. -Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more -comprehensive test application. See the comments at the top of this file, and -the documentation page on the http://www.FreeRTOS.org web site for more -information. */ -#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0 + * Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more + * comprehensive test application. See the comments at the top of this file, and + * the documentation page on the http://www.FreeRTOS.org web site for more + * information. */ +#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0 /*-----------------------------------------------------------*/ @@ -182,8 +182,8 @@ static void prvSetupNestedFPUInterruptsTest( void ); * of the FPU registers, as described at the top of this file. The nature of * these files necessitates that they are written in an assembly file. */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); +extern void vRegTest1Task( void * pvParameters ); +extern void vRegTest2Task( void * pvParameters ); extern void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue ); extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue ); @@ -192,7 +192,7 @@ extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned * to demonstrate how to write interrupt service routines, and how to * synchronise a task with an interrupt. */ -static void prvButtonTestTask( void *pvParameters ); +static void prvButtonTestTask( void * pvParameters ); /* * This file can be used to create either a simple LED flasher example, or a @@ -208,422 +208,433 @@ static void prvOptionallyCreateComprehensveTestApplication( void ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ + * register check tasks to the check software timer. If the variables keep + * incrementing, then the register check tasks have not discovered any errors. If + * a variable stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /* The following variables are used to verify that the interrupt nesting depth -is as intended. ulFPUInterruptNesting is incremented on entry to an interrupt -that uses the FPU, and decremented on exit of the same interrupt. -ulMaxFPUInterruptNesting latches the highest value reached by -ulFPUInterruptNesting. These variables have no other purpose. */ + * is as intended. ulFPUInterruptNesting is incremented on entry to an interrupt + * that uses the FPU, and decremented on exit of the same interrupt. + * ulMaxFPUInterruptNesting latches the highest value reached by + * ulFPUInterruptNesting. These variables have no other purpose. */ volatile unsigned long ulFPUInterruptNesting = 0UL, ulMaxFPUInterruptNesting = 0UL; /* The semaphore used to demonstrate a task being synchronised with an -interrupt. */ + * interrupt. */ static SemaphoreHandle_t xTestSemaphore = NULL; /* The variable that is incremented by the task synchronised with the button -interrupt. */ + * interrupt. */ volatile unsigned long ulButtonPressCounts = 0UL; /*-----------------------------------------------------------*/ -int main(void) +int main( void ) { - /* Configure the hardware ready to run the test. */ - prvSetupHardware(); - - /* Start standard demo/test application flash tasks. See the comments at - the top of this file. The LED flash tasks are always created. The other - tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to - 0 (at the top of this file). See the comments at the top of this file for - more information. */ - vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); - - /* The following function will only create more tasks and timers if - mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this - file). See the comments at the top of this file for more information. */ - prvOptionallyCreateComprehensveTestApplication(); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + /* Configure the hardware ready to run the test. */ + prvSetupHardware(); + + /* Start standard demo/test application flash tasks. See the comments at + * the top of this file. The LED flash tasks are always created. The other + * tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to + * 0 (at the top of this file). See the comments at the top of this file for + * more information. */ + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + + /* The following function will only create more tasks and timers if + * mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this + * file). See the comments at the top of this file for more information. */ + prvOptionallyCreateComprehensveTestApplication(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -long lErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - lErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - lErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - /* Have any errors been latch in lErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( lErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } + static long lChangedTimerPeriodAlready = pdFALSE; + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + long lErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + lErrorFound = pdTRUE; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + lErrorFound = pdTRUE; + } + + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Have any errors been latch in lErrorFound? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( lErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } } /*-----------------------------------------------------------*/ -static void prvButtonTestTask( void *pvParameters ) +static void prvButtonTestTask( void * pvParameters ) { - configASSERT( xTestSemaphore ); - - /* This is the task used as an example of how to synchronise a task with - an interrupt. Each time the button interrupt gives the semaphore, this task - will unblock, increment its execution counter, then return to block - again. */ - - /* Take the semaphore before started to ensure it is in the correct - state. */ - xSemaphoreTake( xTestSemaphore, mainDONT_BLOCK ); - - for( ;; ) - { - xSemaphoreTake( xTestSemaphore, portMAX_DELAY ); - ulButtonPressCounts++; - } + configASSERT( xTestSemaphore ); + + /* This is the task used as an example of how to synchronise a task with + * an interrupt. Each time the button interrupt gives the semaphore, this task + * will unblock, increment its execution counter, then return to block + * again. */ + + /* Take the semaphore before started to ensure it is in the correct + * state. */ + xSemaphoreTake( xTestSemaphore, mainDONT_BLOCK ); + + for( ; ; ) + { + xSemaphoreTake( xTestSemaphore, portMAX_DELAY ); + ulButtonPressCounts++; + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Setup STM32 system (clock, PLL and Flash configuration) */ - SystemInit(); + /* Setup STM32 system (clock, PLL and Flash configuration) */ + SystemInit(); - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); - /* Setup the LED outputs. */ - vParTestInitialise(); + /* Setup the LED outputs. */ + vParTestInitialise(); - /* Configure the button input. This configures the interrupt to use the - lowest interrupt priority, so it is ok to use the ISR safe FreeRTOS API - from the button interrupt handler. */ - STM_EVAL_PBInit( BUTTON_USER, BUTTON_MODE_EXTI ); + /* Configure the button input. This configures the interrupt to use the + * lowest interrupt priority, so it is ok to use the ISR safe FreeRTOS API + * from the button interrupt handler. */ + STM_EVAL_PBInit( BUTTON_USER, BUTTON_MODE_EXTI ); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 ) - { - /* Just to verify that the interrupt nesting behaves as expected, - increment ulFPUInterruptNesting on entry, and decrement it on exit. */ - ulFPUInterruptNesting++; - - /* Fill the FPU registers with 0. */ - vRegTestClearFlopRegistersToParameterValue( 0UL ); - - /* Trigger a timer 2 interrupt, which will fill the registers with a - different value and itself trigger a timer 3 interrupt. Note that the - timers are not actually used. The timer 2 and 3 interrupt vectors are - just used for convenience. */ - NVIC_SetPendingIRQ( TIM2_IRQn ); - - /* Ensure that, after returning from the nested interrupts, all the FPU - registers contain the value to which they were set by the tick hook - function. */ - configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 0UL ) ); - - ulFPUInterruptNesting--; - } - #endif + #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 ) + { + /* Just to verify that the interrupt nesting behaves as expected, + * increment ulFPUInterruptNesting on entry, and decrement it on exit. */ + ulFPUInterruptNesting++; + + /* Fill the FPU registers with 0. */ + vRegTestClearFlopRegistersToParameterValue( 0UL ); + + /* Trigger a timer 2 interrupt, which will fill the registers with a + * different value and itself trigger a timer 3 interrupt. Note that the + * timers are not actually used. The timer 2 and 3 interrupt vectors are + * just used for convenience. */ + NVIC_SetPendingIRQ( TIM2_IRQn ); + + /* Ensure that, after returning from the nested interrupts, all the FPU + * registers contain the value to which they were set by the tick hook + * function. */ + configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 0UL ) ); + + ulFPUInterruptNesting--; + } + #endif /* if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 ) */ } /*-----------------------------------------------------------*/ static void prvSetupNestedFPUInterruptsTest( void ) { -NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the TIM2 interrupt in the NVIC. The timer itself is not used, - just its interrupt vector to force nesting from software. TIM2 must have - a lower priority than TIM3, and both must have priorities above - configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init( &NVIC_InitStructure ); - - /* Enable the TIM3 interrupt in the NVIC. The timer itself is not used, - just its interrupt vector to force nesting from software. TIM2 must have - a lower priority than TIM3, and both must have priorities above - configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 2; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init( &NVIC_InitStructure ); + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable the TIM2 interrupt in the NVIC. The timer itself is not used, + * just its interrupt vector to force nesting from software. TIM2 must have + * a lower priority than TIM3, and both must have priorities above + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); + + /* Enable the TIM3 interrupt in the NVIC. The timer itself is not used, + * just its interrupt vector to force nesting from software. TIM2 must have + * a lower priority than TIM3, and both must have priorities above + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); } /*-----------------------------------------------------------*/ void TIM3_IRQHandler( void ) { - /* Just to verify that the interrupt nesting behaves as expected, increment - ulFPUInterruptNesting on entry, and decrement it on exit. */ - ulFPUInterruptNesting++; - - /* This is the highest priority interrupt in the chain of forced nesting - interrupts, so latch the maximum value reached by ulFPUInterruptNesting. - This is done purely to allow verification that the nesting depth reaches - that intended. */ - if( ulFPUInterruptNesting > ulMaxFPUInterruptNesting ) - { - ulMaxFPUInterruptNesting = ulFPUInterruptNesting; - } - - /* Fill the FPU registers with 99 to overwrite the values written by - TIM2_IRQHandler(). */ - vRegTestClearFlopRegistersToParameterValue( 99UL ); - - ulFPUInterruptNesting--; + /* Just to verify that the interrupt nesting behaves as expected, increment + * ulFPUInterruptNesting on entry, and decrement it on exit. */ + ulFPUInterruptNesting++; + + /* This is the highest priority interrupt in the chain of forced nesting + * interrupts, so latch the maximum value reached by ulFPUInterruptNesting. + * This is done purely to allow verification that the nesting depth reaches + * that intended. */ + if( ulFPUInterruptNesting > ulMaxFPUInterruptNesting ) + { + ulMaxFPUInterruptNesting = ulFPUInterruptNesting; + } + + /* Fill the FPU registers with 99 to overwrite the values written by + * TIM2_IRQHandler(). */ + vRegTestClearFlopRegistersToParameterValue( 99UL ); + + ulFPUInterruptNesting--; } /*-----------------------------------------------------------*/ void TIM2_IRQHandler( void ) { - /* Just to verify that the interrupt nesting behaves as expected, increment - ulFPUInterruptNesting on entry, and decrement it on exit. */ - ulFPUInterruptNesting++; + /* Just to verify that the interrupt nesting behaves as expected, increment + * ulFPUInterruptNesting on entry, and decrement it on exit. */ + ulFPUInterruptNesting++; - /* Fill the FPU registers with 1. */ - vRegTestClearFlopRegistersToParameterValue( 1UL ); + /* Fill the FPU registers with 1. */ + vRegTestClearFlopRegistersToParameterValue( 1UL ); - /* Trigger a timer 3 interrupt, which will fill the registers with a - different value. */ - NVIC_SetPendingIRQ( TIM3_IRQn ); + /* Trigger a timer 3 interrupt, which will fill the registers with a + * different value. */ + NVIC_SetPendingIRQ( TIM3_IRQn ); - /* Ensure that, after returning from the nesting interrupt, all the FPU - registers contain the value to which they were set by this interrupt - function. */ - configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 1UL ) ); + /* Ensure that, after returning from the nesting interrupt, all the FPU + * registers contain the value to which they were set by this interrupt + * function. */ + configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 1UL ) ); - ulFPUInterruptNesting--; + ulFPUInterruptNesting--; } /*-----------------------------------------------------------*/ static void prvOptionallyCreateComprehensveTestApplication( void ) { - #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 ) - { - TimerHandle_t xCheckTimer = NULL; - - /* Configure the interrupts used to test FPU registers being used from - nested interrupts. */ - prvSetupNestedFPUInterruptsTest(); - - /* Start all the other standard demo/test tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - - /* Most importantly, start the tasks that use the FPU. */ - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the semaphore that is used to demonstrate a task being - synchronised with an interrupt. */ - vSemaphoreCreateBinary( xTestSemaphore ); - - /* Create the task that is unblocked by the demonstration interrupt. */ - xTaskCreate( prvButtonTestTask, "BtnTest", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* This task has to be created last as it keeps account of the number of - tasks it expects to see running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - } - #else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */ - { - /* Just to prevent compiler warnings when the configuration options are - set such that these static functions are not used. */ - ( void ) vRegTest1Task; - ( void ) vRegTest2Task; - ( void ) prvCheckTimerCallback; - ( void ) prvSetupNestedFPUInterruptsTest; - } - #endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */ + #if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 ) + { + TimerHandle_t xCheckTimer = NULL; + + /* Configure the interrupts used to test FPU registers being used from + * nested interrupts. */ + prvSetupNestedFPUInterruptsTest(); + + /* Start all the other standard demo/test tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + + /* Most importantly, start the tasks that use the FPU. */ + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + * file */ + xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the semaphore that is used to demonstrate a task being + * synchronised with an interrupt. */ + vSemaphoreCreateBinary( xTestSemaphore ); + + /* Create the task that is unblocked by the demonstration interrupt. */ + xTaskCreate( prvButtonTestTask, "BtnTest", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* This task has to be created last as it keeps account of the number of + * tasks it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + } + #else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */ + { + /* Just to prevent compiler warnings when the configuration options are + * set such that these static functions are not used. */ + ( void ) vRegTest1Task; + ( void ) vRegTest2Task; + ( void ) prvCheckTimerCallback; + ( void ) prvSetupNestedFPUInterruptsTest; + } + #endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */ } /*-----------------------------------------------------------*/ -void EXTI9_5_IRQHandler(void) +void EXTI9_5_IRQHandler( void ) { -long lHigherPriorityTaskWoken = pdFALSE; - - /* Only line 6 is enabled, so there is no need to test which line generated - the interrupt. */ - EXTI_ClearITPendingBit( EXTI_Line6 ); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. First the handler releases a semaphore. - lHigherPriorityTaskWoken has been initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the currently executing task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE. - Passing pdTRUE into the following macro call will cause this interrupt to - return directly to the unblocked, higher priority, task. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); + long lHigherPriorityTaskWoken = pdFALSE; + + /* Only line 6 is enabled, so there is no need to test which line generated + * the interrupt. */ + EXTI_ClearITPendingBit( EXTI_Line6 ); + + /* This interrupt does nothing more than demonstrate how to synchronise a + * task with an interrupt. First the handler releases a semaphore. + * lHigherPriorityTaskWoken has been initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + * semaphore caused the task to unblock, and the unblocked task has a priority + * higher than the currently executing task (the task that this interrupt + * interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE. + * Passing pdTRUE into the following macro call will cause this interrupt to + * return directly to the unblocked, higher priority, task. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/ParTest.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/ParTest.c index f261b35cd72..1cc110a5f9f 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c index bea8f9678c8..ee7d5440954 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/SAM4L_low_power_tick_management.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/config/FreeRTOSConfig.h index 0a67d27f995..47198881bd5 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main.c index 6e67891e62d..a75521e1fc3 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_full.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_full.c index c5ac083b059..fce48cc3729 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_low_power.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_low_power.c index 3a23b19d7ef..f16c4581212 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_low_power.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4L_Atmel_Studio/src/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/comtest.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/comtest.c index c8084146fef..b57e2d94fe3 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/comtest.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/comtest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h index 2c7134c8d2d..4aa2e649ca7 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/Common-Demo-Source/include/demo_serial.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/FreeRTOSConfig.h index c572d38d4bc..fb91b79120f 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.c index d67a31a720b..c880deb6ccb 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/ParTest.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/ParTest.c index e41bc54b844..9f94e562865 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main.c index a5f5650fcec..9a5fbe5d79a 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_blinky.c index a75c9f0ff99..0a1d346db0c 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_full.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_full.c index 9bc65b72a85..d4cc051ec17 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/serial.c b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/serial.c index 19db7df9f32..5ca62bb180f 100644 --- a/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/serial.c +++ b/FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h index da995a41890..fd9fd421711 100644 --- a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c index 47e7d24430d..cda65e7f4d6 100644 --- a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c index c6a208c43fa..e4039abd9fd 100644 --- a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/Simply_Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c index e3e0f7a9fcf..d7a01ad86c9 100644 --- a/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c +++ b/FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -74,26 +74,26 @@ extern void main_full( void ); int main( void ) { - /* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for - instructions. */ - - - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top - of this file. */ - #if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* See http://www.FreeRTOS.org/TI_CC3220_SimpleLink_FreeRTOS_Demo.html for + * instructions. */ + + + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top + * of this file. */ + #if ( configCREATE_SIMPLE_TICKLESS_DEMO == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ @@ -108,7 +108,7 @@ static void prvSetupHardware( void ) void vMainToggleLED( void ) { -static uint32_t ulLEDState = Board_GPIO_LED_OFF; + static uint32_t ulLEDState = Board_GPIO_LED_OFF; ulLEDState = !ulLEDState; GPIO_write( Board_LED0, ulLEDState ); @@ -117,119 +117,135 @@ static uint32_t ulLEDState = Board_GPIO_LED_OFF; void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void *malloc( size_t xSize ) +void * malloc( size_t xSize ) { - /* There should not be a heap defined, so trap any attempts to call - malloc. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* There should not be a heap defined, so trap any attempts to call + * malloc. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ + * state will be stored. */ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; /* Pass out the array that will be used as the Idle task's stack. */ *ppxIdleTaskStackBuffer = uxIdleTaskStack; /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ + * task's state will be stored. */ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; /* Pass out the array that will be used as the Timer task's stack. */ *ppxTimerTaskStackBuffer = uxTimerTaskStack; /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ /* Catch asserts so the file and line number of the assert can be viewed. */ -void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ) +void vMainAssertCalled( const char * pcFileName, + uint32_t ulLineNumber ) { -volatile BaseType_t xSetToNonZeroToStepOutOfLoop = 0; + volatile BaseType_t xSetToNonZeroToStepOutOfLoop = 0; taskENTER_CRITICAL(); + while( xSetToNonZeroToStepOutOfLoop == 0 ) { /* Use the variables to prevent compiler warnings and in an attempt to - ensure they can be viewed in the debugger. If the variables get - optimised away then set copy their values to file scope or globals then - view the variables they are copied to. */ + * ensure they can be viewed in the debugger. If the variables get + * optimised away then set copy their values to file scope or globals then + * view the variables they are copied to. */ ( void ) pcFileName; ( void ) ulLineNumber; } @@ -237,11 +253,11 @@ volatile BaseType_t xSetToNonZeroToStepOutOfLoop = 0; /*-----------------------------------------------------------*/ /* To enable the libraries to build. */ -void PowerCC32XX_enterLPDS( void *driverlibFunc ) +void PowerCC32XX_enterLPDS( void * driverlibFunc ) { ( void ) driverlibFunc; /* This function is not implemented so trap any calls to it by halting - here. */ - configASSERT( driverlibFunc == NULL ); + * here. */ + configASSERT( driverlibFunc == NULL ); } diff --git a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/include/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/include/FreeRTOSConfig.h index b7fae017de4..ab42364c463 100644 --- a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/include/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/include/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/main.c b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/main.c index 493c2daa993..ea363df9f7a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/main.c +++ b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM4/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/include/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/include/FreeRTOSConfig.h index b29497510d0..3d1825f04d9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/include/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/include/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/main.c b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/main.c index fe96d4cab0b..9b052a0094b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/main.c +++ b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/CM7/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/MessageBufferLocations.h b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/MessageBufferLocations.h index 2d76c307232..8ef72a8cdf9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/MessageBufferLocations.h +++ b/FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/MessageBufferLocations.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Blinky_Demo/main_blinky.c index 0cf74d55373..22fdac45fa3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/FreeRTOSConfig.h index 4eddd07c8ba..94fd86c3002 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.c index 3e0389297fa..93d1ca1bddc 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/RegTest_GCC.c b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/RegTest_GCC.c index 482e67d665c..1a723787285 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/RegTest_GCC.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/RegTest_GCC.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/main_full.c index 05430c8dcb9..802fe71a3f8 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/main.c b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/main.c index 25b87554b7b..0340f412f1e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/main.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c index a85b3aaf3c9..4a8a8412dfe 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h index 5ab825a02d4..d107a30514c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c index 84fecc47001..bc79a119005 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c index 482e67d665c..1a723787285 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c index 45e0019d125..bc5a9f61b6d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c index efdd3d48b04..ac35588b819 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,8 +57,8 @@ #include "board.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -72,49 +72,50 @@ static void prvSetupHardware( void ); * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Disable watchdog. */ - WDT_Disable( WDT ); - WDT_Disable( ( Wdt * ) RSWDT ); + /* Disable watchdog. */ + WDT_Disable( WDT ); + WDT_Disable( ( Wdt * ) RSWDT ); - SCB_EnableICache(); - SCB_EnableDCache(); + SCB_EnableICache(); + SCB_EnableDCache(); LED_Configure( 0 ); LED_Configure( 1 ); @@ -123,70 +124,71 @@ static void prvSetupHardware( void ) void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); - /* Call the code that uses a mutex from an ISR. */ - vInterruptSemaphorePeriodicTest(); + /* Call the code that uses a mutex from an ISR. */ + vInterruptSemaphorePeriodicTest(); - /* Call the code that 'gives' a task notification from an ISR. */ - xNotifyTaskFromISR(); - } - #endif + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); + } + #endif /* if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 */ } /*-----------------------------------------------------------*/ @@ -194,5 +196,5 @@ void vApplicationTickHook( void ) int __write( int x ); int __write( int x ) { - return x; + return x; } diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Blinky_Demo/main_blinky.c index a85b3aaf3c9..4a8a8412dfe 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/FreeRTOSConfig.h index 5ab825a02d4..d107a30514c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c index 74df398b840..2ef2f6815e0 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.c index c0c7ed28a9a..54d3d3dd3fe 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/main_full.c index 45e0019d125..bc5a9f61b6d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/main.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/main.c index e8fd7f277fe..2458f45a54b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,8 +57,8 @@ #include "board.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /*-----------------------------------------------------------*/ @@ -72,49 +72,50 @@ static void prvSetupHardware( void ); * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - /* Disable watchdog. */ - WDT_Disable( WDT0 ); - WDT_Disable( WDT1 ); + /* Disable watchdog. */ + WDT_Disable( WDT0 ); + WDT_Disable( WDT1 ); - SCB_EnableICache(); - SCB_EnableDCache(); + SCB_EnableICache(); + SCB_EnableDCache(); LED_Configure( 0 ); LED_Configure( 1 ); @@ -123,70 +124,71 @@ static void prvSetupHardware( void ) void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); - /* Call the code that uses a mutex from an ISR. */ - vInterruptSemaphorePeriodicTest(); + /* Call the code that uses a mutex from an ISR. */ + vInterruptSemaphorePeriodicTest(); - /* Call the code that 'gives' a task notification from an ISR. */ - xNotifyTaskFromISR(); - } - #endif + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); + } + #endif /* if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 */ } /*-----------------------------------------------------------*/ @@ -194,5 +196,5 @@ void vApplicationTickHook( void ) int __write( int x ); int __write( int x ) { - return x; + return x; } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c index 5e04a62830e..fe003fd12b1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/FreeRTOSConfig.h index 8ed50eab391..ccf52defa10 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.c index c6187709135..ec0d3cdb3ed 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_Keil.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_Keil.c index c0c7ed28a9a..54d3d3dd3fe 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_Keil.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/RegTest_Keil.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c index 6179a08f143..aceed381504 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/main.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/main.c index 07b417aa96f..e5c071a3bdc 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -42,7 +42,7 @@ #include "semphr.h" /* Standard demo includes - these are needed here as the tick hook function is -defined in this file. */ + * defined in this file. */ #include "TimerDemo.h" #include "QueueOverwrite.h" #include "EventGroupsDemo.h" @@ -51,8 +51,8 @@ defined in this file. */ #include "TaskNotify.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /*-----------------------------------------------------------*/ @@ -70,212 +70,212 @@ static void prvSystemClockConfig( void ); * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ -#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - extern void main_blinky( void ); +#if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ int main( void ) { - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef GPIO_InitStruct; - /* Configure Flash prefetch and Instruction cache through ART accelerator. */ - #if( ART_ACCLERATOR_ENABLE != 0 ) - { - __HAL_FLASH_ART_ENABLE(); - } - #endif /* ART_ACCLERATOR_ENABLE */ + /* Configure Flash prefetch and Instruction cache through ART accelerator. */ + #if ( ART_ACCLERATOR_ENABLE != 0 ) + { + __HAL_FLASH_ART_ENABLE(); + } + #endif /* ART_ACCLERATOR_ENABLE */ - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping( NVIC_PRIORITYGROUP_4 ); + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping( NVIC_PRIORITYGROUP_4 ); - /* Init the low level hardware. */ - HAL_MspInit(); + /* Init the low level hardware. */ + HAL_MspInit(); - /* Configure the System clock to have a frequency of 200 MHz */ - prvSystemClockConfig(); + /* Configure the System clock to have a frequency of 200 MHz */ + prvSystemClockConfig(); - /* Enable GPIOB Clock (to be able to program the configuration - registers) and configure for LED output. */ - __GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); + /* Enable GPIOB Clock (to be able to program the configuration + * registers) and configure for LED output. */ + __GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - HAL_GPIO_Init( GPIOF, &GPIO_InitStruct ); + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init( GPIOF, &GPIO_InitStruct ); - /* MCO2 : Pin PC9 */ - HAL_RCC_MCOConfig( RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1 ); + /* MCO2 : Pin PC9 */ + HAL_RCC_MCOConfig( RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1 ); } /*-----------------------------------------------------------*/ static void prvSystemClockConfig( void ) { - /* The system Clock is configured as follow : - System Clock source = PLL (HSE) - SYSCLK(Hz) = 200000000 - HCLK(Hz) = 200000000 - AHB Prescaler = 1 - APB1 Prescaler = 4 - APB2 Prescaler = 2 - HSE Frequency(Hz) = 25000000 - PLL_M = 25 - PLL_N = 400 - PLL_P = 2 - PLL_Q = 7 - VDD(V) = 3.3 - Main regulator output voltage = Scale1 mode - Flash Latency(WS) = 7 */ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 400; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - configASSERT( HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) == HAL_OK ); + /* The system Clock is configured as follow : + * System Clock source = PLL (HSE) + * SYSCLK(Hz) = 200000000 + * HCLK(Hz) = 200000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSE Frequency(Hz) = 25000000 + * PLL_M = 25 + * PLL_N = 400 + * PLL_P = 2 + * PLL_Q = 7 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 7 */ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 400; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + HAL_RCC_OscConfig( &RCC_OscInitStruct ); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + * clocks dividers */ + RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 ); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + configASSERT( HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_7 ) == HAL_OK ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; + ( void ) pcTaskName; + ( void ) pxTask; - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; } /*-----------------------------------------------------------*/ -void vAssertCalled( uint32_t ulLine, const char *pcFile ) +void vAssertCalled( uint32_t ulLine, + const char * pcFile ) { -volatile unsigned long ul = 0; - - ( void ) pcFile; - ( void ) ulLine; - - taskENTER_CRITICAL(); - { - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - __NOP(); - } - } - taskEXIT_CRITICAL(); + volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + * function. */ + while( ul == 0 ) + { + __NOP(); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) - { - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) + { + /* The full demo includes a software timer demo/test that requires + * prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); - /* Call the code that uses a mutex from an ISR. */ - vInterruptSemaphorePeriodicTest(); + /* Call the code that uses a mutex from an ISR. */ + vInterruptSemaphorePeriodicTest(); - /* Use a queue set from an ISR. */ - vQueueSetAccessQueueSetFromISR(); + /* Use a queue set from an ISR. */ + vQueueSetAccessQueueSetFromISR(); - /* Use task notifications from an ISR. */ - xNotifyTaskFromISR(); - } - #endif + /* Use task notifications from an ISR. */ + xNotifyTaskFromISR(); + } + #endif /* if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 ) */ } /*-----------------------------------------------------------*/ - - - diff --git a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h index 222259642f3..59043cfd308 100644 --- a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c index 0f3a4613638..d52df6a8a41 100644 --- a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c index fb9ce8044d9..a42d5bcc4ff 100644 --- a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c +++ b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -135,77 +135,77 @@ #include "dynamic.h" /* The rate at which data is sent to the queue, specified in milliseconds, and -converted to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* The LED toggled by the check timer callback function. This is an LED in the -second digit of the two digit 7 segment display. See the documentation page -for this demo on the FreeRTOS.org web site to see which LED this relates to. */ -#define mainCHECK_LED ( 1UL << 3UL ) + * second digit of the two digit 7 segment display. See the documentation page + * for this demo on the FreeRTOS.org web site to see which LED this relates to. */ +#define mainCHECK_LED ( 1UL << 3UL ) /* The LED toggle by the queue receive task. This is an LED in the second digit -of the two digit 7 segment display. See the documentation page for this demo on -the FreeRTOS.org web site to see which LED this relates to. */ -#define mainTASK_CONTROLLED_LED 0x07UL + * of the two digit 7 segment display. See the documentation page for this demo on + * the FreeRTOS.org web site to see which LED this relates to. */ +#define mainTASK_CONTROLLED_LED 0x07UL /* The LED turned on by the button interrupt, and turned off by the LED timer. -This is an LED in the second digit of the two digit 7 segment display. See the -documentation page for this demo on the FreeRTOS.org web site to see which LED -this relates to. */ -#define mainTIMER_CONTROLLED_LED 0x05UL + * This is an LED in the second digit of the two digit 7 segment display. See the + * documentation page for this demo on the FreeRTOS.org web site to see which LED + * this relates to. */ +#define mainTIMER_CONTROLLED_LED 0x05UL /* The LED used by the comtest tasks. See the comtest.c file for more -information. The LEDs used by the comtest task are in the second digit of the -two digit 7 segment display. See the documentation page for this demo on the -FreeRTOS.org web site to see which LEDs this relates to. */ -#define mainCOM_TEST_LED 0x03UL + * information. The LEDs used by the comtest task are in the second digit of the + * two digit 7 segment display. See the documentation page for this demo on the + * FreeRTOS.org web site to see which LEDs this relates to. */ +#define mainCOM_TEST_LED 0x03UL /* Constant used by the standard timer test functions. */ -#define mainTIMER_TEST_PERIOD ( 50 ) +#define mainTIMER_TEST_PERIOD ( 50 ) /* Priorities used by the various different standard demo tasks. */ -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Priorities defined in this main-full.c file. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The period at which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 500UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 500UL / portTICK_PERIOD_MS ) /* The period at which the digit counter timer will expire, in ms, and converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainDIGIT_COUNTER_TIMER_PERIOD_MS ( 250UL / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainDIGIT_COUNTER_TIMER_PERIOD_MS ( 250UL / portTICK_PERIOD_MS ) /* The LED will remain on until the button has not been pushed for a full -5000ms. */ -#define mainLED_TIMER_PERIOD_MS ( 5000UL / portTICK_PERIOD_MS ) + * 5000ms. */ +#define mainLED_TIMER_PERIOD_MS ( 5000UL / portTICK_PERIOD_MS ) /* A zero block time. */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 115200UL ) +#define mainCOM_TEST_BAUD_RATE ( 115200UL ) /*-----------------------------------------------------------*/ @@ -218,8 +218,8 @@ static void prvSetupHardware( void ); * The application specific (not common demo) tasks as described in the comments * at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * The LED timer callback function. This does nothing but switch an LED off. @@ -240,7 +240,8 @@ static void prvDigitCounterTimerCallback( TimerHandle_t xTimer ); * This is not a 'standard' partest function, so the prototype is not in * partest.h, and is instead included here. */ -void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ); +void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, + signed portBASE_TYPE xValue ); /*-----------------------------------------------------------*/ @@ -248,394 +249,401 @@ void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE x static QueueHandle_t xQueue = NULL; /* The LED software timer. This uses prvLEDTimerCallback() as it's callback -function. */ + * function. */ static TimerHandle_t xLEDTimer = NULL; /* The digit counter software timer. This displays a counting digit on one half -of the seven segment displays. */ + * of the seven segment displays. */ static TimerHandle_t xDigitCounterTimer = NULL; /* The check timer. This uses prvCheckTimerCallback() as its callback -function. */ + * function. */ static TimerHandle_t xCheckTimer = NULL; /* If an error is detected in a standard demo task, then pcStatusMessage will -be set to point to a string that identifies the offending task. This is just -to make debugging easier. */ -static const char *pcStatusMessage = NULL; + * be set to point to a string that identifies the offending task. This is just + * to make debugging easier. */ +static const char * pcStatusMessage = NULL; /*-----------------------------------------------------------*/ -int main(void) +int main( void ) { - /* Configure the NVIC, LED outputs and button inputs. */ - prvSetupHardware(); - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two application specific demo tasks, as described in the - comments at the top of this file. */ - xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer that is responsible for turning off the LED - if the button is not pushed within 5000ms, as described at the top of - this file. */ - xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ - ( mainLED_TIMER_PERIOD_MS ),/* The timer period, in this case 5000ms (5s). */ - pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvLEDTimerCallback /* The callback function that switches the LED off. */ - ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* Create the software timer that performs the 'digit counting' - functionality, as described at the top of this file. */ - xDigitCounterTimer = xTimerCreate( "DigitCounter", /* A text name, purely to help debugging. */ - ( mainDIGIT_COUNTER_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvDigitCounterTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* Create a lot of 'standard demo' tasks. Over 40 tasks are created in - this demo. For a much simpler demo, select the 'blinky' build - configuration. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); - vStartQueuePeekTasks(); - vStartRecursiveMutexTasks(); - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartCountingSemaphoreTasks(); - vStartDynamicPriorityTasks(); - - /* The suicide tasks must be created last, as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given - time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + /* Configure the NVIC, LED outputs and button inputs. */ + prvSetupHardware(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two application specific demo tasks, as described in the + * comments at the top of this file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer that is responsible for turning off the LED + * if the button is not pushed within 5000ms, as described at the top of + * this file. */ + xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ + ( mainLED_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ + pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvLEDTimerCallback /* The callback function that switches the LED off. */ + ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* Create the software timer that performs the 'digit counting' + * functionality, as described at the top of this file. */ + xDigitCounterTimer = xTimerCreate( "DigitCounter", /* A text name, purely to help debugging. */ + ( mainDIGIT_COUNTER_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvDigitCounterTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* Create a lot of 'standard demo' tasks. Over 40 tasks are created in + * this demo. For a much simpler demo, select the 'blinky' build + * configuration. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartCountingSemaphoreTasks(); + vStartDynamicPriorityTasks(); + + /* The suicide tasks must be created last, as they need to know how many + * tasks were running prior to their creation in order to ascertain whether + * or not the correct/expected number of tasks are running at any given + * time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { - /* Check the standard demo tasks are running without error. Latch the - latest reported error in the pcStatusMessage character pointer. */ - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: GenQueue"; - } - - if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: QueuePeek\r\n"; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: BlockQueue\r\n"; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: BlockTime\r\n"; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: SemTest\r\n"; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: Death\r\n"; - } - - if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: RecMutex\r\n"; - } - - if( xAreComTestTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: ComTest\r\n"; - } - - if( xAreTimerDemoTasksStillRunning( ( mainCHECK_TIMER_PERIOD_MS ) ) != pdTRUE ) - { - pcStatusMessage = "Error: TimerDemo"; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: PollQueue"; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: CountSem"; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: DynamicPriority"; - } - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. vParTestToggleLED() - is not used to toggle this particular LED as it is on a different IP port - to to the LEDs controlled by ParTest.c. A critical section is not required - as the only other place this port is accessed is from another timer - and - only one timer can be running at any one time. */ - if( ( FM3_GPIO->PDOR3 & mainCHECK_LED ) != 0 ) - { - FM3_GPIO->PDOR3 &= ~mainCHECK_LED; - } - else - { - FM3_GPIO->PDOR3 |= mainCHECK_LED; - } - - /* Have any errors been latch in pcStatusMessage? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( pcStatusMessage != NULL ) - { - /* This call to xTimerChangePeriod() uses a zero block time. Functions - called from inside of a timer callback function must *never* attempt - to block. */ - xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } + /* Check the standard demo tasks are running without error. Latch the + * latest reported error in the pcStatusMessage character pointer. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: GenQueue"; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: QueuePeek\r\n"; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockQueue\r\n"; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockTime\r\n"; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: SemTest\r\n"; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: Death\r\n"; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: RecMutex\r\n"; + } + + if( xAreComTestTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: ComTest\r\n"; + } + + if( xAreTimerDemoTasksStillRunning( ( mainCHECK_TIMER_PERIOD_MS ) ) != pdTRUE ) + { + pcStatusMessage = "Error: TimerDemo"; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: PollQueue"; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: CountSem"; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: DynamicPriority"; + } + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. vParTestToggleLED() + * is not used to toggle this particular LED as it is on a different IP port + * to to the LEDs controlled by ParTest.c. A critical section is not required + * as the only other place this port is accessed is from another timer - and + * only one timer can be running at any one time. */ + if( ( FM3_GPIO->PDOR3 & mainCHECK_LED ) != 0 ) + { + FM3_GPIO->PDOR3 &= ~mainCHECK_LED; + } + else + { + FM3_GPIO->PDOR3 |= mainCHECK_LED; + } + + /* Have any errors been latch in pcStatusMessage? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( pcStatusMessage != NULL ) + { + /* This call to xTimerChangePeriod() uses a zero block time. Functions + * called from inside of a timer callback function must *never* attempt + * to block. */ + xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ static void prvLEDTimerCallback( TimerHandle_t xTimer ) { - /* The timer has expired - so no button pushes have occurred in the last - five seconds - turn the LED off. */ - vParTestSetLED( mainTIMER_CONTROLLED_LED, pdFALSE ); + /* The timer has expired - so no button pushes have occurred in the last + * five seconds - turn the LED off. */ + vParTestSetLED( mainTIMER_CONTROLLED_LED, pdFALSE ); } /*-----------------------------------------------------------*/ static void prvDigitCounterTimerCallback( TimerHandle_t xTimer ) { /* Define the bit patterns that display numbers on the seven segment display. */ -static const unsigned short usNumbersPatterns[] = { 0x8004, 0xF204, 0x4804, 0x6004, 0x3204, 0x2404, 0x0404, 0xF104, 0x0004, 0x2004 }; -static long lCounter = 0L; -const long lNumberOfDigits = 10L; -unsigned short usCheckLEDState; - - /* Unfortunately the LED uses the same port as the digit counter, so remember - the state of the check LED. A critical section is not required to access - the port as only one timer can be executing at any one time. */ - usCheckLEDState = ( FM3_GPIO->PDOR3 & mainCHECK_LED ); - - /* Display the next number, counting up. */ - FM3_GPIO->PDOR3 = usNumbersPatterns[ lCounter ] | usCheckLEDState; - - /* Move onto the next digit. */ - lCounter++; - - /* Ensure the counter does not go off the end of the array. */ - if( lCounter >= lNumberOfDigits ) - { - lCounter = 0L; - } + static const unsigned short usNumbersPatterns[] = { 0x8004, 0xF204, 0x4804, 0x6004, 0x3204, 0x2404, 0x0404, 0xF104, 0x0004, 0x2004 }; + static long lCounter = 0L; + const long lNumberOfDigits = 10L; + unsigned short usCheckLEDState; + + /* Unfortunately the LED uses the same port as the digit counter, so remember + * the state of the check LED. A critical section is not required to access + * the port as only one timer can be executing at any one time. */ + usCheckLEDState = ( FM3_GPIO->PDOR3 & mainCHECK_LED ); + + /* Display the next number, counting up. */ + FM3_GPIO->PDOR3 = usNumbersPatterns[ lCounter ] | usCheckLEDState; + + /* Move onto the next digit. */ + lCounter++; + + /* Ensure the counter does not go off the end of the array. */ + if( lCounter >= lNumberOfDigits ) + { + lCounter = 0L; + } } /*-----------------------------------------------------------*/ /* The ISR executed when the user button is pushed. */ void INT0_7_Handler( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* The button was pushed, so ensure the LED is on before resetting the - LED timer. The LED timer will turn the LED off if the button is not - pushed within 5000ms. */ - vParTestSetLEDFromISR( mainTIMER_CONTROLLED_LED, pdTRUE ); - - /* This interrupt safe FreeRTOS function can be called from this interrupt - because the interrupt priority is below the - configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ - xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); - - /* Clear the interrupt before leaving. This just clears all the interrupts - for simplicity, as only one is actually used in this simple demo anyway. */ - FM3_EXTI->EICL = 0x0000; - - /* If calling xTimerResetFromISR() caused a task (in this case the timer - service/daemon task) to unblock, and the unblocked task has a priority - higher than or equal to the task that was interrupted, then - xHigherPriorityTaskWoken will now be set to pdTRUE, and calling - portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* The button was pushed, so ensure the LED is on before resetting the + * LED timer. The LED timer will turn the LED off if the button is not + * pushed within 5000ms. */ + vParTestSetLEDFromISR( mainTIMER_CONTROLLED_LED, pdTRUE ); + + /* This interrupt safe FreeRTOS function can be called from this interrupt + * because the interrupt priority is below the + * configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ + xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); + + /* Clear the interrupt before leaving. This just clears all the interrupts + * for simplicity, as only one is actually used in this simple demo anyway. */ + FM3_EXTI->EICL = 0x0000; + + /* If calling xTimerResetFromISR() caused a task (in this case the timer + * service/daemon task) to unblock, and the unblocked task has a priority + * higher than or equal to the task that was interrupted, then + * xHigherPriorityTaskWoken will now be set to pdTRUE, and calling + * portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* The timer command queue will have been filled when the timer test tasks - were created in main() (this is part of the test they perform). Therefore, - while the check and digit counter timers can be created in main(), they - cannot be started from main(). Once the scheduler has started, the timer - service task will drain the command queue, and now the check and digit - counter timers can be started successfully. */ - xTimerStart( xCheckTimer, portMAX_DELAY ); - xTimerStart( xDigitCounterTimer, portMAX_DELAY ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle an LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* The timer command queue will have been filled when the timer test tasks + * were created in main() (this is part of the test they perform). Therefore, + * while the check and digit counter timers can be created in main(), they + * cannot be started from main(). Once the scheduler has started, the timer + * service task will drain the command queue, and now the check and digit + * counter timers can be started successfully. */ + xTimerStart( xCheckTimer, portMAX_DELAY ); + xTimerStart( xDigitCounterTimer, portMAX_DELAY ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle an LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - vParTestToggleLED( mainTASK_CONTROLLED_LED ); - } - } + unsigned long ulReceivedValue; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( mainTASK_CONTROLLED_LED ); + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -const unsigned short usButtonInputBit = 0x01U; + const unsigned short usButtonInputBit = 0x01U; - SystemInit(); - SystemCoreClockUpdate(); + SystemInit(); + SystemCoreClockUpdate(); - /* Initialise the IO used for the LEDs on the 7 segment displays. */ - vParTestInitialise(); + /* Initialise the IO used for the LEDs on the 7 segment displays. */ + vParTestInitialise(); - /* Set the switches to input (P18->P1F). */ - FM3_GPIO->DDR5 = 0x0000; - FM3_GPIO->PFR5 = 0x0000; + /* Set the switches to input (P18->P1F). */ + FM3_GPIO->DDR5 = 0x0000; + FM3_GPIO->PFR5 = 0x0000; - /* Assign the button input as GPIO. */ - FM3_GPIO->PFR5 |= usButtonInputBit; + /* Assign the button input as GPIO. */ + FM3_GPIO->PFR5 |= usButtonInputBit; - /* Button interrupt on falling edge. */ - FM3_EXTI->ELVR = 0x0003; + /* Button interrupt on falling edge. */ + FM3_EXTI->ELVR = 0x0003; - /* Clear all external interrupts. */ - FM3_EXTI->EICL = 0x0000; + /* Clear all external interrupts. */ + FM3_EXTI->EICL = 0x0000; - /* Enable the button interrupt. */ - FM3_EXTI->ENIR |= usButtonInputBit; + /* Enable the button interrupt. */ + FM3_EXTI->ENIR |= usButtonInputBit; - /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ - NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ + NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); NVIC_EnableIRQ( EXINT0_7_IRQn ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - for( ;; ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeStackSpace; - - /* This function is called on each cycle of the idle task. In this case it - does nothing useful, other than report the amount of FreeRTOS heap that - remains unallocated. */ - xFreeStackSpace = xPortGetFreeHeapSize(); - - if( xFreeStackSpace > 100 ) - { - /* By now, the kernel has allocated everything it is going to, so - if there is a lot of heap remaining unallocated then - the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be - reduced accordingly. */ - } + volatile size_t xFreeStackSpace; + + /* This function is called on each cycle of the idle task. In this case it + * does nothing useful, other than report the amount of FreeRTOS heap that + * remains unallocated. */ + xFreeStackSpace = xPortGetFreeHeapSize(); + + if( xFreeStackSpace > 100 ) + { + /* By now, the kernel has allocated everything it is going to, so + * if there is a lot of heap remaining unallocated then + * the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be + * reduced accordingly. */ + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* Call the periodic timer test, which tests the timer API functions that - can be called from an ISR. */ - vTimerPeriodicISRTests(); + /* Call the periodic timer test, which tests the timer API functions that + * can be called from an ISR. */ + vTimerPeriodicISRTests(); } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c index 7ce854a9428..9611e387d1a 100644 --- a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -84,23 +84,23 @@ #include "mcu.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue, specified in milliseconds, and -converted to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* The LED toggle by the queue receive task. */ -#define mainTASK_CONTROLLED_LED ( 1UL << 3UL ) +#define mainTASK_CONTROLLED_LED ( 1UL << 3UL ) /* The LED turned on by the button interrupt, and turned off by the LED timer. */ -#define mainTIMER_CONTROLLED_LED ( 1UL << 2UL ) +#define mainTIMER_CONTROLLED_LED ( 1UL << 2UL ) /*-----------------------------------------------------------*/ @@ -112,8 +112,8 @@ static void prvSetupHardware( void ); /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * The LED timer callback function. This does nothing but switch off the @@ -127,240 +127,243 @@ static void vLEDTimerCallback( TimerHandle_t xTimer ); static QueueHandle_t xQueue = NULL; /* The LED software timer. This uses vLEDTimerCallback() as its callback -function. */ + * function. */ static TimerHandle_t xLEDTimer = NULL; /*-----------------------------------------------------------*/ -int main(void) +int main( void ) { - /* Configure the NVIC, LED outputs and button inputs. */ - prvSetupHardware(); - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer that is responsible for turning off the LED - if the button is not pushed within 5000ms, as described at the top of - this file. */ - xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ - ( 5000 / portTICK_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ - pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - vLEDTimerCallback /* The callback function that switches the LED off. */ - ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + /* Configure the NVIC, LED outputs and button inputs. */ + prvSetupHardware(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer that is responsible for turning off the LED + * if the button is not pushed within 5000ms, as described at the top of + * this file. */ + xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ + ( 5000 / portTICK_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ + pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + vLEDTimerCallback /* The callback function that switches the LED off. */ + ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void vLEDTimerCallback( TimerHandle_t xTimer ) { - /* The timer has expired - so no button pushes have occurred in the last - five seconds - turn the LED off. NOTE - accessing the LED port should use - a critical section because it is accessed from multiple tasks, and the - button interrupt - in this trivial case, for simplicity, the critical - section is omitted. */ - FM3_GPIO->PDOR3 |= mainTIMER_CONTROLLED_LED; + /* The timer has expired - so no button pushes have occurred in the last + * five seconds - turn the LED off. NOTE - accessing the LED port should use + * a critical section because it is accessed from multiple tasks, and the + * button interrupt - in this trivial case, for simplicity, the critical + * section is omitted. */ + FM3_GPIO->PDOR3 |= mainTIMER_CONTROLLED_LED; } /*-----------------------------------------------------------*/ /* The ISR executed when the user button is pushed. */ void INT0_7_Handler( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* The button was pushed, so ensure the LED is on before resetting the - LED timer. The LED timer will turn the LED off if the button is not - pushed within 5000ms. */ - FM3_GPIO->PDOR3 &= ~mainTIMER_CONTROLLED_LED; - - /* This interrupt safe FreeRTOS function can be called from this interrupt - because the interrupt priority is below the - configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ - xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); - - /* Clear the interrupt before leaving. This just clears all the interrupts - for simplicity, as only one is actually used in this simple demo anyway. */ - FM3_EXTI->EICL = 0x0000; - - /* If calling xTimerResetFromISR() caused a task (in this case the timer - service/daemon task) to unblock, and the unblocked task has a priority - higher than or equal to the task that was interrupted, then - xHigherPriorityTaskWoken will now be set to pdTRUE, and calling - portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* The button was pushed, so ensure the LED is on before resetting the + * LED timer. The LED timer will turn the LED off if the button is not + * pushed within 5000ms. */ + FM3_GPIO->PDOR3 &= ~mainTIMER_CONTROLLED_LED; + + /* This interrupt safe FreeRTOS function can be called from this interrupt + * because the interrupt priority is below the + * configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ + xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); + + /* Clear the interrupt before leaving. This just clears all the interrupts + * for simplicity, as only one is actually used in this simple demo anyway. */ + FM3_EXTI->EICL = 0x0000; + + /* If calling xTimerResetFromISR() caused a task (in this case the timer + * service/daemon task) to unblock, and the unblocked task has a priority + * higher than or equal to the task that was interrupted, then + * xHigherPriorityTaskWoken will now be set to pdTRUE, and calling + * portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle an LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0 ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle an LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0 ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - /* NOTE - accessing the LED port should use a critical section - because it is accessed from multiple tasks, and the button interrupt - - in this trivial case, for simplicity, the critical section is - omitted. */ - if( ( FM3_GPIO->PDOR3 & mainTASK_CONTROLLED_LED ) != 0 ) - { - FM3_GPIO->PDOR3 &= ~mainTASK_CONTROLLED_LED; - } - else - { - FM3_GPIO->PDOR3 |= mainTASK_CONTROLLED_LED; - } - } - } + unsigned long ulReceivedValue; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + /* NOTE - accessing the LED port should use a critical section + * because it is accessed from multiple tasks, and the button interrupt + * - in this trivial case, for simplicity, the critical section is + * omitted. */ + if( ( FM3_GPIO->PDOR3 & mainTASK_CONTROLLED_LED ) != 0 ) + { + FM3_GPIO->PDOR3 &= ~mainTASK_CONTROLLED_LED; + } + else + { + FM3_GPIO->PDOR3 |= mainTASK_CONTROLLED_LED; + } + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -const unsigned short usButtonInputBit = 0x01U; + const unsigned short usButtonInputBit = 0x01U; - SystemInit(); - SystemCoreClockUpdate(); + SystemInit(); + SystemCoreClockUpdate(); - /* Analog inputs are not used on the LED outputs. */ - FM3_GPIO->ADE = 0x0000; + /* Analog inputs are not used on the LED outputs. */ + FM3_GPIO->ADE = 0x0000; - /* Set to output. */ - FM3_GPIO->DDR1 |= 0xFFFF; - FM3_GPIO->DDR3 |= 0xFFFF; + /* Set to output. */ + FM3_GPIO->DDR1 |= 0xFFFF; + FM3_GPIO->DDR3 |= 0xFFFF; - /* Set as GPIO. */ - FM3_GPIO->PFR1 &= 0x0000; - FM3_GPIO->PFR3 &= 0x0000; + /* Set as GPIO. */ + FM3_GPIO->PFR1 &= 0x0000; + FM3_GPIO->PFR3 &= 0x0000; - /* Start with all LEDs off. */ - FM3_GPIO->PDOR3 = 0xFFFF; - FM3_GPIO->PDOR1 = 0xFFFF; + /* Start with all LEDs off. */ + FM3_GPIO->PDOR3 = 0xFFFF; + FM3_GPIO->PDOR1 = 0xFFFF; - /* Set the switches to input (P18->P1F). */ - FM3_GPIO->DDR5 = 0x0000; - FM3_GPIO->PFR5 = 0x0000; + /* Set the switches to input (P18->P1F). */ + FM3_GPIO->DDR5 = 0x0000; + FM3_GPIO->PFR5 = 0x0000; - /* Assign the button input as GPIO. */ - FM3_GPIO->PFR5 |= usButtonInputBit; + /* Assign the button input as GPIO. */ + FM3_GPIO->PFR5 |= usButtonInputBit; - /* Button interrupt on falling edge. */ - FM3_EXTI->ELVR = 0x0003; + /* Button interrupt on falling edge. */ + FM3_EXTI->ELVR = 0x0003; - /* Clear all external interrupts. */ - FM3_EXTI->EICL = 0x0000; + /* Clear all external interrupts. */ + FM3_EXTI->EICL = 0x0000; - /* Enable the button interrupt. */ - FM3_EXTI->ENIR |= usButtonInputBit; + /* Enable the button interrupt. */ + FM3_EXTI->ENIR |= usButtonInputBit; - /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ - NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ + NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); NVIC_EnableIRQ( EXINT0_7_IRQn ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - for( ;; ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* A tick hook is used by the "Full" build configuration. The Full and - blinky build configurations share a FreeRTOSConfig.h header file, so this - simple build configuration also has to define a tick hook - even though it - does not actually use it for anything. */ + /* A tick hook is used by the "Full" build configuration. The Full and + * blinky build configurations share a FreeRTOSConfig.h header file, so this + * simple build configuration also has to define a tick hook - even though it + * does not actually use it for anything. */ } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This function is called on each cycle of the idle task. In this case it - does nothing useful, other than report the amount of FreeRTOS heap that - remains unallocated. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - if( xFreeHeapSpace > 100 ) - { - /* By now, the kernel has allocated everything it is going to, so - if there is a lot of heap remaining unallocated then - the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be - reduced accordingly. */ - } + volatile size_t xFreeHeapSpace; + + /* This function is called on each cycle of the idle task. In this case it + * does nothing useful, other than report the amount of FreeRTOS heap that + * remains unallocated. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + if( xFreeHeapSpace > 100 ) + { + /* By now, the kernel has allocated everything it is going to, so + * if there is a lot of heap remaining unallocated then + * the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be + * reduced accordingly. */ + } } /*-----------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/serial.c b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/serial.c index b7b18094d61..db59a134878 100644 --- a/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/serial.c +++ b/FreeRTOS/Demo/CORTEX_MB9A310_IAR_Keil/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h index 414af4167e7..aff770ec947 100644 --- a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/ParTest.c b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/ParTest.c index 5f9bfc41ede..76cb536bcda 100644 --- a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main-full.c b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main-full.c index 05b55f82732..998d5f32221 100644 --- a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main-full.c +++ b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -136,77 +136,77 @@ #include "dynamic.h" /* The rate at which data is sent to the queue, specified in milliseconds, and -converted to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* The LED toggled by the check timer callback function. This is an LED in the -second digit of the two digit 7 segment display. See the documentation page -for this demo on the FreeRTOS.org web site to see which LED this relates to. */ -#define mainCHECK_LED 0x07UL + * second digit of the two digit 7 segment display. See the documentation page + * for this demo on the FreeRTOS.org web site to see which LED this relates to. */ +#define mainCHECK_LED 0x07UL /* The LED toggle by the queue receive task. This is an LED in the second digit -of the two digit 7 segment display. See the documentation page for this demo on -the FreeRTOS.org web site to see which LED this relates to. */ -#define mainTASK_CONTROLLED_LED 0x06UL + * of the two digit 7 segment display. See the documentation page for this demo on + * the FreeRTOS.org web site to see which LED this relates to. */ +#define mainTASK_CONTROLLED_LED 0x06UL /* The LED turned on by the button interrupt, and turned off by the LED timer. -This is an LED in the second digit of the two digit 7 segment display. See the -documentation page for this demo on the FreeRTOS.org web site to see which LED -this relates to. */ -#define mainTIMER_CONTROLLED_LED 0x05UL + * This is an LED in the second digit of the two digit 7 segment display. See the + * documentation page for this demo on the FreeRTOS.org web site to see which LED + * this relates to. */ +#define mainTIMER_CONTROLLED_LED 0x05UL /* The LED used by the comtest tasks. See the comtest.c file for more -information. The LEDs used by the comtest task are in the second digit of the -two digit 7 segment display. See the documentation page for this demo on the -FreeRTOS.org web site to see which LEDs this relates to. */ -#define mainCOM_TEST_LED ( 3 ) + * information. The LEDs used by the comtest task are in the second digit of the + * two digit 7 segment display. See the documentation page for this demo on the + * FreeRTOS.org web site to see which LEDs this relates to. */ +#define mainCOM_TEST_LED ( 3 ) /* Constant used by the standard timer test functions. */ -#define mainTIMER_TEST_PERIOD ( 50 ) +#define mainTIMER_TEST_PERIOD ( 50 ) /* Priorities used by the various different standard demo tasks. */ -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* Priorities defined in this main-full.c file. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The period at which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 500UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 500UL / portTICK_PERIOD_MS ) /* The period at which the digit counter timer will expire, in ms, and converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainDIGIT_COUNTER_TIMER_PERIOD_MS ( 250UL / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainDIGIT_COUNTER_TIMER_PERIOD_MS ( 250UL / portTICK_PERIOD_MS ) /* The LED will remain on until the button has not been pushed for a full -5000ms. */ -#define mainLED_TIMER_PERIOD_MS ( 5000UL / portTICK_PERIOD_MS ) + * 5000ms. */ +#define mainLED_TIMER_PERIOD_MS ( 5000UL / portTICK_PERIOD_MS ) /* A zero block time. */ -#define mainDONT_BLOCK ( 0UL ) +#define mainDONT_BLOCK ( 0UL ) /* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 115200UL ) +#define mainCOM_TEST_BAUD_RATE ( 115200UL ) /*-----------------------------------------------------------*/ @@ -219,8 +219,8 @@ static void prvSetupHardware( void ); * The application specific (not common demo) tasks as described in the comments * at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * The LED timer callback function. This does nothing but switch an LED off. @@ -241,7 +241,8 @@ static void prvDigitCounterTimerCallback( TimerHandle_t xTimer ); * This is not a 'standard' partest function, so the prototype is not in * partest.h, and is instead included here. */ -void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ); +void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, + signed portBASE_TYPE xValue ); /*-----------------------------------------------------------*/ @@ -249,377 +250,384 @@ void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE x static QueueHandle_t xQueue = NULL; /* The LED software timer. This uses prvLEDTimerCallback() as it's callback -function. */ + * function. */ static TimerHandle_t xLEDTimer = NULL; /* The digit counter software timer. This displays a counting digit on one half -of the seven segment displays. */ + * of the seven segment displays. */ static TimerHandle_t xDigitCounterTimer = NULL; /* The check timer. This uses prvCheckTimerCallback() as its callback -function. */ + * function. */ static TimerHandle_t xCheckTimer = NULL; /* If an error is detected in a standard demo task, then pcStatusMessage will -be set to point to a string that identifies the offending task. This is just -to make debugging easier. */ -static const char *pcStatusMessage = NULL; + * be set to point to a string that identifies the offending task. This is just + * to make debugging easier. */ +static const char * pcStatusMessage = NULL; /*-----------------------------------------------------------*/ -int main(void) +int main( void ) { - /* Configure the NVIC, LED outputs and button inputs. */ - prvSetupHardware(); - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two application specific demo tasks, as described in the - comments at the top of this file. */ - xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer that is responsible for turning off the LED - if the button is not pushed within 5000ms, as described at the top of - this file. */ - xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ - ( mainLED_TIMER_PERIOD_MS ),/* The timer period, in this case 5000ms (5s). */ - pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvLEDTimerCallback /* The callback function that switches the LED off. */ - ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* Create the software timer that performs the 'digit counting' - functionality, as described at the top of this file. */ - xDigitCounterTimer = xTimerCreate( "DigitCounter", /* A text name, purely to help debugging. */ - ( mainDIGIT_COUNTER_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvDigitCounterTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* Create a lot of 'standard demo' tasks. Over 40 tasks are created in - this demo. For a much simpler demo, select the 'blinky' build - configuration. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); - vStartQueuePeekTasks(); - vStartRecursiveMutexTasks(); - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartCountingSemaphoreTasks(); - vStartDynamicPriorityTasks(); - - /* The suicide tasks must be created last, as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given - time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + /* Configure the NVIC, LED outputs and button inputs. */ + prvSetupHardware(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two application specific demo tasks, as described in the + * comments at the top of this file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer that is responsible for turning off the LED + * if the button is not pushed within 5000ms, as described at the top of + * this file. */ + xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ + ( mainLED_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ + pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvLEDTimerCallback /* The callback function that switches the LED off. */ + ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* Create the software timer that performs the 'digit counting' + * functionality, as described at the top of this file. */ + xDigitCounterTimer = xTimerCreate( "DigitCounter", /* A text name, purely to help debugging. */ + ( mainDIGIT_COUNTER_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvDigitCounterTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* Create a lot of 'standard demo' tasks. Over 40 tasks are created in + * this demo. For a much simpler demo, select the 'blinky' build + * configuration. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartRecursiveMutexTasks(); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartCountingSemaphoreTasks(); + vStartDynamicPriorityTasks(); + + /* The suicide tasks must be created last, as they need to know how many + * tasks were running prior to their creation in order to ascertain whether + * or not the correct/expected number of tasks are running at any given + * time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { - /* Check the standard demo tasks are running without error. Latch the - latest reported error in the pcStatusMessage character pointer. */ - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: GenQueue"; - } - - if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: QueuePeek\r\n"; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: BlockQueue\r\n"; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: BlockTime\r\n"; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: SemTest\r\n"; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: Death\r\n"; - } - - if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: RecMutex\r\n"; - } - - if( xAreComTestTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: ComTest\r\n"; - } - - if( xAreTimerDemoTasksStillRunning( ( mainCHECK_TIMER_PERIOD_MS ) ) != pdTRUE ) - { - pcStatusMessage = "Error: TimerDemo"; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: PollQueue"; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: CountSem"; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: DynamicPriority"; - } - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - /* Have any errors been latch in pcStatusMessage? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( pcStatusMessage != NULL ) - { - /* This call to xTimerChangePeriod() uses a zero block time. Functions - called from inside of a timer callback function must *never* attempt - to block. */ - xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } + /* Check the standard demo tasks are running without error. Latch the + * latest reported error in the pcStatusMessage character pointer. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: GenQueue"; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: QueuePeek\r\n"; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockQueue\r\n"; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockTime\r\n"; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: SemTest\r\n"; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: Death\r\n"; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: RecMutex\r\n"; + } + + if( xAreComTestTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: ComTest\r\n"; + } + + if( xAreTimerDemoTasksStillRunning( ( mainCHECK_TIMER_PERIOD_MS ) ) != pdTRUE ) + { + pcStatusMessage = "Error: TimerDemo"; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: PollQueue"; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: CountSem"; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: DynamicPriority"; + } + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + * everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Have any errors been latch in pcStatusMessage? If so, shorten the + * period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + * This will result in an increase in the rate at which mainCHECK_LED + * toggles. */ + if( pcStatusMessage != NULL ) + { + /* This call to xTimerChangePeriod() uses a zero block time. Functions + * called from inside of a timer callback function must *never* attempt + * to block. */ + xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ static void prvLEDTimerCallback( TimerHandle_t xTimer ) { - /* The timer has expired - so no button pushes have occurred in the last - five seconds - turn the LED off. */ - vParTestSetLED( mainTIMER_CONTROLLED_LED, pdFALSE ); + /* The timer has expired - so no button pushes have occurred in the last + * five seconds - turn the LED off. */ + vParTestSetLED( mainTIMER_CONTROLLED_LED, pdFALSE ); } /*-----------------------------------------------------------*/ static void prvDigitCounterTimerCallback( TimerHandle_t xTimer ) { /* Define the bit patterns that display numbers on the seven segment display. */ -static const unsigned short usNumbersPatterns[] = { 0xC000U, 0xF900U, 0xA400U, 0xB000U, 0x9900U, 0x9200U, 0x8200U, 0xF800U, 0x8000U, 0x9000U }; -static long lCounter = 0L; -const long lNumberOfDigits = 10L; + static const unsigned short usNumbersPatterns[] = { 0xC000U, 0xF900U, 0xA400U, 0xB000U, 0x9900U, 0x9200U, 0x8200U, 0xF800U, 0x8000U, 0x9000U }; + static long lCounter = 0L; + const long lNumberOfDigits = 10L; - /* Display the next number, counting up. */ - FM3_GPIO->PDOR1 = usNumbersPatterns[ lCounter ]; + /* Display the next number, counting up. */ + FM3_GPIO->PDOR1 = usNumbersPatterns[ lCounter ]; - /* Move onto the next digit. */ - lCounter++; + /* Move onto the next digit. */ + lCounter++; - /* Ensure the counter does not go off the end of the array. */ - if( lCounter >= lNumberOfDigits ) - { - lCounter = 0L; - } + /* Ensure the counter does not go off the end of the array. */ + if( lCounter >= lNumberOfDigits ) + { + lCounter = 0L; + } } /*-----------------------------------------------------------*/ /* The ISR executed when the user button is pushed. */ void INT0_7_Handler( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* The button was pushed, so ensure the LED is on before resetting the - LED timer. The LED timer will turn the LED off if the button is not - pushed within 5000ms. */ - vParTestSetLEDFromISR( mainTIMER_CONTROLLED_LED, pdTRUE ); - - /* This interrupt safe FreeRTOS function can be called from this interrupt - because the interrupt priority is below the - configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ - xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); - - /* Clear the interrupt before leaving. This just clears all the interrupts - for simplicity, as only one is actually used in this simple demo anyway. */ - FM3_EXTI->EICL = 0x0000; - - /* If calling xTimerResetFromISR() caused a task (in this case the timer - service/daemon task) to unblock, and the unblocked task has a priority - higher than or equal to the task that was interrupted, then - xHigherPriorityTaskWoken will now be set to pdTRUE, and calling - portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* The button was pushed, so ensure the LED is on before resetting the + * LED timer. The LED timer will turn the LED off if the button is not + * pushed within 5000ms. */ + vParTestSetLEDFromISR( mainTIMER_CONTROLLED_LED, pdTRUE ); + + /* This interrupt safe FreeRTOS function can be called from this interrupt + * because the interrupt priority is below the + * configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ + xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); + + /* Clear the interrupt before leaving. This just clears all the interrupts + * for simplicity, as only one is actually used in this simple demo anyway. */ + FM3_EXTI->EICL = 0x0000; + + /* If calling xTimerResetFromISR() caused a task (in this case the timer + * service/daemon task) to unblock, and the unblocked task has a priority + * higher than or equal to the task that was interrupted, then + * xHigherPriorityTaskWoken will now be set to pdTRUE, and calling + * portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* The timer command queue will have been filled when the timer test tasks - were created in main() (this is part of the test they perform). Therefore, - while the check and digit counter timers can be created in main(), they - cannot be started from main(). Once the scheduler has started, the timer - service task will drain the command queue, and now the check and digit - counter timers can be started successfully. */ - xTimerStart( xCheckTimer, portMAX_DELAY ); - xTimerStart( xDigitCounterTimer, portMAX_DELAY ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle an LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* The timer command queue will have been filled when the timer test tasks + * were created in main() (this is part of the test they perform). Therefore, + * while the check and digit counter timers can be created in main(), they + * cannot be started from main(). Once the scheduler has started, the timer + * service task will drain the command queue, and now the check and digit + * counter timers can be started successfully. */ + xTimerStart( xCheckTimer, portMAX_DELAY ); + xTimerStart( xDigitCounterTimer, portMAX_DELAY ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle an LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - vParTestToggleLED( mainTASK_CONTROLLED_LED ); - } - } + unsigned long ulReceivedValue; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vParTestToggleLED( mainTASK_CONTROLLED_LED ); + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -const unsigned short usButtonInputBit = 0x01U; + const unsigned short usButtonInputBit = 0x01U; - SystemInit(); - SystemCoreClockUpdate(); + SystemInit(); + SystemCoreClockUpdate(); - /* Initialise the IO used for the LEDs on the 7 segment displays. */ - vParTestInitialise(); + /* Initialise the IO used for the LEDs on the 7 segment displays. */ + vParTestInitialise(); - /* Set the switches to input (P18->P1F). */ - FM3_GPIO->DDR5 = 0x0000; - FM3_GPIO->PFR5 = 0x0000; + /* Set the switches to input (P18->P1F). */ + FM3_GPIO->DDR5 = 0x0000; + FM3_GPIO->PFR5 = 0x0000; - /* Assign the button input as GPIO. */ - FM3_GPIO->PFR1 |= usButtonInputBit; + /* Assign the button input as GPIO. */ + FM3_GPIO->PFR1 |= usButtonInputBit; - /* Button interrupt on falling edge. */ - FM3_EXTI->ELVR = 0x0003; + /* Button interrupt on falling edge. */ + FM3_EXTI->ELVR = 0x0003; - /* Clear all external interrupts. */ - FM3_EXTI->EICL = 0x0000; + /* Clear all external interrupts. */ + FM3_EXTI->EICL = 0x0000; - /* Enable the button interrupt. */ - FM3_EXTI->ENIR |= usButtonInputBit; + /* Enable the button interrupt. */ + FM3_EXTI->ENIR |= usButtonInputBit; - /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ - NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ + NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); NVIC_EnableIRQ( EXINT0_7_IRQn ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - for( ;; ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeStackSpace; - - /* This function is called on each cycle of the idle task. In this case it - does nothing useful, other than report the amount of FreeRTOS heap that - remains unallocated. */ - xFreeStackSpace = xPortGetFreeHeapSize(); - - if( xFreeStackSpace > 100 ) - { - /* By now, the kernel has allocated everything it is going to, so - if there is a lot of heap remaining unallocated then - the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be - reduced accordingly. */ - } + volatile size_t xFreeStackSpace; + + /* This function is called on each cycle of the idle task. In this case it + * does nothing useful, other than report the amount of FreeRTOS heap that + * remains unallocated. */ + xFreeStackSpace = xPortGetFreeHeapSize(); + + if( xFreeStackSpace > 100 ) + { + /* By now, the kernel has allocated everything it is going to, so + * if there is a lot of heap remaining unallocated then + * the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be + * reduced accordingly. */ + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* Call the periodic timer test, which tests the timer API functions that - can be called from an ISR. */ - vTimerPeriodicISRTests(); + /* Call the periodic timer test, which tests the timer API functions that + * can be called from an ISR. */ + vTimerPeriodicISRTests(); } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c index 618efa2d810..bdc689dd542 100644 --- a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -85,23 +85,23 @@ #include "system_mb9bf50x.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue, specified in milliseconds, and -converted to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* The LED toggle by the queue receive task. */ -#define mainTASK_CONTROLLED_LED 0x8000UL +#define mainTASK_CONTROLLED_LED 0x8000UL /* The LED turned on by the button interrupt, and turned off by the LED timer. */ -#define mainTIMER_CONTROLLED_LED 0x8000UL +#define mainTIMER_CONTROLLED_LED 0x8000UL /*-----------------------------------------------------------*/ @@ -113,8 +113,8 @@ static void prvSetupHardware( void ); /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * The LED timer callback function. This does nothing but switch off the @@ -128,241 +128,244 @@ static void vLEDTimerCallback( TimerHandle_t xTimer ); static QueueHandle_t xQueue = NULL; /* The LED software timer. This uses vLEDTimerCallback() as its callback -function. */ + * function. */ static TimerHandle_t xLEDTimer = NULL; /*-----------------------------------------------------------*/ -int main(void) +int main( void ) { - /* Configure the NVIC, LED outputs and button inputs. */ - prvSetupHardware(); - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer that is responsible for turning off the LED - if the button is not pushed within 5000ms, as described at the top of - this file. */ - xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ - ( 5000 / portTICK_PERIOD_MS ),/* The timer period, in this case 5000ms (5s). */ - pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - vLEDTimerCallback /* The callback function that switches the LED off. */ - ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); + /* Configure the NVIC, LED outputs and button inputs. */ + prvSetupHardware(); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer that is responsible for turning off the LED + * if the button is not pushed within 5000ms, as described at the top of + * this file. */ + xLEDTimer = xTimerCreate( "LEDTimer", /* A text name, purely to help debugging. */ + ( 5000 / portTICK_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ + pdFALSE, /* This is a one-shot timer, so xAutoReload is set to pdFALSE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + vLEDTimerCallback /* The callback function that switches the LED off. */ + ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following line + * will never be reached. If the following line does execute, then there was + * insufficient FreeRTOS heap memory available for the idle and/or timer tasks + * to be created. See the memory management section on the FreeRTOS web site + * for more details. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void vLEDTimerCallback( TimerHandle_t xTimer ) { - /* The timer has expired - so no button pushes have occurred in the last - five seconds - turn the LED off. NOTE - accessing the LED port should use - a critical section because it is accessed from multiple tasks, and the - button interrupt - in this trivial case, for simplicity, the critical - section is omitted. */ - FM3_GPIO->PDOR1 |= mainTIMER_CONTROLLED_LED; + /* The timer has expired - so no button pushes have occurred in the last + * five seconds - turn the LED off. NOTE - accessing the LED port should use + * a critical section because it is accessed from multiple tasks, and the + * button interrupt - in this trivial case, for simplicity, the critical + * section is omitted. */ + FM3_GPIO->PDOR1 |= mainTIMER_CONTROLLED_LED; } /*-----------------------------------------------------------*/ /* The ISR executed when the user button is pushed. */ void INT0_7_Handler( void ) { -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* The button was pushed, so ensure the LED is on before resetting the - LED timer. The LED timer will turn the LED off if the button is not - pushed within 5000ms. */ - FM3_GPIO->PDOR1 &= ~mainTIMER_CONTROLLED_LED; - - /* This interrupt safe FreeRTOS function can be called from this interrupt - because the interrupt priority is below the - configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ - xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); - - /* Clear the interrupt before leaving. This just clears all the interrupts - for simplicity, as only one is actually used in this simple demo anyway. */ - FM3_EXTI->EICL = 0x0000; - - /* If calling xTimerResetFromISR() caused a task (in this case the timer - service/daemon task) to unblock, and the unblocked task has a priority - higher than or equal to the task that was interrupted, then - xHigherPriorityTaskWoken will now be set to pdTRUE, and calling - portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* The button was pushed, so ensure the LED is on before resetting the + * LED timer. The LED timer will turn the LED off if the button is not + * pushed within 5000ms. */ + FM3_GPIO->PDOR1 &= ~mainTIMER_CONTROLLED_LED; + + /* This interrupt safe FreeRTOS function can be called from this interrupt + * because the interrupt priority is below the + * configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */ + xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken ); + + /* Clear the interrupt before leaving. This just clears all the interrupts + * for simplicity, as only one is actually used in this simple demo anyway. */ + FM3_EXTI->EICL = 0x0000; + + /* If calling xTimerResetFromISR() caused a task (in this case the timer + * service/daemon task) to unblock, and the unblocked task has a priority + * higher than or equal to the task that was interrupted, then + * xHigherPriorityTaskWoken will now be set to pdTRUE, and calling + * portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */ + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle an LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0 ); - } + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, the constant used converts ticks + * to ms. While in the Blocked state this task will not consume any CPU + * time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + * toggle an LED. 0 is used as the block time so the sending operation + * will not block - it shouldn't need to block as the queue should always + * be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0 ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - /* NOTE - accessing the LED port should use a critical section - because it is accessed from multiple tasks, and the button interrupt - - in this trivial case, for simplicity, the critical section is - omitted. */ - if( ( FM3_GPIO->PDOR3 & mainTASK_CONTROLLED_LED ) != 0 ) - { - FM3_GPIO->PDOR3 &= ~mainTASK_CONTROLLED_LED; - } - else - { - FM3_GPIO->PDOR3 |= mainTASK_CONTROLLED_LED; - } - } - } + unsigned long ulReceivedValue; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + /* NOTE - accessing the LED port should use a critical section + * because it is accessed from multiple tasks, and the button interrupt + * - in this trivial case, for simplicity, the critical section is + * omitted. */ + if( ( FM3_GPIO->PDOR3 & mainTASK_CONTROLLED_LED ) != 0 ) + { + FM3_GPIO->PDOR3 &= ~mainTASK_CONTROLLED_LED; + } + else + { + FM3_GPIO->PDOR3 |= mainTASK_CONTROLLED_LED; + } + } + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -const unsigned short usButtonInputBit = 0x01U; -const unsigned short usGPIOState = 0xFF00U; + const unsigned short usButtonInputBit = 0x01U; + const unsigned short usGPIOState = 0xFF00U; - SystemInit(); - SystemCoreClockUpdate(); + SystemInit(); + SystemCoreClockUpdate(); - /* Analog inputs are not used on the LED outputs. */ - FM3_GPIO->ADE = 0x00FF; + /* Analog inputs are not used on the LED outputs. */ + FM3_GPIO->ADE = 0x00FF; - /* LED seg1 to GPIO output (P18->P1F). */ - FM3_GPIO->DDR1 = 0xFF00; - FM3_GPIO->PFR1 = 0x0000; + /* LED seg1 to GPIO output (P18->P1F). */ + FM3_GPIO->DDR1 = 0xFF00; + FM3_GPIO->PFR1 = 0x0000; - /* LED seg2 to GPIO output (P30->P3F). */ - FM3_GPIO->DDR3 = 0xFF00; - FM3_GPIO->PFR3 = 0x0000; + /* LED seg2 to GPIO output (P30->P3F). */ + FM3_GPIO->DDR3 = 0xFF00; + FM3_GPIO->PFR3 = 0x0000; - /* Start with all LEDs off. */ - FM3_GPIO->PDOR3 = usGPIOState; - FM3_GPIO->PDOR1 = usGPIOState; + /* Start with all LEDs off. */ + FM3_GPIO->PDOR3 = usGPIOState; + FM3_GPIO->PDOR1 = usGPIOState; - /* Set the switches to input (P18->P1F). */ - FM3_GPIO->DDR5 = 0x0000; - FM3_GPIO->PFR5 = 0x0000; + /* Set the switches to input (P18->P1F). */ + FM3_GPIO->DDR5 = 0x0000; + FM3_GPIO->PFR5 = 0x0000; - /* Assign the button input as GPIO. */ - FM3_GPIO->PFR1 |= usButtonInputBit; + /* Assign the button input as GPIO. */ + FM3_GPIO->PFR1 |= usButtonInputBit; - /* Button interrupt on falling edge. */ - FM3_EXTI->ELVR = 0x0003; + /* Button interrupt on falling edge. */ + FM3_EXTI->ELVR = 0x0003; - /* Clear all external interrupts. */ - FM3_EXTI->EICL = 0x0000; + /* Clear all external interrupts. */ + FM3_EXTI->EICL = 0x0000; - /* Enable the button interrupt. */ - FM3_EXTI->ENIR |= usButtonInputBit; + /* Enable the button interrupt. */ + FM3_EXTI->ENIR |= usButtonInputBit; - /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ - NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + /* Setup the GPIO and the NVIC for the switch used in this simple demo. */ + NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); NVIC_EnableIRQ( EXINT0_7_IRQn ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - for( ;; ); + /* Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* A tick hook is used by the "Full" build configuration. The Full and - blinky build configurations share a FreeRTOSConfig.h header file, so this - simple build configuration also has to define a tick hook - even though it - does not actually use it for anything. */ + /* A tick hook is used by the "Full" build configuration. The Full and + * blinky build configurations share a FreeRTOSConfig.h header file, so this + * simple build configuration also has to define a tick hook - even though it + * does not actually use it for anything. */ } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; - - /* This function is called on each cycle of the idle task. In this case it - does nothing useful, other than report the amount of FreeRTOS heap that - remains unallocated. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - if( xFreeHeapSpace > 100 ) - { - /* By now, the kernel has allocated everything it is going to, so - if there is a lot of heap remaining unallocated then - the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be - reduced accordingly. */ - } + volatile size_t xFreeHeapSpace; + + /* This function is called on each cycle of the idle task. In this case it + * does nothing useful, other than report the amount of FreeRTOS heap that + * remains unallocated. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + if( xFreeHeapSpace > 100 ) + { + /* By now, the kernel has allocated everything it is going to, so + * if there is a lot of heap remaining unallocated then + * the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be + * reduced accordingly. */ + } } /*-----------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/serial.c b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/serial.c index 9543039ccd5..78883d89b2b 100644 --- a/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/serial.c +++ b/FreeRTOS/Demo/CORTEX_MB9B500_IAR_Keil/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h index 3a122e4a9c6..9ff3e88098c 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -28,104 +28,114 @@ #define FREERTOS_CONFIG_H /*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -#define configUSE_TRACE_FACILITY 0 -#define configGENERATE_RUN_TIME_STATS 0 - -#define configUSE_TICKLESS_IDLE 0 -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( ( unsigned long ) 25000000 ) -#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 60 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_QUEUE_SETS 1 -#define configUSE_COUNTING_SEMAPHORES 1 - -#define configMAX_PRIORITIES ( 9UL ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) -#define configQUEUE_REGISTRY_SIZE 10 -#define configSUPPORT_STATIC_ALLOCATION 1 +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html +*----------------------------------------------------------*/ + +#define configGENERATE_RUN_TIME_STATS 0 + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 25000000 ) +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 60 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) + +/* TODO TraceRecorder (Step 4): Enable configUSE_TRACE_FACILITY in FreeRTOSConfig.h. */ +#define configUSE_TRACE_FACILITY 1 + +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 + +#define configMAX_PRIORITIES ( 9UL ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) +#define configQUEUE_REGISTRY_SIZE 10 +#define configSUPPORT_STATIC_ALLOCATION 1 /* Timer related defines. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 4 ) -#define configTIMER_QUEUE_LENGTH 20 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) -#define configUSE_TASK_NOTIFICATIONS 1 -#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3 /* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskAbortDelay 1 -#define INCLUDE_xTaskGetHandle 1 - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -#define configKERNEL_INTERRUPT_PRIORITY ( 255 ) /* All eight bits as QEMU doesn't model the priority bits. */ + * to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 + +/* This demo makes use of one or more example stats formatting functions. These + * format the raw data provided by the uxTaskGetSystemState() function in to human + * readable ASCII form. See the notes in the implementation of vTaskList() within + * FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +#define configKERNEL_INTERRUPT_PRIORITY ( 255 ) /* All eight bits as QEMU doesn't model the priority bits. */ + + /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! -See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 4 ) + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 4 ) /* Use the Cortex-M3 optimised task selection rather than the generic C code -version. */ -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + * version. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 /* The Win32 target is capable of running all the tests tasks at the same * time. */ -#define configRUN_ADDITIONAL_TESTS 1 +#define configRUN_ADDITIONAL_TESTS 1 /* The test that checks the trigger level on stream buffers requires an -allowable margin of error on slower processors (slower than the Win32 -machine on which the test is developed). */ -#define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 4 + * allowable margin of error on slower processors (slower than the Win32 + * machine on which the test is developed). */ +#define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 4 #ifndef __IASMARM__ /* Prevent C code being included in IAR asm files. */ - void vAssertCalled( const char *pcFileName, uint32_t ulLine ); - #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); + void vAssertCalled( const char * pcFileName, + uint32_t ulLine ); + #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); #endif -#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 5 ) -#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) -#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 5 ) +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) + +#define configENABLE_BACKWARD_COMPATIBILITY 0 + +/* TODO TraceRecorder (Step 5): Include trcRecorder.h at the end of FreeRTOSConfig.h. */ +#include "trcRecorder.h" #endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c index 582a220efd9..b47c8e5fd1a 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h index 0b63235944f..e393ad8274d 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Readme.md b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Readme.md index 7ec0f47c496..061db09c1d8 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Readme.md +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Readme.md @@ -11,3 +11,31 @@ 2. Open ```.vscode/launch.json```, and ensure the ```miDebuggerPath``` variable is set to the path where arm-none-eabi-gdb is on your machine. 3. Open ```main.c```, and set ```mainCREATE_SIMPLE_BLINKY_DEMO_ONLY``` to ```1``` to generate just the [simply blinky demo](https://www.freertos.org/a00102.html#simple_blinky_demo). 4. On the VSCode left side panel, select the “Run and Debug†button. Then select “Launch QEMU RTOSDemo†from the dropdown on the top right and press the play button. This will build, run, and attach a debugger to the demo program. + +## Tracing with Percepio View +This demo project includes Percepio TraceRecorder, configured for snapshot tracing with Percepio View or Tracealyzer. +Percepio View is a free tracing tool from Percepio, providing the core features of Percepio Tracealyzer but limited to snapshot tracing. +No license or registration is required. More information and download is found at [Percepio's product page for Percepio View](https://traceviewer.io/freertos-view). + +### TraceRecorder Integration +If you like to study how TraceRecorder is integrated, the steps for adding TraceRecorder are tagged with "TODO TraceRecorder" comments in the demo source code. +This way, if using an Eclipse-based IDE, you can find a summary in the Tasks window by selecting Window -> Show View -> Tasks (or Other, if not listed). +See also [the official getting-started guide](https://traceviewer.io/getting-started-freertos-view). + +### Usage with GCC +To save the TraceRecorder trace, start a debug session with GDB, for example using the provided Eclipse launch profile (should work in most Eclipse-based IDEs). +Halt the execution and the run the command below. +This saves the trace as trace.bin in the build/gcc folder. +Open the trace file in Percepio View or Tracealyzer. + +``` +dump binary value trace.bin *RecorderDataPtr +``` +Note that you can copy/paste this command into the Eclipse Debugger Console by using Ctrl-C, Ctrl-V. + +### Usage with IAR Embedded Workbench for Arm +The IAR project is not yet updated for TraceRecorder (work in progress). However, you can easily extend the existing IAR project with TraceRecorder. +Simply add the source files and include paths for TraceRecorder listed in build/gcc/Makefile. Build and run. +To save the trace, please refer to the guides at [https://percepio.com/iar](https://percepio.com/iar). + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcConfig.h new file mode 100644 index 00000000000..226d9bbafed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcConfig.h @@ -0,0 +1,338 @@ +/* + * Trace Recorder for Tracealyzer v4.10.2 + * Copyright 2023 Percepio AB + * www.percepio.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Main configuration parameters for the trace recorder library. + * More settings can be found in trcStreamingConfig.h and trcSnapshotConfig.h. + */ + +#ifndef TRC_CONFIG_H +#define TRC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * Include of processor header file + * + * Here you may need to include the header file for your processor. This is + * required at least for the ARM Cortex-M port, that uses the ARM CMSIS API. + * Try that in case of build problems. Otherwise, remove the #error line below. + *****************************************************************************/ +//#error "Trace Recorder: Please include your processor's header file here and remove this line." + +/* TODO TraceRecorder (Step 6): For Arm Cortex-M devices, include cmsis.h here. */ +#include + +/** + * @def TRC_CFG_HARDWARE_PORT + * @brief Specify what hardware port to use (i.e., the "timestamping driver"). + * + * All ARM Cortex-M MCUs are supported by "TRC_HARDWARE_PORT_ARM_Cortex_M". + * This port uses the DWT cycle counter for Cortex-M3/M4/M7 devices, which is + * available on most such devices. In case your device don't have DWT support, + * you will get an error message opening the trace. In that case, you may + * force the recorder to use SysTick timestamping instead, using this define: + * + * #define TRC_CFG_ARM_CM_USE_SYSTICK + * + * For ARM Cortex-M0/M0+ devices, SysTick mode is used automatically. + * + * See trcHardwarePort.h for available ports and information on how to + * define your own port, if not already present. + */ + +/* TODO TraceRecorder (Step 7): Select the Arm Cortex-M hardware port. */ +#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_ARM_Cortex_M + +/* Needed to use TraceRecorder on QEMU - specifies using SysTick counter + * for timestamping, instead of DWT cycle counter (default but unsupported on qemu) */ +#define TRC_CFG_ARM_CM_USE_SYSTICK + +/** + * @def TRC_CFG_SCHEDULING_ONLY + * @brief Macro which should be defined as an integer value. + * + * If this setting is enabled (= 1), only scheduling events are recorded. + * If disabled (= 0), all events are recorded (unless filtered in other ways). + * + * Default value is 0 (= include additional events). + */ +#define TRC_CFG_SCHEDULING_ONLY 0 + +/** + * @def TRC_CFG_INCLUDE_MEMMANG_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * This controls if malloc and free calls should be traced. Set this to zero (0) + * to exclude malloc/free calls, or one (1) to include such events in the trace. + * + * Default value is 1. + */ +#define TRC_CFG_INCLUDE_MEMMANG_EVENTS 1 + +/** + * @def TRC_CFG_INCLUDE_USER_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), all code related to User Events is excluded in order + * to reduce code size. Any attempts of storing User Events are then silently + * ignored. + * + * User Events are application-generated events, like "printf" but for the + * trace log, generated using vTracePrint and vTracePrintF. + * The formatting is done on host-side, by Tracealyzer. User Events are + * therefore much faster than a console printf and can often be used + * in timing critical code without problems. + * + * Note: In streaming mode, User Events are used to provide error messages + * and warnings from the recorder (in case of incorrect configuration) for + * display in Tracealyzer. Disabling user events will also disable these + * warnings. You can however still catch them by calling xTraceErrorGetLast + * or by putting breakpoints in xTraceError and xTraceWarning. + * + * Default value is 1. + */ +#define TRC_CFG_INCLUDE_USER_EVENTS 1 + +/** + * @def TRC_CFG_INCLUDE_ISR_TRACING + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the code for recording Interrupt Service Routines is + * excluded, in order to reduce code size. This means that any calls to + * vTraceStoreISRBegin/vTraceStoreISREnd will be ignored. + * This does not completely disable ISR tracing, in cases where an ISR is + * calling a traced kernel service. These events will still be recorded and + * show up in anonymous ISR instances in Tracealyzer, with names such as + * "ISR sending to ". + * To disable such tracing, please refer to vTraceSetFilterGroup and + * vTraceSetFilterMask. + * + * Default value is 1. + * + * Note: tracing ISRs requires that you insert calls to vTraceStoreISRBegin + * and vTraceStoreISREnd in your interrupt handlers. + */ +#define TRC_CFG_INCLUDE_ISR_TRACING 1 + +/** + * @def TRC_CFG_INCLUDE_READY_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If one (1), events are recorded when tasks enter scheduling state "ready". + * This allows Tracealyzer to show the initial pending time before tasks enter + * the execution state and present accurate response times in the statistics + * report. + * If zero (0), "ready events" are not created, which allows for recording + * longer traces in the same amount of RAM. This will however cause + * Tracealyzer to report a single instance for each actor and prevent accurate + * response times in the statistics report. + * + * Default value is 1. + */ +#define TRC_CFG_INCLUDE_READY_EVENTS 1 + +/** + * @def TRC_CFG_INCLUDE_OSTICK_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is one (1), events will be generated whenever the OS clock is + * increased. If zero (0), OS tick events are not generated, which allows for + * recording longer traces in the same amount of RAM. + * + * Default value is 1. + */ + +/* TODO TraceRecorder (Tweak 2): Disabling OS tick event tracing (to reduce event rate). */ +#define TRC_CFG_INCLUDE_OSTICK_EVENTS 0 + +/** + * @def TRC_CFG_ENABLE_STACK_MONITOR + * @brief If enabled (1), the recorder periodically reports the unused stack space of + * all active tasks. + * The stack monitoring runs in the Tracealyzer Control task, TzCtrl. This task + * is always created by the recorder when in streaming mode. + * In snapshot mode, the TzCtrl task is only used for stack monitoring and is + * not created unless this is enabled. + */ +#define TRC_CFG_ENABLE_STACK_MONITOR 0 + +/** + * @def TRC_CFG_STACK_MONITOR_MAX_TASKS + * @brief Macro which should be defined as a non-zero integer value. + * + * This controls how many tasks that can be monitored by the stack monitor. + * If this is too small, some tasks will be excluded and a warning is shown. + * + * Default value is 10. + */ +#define TRC_CFG_STACK_MONITOR_MAX_TASKS 10 + +/** + * @def TRC_CFG_STACK_MONITOR_MAX_REPORTS + * @brief Macro which should be defined as a non-zero integer value. + * + * This defines how many tasks that will be subject to stack usage analysis for + * each execution of the Tracealyzer Control task (TzCtrl). Note that the stack + * monitoring cycles between the tasks, so this does not affect WHICH tasks that + * are monitored, but HOW OFTEN each task stack is analyzed. + * + * This setting can be combined with TRC_CFG_CTRL_TASK_DELAY to tune the + * frequency of the stack monitoring. This is motivated since the stack analysis + * can take some time to execute. + * However, note that the stack analysis runs in a separate task (TzCtrl) that + * can be executed on low priority. This way, you can avoid that the stack + * analysis disturbs any time-sensitive tasks. + * + * Default value is 1. + */ +#define TRC_CFG_STACK_MONITOR_MAX_REPORTS 1 + +/** + * @def TRC_CFG_CTRL_TASK_PRIORITY + * @brief The scheduling priority of the Tracealyzer Control (TzCtrl) task. + * + * In streaming mode, TzCtrl is used to receive start/stop commands from + * Tracealyzer and in some cases also to transmit the trace data (for stream + * ports that uses the internal buffer, like TCP/IP). For such stream ports, + * make sure the TzCtrl priority is high enough to ensure reliable periodic + * execution and transfer of the data, but low enough to avoid disturbing any + * time-sensitive functions. + * + * In Snapshot mode, TzCtrl is only used for the stack usage monitoring and is + * not created if stack monitoring is disabled. TRC_CFG_CTRL_TASK_PRIORITY should + * be low, to avoid disturbing any time-sensitive tasks. + */ +#define TRC_CFG_CTRL_TASK_PRIORITY 0 + +/** + * @def TRC_CFG_CTRL_TASK_DELAY + * @brief The delay between loops of the TzCtrl task (see TRC_CFG_CTRL_TASK_PRIORITY), + * which affects the frequency of the stack monitoring. + * + * In streaming mode, this also affects the trace data transfer if you are using + * a stream port leveraging the internal buffer (like TCP/IP). A shorter delay + * increases the CPU load of TzCtrl somewhat, but may improve the performance of + * of the trace streaming, especially if the trace buffer is small. + * + * The unit depends on the delay function used for the specific kernel port (trcKernelPort.c). + * For example, FreeRTOS uses ticks while Zephyr uses ms. + */ + +#define TRC_CFG_CTRL_TASK_DELAY 0xFFFFFFFF + +/** + * @def TRC_CFG_CTRL_TASK_STACK_SIZE + * @brief The stack size of the Tracealyzer Control (TzCtrl) task. + * See TRC_CFG_CTRL_TASK_PRIORITY for further information about TzCtrl. + */ +#define TRC_CFG_CTRL_TASK_STACK_SIZE 256 + +/** + * @def TRC_CFG_RECORDER_BUFFER_ALLOCATION + * @brief Specifies how the recorder buffer is allocated (also in case of streaming, in + * port using the recorder's internal temporary buffer) + * + * Values: + * TRC_RECORDER_BUFFER_ALLOCATION_STATIC - Static allocation (internal) + * TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC - Malloc in vTraceEnable + * TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM - Use vTraceSetRecorderDataBuffer + * + * Static and dynamic mode does the allocation for you, either in compile time + * (static) or in runtime (malloc). + * The custom mode allows you to control how and where the allocation is made, + * for details see TRC_ALLOC_CUSTOM_BUFFER and vTraceSetRecorderDataBuffer(). + */ +#define TRC_CFG_RECORDER_BUFFER_ALLOCATION TRC_RECORDER_BUFFER_ALLOCATION_STATIC + +/** + * @def TRC_CFG_MAX_ISR_NESTING + * @brief Defines how many levels of interrupt nesting the recorder can handle, in + * case multiple ISRs are traced and ISR nesting is possible. If this + * is exceeded, the particular ISR will not be traced and the recorder then + * logs an error message. This setting is used to allocate an internal stack + * for keeping track of the previous execution context (4 byte per entry). + * + * This value must be a non-zero positive constant, at least 1. + * + * Default value: 8 + */ +#define TRC_CFG_MAX_ISR_NESTING 8 + +/** + * @def TRC_CFG_ISR_TAILCHAINING_THRESHOLD + * @brief Macro which should be defined as an integer value. + * + * If tracing multiple ISRs, this setting allows for accurate display of the + * context-switching also in cases when the ISRs execute in direct sequence. + * + * vTraceStoreISREnd normally assumes that the ISR returns to the previous + * context, i.e., a task or a preempted ISR. But if another traced ISR + * executes in direct sequence, Tracealyzer may incorrectly display a minimal + * fragment of the previous context in between the ISRs. + * + * By using TRC_CFG_ISR_TAILCHAINING_THRESHOLD you can avoid this. This is + * however a threshold value that must be measured for your specific setup. + * See http://percepio.com/2014/03/21/isr_tailchaining_threshold/ + * + * The default setting is 0, meaning "disabled" and that you may get an + * extra fragments of the previous context in between tail-chained ISRs. + * + * Note: This setting has separate definitions in trcSnapshotConfig.h and + * trcStreamingConfig.h, since it is affected by the recorder mode. + */ +#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0 + +/** + * @def TRC_CFG_RECORDER_DATA_INIT + * @brief Macro which states whether the recorder data should have an initial value. + * + * In very specific cases where traced objects are created before main(), + * the recorder will need to be started even before that. In these cases, + * the recorder data would be initialized by vTraceEnable(TRC_INIT) but could + * then later be overwritten by the initialization value. + * If this is an issue for you, set TRC_CFG_RECORDER_DATA_INIT to 0. + * The following code can then be used before any traced objects are created: + * + * extern uint32_t RecorderInitialized; + * RecorderInitialized = 0; + * xTraceInitialize(); + * + * After the clocks are properly initialized, use vTraceEnable(...) to start + * the tracing. + * + * Default value is 1. + */ +#define TRC_CFG_RECORDER_DATA_INIT 1 + +/** + * @def TRC_CFG_RECORDER_DATA_ATTRIBUTE + * @brief When setting TRC_CFG_RECORDER_DATA_INIT to 0, you might also need to make + * sure certain recorder data is placed in a specific RAM section to avoid being + * zeroed out after initialization. Define TRC_CFG_RECORDER_DATA_ATTRIBUTE as + * that attribute. + * + * Example: + * #define TRC_CFG_RECORDER_DATA_ATTRIBUTE __attribute__((section(".bss.trace_recorder_data"))) + * + * Default value is empty. + */ +#define TRC_CFG_RECORDER_DATA_ATTRIBUTE + +/** + * @def TRC_CFG_USE_TRACE_ASSERT + * @brief Enable or disable debug asserts. Information regarding any assert that is + * triggered will be in trcAssert.c. + */ +#define TRC_CFG_USE_TRACE_ASSERT 1 + +#ifdef __cplusplus +} +#endif + +#endif /* _TRC_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortConfig.h new file mode 100644 index 00000000000..b4e169fcbd6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortConfig.h @@ -0,0 +1,132 @@ +/* + * Trace Recorder for Tracealyzer v4.10.2 + * Copyright 2023 Percepio AB + * www.percepio.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Configuration parameters for the kernel port. + * More settings can be found in trcKernelPortStreamingConfig.h and + * trcKernelPortSnapshotConfig.h. + */ + +#ifndef TRC_KERNEL_PORT_CONFIG_H +#define TRC_KERNEL_PORT_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @def TRC_CFG_RECORDER_MODE + * @brief Specify what recording mode to use. Snapshot means that the data is saved in + * an internal RAM buffer, for later upload. Streaming means that the data is + * transferred continuously to the host PC. + * + * For more information, see http://percepio.com/2016/10/05/rtos-tracing/ + * and the Tracealyzer User Manual. + * + * Values: + * TRC_RECORDER_MODE_SNAPSHOT (no longer used) + * TRC_RECORDER_MODE_STREAMING (supports snapshots and streaming) + */ +#define TRC_CFG_RECORDER_MODE TRC_RECORDER_MODE_STREAMING + +/** + * @def TRC_CFG_FREERTOS_VERSION + * @brief Specify what version of FreeRTOS that is used (don't change unless using the + * trace recorder library with an older version of FreeRTOS). + * + * TRC_FREERTOS_VERSION_7_3_X If using FreeRTOS v7.3.X + * TRC_FREERTOS_VERSION_7_4_X If using FreeRTOS v7.4.X + * TRC_FREERTOS_VERSION_7_5_X If using FreeRTOS v7.5.X + * TRC_FREERTOS_VERSION_7_6_X If using FreeRTOS v7.6.X + * TRC_FREERTOS_VERSION_8_X_X If using FreeRTOS v8.X.X + * TRC_FREERTOS_VERSION_9_0_0 If using FreeRTOS v9.0.0 + * TRC_FREERTOS_VERSION_9_0_1 If using FreeRTOS v9.0.1 + * TRC_FREERTOS_VERSION_9_0_2 If using FreeRTOS v9.0.2 + * TRC_FREERTOS_VERSION_10_0_0 If using FreeRTOS v10.0.0 + * TRC_FREERTOS_VERSION_10_0_1 If using FreeRTOS v10.0.1 + * TRC_FREERTOS_VERSION_10_1_0 If using FreeRTOS v10.1.0 + * TRC_FREERTOS_VERSION_10_1_1 If using FreeRTOS v10.1.1 + * TRC_FREERTOS_VERSION_10_2_0 If using FreeRTOS v10.2.0 + * TRC_FREERTOS_VERSION_10_2_1 If using FreeRTOS v10.2.1 + * TRC_FREERTOS_VERSION_10_3_0 If using FreeRTOS v10.3.0 + * TRC_FREERTOS_VERSION_10_3_1 If using FreeRTOS v10.3.1 + * TRC_FREERTOS_VERSION_10_4_0 If using FreeRTOS v10.4.0 + * TRC_FREERTOS_VERSION_10_4_1 If using FreeRTOS v10.4.1 + * TRC_FREERTOS_VERSION_10_4_2 If using FreeRTOS v10.4.2 + * TRC_FREERTOS_VERSION_10_4_3 If using FreeRTOS v10.4.3 + * TRC_FREERTOS_VERSION_10_5_0 If using FreeRTOS v10.5.0 + * TRC_FREERTOS_VERSION_10_5_1 If using FreeRTOS v10.5.1 + * TRC_FREERTOS_VERSION_10_6_0 If using FreeRTOS v10.6.0 + * TRC_FREERTOS_VERSION_10_6_1 If using FreeRTOS v10.6.1 + * TRC_FREERTOS_VERSION_10_6_2 If using FreeRTOS v10.6.2 + * TRC_FREERTOS_VERSION_11_0_0 If using FreeRTOS v11.0.0 + * TRC_FREERTOS_VERSION_11_0_1 If using FreeRTOS v11.0.1 + * TRC_FREERTOS_VERSION_11_1_0 If using FreeRTOS v11.1.0 or later + */ + +/* TODO TraceRecorder (Step 8): Specify FreeRTOS version here. */ +#define TRC_CFG_FREERTOS_VERSION TRC_FREERTOS_VERSION_11_1_0 + +/** + * @def TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any "event group" events. + * + * Default value is 0 (excluded) since dependent on event_groups.c + */ +#define TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS 0 + +/** + * @def TRC_CFG_INCLUDE_TIMER_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any Timer events. + * + * Default value is 0 since dependent on timers.c + */ + +/* TODO TraceRecorder (Tweak 1): Enabling Timer event tracing. */ +/* Note: Only the "optional" FreeRTOS services mentioned in this file + * needs to be enabled in the tracing. Others are included by default.*/ +#define TRC_CFG_INCLUDE_TIMER_EVENTS 1 + +/** + * @def TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any "pending function call" + * events, such as xTimerPendFunctionCall(). + * + * Default value is 0 since dependent on timers.c + */ +#define TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS 0 + +/** + * @def TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any stream buffer or message + * buffer events. + * + * Default value is 0 since dependent on stream_buffer.c (new in FreeRTOS v10) + */ +#define TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS 0 + +/** + * @def TRC_CFG_ACKNOWLEDGE_QUEUE_SET_SEND + * @brief When using FreeRTOS v10.3.0 or v10.3.1, please make sure that the trace + * point in prvNotifyQueueSetContainer() in queue.c is renamed from + * traceQUEUE_SEND to traceQUEUE_SET_SEND in order to tell them apart from + * other traceQUEUE_SEND trace points. Then set this to TRC_ACKNOWLEDGED. + */ +#define TRC_CFG_ACKNOWLEDGE_QUEUE_SET_SEND 0 /* TRC_ACKNOWLEDGED */ + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_KERNEL_PORT_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortSnapshotConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortSnapshotConfig.h new file mode 100644 index 00000000000..99ac533829a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortSnapshotConfig.h @@ -0,0 +1,69 @@ +/* + * Trace Recorder for Tracealyzer v4.10.2 + * Copyright 2023 Percepio AB + * www.percepio.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Kernel port configuration parameters for snapshot mode. + */ + +#ifndef TRC_KERNEL_PORT_SNAPSHOT_CONFIG_H +#define TRC_KERNEL_PORT_SNAPSHOT_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @def TRC_CFG_NTASK, TRC_CFG_NISR, TRC_CFG_NQUEUE, TRC_CFG_NSEMAPHORE... + * @brief A group of macros which should be defined as integer values, zero or larger. + * + * These define the capacity of the Object Property Table, i.e., the maximum + * number of objects active at any given point, within each object class (e.g., + * task, queue, semaphore, ...). + * + * If tasks or other objects are deleted in your system, this + * setting does not limit the total amount of objects created, only the number + * of objects that have been successfully created but not yet deleted. + * + * Using too small values will cause vTraceError to be called, which stores an + * error message in the trace that is shown when opening the trace file. The + * error message can also be retrieved using xTraceGetLastError. + * + * It can be wise to start with large values for these constants, + * unless you are very confident on these numbers. Then do a recording and + * check the actual usage by selecting View menu -> Trace Details -> + * Resource Usage -> Object Table. + */ +#define TRC_CFG_NTASK 15 +#define TRC_CFG_NISR 5 +#define TRC_CFG_NQUEUE 10 +#define TRC_CFG_NSEMAPHORE 10 +#define TRC_CFG_NMUTEX 10 +#define TRC_CFG_NTIMER 5 +#define TRC_CFG_NEVENTGROUP 5 +#define TRC_CFG_NSTREAMBUFFER 5 +#define TRC_CFG_NMESSAGEBUFFER 5 + +/** + * @def TRC_CFG_NAME_LEN_TASK, TRC_CFG_NAME_LEN_QUEUE, ... + * @brief Macros that specify the maximum lengths (number of characters) for names of + * kernel objects, such as tasks and queues. If longer names are used, they will + * be truncated when stored in the recorder. + */ +#define TRC_CFG_NAME_LEN_TASK 15 +#define TRC_CFG_NAME_LEN_ISR 15 +#define TRC_CFG_NAME_LEN_QUEUE 15 +#define TRC_CFG_NAME_LEN_SEMAPHORE 15 +#define TRC_CFG_NAME_LEN_MUTEX 15 +#define TRC_CFG_NAME_LEN_TIMER 15 +#define TRC_CFG_NAME_LEN_EVENTGROUP 15 +#define TRC_CFG_NAME_LEN_STREAMBUFFER 15 +#define TRC_CFG_NAME_LEN_MESSAGEBUFFER 15 + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_KERNEL_PORT_SNAPSHOT_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortStreamingConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortStreamingConfig.h new file mode 100644 index 00000000000..1c112644589 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcKernelPortStreamingConfig.h @@ -0,0 +1,24 @@ +/* + * Trace Recorder for Tracealyzer v4.10.2 + * Copyright 2023 Percepio AB + * www.percepio.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Kernel port configuration parameters for streaming mode. + */ + +#ifndef TRC_KERNEL_PORT_STREAMING_CONFIG_H +#define TRC_KERNEL_PORT_STREAMING_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Nothing yet */ + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_KERNEL_PORT_STREAMING_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcSnapshotConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcSnapshotConfig.h new file mode 100644 index 00000000000..0bcffc32895 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcSnapshotConfig.h @@ -0,0 +1,245 @@ +/* + * Trace Recorder for Tracealyzer v4.10.2 + * Copyright 2023 Percepio AB + * www.percepio.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Configuration parameters for trace recorder library in snapshot mode. + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + */ + +#ifndef TRC_SNAPSHOT_CONFIG_H +#define TRC_SNAPSHOT_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @def TRC_CFG_SNAPSHOT_MODE + * @brief Macro which should be defined as one of: + * - TRC_SNAPSHOT_MODE_RING_BUFFER + * - TRC_SNAPSHOT_MODE_STOP_WHEN_FULL + * Default is TRC_SNAPSHOT_MODE_RING_BUFFER. + * + * With TRC_CFG_SNAPSHOT_MODE set to TRC_SNAPSHOT_MODE_RING_BUFFER, the + * events are stored in a ring buffer, i.e., where the oldest events are + * overwritten when the buffer becomes full. This allows you to get the last + * events leading up to an interesting state, e.g., an error, without having + * to store the whole run since startup. + * + * When TRC_CFG_SNAPSHOT_MODE is TRC_SNAPSHOT_MODE_STOP_WHEN_FULL, the + * recording is stopped when the buffer becomes full. This is useful for + * recording events following a specific state, e.g., the startup sequence. + */ +#define TRC_CFG_SNAPSHOT_MODE TRC_SNAPSHOT_MODE_RING_BUFFER + +/** + * @def TRC_CFG_EVENT_BUFFER_SIZE + * @brief Macro which should be defined as an integer value. + * + * This defines the capacity of the event buffer, i.e., the number of records + * it may store. Most events use one record (4 byte), although some events + * require multiple 4-byte records. You should adjust this to the amount of RAM + * available in the target system. + * + * Default value is 1000, which means that 4000 bytes is allocated for the + * event buffer. + */ +#define TRC_CFG_EVENT_BUFFER_SIZE 1000 + +/** + * @def TRC_CFG_INCLUDE_FLOAT_SUPPORT + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the support for logging floating point values in + * vTracePrintF is stripped out, in case floating point values are not used or + * supported by the platform used. + * + * Floating point values are only used in vTracePrintF and its subroutines, to + * allow for storing float (%f) or double (%lf) arguments. + * + * vTracePrintF can be used with integer and string arguments in either case. + * + * Default value is 0. + */ +#define TRC_CFG_INCLUDE_FLOAT_SUPPORT 0 + +/** + * @def TRC_CFG_SYMBOL_TABLE_SIZE + * @brief Macro which should be defined as an integer value. + * + * This defines the capacity of the symbol table, in bytes. This symbol table + * stores User Events labels and names of deleted tasks, queues, or other kernel + * objects. If you don't use User Events or delete any kernel + * objects you set this to a very low value. The minimum recommended value is 4. + * A size of zero (0) is not allowed since a zero-sized array may result in a + * 32-bit pointer, i.e., using 4 bytes rather than 0. + * + * Default value is 800. + */ +#define TRC_CFG_SYMBOL_TABLE_SIZE 800 + +#if (TRC_CFG_SYMBOL_TABLE_SIZE == 0) +#error "TRC_CFG_SYMBOL_TABLE_SIZE may not be zero!" +#endif + +/****************************************************************************** + *** ADVANCED SETTINGS ******************************************************** + ****************************************************************************** + * The remaining settings are not necessary to modify but allows for optimizing + * the recorder setup for your specific needs, e.g., to exclude events that you + * are not interested in, in order to get longer traces. + *****************************************************************************/ + +/** + * @def TRC_CFG_HEAP_SIZE_BELOW_16M + * @brief An integer constant that can be used to reduce the buffer usage of memory + * allocation events (malloc/free). This value should be 1 if the heap size is + * below 16 MB (2^24 byte), and you can live with reported addresses showing the + * lower 24 bits only. If 0, you get the full 32-bit addresses. + * + * Default value is 0. + */ +#define TRC_CFG_HEAP_SIZE_BELOW_16M 0 + +/** + * @def TRC_CFG_USE_IMPLICIT_IFE_RULES + * @brief Macro which should be defined as either zero (0) or one (1). + * Default is 1. + * + * Tracealyzer groups the events into "instances" based on Instance Finish + * Events (IFEs), produced either by default rules or calls to the recorder + * functions xTraceTaskInstanceFinishedNow and xTraceTaskInstanceFinishedNext. + * + * If TRC_CFG_USE_IMPLICIT_IFE_RULES is one (1), the default IFE rules is + * used, resulting in a "typical" grouping of events into instances. + * If these rules don't give appropriate instances in your case, you can + * override the default rules using xTraceTaskInstanceFinishedNow/Next for one + * or several tasks. The default IFE rules are then disabled for those tasks. + * + * If TRC_CFG_USE_IMPLICIT_IFE_RULES is zero (0), the implicit IFE rules are + * disabled globally. You must then call xTraceTaskInstanceFinishedNow or + * xTraceTaskInstanceFinishedNext to manually group the events into instances, + * otherwise the tasks will appear a single long instance. + * + * The default IFE rules count the following events as "instance finished": + * - Task delay, delay until + * - Task suspend + * - Blocking on "input" operations, i.e., when the task is waiting for the + * next a message/signal/event. But only if this event is blocking. + */ +#define TRC_CFG_USE_IMPLICIT_IFE_RULES 1 + +/** + * @def TRC_CFG_USE_16BIT_OBJECT_HANDLES + * @brief Macro which should be defined as either zero (0) or one (1). + * + * If set to 0 (zero), the recorder uses 8-bit handles to identify kernel + * objects such as tasks and queues. This limits the supported number of + * concurrently active objects to 255 of each type (tasks, queues, mutexes, + * etc.) Note: 255, not 256, since handle 0 is reserved. + * + * If set to 1 (one), the recorder uses 16-bit handles to identify kernel + * objects such as tasks and queues. This limits the supported number of + * concurrent objects to 65535 of each type (object class). However, since the + * object property table is limited to 64 KB, the practical limit is about + * 3000 objects in total. + * + * Default is 0 (8-bit handles) + * + * NOTE: An object with handle above 255 will use an extra 4-byte record in + * the event buffer whenever the object is referenced. Moreover, some internal + * tables in the recorder gets slightly larger when using 16-bit handles. + */ +#define TRC_CFG_USE_16BIT_OBJECT_HANDLES 0 + +/** + * @def TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER + * @brief Macro which should be defined as an integer value. + * + * Set TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER to 1 to enable the + * separate user event buffer (UB). + * In this mode, user events are stored separately from other events, + * e.g., RTOS events. Thereby you can get a much longer history of + * user events as they don't need to share the buffer space with more + * frequent events. + * + * The UB is typically used with the snapshot ring-buffer mode, so the + * recording can continue when the main buffer gets full. And since the + * main buffer then overwrites the earliest events, Tracealyzer displays + * "Unknown Actor" instead of task scheduling for periods with UB data only. + * + * In UB mode, user events are structured as UB channels, which contains + * a channel name and a default format string. Register a UB channel using + * xTraceRegisterUBChannel. + * + * Events and data arguments are written using vTraceUBEvent and + * vTraceUBData. They are designed to provide efficient logging of + * repeating events, using the same format string within each channel. + * + * Examples: + * TraceStringHandle_t chn1; + * TraceStringHandle_t fmt1; + * xTraceStringRegister("Channel 1", &chn1); + * xTraceStringRegister("Event!", &fmt1); + * traceUBChannel UBCh1 = xTraceRegisterUBChannel(chn1, fmt1); + * + * TraceStringHandle_t chn2; + * TraceStringHandle_t fmt2; + * xTraceStringRegister("Channel 2", &chn2); + * xTraceStringRegister("X: %d, Y: %d", &fmt2); + * traceUBChannel UBCh2 = xTraceRegisterUBChannel(chn2, fmt2); + * + * // Result in "[Channel 1] Event!" + * vTraceUBEvent(UBCh1); + * + * // Result in "[Channel 2] X: 23, Y: 19" + * vTraceUBData(UBCh2, 23, 19); + * + * You can also use the other user event functions, like xTracePrintF. + * as they are then rerouted to the UB instead of the main event buffer. + * vTracePrintF then looks up the correct UB channel based on the + * provided channel name and format string, or creates a new UB channel + * if no match is found. The format string should therefore not contain + * "random" messages but mainly format specifiers. Random strings should + * be stored using %s and with the string as an argument. + * + * // Creates a new UB channel ("Channel 2", "%Z: %d") + * xTracePrintF(chn2, "%Z: %d", value1); + * + * // Finds the existing UB channel + * xTracePrintF(chn2, "%Z: %d", value2); + */ +#define TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER 0 + +/** + * @def TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE + * @brief Macro which should be defined as an integer value. + * + * This defines the capacity of the user event buffer (UB), in number of slots. + * A single user event can use multiple slots, depending on the arguments. + * + * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. + */ +#define TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE 200 + +/** + * @def TRC_CFG_UB_CHANNELS + * @brief Macro which should be defined as an integer value. + * + * This defines the number of User Event Buffer Channels (UB channels). + * These are used to structure the events when using the separate user + * event buffer, and contains both a User Event Channel (the name) and + * a default format string for the channel. + * + * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. + */ +#define TRC_CFG_UB_CHANNELS 32 + +#ifdef __cplusplus +} +#endif + +#endif /*TRC_SNAPSHOT_CONFIG_H*/ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcStreamPortConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcStreamPortConfig.h new file mode 100644 index 00000000000..b14e1c67ff3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcStreamPortConfig.h @@ -0,0 +1,63 @@ +/* +* Trace Recorder for Tracealyzer v4.10.2 +* Copyright 2023 Percepio AB +* www.percepio.com +* +* SPDX-License-Identifier: Apache-2.0 +* + * The configuration for trace streaming ("stream ports"). +*/ + +#ifndef TRC_STREAM_PORT_CONFIG_H +#define TRC_STREAM_PORT_CONFIG_H + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type flags */ +#define TRC_STREAM_PORT_RINGBUFFER_MODE_STOP_WHEN_FULL (0U) +#define TRC_STREAM_PORT_RINGBUFFER_MODE_OVERWRITE_WHEN_FULL (1U) + +/** + * @def TRC_CFG_STREAM_PORT_BUFFER_SIZE + * + * @brief Defines the size of the ring buffer use for storing trace events. + */ + +/* TODO TraceRecorder (Tweak 3): Adjust the RingBuffer size here + * to increase trace length or reduce memory usage. */ +#define TRC_CFG_STREAM_PORT_BUFFER_SIZE 10240 + +/** + * @def TRC_CFG_STREAM_PORT_BUFFER_MODE + * + * @brief Configures the behavior of the ring buffer when full. + * + * With TRC_CFG_STREAM_PORT_MODE set to TRC_STREAM_PORT_RINGBUFFER_MODE_OVERWRITE_WHEN_FULL, the + * events are stored in a ring buffer, i.e., where the oldest events are + * overwritten when the buffer becomes full. This allows you to get the last + * events leading up to an interesting state, e.g., an error, without having + * to store the whole run since startup. + * + * When TRC_CFG_STREAM_PORT_MODE is TRC_STREAM_PORT_RINGBUFFER_MODE_STOP_WHEN_FULL, the + * recording is stopped when the buffer becomes full. This is useful for + * recording events following a specific state, e.g., the startup sequence. + */ +#define TRC_CFG_STREAM_PORT_RINGBUFFER_MODE TRC_STREAM_PORT_RINGBUFFER_MODE_OVERWRITE_WHEN_FULL + +#ifdef __cplusplus +} +#endif + +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)*/ + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ + +#endif /* TRC_STREAM_PORT_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcStreamingConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcStreamingConfig.h new file mode 100644 index 00000000000..ac2197aca74 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig/trcStreamingConfig.h @@ -0,0 +1,51 @@ +/* + * Trace Recorder for Tracealyzer v4.10.2 + * Copyright 2023 Percepio AB + * www.percepio.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Configuration parameters for the trace recorder library in streaming mode. + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + */ + +#ifndef TRC_STREAMING_CONFIG_H +#define TRC_STREAMING_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @def TRC_CFG_ENTRY_SLOTS + * @brief The maximum number of objects and symbols that can be stored. This includes: + * - Task names + * - Named ISRs (vTraceSetISRProperties) + * - Named kernel objects (vTraceStoreKernelObjectName) + * - User event channels (xTraceStringRegister) + * + * If this value is too small, not all symbol names will be stored and the + * trace display will be affected. In that case, there will be warnings + * (as User Events) from TzCtrl task, that monitors this. + */ +#define TRC_CFG_ENTRY_SLOTS 50 + +/** + * @def TRC_CFG_ENTRY_SYMBOL_MAX_LENGTH + * @brief The maximum length of symbol names, including: + * - Task names + * - Named ISRs (vTraceSetISRProperties) + * - Named kernel objects (vTraceStoreKernelObjectName) + * - User event channel names (xTraceStringRegister) + * + * If longer symbol names are used, they will be truncated by the recorder, + * which will affect the trace display. In that case, there will be warnings + * (as User Events) from TzCtrl task, that monitors this. + */ +#define TRC_CFG_ENTRY_SYMBOL_MAX_LENGTH 28 + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project index da12b7d9b3e..d4c5e3496d8 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project @@ -25,11 +25,6 @@ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - CommonDemoSource - 2 - FREERTOS_ROOT/Demo/Common/Minimal - FreeRTOS_kernel 2 @@ -40,35 +35,55 @@ 2 virtual:/virtual + + TraceRecorderConfig + 2 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/TraceRecorderConfig + + + Source/Blinky_Demo + 2 + virtual:/virtual + Source/FreeRTOSConfig.h 1 FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h - Source/IntQueueTimer.c + Source/Full_Demo + 2 + virtual:/virtual + + + Source/main.c 1 - FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c - Source/IntQueueTimer.h + Source/Blinky_Demo/main_blinky.c 1 - FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h + PARENT-2-PROJECT_LOC/main_blinky.c - Source/main.c + Source/Full_Demo/CommonDemoSource + 2 + FREERTOS_ROOT/Demo/Common/Minimal + + + Source/Full_Demo/IntQueueTimer.c 1 - FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c + PARENT-2-PROJECT_LOC/IntQueueTimer.c - Source/main_blinky.c + Source/Full_Demo/IntQueueTimer.h 1 - FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c + PARENT-2-PROJECT_LOC/IntQueueTimer.h - Source/main_full.c + Source/Full_Demo/main_full.c 1 - FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c + PARENT-2-PROJECT_LOC/main_full.c diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile index 33e0cdde622..57df4e48f08 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile @@ -1,19 +1,28 @@ OUTPUT_DIR := ./output -IMAGE := RTOSDemo.out -SUB_MAKEFILE_DIR = ./library-makefiles +IMAGE := $(OUTPUT_DIR)/RTOSDemo.out # The directory that contains the /source and /demo sub directories. -FREERTOS_ROOT = ./../../../../ +FREERTOS_ROOT = ./../../../.. CC = arm-none-eabi-gcc LD = arm-none-eabi-gcc SIZE = arm-none-eabi-size MAKE = make - -CFLAGS += $(INCLUDE_DIRS) -nostartfiles -ffreestanding -mthumb -mcpu=cortex-m3 \ - -Wall -Wextra -g3 -O0 -ffunction-sections -fdata-sections \ - -MMD -MP -MF"$(@:%.o=%.d)" -MT $@ +CFLAGS += -ffreestanding -mthumb -mcpu=cortex-m3 +CFLAGS += -Wall -Wextra -Wshadow -Wno-unused-value +CFLAGS += -g3 -Os -ffunction-sections -fdata-sections +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT $@ +#CFLAGS += -std=c99 +#CFLAGS += -Wpedantic -fanalyzer +#CFLAGS += -flto +CFLAGS += $(INCLUDE_DIRS) + +LDFLAGS = -T ./mps2_m3.ld +LDFLAGS += -Xlinker -Map=$(OUTPUT_DIR)/RTOSDemo.map +LDFLAGS += -Xlinker --gc-sections +LDFLAGS += -nostartfiles +LDFLAGS += -specs=nano.specs -specs=nosys.specs # -specs=rdimon.specs # # Kernel build. @@ -33,7 +42,7 @@ SOURCE_FILES += $(KERNEL_DIR)/portable/MemMang/heap_4.c SOURCE_FILES += $(KERNEL_DIR)/portable/GCC/ARM_CM3/port.c # -# Common demo files for the "full" build, as opposed to the "blinky" build - +# Common demo files for the "full" build, as opposed to the "blinky" build - # these files are build by all the FreeRTOS kernel demos. # DEMO_ROOT = $(FREERTOS_ROOT)/Demo @@ -79,9 +88,49 @@ SOURCE_FILES += (DEMO_PROJECT)/main.c SOURCE_FILES += (DEMO_PROJECT)/main_blinky.c SOURCE_FILES += (DEMO_PROJECT)/main_full.c SOURCE_FILES += ./startup_gcc.c +SOURCE_FILES += ./RegTest.c # Lightweight print formatting to use in place of the heavier GCC equivalent. SOURCE_FILES += ./printf-stdarg.c +# Percepio TraceRecorder (FreeRTOS-Plus-Trace) +TRACERECORDER_DIR = $(DEMO_ROOT)/../../FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace +TRACERECORDER_CFG_DIR = $(DEMO_PROJECT)/TraceRecorderConfig +VPATH += $(TRACERECORDER_DIR) +VPATH += $(TRACERECORDER_DIR)/kernelports/FreeRTOS +VPATH += $(TRACERECORDER_DIR)/streamports/RingBuffer +INCLUDE_DIRS += -I$(TRACERECORDER_CFG_DIR) +INCLUDE_DIRS += -I$(TRACERECORDER_DIR)/include +INCLUDE_DIRS += -I$(TRACERECORDER_DIR)/kernelports/FreeRTOS/include +INCLUDE_DIRS += -I$(TRACERECORDER_DIR)/streamports/RingBuffer/include +SOURCE_FILES += (TRACERECORDER_DIR)/kernelports/FreeRTOS/trcKernelPort.c +SOURCE_FILES += (TRACERECORDER_DIR)/streamports/RingBuffer/trcStreamPort.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcAssert.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcCounter.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcDependency.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcDiagnostics.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcEntryTable.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcError.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcEvent.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcEventBuffer.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcExtension.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcHardwarePort.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcHeap.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcInternalEventBuffer.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcInterval.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcISR.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcMultiCoreEventBuffer.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcObject.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcPrint.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcRunnable.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcSnapshotRecorder.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcStackMonitor.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcStateMachine.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcStaticBuffer.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcStreamingRecorder.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcString.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcTask.c +SOURCE_FILES += (TRACERECORDER_DIR)/trcTimestamp.c + #Create a list of object files with the desired output directory path. OBJS = $(SOURCE_FILES:%.c=%.o) OBJS_NO_PATH = $(notdir $(OBJS)) @@ -92,27 +141,25 @@ DEP_FILES := $(SOURCE_FILES:%.c=$(OUTPUT_DIR)/%.d) DEP_FILES_NO_PATH = $(notdir $(DEP_FILES)) DEP_OUTPUT = $(DEP_FILES_NO_PATH:%.d=$(OUTPUT_DIR)/%.d) -all: $(OUTPUT_DIR)/$(IMAGE) +all: $(IMAGE) %.o : %.c $(OUTPUT_DIR)/%.o : %.c $(OUTPUT_DIR)/%.d Makefile $(CC) $(CFLAGS) -c $< -o $@ -$(OUTPUT_DIR)/$(IMAGE): ./mps2_m3.ld $(OBJS_OUTPUT) Makefile +$(IMAGE): ./mps2_m3.ld $(OBJS_OUTPUT) Makefile @echo "" @echo "" @echo "--- Final linking ---" @echo "" - $(LD) $(OBJS_OUTPUT) $(CFLAGS) -Xlinker --gc-sections -Xlinker -T ./mps2_m3.ld \ - -Xlinker -Map=$(OUTPUT_DIR)/RTOSDemo.map -specs=nano.specs \ - -specs=nosys.specs -specs=rdimon.specs -o $(OUTPUT_DIR)/$(IMAGE) - $(SIZE) $(OUTPUT_DIR)/$(IMAGE) + $(LD) $(CFLAGS) $(LDFLAGS) $(OBJS_OUTPUT) -o $(IMAGE) + $(SIZE) $(IMAGE) $(DEP_OUTPUT): include $(wildcard $(DEP_OUTPUT)) clean: - rm -f $(OUTPUT_DIR)/$(IMAGE) $(OUTPUT_DIR)/*.o $(OUTPUT_DIR)/*.d + rm -f $(IMAGE) $(OUTPUT_DIR)/RTOSDemo.map $(OUTPUT_DIR)/*.o $(OUTPUT_DIR)/*.d #use "make print-[VARIABLE_NAME] to print the value of a variable generated by #this makefile. diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/RegTest.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/RegTest.c new file mode 100644 index 00000000000..f2fb17f677b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/RegTest.c @@ -0,0 +1,187 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + +void vRegTest1Implementation( void ) __attribute__ ((naked)); +void vRegTest2Implementation( void ) __attribute__ ((naked)); + +void vRegTest1Implementation( void ) +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + + /* Fill the core registers with known values. */ + "mov r0, #100 \n" + "mov r1, #101 \n" + "mov r2, #102 \n" + "mov r3, #103 \n" + "mov r4, #104 \n" + "mov r5, #105 \n" + "mov r6, #106 \n" + "mov r7, #107 \n" + "mov r8, #108 \n" + "mov r9, #109 \n" + "mov r10, #110 \n" + "mov r11, #111 \n" + "mov r12, #112 \n" + + "reg1_loop: \n" + + "cmp r0, #100 \n" + "bne reg1_error_loop \n" + "cmp r1, #101 \n" + "bne reg1_error_loop \n" + "cmp r2, #102 \n" + "bne reg1_error_loop \n" + "cmp r3, #103 \n" + "bne reg1_error_loop \n" + "cmp r4, #104 \n" + "bne reg1_error_loop \n" + "cmp r5, #105 \n" + "bne reg1_error_loop \n" + "cmp r6, #106 \n" + "bne reg1_error_loop \n" + "cmp r7, #107 \n" + "bne reg1_error_loop \n" + "cmp r8, #108 \n" + "bne reg1_error_loop \n" + "cmp r9, #109 \n" + "bne reg1_error_loop \n" + "cmp r10, #110 \n" + "bne reg1_error_loop \n" + "cmp r11, #111 \n" + "bne reg1_error_loop \n" + "cmp r12, #112 \n" + "bne reg1_error_loop \n" + + /* Everything passed, increment the loop counter. */ + "push { r0-r1 } \n" + "ldr r0, =ulRegTest1LoopCounter \n" + "ldr r1, [r0] \n" + "adds r1, r1, #1 \n" + "str r1, [r0] \n" + "pop { r0-r1 } \n" + + /* Start again. */ + "b reg1_loop \n" + + "reg1_error_loop: \n" + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + "b reg1_error_loop \n" + "nop \n" + ); /* __asm volatile. */ +} +/*-----------------------------------------------------------*/ + +void vRegTest2Implementation( void ) +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + + /* Set all the core registers to known values. */ + "mov r0, #-1 \n" + "mov r1, #1 \n" + "mov r2, #2 \n" + "mov r3, #3 \n" + "mov r4, #4 \n" + "mov r5, #5 \n" + "mov r6, #6 \n" + "mov r7, #7 \n" + "mov r8, #8 \n" + "mov r9, #9 \n" + "mov r10, #10 \n" + "mov r11, #11 \n" + "mov r12, #12 \n" + + "reg2_loop : \n" + + "cmp r0, #-1 \n" + "bne reg2_error_loop \n" + "cmp r1, #1 \n" + "bne reg2_error_loop \n" + "cmp r2, #2 \n" + "bne reg2_error_loop \n" + "cmp r3, #3 \n" + "bne reg2_error_loop \n" + "cmp r4, #4 \n" + "bne reg2_error_loop \n" + "cmp r5, #5 \n" + "bne reg2_error_loop \n" + "cmp r6, #6 \n" + "bne reg2_error_loop \n" + "cmp r7, #7 \n" + "bne reg2_error_loop \n" + "cmp r8, #8 \n" + "bne reg2_error_loop \n" + "cmp r9, #9 \n" + "bne reg2_error_loop \n" + "cmp r10, #10 \n" + "bne reg2_error_loop \n" + "cmp r11, #11 \n" + "bne reg2_error_loop \n" + "cmp r12, #12 \n" + "bne reg2_error_loop \n" + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + "push { r0-r1 } \n" + "ldr r0, =ulRegTest2LoopCounter \n" + "ldr r1, [r0] \n" + "adds r1, r1, #1 \n" + "str r1, [r0] \n" + + /* Yield to increase test coverage. */ + "movs r0, #0x01 \n" + "ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */ + "lsl r0, r0, #28 \n" /* Shift to PendSV bit */ + "str r0, [r1] \n" + "dsb \n" + + "pop { r0-r1 } \n" + + /* Start again. */ + "b reg2_loop \n" + + "reg2_error_loop: \n" + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + "b reg2_error_loop \n" + + ); /* __asm volatile */ +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c index ee3ac05a744..2d1abbf064b 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -27,22 +27,6 @@ #include #include -/* UART peripheral register addresses and bits. */ -#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) -#define UART_DR( baseaddr ) ( *( uint32_t * ) ( baseaddr ) ) -#define UART_STATE( baseaddr ) ( *( uint32_t * ) ( baseaddr + 4 ) ) -#define UART_STATE_TXFULL ( 1 << 0 ) - -typedef struct UART_t -{ - volatile uint32_t DATA; - volatile uint32_t STATE; - volatile uint32_t CTRL; - volatile uint32_t INTSTATUS; - volatile uint32_t BAUDDIV; -} UART_t; - - /* FreeRTOS interrupt handlers. */ extern void vPortSVCHandler( void ); extern void xPortPendSVHandler( void ); @@ -53,13 +37,13 @@ extern void TIMER1_Handler( void ); /* Exception handlers. */ static void HardFault_Handler( void ) __attribute__( ( naked ) ); static void Default_Handler( void ) __attribute__( ( naked ) ); -void Reset_Handler( void ); +void Reset_Handler( void ) __attribute__( ( naked ) ); extern int main( void ); extern uint32_t _estack; /* Vector table. */ -const uint32_t* isr_vector[] __attribute__((section(".isr_vector"))) = +const uint32_t* isr_vector[] __attribute__((section(".isr_vector"), used)) = { ( uint32_t * ) &_estack, ( uint32_t * ) &Reset_Handler, // Reset -15 @@ -68,15 +52,15 @@ const uint32_t* isr_vector[] __attribute__((section(".isr_vector"))) = ( uint32_t * ) &Default_Handler, // MemManage_Handler -12 ( uint32_t * ) &Default_Handler, // BusFault_Handler -11 ( uint32_t * ) &Default_Handler, // UsageFault_Handler -10 - 0, // reserved - 0, // reserved - 0, // reserved + 0, // reserved -9 + 0, // reserved -8 + 0, // reserved -7 0, // reserved -6 - ( uint32_t * ) &vPortSVCHandler, // SVC_Handler -5 - ( uint32_t * ) &Default_Handler, // DebugMon_Handler -4 - 0, // reserved - ( uint32_t * ) &xPortPendSVHandler, // PendSV handler -2 - ( uint32_t * ) &xPortSysTickHandler,// SysTick_Handler -1 + ( uint32_t * ) &vPortSVCHandler, // SVC_Handler -5 + ( uint32_t * ) &Default_Handler, // DebugMon_Handler -4 + 0, // reserved -3 + ( uint32_t * ) &xPortPendSVHandler, // PendSV handler -2 + ( uint32_t * ) &xPortSysTickHandler,// SysTick_Handler -1 0, 0, 0, @@ -86,7 +70,7 @@ const uint32_t* isr_vector[] __attribute__((section(".isr_vector"))) = 0, 0, ( uint32_t * ) TIMER0_Handler, // Timer 0 - ( uint32_t * ) TIMER1_Handler, // Timer 1 + ( uint32_t * ) TIMER1_Handler, // Timer 1 0, 0, 0, @@ -99,7 +83,7 @@ void Reset_Handler( void ) } /* Variables used to store the value of registers at the time a hardfault - * occurs. These are volatile to try and prevent the compiler/linker optimising + * occurs. These are volatile to try and prevent the compiler/linker optimizing * them away as the variables never actually get used. */ volatile uint32_t r0; volatile uint32_t r1; @@ -113,7 +97,7 @@ volatile uint32_t psr;/* Program status register. */ /* Called from the hardfault handler to provide information on the processor * state at the time of the fault. */ -void prvGetRegistersFromStack( uint32_t *pulFaultStackAddress ) +__attribute__( ( used ) ) void prvGetRegistersFromStack( uint32_t *pulFaultStackAddress ) { r0 = pulFaultStackAddress[ 0 ]; r1 = pulFaultStackAddress[ 1 ]; @@ -138,13 +122,12 @@ void Default_Handler( void ) __asm volatile ( ".align 8 \n" - " ldr r3, NVIC_INT_CTRL_CONST \n" /* Load the address of the interrupt control register into r3. */ + " ldr r3, =0xe000ed04 \n" /* Load the address of the interrupt control register into r3. */ " ldr r2, [r3, #0] \n" /* Load the value of the interrupt control register into r2. */ " uxtb r2, r2 \n" /* The interrupt number is in the least significant byte - clear all other bits. */ "Infinite_Loop: \n" /* Sit in an infinite loop - the number of the executing interrupt is held in r2. */ " b Infinite_Loop \n" - ".align 4 \n" - "NVIC_INT_CTRL_CONST: .word 0xe000ed04 \n" + " .ltorg \n" ); } @@ -158,9 +141,9 @@ void HardFault_Handler( void ) " mrseq r0, msp \n" " mrsne r0, psp \n" " ldr r1, [r0, #24] \n" - " ldr r2, handler2_address_const \n" + " ldr r2, =prvGetRegistersFromStack \n" " bx r2 \n" - " handler2_address_const: .word prvGetRegistersFromStack \n" + " .ltorg \n" ); } diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewp index 2af9104f3a5..e7955f066dc 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewp @@ -1,6 +1,6 @@ - 3 + 4 Debug @@ -11,7 +11,7 @@ General 3 - 33 + 36 1 1 + + + + ICCARM 2 - 37 + 38 1 1 + + AARM 2 - 11 + 12 1 1 + @@ -659,19 +688,11 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 - 25 + 27 1 1 + + + + @@ -1046,6 +1083,11 @@ + + BUILDACTION + 2 + + Blinky Demo @@ -1208,6 +1250,9 @@ $PROJ_DIR$\..\..\main_full.c + + $PROJ_DIR$\RegTest.S + System files diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt index 5e4ad93a2ad..41f7a12e6d2 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt @@ -1,6 +1,6 @@ - 3 + 4 Debug @@ -9,9 +9,9 @@ 1 C-STAT - 515 + 518 - 515 + 518 0 @@ -25,7 +25,7 @@ Debug\C-STAT - 2.3.1 + 2.6.0 @@ -356,6 +356,7 @@ + @@ -798,6 +799,7 @@ + @@ -817,6 +819,7 @@ + @@ -830,6 +833,7 @@ + @@ -840,7 +844,15 @@ - + + + + + + + + + @@ -876,6 +888,7 @@ + @@ -883,6 +896,7 @@ + @@ -900,6 +914,9 @@ + + + @@ -922,6 +939,7 @@ + @@ -946,6 +964,7 @@ + @@ -1002,6 +1021,11 @@ + + + + + @@ -1018,6 +1042,7 @@ + @@ -1048,6 +1073,7 @@ + @@ -1063,6 +1089,10 @@ + + + + @@ -1081,6 +1111,16 @@ + + + + + + + + + + @@ -1423,7 +1463,7 @@ Blinky Demo - $PROJ_DIR$\main_blinky.c + $PROJ_DIR$\..\..\main_blinky.c @@ -1431,25 +1471,25 @@ include - $PROJ_DIR$\..\..\Source\include\event_groups.h + $PROJ_DIR$\..\..\..\..\Source\include\event_groups.h - $PROJ_DIR$\..\..\Source\include\message_buffer.h + $PROJ_DIR$\..\..\..\..\Source\include\message_buffer.h - $PROJ_DIR$\..\..\Source\include\queue.h + $PROJ_DIR$\..\..\..\..\Source\include\queue.h - $PROJ_DIR$\..\..\Source\include\semphr.h + $PROJ_DIR$\..\..\..\..\Source\include\semphr.h - $PROJ_DIR$\..\..\Source\include\stream_buffer.h + $PROJ_DIR$\..\..\..\..\Source\include\stream_buffer.h - $PROJ_DIR$\..\..\Source\include\task.h + $PROJ_DIR$\..\..\..\..\Source\include\task.h - $PROJ_DIR$\..\..\Source\include\timers.h + $PROJ_DIR$\..\..\..\..\Source\include\timers.h @@ -1459,37 +1499,37 @@ ARM_CM3 - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM3\port.c - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM3\portasm.s MemMang - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + $PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_4.c - $PROJ_DIR$\..\..\Source\event_groups.c + $PROJ_DIR$\..\..\..\..\Source\event_groups.c - $PROJ_DIR$\..\..\Source\list.c + $PROJ_DIR$\..\..\..\..\Source\list.c - $PROJ_DIR$\..\..\Source\queue.c + $PROJ_DIR$\..\..\..\..\Source\queue.c - $PROJ_DIR$\..\..\Source\stream_buffer.c + $PROJ_DIR$\..\..\..\..\Source\stream_buffer.c - $PROJ_DIR$\..\..\Source\tasks.c + $PROJ_DIR$\..\..\..\..\Source\tasks.c - $PROJ_DIR$\..\..\Source\timers.c + $PROJ_DIR$\..\..\..\..\Source\timers.c @@ -1497,89 +1537,92 @@ Standard Demo Tasks - $PROJ_DIR$\..\Common\Minimal\AbortDelay.c + $PROJ_DIR$\..\..\..\Common\Minimal\AbortDelay.c - $PROJ_DIR$\..\Common\Minimal\BlockQ.c + $PROJ_DIR$\..\..\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\..\Common\Minimal\blocktim.c + $PROJ_DIR$\..\..\..\Common\Minimal\blocktim.c - $PROJ_DIR$\..\Common\Minimal\countsem.c + $PROJ_DIR$\..\..\..\Common\Minimal\countsem.c - $PROJ_DIR$\..\Common\Minimal\death.c + $PROJ_DIR$\..\..\..\Common\Minimal\death.c - $PROJ_DIR$\..\Common\Minimal\dynamic.c + $PROJ_DIR$\..\..\..\Common\Minimal\dynamic.c - $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\EventGroupsDemo.c - $PROJ_DIR$\..\Common\Minimal\GenQTest.c + $PROJ_DIR$\..\..\..\Common\Minimal\GenQTest.c - $PROJ_DIR$\..\Common\Minimal\integer.c + $PROJ_DIR$\..\..\..\Common\Minimal\integer.c - $PROJ_DIR$\..\Common\Minimal\IntQueue.c + $PROJ_DIR$\..\..\..\Common\Minimal\IntQueue.c - $PROJ_DIR$\IntQueueTimer.c + $PROJ_DIR$\..\..\IntQueueTimer.c - $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + $PROJ_DIR$\..\..\..\Common\Minimal\IntSemTest.c - $PROJ_DIR$\..\Common\Minimal\MessageBufferAMP.c + $PROJ_DIR$\..\..\..\Common\Minimal\MessageBufferAMP.c - $PROJ_DIR$\..\Common\Minimal\MessageBufferDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\MessageBufferDemo.c - $PROJ_DIR$\..\Common\Minimal\PollQ.c + $PROJ_DIR$\..\..\..\Common\Minimal\PollQ.c - $PROJ_DIR$\..\Common\Minimal\QPeek.c + $PROJ_DIR$\..\..\..\Common\Minimal\QPeek.c - $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + $PROJ_DIR$\..\..\..\Common\Minimal\QueueOverwrite.c - $PROJ_DIR$\..\Common\Minimal\QueueSet.c + $PROJ_DIR$\..\..\..\Common\Minimal\QueueSet.c - $PROJ_DIR$\..\Common\Minimal\QueueSetPolling.c + $PROJ_DIR$\..\..\..\Common\Minimal\QueueSetPolling.c - $PROJ_DIR$\..\Common\Minimal\recmutex.c + $PROJ_DIR$\..\..\..\Common\Minimal\recmutex.c - $PROJ_DIR$\..\Common\Minimal\semtest.c + $PROJ_DIR$\..\..\..\Common\Minimal\semtest.c - $PROJ_DIR$\..\Common\Minimal\StaticAllocation.c + $PROJ_DIR$\..\..\..\Common\Minimal\StaticAllocation.c - $PROJ_DIR$\..\Common\Minimal\StreamBufferDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\StreamBufferDemo.c - $PROJ_DIR$\..\Common\Minimal\StreamBufferInterrupt.c + $PROJ_DIR$\..\..\..\Common\Minimal\StreamBufferInterrupt.c - $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + $PROJ_DIR$\..\..\..\Common\Minimal\TaskNotify.c - $PROJ_DIR$\..\Common\Minimal\TaskNotifyArray.c + $PROJ_DIR$\..\..\..\Common\Minimal\TaskNotifyArray.c - $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\TimerDemo.c - $PROJ_DIR$\main_full.c + $PROJ_DIR$\..\..\main_full.c + + + $PROJ_DIR$\RegTest.S @@ -1589,9 +1632,9 @@ - $PROJ_DIR$\FreeRTOSConfig.h + $PROJ_DIR$\..\..\FreeRTOSConfig.h - $PROJ_DIR$\main.c + $PROJ_DIR$\..\..\main.c diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RegTest.S b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RegTest.S new file mode 100644 index 00000000000..5b0541fc8a6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RegTest.S @@ -0,0 +1,181 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + + RSEG CODE:CODE(2) + thumb + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + + PUBLIC vRegTest1Implementation + PUBLIC vRegTest2Implementation + +/*-----------------------------------------------------------*/ + +vRegTest1Implementation + + /* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + +reg1_loop: + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + +/*-----------------------------------------------------------*/ + + +vRegTest2Implementation + + /* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + +reg2_loop: + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop + +/*-----------------------------------------------------------*/ + + + END + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c index 838dcf57e85..3798c9d5978 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -43,7 +43,7 @@ * Use the following commands to start the application running in a way that * enables the debugger to connect, omit the "-s -S" to run the project without * the debugger: - * qemu-system-arm -machine mps2-an385 -cpu cortex-m3 -kernel [path-to]/RTOSDemo.out -nographic -serial stdio -semihosting -semihosting-config enable=on,target=native -s -S + * qemu-system-arm -machine mps2-an385 -cpu cortex-m3 -kernel [path-to]/RTOSDemo.out -monitor none -nographic -serial stdio -s -S */ /* FreeRTOS includes. */ @@ -54,26 +54,33 @@ #include #include -/* This project provides two demo applications. A simple blinky style demo -application, and a more comprehensive test and demo application. The -mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. +/* TODO: Steps for adding TraceRecorder are tagged with comments like this. */ +/* TODO: This way, Eclipse IDEs can provide a summary in the Tasks window. */ +/* TODO: To open Tasks, select Window -> Show View -> Tasks (or Other) */ -If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built. -The blinky demo is implemented and described in main_blinky.c. +/* TODO TraceRecorder (Step 1): Include trcRecorder.h to access the API. */ +#include -If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and -demo application will be built. The comprehensive test and demo application is -implemented and described in main_full.c. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 +/* This project provides two demo applications. A simple blinky style demo + * application, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. + * + * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built. + * The blinky demo is implemented and described in main_blinky.c. + * + * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and + * demo application will be built. The comprehensive test and demo application is + * implemented and described in main_full.c. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /* printf() output uses the UART. These constants define the addresses of the -required UART registers. */ -#define UART0_ADDRESS ( 0x40004000UL ) -#define UART0_DATA ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 0UL ) ) ) ) -#define UART0_STATE ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 4UL ) ) ) ) -#define UART0_CTRL ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 8UL ) ) ) ) -#define UART0_BAUDDIV ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 16UL ) ) ) ) -#define TX_BUFFER_MASK ( 1UL ) + * required UART registers. */ +#define UART0_ADDRESS ( 0x40004000UL ) +#define UART0_DATA ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 0UL ) ) ) ) +#define UART0_STATE ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 4UL ) ) ) ) +#define UART0_CTRL ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 8UL ) ) ) ) +#define UART0_BAUDDIV ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 16UL ) ) ) ) +#define TX_BUFFER_MASK ( 1UL ) /* * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. @@ -98,212 +105,251 @@ static void prvUARTInit( void ); void main( void ) { - /* See https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html for - instructions. */ - - /* Hardware initialisation. printf() output uses the UART for IO. */ - prvUARTInit(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif + /* See https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html for + * instructions. */ + + /* Initializing TraceRecorder. Using #if (configUSE_TRACE_FACILITY == 1) + * is normally not needed. TraceRecorder API calls are normally ignored + * and produce no code when configUSE_TRACE_FACILITY is 0, assuming + * trcRecorder.h is included. However, this was missing for + * xTraceTimestampSetPeriod() in TraceRecorder v4.10.2. */ +#if (configUSE_TRACE_FACILITY == 1) + + /* TODO TraceRecorder (Step 2): Call xTraceInitialize early in main(). + * This should be called before any FreeRTOS calls are made. */ + xTraceInitialize(); + + /* TODO TraceRecorder (Step 3): Call xTraceEnable to start tracing. */ + xTraceEnable(TRC_START); + + /* Extra step needed for using TraceRecorder on QEMU. */ + xTraceTimestampSetPeriod(configCPU_CLOCK_HZ/configTICK_RATE_HZ); + +#endif + + /* Hardware initialisation. printf() output uses the UART for IO. */ + prvUARTInit(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created using the dynamic allocation (as opposed to - static allocation) option. It is also called by various parts of the - demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the - size of the heap available to pvPortMalloc() is defined by - configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() - API function can be used to query the size of free heap space that remains - (although it does not provide information on how the remaining heap might be - fragmented). See http://www.freertos.org/a00111.html for more - information. */ - printf( "\r\n\r\nMalloc failed\r\n" ); - portDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created using the dynamic allocation (as opposed to + * static allocation) option. It is also called by various parts of the + * demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the + * size of the heap available to pvPortMalloc() is defined by + * configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() + * API function can be used to query the size of free heap space that remains + * (although it does not provide information on how the remaining heap might be + * fragmented). See http://www.freertos.org/a00111.html for more + * information. */ + printf( "\r\n\r\nMalloc failed\r\n" ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If application tasks make use of the - vTaskDelete() API function to delete themselves then it is also important - that vApplicationIdleHook() is permitted to return to its calling function, - because it is the responsibility of the idle task to clean up memory - allocated by the kernel to any task that has since deleted itself. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If application tasks make use of the + * vTaskDelete() API function to delete themselves then it is also important + * that vApplicationIdleHook() is permitted to return to its calling function, + * because it is the responsibility of the idle task to clean up memory + * allocated by the kernel to any task that has since deleted itself. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - printf( "\r\n\r\nStack overflow in %s\r\n", pcTaskName ); - portDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + printf( "\r\n\r\nStack overflow in %s\r\n", pcTaskName ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - extern void vFullDemoTickHookFunction( void ); - - vFullDemoTickHookFunction(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ + + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + { + extern void vFullDemoTickHookFunction( void ); + + vFullDemoTickHookFunction(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ } /*-----------------------------------------------------------*/ void vApplicationDaemonTaskStartupHook( void ) { - /* This function will be called once only, when the daemon task starts to - execute (sometimes called the timer task). This is useful if the - application includes initialisation code that would benefit from executing - after the scheduler has been started. */ + /* This function will be called once only, when the daemon task starts to + * execute (sometimes called the timer task). This is useful if the + * application includes initialisation code that would benefit from executing + * after the scheduler has been started. */ + + xTraceEnable(TRC_START); } /*-----------------------------------------------------------*/ -void vAssertCalled( const char *pcFileName, uint32_t ulLine ) +void vAssertCalled( const char * pcFileName, + uint32_t ulLine ) { -volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; - - /* Called if an assertion passed to configASSERT() fails. See - http://www.freertos.org/a00110.html#configASSERT for more information. */ - - printf( "ASSERT! Line %d, file %s\r\n", ( int ) ulLine, pcFileName ); - - taskENTER_CRITICAL(); - { - /* You can step out of this function to debug the assertion by using - the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero - value. */ - while( ulSetToNonZeroInDebuggerToContinue == 0 ) - { - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - } - } - taskEXIT_CRITICAL(); + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + + printf( "ASSERT! Line %d, file %s\r\n", ( int ) ulLine, pcFileName ); + + taskENTER_CRITICAL(); + { + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ static void prvUARTInit( void ) { - UART0_BAUDDIV = 16; - UART0_CTRL = 1; + UART0_BAUDDIV = 16; + UART0_CTRL = 1; } /*-----------------------------------------------------------*/ -int __write( int iFile, char *pcString, int iStringLength ) +int __write( int iFile, + char * pcString, + int iStringLength ) { - int iNextChar; + int iNextChar; + + /* Avoid compiler warnings about unused parameters. */ + ( void ) iFile; - /* Avoid compiler warnings about unused parameters. */ - ( void ) iFile; + /* Output the formatted string to the UART. */ + for( iNextChar = 0; iNextChar < iStringLength; iNextChar++ ) + { + while( ( UART0_STATE & TX_BUFFER_MASK ) != 0 ) + { + } - /* Output the formatted string to the UART. */ - for( iNextChar = 0; iNextChar < iStringLength; iNextChar++ ) - { - while( ( UART0_STATE & TX_BUFFER_MASK ) != 0 ); - UART0_DATA = *pcString; - pcString++; - } + UART0_DATA = *pcString; + pcString++; + } - return iStringLength; + return iStringLength; } /*-----------------------------------------------------------*/ -void *malloc( size_t size ) +void * malloc( size_t size ) { - ( void ) size; + ( void ) size; - /* This project uses heap_4 so doesn't set up a heap for use by the C - library - but something is calling the C library malloc(). See - https://freertos.org/a00111.html for more information. */ - printf( "\r\n\r\nUnexpected call to malloc() - should be usine pvPortMalloc()\r\n" ); - portDISABLE_INTERRUPTS(); - for( ;; ); + /* This project uses heap_4 so doesn't set up a heap for use by the C + * library - but something is calling the C library malloc(). See + * https://freertos.org/a00111.html for more information. */ + printf( "\r\n\r\nUnexpected call to malloc() - should be usine pvPortMalloc()\r\n" ); + portDISABLE_INTERRUPTS(); + for( ; ; ) + { + } } - diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c index 27d0d2a293d..5e5e10f9572 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -66,29 +66,29 @@ #include "queue.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The times are converted from -milliseconds to ticks using the pdMS_TO_TICKS() macro. */ -#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) -#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + * milliseconds to ticks using the pdMS_TO_TICKS() macro. */ +#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) +#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) /* The number of items the queue can hold at once. */ -#define mainQUEUE_LENGTH ( 2 ) +#define mainQUEUE_LENGTH ( 2 ) /* The values sent to the queue receive task from the queue send task and the -queue send software timer respectively. */ -#define mainVALUE_SENT_FROM_TASK ( 100UL ) -#define mainVALUE_SENT_FROM_TIMER ( 200UL ) + * queue send software timer respectively. */ +#define mainVALUE_SENT_FROM_TASK ( 100UL ) +#define mainVALUE_SENT_FROM_TIMER ( 200UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * The callback function executed when the software timer expires. @@ -108,128 +108,152 @@ static TimerHandle_t xTimer = NULL; /*** SEE THE COMMENTS AT THE TOP OF THIS FILE ***/ void main_blinky( void ) { -const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this simple case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer, but don't start it yet. */ - xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ - xTimerPeriod, /* The period of the software timer in ticks. */ - pdTRUE, /* xAutoReload is set to pdTRUE, so this is an auto-reload timer. */ - NULL, /* The timer's ID is not used. */ - prvQueueSendTimerCallback );/* The function executed when the timer expires. */ - - xTimerStart( xTimer, 0 ); /* The scheduler has not started so use a block time of 0. */ - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. NOTE: This demo uses static allocation - for the idle and timer tasks so this line should never execute. */ - for( ;; ); + const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + /* TODO TraceRecorder (Tweak 4): Setting a name for the queue (optional). */ + vTraceSetQueueName(xQueue, "Blinky-Queue"); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this simple case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer, but don't start it yet. */ + xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ + xTimerPeriod, /* The period of the software timer in ticks. */ + pdTRUE, /* xAutoReload is set to pdTRUE, so this is an auto-reload timer. */ + NULL, /* The timer's ID is not used. */ + prvQueueSendTimerCallback ); /* The function executed when the timer expires. */ + + xTimerStart( xTimer, 0 ); /* The scheduler has not started so use a block time of 0. */ + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. NOTE: This demo uses static allocation + * for the idle and timer tasks so this line should never execute. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, pdMS_TO_TICKS() was used to - convert a time specified in milliseconds into a time specified in ticks. - While in the Blocked state this task will not consume any CPU time. */ - vTaskDelayUntil( &xNextWakeTime, xBlockTime ); - - /* Send to the queue - causing the queue receive task to unblock and - write to the console. 0 is used as the block time so the send operation - will not block - it shouldn't need to block as the queue should always - have at least one space at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in ticks. + * While in the Blocked state this task will not consume any CPU time. */ + vTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock and + * write to the console. 0 is used as the block time so the send operation + * will not block - it shouldn't need to block as the queue should always + * have at least one space at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) { -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; + const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; - /* This is the software timer callback function. The software timer has a - period of two seconds and is reset each time a key is pressed. This - callback function will execute if the timer expires, which will only happen - if a key is not pressed for two seconds. */ + /* This is the software timer callback function. The software timer has a + * period of two seconds and is reset each time a key is pressed. This + * callback function will execute if the timer expires, which will only happen + * if a key is not pressed for two seconds. */ - /* Avoid compiler warnings resulting from the unused parameter. */ - ( void ) xTimerHandle; + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; - /* Send to the queue - causing the queue receive task to unblock and - write out a message. This function is called from the timer/daemon task, so - must not block. Hence the block time is set to 0. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon task, so + * must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -uint32_t ulReceivedValue; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. It will not use any CPU time while it is in the - Blocked state. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it an expected value? */ - if( ulReceivedValue == mainVALUE_SENT_FROM_TASK ) - { - /* It is normally not good to call printf() from an embedded system, - although it is ok in this simulated case. */ - printf( "Message received from task\r\n" ); - } - else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER ) - { - printf( "Message received from software timer\r\n" ); - } - else - { - printf( "Unexpected message\r\n" ); - } - } + uint32_t ulReceivedValue; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* TraceRecorder: Registering a channel name for the user events. */ + TraceStringHandle_t xUserEventLogChannel; + xTraceStringRegister("Log", &xUserEventLogChannel); + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it an expected value? */ + if( ulReceivedValue == mainVALUE_SENT_FROM_TASK ) + { + /* It is normally not good to call printf() from an embedded system, + * although it is ok in this simulated case. */ + printf( "Message received from task\r\n" ); + + /****************************************************************** + * TODO TraceRecorder (Tweak 5): Added User Events (xTracePrint). + * Can be a better alternative to printf (faster and thread-safe). + * xTracePrint is similar to puts(), i.e. strings only. + * xTracePrintF is similar to printf (with integer arguments). + * Examples: + * xTracePrint(channel, "Something happened!"); + * xTracePrintF(channel, "Value 1: %d, Value 2: %d", val1, val2); + * See trcPrint.h for details. + *****************************************************************/ + xTracePrint(xUserEventLogChannel, "Message received from task"); + } + else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER ) + { + printf( "Message received from software timer\r\n" ); + + xTracePrint(xUserEventLogChannel, + "Message received from software timer"); + } + else + { + printf( "Unexpected message\r\n" ); + + xTracePrint(xUserEventLogChannel, "Unexpected message"); + } + } } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c index 0838a4d64cd..38d50c4d5b0 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -98,222 +98,311 @@ /*-----------------------------------------------------------*/ /* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* Stack sizes are defined relative to configMINIMAL_STACK_SIZE so they scale -across projects that have that constant set differently - in this case the -constant is different depending on the compiler in use. */ -#define mainMESSAGE_BUFFER_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) + * across projects that have that constant set differently - in this case the + * constant is different depending on the compiler in use. */ +#define mainMESSAGE_BUFFER_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) +#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) + +/* Parameters that are passed into the register check tasks solely for the + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + /*-----------------------------------------------------------*/ +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void * pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void * pvParameters ); +extern void vRegTest2Implementation( void ); + /* The task that checks the operation of all the other standard demo tasks, as * described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the + * register test tasks to the check task. If the variables keep incrementing, + * then the register test tasks have not discovered any errors. If a variable + * stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ void main_full( void ) { - /* Start the standard demo tasks. */ - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartInterruptQueueTasks(); - vStartRecursiveMutexTasks(); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartQueuePeekTasks(); - vStartQueueSetTasks(); - vStartEventGroupTasks(); - vStartMessageBufferTasks( mainMESSAGE_BUFFER_STACK_SIZE ); - vStartStreamBufferTasks(); - vCreateAbortDelayTasks(); - vStartCountingSemaphoreTasks(); - vStartDynamicPriorityTasks(); - vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE ); - vStartQueueOverwriteTask( tskIDLE_PRIORITY ); - vStartQueueSetPollingTask(); - vStartStaticallyAllocatedTasks(); - vStartTaskNotifyTask(); - vStartTaskNotifyArrayTask(); - vStartTimerDemoTask( 50 ); - vStartStreamBufferInterruptDemo(); - vStartInterruptSemaphoreTasks(); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If configSUPPORT_STATIC_ALLOCATION was false then execution would only - get here if there was insufficient heap memory to create either the idle or - timer tasks. As static allocation is used execution should never be able - to reach here. */ - for( ;; ); + /* Start the standard demo tasks. */ + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartInterruptQueueTasks(); + vStartRecursiveMutexTasks(); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartQueuePeekTasks(); + vStartQueueSetTasks(); + vStartEventGroupTasks(); + vStartMessageBufferTasks( mainMESSAGE_BUFFER_STACK_SIZE ); + vStartStreamBufferTasks(); + vCreateAbortDelayTasks(); + vStartCountingSemaphoreTasks(); + vStartDynamicPriorityTasks(); + vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE ); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); + vStartQueueSetPollingTask(); + vStartStaticallyAllocatedTasks(); + vStartTaskNotifyTask(); + vStartTaskNotifyArrayTask(); + vStartTimerDemoTask( 50 ); + vStartStreamBufferInterruptDemo(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, /* Function that implements the task. */ + "Reg1", /* Human readable name for the task - not used by the kernel but helps debugging. */ + configMINIMAL_STACK_SIZE, /* Size of stack to allocate for the task - in words not bytes. */ + mainREG_TEST_TASK_1_PARAMETER, /* A parameter passed into the task to check parameter passing is working correctly. */ + tskIDLE_PRIORITY, /* Priority assigned to the task - must be between 0 (tskIDLE_PRIORITY) and (configMAX_PRIORITIES - 1). */ + NULL ); /* Can be used to pass a handle to the create task out of the xTaskCreate() function. */ + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + * tasks were running prior to their creation in order to ascertain whether + * or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If configSUPPORT_STATIC_ALLOCATION was false then execution would only + * get here if there was insufficient heap memory to create either the idle or + * timer tasks. As static allocation is used execution should never be able + * to reach here. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ /* See the comments at the top of this file. */ -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -static const char * pcMessage = "PASS"; -const TickType_t xTaskPeriod = pdMS_TO_TICKS( 5000UL ); -TickType_t xPreviousWakeTime; -extern uint32_t ulNestCount; + static const char * pcMessage = "PASS"; + unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + + const TickType_t xTaskPeriod = pdMS_TO_TICKS( 5000UL ); + TickType_t xPreviousWakeTime; + extern uint32_t ulNestCount; /* Avoid warning about unused parameter. */ ( void ) pvParameters; - xPreviousWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - vTaskDelayUntil( &xPreviousWakeTime, xTaskPeriod ); - - /* Has an error been found in any task? */ - if( xAreStreamBufferTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreStreamBufferTasksStillRunning() returned false"; - } - else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreMessageBufferTasksStillRunning() returned false"; - } - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreGenericQueueTasksStillRunning() returned false"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcMessage = "xIsCreateTaskStillRunning() returned false"; - } - else if( xAreIntQueueTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreIntQueueTasksStillRunning() returned false"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreBlockTimeTestTasksStillRunning() returned false"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreSemaphoreTasksStillRunning() returned false"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - pcMessage = "xArePollingQueuesStillRunning() returned false"; - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreQueuePeekTasksStillRunning() returned false"; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreRecursiveMutexTasksStillRunning() returned false"; - } - else if( xAreQueueSetTasksStillRunning() != pdPASS ) - { - pcMessage = "xAreQueueSetTasksStillRunning() returned false"; - } - else if( xAreEventGroupTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreEventGroupTasksStillRunning() returned false"; - } - else if( xAreAbortDelayTestTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreAbortDelayTestTasksStillRunning() returned false"; - } - else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreCountingSemaphoreTasksStillRunning() returned false"; - } - else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreDynamicPriorityTasksStillRunning() returned false"; - } - else if( xAreMessageBufferAMPTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreMessageBufferAMPTasksStillRunning() returned false"; - } - else if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) - { - pcMessage = "xIsQueueOverwriteTaskStillRunning() returned false"; - } - else if( xAreQueueSetPollTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreQueueSetPollTasksStillRunning() returned false"; - } - else if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreStaticAllocationTasksStillRunning() returned false"; - } - else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreTaskNotificationTasksStillRunning() returned false"; - } - else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreTaskNotificationArrayTasksStillRunning() returned false"; - } - else if( xAreTimerDemoTasksStillRunning( xTaskPeriod ) != pdTRUE ) - { - pcMessage = "xAreTimerDemoTasksStillRunning() returned false"; - } - else if( xIsInterruptStreamBufferDemoStillRunning() != pdTRUE ) - { - pcMessage = "xIsInterruptStreamBufferDemoStillRunning() returned false"; - } - else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "xAreInterruptSemaphoreTasksStillRunning() returned false"; - } - - /* It is normally not good to call printf() from an embedded system, - although it is ok in this simulated case. */ - printf( "%s : %d (%d)\r\n", pcMessage, (int) xTaskGetTickCount(), ( int ) ulNestCount ); - } + xPreviousWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + vTaskDelayUntil( &xPreviousWakeTime, xTaskPeriod ); + + /* Has an error been found in any task? */ + if( xAreStreamBufferTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreStreamBufferTasksStillRunning() returned false"; + } + else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreMessageBufferTasksStillRunning() returned false"; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreGenericQueueTasksStillRunning() returned false"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcMessage = "xIsCreateTaskStillRunning() returned false"; + } + else if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreIntQueueTasksStillRunning() returned false"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreBlockTimeTestTasksStillRunning() returned false"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreSemaphoreTasksStillRunning() returned false"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + pcMessage = "xArePollingQueuesStillRunning() returned false"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreQueuePeekTasksStillRunning() returned false"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreRecursiveMutexTasksStillRunning() returned false"; + } + else if( xAreQueueSetTasksStillRunning() != pdPASS ) + { + pcMessage = "xAreQueueSetTasksStillRunning() returned false"; + } + else if( xAreEventGroupTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreEventGroupTasksStillRunning() returned false"; + } + else if( xAreAbortDelayTestTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreAbortDelayTestTasksStillRunning() returned false"; + } + else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreCountingSemaphoreTasksStillRunning() returned false"; + } + else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreDynamicPriorityTasksStillRunning() returned false"; + } + else if( xAreMessageBufferAMPTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreMessageBufferAMPTasksStillRunning() returned false"; + } + else if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + pcMessage = "xIsQueueOverwriteTaskStillRunning() returned false"; + } + else if( xAreQueueSetPollTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreQueueSetPollTasksStillRunning() returned false"; + } + else if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreStaticAllocationTasksStillRunning() returned false"; + } + else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreTaskNotificationTasksStillRunning() returned false"; + } + else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreTaskNotificationArrayTasksStillRunning() returned false"; + } + else if( xAreTimerDemoTasksStillRunning( xTaskPeriod ) != pdTRUE ) + { + pcMessage = "xAreTimerDemoTasksStillRunning() returned false"; + } + else if( xIsInterruptStreamBufferDemoStillRunning() != pdTRUE ) + { + pcMessage = "xIsInterruptStreamBufferDemoStillRunning() returned false"; + } + else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "xAreInterruptSemaphoreTasksStillRunning() returned false"; + } + else if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + /* Check that the register test 1 task is still running. */ + pcMessage = "Error in RegTest 1"; + } + else if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + /* Check that the register test 2 task is still running. */ + pcMessage = "Error in RegTest 2"; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* It is normally not good to call printf() from an embedded system, + * although it is ok in this simulated case. */ + printf( "%s : %d (%d)\r\n", pcMessage, ( int ) xTaskGetTickCount(), ( int ) ulNestCount ); + } } /*-----------------------------------------------------------*/ void vFullDemoTickHookFunction( void ) { - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + + /* Call the event group ISR tests. */ + vPeriodicEventGroupsProcessing(); + + /* Exercise stream buffers from interrupts. */ + vPeriodicStreamBufferProcessing(); + + /* Exercise using queue overwrites from interrupts. */ + vQueueOverwritePeriodicISRDemo(); - /* Call the event group ISR tests. */ - vPeriodicEventGroupsProcessing(); + /* Exercise using Queue Sets from interrupts. */ + vQueueSetPollingInterruptAccess(); - /* Exercise stream buffers from interrupts. */ - vPeriodicStreamBufferProcessing(); + /* Exercise using task notifications from interrupts. */ + xNotifyTaskFromISR(); + xNotifyArrayTaskFromISR(); - /* Exercise using queue overwrites from interrupts. */ - vQueueOverwritePeriodicISRDemo(); + /* Exercise software timers from interrupts. */ + vTimerPeriodicISRTests(); - /* Exercise using Queue Sets from interrupts. */ - vQueueSetPollingInterruptAccess(); + /* Exercise stream buffers from interrupts. */ + vBasicStreamBufferSendFromISR(); - /* Exercise using task notifications from interrupts. */ - xNotifyTaskFromISR(); - xNotifyArrayTaskFromISR(); + /* Exercise semaphores from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ - /* Exercise software timers from interrupts. */ - vTimerPeriodicISRTests(); +static void prvRegTestTaskEntry1( void * pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } - /* Exercise stream buffers from interrupts. */ - vBasicStreamBufferSendFromISR(); + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void * pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } - /* Exercise semaphores from interrupts. */ - vInterruptSemaphorePeriodicTest(); + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/.gitignore new file mode 100644 index 00000000000..f4bd332c97f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/.gitignore @@ -0,0 +1,3 @@ +Listings/ +Objects/ +*.uvguix.* diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h index c51491bf20d..1131bcc5f28 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -142,6 +142,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c index 57412954d1c..06a1c6b54b9 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S index 77f656b20b9..64dace52116 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S @@ -1,10 +1,11 @@ /* File: startup_ARMCM4.S * Purpose: startup file for Cortex-M4 devices. Should use with * GCC for ARM Embedded Processors - * Version: V2.0 - * Date: 16 August 2013 + * Version: V2.01 + * Date: 12 June 2014 * -/* Copyright (c) 2011 - 2013 ARM LIMITED + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -30,6 +31,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ + .syntax unified .arch armv7e-m diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx index ed14f58feec..72dad3be84c 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx @@ -10,7 +10,7 @@ RTOSDemo 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::..\..\Program Files (x86)\ARM_Compiler_5.06u7 + 5060960::V5.06 update 7 (build 960)::.\ARM_Compiler_5.06u7 0 @@ -463,6 +463,57 @@ mpu_wrappers_v2.c 1 ..\..\..\Source\portable\Common\mpu_wrappers_v2.c + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --diag_suppress=1296 + + + + + + + stream_buffer.c diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c index 0821c57f703..c9cae6af16a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c index c8fd35b9a3a..cb2fdf705d6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -55,22 +55,22 @@ /*-----------------------------------------------------------*/ /* Misc constants. */ -#define mainDONT_BLOCK ( 0 ) +#define mainDONT_BLOCK ( 0 ) /* GCC specifics. */ -#define mainALIGN_TO( x ) __attribute__((aligned(x))) +#define mainALIGN_TO( x ) __attribute__( ( aligned( x ) ) ) /* Hardware register addresses. */ -#define mainVTOR ( * ( volatile uint32_t * ) 0xE000ED08 ) +#define mainVTOR ( *( volatile uint32_t * ) 0xE000ED08 ) /* The period of the timer must be less than the rate at which -configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the -check task will think the timer has stopped. */ -#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 ) + * configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the + * check task will think the timer has stopped. */ +#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 ) /* The name of the task that is deleted by the Idle task is used in a couple of -places, so is #defined. */ -#define mainTASK_TO_DELETE_NAME "DeleteMe" + * places, so is #defined. */ +#define mainTASK_TO_DELETE_NAME "DeleteMe" /*-----------------------------------------------------------*/ /* Prototypes for functions that implement tasks. -----------*/ @@ -98,8 +98,8 @@ places, so is #defined. */ * User mode, and vRegTest2Implementation() receives the task handle using its * parameter. */ -extern void vRegTest1Implementation( void *pvParameters ); -extern void vRegTest2Implementation( void *pvParameters ); +extern void vRegTest1Implementation( void * pvParameters ); +extern void vRegTest2Implementation( void * pvParameters ); /* * The second two register test tasks are similar to the first two, but do test @@ -110,9 +110,9 @@ extern void vRegTest2Implementation( void *pvParameters ); * * The functions ending 'Implementation' are called by the register check tasks. */ -static void prvRegTest3Task( void *pvParameters ); +static void prvRegTest3Task( void * pvParameters ); extern void vRegTest3Implementation( void ); -static void prvRegTest4Task( void *pvParameters ); +static void prvRegTest4Task( void * pvParameters ); extern void vRegTest4Implementation( void ); /* @@ -130,27 +130,27 @@ extern void vRegTest4Implementation( void ); * either pass or fail to the terminal, depending on the status of the reg * test tasks. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); /* * Prototype for a task created in User mode using the original vTaskCreate() * API function. The task demonstrates the characteristics of such a task, * before simply deleting itself. */ -static void prvOldStyleUserModeTask( void *pvParameters ); +static void prvOldStyleUserModeTask( void * pvParameters ); /* * Prototype for a task created in Privileged mode using the original * vTaskCreate() API function. The task demonstrates the characteristics of * such a task, before simply deleting itself. */ -static void prvOldStylePrivilegedModeTask( void *pvParameters ); +static void prvOldStylePrivilegedModeTask( void * pvParameters ); /* * A task that exercises the API of various RTOS objects before being deleted by * the Idle task. This is done for MPU API code coverage test purposes. */ -static void prvTaskToDelete( void *pvParameters ); +static void prvTaskToDelete( void * pvParameters ); /* * Functions called by prvTaskToDelete() to exercise the MPU API. @@ -169,7 +169,7 @@ static void prvSetupHardware( void ); * is simpler to call from asm code than the normal vTaskDelete() API function. * It has the noinline attribute because it is called from asm code. */ -void vMainDeleteMe( void ) __attribute__((noinline)); +void vMainDeleteMe( void ) __attribute__( ( noinline ) ); /* * Used by the first two reg test tasks and a software timer callback function @@ -178,7 +178,8 @@ void vMainDeleteMe( void ) __attribute__((noinline)); * task detects an error it will delete itself, and in so doing prevent itself * from sending any more 'I'm Alive' messages to the check task. */ -void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber ); +void vMainSendImAlive( QueueHandle_t xHandle, + uint32_t ulTaskNumber ); /* * The check task is created with access to three memory regions (plus its @@ -200,118 +201,118 @@ static void prvTimerCallback( TimerHandle_t xExpiredTimer ); * Simple routine to print a string to ITM for viewing in the Keil serial debug * viewer. */ -static void prvITMPrintString( const char *pcString ); +static void prvITMPrintString( const char * pcString ); /*-----------------------------------------------------------*/ /* The handle of the queue used to communicate between tasks and between tasks -and interrupts. Note that this is a global scope variable that falls outside of -any MPU region. As such other techniques have to be used to allow the tasks -to gain access to the queue. See the comments in the tasks themselves for -further information. */ + * and interrupts. Note that this is a global scope variable that falls outside of + * any MPU region. As such other techniques have to be used to allow the tasks + * to gain access to the queue. See the comments in the tasks themselves for + * further information. */ QueueHandle_t xGlobalScopeCheckQueue = NULL; /* Holds the handle of a task that is deleted in the idle task hook - this is -done for code coverage test purposes only. */ + * done for code coverage test purposes only. */ static TaskHandle_t xTaskToDelete = NULL; /* The timer that periodically sends data to the check task on the queue. */ static TimerHandle_t xTimer = NULL; -#if defined ( __GNUC__ ) - extern uint32_t __FLASH_segment_start__[]; - extern uint32_t __FLASH_segment_end__[]; - extern uint32_t __SRAM_segment_start__[]; - extern uint32_t __SRAM_segment_end__[]; - extern uint32_t __privileged_functions_start__[]; - extern uint32_t __privileged_functions_end__[]; - extern uint32_t __privileged_data_start__[]; - extern uint32_t __privileged_data_end__[]; - extern uint32_t __privileged_functions_actual_end__[]; - extern uint32_t __privileged_data_actual_end__[]; -#else - extern uint32_t Image$$ER_FREERTOS_SYSTEM_CALLS$$Base; - extern uint32_t Image$$ER_FREERTOS_SYSTEM_CALLS$$Limit; - - const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0xE0000UL; - const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x100000UL; - const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x100000UL; - const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x120000UL; - const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0xE0000UL; - const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0xF0000UL; - const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_FREERTOS_SYSTEM_CALLS$$Base ); - const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_FREERTOS_SYSTEM_CALLS$$Limit ); - const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x100000UL; - const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x108000UL; -#endif +#if defined( __GNUC__ ) + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + extern uint32_t __privileged_functions_actual_end__[]; + extern uint32_t __privileged_data_actual_end__[]; +#else /* if defined( __GNUC__ ) */ + extern uint32_t Image$$ER_FREERTOS_SYSTEM_CALLS$$Base; + extern uint32_t Image$$ER_FREERTOS_SYSTEM_CALLS$$Limit; + + const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0xE0000UL; + const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x100000UL; + const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x100000UL; + const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x120000UL; + const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0xE0000UL; + const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0xF0000UL; + const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_FREERTOS_SYSTEM_CALLS$$Base ); + const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_FREERTOS_SYSTEM_CALLS$$Limit ); + const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x100000UL; + const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x108000UL; +#endif /* if defined( __GNUC__ ) */ /*-----------------------------------------------------------*/ /* Data used by the 'check' task. ---------------------------*/ /*-----------------------------------------------------------*/ /* Define the constants used to allocate the check task stack. Note that the -stack size is defined in words, not bytes. */ -#define mainCHECK_TASK_STACK_SIZE_WORDS 128 -#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * stack size is defined in words, not bytes. */ +#define mainCHECK_TASK_STACK_SIZE_WORDS 128 +#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stack that will be used by the check task. The kernel will - automatically create an MPU region for the stack. The stack alignment must - match its size, so if 128 words are reserved for the stack then it must be - aligned to ( 128 * 4 ) bytes. */ + * automatically create an MPU region for the stack. The stack alignment must + * match its size, so if 128 words are reserved for the stack then it must be + * aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainCHECK_TASK_STACK_ALIGNMENT ); /* Declare three arrays - an MPU region will be created for each array -using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE -MPU FUNCTIONALITY, the data is not used by the check tasks primary function -of monitoring the reg test tasks and printing out status information. - -Note that the arrays allocate slightly more RAM than is actually assigned to -the MPU region. This is to permit writes off the end of the array to be -detected even when the arrays are placed in adjacent memory locations (with no -gaps between them). The align size must be a power of two. */ -#define mainREAD_WRITE_ARRAY_SIZE 130 -#define mainREAD_WRITE_ALIGN_SIZE 128 + * using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE + * MPU FUNCTIONALITY, the data is not used by the check tasks primary function + * of monitoring the reg test tasks and printing out status information. + * + * Note that the arrays allocate slightly more RAM than is actually assigned to + * the MPU region. This is to permit writes off the end of the array to be + * detected even when the arrays are placed in adjacent memory locations (with no + * gaps between them). The align size must be a power of two. */ +#define mainREAD_WRITE_ARRAY_SIZE 130 +#define mainREAD_WRITE_ALIGN_SIZE 128 char cReadWriteArray[ mainREAD_WRITE_ARRAY_SIZE ] mainALIGN_TO( mainREAD_WRITE_ALIGN_SIZE ); -#define mainREAD_ONLY_ARRAY_SIZE 260 -#define mainREAD_ONLY_ALIGN_SIZE 256 +#define mainREAD_ONLY_ARRAY_SIZE 260 +#define mainREAD_ONLY_ALIGN_SIZE 256 char cReadOnlyArray[ mainREAD_ONLY_ARRAY_SIZE ] mainALIGN_TO( mainREAD_ONLY_ALIGN_SIZE ); -#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 -#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 +#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 +#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 char cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] mainALIGN_TO( mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ); /* The following two variables are used to communicate the status of the second -two register check tasks (tasks 3 and 4) to the check task. If the variables -keep incrementing, then the register check tasks have not discovered any errors. -If a variable stops incrementing, then an error has been found. The variables -overlay the array that the check task has access to so they can be read by the -check task without causing a memory fault. The check task has the highest -priority so will have finished with the array before the register test tasks -start to access it. */ -volatile uint32_t *pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); + * two register check tasks (tasks 3 and 4) to the check task. If the variables + * keep incrementing, then the register check tasks have not discovered any errors. + * If a variable stops incrementing, then an error has been found. The variables + * overlay the array that the check task has access to so they can be read by the + * check task without causing a memory fault. The check task has the highest + * priority so will have finished with the array before the register test tasks + * start to access it. */ +volatile uint32_t * pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), * pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); /* Fill in a TaskParameters_t structure to define the check task - this is the -structure passed to the xTaskCreateRestricted() function. */ + * structure passed to the xTaskCreateRestricted() function. */ static const TaskParameters_t xCheckTaskParameters = { - prvCheckTask, /* pvTaskCode - the function that implements the task. */ - "Check", /* pcName */ - mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ - ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT,/* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ - xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - - /* xRegions - In this case the xRegions array is used to create MPU regions - for all three of the arrays declared directly above. Each MPU region is - created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE - MPU FUNCTIONALITY, the data is not used by the check tasks primary function - of monitoring the reg test tasks and printing out status information.*/ - { - /* Base address Length Parameters */ - { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, - { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, - { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } - } + prvCheckTask, /* pvTaskCode - the function that implements the task. */ + "Check", /* pcName */ + mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ + ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ + xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + + /* xRegions - In this case the xRegions array is used to create MPU regions + * for all three of the arrays declared directly above. Each MPU region is + * created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE + * MPU FUNCTIONALITY, the data is not used by the check tasks primary function + * of monitoring the reg test tasks and printing out status information.*/ + { + /* Base address Length Parameters */ + { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, + { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, + { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } + } }; @@ -321,49 +322,49 @@ static const TaskParameters_t xCheckTaskParameters = /*-----------------------------------------------------------*/ /* Define the constants used to allocate the reg test task stacks. Note that -that stack size is defined in words, not bytes. */ -#define mainREG_TEST_STACK_SIZE_WORDS 128 -#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * that stack size is defined in words, not bytes. */ +#define mainREG_TEST_STACK_SIZE_WORDS 128 +#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stacks that will be used by the reg test tasks. The kernel will -automatically create an MPU region for the stack. The stack alignment must -match its size, so if 128 words are reserved for the stack then it must be -aligned to ( 128 * 4 ) bytes. */ + * automatically create an MPU region for the stack. The stack alignment must + * match its size, so if 128 words are reserved for the stack then it must be + * aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xRegTest1Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); static portSTACK_TYPE xRegTest2Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); /* Fill in a TaskParameters_t structure per reg test task to define the tasks. */ static const TaskParameters_t xRegTest1Parameters = { - vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */ - "RegTest1", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ - xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */ + "RegTest1", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ + xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ static TaskParameters_t xRegTest2Parameters = { - vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */ - "RegTest2", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ - tskIDLE_PRIORITY, /* uxPriority */ - xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */ + "RegTest2", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + tskIDLE_PRIORITY, /* uxPriority */ + xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ @@ -373,768 +374,789 @@ static TaskParameters_t xRegTest2Parameters = /*-----------------------------------------------------------*/ /* Define the constants used to allocate the stack of the task that is -deleted. Note that that stack size is defined in words, not bytes. */ -#define mainDELETE_TASK_STACK_SIZE_WORDS 128 -#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * deleted. Note that that stack size is defined in words, not bytes. */ +#define mainDELETE_TASK_STACK_SIZE_WORDS 128 +#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stack that will be used by the task that gets deleted. The -kernel will automatically create an MPU region for the stack. The stack -alignment must match its size, so if 128 words are reserved for the stack -then it must be aligned to ( 128 * 4 ) bytes. */ + * kernel will automatically create an MPU region for the stack. The stack + * alignment must match its size, so if 128 words are reserved for the stack + * then it must be aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xDeleteTaskStack[ mainDELETE_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainTASK_TO_DELETE_STACK_ALIGNMENT ); static TaskParameters_t xTaskToDeleteParameters = { - prvTaskToDelete, /* pvTaskCode - the function that implements the task. */ - mainTASK_TO_DELETE_NAME, /* pcName */ - mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ - tskIDLE_PRIORITY + 1, /* uxPriority */ - xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + prvTaskToDelete, /* pvTaskCode - the function that implements the task. */ + mainTASK_TO_DELETE_NAME, /* pcName */ + mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + tskIDLE_PRIORITY + 1, /* uxPriority */ + xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ int main( void ) { - prvSetupHardware(); + prvSetupHardware(); - prvITMPrintString( "Starting\r\n" ); + prvITMPrintString( "Starting\r\n" ); - /* Create the queue used to pass "I'm alive" messages to the check task. */ - xGlobalScopeCheckQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + /* Create the queue used to pass "I'm alive" messages to the check task. */ + xGlobalScopeCheckQueue = xQueueCreate( 1, sizeof( uint32_t ) ); - /* One check task uses the task parameter to receive the queue handle. - This allows the file scope variable to be accessed from within the task. - The pvParameters member of xRegTest2Parameters can only be set after the - queue has been created so is set here. */ - xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue; + /* One check task uses the task parameter to receive the queue handle. + * This allows the file scope variable to be accessed from within the task. + * The pvParameters member of xRegTest2Parameters can only be set after the + * queue has been created so is set here. */ + xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue; - /* Create three test tasks. Handles to the created tasks are not required, - hence the second parameter is NULL. */ - xTaskCreateRestricted( &xRegTest1Parameters, NULL ); + /* Create three test tasks. Handles to the created tasks are not required, + * hence the second parameter is NULL. */ + xTaskCreateRestricted( &xRegTest1Parameters, NULL ); xTaskCreateRestricted( &xRegTest2Parameters, NULL ); - xTaskCreateRestricted( &xCheckTaskParameters, NULL ); - - /* Create a task that does nothing but ensure some of the MPU API functions - can be called correctly, then get deleted. This is done for code coverage - test purposes only. The task's handle is saved in xTaskToDelete so it can - get deleted in the idle task hook. */ - xTaskCreateRestricted( &xTaskToDeleteParameters, &xTaskToDelete ); - - /* Create the tasks that are created using the original xTaskCreate() API - function. */ - xTaskCreate( prvOldStyleUserModeTask, /* The function that implements the task. */ - "Task1", /* Text name for the task. */ - 100, /* Stack depth in words. */ - NULL, /* Task parameters. */ - 3, /* Priority and mode (user in this case). */ - NULL /* Handle. */ - ); - - xTaskCreate( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ - "Task2", /* Text name for the task. */ - 100, /* Stack depth in words. */ - NULL, /* Task parameters. */ - ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ - NULL /* Handle. */ - ); - - /* Create the third and fourth register check tasks, as described at the top - of this file. */ - xTaskCreate( prvRegTest3Task, "Reg3", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_3_PARAMETER, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTest4Task, "Reg4", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_4_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* Create and start the software timer. */ - xTimer = xTimerCreate( "Timer", /* Test name for the timer. */ - mainTIMER_PERIOD, /* Period of the timer. */ - pdTRUE, /* The timer will auto-reload itself. */ - ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */ - prvTimerCallback ); /* The function called when the timer expires. */ - configASSERT( xTimer ); - xTimerStart( xTimer, mainDONT_BLOCK ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - for( ;; ); + xTaskCreateRestricted( &xCheckTaskParameters, NULL ); + + /* Create a task that does nothing but ensure some of the MPU API functions + * can be called correctly, then get deleted. This is done for code coverage + * test purposes only. The task's handle is saved in xTaskToDelete so it can + * get deleted in the idle task hook. */ + xTaskCreateRestricted( &xTaskToDeleteParameters, &xTaskToDelete ); + + /* Create the tasks that are created using the original xTaskCreate() API + * function. */ + xTaskCreate( prvOldStyleUserModeTask, /* The function that implements the task. */ + "Task1", /* Text name for the task. */ + 100, /* Stack depth in words. */ + NULL, /* Task parameters. */ + 3, /* Priority and mode (user in this case). */ + NULL /* Handle. */ + ); + + xTaskCreate( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ + "Task2", /* Text name for the task. */ + 100, /* Stack depth in words. */ + NULL, /* Task parameters. */ + ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ + NULL /* Handle. */ + ); + + /* Create the third and fourth register check tasks, as described at the top + * of this file. */ + xTaskCreate( prvRegTest3Task, "Reg3", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_3_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest4Task, "Reg4", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_4_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create and start the software timer. */ + xTimer = xTimerCreate( "Timer", /* Test name for the timer. */ + mainTIMER_PERIOD, /* Period of the timer. */ + pdTRUE, /* The timer will auto-reload itself. */ + ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */ + prvTimerCallback ); /* The function called when the timer expires. */ + configASSERT( xTimer ); + xTimerStart( xTimer, mainDONT_BLOCK ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + * task. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { /* This task is created in privileged mode so can access the file scope -queue variable. Take a stack copy of this before the task is set into user -mode. Once that task is in user mode the file scope queue variable will no -longer be accessible but the stack copy will. */ -QueueHandle_t xQueue = xGlobalScopeCheckQueue; -int32_t lMessage; -uint32_t ulStillAliveCounts[ 3 ] = { 0 }; -const char *pcStatusMessage = "PASS\r\n"; -uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0; + * queue variable. Take a stack copy of this before the task is set into user + * mode. Once that task is in user mode the file scope queue variable will no + * longer be accessible but the stack copy will. */ + QueueHandle_t xQueue = xGlobalScopeCheckQueue; + int32_t lMessage; + uint32_t ulStillAliveCounts[ 3 ] = { 0 }; + const char * pcStatusMessage = "PASS\r\n"; + uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0; /* The register test tasks that also test the floating point registers increment -a counter on each iteration of their loop. The counters are inside the array -that this task has access to. */ -volatile uint32_t *pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* Demonstrate how the various memory regions can and can't be accessed. - The task privilege level is set down to user mode within this function. */ - prvTestMemoryRegions(); - - /* Clear overlaid reg test counters before entering the loop below. */ - *pulOverlaidCounter3 = 0UL; - *pulOverlaidCounter4 = 0UL; - - /* This loop performs the main function of the task, which is blocking - on a message queue then processing each message as it arrives. */ - for( ;; ) - { - /* Wait for the next message to arrive. */ - xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); - - switch( lMessage ) - { - case configREG_TEST_1_STILL_EXECUTING : - case configREG_TEST_2_STILL_EXECUTING : - case configTIMER_STILL_EXECUTING : - /* Message from the first or second register check task, or - the timer callback function. Increment the count of the - number of times the message source has sent the message as - the message source must still be executed. */ - ( ulStillAliveCounts[ lMessage ] )++; - break; - - case configPRINT_SYSTEM_STATUS : - /* Message from tick hook, time to print out the system - status. If messages have stopped arriving from either of - the first two reg test task or the timer callback then the - status must be set to fail. */ - if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) ) - { - /* One or both of the test tasks are no longer sending - 'still alive' messages. */ - pcStatusMessage = "FAIL\r\n"; - } - else - { - /* Reset the count of 'still alive' messages. */ - memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); - } - - /* Check that the register test 3 task is still incrementing - its counter, and therefore still running. */ - if( ulLastRegTest3CountValue == *pulOverlaidCounter3 ) - { - pcStatusMessage = "FAIL\r\n"; - } - ulLastRegTest3CountValue = *pulOverlaidCounter3; - - /* Check that the register test 4 task is still incrementing - its counter, and therefore still running. */ - if( ulLastRegTest4Value == *pulOverlaidCounter4 ) - { - pcStatusMessage = "FAIL\r\n"; - } - ulLastRegTest4Value = *pulOverlaidCounter4; - - /**** print pcStatusMessage here. ****/ - prvITMPrintString( pcStatusMessage ); - break; - - default : - /* Something unexpected happened. Delete this task so the - error is apparent (no output will be displayed). */ - vMainDeleteMe(); - break; - } - } + * a counter on each iteration of their loop. The counters are inside the array + * that this task has access to. */ + volatile uint32_t * pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), * pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* Demonstrate how the various memory regions can and can't be accessed. + * The task privilege level is set down to user mode within this function. */ + prvTestMemoryRegions(); + + /* Clear overlaid reg test counters before entering the loop below. */ + *pulOverlaidCounter3 = 0UL; + *pulOverlaidCounter4 = 0UL; + + /* This loop performs the main function of the task, which is blocking + * on a message queue then processing each message as it arrives. */ + for( ; ; ) + { + /* Wait for the next message to arrive. */ + xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); + + switch( lMessage ) + { + case configREG_TEST_1_STILL_EXECUTING: + case configREG_TEST_2_STILL_EXECUTING: + case configTIMER_STILL_EXECUTING: + + /* Message from the first or second register check task, or + * the timer callback function. Increment the count of the + * number of times the message source has sent the message as + * the message source must still be executed. */ + ( ulStillAliveCounts[ lMessage ] )++; + break; + + case configPRINT_SYSTEM_STATUS: + + /* Message from tick hook, time to print out the system + * status. If messages have stopped arriving from either of + * the first two reg test task or the timer callback then the + * status must be set to fail. */ + if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) ) + { + /* One or both of the test tasks are no longer sending + * 'still alive' messages. */ + pcStatusMessage = "FAIL\r\n"; + } + else + { + /* Reset the count of 'still alive' messages. */ + memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); + } + + /* Check that the register test 3 task is still incrementing + * its counter, and therefore still running. */ + if( ulLastRegTest3CountValue == *pulOverlaidCounter3 ) + { + pcStatusMessage = "FAIL\r\n"; + } + + ulLastRegTest3CountValue = *pulOverlaidCounter3; + + /* Check that the register test 4 task is still incrementing + * its counter, and therefore still running. */ + if( ulLastRegTest4Value == *pulOverlaidCounter4 ) + { + pcStatusMessage = "FAIL\r\n"; + } + + ulLastRegTest4Value = *pulOverlaidCounter4; + + /**** print pcStatusMessage here. ****/ + prvITMPrintString( pcStatusMessage ); + break; + + default: + + /* Something unexpected happened. Delete this task so the + * error is apparent (no output will be displayed). */ + vMainDeleteMe(); + break; + } + } } /*-----------------------------------------------------------*/ static void prvTestMemoryRegions( void ) { -int32_t x; -char cTemp; - - /* The check task (from which this function is called) is created in the - Privileged mode. The privileged array can be both read from and written - to while this task is privileged. */ - cPrivilegedOnlyAccessArray[ 0 ] = 'a'; - if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) - { - /* Something unexpected happened. Delete this task so the error is - apparent (no output will be displayed). */ - vMainDeleteMe(); - } - - /* Writing off the end of the RAM allocated to this task will *NOT* cause a - protection fault because the task is still executing in a privileged mode. - Uncomment the following to test. */ - /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ - - /* Now set the task into user mode. */ - portSWITCH_TO_USER_MODE(); - - /* Accessing the privileged only array will now cause a fault. Uncomment - the following line to test. */ - /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ - - /* The read/write array can still be successfully read and written. */ - for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ ) - { - cReadWriteArray[ x ] = 'a'; - if( cReadWriteArray[ x ] != 'a' ) - { - /* Something unexpected happened. Delete this task so the error is - apparent (no output will be displayed). */ - vMainDeleteMe(); - } - } - - /* But attempting to read or write off the end of the RAM allocated to this - task will cause a fault. Uncomment either of the following two lines to - test. */ - /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ - /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ - - /* The read only array can be successfully read... */ - for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ ) - { - cTemp = cReadOnlyArray[ x ]; - } - - /* ...but cannot be written. Uncomment the following line to test. */ - /* cReadOnlyArray[ 0 ] = 'a'; */ - - /* Writing to the first and last locations in the stack array should not - cause a protection fault. Note that doing this will cause the kernel to - detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than - 1, hence the test is commented out by default. */ - /* xCheckTaskStack[ 0 ] = 0; - xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */ - - /* Writing off either end of the stack array should cause a protection - fault, uncomment either of the following two lines to test. */ - /* xCheckTaskStack[ -1 ] = 0; */ - /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ - - ( void ) cTemp; + int32_t x; + char cTemp; + + /* The check task (from which this function is called) is created in the + * Privileged mode. The privileged array can be both read from and written + * to while this task is privileged. */ + cPrivilegedOnlyAccessArray[ 0 ] = 'a'; + + if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + * apparent (no output will be displayed). */ + vMainDeleteMe(); + } + + /* Writing off the end of the RAM allocated to this task will *NOT* cause a + * protection fault because the task is still executing in a privileged mode. + * Uncomment the following to test. */ + /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ + + /* Now set the task into user mode. */ + portSWITCH_TO_USER_MODE(); + + /* Accessing the privileged only array will now cause a fault. Uncomment + * the following line to test. */ + /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ + + /* The read/write array can still be successfully read and written. */ + for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ ) + { + cReadWriteArray[ x ] = 'a'; + + if( cReadWriteArray[ x ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + * apparent (no output will be displayed). */ + vMainDeleteMe(); + } + } + + /* But attempting to read or write off the end of the RAM allocated to this + * task will cause a fault. Uncomment either of the following two lines to + * test. */ + /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ + /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ + + /* The read only array can be successfully read... */ + for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ ) + { + cTemp = cReadOnlyArray[ x ]; + } + + /* ...but cannot be written. Uncomment the following line to test. */ + /* cReadOnlyArray[ 0 ] = 'a'; */ + + /* Writing to the first and last locations in the stack array should not + * cause a protection fault. Note that doing this will cause the kernel to + * detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than + * 1, hence the test is commented out by default. */ + + /* xCheckTaskStack[ 0 ] = 0; + * xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */ + + /* Writing off either end of the stack array should cause a protection + * fault, uncomment either of the following two lines to test. */ + /* xCheckTaskStack[ -1 ] = 0; */ + /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ + + ( void ) cTemp; } /*-----------------------------------------------------------*/ static void prvExerciseEventGroupAPI( void ) { -EventGroupHandle_t xEventGroup; -EventBits_t xBits; -const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01; - - /* Exercise some event group functions. */ - xEventGroup = xEventGroupCreate(); - configASSERT( xEventGroup ); - - /* No bits should be set. */ - xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK ); - configASSERT( xBits == ( EventBits_t ) 0 ); - - /* Set bits and read back to ensure the bits were set. */ - xEventGroupSetBits( xEventGroup, xBitsToWaitFor ); - xBits = xEventGroupGetBits( xEventGroup ); - configASSERT( xBits == xBitsToWaitFor ); - - /* Clear a bit and read back again using a different API function. */ - xEventGroupClearBits( xEventGroup, xBitToClear ); - xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK ); - configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) ); - - /* Finished with the event group. */ - vEventGroupDelete( xEventGroup ); + EventGroupHandle_t xEventGroup; + EventBits_t xBits; + const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01; + + /* Exercise some event group functions. */ + xEventGroup = xEventGroupCreate(); + configASSERT( xEventGroup ); + + /* No bits should be set. */ + xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK ); + configASSERT( xBits == ( EventBits_t ) 0 ); + + /* Set bits and read back to ensure the bits were set. */ + xEventGroupSetBits( xEventGroup, xBitsToWaitFor ); + xBits = xEventGroupGetBits( xEventGroup ); + configASSERT( xBits == xBitsToWaitFor ); + + /* Clear a bit and read back again using a different API function. */ + xEventGroupClearBits( xEventGroup, xBitToClear ); + xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK ); + configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) ); + + /* Finished with the event group. */ + vEventGroupDelete( xEventGroup ); } /*-----------------------------------------------------------*/ static void prvExerciseSemaphoreAPI( void ) { -SemaphoreHandle_t xSemaphore; -const UBaseType_t uxMaxCount = 5, uxInitialCount = 0; - - /* Most of the semaphore API is common to the queue API and is already being - used. This function uses a few semaphore functions that are unique to the - RTOS objects, rather than generic and used by queues also. - - First create and use a counting semaphore. */ - xSemaphore = xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ); - configASSERT( xSemaphore ); - - /* Give the semaphore a couple of times and ensure the count is returned - correctly. */ - xSemaphoreGive( xSemaphore ); - xSemaphoreGive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 ); - vSemaphoreDelete( xSemaphore ); - - /* Create a recursive mutex, and ensure the mutex holder and count are - returned returned correctly. */ - xSemaphore = xSemaphoreCreateRecursiveMutex(); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphore ); - xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); - xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) ); - xSemaphoreGiveRecursive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); - xSemaphoreGiveRecursive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); - vSemaphoreDelete( xSemaphore ); - - /* Create a normal mutex, and sure the mutex holder and count are returned - returned correctly. */ - xSemaphore = xSemaphoreCreateMutex(); - configASSERT( xSemaphore ); - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */ - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); - xSemaphoreGive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); - vSemaphoreDelete( xSemaphore ); + SemaphoreHandle_t xSemaphore; + const UBaseType_t uxMaxCount = 5, uxInitialCount = 0; + + /* Most of the semaphore API is common to the queue API and is already being + * used. This function uses a few semaphore functions that are unique to the + * RTOS objects, rather than generic and used by queues also. + * + * First create and use a counting semaphore. */ + xSemaphore = xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ); + configASSERT( xSemaphore ); + + /* Give the semaphore a couple of times and ensure the count is returned + * correctly. */ + xSemaphoreGive( xSemaphore ); + xSemaphoreGive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 ); + vSemaphoreDelete( xSemaphore ); + + /* Create a recursive mutex, and ensure the mutex holder and count are + * returned returned correctly. */ + xSemaphore = xSemaphoreCreateRecursiveMutex(); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphore ); + xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); + xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) ); + xSemaphoreGiveRecursive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); + xSemaphoreGiveRecursive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); + vSemaphoreDelete( xSemaphore ); + + /* Create a normal mutex, and sure the mutex holder and count are returned + * returned correctly. */ + xSemaphore = xSemaphoreCreateMutex(); + configASSERT( xSemaphore ); + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */ + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); + xSemaphoreGive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); + vSemaphoreDelete( xSemaphore ); } /*-----------------------------------------------------------*/ static void prvExerciseTaskNotificationAPI( void ) { -uint32_t ulNotificationValue; -BaseType_t xReturned; - - /* The task should not yet have a notification pending. */ - xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); - configASSERT( xReturned == pdFAIL ); - configASSERT( ulNotificationValue == 0UL ); - - /* Exercise the 'give' and 'take' versions of the notification API. */ - xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); - xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); - ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK ); - configASSERT( ulNotificationValue == 2 ); - - /* Exercise the 'notify' and 'clear' API. */ - ulNotificationValue = 20; - xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); - ulNotificationValue = 0; - xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); - configASSERT( xReturned == pdPASS ); - configASSERT( ulNotificationValue == 20 ); - xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); - xReturned = xTaskNotifyStateClear( NULL ); - configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */ - xReturned = xTaskNotifyStateClear( NULL ); - configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */ + uint32_t ulNotificationValue; + BaseType_t xReturned; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotificationValue == 0UL ); + + /* Exercise the 'give' and 'take' versions of the notification API. */ + xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK ); + configASSERT( ulNotificationValue == 2 ); + + /* Exercise the 'notify' and 'clear' API. */ + ulNotificationValue = 20; + xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); + ulNotificationValue = 0; + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotificationValue == 20 ); + xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */ + xReturned = xTaskNotifyStateClear( NULL ); + configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */ } /*-----------------------------------------------------------*/ -static void prvTaskToDelete( void *pvParameters ) +static void prvTaskToDelete( void * pvParameters ) { - /* Remove compiler warnings about unused parameters. */ - ( void ) pvParameters; - - /* Check the enter and exit critical macros are working correctly. If the - SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will - fault. */ - taskENTER_CRITICAL(); - taskEXIT_CRITICAL(); - - /* Exercise the API of various RTOS objects. */ - prvExerciseEventGroupAPI(); - prvExerciseSemaphoreAPI(); - prvExerciseTaskNotificationAPI(); - - /* For code coverage test purposes it is deleted by the Idle task. */ - configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 ); - vTaskSuspend( NULL ); + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Check the enter and exit critical macros are working correctly. If the + * SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will + * fault. */ + taskENTER_CRITICAL(); + taskEXIT_CRITICAL(); + + /* Exercise the API of various RTOS objects. */ + prvExerciseEventGroupAPI(); + prvExerciseSemaphoreAPI(); + prvExerciseTaskNotificationAPI(); + + /* For code coverage test purposes it is deleted by the Idle task. */ + configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 ); + vTaskSuspend( NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile const uint32_t *pul; -volatile uint32_t ulReadData; - - /* The idle task, and therefore this function, run in Supervisor mode and - can therefore access all memory. Try reading from corners of flash and - RAM to ensure a memory fault does not occur. - - Start with the edges of the privileged data area. */ - pul = __privileged_data_start__; - ulReadData = *pul; - pul = __privileged_data_end__ - 1; - ulReadData = *pul; - - /* Next the standard SRAM area. */ - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* And the standard Flash area - the start of which is marked for - privileged access only. */ - pul = __FLASH_segment_start__; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Reading off the end of Flash or SRAM space should cause a fault. - Uncomment one of the following two pairs of lines to test. */ - - /* pul = __FLASH_segment_end__ + 4; - ulReadData = *pul; */ - - /* pul = __SRAM_segment_end__ + 1; - ulReadData = *pul; */ - - /* One task is created purely so it can be deleted - done for code coverage - test purposes. */ - if( xTaskToDelete != NULL ) - { - vTaskDelete( xTaskToDelete ); - xTaskToDelete = NULL; - } - - ( void ) ulReadData; + volatile const uint32_t * pul; + volatile uint32_t ulReadData; + + /* The idle task, and therefore this function, run in Supervisor mode and + * can therefore access all memory. Try reading from corners of flash and + * RAM to ensure a memory fault does not occur. + * + * Start with the edges of the privileged data area. */ + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Next the standard SRAM area. */ + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* And the standard Flash area - the start of which is marked for + * privileged access only. */ + pul = __FLASH_segment_start__; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading off the end of Flash or SRAM space should cause a fault. + * Uncomment one of the following two pairs of lines to test. */ + + /* pul = __FLASH_segment_end__ + 4; + * ulReadData = *pul; */ + + /* pul = __SRAM_segment_end__ + 1; + * ulReadData = *pul; */ + + /* One task is created purely so it can be deleted - done for code coverage + * test purposes. */ + if( xTaskToDelete != NULL ) + { + vTaskDelete( xTaskToDelete ); + xTaskToDelete = NULL; + } + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ -static void prvOldStyleUserModeTask( void *pvParameters ) +static void prvOldStyleUserModeTask( void * pvParameters ) { -const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000; -volatile const uint32_t *pul; -volatile uint32_t ulReadData; + const volatile uint32_t * pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000; + volatile const uint32_t * pul; + volatile uint32_t ulReadData; /* The following lines are commented out to prevent the unused variable -compiler warnings when the tests that use the variable are also commented out. */ + * compiler warnings when the tests that use the variable are also commented out. */ /* extern uint32_t __privileged_functions_start__[]; */ /* const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; */ - ( void ) pvParameters; - - /* This task is created in User mode using the original xTaskCreate() API - function. It should have access to all Flash and RAM except that marked - as Privileged access only. Reading from the start and end of the non- - privileged RAM should not cause a problem (the privileged RAM is the first - block at the bottom of the RAM memory). */ - pul = __privileged_data_end__ + 1; - ulReadData = *pul; - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* Likewise reading from the start and end of the non-privileged Flash - should not be a problem (the privileged Flash is the first block at the - bottom of the Flash memory). */ - pul = __privileged_functions_end__ + 1; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Standard peripherals are accessible. */ - ulReadData = *pulStandardPeripheralRegister; - - /* System peripherals are not accessible. Uncomment the following line - to test. Also uncomment the declaration of pulSystemPeripheralRegister - at the top of this function. - ulReadData = *pulSystemPeripheralRegister; */ - - /* Reading from anywhere inside the privileged Flash or RAM should cause a - fault. This can be tested by uncommenting any of the following pairs of - lines. Also uncomment the declaration of __privileged_functions_start__ - at the top of this function. */ - - /* pul = __privileged_functions_start__; - ulReadData = *pul; */ - - /*pul = __privileged_functions_end__ - 1; - ulReadData = *pul;*/ - - /*pul = __privileged_data_start__; - ulReadData = *pul;*/ - - /*pul = __privileged_data_end__ - 1; - ulReadData = *pul;*/ - - /* Must not just run off the end of a task function, so delete this task. - Note that because this task was created using xTaskCreate() the stack was - allocated dynamically and I have not included any code to free it again. */ - vTaskDelete( NULL ); - - ( void ) ulReadData; + ( void ) pvParameters; + + /* This task is created in User mode using the original xTaskCreate() API + * function. It should have access to all Flash and RAM except that marked + * as Privileged access only. Reading from the start and end of the non- + * privileged RAM should not cause a problem (the privileged RAM is the first + * block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + * should not be a problem (the privileged Flash is the first block at the + * bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Standard peripherals are accessible. */ + ulReadData = *pulStandardPeripheralRegister; + + /* System peripherals are not accessible. Uncomment the following line + * to test. Also uncomment the declaration of pulSystemPeripheralRegister + * at the top of this function. + * ulReadData = *pulSystemPeripheralRegister; */ + + /* Reading from anywhere inside the privileged Flash or RAM should cause a + * fault. This can be tested by uncommenting any of the following pairs of + * lines. Also uncomment the declaration of __privileged_functions_start__ + * at the top of this function. */ + + /* pul = __privileged_functions_start__; + * ulReadData = *pul; */ + + /*pul = __privileged_functions_end__ - 1; + * ulReadData = *pul;*/ + + /*pul = __privileged_data_start__; + * ulReadData = *pul;*/ + + /*pul = __privileged_data_end__ - 1; + * ulReadData = *pul;*/ + + /* Must not just run off the end of a task function, so delete this task. + * Note that because this task was created using xTaskCreate() the stack was + * allocated dynamically and I have not included any code to free it again. */ + vTaskDelete( NULL ); + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ -static void prvOldStylePrivilegedModeTask( void *pvParameters ) +static void prvOldStylePrivilegedModeTask( void * pvParameters ) { -volatile const uint32_t *pul; -volatile uint32_t ulReadData; -const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */ + volatile const uint32_t * pul; + volatile uint32_t ulReadData; + const volatile uint32_t * pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */ + /*const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;*/ - ( void ) pvParameters; - - /* This task is created in Privileged mode using the original xTaskCreate() - API function. It should have access to all Flash and RAM including that - marked as Privileged access only. So reading from the start and end of the - non-privileged RAM should not cause a problem (the privileged RAM is the - first block at the bottom of the RAM memory). */ - pul = __privileged_data_end__ + 1; - ulReadData = *pul; - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* Likewise reading from the start and end of the non-privileged Flash - should not be a problem (the privileged Flash is the first block at the - bottom of the Flash memory). */ - pul = __privileged_functions_end__ + 1; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Reading from anywhere inside the privileged Flash or RAM should also - not be a problem. */ - pul = __privileged_functions_start__; - ulReadData = *pul; - pul = __privileged_functions_end__ - 1; - ulReadData = *pul; - pul = __privileged_data_start__; - ulReadData = *pul; - pul = __privileged_data_end__ - 1; - ulReadData = *pul; - - /* Finally, accessing both System and normal peripherals should both be - possible. */ - ulReadData = *pulSystemPeripheralRegister; - /*ulReadData = *pulStandardPeripheralRegister;*/ - - /* Must not just run off the end of a task function, so delete this task. - Note that because this task was created using xTaskCreate() the stack was - allocated dynamically and I have not included any code to free it again. */ - vTaskDelete( NULL ); - - ( void ) ulReadData; + ( void ) pvParameters; + + /* This task is created in Privileged mode using the original xTaskCreate() + * API function. It should have access to all Flash and RAM including that + * marked as Privileged access only. So reading from the start and end of the + * non-privileged RAM should not cause a problem (the privileged RAM is the + * first block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + * should not be a problem (the privileged Flash is the first block at the + * bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading from anywhere inside the privileged Flash or RAM should also + * not be a problem. */ + pul = __privileged_functions_start__; + ulReadData = *pul; + pul = __privileged_functions_end__ - 1; + ulReadData = *pul; + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Finally, accessing both System and normal peripherals should both be + * possible. */ + ulReadData = *pulSystemPeripheralRegister; + /*ulReadData = *pulStandardPeripheralRegister;*/ + + /* Must not just run off the end of a task function, so delete this task. + * Note that because this task was created using xTaskCreate() the stack was + * allocated dynamically and I have not included any code to free it again. */ + vTaskDelete( NULL ); + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ void vMainDeleteMe( void ) { - vTaskDelete( NULL ); + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber ) +void vMainSendImAlive( QueueHandle_t xHandle, + uint32_t ulTaskNumber ) { - if( xHandle != NULL ) - { - xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); - } + if( xHandle != NULL ) + { + xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - extern void SystemInit( void ); - extern uint32_t __Vectors[]; - - /* Assuming downloading code via the debugger - so ensure the hardware - is using the vector table downloaded with the application. */ - mainVTOR = ( uint32_t ) __Vectors; - - #if ( ( configASSERT_DEFINED == 1 ) && ( defined ( __GNUC__ ) ) ) - { - /* Sanity check linker configuration sizes sections adequately. */ - const uint32_t ulPrivilegedFunctionsActualEnd = ( uint32_t ) __privileged_functions_actual_end__; - const uint32_t ulPrivilegedDataActualEnd = ( uint32_t ) __privileged_data_actual_end__; - const uint32_t ulPrivilegedFunctionsEnd = ( uint32_t ) __privileged_functions_end__; - const uint32_t ulPrivilegedDataEnd = ( uint32_t ) __privileged_data_end__; - - configASSERT( ulPrivilegedFunctionsActualEnd < ulPrivilegedFunctionsEnd ); - configASSERT( ulPrivilegedDataActualEnd < ulPrivilegedDataEnd ); - - /* Clear the privileged data to 0 as the C start up code is only set to - clear the non-privileged bss. */ - memset( ( void * ) __privileged_data_start__, 0x00, ( size_t ) __privileged_data_actual_end__ - ( size_t ) __privileged_data_start__ ); - } - #endif - - SystemInit(); - SystemCoreClockUpdate(); + extern void SystemInit( void ); + extern uint32_t __Vectors[]; + + /* Assuming downloading code via the debugger - so ensure the hardware + * is using the vector table downloaded with the application. */ + mainVTOR = ( uint32_t ) __Vectors; + + #if ( ( configASSERT_DEFINED == 1 ) && ( defined( __GNUC__ ) ) ) + { + /* Sanity check linker configuration sizes sections adequately. */ + const uint32_t ulPrivilegedFunctionsActualEnd = ( uint32_t ) __privileged_functions_actual_end__; + const uint32_t ulPrivilegedDataActualEnd = ( uint32_t ) __privileged_data_actual_end__; + const uint32_t ulPrivilegedFunctionsEnd = ( uint32_t ) __privileged_functions_end__; + const uint32_t ulPrivilegedDataEnd = ( uint32_t ) __privileged_data_end__; + + configASSERT( ulPrivilegedFunctionsActualEnd < ulPrivilegedFunctionsEnd ); + configASSERT( ulPrivilegedDataActualEnd < ulPrivilegedDataEnd ); + + /* Clear the privileged data to 0 as the C start up code is only set to + * clear the non-privileged bss. */ + memset( ( void * ) __privileged_data_start__, 0x00, ( size_t ) __privileged_data_actual_end__ - ( size_t ) __privileged_data_start__ ); + } + #endif /* if ( ( configASSERT_DEFINED == 1 ) && ( defined( __GNUC__ ) ) ) */ + + SystemInit(); + SystemCoreClockUpdate(); } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { -static uint32_t ulCallCount = 0; -const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 5000 ); -const uint32_t ulMessage = configPRINT_SYSTEM_STATUS; -portBASE_TYPE xDummy; - - /* If configUSE_TICK_HOOK is set to 1 then this function will get called - from each RTOS tick. It is called from the tick interrupt and therefore - will be executing in the privileged state. */ - - ulCallCount++; - - /* Is it time to print out the pass/fail message again? */ - if( ulCallCount >= ulCallsBetweenSends ) - { - ulCallCount = 0; - - /* Send a message to the check task to command it to check that all - the tasks are still running then print out the status. - - This is running in an ISR so has to use the "FromISR" version of - xQueueSend(). Because it is in an ISR it is running with privileges - so can access xGlobalScopeCheckQueue directly. */ - xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy ); - } + static uint32_t ulCallCount = 0; + const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 5000 ); + const uint32_t ulMessage = configPRINT_SYSTEM_STATUS; + portBASE_TYPE xDummy; + + /* If configUSE_TICK_HOOK is set to 1 then this function will get called + * from each RTOS tick. It is called from the tick interrupt and therefore + * will be executing in the privileged state. */ + + ulCallCount++; + + /* Is it time to print out the pass/fail message again? */ + if( ulCallCount >= ulCallsBetweenSends ) + { + ulCallCount = 0; + + /* Send a message to the check task to command it to check that all + * the tasks are still running then print out the status. + * + * This is running in an ISR so has to use the "FromISR" version of + * xQueueSend(). Because it is in an ISR it is running with privileges + * so can access xGlobalScopeCheckQueue directly. */ + xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy ); + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this - function will automatically get called if a task overflows its stack. */ - ( void ) pxTask; - ( void ) pcTaskName; - for( ;; ); + /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this + * function will automatically get called if a task overflows its stack. */ + ( void ) pxTask; + ( void ) pcTaskName; + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will - be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() - is called automatically when a task, queue or semaphore is created. */ - for( ;; ); + /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will + * be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() + * is called automatically when a task, queue or semaphore is created. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvTimerCallback( TimerHandle_t xExpiredTimer ) { -uint32_t ulCount; + uint32_t ulCount; - /* The count of the number of times this timer has expired is saved in the - timer's ID. Obtain the current count. */ - ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer ); + /* The count of the number of times this timer has expired is saved in the + * timer's ID. Obtain the current count. */ + ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer ); - /* Increment the count, and save it back into the timer's ID. */ - ulCount++; - vTimerSetTimerID( xTimer, ( void * ) ulCount ); + /* Increment the count, and save it back into the timer's ID. */ + ulCount++; + vTimerSetTimerID( xTimer, ( void * ) ulCount ); - /* Let the check task know the timer is still running. */ - vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING ); + /* Let the check task know the timer is still running. */ + vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING ); } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ -static void prvITMPrintString( const char *pcString ) +static void prvITMPrintString( const char * pcString ) { - while( *pcString != 0x00 ) - { - ITM_SendChar( *pcString ); - pcString++; - } + while( *pcString != 0x00 ) + { + ITM_SendChar( *pcString ); + pcString++; + } } /*-----------------------------------------------------------*/ -static void prvRegTest3Task( void *pvParameters ) +static void prvRegTest3Task( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == configREG_TEST_TASK_3_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest3Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == configREG_TEST_TASK_3_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest3Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -static void prvRegTest4Task( void *pvParameters ) +static void prvRegTest4Task( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == configREG_TEST_TASK_4_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest4Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == configREG_TEST_TASK_4_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest4Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/.gitignore new file mode 100644 index 00000000000..f8b83b3665e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/.gitignore @@ -0,0 +1,2 @@ +.settings/ +Debug/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h index d1ee25674e1..dff13d8cafa 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -151,6 +151,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c index d902d965200..ee8fda1c92b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c index d348648da27..d7f651f20e1 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h index 753dedbb213..279d995fc41 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project index 02eb533de16..89de2a82962 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project @@ -53,6 +53,15 @@ + + 1701346271384 + FreeRTOS + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-examples + + 1578832143838 FreeRTOS/portable diff --git a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c index 08089fed022..4c5226fa9e7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h index f2f40a118ad..834e53623fb 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -149,6 +149,9 @@ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd index c798137190a..767974745dc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd @@ -1,6 +1,6 @@ - 3 + 4 Release @@ -11,7 +11,7 @@ C-SPY 2 - 32 + 33 1 0 + + + + + + + + @@ -457,6 +489,39 @@ + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + GDBSERVER_ID 2 @@ -494,6 +559,27 @@ + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + IJET_ID 2 @@ -1187,7 +1273,7 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1517,6 +1607,10 @@ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp index 1ab1a07079f..9fd8141b7ce 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp @@ -1,6 +1,6 @@ - 3 + 4 Release @@ -11,7 +11,7 @@ General 3 - 35 + 36 1 0 + ICCARM 2 - 37 + 38 1 0 + + AARM 2 - 11 + 12 1 0 + @@ -676,18 +694,10 @@ - 112 + 1 inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1083,6 +1093,11 @@ + + BUILDACTION + 2 + + Config @@ -1155,6 +1170,9 @@ $PROJ_DIR$\..\..\..\..\..\Source\portable\Common\mpu_wrappers_v2.c + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\mpu_wrappers_v2_asm.S + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\port.c @@ -1164,9 +1182,6 @@ $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\portasm.s - - $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\mpu_wrappers_v2_asm.S - $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\portmacro.h diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c index 900ed89e6b7..b3847c03998 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewd b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewd index 8491b4e1a66..fd039f09c90 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewd @@ -1,6 +1,6 @@ - 3 + 4 Release @@ -11,7 +11,7 @@ C-SPY 2 - 32 + 33 1 0 + + + + + + + + @@ -457,6 +489,39 @@ + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + GDBSERVER_ID 2 @@ -494,6 +559,27 @@ + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + IJET_ID 2 @@ -1187,7 +1273,7 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1517,6 +1607,10 @@ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewp b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewp index 9815b540dbf..f46fb9f82d7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/FreeRTOSDemo_s.ewp @@ -1,6 +1,6 @@ - 3 + 4 Release @@ -11,7 +11,7 @@ General 3 - 35 + 36 1 0 + ICCARM 2 - 37 + 38 1 0 + + AARM 2 - 11 + 12 1 0 + @@ -674,14 +691,6 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1077,6 +1086,11 @@ + + BUILDACTION + 2 + + Device diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c index 48653a444c3..915a6a9ea2d 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h index 8a7bfadba54..760257b9869 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -144,6 +144,9 @@ extern uint32_t SystemCoreClock; /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/FreeRTOSDemo_ns.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/FreeRTOSDemo_ns.uvprojx index d69d374bd0e..33fd8fc21e4 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/FreeRTOSDemo_ns.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/FreeRTOSDemo_ns.uvprojx @@ -10,13 +10,13 @@ FreeRTOSDemo_ns 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 M2351KIAAEES Nuvoton - Nuvoton.NuMicro_DFP.1.3.20 + Nuvoton.NuMicro_DFP.1.3.19 https://github.com/OpenNuvoton/cmsis-packs/raw/master/Nuvoton_DFP/ IRAM(0x20000000,0x18000) IROM(0x00000000,0x00080000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c index c702e95cdd6..d97be0a85aa 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/FreeRTOSDemo_s.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/FreeRTOSDemo_s.uvprojx index 1935b660d02..bb961ae6ed8 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/FreeRTOSDemo_s.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/FreeRTOSDemo_s.uvprojx @@ -10,13 +10,13 @@ FreeRTOSDemo_s 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 M2351KIAAEES Nuvoton - Nuvoton.NuMicro_DFP.1.3.20 + Nuvoton.NuMicro_DFP.1.3.19 https://github.com/OpenNuvoton/cmsis-packs/raw/master/Nuvoton_DFP/ IRAM(0x20000000,0x18000) IROM(0x00000000,0x00080000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c index d247ecc1656..0cc1558b923 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/Config/FreeRTOSConfig.h index 63d7a9da45c..bb7f1aea6bf 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -149,6 +149,9 @@ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewd index 722af9eacca..9a8ba4f1c67 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewd @@ -1,6 +1,6 @@ - 3 + 4 Release @@ -11,7 +11,7 @@ C-SPY 2 - 32 + 33 1 0 + + + + + + + + @@ -457,6 +489,39 @@ + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + GDBSERVER_ID 2 @@ -494,6 +559,27 @@ + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + IJET_ID 2 @@ -1072,7 +1158,7 @@ STLINK_ID 2 - 7 + 8 1 0 + + @@ -1417,7 +1511,7 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1509,6 +1607,10 @@ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewp index e4cbc069364..8971b309d44 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/FreeRTOSDemo.ewp @@ -1,6 +1,6 @@ - 3 + 4 Release @@ -11,7 +11,7 @@ General 3 - 35 + 36 1 0 + ICCARM 2 - 37 + 38 1 0 + + AARM 2 - 11 + 12 1 0 + @@ -677,14 +695,6 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1080,6 +1090,11 @@ + + BUILDACTION + 2 + + Config diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/main.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/main.c index 09311b03620..40f222a240c 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/Config/FreeRTOSConfig.h index 4bf648148f1..3fd5988585a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -144,6 +144,9 @@ extern uint32_t SystemCoreClock; /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/FreeRTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/FreeRTOSDemo.uvprojx index b9c71c1e3be..50796b109a2 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/FreeRTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/FreeRTOSDemo.uvprojx @@ -10,13 +10,13 @@ FreeRTOSDemo 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 M2351KIAAEES Nuvoton - Nuvoton.NuMicro_DFP.1.3.20 + Nuvoton.NuMicro_DFP.1.3.19 https://github.com/OpenNuvoton/cmsis-packs/raw/master/Nuvoton_DFP/ IRAM(0x20000000,0x18000) IROM(0x00000000,0x00080000) CPUTYPE("ARMV8MBL") TZ CLOCK(12000000) ESEL ELITTLE diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/main.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/main.c index 471ef6c4849..3ac6bc4ee62 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects_NTZ/Keil/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.c index 7ae69babd16..0c13f3daf25 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.h index 0837aad72d6..544ea775c29 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/RegTests/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h index 391a6294978..e6c4f8508db 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -160,6 +160,9 @@ extern uint32_t SystemCoreClock; /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/FreeRTOSDemo.emProject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/FreeRTOSDemo.emProject index 0dc66229e56..83d87746b39 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/FreeRTOSDemo.emProject +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/FreeRTOSDemo.emProject @@ -55,10 +55,10 @@ - + @@ -106,7 +106,8 @@ + default_const_section=".init_rodata" + gcc_strict_prototypes_warning="No" /> @@ -115,10 +116,10 @@ - + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/main.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/main.c index 98646f1cf23..6b4da7f1678 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.c index be47547c0eb..2358727e051 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.h index 0837aad72d6..544ea775c29 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NTZ_Nordic_NRF9160_SES/Source/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c index d3d04719f6a..8076816f8bd 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h index 1362b455699..faf9bfefdba 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h index b02100760c4..a64ab443316 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -155,6 +155,9 @@ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd index 5f232029043..db6a62b68a4 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd @@ -1,12342 +1,1648 @@ - + - - 3 - - - - debug - - - - ARM - - - - 1 - - - - C-SPY - - 2 - - - - 32 - - 1 - + 4 + + debug + + ARM + 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - - 2 - - - - 1 - - 1 - - 1 - - - - - - - - - - - - - - - - CADI_ID - - 2 - - - - 0 - - 1 - - 1 - - - - - - - - - - - - - - - - - - CMSISDAP_ID - - 2 - - - - 4 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - - 2 - - - - 0 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - IJET_ID - - 2 - - - - 9 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - - 2 - - - - 16 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - - 2 - - - - 3 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - NULINK_ID - - 2 - - - - 0 - - 1 - - 1 - - - - - - - - - - - - - - PEMICRO_ID - - 2 - - - - 3 - - 1 - - 1 - - - - - - - - - - - - - - - - STLINK_ID - - 2 - - - - 7 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - - 2 - - - - 0 - - 1 - - 1 - - - - - - - - - - - - - - - - TIFET_ID - - 2 - - - - 1 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XDS100_ID - - 2 - - - - 9 - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - - 0 - - - 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- - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - - 0 - - - - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - - 0 - - - - - - $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin - - 0 - - - - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - - 0 - - - - - - - + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp index 6b69d229ad5..60c9bed9171 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp @@ -1,6 +1,6 @@ - 3 + 4 debug @@ -11,7 +11,7 @@ General 3 - 35 + 36 1 1 + ICCARM 2 - 37 + 38 1 1 + + AARM 2 - 11 + 12 1 1 + @@ -685,14 +703,6 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1088,6 +1098,11 @@ + + BUILDACTION + 2 + + Config @@ -1198,6 +1213,9 @@ ARM_CM33 non_secure + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\non_secure\mpu_wrappers_v2_asm.S + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\non_secure\port.c @@ -1207,9 +1225,6 @@ $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\non_secure\portasm.s - - $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\non_secure\mpu_wrappers_v2_asm.S - $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\non_secure\portmacro.h diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd index b23ea7ac4de..3bcd6076c78 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd @@ -1,6 +1,6 @@ - 3 + 4 debug @@ -11,7 +11,7 @@ C-SPY 2 - 32 + 33 1 1 + + + + + + + + @@ -457,6 +489,39 @@ + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + GDBSERVER_ID 2 @@ -494,6 +559,27 @@ + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + IJET_ID 2 @@ -1187,7 +1273,7 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1517,6 +1607,10 @@ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp index 0ab1d327202..246a6d0c7cc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp @@ -1,6 +1,6 @@ - 3 + 4 debug @@ -11,7 +11,7 @@ General 3 - 35 + 36 1 1 + ICCARM 2 - 37 + 38 1 1 + + AARM 2 - 11 + 12 1 1 + @@ -678,14 +695,6 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1081,6 +1090,11 @@ + + BUILDACTION + 2 + + Config diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h index a1e21d29220..da9ade7d698 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -154,6 +154,9 @@ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project index 8588fa7ec09..b7d2db19e9a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project @@ -117,6 +117,15 @@ 1.0-name-matches-false-false-*.h + + 1701338096747 + FreeRTOS + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-examples + + 1682451751797 NXP_Code diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c index 0a6d1b9abfd..edb03e029b7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h index c2084aef4e1..e9fbbbc8056 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -156,6 +156,9 @@ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd index b23ea7ac4de..3bcd6076c78 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd @@ -1,6 +1,6 @@ - 3 + 4 debug @@ -11,7 +11,7 @@ C-SPY 2 - 32 + 33 1 1 + + + + + + + + @@ -457,6 +489,39 @@ + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + GDBSERVER_ID 2 @@ -494,6 +559,27 @@ + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + IJET_ID 2 @@ -1187,7 +1273,7 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1517,6 +1607,10 @@ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp index 26d89806245..7691e7a940b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp @@ -1,6 +1,6 @@ - 3 + 4 debug @@ -11,7 +11,7 @@ General 3 - 35 + 36 1 1 + ICCARM 2 - 37 + 38 1 1 + + AARM 2 - 11 + 12 1 1 + @@ -681,14 +699,6 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1084,6 +1094,11 @@ + + BUILDACTION + 2 + + Config @@ -1135,6 +1150,9 @@ IAR ARM_CM33_NTZ + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\mpu_wrappers_v2_asm.S + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\port.c @@ -1144,9 +1162,6 @@ $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\portasm.s - - $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\mpu_wrappers_v2_asm.S - $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM33_NTZ\non_secure\portmacro.h diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.project b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.project index b459a5645a9..ab88855641a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.project @@ -95,7 +95,7 @@ - 1682480839426 + 1701338446087 FreeRTOS 5 @@ -103,6 +103,15 @@ 1.0-name-matches-false-false-*.c + + 1701338446104 + FreeRTOS + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-examples + + 1682481066220 NXP_Code diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/Config/FreeRTOSConfig.h index 674d898cdee..b7d7bfb0d31 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -154,6 +154,9 @@ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c index 0a6d1b9abfd..edb03e029b7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c index 1492dfea973..445cf30e065 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h index 0837aad72d6..544ea775c29 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c index 340418c0061..35c07707f11 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c index 532355c9728..d35a51aee2b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c index 636b5b9f9e1..de77d0b2b92 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h index 150e68a53d4..a3206f36d7d 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -157,6 +157,9 @@ extern uint32_t SystemCoreClock; /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/FreeRTOSDemo.emProject b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/FreeRTOSDemo.emProject index 23049f3a318..1182795a7bc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/FreeRTOSDemo.emProject +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/FreeRTOSDemo.emProject @@ -58,10 +58,10 @@ - + @@ -82,9 +82,9 @@ + - @@ -107,7 +107,8 @@ + default_const_section=".init_rodata" + gcc_strict_prototypes_warning="No" /> @@ -116,10 +117,10 @@ - + @@ -189,12 +190,6 @@ - - - - - - @@ -202,7 +197,8 @@ + default_const_section=".init_rodata" + gcc_strict_prototypes_warning="No" /> @@ -211,13 +207,19 @@ - + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/main_ns.c index 3d0ac1c2ec7..d08cc46a12a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/main_ns.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/main_ns.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.c index 2c9fc5ca9ef..fd05824d4b7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.h index 0837aad72d6..544ea775c29 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/NonSecure/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Secure/main_s.c index bce4d1ca84f..9f54c99a988 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Secure/main_s.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Nordic_NRF9160_SES/Secure/main_s.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Config/FreeRTOSConfig.h index a35154ab17a..ae63ef96fa6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -154,6 +154,9 @@ extern uint32_t SystemCoreClock; /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx index 8423d394e8c..8861361eea7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx @@ -10,7 +10,7 @@ FVP Simulation Model 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/main_ns.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/main_ns.c index f9fbc3d52db..442720633a6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/main_ns.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/main_ns.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.c index ce607bccdfa..22ebb5cf433 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.h index be1426b178b..0a8d7401528 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx index 1ee4aba4b5e..d83c5c1ab43 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx @@ -10,7 +10,7 @@ FVP Simulation Model 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/main_s.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/main_s.c index 0f48bd584d3..badcacacf2e 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/main_s.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/main_s.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h index 9b6bfae766c..e83bb33c70b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -44,6 +44,10 @@ extern void vAssertCalled( void ); #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() #define configQUEUE_REGISTRY_SIZE 20 +#ifdef PICOLIBC_TLS +#define configUSE_PICOLIBC_TLS 1 +#endif + #define configUSE_PREEMPTION 1 #define configUSE_TIME_SLICING 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -68,7 +72,6 @@ extern void vAssertCalled( void ); #define configUSE_COUNTING_SEMAPHORES 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1 #define configSUPPORT_STATIC_ALLOCATION 1 -#define configNUM_TX_DESCRIPTORS 15 #define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 2 #define configCHECK_FOR_STACK_OVERFLOW 2 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0 @@ -116,6 +119,9 @@ unsigned long ulGetRunTimeCounterValue( void ); /* Prototype of function that re /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ @@ -127,9 +133,4 @@ unsigned long ulGetRunTimeCounterValue( void ); /* Prototype of function that re extern void vLoggingPrintf( const char * pcFormatString, ... ); -#ifdef HEAP3 - #define xPortGetMinimumEverFreeHeapSize ( x ) - #define xPortGetFreeHeapSize ( x ) -#endif - #endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile index e577429d071..82c018698d2 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile @@ -1,4 +1,5 @@ CC = arm-none-eabi-gcc +SIZE = arm-none-eabi-size BIN := RTOSDemo.axf BUILD_DIR := build @@ -34,33 +35,28 @@ INCLUDE_DIRS += -I$(FREERTOS_DIR)/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/C INCLUDE_DIRS += -I$(KERNEL_DIR)/include INCLUDE_DIRS += -I$(KERNEL_DIR)/portable/GCC/ARM_CM3_MPU -DEFINES := -DQEMU_SOC_MPS2 DEFINES := -DHEAP4 - CPPFLAGS += $(DEFINES) -CFLAGS += -mcpu=cortex-m3 -CFLAGS += -Wno-error=implicit-function-declaration -CFLAGS += -Wno-builtin-declaration-mismatch -CFLAGS += -Werror -CFLAGS += -Wall -CFLAGS += -Wextra -CFLAGS += -fstrict-aliasing -CFLAGS += -Wstrict-aliasing -CFLAGS += -Wno-error=address-of-packed-member -CFLAGS += -Wno-unused-parameter +CFLAGS += -mthumb -mcpu=cortex-m3 +CFLAGS += -Wall -Wextra -Wshadow -Wno-unused-parameter +#CFLAGS += -Wpedantic -fanalyzer CFLAGS += $(INCLUDE_DIRS) LDFLAGS = -T ./scripts/mps2_m3.ld -LDFLAGS += -mthumb - LDFLAGS += -Xlinker -Map=${BUILD_DIR}/output.map +LDFLAGS += -Xlinker --gc-sections LDFLAGS += -nostartfiles -nostdlib -nolibc -nodefaultlibs ifeq ($(DEBUG), 1) - CFLAGS += -ggdb3 -Og -save-temps=obj + CFLAGS += -g3 -Og -ffunction-sections -fdata-sections -save-temps=obj else - CFLAGS += -O3 + CFLAGS += -Os -ffunction-sections -fdata-sections +endif + +ifeq ($(PICOLIBC), 1) + CFLAGS += --specs=picolibc.specs -DPICOLIBC_INTEGER_PRINTF_SCANF + LDFLAGS += --specs=picolibc.specs -DPICOLIBC_INTEGER_PRINTF_SCANF endif OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) @@ -68,7 +64,8 @@ OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) .PHONY: clean $(BUILD_DIR)/$(BIN) : $(OBJ_FILES) - $(CC) -ffunction-sections -fdata-sections $(LDFLAGS) $+ -o $(@) + $(CC) $(CFLAGS) $(LDFLAGS) $+ -o $(@) + $(SIZE) $(@) %.d: %.c @set -e; rm -f $@; \ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.c index c4c2ac9a790..3f4b856a6eb 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -70,8 +70,8 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, void vApplicationMallocFailedHook( void ) { /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will - * be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() - * is called automatically when a task, queue or semaphore is created. */ + * be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() + * is called automatically when a task, queue or semaphore is created. */ printf( "Application Malloc Failed Hook called\n" ); for( ; ; ) diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.h b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.h index 0cf3a6ff713..676db4e07cc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/app_main.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c index 5deb2bfad9e..b5b1a45cd08 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -34,8 +34,10 @@ extern void vPortSVCHandler( void ); extern void xPortPendSVHandler( void ); extern void xPortSysTickHandler( void ); -extern void uart_init(); -extern int main(); +extern void uart_init( void ); +extern int main( void ); + +void _start( void ); extern uint32_t _estack, _sidata, _sdata, _edata, _sbss, _ebss; @@ -61,13 +63,12 @@ void Reset_Handler( void ) } /* jump to board initialisation */ - void _start( void ); _start(); } void prvGetRegistersFromStack( uint32_t * pulFaultStackAddress ) { -/* These are volatile to try and prevent the compiler/linker optimising them +/* These are volatile to try and prevent the compiler/linker optimizing them * away as the variables never actually get used. If the debugger won't show the * values of the variables, make them global my moving their declaration outside * of this function. */ @@ -111,17 +112,17 @@ void Default_Handler( void ) { __asm volatile ( - "Default_Handler: \n" - " ldr r3, NVIC_INT_CTRL_CONST \n" + "Default_Handler:\n" + " ldr r3, =0xe000ed04\n" " ldr r2, [r3, #0]\n" " uxtb r2, r2\n" "Infinite_Loop:\n" " b Infinite_Loop\n" ".size Default_Handler, .-Default_Handler\n" - ".align 4\n" - "NVIC_INT_CTRL_CONST: .word 0xe000ed04\n" + ".ltorg\n" ); } + static void HardFault_Handler( void ) __attribute__( ( naked ) ); void HardFault_Handler( void ) { @@ -132,9 +133,9 @@ void HardFault_Handler( void ) " mrseq r0, msp \n" " mrsne r0, psp \n" " ldr r1, [r0, #24] \n" - " ldr r2, handler2_address_const \n" + " ldr r2, =prvGetRegistersFromStack \n" " bx r2 \n" - " handler2_address_const: .word prvGetRegistersFromStack \n" + " .ltorg \n" ); } @@ -147,9 +148,9 @@ void MemMang_Handler( void ) " ite eq \n" " mrseq r0, msp \n" " mrsne r0, psp \n" - " ldr r1, handler3_address_const \n" + " ldr r1, =vHandleMemoryFault \n" " bx r1 \n" - " handler3_address_const: .word vHandleMemoryFault \n" + " .ltorg \n" ); } @@ -161,9 +162,9 @@ void BusFault_Handler( void ) " ite eq \n" " mrseq r0, msp \n" " mrsne r0, psp \n" - " ldr r1, handler4_address_const \n" + " ldr r1, =vHandleMemoryFault \n" " bx r1 \n" - " handler4_address_const: .word vHandleMemoryFault \n" + " .ltorg \n" ); } @@ -175,9 +176,9 @@ void UsageFault_Handler( void ) " ite eq \n" " mrseq r0, msp \n" " mrsne r0, psp \n" - " ldr r1, handler5_address_const \n" + " ldr r1, =vHandleMemoryFault \n" " bx r1 \n" - " handler5_address_const: .word vHandleMemoryFault \n" + " .ltorg \n" ); } @@ -189,9 +190,9 @@ void Debug_Handler( void ) " ite eq \n" " mrseq r0, msp \n" " mrsne r0, psp \n" - " ldr r1, handler6_address_const \n" + " ldr r1, =vHandleMemoryFault \n" " bx r1 \n" - " handler6_address_const: .word vHandleMemoryFault \n" + " .ltorg \n" ); } @@ -232,12 +233,12 @@ const uint32_t * const isr_vector[] __attribute__( ( section( ".isr_vector" ) ) void _start( void ) { uart_init(); - main( 0, 0 ); + main(); exit( 0 ); } __attribute__( ( naked ) ) -void exit( __attribute__( ( unused ) ) int status ) +void exit( int status ) { /* Force qemu to exit using ARM Semihosting */ __asm volatile ( @@ -249,5 +250,8 @@ void exit( __attribute__( ( unused ) ) int status ) "movs r0, #0x18\n" /* SYS_EXIT */ "bkpt 0xab\n" "end: b end\n" + ".ltorg\n" ); + + ( void ) status; } diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c index 32165199a07..6481ac42969 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,7 +37,7 @@ void vApplicationIdleHook( void ); void vApplicationTickHook( void ); -int main() +int main( void ) { app_main(); return 0; diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.c index 35c1d829e7a..1d8b4127a19 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.h index b85104c2cd5..5aca0b4974d 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/mpu_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/scripts/mps2_m3.ld b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/scripts/mps2_m3.ld index cd9665fdbe9..6d92fd34c04 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/scripts/mps2_m3.ld +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/scripts/mps2_m3.ld @@ -175,6 +175,26 @@ SECTIONS _edata = .; } > RAM AT > FLASH + .tdata : { + *(.tdata .tdata.*) + } >FLASH + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tbss_end = . ); + PROVIDE( __tls_end = . ); + } >FLASH + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - ADDR(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); . = ALIGN(4); .bss : @@ -195,8 +215,10 @@ SECTIONS PROVIDE ( end = . ); PROVIDE ( _end = . ); _heap_bottom = .; + __heap_start = .; . = . + _Min_Heap_Size; _heap_top = .; + __heap_end = .; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c index 09e49c21b79..d8fc48cb9d6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -45,29 +45,54 @@ typedef struct UART_t #define UART_CTRL_TX_EN ( 1 << 0 ) #define UART_CTRL_RX_EN ( 1 << 1 ) - -extern unsigned long _heap_bottom; -extern unsigned long _heap_top; -extern unsigned long g_ulBase; - -static void * heap_end = 0; - /** * @brief initializes the UART emulated hardware */ -void uart_init() +void uart_init(void) { UART0_ADDR->BAUDDIV = 16; UART0_ADDR->CTRL = UART_CTRL_TX_EN; } +#ifdef __PICOLIBC__ + +#include + +/** + * @brief Write byte to the UART channel to be displayed on the command line + * with qemu + * @param [in] c byte to send + * @param [in] file ignored + * @returns the character written (cast to unsigned so it is not an error value) + */ + +int +_uart_putc(char c, FILE *file) +{ + ( void ) file; + UART_DR( UART0_ADDR ) = c; + return (unsigned char) c; +} + +static FILE __stdio = FDEV_SETUP_STREAM(_uart_putc, NULL, NULL, _FDEV_SETUP_WRITE); + +FILE *const stdout = &__stdio; + +#else + +extern unsigned long _heap_bottom; +extern unsigned long _heap_top; + +static char * heap_end = ( char * ) &_heap_bottom; + /** * @brief not used anywhere in the code * @todo implement if necessary * */ -int _fstat( __attribute__( ( unused ) ) int file ) +int _fstat( int file ) { + ( void ) file; return 0; } @@ -76,10 +101,13 @@ int _fstat( __attribute__( ( unused ) ) int file ) * @todo implement if necessary * */ -int _read( __attribute__( ( unused ) ) int file, - __attribute__( ( unused ) ) char * buf, - __attribute__( ( unused ) ) int len ) +int _read( int file, + char * buf, + int len ) { + ( void ) file; + ( void ) buf; + ( void ) len; return -1; } @@ -91,12 +119,14 @@ int _read( __attribute__( ( unused ) ) int file, * @param [in] len length of the buffer * @returns the number of bytes written */ -int _write( __attribute__( ( unused ) ) int file, - __attribute__( ( unused ) ) char * buf, +int _write( int file, + char * buf, int len ) { int todo; + ( void ) file; + for( todo = 0; todo < len; todo++ ) { UART_DR( UART0_ADDR ) = *buf++; @@ -113,16 +143,9 @@ int _write( __attribute__( ( unused ) ) int file, */ void * _sbrk( int incr ) { - char * prev_heap_end; + void * prev_heap_end = heap_end; - if( heap_end == 0 ) - { - heap_end = ( void * ) &_heap_bottom; - } - - prev_heap_end = heap_end; - - if( ( heap_end + incr ) > ( void * ) &_heap_top ) + if( ( heap_end + incr ) > ( char * ) &_heap_top ) { return ( void * ) -1; } @@ -131,6 +154,7 @@ void * _sbrk( int incr ) return prev_heap_end; } + void _close( int fd ) { ( void ) fd; @@ -176,11 +200,13 @@ void _kill( pid_t pid, ( void ) sig; } -int _getpid() +int _getpid( void ) { return 1; } +#endif + #ifdef __cplusplus } #endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/.gitignore new file mode 100644 index 00000000000..f8b83b3665e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/.gitignore @@ -0,0 +1,2 @@ +.settings/ +Debug/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Config/FreeRTOSConfig.h index 234b7967391..cec7aa548a2 100755 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -159,6 +159,9 @@ header file. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.c index 5591ca24ff1..ad1cb6cf43e 100755 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.h b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.h index 0cf3a6ff713..676db4e07cc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/app_main.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.c index d348648da27..d7f651f20e1 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.h index 753dedbb213..279d995fc41 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/mpu_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.c index 01a2fdd150f..e7bcff5f7f1 100755 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.h index 0837aad72d6..544ea775c29 100755 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests_asm.c b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests_asm.c index 60fd1ed9f09..e96fc4077b3 100755 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests_asm.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Demo/reg_tests_asm.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.project index 730a7efc247..e554f4084f5 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.project @@ -53,6 +53,15 @@ + + 1701333116189 + FreeRTOS + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-examples + + 1579730437023 FreeRTOS/portable diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000000..99f26c0203a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/memfault_handler.c index 08089fed022..4c5226fa9e7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/sysmem.c b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/sysmem.c index e5e1bc2d948..b89d75ed854 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/sysmem.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_NUCLEO_L152RE_GCC/Projects/GCC/Startup/sysmem.c @@ -60,7 +60,7 @@ register char * stack_ptr asm("sp"); _sbrk Increase program data space. Malloc and related functions depend on this **/ -caddr_t _sbrk(int incr) +char * _sbrk(int incr) { extern char end asm("end"); static char *heap_end; @@ -73,11 +73,11 @@ caddr_t _sbrk(int incr) if (heap_end + incr > stack_ptr) { errno = ENOMEM; - return (caddr_t) -1; + return (char *) -1; } heap_end += incr; - return (caddr_t) prev_heap_end; + return prev_heap_end; } diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h index 755cd86cd0b..bb06a9ec3f3 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -145,6 +145,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c index 3c02e6921f7..504793443c3 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c index 761b1ba237b..b95bd5f4d1f 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.h index ec3f68f3427..24cdd99b367 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.c index a8d1b874271..d1398cb6a7d 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.h index 98d489c8aa1..8130d3b9af7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/mpu_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c index d4efebfb675..550cc6df2f3 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h index 0837aad72d6..544ea775c29 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project index 23501c2b083..2e0f2b82729 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project @@ -63,7 +63,7 @@ - 1594591511105 + 1701327345246 FreeRTOS 5 @@ -71,6 +71,15 @@ 1.0-name-matches-false-false-*.c + + 1701327345257 + FreeRTOS + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-examples + + 1594591566433 FreeRTOS/portable diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c index 17001f89d76..cf41af8bb6e 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c index e5e1bc2d948..b89d75ed854 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c @@ -60,7 +60,7 @@ register char * stack_ptr asm("sp"); _sbrk Increase program data space. Malloc and related functions depend on this **/ -caddr_t _sbrk(int incr) +char * _sbrk(int incr) { extern char end asm("end"); static char *heap_end; @@ -73,11 +73,11 @@ caddr_t _sbrk(int incr) if (heap_end + incr > stack_ptr) { errno = ENOMEM; - return (caddr_t) -1; + return (char *) -1; } heap_end += incr; - return (caddr_t) prev_heap_end; + return prev_heap_end; } diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd index e380c1f250a..55de9793f20 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd @@ -1,6 +1,6 @@ - 3 + 4 FreeRTOSDemo @@ -11,7 +11,7 @@ C-SPY 2 - 32 + 33 1 1 + + + + + + + + @@ -457,6 +489,39 @@ + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + GDBSERVER_ID 2 @@ -494,6 +559,27 @@ + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + IJET_ID 2 @@ -1072,7 +1158,7 @@ STLINK_ID 2 - 7 + 8 1 1 + + @@ -1473,6 +1567,10 @@ + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin 0 @@ -1509,6 +1607,10 @@ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin 0 + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp index 48c4ae4b28d..512ab5111b9 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp @@ -1,6 +1,6 @@ - 3 + 4 FreeRTOSDemo @@ -11,7 +11,7 @@ General 3 - 34 + 36 1 1 + + + ICCARM 2 - 37 + 38 1 1 + + AARM 2 - 11 + 12 1 1 + @@ -669,19 +695,11 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 - 26 + 27 1 1 + + @@ -1064,6 +1090,11 @@ + + BUILDACTION + 2 + + Config diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx index ff5b9bda5d6..f9a46a78530 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx @@ -10,14 +10,14 @@ FreeRTOSDemo 0x4 ARM-ADS - 6180000::V6.18::ARMCLANG + 6210000::V6.21::ARMCLANG 1 STM32H743ZITx STMicroelectronics - Keil.STM32H7xx_DFP.3.0.0 - http://www.keil.com/pack/ + Keil.STM32H7xx_DFP.3.1.0 + https://www.keil.com/pack/ IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/memfault_handler.c index 84ceb512ae2..843c3906bc3 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx index db512b13015..85adaa8a1dc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx @@ -16,8 +16,8 @@ STM32H743ZITx STMicroelectronics - Keil.STM32H7xx_DFP.3.0.0 - http://www.keil.com/pack/ + Keil.STM32H7xx_DFP.3.1.0 + https://www.keil.com/pack/ IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE @@ -478,6 +478,57 @@ mpu_wrappers_v2.c 1 ..\..\..\..\Source\portable\Common\mpu_wrappers_v2.c + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --diag_suppress=1296 + + + + + + + port.c @@ -1136,4 +1187,13 @@ + + + + FreeRTOSDemo + 1 + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c index 6c14c6ff08c..28ba72b319a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.ccsproject b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.ccsproject new file mode 100644 index 00000000000..7fdda62015b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.ccsproject @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.clang-format b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.clang-format new file mode 100644 index 00000000000..c745d9c66fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.clang-format @@ -0,0 +1,104 @@ +--- +Language: Cpp +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: None +AlignConsecutiveBitFields: AcrossEmptyLinesAndComments +AlignConsecutiveDeclarations: None +AlignConsecutiveMacros: AcrossEmptyLinesAndComments +AlignEscapedNewlines: Left +AlignOperands: AlignAfterOperator +AlignTrailingComments: true +AllowAllArgumentsOnNextLine: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: Never +AllowShortCaseLabelsOnASingleLine: false +AllowShortEnumsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: false +AllowShortLambdasOnASingleLine: All +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: Yes +BinPackArguments: false +BinPackParameters: false +BitFieldColonSpacing: Both +BraceWrapping: + AfterCaseLabel: true + AfterClass: true + AfterControlStatement: Always + AfterEnum: true + AfterExternBlock: false + AfterFunction: true + AfterNamespace: true + AfterStruct: true + AfterUnion: true + BeforeCatch: true + BeforeElse: true + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBinaryOperators: NonAssignment +BreakBeforeBraces: Custom +BreakBeforeConceptDeclarations: true +BreakBeforeTernaryOperators: true +BreakConstructorInitializers: BeforeColon +BreakInheritanceList: BeforeColon +BreakStringLiterals: true +ColumnLimit: 90 +CompactNamespaces: false +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +EmptyLineBeforeAccessModifier: Always +FixNamespaceComments: true +IncludeBlocks: Preserve +IndentCaseBlocks: false +IndentCaseLabels: true +IndentExternBlock: NoIndent +IndentGotoLabels: true +IndentPPDirectives: BeforeHash +IndentWidth: 4 +IndentWrappedFunctionNames: true +KeepEmptyLinesAtTheStartOfBlocks: false +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +PenaltyBreakAssignment: 1000 +PenaltyBreakBeforeFirstCallParameter: 200 +PenaltyBreakComment: 50 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 100 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 100 +PenaltyIndentedWhitespace: 0 +PenaltyReturnTypeOnItsOwnLine: 10000 +PointerAlignment: Middle +ReflowComments: true +SortIncludes: false +SortUsingDeclarations: true +SpaceAfterCStyleCast: true +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: false +SpaceBeforeCpp11BracedList: true +SpaceBeforeCtorInitializerColon: false +SpaceBeforeInheritanceColon: false +SpaceBeforeParens: Never +SpaceBeforeRangeBasedForLoopColon: false +SpaceBeforeSquareBrackets: false +SpaceInEmptyBlock: false +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInConditionalStatement: true +SpacesInContainerLiterals: true +SpacesInCStyleCastParentheses: true +SpacesInParentheses: true +SpacesInSquareBrackets: true +TabWidth: 4 +UseCRLF: false +UseTab: Never +... + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.cproject b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.cproject new file mode 100644 index 00000000000..f498a34b3c5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.cproject @@ -0,0 +1,177 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.gitignore new file mode 100644 index 00000000000..ba04ae8d56e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.gitignore @@ -0,0 +1,4 @@ +[Bb]uild +[Dd]ebug +.settings/ +.launches/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.project new file mode 100644 index 00000000000..4d25d42f972 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.project @@ -0,0 +1,126 @@ + + + RM46_Demo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + FreeRTOS-Kernel + 2 + FREERTOS_KERNEL_DIR + + + + + 1703728340587 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-CMakeLists.txt + + + + 1703728340594 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-build + + + + 1703284178173 + FreeRTOS-Kernel + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.c + + + + 1703284178175 + FreeRTOS-Kernel + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-examples + + + + 1703728468486 + FreeRTOS-Kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Common + + + + 1703728468488 + FreeRTOS-Kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1703267897500 + FreeRTOS-Kernel/portable/Common + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-mpu_wrappers.c + + + + 1703728489501 + FreeRTOS-Kernel/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CRx_MPU + + + + + + BOARD_FILES_DIR + $%7BPROJECT_LOC%7D/BoardFiles + + + FREERTOS_KERNEL_DIR + $%7BPARENT-2-PROJECT_LOC%7D/Source + + + FREERTOS_PORT_DIR + $%7BPARENT-2-PROJECT_LOC%7D/Source/portable/GCC/ARM_CRx_MPU + + + REPOSITORY_ROOT + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.vscode/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC.code-workspace b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.vscode/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC.code-workspace new file mode 100644 index 00000000000..87f157a2203 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.vscode/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC.code-workspace @@ -0,0 +1,50 @@ +{ + "folders": [ + { + "path": ".." + }, + { + "path": "../../../Source", + "name": "FreeRTOS-Kernel" + }, + { + "path": "../../../Source/portable/GCC/ARM_CRx_MPU", + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_MPU", + "../../Source/include", + "../../Source", + ], + } + ], + "settings": { + "files.associations": { + "*.h": "c", + "variant": "c" + }, + + "files.exclude": { + "**/.launches/**": true, + "**/.settings/**": true, + "**/.ccsproject/**": true, + "**/examples**": true, + "**/.github**": true, + "**/.git[a-hj-z-]**": true, + "**/portable/**": true + + }, + + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_MPU", + "../../Source/include", + "../../Source", + ], + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.vscode/settings.json b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.vscode/settings.json new file mode 100644 index 00000000000..3bbc53ac26a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/.vscode/settings.json @@ -0,0 +1,8 @@ +{ + "files.associations": { + ".cSpellWords.txt": "magic", + "freertos.h": "c", + "portable.h": "c", + "portmacro.h": "c" + } +} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/HalCoGen-RM46L852.dil b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/HalCoGen-RM46L852.dil new file mode 100644 index 00000000000..64223ae581f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/HalCoGen-RM46L852.dil @@ -0,0 +1,10393 @@ +# RM46L852ZWT 02/06/22 16:30:00 +# +ARCH=RM46L852ZWT +# +DRIVER.TOOLS.VAR.GCC.VALUE=1 +DRIVER.TOOLS.VAR.ARM.VALUE=0 +DRIVER.TOOLS.VAR.IAR.VALUE=0 +DRIVER.TOOLS.VAR.GHS.VALUE=0 +DRIVER.TOOLS.VAR.TI.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_0.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=spi4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2 +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_1.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MEMINIT_SELECTED.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=220.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xfcffffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=ecap5Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=256_KB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=220.000 +DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=220.00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=dmaBTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_CCM_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE_AVAIL.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=2 +DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63ffffff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=etpwm5TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18 +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATEVALUE.VALUE=0x5 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_isrStub +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003fffff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=110.0 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08000500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=etpwm1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0xFF000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_STACK.VALUE=5 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATE.VALUE=1 +DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=vPortPreemptiveTick +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=ecap6Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x00030000 +DRIVER.SYSTEM.VAR.CORE_MPU_TOTAL_REGION.VALUE=12 +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=64_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_VALUE_NEW.VALUE=0x00300020 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=dmaFTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203fffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt +DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.USB_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCI_ALL_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=24 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=220.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x1000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48 +DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=6 +DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001 +DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=etpwm1TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATEVALUE.VALUE=0xA +DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0x08400000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_CPUSELFTEST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x19 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=dmaLFSAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_SP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x17 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08000600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_EFUSE_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=OSC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=165.0 +DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=linLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xf07fffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=eqep1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=etpwm7Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=1 +DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt +DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATEVALUE.VALUE=0x5 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843ffff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_SP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM_OLDCODE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x11 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08001000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=STRONGLYORDERED_SHAREABLE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=13.750 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=etpwm2TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=VCLKA4_DIVR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=110.000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=27.500 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=16_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0xFC000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=165 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt +DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=16_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_FIRST.VALUE=6 +DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=eqep2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002F800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x080017ff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=165 +DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=0.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=etpwm3Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PMM_AUTO_CLK_WAKE_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00008020 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00180000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x08 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATEVALUE.VALUE=0x5 +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5 +DRIVER.SYSTEM.VAR.VIM_PARITY_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE +DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=128 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=512_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECAP_OLDCODE.VALUE=1 +DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt +DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATEVALUE.VALUE=0x5 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=2_KB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=OSC +DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=ecap1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68 +DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_NA_USER_NA_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.DMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x1100 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00140000 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=etpwm3TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=EMACRxIntISR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=55.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ESRAM_SELECTED.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=110.000 +DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xfe0001ff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=spi4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt +DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=4_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE_AVAIL.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESERVED_ENTRY.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE_AVAIL.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=ecap2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87ffffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_GB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x17 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=vPortYieldWithinAPI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=linHighLevelInterrupt +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATEVALUE.VALUE=0xA +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08000700 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.PMM_PMCTRL_PWRDN.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=etpwm4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803ffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0xFE000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL_VAL.VALUE=A400 +DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=dmaHBCAInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13 +DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=6 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=ecap3nterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RW_USER_NA_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=4_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ROM_PBIST_SELFCHECK_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=spi2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt +DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=vPortSWI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_FLASHECC_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=etpwm4TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3 +DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_RTP_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=110.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_ROM_PBIST_SELFCHECK_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_M3.VALUE=0 +DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x00137FE0 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sciHighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATEVALUE.VALUE=0x5 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08000400 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=ecap4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=1 +DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=256_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE_NEW.VALUE=0xA +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=1 +DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=A400 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=220.00 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x1F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_SP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=etpwm5Interrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2 +DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_FMCBUS2_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.AJSM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_RAMPARITYCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_DP_PBISTCHECK_ENA.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_MAPPING.VALUE=111 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_MAPPING.VALUE=103 +DRIVER.SYSTEM.VAR.VIM_PHANTOM_NAME.VALUE=phantomInterrupt +DRIVER.OS.VAR.OS_USERECERSIVEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_USETIMERS.VALUE=0 +DRIVER.OS.VAR.OS_USECNTSEMAPHORE.VALUE=0 +DRIVER.OS.VAR.OS_GENERATERUNTIMESTATS.VALUE=0 +DRIVER.OS.VAR.OS_USEMPU.VALUE=0 +DRIVER.OS.VAR.OS_TOTALHEAPSIZE.VALUE=8192 +DRIVER.OS.VAR.OS_USEVERBOSESTACK.VALUE=2 +DRIVER.OS.VAR.OS_TIMERPRIORITY.VALUE=0 +DRIVER.OS.VAR.OS_SVCENABLE.VALUE=0 +DRIVER.OS.VAR.OS_MAXTASKNAMELEN.VALUE=16 +DRIVER.OS.VAR.OS_MAXPRIORITIES.VALUE=5 +DRIVER.OS.VAR.OS_TIMERTASKSTACKDEPTH.VALUE=0 +DRIVER.OS.VAR.OS_COROUTINEPRIORITIES.VALUE=2 +DRIVER.OS.VAR.OS_USECOROUTINES.VALUE=0 +DRIVER.OS.VAR.OS_USEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_CPUCLOCKHZ.VALUE=110000000 +DRIVER.OS.VAR.OS_USEMALLOCFAILEDHOOK.VALUE=0 +DRIVER.OS.VAR.OS_MINSTACKSIZE.VALUE=128 +DRIVER.OS.VAR.OS_SYSTEM_MODE.VALUE=0x1F +DRIVER.OS.VAR.OS_USEPREEMPTION.VALUE=1 +DRIVER.OS.VAR.OS_IDLESHOULDYIELD.VALUE=1 +DRIVER.OS.VAR.OS_USEIDLEHOOK.VALUE=0 +DRIVER.OS.VAR.OS_TICKRATEHZ.VALUE=1000 +DRIVER.OS.VAR.OS_TIMERPQUEUELENGTH.VALUE=0 +DRIVER.OS.VAR.OS_USETRACE.VALUE=0 +DRIVER.OS.VAR.OS_USESTACK.VALUE=0 +DRIVER.OS.VAR.OS_USETICKHOOK.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=148.945 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL31_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL23_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL15_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL60_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL52_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL44_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL36_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL28_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=110 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_INT_LEVEL.VALUE=0 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+DRIVER.SCI.VAR.SCILIN_BASE.VALUE=0xFFF7E400 +DRIVER.SCI.VAR.SCI_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCILIN_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=715 +DRIVER.SCI.VAR.SCILIN_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCILIN_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCILIN_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCILIN_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCILIN_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.SCI.VAR.SCILIN_BAUDRATE.VALUE=115200 +DRIVER.SCI.VAR.SCILIN_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCILIN_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCILIN_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCILIN_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCILIN_ACTUALBAUDRATE.VALUE=9602 +DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI_BASE.VALUE=0xFFF7E500 +DRIVER.SCI.VAR.SCILIN_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400 +DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=11 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=72.727 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00 +DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=11 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_TQ.VALUE=181.818 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_TQ.VALUE=181.818 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_TQ.VALUE=181.818 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=72.727 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_BRP.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRP.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_BRP.VALUE=19 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=3 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SJW.VALUE=3 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SJW.VALUE=3 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SJW.VALUE=3 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=72.727 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000 +DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000 +DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=10 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=10 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.LIN.VAR.LIN_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=4954 +DRIVER.LIN.VAR.LIN_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=19.985 +DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN_BAUDRATE.VALUE=20.000 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+DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0 +DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C_STPCND.VALUE=1 +DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=13 +DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER +DRIVER.I2C.VAR.I2C_PORT_BIT0_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C_ALINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C_RXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C_BASE.VALUE=0xFFF7D400 +DRIVER.I2C.VAR.I2C_ARDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT1_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C_TXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C_MSMODE.VALUE=1 +DRIVER.I2C.VAR.I2C_ICCH.VALUE=34 +DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0 +DRIVER.I2C.VAR.I2C_ICCL.VALUE=34 +DRIVER.I2C.VAR.I2C_AAS.VALUE=0 +DRIVER.I2C.VAR.I2C_BCM.VALUE=0 +DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C_ARDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C_PARITYENA.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT0_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C_LENGTH.VALUE=8 +DRIVER.I2C.VAR.I2C_NACKINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT1_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C_ICRRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C_STACND.VALUE=1 +DRIVER.I2C.VAR.I2C_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_NACKINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C_EVENPARITY.VALUE=0 +DRIVER.I2C.VAR.I2C_BAUDRATE.VALUE=100 +DRIVER.I2C.VAR.I2C_MODCLK.VALUE=8 +DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10 +DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00 +DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40 +DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0 +DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792 +DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00 +DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=220.00 +DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400 +DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0xA +DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1 +DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0 +DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=544500 +DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_2.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_2.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_13.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_3.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_3.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_10.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_4.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_4.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_5.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_5.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_12.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_6.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_6.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_13.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_7.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_7.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_8.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_10.VALUE=1 +DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_9.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_11.VALUE=1 +DRIVER.PINMUX.VAR.DMA_FIDXD_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_13.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_14.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_10.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_15.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_11.VALUE=1 +DRIVER.PINMUX.VAR.DMA_CHPR_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_16.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_12.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_13.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1 +DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_15.VALUE=1 +DRIVER.PINMUX.VAR.DMA_ENABLEINT_1.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_16.VALUE=1 +DRIVER.PINMUX.VAR.DMA_ENABLEINT_2.VALUE=1 +DRIVER.PINMUX.VAR.DMA_ENABLEINT_3.VALUE=1 +DRIVER.PINMUX.VAR.DMA_PRITY_10.VALUE=FIXED +DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1 +DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N17_EMIF_nCS_0" +DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED +DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_P1_HET1_24" +DRIVER.PINMUX.VAR.DMA_PRITY_12.VALUE=FIXED +DRIVER.PINMUX.VAR.PINMUX20.VALUE=PINMUX_BALL_F3_MIBSPI1NCS_1 +DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA" +DRIVER.PINMUX.VAR.DMA_PRITY_13.VALUE=FIXED +DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1" +DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0" +DRIVER.PINMUX.VAR.DMA_PRITY_14.VALUE=FIXED +DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6" +DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1" +DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_15.VALUE=FIXED +DRIVER.PINMUX.VAR.PINMUX23.VALUE=PINMUX_BALL_C6_EMIF_ADDR_8 +DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED +DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_BALL_B12_HET1_04 | PINMUX_BALL_V8_MIBSPI3SOMI | PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V9_MIBSPI3CLK" +DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_B4_HET1_12" +DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_BALL_A4_HET1_16 | PINMUX_BALL_J1_HET1_18 | PINMUX_BALL_P2_HET1_20" +DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_M2_GIOB_0" +DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.PINMUX35.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_BALL_E19_MIBSPI5NCS_0 +DRIVER.PINMUX.VAR.PINMUX19.VALUE=PINMUX_BALL_B11_HET1_30 +DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX29.VALUE=PINMUX_BALL_D3_SPI2NENA +DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_10.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_11.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_PRITY_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_20.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_12.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_21.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_13.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_30.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_22.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_14.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_FIDXS_0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_0.VALUE=ENABLED +DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_109_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_31.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_23.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_15.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_TTYPE_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXS_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_1.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ENABLEREG_1.VALUE=1 +DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_24.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_16.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_FIDXS_2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_2.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ENABLEREG_2.VALUE=1 +DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_25.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_17.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_FIDXS_3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_3.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ENABLEREG_3.VALUE=1 +DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_26.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_18.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_FIDXS_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_4.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ENABLEREG_4.VALUE=1 +DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_27.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_19.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXS_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_5.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ADDMR_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_28.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_FIDXS_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_6.VALUE=ENABLED +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_29.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED +DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED +DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXS_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_9.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_10.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_10.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_11.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTASS_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_20.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_12.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_12.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_21.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_13.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_13.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_30.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_22.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_14.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_14.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_31.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_23.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_15.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_PRITY_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ACC_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_STADD_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_24.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_17.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_STADD_3.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_26.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_18.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_STADD_4.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_27.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_19.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_28.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_28.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_29.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_29.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_0.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_2.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_0.VALUE=CONSTANT +DRIVER.PINMUX.VAR.ETPWM_TBCLK_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.DMA_TTYPE_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_1.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_2.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_3.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_4.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_5.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_ADDMR_6.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_ADDMR_7.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_ADDMR_8.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_ADDMR_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_9.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5.VALUE=8BIT +DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_ADDMW_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_DEBUGMODE.VALUE=IGNORE_SUSPEND +DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_0.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ERRACT.VALUE=IGNORE +DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_1.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CHPR_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_2.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_BASE_PORT.VALUE=0xFFFFF040 +DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT +DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_4.VALUE=CONSTANT +DRIVER.PINMUX.VAR.MUX5_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_5.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_1.VALUE=1 +DRIVER.PINMUX.VAR.MUX5_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_6.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTFTCEN_2.VALUE=1 +DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTFTCEN_3.VALUE=1 +DRIVER.PINMUX.VAR.MUX51_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_8.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTEN_10.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_4.VALUE=1 +DRIVER.PINMUX.VAR.MUX51_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX41_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_9.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTEN_11.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_5.VALUE=1 +DRIVER.PINMUX.VAR.MUX51_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_12.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_6.VALUE=1 +DRIVER.PINMUX.VAR.MUX51_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1 +DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_14.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_8.VALUE=1 +DRIVER.PINMUX.VAR.ALT_ADC_SELECT.VALUE=1 +DRIVER.PINMUX.VAR.MUX98_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_92_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_84_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_76_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_68_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_1_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_15.VALUE=1 +DRIVER.PINMUX.VAR.DMA_PRITY_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_9.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTEN_16.VALUE=1 +DRIVER.PINMUX.VAR.MUX20_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX20_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX20_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_61_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX20_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX20_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX10_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ENDADD_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ENDADD_2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ENDADD_3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ENDADD_4.VALUE=0 +DRIVER.PINMUX.VAR.ETHERNET_SELECT.VALUE=RMII +DRIVER.PINMUX.VAR.MUX91_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTASS_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTASS_1.VALUE=TO_VIM +DRIVER.PINMUX.VAR.DMA_INTASS_2.VALUE=TO_VIM +DRIVER.PINMUX.VAR.ETPWM5_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.CONCOUNT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTASS_3.VALUE=TO_VIM +DRIVER.PINMUX.VAR.DMA_INTASS_4.VALUE=TO_VIM +DRIVER.PINMUX.VAR.DMA_ADDMR_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHAS_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ACC_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHAS_2.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_3.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_10.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_10.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_CHAS_4.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_11.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ADDMW_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_INTMP_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHAS_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX96_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_20.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_12.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_12.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_CHAS_6.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_21.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_13.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_13.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_CHAS_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_30.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_22.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_14.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_CHAS_8.VALUE=0 +DRIVER.PINMUX.VAR.GIOB_DISABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PIN_MUX_105_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_31.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXS_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_23.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ADDMW_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXS_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_15.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_ADDMR_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_TRIG_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHAS_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_24.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_16.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX81_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_25.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_17.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX81_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_26.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_18.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_0.VALUE=0 +DRIVER.PINMUX.VAR.MUX81_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXS_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_27.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_FIDXS_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_19.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ENABLE1.VALUE=1 +DRIVER.PINMUX.VAR.MUX81_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_28.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_2.VALUE=0 +DRIVER.PINMUX.VAR.MUX81_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXS_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_29.VALUE=ENABLED +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_3.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BYP_10.VALUE=1 +DRIVER.PINMUX.VAR.ECAP.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_BYP_11.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_1.VALUE=1 +DRIVER.PINMUX.VAR.MUX4_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BYP_12.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_2.VALUE=1 +DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1 +DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BYP_14.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_4.VALUE=1 +DRIVER.PINMUX.VAR.MUX50_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_IFT_COUNT_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BYP_15.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_5.VALUE=1 +DRIVER.PINMUX.VAR.DMA_PRITY_1.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX50_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BYP_16.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_6.VALUE=1 +DRIVER.PINMUX.VAR.DMA_PRITY_2.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX50_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_7.VALUE=1 +DRIVER.PINMUX.VAR.DMA_PRITY_3.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX50_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_8.VALUE=1 +DRIVER.PINMUX.VAR.DMA_PRITY_4.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX103_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_90_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_82_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_74_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_66_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_58_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTBTCEN_9.VALUE=1 +DRIVER.PINMUX.VAR.DMA_TRIG_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_5.VALUE=FIXED +DRIVER.PINMUX.VAR.DMA_PRITY_6.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX11_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_PRITY_7.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX11_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED +DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX11_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TBCLK_SYNC_ENABLE.VALUE=0 +DRIVER.PINMUX.VAR.AD1.VALUE=0 +DRIVER.PINMUX.VAR.MUX11_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.AD2.VALUE=0 +DRIVER.PINMUX.VAR.MUX94_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX86_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX78_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_20_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_12_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX9_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX104_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_PRITY_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.ALT_ADC.VALUE=0 +DRIVER.PINMUX.VAR.I2C.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX71_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_DEBUGMODE_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX95_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM3_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.MUX95_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_10.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_103_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_12.VALUE=0 +DRIVER.PINMUX.VAR.MUX80_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_13.VALUE=0 +DRIVER.PINMUX.VAR.HET1.VALUE=0 +DRIVER.PINMUX.VAR.MUX80_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_10.VALUE=0 +DRIVER.PINMUX.VAR.HET2.VALUE=0 +DRIVER.PINMUX.VAR.MUX80_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX2_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_1.VALUE=1 +DRIVER.PINMUX.VAR.MUX80_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_12.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_2.VALUE=1 +DRIVER.PINMUX.VAR.MUX80_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_13.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_3.VALUE=1 +DRIVER.PINMUX.VAR.MUX56_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_10.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTEN_4.VALUE=1 +DRIVER.PINMUX.VAR.MUX3_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXD_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXD_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_11.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_AIM_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTEN_5.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTASS_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX3_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_20.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_12.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTEN_6.VALUE=1 +DRIVER.PINMUX.VAR.EMIF.VALUE=0 +DRIVER.PINMUX.VAR.MUX41_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_21.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_13.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTEN_7.VALUE=1 +DRIVER.PINMUX.VAR.ETPWM_TZ1.VALUE=ASYNC +DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_22.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_14.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_10.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_8.VALUE=1 +DRIVER.PINMUX.VAR.ETPWM_TZ2.VALUE=ASYNC +DRIVER.PINMUX.VAR.MUX41_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX40_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_95_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_87_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_79_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_31.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_23.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_15.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMR_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTEN_9.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ACC_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.ETPWM_TZ3.VALUE=ASYNC +DRIVER.PINMUX.VAR.MUX41_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_24.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_16.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_12.VALUE=0 +DRIVER.PINMUX.VAR.MUX41_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_25.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_17.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_13.VALUE=0 +DRIVER.PINMUX.VAR.MUX41_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_26.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_18.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX97_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_80_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_72_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_64_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_56_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_48_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_27.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_19.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_ADDMW_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.GIOA.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT +DRIVER.PINMUX.VAR.GIOB.VALUE=0 +DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13.VALUE=8BIT +DRIVER.PINMUX.VAR.GIOB_DISABLE.VALUE=0 +DRIVER.PINMUX.VAR.MUX10_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX10_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_CHANNEL_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX10_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_28.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX10_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_29.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17.VALUE=8BIT +DRIVER.PINMUX.VAR.MUX10_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18.VALUE=8BIT +DRIVER.PINMUX.VAR.PIN_MUX_10_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_BYP_1.VALUE=1 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_BYP_2.VALUE=1 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_BYP_3.VALUE=1 +DRIVER.PINMUX.VAR.DMA_BYP_4.VALUE=1 +DRIVER.PINMUX.VAR.EQEP.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_BYP_5.VALUE=1 +DRIVER.PINMUX.VAR.DMA_BYP_6.VALUE=1 +DRIVER.PINMUX.VAR.DMA_BYP_7.VALUE=1 +DRIVER.PINMUX.VAR.DMA_BYP_8.VALUE=1 +DRIVER.PINMUX.VAR.MUX90_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1 +DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0 +DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0 +DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.OHCI0.VALUE=0 +DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0 +DRIVER.PINMUX.VAR.W2FC.VALUE=0 +DRIVER.PINMUX.VAR.OHCI1.VALUE=0 +DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX94_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX86_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX78_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX94_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX86_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX78_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX94_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX86_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX78_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_108_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX94_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX86_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX78_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX94_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX86_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX78_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX9_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH +DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXD_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_11.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_PRITY_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX9_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_12.VALUE=HIGH +DRIVER.PINMUX.VAR.MUX71_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX9_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXD_3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_13.VALUE=HIGH +DRIVER.PINMUX.VAR.MUX71_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX9_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_10.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_14.VALUE=HIGH +DRIVER.PINMUX.VAR.MUX71_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX51_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_11.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXD_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_15.VALUE=HIGH +DRIVER.PINMUX.VAR.MUX71_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_20.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_12.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_16.VALUE=HIGH +DRIVER.PINMUX.VAR.ETPWM1_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.MUX71_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_3.VALUE=0 +DRIVER.PINMUX.VAR.MUX63_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX55_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX47_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX39_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX2_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_30.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_22.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_14.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_EIDXD_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_23.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CHANNEL_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_15.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_CHANNEL_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXD_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_IET_COUNT_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_11.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.MUX2_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_24.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_16.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_12.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.MUX40_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX2_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_25.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_17.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_13.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.MUX40_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX2_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_26.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_18.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_14.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTFTCEN_10.VALUE=1 +DRIVER.PINMUX.VAR.MUX40_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_93_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_85_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_77_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_69_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_2_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_27.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_ADDMW_19.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_IET_COUNT_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_15.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_PRITY_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_11.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX40_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_28.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_TRIG_16.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTFTCEN_12.VALUE=1 +DRIVER.PINMUX.VAR.MUX40_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_29.VALUE=CONSTANT +DRIVER.PINMUX.VAR.DMA_INTFTCEN_13.VALUE=1 +DRIVER.PINMUX.VAR.MUX40_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_14.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_10.VALUE=1 +DRIVER.PINMUX.VAR.MUX102_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_70_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_62_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_54_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_46_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_38_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_15.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_11.VALUE=1 +DRIVER.PINMUX.VAR.DMA_CHPR_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ERRACT_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MII.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTFTCEN_16.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_12.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_13.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_14.VALUE=1 +DRIVER.PINMUX.VAR.GATE_EMIF_CLK_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_15.VALUE=1 +DRIVER.PINMUX.VAR.DMA_TRIG_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHPR_1.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_INTHBCEN_16.VALUE=1 +DRIVER.PINMUX.VAR.DMA_CHPR_2.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_CHPR_3.VALUE=HIGH +DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SYNC_ENABLE.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTMP_10.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_CHPR_4.VALUE=HIGH +DRIVER.PINMUX.VAR.MUX93_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_29_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_11.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_CHPR_5.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_TRIG_1.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.ETPWM_EPWM1SYNCI.VALUE=ASYNC +DRIVER.PINMUX.VAR.DMA_INTMP_12.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_CHPR_6.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_TRIG_2.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.ETPWM6_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.DMA_INTMP_13.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_CHPR_7.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_TRIG_3.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTMP_14.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_CHPR_8.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_TRIG_4.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_CHANNEL_28_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_6_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_15.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_CHPR_9.VALUE=HIGH +DRIVER.PINMUX.VAR.DMA_TRIG_5.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTHBCEN_1.VALUE=1 +DRIVER.PINMUX.VAR.SCI.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTMP_16.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_TRIG_6.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTHBCEN_2.VALUE=1 +DRIVER.PINMUX.VAR.DMA_TRIG_7.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTHBCEN_3.VALUE=1 +DRIVER.PINMUX.VAR.DMA_TRIG_8.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTHBCEN_4.VALUE=1 +DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_9_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_9.VALUE=HARDWARE_TRIGGER +DRIVER.PINMUX.VAR.DMA_INTHBCEN_5.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_1.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_INTHBCEN_6.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_2.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_ENABLEPAR.VALUE=1 +DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_7.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_3.VALUE=GROUP_A +DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_8.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_4.VALUE=GROUP_A +DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTHBCEN_9.VALUE=1 +DRIVER.PINMUX.VAR.DMA_CHPR_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL +DRIVER.PINMUX.VAR.ETPWM.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL +DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTMP_7.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_ACC_3.VALUE=ALL +DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTMP_8.VALUE=GROUP_A +DRIVER.PINMUX.VAR.DMA_ACC_4.VALUE=ALL +DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_0_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTMP_9.VALUE=GROUP_A +DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000 +DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_20_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_12_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TRIG_8_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_0.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXS_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_0.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMW_10_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXS_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMR_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHPR_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_PRITY_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_BASE_RAM.VALUE=0xFFF80000 +DRIVER.PINMUX.VAR.DMA_EIDXS_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_10.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_25_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_AIM_17_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TTYPE_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXS_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_5.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_1.VALUE=1 +DRIVER.PINMUX.VAR.DMA_FIDXD_6.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_12.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_2.VALUE=1 +DRIVER.PINMUX.VAR.SPI2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_7.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_13.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_3.VALUE=1 +DRIVER.PINMUX.VAR.DMA_FIDXD_8.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_4.VALUE=1 +DRIVER.PINMUX.VAR.SPI4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_24_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_16_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_9.VALUE=0 +DRIVER.PINMUX.VAR.DMA_AIM_2_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHAS_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_5.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTASS_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.RMII.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHAS_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_6.VALUE=1 +DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2" +DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1 +DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11" +DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1 +DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5" +DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_PRITY_14_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1 +DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6" +DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT +DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03" +DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT +DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05" +DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_V7_HET1_09" +DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_1_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_1.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHPR_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.ALT_ADC_A.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06" +DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_20.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15" +DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_21.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3" +DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_30.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_22.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_14.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_4.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_31.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_31_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXS_23.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_23_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXS_15.VALUE=0 +DRIVER.PINMUX.VAR.DMA_ADDMW_15_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_ADDMR_7_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_CHANNEL_5.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_4_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_TRIG_11_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_24.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_16.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_6.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT +DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_7.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_26.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_18.VALUE=0 +DRIVER.PINMUX.VAR.DMA_FIDXD_10.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_8.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_TTYPE_0.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_0.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.DMA_EIDXS_27.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_27_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_EIDXS_19.VALUE=0 +DRIVER.PINMUX.VAR.DMA_TTYPE_19_VALUE.VALUE=0x0001 +DRIVER.PINMUX.VAR.DMA_FIDXD_11.VALUE=0 +DRIVER.PINMUX.VAR.DMA_CHANNEL_9.VALUE=CHANNEL0 +DRIVER.PINMUX.VAR.DMA_TTYPE_1.VALUE=FRAME_TRANSFER +DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_1.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0 +DRIVER.CRC.VAR.CRC_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM +DRIVER.CRC.VAR.CRC_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH2_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH1_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400 +DRIVER.CRC.VAR.CRC_CH1_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.CRC_CH2_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH2_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH1_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH1_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC_CH2_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH2_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.CRC_CH1_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH2_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_RES_1.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_BASE.VALUE=0xFE000000 +DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT +DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.CRC_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT +DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC_CH1_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE +DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF +DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800 +DRIVER.EMAC.VAR.EMAC_LOOPBACK_ENA.VALUE=0 +DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900 +DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000 +DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF +DRIVER.EMAC.VAR.EMAC_TRANSMIT_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_CHANNELNUMBER.VALUE=0 +DRIVER.EMAC.VAR.EMAC_RX_PBUF_ALLOC.VALUE=10 +DRIVER.EMAC.VAR.EMAC_UNICAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_FULL_DUPLEX_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=0 +DRIVER.EMAC.VAR.EMAC_MII_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000 +DRIVER.EMAC.VAR.EMAC_BROADCAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_RECEIVE_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0 +DRIVER.EMIF.VAR.EMIF_AVAILABLE.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=145 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=145 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=73 +DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=291 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=73 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_INIT_TIME.VALUE=200 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=8000005 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=73 +DRIVER.EMIF.VAR.EMIF_CLK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001 +DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=73 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=291 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0 +DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0 +DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0 +DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1 +DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1 +DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM +DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0 +DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000 +DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200 +DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM3_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM6_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP5_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP5_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP2_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP6_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_BASE.VALUE=0xFCF79300 +DRIVER.ECAP.VAR.ECAP4_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP5_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP4_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_BASE.VALUE=0xFCF79400 +DRIVER.ECAP.VAR.ECAP2_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP6_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP3_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP3_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP3_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_BASE.VALUE=0xFCF79500 +DRIVER.ECAP.VAR.ECAP5_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP4_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_BASE.VALUE=0xFCF79600 +DRIVER.ECAP.VAR.ECAP6_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP4_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_BASE.VALUE=0xFCF79700 +DRIVER.ECAP.VAR.ECAP3_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_BASE.VALUE=0xFCF79800 +DRIVER.ECAP.VAR.ECAP6_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT4.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP2_QUPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_BASE.VALUE=0xFCF79900 +DRIVER.EQEP.VAR.EQEP1_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_BASE.VALUE=0xFCF79A00 +DRIVER.EQEP.VAR.EQEP1_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP2_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP1_PCSPW.VALUE=0x000 +DRIVER.EQEP.VAR.EQEP1_POSCMP.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP1_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP2_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP2_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP2_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCSPW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.EQEP.VAR.EQEP2_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP1_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP1_WDPRD.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP1_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSCMP.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QUPRD.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP2_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.FEE.VAR.FEE_START_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_READ_CYCLE_COUNT.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_NUMBER_OF_VIRTUAL_SECTORS.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX15_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_CRC_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_NUMBER.VALUE=12 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_BANK.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_NUMBER.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_SECTORS_EEP1.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_START.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_DRIVER_INDEX.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX9_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX13_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX2_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_NUMBER.VALUE=10 +DRIVER.FEE.VAR.FEE_NUMBER_OF_EEPS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_NUMBER.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_DEVICE_INDEX.VALUE=0 +DRIVER.FEE.VAR.FEE_PAGE_OVERHEAD.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_NUMBER.VALUE=3 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MAJOR_VERSION.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_END.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_START.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_SECTOR_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUALPAGE_SIZE.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VS3_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX7_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_END.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX11_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_WRITECOUNTER_SAVE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VS_INDEX.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_NUMBER.VALUE=15 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_PATCH_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_JOBERROR_NOTIFICATION.VALUE=JobErrorNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_NUMBER.VALUE=6 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_END.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_SIZE.VALUE=0x10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_TOTAL_BLOCKS_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_SIZE.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_END.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_MAXIMUM_BLOCKING_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_NO_OF_UNCONFIGURED_BLOCKS_TO_COPY.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_BANK_NUM.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_END.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_START.VALUE=1 +DRIVER.FEE.VAR.FEE_SECTOR_OVERHEAD.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MINOR_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VERSIONINFO_API.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DATASETS.VALUE=1 +DRIVER.FEE.VAR.MAX_BLOCK_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_WRITE_CYCLES.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_OFFSET.VALUE=16 +DRIVER.FEE.VAR.FEE_NUMBER_OF_BLOCKS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_BANK.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX14_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX3_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_NUMBER_OF_EIGHTBYTEWRITES.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_NUMBER.VALUE=11 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_NUMBER.VALUE=9 +DRIVER.FEE.VAR.FEE_END_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_HANDLING.VALUE=TI_Fee_None +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_DEVERROR_DETECT.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_START.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX8_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_MAX_NUMBER_OF_LINKS.VALUE=256 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX12_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_DATASELECT_BITS.VALUE=0 +DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=220.000 +DRIVER.FEE.VAR.FEE_TOTAL_SECTORS.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_NUMBER.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_JOBEND_NOTIFICATION.VALUE=JobEndNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_ENABLE_ECC.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_OVERHEAD.VALUE=24 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS2_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX10_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_NUMBER.VALUE=14 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_START.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_CHECK_BANK7_ACCESS.VALUE=STD_OFF +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_POLLING_MODE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_SIZE.VALUE=0 +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_1.VALUE=0xFFFFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_0.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_0.VALUE=0xED +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_1.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_1.VALUE=0xC0 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_2.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_3.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_0.VALUE=0xED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_1.VALUE=0xC0 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_1.VALUE=0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/HalCoGen-RM46L852.hcg b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/HalCoGen-RM46L852.hcg new file mode 100644 index 00000000000..34fd00c5c22 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/HalCoGen-RM46L852.hcg @@ -0,0 +1,1032 @@ + + + + RM46x + RM46L852ZWT_FREERTOS + HalCoGen-RM46L852.dil + gcc + + + 04.07.01 + + + + + + + + + + + + + + + + + + + + + + + + + hal_stdtypes.h + include\hal_stdtypes.h + + + sys_common.h + include\sys_common.h + + + reg_system.h + include\reg_system.h + + + reg_flash.h + include\reg_flash.h + + + reg_tcram.h + include\reg_tcram.h + + + reg_vim.h + include\reg_vim.h + + + reg_pbist.h + include\reg_pbist.h + + + reg_stc.h + include\reg_stc.h + + + reg_efc.h + include\reg_efc.h + + + reg_pcr.h + include\reg_pcr.h + + + reg_pmm.h + include\reg_pmm.h + + + reg_dma.h + include\reg_dma.h + + + system.h + include\system.h + + + sys_vim.h + include\sys_vim.h + + + sys_core.h + include\sys_core.h + + + sys_mpu.h + include\sys_mpu.h + + + sys_pmu.h + include\sys_pmu.h + + + sys_pcr.h + include\sys_pcr.h + + + sys_pmm.h + include\sys_pmm.h + + + sys_dma.h + include\sys_dma.h + + + sys_selftest.h + include\sys_selftest.h + + + sys_core.s + source\sys_core.s + + + sys_intvecs.s + source\sys_intvecs.s + + + sys_mpu.s + source\sys_mpu.s + + + sys_pmu.s + source\sys_pmu.s + + + dabort.s + source\dabort.s + + + sys_pcr.c + source\sys_pcr.c + + + sys_pmm.c + source\sys_pmm.c + + + sys_dma.c + source\sys_dma.c + + + system.c + source\system.c + + + sys_phantom.c + source\sys_phantom.c + + + sys_startup.c + source\sys_startup.c + + + sys_selftest.c + source\sys_selftest.c + + + sys_vim.c + source\sys_vim.c + + + sys_main.c + source\sys_main.c + + + notification.c + source\notification.c + + + sys_link.ld + source\sys_link.ld + + + HL_Test.h + + + errata_SSWF021_45.h + include\errata_SSWF021_45.h + + + errata_SSWF021_45_defs.h + include\errata_SSWF021_45_defs.h + + + errata_SSWF021_45.c + source\errata_SSWF021_45.c + + + os_projdefs.h + + + FreeRTOSConfig.h + + + os_portmacro.h + + + os_mpu_wrappers.h + + + os_portable.h + + + FreeRTOS.h + + + os_list.h + + + os_queue.h + + + os_semphr.h + + + os_croutine.h + + + os_StackMacros.h + + + os_task.h + + + os_timer.h + + + os_port.c + + + os_portasm.s + + + os_tasks.c + + + os_queue.c + + + os_list.c + + + os_croutine.c + + + os_timer.c + + + os_mpu_wrappers.c + + + os_heap.c + + + os_event_groups.c + + + os_event_groups.h + + + reg_pinmux.h + + + pinmux.h + + + pinmux.c + + + reg_gio.h + + + gio.h + + + gio.c + + + reg_sci.h + + + sci.h + + + sci.c + + + reg_lin.h + + + lin.h + + + + + reg_mibspi.h + + + mibspi.h + + + mibspi.c + + + reg_spi.h + + + spi.h + + + spi.c + + + reg_can.h + + + can.h + + + can.c + + + reg_adc.h + + + adc.h + + + adc.c + + + + + + + + + std_nhet.h + + + reg_het.h + + + het.h + + + het.c + + + reg_htu.h + + + htu.h + + + + + + + + + reg_esm.h + + + esm.h + + + esm.c + + + reg_i2c.h + + + i2c.h + + + + emac.h + + + hw_emac.h + + + hw_emac_ctrl.h + + + hw_mdio.h + + + hw_reg_access.h + + + mdio.h + + + emac.c + + + mdio.c + + + phy_dp83640.c + + + phy_dp83640.h + + + reg_dcc.h + + + dcc.h + + + + reg_emif.h + + + emif.h + + + emif.c + + + reg_pom.h + + + pom.h + + + + usbcdc.h + + + usb_serial_structs.h + + + usbdcdc.h + + + usbdevice.h + + + usbdevicepriv.h + + + usb-ids.h + + + usblib.h + + + usb.h + + + hw_usb.h + + + + + + + + + + + + reg_crc.h + + + crc.h + + + + reg_etpwm.h + + + etpwm.h + + + + reg_ecap.h + + + ecap.h + + + + reg_eqep.h + + + eqep.h + + + + Device_RM46.h + + + Device_header.h + + + Device_types.h + + + ti_fee_cfg.h + + + MemMap.h + + + ti_fee_types.h + + + ti_fee.h + + + fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + include\os_projdefs.h + + + include\FreeRTOSConfig.h + + + include\os_portmacro.h + + + include\os_mpu_wrappers.h + + + include\os_portable.h + + + include\FreeRTOS.h + + + include\os_list.h + + + include\os_queue.h + + + include\os_semphr.h + + + include\os_croutine.h + + + include\os_StackMacros.h + + + include\os_task.h + + + include\os_timer.h + + + source\os_port.c + + + source\os_portasm.s + + + source\os_tasks.c + + + source\os_queue.c + + + source\os_list.c + + + source\os_croutine.c + + + source\os_timer.c + + + source\os_mpu_wrappers.c + + + source\os_heap.c + + + source\os_event_groups.c + + + include\os_event_groups.h + + + + + + + include\reg_pinmux.h + + + include\pinmux.h + + + source\pinmux.c + + + + + + + include\reg_gio.h + + + include\gio.h + + + source\gio.c + + + + + + + include\reg_sci.h + + + include\sci.h + + + source\sci.c + + + + + + + include\reg_lin.h + + + include\lin.h + + + + + + + + + + include\reg_mibspi.h + + + include\mibspi.h + + + source\mibspi.c + + + + + + + include\reg_spi.h + + + include\spi.h + + + source\spi.c + + + + + + + include\reg_can.h + + + include\can.h + + + source\can.c + + + + + + + include\reg_adc.h + + + include\adc.h + + + source\adc.c + + + + + + + include\std_nhet.h + + + include\reg_het.h + + + include\het.h + + + source\het.c + + + include\reg_htu.h + + + include\htu.h + + + + + + + include\reg_esm.h + + + include\esm.h + + + source\esm.c + + + + + + + include\reg_i2c.h + + + include\i2c.h + + + + + + + + + + include\emac.h + + + include\hw_emac.h + + + include\hw_emac_ctrl.h + + + include\hw_mdio.h + + + include\hw_reg_access.h + + + include\mdio.h + + + source\emac.c + + + source\mdio.c + + + source\phy_dp83640.c + + + include\phy_dp83640.h + + + + + + + include\reg_dcc.h + + + include\dcc.h + + + + + + + + + + include\reg_emif.h + + + include\emif.h + + + source\emif.c + + + + + + + include\reg_pom.h + + + include\pom.h + + + + + + + + + + include\usbcdc.h + + + include\usb_serial_structs.h + + + include\usbdcdc.h + + + include\usbdevice.h + + + include\usbdevicepriv.h + + + include\usb-ids.h + + + include\usblib.h + + + include\usb.h + + + include\hw_usb.h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + include\reg_crc.h + + + include\crc.h + + + + + + + + + + include\reg_etpwm.h + + + include\etpwm.h + + + + + + + + + + include\reg_ecap.h + + + include\ecap.h + + + + + + + + + + include\reg_eqep.h + + + include\eqep.h + + + + + + + + + + include\Device_RM46.h + + + include\Device_header.h + + + include\Device_types.h + + + include\ti_fee_cfg.h + + + include\MemMap.h + + + include\ti_fee_types.h + + + include\ti_fee.h + + + include\fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_RM46.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_RM46.h new file mode 100644 index 00000000000..689d3f4c211 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_RM46.h @@ -0,0 +1,112 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_RM46.c + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the number of sectors. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy History Added. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_RM46_H + #define DEVICE_RM46_H + + /** @def DEVICE_CONFIGURATION_VERSION + * @brief Device Configuration Version + * + * @note Indicates the current version of the device files + */ + #define DEVICE_CONFIGURATION_VERSION \ + 0U /* Indicates the current version of the device files */ + + /** @def DEVICE_NUMBER_OF_FLASH_BANKS + * @brief Number of Flash Banks + * + * @note Defines the number of Flash Banks on the device + */ + #define DEVICE_NUMBER_OF_FLASH_BANKS \ + 1U /* Defines the number of Flash Banks on the device */ + + /** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS + * @brief Maximum number of Sectors + * + * @note Defines the maxium number of sectors in all banks + */ + #define DEVICE_BANK_MAX_NUMBER_OF_SECTORS \ + 4U /* Defines the maxium number of sectors in all banks */ + + /** @def DEVICE_BANK1_NUMBER_OF_SECTORS + * @brief Number of Sectors + * + * @note Defines the number of sectors in bank1 + */ + #define DEVICE_BANK1_NUMBER_OF_SECTORS \ + 4U /* Defines the number of sectors in bank1 \ + */ + + /** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS + * @brief Number of Sectors + * + * @note Defines the number of Read Cycle Thresholds + */ + #define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS \ + 4U /* Defines the number of Read Cycle Thresholds */ + + /* Include Files */ + #ifndef _PLATFORM_TYPES_H_ + #define _PLATFORM_TYPES_H_ + #endif + #include "F021.h" + #include "hal_stdtypes.h" + #include "Device_types.h" + +#endif /* DEVICE_RM46_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_header.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_header.h new file mode 100644 index 00000000000..6ed76ab3fd6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_header.h @@ -0,0 +1,65 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_header.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file includes the header file. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy History Added. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef TI_FEE_DEVICEHEADER_H +#define TI_FEE_DEVICEHEADER_H + +/* Uncomment the appropriate include file depending on the device you are using */ +#include "Device_RM46.h" + +/* End of file */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_types.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_types.h new file mode 100644 index 00000000000..5508dc67a41 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/Device_types.h @@ -0,0 +1,133 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the structures. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy History Added. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_TYPES_H + #define DEVICE_TYPES_H + + #include "hal_stdtypes.h" + +/* Enum to describe the type of error handling on the device */ +typedef enum +{ + Device_ErrorHandlingNone, /* Device has no error handling */ + Device_ErrorHandlingParity, /* Device has parity error handling */ + Device_ErrorHandlingEcc /* Device has ECC error handling */ +} Device_FlashErrorCorrectionProcessType; + +/* Enum to describe the ARM core on the device*/ +typedef enum +{ + Device_CoreNone, /* To indicate that the device has a single core */ + Device_Arm7, /* To indicate that the device has a ARM7 core */ + Device_CortexR4, /* To indicate that the device has a CortexR4 core */ + Device_CortexM3 /* To indicate that the device has a CortexM3 core */ +} Device_ArmCoreType; + +/* Structure defines an individual sector within a bank */ +typedef struct +{ + Fapi_FlashSectorType Device_Sector; /* Sector number */ + uint32 Device_SectorStartAddress; /* Starting address of the sector */ + uint32 Device_SectorLength; /* Length of the sector */ + uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */ + uint32 Device_EccAddress; + uint32 Device_EccLength; +} Device_SectorType; + +/* Structure defines an individual bank */ +typedef struct +{ + Fapi_FmcRegistersType * Device_ControlRegister; + Fapi_FlashBankType Device_Core; /* Core number for this bank */ + Device_SectorType Device_SectorInfo[ DEVICE_BANK_MAX_NUMBER_OF_SECTORS ]; /* Array of + the + Sectors + within a + bank */ +} Device_BankType; + +/* Structure defines the Flash structure of the device */ +typedef struct +{ + uint8 Device_DeviceName[ 12 ]; /* Device name */ + uint32 Device_EngineeringId; /* Device Engineering ID */ + Device_FlashErrorCorrectionProcessType + Device_FlashErrorHandlingProcessInfo; /* Indicates + which + type + of bit + Error + handling + is on + the + device + */ + Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device + */ + boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash + interrupts for processing Flash */ + uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS + */ + uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS + */ + Device_BankType Device_BankInfo[ DEVICE_NUMBER_OF_FLASH_BANKS ]; /* Array of Banks on + the device */ +} Device_FlashType; + +#endif /* DEVICE_TYPES_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/MemMap.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/MemMap.h new file mode 100644 index 00000000000..9acca6757e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/MemMap.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MEM_MAP_H__ +#define __MEM_MAP_H__ + +#endif /* __MEM_MAP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/adc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/adc.h new file mode 100644 index 00000000000..95d8aa60fc9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/adc.h @@ -0,0 +1,343 @@ +/** @file adc.h + * @brief ADC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +#include "reg_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ADC General Definitions */ + +/** @def adcGROUP0 + * @brief Alias name for ADC event group + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP0 0U + +/** @def adcGROUP1 + * @brief Alias name for ADC group 1 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP1 1U + +/** @def adcGROUP2 + * @brief Alias name for ADC group 2 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP2 2U + +/** @def ADC_12_BIT_MODE + * @brief Alias name for ADC 12-bit mode of operation + */ +#define ADC_12_BIT_MODE 0x80000000U + +/** @enum adcResolution + * @brief Alias names for data resolution + * This enumeration is used to provide alias names for the data resolution: + * - 12 bit resolution + * - 10 bit resolution + * - 8 bit resolution + */ +enum adcResolution +{ + ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */ + ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */ + ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */ +}; + +/** @enum adcFiFoStatus + * @brief Alias names for FiFo status + * This enumeration is used to provide alias names for the current FiFo states: + * - FiFo is not full + * - FiFo is full + * - FiFo overflow occurred + */ + +enum adcFiFoStatus +{ + ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */ + ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */ + ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */ +}; + +/** @enum adcConversionStatus + * @brief Alias names for conversion status + * This enumeration is used to provide alias names for the current conversion states: + * - Conversion is not finished + * - Conversion is finished + */ + +enum adcConversionStatus +{ + ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished + */ + ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */ +}; + +/** @enum adc1HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc1HwTriggerSource +{ + ADC1_EVENT = 0U, /**< Alias for event pin */ + ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + + ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/** @enum adc2HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc2HwTriggerSource +{ + ADC2_EVENT = 0U, /**< Alias for event pin */ + ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct adcData + * @brief ADC Conversion data structure + * + * This type is used to pass adc conversion data. + */ + +/** @typedef adcData_t + * @brief ADC Data Type Definition + */ +typedef struct adcData +{ + uint32 id; /**< Channel/Pin Id */ + uint16 value; /**< Conversion data value */ +} adcData_t; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +typedef struct adc_config_reg +{ + uint32 CONFIG_OPMODECR; + uint32 CONFIG_CLOCKCR; + uint32 CONFIG_GxMODECR[ 3U ]; + uint32 CONFIG_G0SRC; + uint32 CONFIG_G1SRC; + uint32 CONFIG_G2SRC; + uint32 CONFIG_BNDCR; + uint32 CONFIG_BNDEND; + uint32 CONFIG_G0SAMP; + uint32 CONFIG_G1SAMP; + uint32 CONFIG_G2SAMP; + uint32 CONFIG_G0SAMPDISEN; + uint32 CONFIG_G1SAMPDISEN; + uint32 CONFIG_G2SAMPDISEN; + uint32 CONFIG_PARCR; +} adc_config_reg_t; + +#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC1_CLOCKCR_CONFIGVALUE ( 10U ) + +#define ADC1_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC1_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC1_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC1_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) + +#define ADC1_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC1_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC1_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC1_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC1_PARCR_CONFIGVALUE ( 0x00000005U ) + +#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC2_CLOCKCR_CONFIGVALUE ( 10U ) + +#define ADC2_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC2_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC2_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC2_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) + +#define ADC2_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC2_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC2_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC2_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC2_PARCR_CONFIGVALUE ( 0x00000005U ) + +/** + * @defgroup ADC ADC + * @brief Analog To Digital Converter Module. + * + * The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit + *resolution + * + * Related Files + * - reg_adc.h + * - adc.h + * - adc.c + * @addtogroup ADC + * @{ + */ + +/* ADC Interface Functions */ + +void adcInit( void ); +void adcStartConversion( adcBASE_t * adc, uint32 group ); +void adcStopConversion( adcBASE_t * adc, uint32 group ); +void adcResetFiFo( adcBASE_t * adc, uint32 group ); +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ); +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ); +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ); +void adcEnableNotification( adcBASE_t * adc, uint32 group ); +void adcDisableNotification( adcBASE_t * adc, uint32 group ); +void adcCalibration( adcBASE_t * adc ); +uint32 adcMidPointCalibration( adcBASE_t * adc ); +void adcSetEVTPin( adcBASE_t * adc, uint32 value ); +uint32 adcGetEVTPin( adcBASE_t * adc ); + +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void adcNotification(adcBASE_t *adc, uint32 group) + * @brief Group notification + * @param[in] adc Pointer to ADC node: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group number of ADC node: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * @note This function has to be provide by the user. + */ +void adcNotification( adcBASE_t * adc, uint32 group ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* ifndef __ADC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/can.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/can.h new file mode 100644 index 00000000000..051b731769f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/can.h @@ -0,0 +1,880 @@ +/** @file can.h + * @brief CAN Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CAN_H__ +#define __CAN_H__ + +#include "reg_can.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CAN General Definitions */ + +/** @def canLEVEL_ACTIVE + * @brief Alias name for CAN error operation level active (Error counter 0-31) + */ +#define canLEVEL_ACTIVE 0x00U + +/** @def canLEVEL_PASSIVE + * @brief Alias name for CAN error operation level passive (Error counter 32-63) + */ +#define canLEVEL_PASSIVE 0x20U + +/** @def canLEVEL_WARNING + * @brief Alias name for CAN error operation level warning (Error counter 64-127) + */ +#define canLEVEL_WARNING 0x40U + +/** @def canLEVEL_BUS_OFF + * @brief Alias name for CAN error operation level bus off (Error counter 128-255) + */ +#define canLEVEL_BUS_OFF 0x80U + +/** @def canLEVEL_PARITY_ERR + * @brief Alias name for CAN Parity error (Error counter 256-511) + */ +#define canLEVEL_PARITY_ERR 0x100U + +/** @def canLEVEL_TxOK + * @brief Alias name for CAN Sucessful Transmission + */ +#define canLEVEL_TxOK 0x08U + +/** @def canLEVEL_RxOK + * @brief Alias name for CAN Sucessful Reception + */ +#define canLEVEL_RxOK 0x10U + +/** @def canLEVEL_WakeUpPnd + * @brief Alias name for CAN Initiated a WakeUp to system + */ +#define canLEVEL_WakeUpPnd 0x200U + +/** @def canLEVEL_PDA + * @brief Alias name for CAN entered low power mode successfully. + */ +#define canLEVEL_PDA 0x400U + +/** @def canERROR_NO + * @brief Alias name for no CAN error occurred + */ +#define canERROR_OK 0U + +/** @def canERROR_STUFF + * @brief Alias name for CAN stuff error an RX message + */ +#define canERROR_STUFF 1U + +/** @def canERROR_FORMAT + * @brief Alias name for CAN form/format error an RX message + */ +#define canERROR_FORMAT 2U + +/** @def canERROR_ACKNOWLEDGE + * @brief Alias name for CAN TX message wasn't acknowledged + */ +#define canERROR_ACKNOWLEDGE 3U + +/** @def canERROR_BIT1 + * @brief Alias name for CAN TX message sending recessive level but monitoring dominant + */ +#define canERROR_BIT1 4U + +/** @def canERROR_BIT0 + * @brief Alias name for CAN TX message sending dominant level but monitoring recessive + */ +#define canERROR_BIT0 5U + +/** @def canERROR_CRC + * @brief Alias name for CAN RX message received wrong CRC + */ +#define canERROR_CRC 6U + +/** @def canERROR_NO + * @brief Alias name for CAN no message has send or received since last call of + * CANGetLastError + */ +#define canERROR_NO 7U + +/** @def canMESSAGE_BOX1 + * @brief Alias name for CAN message box 1 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX1 1U + +/** @def canMESSAGE_BOX2 + * @brief Alias name for CAN message box 2 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX2 2U + +/** @def canMESSAGE_BOX3 + * @brief Alias name for CAN message box 3 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX3 3U + +/** @def canMESSAGE_BOX4 + * @brief Alias name for CAN message box 4 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX4 4U + +/** @def canMESSAGE_BOX5 + * @brief Alias name for CAN message box 5 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX5 5U + +/** @def canMESSAGE_BOX6 + * @brief Alias name for CAN message box 6 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX6 6U + +/** @def canMESSAGE_BOX7 + * @brief Alias name for CAN message box 7 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX7 7U + +/** @def canMESSAGE_BOX8 + * @brief Alias name for CAN message box 8 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX8 8U + +/** @def canMESSAGE_BOX9 + * @brief Alias name for CAN message box 9 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX9 9U + +/** @def canMESSAGE_BOX10 + * @brief Alias name for CAN message box 10 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX10 10U + +/** @def canMESSAGE_BOX11 + * @brief Alias name for CAN message box 11 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX11 11U + +/** @def canMESSAGE_BOX12 + * @brief Alias name for CAN message box 12 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX12 12U + +/** @def canMESSAGE_BOX13 + * @brief Alias name for CAN message box 13 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX13 13U + +/** @def canMESSAGE_BOX14 + * @brief Alias name for CAN message box 14 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX14 14U + +/** @def canMESSAGE_BOX15 + * @brief Alias name for CAN message box 15 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX15 15U + +/** @def canMESSAGE_BOX16 + * @brief Alias name for CAN message box 16 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX16 16U + +/** @def canMESSAGE_BOX17 + * @brief Alias name for CAN message box 17 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX17 17U + +/** @def canMESSAGE_BOX18 + * @brief Alias name for CAN message box 18 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX18 18U + +/** @def canMESSAGE_BOX19 + * @brief Alias name for CAN message box 19 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX19 19U + +/** @def canMESSAGE_BOX20 + * @brief Alias name for CAN message box 20 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX20 20U + +/** @def canMESSAGE_BOX21 + * @brief Alias name for CAN message box 21 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX21 21U + +/** @def canMESSAGE_BOX22 + * @brief Alias name for CAN message box 22 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX22 22U + +/** @def canMESSAGE_BOX23 + * @brief Alias name for CAN message box 23 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX23 23U + +/** @def canMESSAGE_BOX24 + * @brief Alias name for CAN message box 24 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX24 24U + +/** @def canMESSAGE_BOX25 + * @brief Alias name for CAN message box 25 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX25 25U + +/** @def canMESSAGE_BOX26 + * @brief Alias name for CAN message box 26 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX26 26U + +/** @def canMESSAGE_BOX27 + * @brief Alias name for CAN message box 27 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX27 27U + +/** @def canMESSAGE_BOX28 + * @brief Alias name for CAN message box 28 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX28 28U + +/** @def canMESSAGE_BOX29 + * @brief Alias name for CAN message box 29 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX29 29U + +/** @def canMESSAGE_BOX30 + * @brief Alias name for CAN message box 30 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX30 30U + +/** @def canMESSAGE_BOX31 + * @brief Alias name for CAN message box 31 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX31 31U + +/** @def canMESSAGE_BOX32 + * @brief Alias name for CAN message box 32 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX32 32U + +/** @def canMESSAGE_BOX33 + * @brief Alias name for CAN message box 33 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX33 33U + +/** @def canMESSAGE_BOX34 + * @brief Alias name for CAN message box 34 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX34 34U + +/** @def canMESSAGE_BOX35 + * @brief Alias name for CAN message box 35 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX35 35U + +/** @def canMESSAGE_BOX36 + * @brief Alias name for CAN message box 36 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX36 36U + +/** @def canMESSAGE_BOX37 + * @brief Alias name for CAN message box 37 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX37 37U + +/** @def canMESSAGE_BOX38 + * @brief Alias name for CAN message box 38 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX38 38U + +/** @def canMESSAGE_BOX39 + * @brief Alias name for CAN message box 39 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX39 39U + +/** @def canMESSAGE_BOX40 + * @brief Alias name for CAN message box 40 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX40 40U + +/** @def canMESSAGE_BOX41 + * @brief Alias name for CAN message box 41 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX41 41U + +/** @def canMESSAGE_BOX42 + * @brief Alias name for CAN message box 42 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX42 42U + +/** @def canMESSAGE_BOX43 + * @brief Alias name for CAN message box 43 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX43 43U + +/** @def canMESSAGE_BOX44 + * @brief Alias name for CAN message box 44 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX44 44U + +/** @def canMESSAGE_BOX45 + * @brief Alias name for CAN message box 45 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX45 45U + +/** @def canMESSAGE_BOX46 + * @brief Alias name for CAN message box 46 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX46 46U + +/** @def canMESSAGE_BOX47 + * @brief Alias name for CAN message box 47 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX47 47U + +/** @def canMESSAGE_BOX48 + * @brief Alias name for CAN message box 48 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX48 48U + +/** @def canMESSAGE_BOX49 + * @brief Alias name for CAN message box 49 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX49 49U + +/** @def canMESSAGE_BOX50 + * @brief Alias name for CAN message box 50 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX50 50U + +/** @def canMESSAGE_BOX51 + * @brief Alias name for CAN message box 51 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX51 51U + +/** @def canMESSAGE_BOX52 + * @brief Alias name for CAN message box 52 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX52 52U + +/** @def canMESSAGE_BOX53 + * @brief Alias name for CAN message box 53 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX53 53U + +/** @def canMESSAGE_BOX54 + * @brief Alias name for CAN message box 54 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX54 54U + +/** @def canMESSAGE_BOX55 + * @brief Alias name for CAN message box 55 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX55 55U + +/** @def canMESSAGE_BOX56 + * @brief Alias name for CAN message box 56 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX56 56U + +/** @def canMESSAGE_BOX57 + * @brief Alias name for CAN message box 57 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX57 57U + +/** @def canMESSAGE_BOX58 + * @brief Alias name for CAN message box 58 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX58 58U + +/** @def canMESSAGE_BOX59 + * @brief Alias name for CAN message box 59 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX59 59U + +/** @def canMESSAGE_BOX60 + * @brief Alias name for CAN message box 60 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX60 60U + +/** @def canMESSAGE_BOX61 + * @brief Alias name for CAN message box 61 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX61 61U + +/** @def canMESSAGE_BOX62 + * @brief Alias name for CAN message box 62 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX62 62U + +/** @def canMESSAGE_BOX63 + * @brief Alias name for CAN message box 63 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX63 63U + +/** @def canMESSAGE_BOX64 + * @brief Alias name for CAN message box 64 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX64 64U + +/** @enum canloopBackType + * @brief canLoopback type definition + */ + +/** @typedef canloopBackType_t + * @brief canLoopback type Type Definition + * + * This type is used to select the can module Loopback type Digital or Analog loopback. + */ +typedef enum canloopBackType +{ + Internal_Lbk = 0x00000010U, + External_Lbk = 0x00000100U, + Internal_Silent_Lbk = 0x00000018U +} canloopBackType_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct can_config_reg +{ + uint32 CONFIG_CTL; + uint32 CONFIG_ES; + uint32 CONFIG_BTR; + uint32 CONFIG_TEST; + uint32 CONFIG_ABOTR; + uint32 CONFIG_INTMUX0; + uint32 CONFIG_INTMUX1; + uint32 CONFIG_INTMUX2; + uint32 CONFIG_INTMUX3; + uint32 CONFIG_TIOC; + uint32 CONFIG_RIOC; +} can_config_reg_t; + +/* Configuration registers initial value for CAN1*/ +#define CAN1_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN1_ES_CONFIGVALUE 0x00000007U +#define CAN1_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 4U + 3U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 6U ) | ( uint32 ) 19U ) +#define CAN1_TEST_CONFIGVALUE 0x00000080U +#define CAN1_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN1_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN1_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN1_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) +#define CAN1_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN2*/ +#define CAN2_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN2_ES_CONFIGVALUE 0x00000007U +#define CAN2_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 4U + 3U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 6U ) | ( uint32 ) 19U ) +#define CAN2_TEST_CONFIGVALUE 0x00000080U +#define CAN2_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN2_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN2_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) +#define CAN2_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN3*/ +#define CAN3_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN3_ES_CONFIGVALUE 0x00000007U +#define CAN3_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 4U + 3U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 6U ) | ( uint32 ) 19U ) +#define CAN3_TEST_CONFIGVALUE 0x00000080U +#define CAN3_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN3_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN3_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) +#define CAN3_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/** + * @defgroup CAN CAN + * @brief Controller Area Network Module. + * + * The Controller Area Network is a high-integrity, serial, multi-master communication + * protocol for distributed real-time applications. This CAN module is implemented + * according to ISO 11898-1 and is suitable for industrial, automotive and general + * embedded communications + * + * Related Files + * - reg_can.h + * - can.h + * - can.c + * @addtogroup CAN + * @{ + */ + +/* CAN Interface Functions */ + +void canInit( void ); +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ); +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ); +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ); +uint32 canFillMessageObjectData( canBASE_t * node, + uint32 messageBox, + const uint8 * data ); +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ); +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ); +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ); +uint32 canGetLastError( canBASE_t * node ); +uint32 canGetErrorLevel( canBASE_t * node ); +void canEnableErrorNotification( canBASE_t * node ); +void canDisableErrorNotification( canBASE_t * node ); +void canEnableStatusChangeNotification( canBASE_t * node ); +void canDisableStatusChangeNotification( canBASE_t * node ); +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ); +void canDisableloopback( canBASE_t * node ); +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ); +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ); +uint32 canIoTxGetBit( canBASE_t * node ); +uint32 canIoRxGetBit( canBASE_t * node ); +uint32 canGetID( canBASE_t * node, uint32 messageBox ); +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ); +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void canErrorNotification(canBASE_t *node, uint32 notification) + * @brief Error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Error notification code: + * - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 + * and 63 + * - canLEVEL_WARNING (0x40) : When RX- or TX error counter are between 64 + * and 127 + * - canLEVEL_BUS_OFF (0x80) : When RX- or TX error counter are between 128 + * and 255 + * - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256 + * + * @note This function has to be provide by the user. + */ +void canErrorNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification) + * @brief Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Status change notification code: + * - canLEVEL_TxOK (0x08) : When successful transmission + * - canLEVEL_RxOK (0x10) : When successful reception + * - canLEVEL_WakeUpPnd (0x200): When successful WakeUp to system initiated + * - canLEVEL_PDA (0x400): When successful low power mode entrance + * + * @note This function has to be provide by the user. + */ +void canStatusChangeNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox) + * @brief Message notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * + * @note This function has to be provide by the user. + */ +void canMessageNotification( canBASE_t * node, uint32 messageBox ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __CAN_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/crc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/crc.h new file mode 100644 index 00000000000..2290826807d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/crc.h @@ -0,0 +1,326 @@ +/** @file CRC.h + * @brief CRC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + +#include "reg_crc.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CRC General Definitions */ + +/** @def CRCLEVEL_ACTIVE + * @brief Alias name for CRC error operation level active + */ +#define CRCLEVEL_ACTIVE 0x00U + +/** @def CRC_AUTO + * @brief Alias name for CRC auto mode + */ +#define CRC_AUTO 0x00000001U + +/** @def CRC_SEMI_CPU + * @brief Alias name for semi cpu mode setting + */ +#define CRC_SEMI_CPU 0x00000002U + +/** @def CRC_FULL_CPU + * @brief Alias name for CRC cpu full mode + */ +#define CRC_FULL_CPU 0x00000003U + +/** @def CRC_CH4_TO + * @brief Alias name for channel4 time out interrupt flag + */ +#define CRC_CH4_TO 0x10000000U + +/** @def CRC_CH4_UR + * @brief Alias name for channel4 underrun interrupt flag + */ +#define CRC_CH4_UR 0x08000000U + +/** @def CRC_CH4_OR + * @brief Alias name for channel4 overrun interrupt flag + */ +#define CRC_CH4_OR 0x04000000U + +/** @def CRC_CH4_FAIL + * @brief Alias name for channel4 crc fail interrupt flag + */ +#define CRC_CH4_FAIL 0x02000000U + +/** @def CRC_CH4_CC + * @brief Alias name for channel4 compression complete interrupt flag + */ +#define CRC_CH4_CC 0x01000000U + +/** @def CRC_CH3_TO + * @brief Alias name for channel3 time out interrupt flag + */ +#define CRC_CH3_TO 0x00100000U + +/** @def CRC_CH3_UR + * @brief Alias name for channel3 underrun interrupt flag + */ +#define CRC_CH3_UR 0x00080000U + +/** @def CRC_CH3_OR + * @brief Alias name for channel3 overrun interrupt flag + */ +#define CRC_CH3_OR 0x00040000U + +/** @def CRC_CH3_FAIL + * @brief Alias name for channel3 crc fail interrupt flag + */ +#define CRC_CH3_FAIL 0x00020000U + +/** @def CRC_CH3_CC + * @brief Alias name for channel3 compression complete interrupt flag + */ +#define CRC_CH3_CC 0x00010000U + +/** @def CRC_CH2_TO + * @brief Alias name for channel2 time out interrupt flag + */ +#define CRC_CH2_TO 0x00001000U + +/** @def CRC_CH2_UR + * @brief Alias name for channel2 underrun interrupt flag + */ +#define CRC_CH2_UR 0x00000800U + +/** @def CRC_CH2_OR + * @brief Alias name for channel2 overrun interrupt flag + */ +#define CRC_CH2_OR 0x00000400U + +/** @def CRC_CH2_FAIL + * @brief Alias name for channel2 crc fail interrupt flag + */ +#define CRC_CH2_FAIL 0x00000200U + +/** @def CRC_CH2_CC + * @brief Alias name for channel2 compression complete interrupt flag + */ +#define CRC_CH2_CC 0x00000100U + +/** @def CRC_CH1_TO + * @brief Alias name for channel1 time out interrupt flag + */ +#define CRC_CH1_TO 0x00000010U + +/** @def CRC_CH1_UR + * @brief Alias name for channel1 underrun interrupt flag + */ +#define CRC_CH1_UR 0x00000008U + +/** @def CRC_CH1_OR + * @brief Alias name for channel1 overrun interrupt flag + */ +#define CRC_CH1_OR 0x00000004U + +/** @def CRC_CH1_FAIL + * @brief Alias name for channel1 crc fail interrupt flag + */ +#define CRC_CH1_FAIL 0x00000002U + +/** @def CRC_CH1_CC + * @brief Alias name for channel1 compression complete interrupt flag + */ +#define CRC_CH1_CC 0x00000001U + +/** @def CRC_CH1 + * @brief Alias name for channel1 + */ +#define CRC_CH1 0x00000000U + +/** @def CRC_CH1 + * @brief Alias name for channel2 + */ +#define CRC_CH2 0x00000001U + +/** @def CRC_CH3 + * @brief Alias name for channel3 + */ +#define CRC_CH3 0x00000002U + +/** @def CRC_CH4 + * @brief Alias name for channel4 + */ +#define CRC_CH4 0x00000003U + +/** @struct crcModConfig + * @brief CRC mode specific parameters + * + * This type is used to pass crc mode specific parameters + */ + +/** @typedef crcModConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcModConfig +{ + uint32 mode; /**< Mode of operation */ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint64 * src_data_pat; /**< Pattern data */ + uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/ +} crcModConfig_t; + +/** @struct crcConfig + * @brief CRC configuration for different modes + * + * This type is used to pass crc configuration + */ + +/** @typedef crcConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcConfig +{ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint32 mode; /**< Mode of operation */ + uint32 pcount; /**< Pattern count*/ + uint32 scount; /**< Sector count */ + uint32 wdg_preload; /**< Watchdog period */ + uint32 block_preload; /**< Block period*/ +} crcConfig_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +typedef struct crc_config_reg +{ + uint32 CONFIG_CTRL0; + uint32 CONFIG_CTRL1; + uint32 CONFIG_CTRL2; + uint32 CONFIG_INTS; + uint32 CONFIG_PCOUNT_REG1; + uint32 CONFIG_SCOUNT_REG1; + uint32 CONFIG_WDTOPLD1; + uint32 CONFIG_BCTOPLD1; + uint32 CONFIG_PCOUNT_REG2; + uint32 CONFIG_SCOUNT_REG2; + uint32 CONFIG_WDTOPLD2; + uint32 CONFIG_BCTOPLD2; +} crc_config_reg_t; + +#define CRC_CTRL0_CONFIGVALUE 0x00000000U +#define CRC_CTRL1_CONFIGVALUE 0x00000000U +#define CRC_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC_PCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC_SCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC_WDTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC_BCTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC_PCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC_SCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC_WDTOPLD2_CONFIGVALUE ( 0x00000000U ) +#define CRC_BCTOPLD2_CONFIGVALUE ( 0x00000000U ) + +/** + * @defgroup CRC CRC + * @brief Cyclic Redundancy Check Controller Module. + * + * The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) + *to verify the integrity of memory system. A signature representing the contents of the + *memory is obtained when the contents of the memory are read into CRC controller. The + *responsibility of CRC controller is to calculate the signature for a set of data and + *then compare the calculated signature value against a pre-determined good signature + *value. CRC controller supports two channels to perform CRC calculation on multiple + * memories in parallel and can be used on any memory system. + * + * Related Files + * - reg_crc.h + * - crc.h + * - crc.c + * @addtogroup CRC + * @{ + */ + +/* CRC Interface Functions */ +void crcInit( void ); +void crcSendPowerDown( crcBASE_t * crc ); +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ); +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ); +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ); +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ); +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ); +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ); +void crcChannelReset( crcBASE_t * crc, uint32 channel ); +void crcEnableNotification( crcBASE_t * crc, uint32 flags ); +void crcDisableNotification( crcBASE_t * crc, uint32 flags ); +void crcGetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void crcNotification(crcBASE_t *crc, uint32 flags) + * @brief Interrupt callback + * @param[in] crc - crc module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void crcNotification( crcBASE_t * crc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __CRC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/dcc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/dcc.h new file mode 100644 index 00000000000..0b00b2bb13b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/dcc.h @@ -0,0 +1,308 @@ +/** @file dcc.h + * @brief DCC Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DCC_H__ +#define __DCC_H__ + +#include "reg_dcc.h" +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DCC General Definitions */ + +/** @def dcc1CNT0_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 0 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U + +/** @def dcc1CNT0_CLKSRC_TCK + * @brief Alias name for DCC1 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc1CNT1_CLKSRC_PLL1 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL1 + * + * This is an alias name for the Clock Source PLL for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U + +/** @def dcc1CNT1_CLKSRC_PLL2 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL2 + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U + +/** @def dcc1CNT1_CLKSRC_LFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source LFLPO + * + * This is an alias name for the Clock Source LFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U + +/** @def dcc1CNT1_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN1 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1 + * + * This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN2 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2 + * + * This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U + +/** @def dcc1CNT1_CLKSRC_VCLK + * @brief Alias name for DCC1 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc1CNT1_CLKSRC_N2HET1_31 + * @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31 + * + * This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU + +/** @def dcc2CNT0_CLKSRC_TCK + * @brief Alias name for DCC2 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc2CNT1_CLKSRC_VCLK + * @brief Alias name for DCC2 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc2CNT1_CLKSRC_N2HET1_0 + * @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0 + * + * This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU + +/** @def dccNOTIFICATION_DONE + * @brief Alias name for DCC Done notification + * + * This is an alias name for the DCC Done notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_DONE 0x0000A000U + +/** @def dccNOTIFICATION_ERROR + * @brief Alias name for DCC Error notification + * + * This is an alias name for the DCC Error notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_ERROR 0x000000A0U + +/** @enum dcc1clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc1clocksource +{ + DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/ + DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/ + DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/ + DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/ + DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/ + DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/** @enum dcc2clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc2clocksource +{ + DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/* Configuration registers */ +typedef struct dcc_config_reg +{ + uint32 CONFIG_GCTRL; + uint32 CONFIG_CNT0SEED; + uint32 CONFIG_VALID0SEED; + uint32 CONFIG_CNT1SEED; + uint32 CONFIG_CNT1CLKSRC; + uint32 CONFIG_CNT0CLKSRC; +} dcc_config_reg_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** + * @defgroup DCC DCC + * @brief Dual-Clock Comparator Module + * + * The primary purpose of a DCC module is to measure the frequency of a clock signal + * using a second known clock signal as a reference. This capability can be used to ensure + * the correct frequency range for several different device clock sources, thereby + * enhancing the system safety metrics. + * + * Related Files + * - reg_dcc.h + * - dcc.h + * - dcc.c + * @addtogroup DCC + * @{ + */ + +/* DCC Interface Functions */ +void dccInit( void ); +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ); +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ); +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ); +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ); +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ); +void dccEnable( dccBASE_t * dcc ); +void dccDisable( dccBASE_t * dcc ); +uint32 dccGetErrStatus( dccBASE_t * dcc ); + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ); +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ); +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags) + * @brief Interrupt callback + * @param[in] dcc - dcc module base address + * @param[in] flags - status flags + * + * This is a callback function provided by the application. It is call when + * a dcc is complete or detected error. + */ +void dccNotification( dccBASE_t * dcc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __DCC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ecap.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ecap.h new file mode 100644 index 00000000000..c8dbcc50d46 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ecap.h @@ -0,0 +1,348 @@ +/** @file ecap.h + * @brief ECAP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#include "reg_ecap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @brief Enumeration to define the capture (CAP) interrupts + */ +typedef enum +{ + ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */ + ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */ + ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */ + ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */ + ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */ + ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */ + ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */ + ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */ + ecapInt_All = 0x00FFU /*< Denotes All interrupts */ +} ecapInterrupt_t; + +/** @brief Enumeration to define the capture (CAP) prescaler values + */ +typedef enum +{ + ecapPrescale_By_1 = ( ( uint16 ) 0U << 9U ), /*< Divide by 1 */ + ecapPrescale_By_2 = ( ( uint16 ) 1U << 9U ), /*< Divide by 2 */ + ecapPrescale_By_4 = ( ( uint16 ) 2U << 9U ), /*< Divide by 4 */ + ecapPrescale_By_6 = ( ( uint16 ) 3U << 9U ), /*< Divide by 6 */ + ecapPrescale_By_8 = ( ( uint16 ) 4U << 9U ), /*< Divide by 8 */ + ecapPrescale_By_10 = ( ( uint16 ) 5U << 9U ), /*< Divide by 10 */ + ecapPrescale_By_12 = ( ( uint16 ) 6U << 9U ), /*< Divide by 12 */ + ecapPrescale_By_14 = ( ( uint16 ) 7U << 9U ), /*< Divide by 14 */ + ecapPrescale_By_16 = ( ( uint16 ) 8U << 9U ), /*< Divide by 16 */ + ecapPrescale_By_18 = ( ( uint16 ) 9U << 9U ), /*< Divide by 18 */ + ecapPrescale_By_20 = ( ( uint16 ) 10U << 9U ), /*< Divide by 20 */ + ecapPrescale_By_22 = ( ( uint16 ) 11U << 9U ), /*< Divide by 22 */ + ecapPrescale_By_24 = ( ( uint16 ) 12U << 9U ), /*< Divide by 24 */ + ecapPrescale_By_26 = ( ( uint16 ) 13U << 9U ), /*< Divide by 26 */ + ecapPrescale_By_28 = ( ( uint16 ) 14U << 9U ), /*< Divide by 28 */ + ecapPrescale_By_30 = ( ( uint16 ) 15U << 9U ), /*< Divide by 30 */ + ecapPrescale_By_32 = ( ( uint16 ) 16U << 9U ), /*< Divide by 32 */ + ecapPrescale_By_34 = ( ( uint16 ) 17U << 9U ), /*< Divide by 34 */ + ecapPrescale_By_36 = ( ( uint16 ) 18U << 9U ), /*< Divide by 36 */ + ecapPrescale_By_38 = ( ( uint16 ) 19U << 9U ), /*< Divide by 38 */ + ecapPrescale_By_40 = ( ( uint16 ) 20U << 9U ), /*< Divide by 40 */ + ecapPrescale_By_42 = ( ( uint16 ) 21U << 9U ), /*< Divide by 42 */ + ecapPrescale_By_44 = ( ( uint16 ) 22U << 9U ), /*< Divide by 44 */ + ecapPrescale_By_46 = ( ( uint16 ) 23U << 9U ), /*< Divide by 46 */ + ecapPrescale_By_48 = ( ( uint16 ) 24U << 9U ), /*< Divide by 48 */ + ecapPrescale_By_50 = ( ( uint16 ) 25U << 9U ), /*< Divide by 50 */ + ecapPrescale_By_52 = ( ( uint16 ) 26U << 9U ), /*< Divide by 52 */ + ecapPrescale_By_54 = ( ( uint16 ) 27U << 9U ), /*< Divide by 54 */ + ecapPrescale_By_56 = ( ( uint16 ) 28U << 9U ), /*< Divide by 56 */ + ecapPrescale_By_58 = ( ( uint16 ) 29U << 9U ), /*< Divide by 58 */ + ecapPrescale_By_60 = ( ( uint16 ) 30U << 9U ), /*< Divide by 60 */ + ecapPrescale_By_62 = ( ( uint16 ) 31U << 9U ) /*< Divide by 62 */ +} ecapPrescale_t; + +/** @brief Enumeration to define the Sync Out options + */ +typedef enum +{ + SyncOut_SyncIn = ( ( uint16 ) 0U << 6U ), /*< Sync In used for Sync Out */ + SyncOut_CTRPRD = ( ( uint16 ) 1U << 6U ), /*< CTR = PRD used for Sync Out */ + SyncOut_None = ( ( uint16 ) 2U << 6U ) /*< Disables Sync Out */ +} ecapSyncOut_t; + +/** @brief Enumeration to define the Polarity + */ +typedef enum +{ + RISING_EDGE = 0U, + FALLING_EDGE = 1U +} ecapEdgePolarity_t; + +typedef enum +{ + ACTIVE_HIGH = 0U, + ACTIVE_LOW = 1U +} ecapAPWMPolarity_t; + +/** @brief Enumeration to define the Mode of operation + */ +typedef enum +{ + CONTINUOUS = 0U, + ONE_SHOT = 1U +} ecapMode_t; + +/** @brief Enumeration to define the capture events + */ +typedef enum +{ + CAPTURE_EVENT1 = 0U, + CAPTURE_EVENT2 = 1U, + CAPTURE_EVENT3 = 2U, + CAPTURE_EVENT4 = 3U +} ecapEvent_t; + +typedef enum +{ + RESET_ENABLE = 1U, + RESET_DISABLE = 0U +} ecapReset_t; + +typedef struct ecap_config_reg +{ + uint32 CONFIG_CTRPHS; + uint16 CONFIG_ECCTL1; + uint16 CONFIG_ECCTL2; + uint16 CONFIG_ECEINT; +} ecap_config_reg_t; + +#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP1_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP1_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP1_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP2_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP2_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP2_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP3_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP3_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP3_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP4_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP4_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP4_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP5_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP5_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP5_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP6_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP6_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP6_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +/** + * @defgroup eCAP eCAP + * @brief Enhanced Capture Module. + * + * The enhanced Capture (eCAP) module is essential in systems where accurate timing of + *external events is important. This microcontroller implements 6 instances of the eCAP + *module. + * + * Related Files + * - reg_ecap.h + * - ecap.h + * - ecap.c + * @addtogroup eCAP + * @{ + */ +void ecapInit( void ); +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ); +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ); +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ); +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ); +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ); +void ecapEnableCapture( ecapBASE_t * ecap ); +void ecapDisableCapture( ecapBASE_t * ecap ); +void ecapStartCounter( ecapBASE_t * ecap ); +void ecapStopCounter( ecapBASE_t * ecap ); +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ); +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ); +void ecapDisableAPWMMode( ecapBASE_t * ecap ); +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ); +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ); +uint32 ecapGetCAP1( ecapBASE_t * ecap ); +uint32 ecapGetCAP2( ecapBASE_t * ecap ); +uint32 ecapGetCAP3( ecapBASE_t * ecap ); +uint32 ecapGetCAP4( ecapBASE_t * ecap ); +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); + +/** @brief Interrupt callback + * @param[in] ecap Handle to CAP object + * @param[in] flags Copy of interrupt flags + */ +void ecapNotification( ecapBASE_t * ecap, uint16 flags ); + +/**@}*/ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +#endif /*end of _CAP_H_ definition */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/emac.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/emac.h new file mode 100644 index 00000000000..99f74dc8c59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/emac.h @@ -0,0 +1,440 @@ +/** + * \file emac.h + * + * \brief EMAC APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __EMAC_H__ +#define __EMAC_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "hw_reg_access.h" +#include "hw_emac.h" +#include "hw_emac_ctrl.h" +#include "mdio.h" +#include "phy_dp83640.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/*****************************************************************************/ + +/* +** Macros which can be used as speed parameter to the API EMACRMIISpeedSet +*/ +#define EMAC_RMIISPEED_10MBPS ( 0x00000000U ) +#define EMAC_RMIISPEED_100MBPS ( 0x00008000U ) + +/* Macros for enabling taken as inputs from HALCoGen GUI. */ +#define EMAC_TX_ENABLE ( 1U ) +#define EMAC_RX_ENABLE ( 1U ) +#define EMAC_MII_ENABLE ( 1U ) +#define EMAC_FULL_DUPLEX_ENABLE ( 1U ) +#define EMAC_LOOPBACK_ENABLE ( 0U ) +#define EMAC_BROADCAST_ENABLE ( 1U ) +#define EMAC_UNICAST_ENABLE ( 1U ) +#define EMAC_CHANNELNUMBER ( 0U ) +#define EMAC_PHYADDRESS ( 0U ) + +/* + * Macros to indicate EMAC Channel Numbers + */ +#define EMAC_CHANNEL_0 ( 0x00000000U ) +#define EMAC_CHANNEL_1 ( 0x00000001U ) +#define EMAC_CHANNEL_2 ( 0x00000002U ) +#define EMAC_CHANNEL_3 ( 0x00000003U ) +#define EMAC_CHANNEL_4 ( 0x00000004U ) +#define EMAC_CHANNEL_5 ( 0x00000005U ) +#define EMAC_CHANNEL_6 ( 0x00000006U ) +#define EMAC_CHANNEL_7 ( 0x00000007U ) + +/* Macros which can be used as duplexMode parameter to the API +** EMACDuplexSet +*/ +#define EMAC_DUPLEX_FULL ( 0x00000001U ) +#define EMAC_DUPLEX_HALF ( 0x00000000U ) + +/* +** Macros which can be used as matchFilt parameters to the API +** EMACMACAddrSet +*/ +/* Address not used to match/filter incoming packets */ +#define EMAC_MACADDR_NO_MATCH_NO_FILTER ( 0x00000000U ) + +/* Address will be used to filter incoming packets */ +#define EMAC_MACADDR_FILTER ( 0x00100000U ) + +/* Address will be used to match incoming packets */ +#define EMAC_MACADDR_MATCH ( 0x00180000U ) + +/* +** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API +*/ +#define EMAC_INT_CORE0_RX ( 0x1U ) +#define EMAC_INT_CORE1_RX ( 0x5U ) +#define EMAC_INT_CORE2_RX ( 0x9U ) + +/* +** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API +*/ +#define EMAC_INT_CORE0_TX ( 0x2U ) +#define EMAC_INT_CORE1_TX ( 0x6U ) +#define EMAC_INT_CORE2_TX ( 0xAU ) +/* Base Addresses */ +#define EMAC_CTRL_RAM_0_BASE 0xFC520000U +#define EMAC_0_BASE 0xFCF78000U +#define EMAC_CTRL_0_BASE 0xFCF78800U +#define MDIO_0_BASE 0xFCF78900U + +/*MAC address length*/ +#define EMAC_HWADDR_LEN 6U +#define MAX_EMAC_INSTANCE 1U +#define SIZE_EMAC_CTRL_RAM 0x2000U +#define MAX_TRANSFER_UNIT 1514U +#define MAX_RX_PBUF_ALLOC ( 10U ) +#define MIN_PKT_LEN 60U +#define MIN_PACKET_SIZE ( 46U ) + +#define EMAC_BUF_DESC_OWNER 0x20000000U +#define EMAC_BUF_DESC_SOP 0x80000000U +#define EMAC_BUF_DESC_EOP 0x40000000U +#define EMAC_BUF_DESC_EOQ 0x10000000U + +#define EMAC_NETSTATREGS( n ) ( ( uint32 ) 0x200U + ( uint32 ) ( ( n ) * 4U ) ) + +/* Error Signalling Macros */ +#define EMAC_ERR_CONNECT 0x2U /* Not connected. */ +#define EMAC_ERR_OK 0x1U /* No error, everything OK. */ + +/* Macros for Configuration Value Registers */ +#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_MACSRCADDRHI_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 24U ) | ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MACSRCADDRLO_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU +#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U +#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U + +/* Structure to store pending status from the Tx Interrupt Status Registers. */ +typedef struct emac_tx_int_status +{ + volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit + Interrupt Status (Masked) Register (TXINTSTATMASKED) + */ + volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit + Interrupt Status (Unmasked) Register (TXINTSTATRAW) */ +} emac_tx_int_status_t; + +/* Structure to store pending status from the Rx Interrupt Status Registers. */ +typedef struct emac_rx_int_status +{ + volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the + Receive Interrupt Status (Unmasked) + Register (RXINTSTATRAW) */ + + volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive + Interrupt Status (Unmasked) Register + (RXINTSTATRAW) */ +} emac_rx_int_status_t; + +/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure.*/ +typedef struct emac_tx_bd +{ + volatile struct emac_tx_bd * next; + volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be + transmitted. */ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_tx_bd_t; + +/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure. */ +typedef struct emac_rx_bd +{ + volatile struct emac_rx_bd * next; /*Used as a pointer for next element in the linked + list of descriptors.*/ + volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received + data.*/ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_rx_bd_t; + +/** + * Helper struct to hold the data used to operate on a particular + * receive channel + */ +typedef struct rxch_struct +{ + volatile emac_rx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can receive new data.*/ + volatile emac_rx_bd_t * active_head; /*Used to point to the active descriptor in the + chain which is receiving.*/ + volatile emac_rx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ +} rxch_t; + +/** + * Helper struct to hold the data used to operate on a particular + * transmit channel + */ +typedef struct txch_struct +{ + volatile emac_tx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can transmit new data.*/ + volatile emac_tx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ + volatile emac_tx_bd_t * next_bd_to_process; /*Used to point to the next descriptor in + the chain to be processed.*/ +} txch_t; + +/** + * Helper struct to hold private data used to operate the ethernet interface. + */ +typedef struct hdkif_struct +{ + /* MAC Address of the Module. */ + uint8_t mac_addr[ 6 ]; + + /* emac base address */ + uint32 emac_base; + + /* emac controller base address */ + volatile uint32 emac_ctrl_base; + volatile uint32 emac_ctrl_ram; + + /* mdio base address */ + volatile uint32 mdio_base; + + /* phy parameters for this instance - for future use */ + uint32 phy_addr; + boolean ( *phy_autoneg )( uint32 param1, uint32 param2, uint16 param3 ); + boolean ( *phy_partnerability )( uint32 param4, uint32 param5, uint16 * param6 ); + + /* The tx/rx channels for the interface */ + txch_t txchptr; + rxch_t rxchptr; +} hdkif_t; + +/*Ethernet Frame Structure */ +typedef struct ethernet_frame +{ + uint8 dest_addr[ 6 ]; /* Destination MAC Address */ + uint8 src_addr[ 6 ]; /*Source MAC Address. */ + uint16 frame_length; /* Data Frame Length */ + uint8 data[ 1500 ]; /* Data */ +} ethernet_frame_t; + +/* Struct used to take packet data input from the user for transmit APIs. */ +typedef struct pbuf_struct +{ + /** next pbuf in singly linked pbuf chain */ + struct pbuf_struct * next; + + /** + * Pointer to the actual ethernet packet/packet fragment to be transmitted. + * The packet needs to be in the following format: + * |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2 + *bytes)| Data (46- 1500 bytes) The data can be split up over multiple pbufs which are + *linked as a linked list. + **/ + uint8 * payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + uint16 tot_len; + + /** length of this buffer */ + uint16 len; +} pbuf_t; + +/* Structure to hold the values of the EMAC Configuration Registers. */ +typedef struct emac_config_reg_struct +{ + /* EMAC Module Register Values */ + uint32 TXCONTROL; /* Transmit Control Register. */ + uint32 RXCONTROL; /* Receive Control Register */ + uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */ + uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */ + uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */ + uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/ + uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/ + uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/ + + /*MDIO Module Registers */ + uint32 MDIOCONTROL; /*MDIO Control Register. */ + + /* EMAC Control Module Registers */ + uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ +} emac_config_reg_t; +/*****************************************************************************/ + +/** + * @defgroup EMACMDIO EMAC/MDIO + * @brief Ethernet Media Access Controller/Management Data Input/Output. + * + * The EMAC controls the flow of packet data from the system to the PHY. The MDIO module + *controls PHY configuration and status monitoring. + * + * Both the EMAC and the MDIO modules interface to the system core through a custom + *interface that allows efficient data transmission and reception. This custom interface + *is referred to as the EMAC control module and is considered integral to the EMAC/MDIO + *peripheral + * + * Related Files + * - emac.h + * - emac.c + * - hw_emac.h + * - hw_emac_ctrl.h + * - hw_mdio.h + * - hw_reg_access.h + * - mdio.h + * - mdio.c + * @addtogroup EMACMDIO + * @{ + */ + +/* +** Prototypes for the APIs +*/ +extern uint32 EMACLinkSetup( hdkif_t * hdkif ); +extern void EMACInstConfig( hdkif_t * hdkif ); +extern void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ); +extern void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ); +extern void EMACTxEnable( uint32 emacBase ); +extern void EMACTxDisable( uint32 emacBase ); +extern void EMACRxEnable( uint32 emacBase ); +extern void EMACRxDisable( uint32 emacBase ); +extern void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACInit( uint32 emacCtrlBase, uint32 emacBase ); +extern void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ); +extern void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ); +extern void EMACMIIEnable( uint32 emacBase ); +extern void EMACMIIDisable( uint32 emacBase ); +extern void EMACRxUnicastSet( uint32 emacBase, uint32 channel ); +extern void EMACRxUnicastClear( uint32 emacBase, uint32 channel ); +extern void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ); +extern void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ); +extern uint32 EMACIntVectorGet( uint32 emacBase ); +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ); +void EMACTxTeardown( uint32 emacBase, uint32 channel ); +void EMACRxTeardown( uint32 emacBase, uint32 channel ); +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ); +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ); +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ); +void EMACEnableIdleState( uint32 emacBase ); +void EMACDisableIdleState( uint32 emacBase ); +void EMACEnableLoopback( uint32 emacBase ); +void EMACDisableLoopback( uint32 emacBase ); +void EMACTxFlowControlEnable( uint32 emacBase ); +void EMACTxFlowControlDisable( uint32 emacBase ); +void EMACRxFlowControlEnable( uint32 emacBase ); +void EMACRxFlowControlDisable( uint32 emacBase ); +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ); +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ); +void EMACDMAInit( hdkif_t * hdkif ); +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ); +void EMACTxIntHandler( hdkif_t * hdkif ); +void EMACReceive( hdkif_t * hdkif ); +/* Notification Function to which received packets are passed after processing */ +void emacTxNotification( hdkif_t * hdkif ); +void emacRxNotification( hdkif_t * hdkif ); +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ); +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ); +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __EMAC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/emif.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/emif.h new file mode 100644 index 00000000000..8e65dcacc63 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/emif.h @@ -0,0 +1,216 @@ +/** @file emif.h + * @brief emif Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ + +#include "reg_emif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum emif_pins + * @brief Alias for emif pins + * + */ +enum emif_pins +{ + emif_wait_pin0 = 0U, + emif_wait_pin1 = 1U +}; + +/** @enum emif_size + * @brief Alias for emif page size + * + */ +enum emif_size +{ + elements_256 = 0U, + elements_512 = 1U, + elements_1024 = 2U, + elements_2048 = 3U +}; + +/** @enum emif_port + * @brief Alias for emif port + * + */ +enum emif_port +{ + emif_8_bit_port = 0U, + emif_16_bit_port = 1U +}; + +/** @enum emif_pagesize + * @brief Alias for emif pagesize + * + */ +enum emif_pagesize +{ + emif_4_words = 0U, + emif_8_words = 1U +}; + +/** @enum emif_wait_polarity + * @brief Alias for emif wait polarity + * + */ +enum emif_wait_polarity +{ + emif_pin_low = 0U, + emif_pin_high = 1U +}; + +#define PTR ( ( volatile uint32 * ) ( 0x80000000U ) ) + +/* Configuration registers */ +typedef struct emif_config_reg +{ + uint32 CONFIG_AWCC; + uint32 CONFIG_SDCR; + uint32 CONFIG_SDRCR; + uint32 CONFIG_CE2CFG; + uint32 CONFIG_CE3CFG; + uint32 CONFIG_CE4CFG; + uint32 CONFIG_CE5CFG; + uint32 CONFIG_SDTIMR; + uint32 CONFIG_SDSRETR; + uint32 CONFIG_INTMSK; + uint32 CONFIG_PMCR; +} emif_config_reg_t; + +/* Configuration registers initial value for EMIF*/ +#define EMIF_AWCC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) \ + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) 0xC0000000U ) + +#define EMIF_SDCR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 31U ) | ( uint32 ) ( ( uint32 ) 1U << 14U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) elements_256 ) ) + +#define EMIF_SDRCR_CONFIGVALUE 0U + +#define EMIF_CE2CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE3CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE4CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE5CFG_CONFIGVALUE 0x3FFFFFFDU + +#define EMIF_SDTIMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | 0x00000000U ) + +#define EMIF_SDSRETR_CONFIGVALUE 0U +#define EMIF_INTMSK_CONFIGVALUE 0x00000000U +#define EMIF_PMCR_CONFIGVALUE \ + ( 0xFC000000U | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +/** + * @defgroup EMIF EMIF + * @brief External Memory Interface. + * + * This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories + *utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU + *to connect to a variety of external devices including: + * - Single data rate (SDR) SDRAM + * - Asynchronous devices including NOR Flash and SRAM + * The most common use for the EMIF is to interface with both a flash device and an SDRAM + *device simultaneously. contains an example of operating the EMIF in this configuration. + * + * Related Files + * - reg_emif.h + * - emif.h + * - emif.c + * @addtogroup EMIF + * @{ + */ +/* EMIF Interface Functions */ + +void emif_SDRAMInit( void ); +void emif_SDRAM_StartupInit( void ); +void emif_ASYNC1Init( void ); +void emif_ASYNC2Init( void ); +void emif_ASYNC3Init( void ); +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /*EMIF_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/eqep.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/eqep.h new file mode 100644 index 00000000000..2a1c1622d66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/eqep.h @@ -0,0 +1,867 @@ +/** @file eqep.h + * @brief EQEP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __eQEP_H__ +#define __eQEP_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "reg_eqep.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/*QDECCTL Register */ +#define eQEP_QDECCTL_QSRC \ + ( ( uint16 ) ( ( uint16 ) 3U << 14U ) ) /* "Reason - TI_Fee_Fix is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_Fee_None is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None + #endif + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_MAXIMUM_BLOCKING_TIME is a + * symbolic constant"*/ + #define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_OPERATING_FREQUENCY is a symbolic + * constant."*/ + #define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_CHECKSUM_ENABLE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - NVM_DATASET_SELECTION_BITS is a + * symbolic constant."*/ + #define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EEPS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_INDEX is a symbolic constant."*/ + #define TI_FEE_INDEX FEE_INDEX + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PAGE_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_BLOCK_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_PAGE_SIZE is a symbolic + * constant."*/ + #define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY + * is a symbolic constant."*/ + #define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY \ + FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a + * symbolic constant."*/ + #define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_END_NOTIFICATION is a + * symbolic constant."*/ + #define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is a + * symbolic constant."*/ + #define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_POLLING_MODE is a symbolic + * constant."*/ + #define TI_FEE_POLLING_MODE FEE_POLLING_MODE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a symbolic + * constant."*/ + #ifndef FEE_CHECK_BANK7_ACCESS + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #endif + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_TOTAL_BLOCKS_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUALSECTOR_SIZE is a symbolic + * constant."*/ + #define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PHYSICALSECTOR_SIZE is a symbolic + * constant."*/ + #define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/ + #define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC \ + FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_USEPARTIALERASEDSECTOR is a + * symbolic constant."*/ + #define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR + + /*----------------------------------------------------------------------------*/ + /* Virtual Sector Configuration */ + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a + * symbolic constant."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is required + * here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 is + * a symbolic constant."*/ + /*SAFETYMCUSW 384 S MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is required + * here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + + /*----------------------------------------------------------------------------*/ + /* Block Configuration */ + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_FEE_VARIABLE_DATASETS is a symbolic + * constant."*/ + #define TI_FEE_VARIABLE_DATASETS STD_ON + + #endif /* TI_FEE_DRIVER */ + +#endif /* FEE_INTERFACE_H */ + +/********************************************************************************************************************** + * END OF FILE: fee_interface.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/gio.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/gio.h new file mode 100644 index 00000000000..c44d11fa60f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/gio.h @@ -0,0 +1,182 @@ +/** @file gio.h + * @brief GIO Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GIO_H__ +#define __GIO_H__ + +#include "reg_gio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef struct gio_config_reg +{ + uint32 CONFIG_INTDET; + uint32 CONFIG_POL; + uint32 CONFIG_INTENASET; + uint32 CONFIG_LVLSET; + + uint32 CONFIG_PORTADIR; + uint32 CONFIG_PORTAPDR; + uint32 CONFIG_PORTAPSL; + uint32 CONFIG_PORTAPULDIS; + + uint32 CONFIG_PORTBDIR; + uint32 CONFIG_PORTBPDR; + uint32 CONFIG_PORTBPSL; + uint32 CONFIG_PORTBPULDIS; +} gio_config_reg_t; + +#define GIO_INTDET_CONFIGVALUE 0U +#define GIO_POL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_INTENASET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_LVLSET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_PORTADIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +#define GIO_PORTBDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +/** + * @defgroup GIO GIO + * @brief General-Purpose Input/Output Module. + * + * The GIO module provides the family of devices with input/output (I/O) capability. + * The I/O pins are bidirectional and bit-programmable. + * The GIO module also supports external interrupt capability. + * + * Related Files + * - reg_gio.h + * - gio.h + * - gio.c + * @addtogroup GIO + * @{ + */ + +/* GIO Interface Functions */ +void gioInit( void ); +void gioSetDirection( gioPORT_t * port, uint32 dir ); +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ); +void gioSetPort( gioPORT_t * port, uint32 value ); +uint32 gioGetBit( gioPORT_t * port, uint32 bit ); +uint32 gioGetPort( gioPORT_t * port ); +void gioToggleBit( gioPORT_t * port, uint32 bit ); +void gioEnableNotification( gioPORT_t * port, uint32 bit ); +void gioDisableNotification( gioPORT_t * port, uint32 bit ); +void gioNotification( gioPORT_t * port, uint32 bit ); +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __GIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h new file mode 100644 index 00000000000..bd58bb73688 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h @@ -0,0 +1,194 @@ +/** @file hal_stdtypes.h + * @brief HALCoGen standard types header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Type and Global definitions which are relevant for all drivers. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HAL_STDTYPES_H__ +#define __HAL_STDTYPES_H__ + +#include +#include + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ +/************************************************************/ +/* Type Definitions */ +/************************************************************/ +#ifndef _UINT64_DECLARED +typedef uint64_t uint64; + #define _UINT64_DECLARED +#endif + +#ifndef _UINT32_DECLARED +typedef uint32_t uint32; + #define _UINT32_DECLARED +#endif + +#ifndef _UINT16_DECLARED +typedef uint16_t uint16; + #define _UINT16_DECLARED +#endif + +#ifndef _UINT8_DECLARED +typedef uint8_t uint8; + #define _UINT8_DECLARED +#endif + +#ifndef _BOOLEAN_DECLARED + #ifdef __cplusplus +typedef bool boolean; + #else +typedef _Bool boolean; + #endif + #define _BOOLEAN_DECLARED +#endif + +#ifndef _SINT64_DECLARED +typedef int64_t sint64; + #define _SINT64_DECLARED +#endif + +#ifndef _SINT32_DECLARED +typedef int32_t sint32; + #define _SINT32_DECLARED +#endif + +#ifndef _SINT16_DECLARED +typedef int16_t sint16; + #define _SINT16_DECLARED +#endif + +#ifndef _SINT8_DECLARED +typedef int8_t sint8; + #define _SINT8_DECLARED +#endif + +#ifndef _FLOAT32_DECLARED +typedef float float32; + #define _FLOAT32_DECLARED +#endif + +#ifndef _FLOAT64_DECLARED +typedef double float64; + #define _FLOAT64_DECLARED +#endif + +typedef uint8 Std_ReturnType; + +typedef struct +{ + uint16 vendorID; + uint16 moduleID; + uint8 instanceID; + uint8 sw_major_version; + uint8 sw_minor_version; + uint8 sw_patch_version; +} Std_VersionInfoType; + +/*****************************************************************************/ +/* SYMBOL DEFINITIONS */ +/*****************************************************************************/ +#ifndef STATUSTYPEDEFINED + #define STATUSTYPEDEFINED + #define E_OK 0x00U + +typedef unsigned char StatusType; +#endif + +#ifndef E_NOT_OK + #define E_NOT_OK 0x01U +#endif + +#ifndef STD_ON + #define STD_ON 0x01U +#endif + +#ifndef STD_OFF + #define STD_OFF 0x00U +#endif + +/************************************************************/ +/* Global Definitions */ +/************************************************************/ + +/** @def NULL + * @brief NULL definition + */ + +#ifndef NULL + /*SAFETYMCUSW 218 S MR:20.2 "Custom Type Definition." */ + #define NULL ( ( void * ) 0U ) +#endif + +/*****************************************************************************/ +/* Define: NULL_PTR */ +/* Description: Void pointer to 0 */ +/*****************************************************************************/ +#ifndef NULL_PTR + #define NULL_PTR ( ( void * ) 0x0 ) +#endif + +/** @def TRUE + * @brief definition for TRUE + */ +#ifndef TRUE + #define TRUE true +#endif + +/** @def FALSE + * @brief BOOLEAN definition for FALSE + */ +#ifndef FALSE + #define FALSE false +#endif + +/*****************************************************************************/ +/* Define: NULL_PTR */ +/* Description: Void pointer to 0 */ +/*****************************************************************************/ +#ifndef NULL_PTR + #define NULL_PTR ( ( void * ) 0x0U ) +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* __HAL_STDTYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/het.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/het.h new file mode 100644 index 00000000000..f381d77462c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/het.h @@ -0,0 +1,600 @@ +/** @file het.h + * @brief HET Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HET_H__ +#define __HET_H__ + +#include "reg_het.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def pwm0 + * @brief Pwm signal 0 + * + * Alias for pwm signal 0 + */ +#define pwm0 0U + +/** @def pwm1 + * @brief Pwm signal 1 + * + * Alias for pwm signal 1 + */ +#define pwm1 1U + +/** @def pwm2 + * @brief Pwm signal 2 + * + * Alias for pwm signal 2 + */ +#define pwm2 2U + +/** @def pwm3 + * @brief Pwm signal 3 + * + * Alias for pwm signal 3 + */ +#define pwm3 3U + +/** @def pwm4 + * @brief Pwm signal 4 + * + * Alias for pwm signal 4 + */ +#define pwm4 4U + +/** @def pwm5 + * @brief Pwm signal 5 + * + * Alias for pwm signal 5 + */ +#define pwm5 5U + +/** @def pwm6 + * @brief Pwm signal 6 + * + * Alias for pwm signal 6 + */ +#define pwm6 6U + +/** @def pwm7 + * @brief Pwm signal 7 + * + * Alias for pwm signal 7 + */ +#define pwm7 7U + +/** @def edge0 + * @brief Edge signal 0 + * + * Alias for edge signal 0 + */ +#define edge0 0U + +/** @def edge1 + * @brief Edge signal 1 + * + * Alias for edge signal 1 + */ +#define edge1 1U + +/** @def edge2 + * @brief Edge signal 2 + * + * Alias for edge signal 2 + */ +#define edge2 2U + +/** @def edge3 + * @brief Edge signal 3 + * + * Alias for edge signal 3 + */ +#define edge3 3U + +/** @def edge4 + * @brief Edge signal 4 + * + * Alias for edge signal 4 + */ +#define edge4 4U + +/** @def edge5 + * @brief Edge signal 5 + * + * Alias for edge signal 5 + */ +#define edge5 5U + +/** @def edge6 + * @brief Edge signal 6 + * + * Alias for edge signal 6 + */ +#define edge6 6U + +/** @def edge7 + * @brief Edge signal 7 + * + * Alias for edge signal 7 + */ +#define edge7 7U + +/** @def cap0 + * @brief Capture signal 0 + * + * Alias for capture signal 0 + */ +#define cap0 0U + +/** @def cap1 + * @brief Capture signal 1 + * + * Alias for capture signal 1 + */ +#define cap1 1U + +/** @def cap2 + * @brief Capture signal 2 + * + * Alias for capture signal 2 + */ +#define cap2 2U + +/** @def cap3 + * @brief Capture signal 3 + * + * Alias for capture signal 3 + */ +#define cap3 3U + +/** @def cap4 + * @brief Capture signal 4 + * + * Alias for capture signal 4 + */ +#define cap4 4U + +/** @def cap5 + * @brief Capture signal 5 + * + * Alias for capture signal 5 + */ +#define cap5 5U + +/** @def cap6 + * @brief Capture signal 6 + * + * Alias for capture signal 6 + */ +#define cap6 6U + +/** @def cap7 + * @brief Capture signal 7 + * + * Alias for capture signal 7 + */ +#define cap7 7U + +/** @def pwmEND_OF_DUTY + * @brief Pwm end of duty + * + * Alias for pwm end of duty notification + */ +#define pwmEND_OF_DUTY 2U + +/** @def pwmEND_OF_PERIOD + * @brief Pwm end of period + * + * Alias for pwm end of period notification + */ +#define pwmEND_OF_PERIOD 4U + +/** @def pwmEND_OF_BOTH + * @brief Pwm end of duty and period + * + * Alias for pwm end of duty and period notification + */ +#define pwmEND_OF_BOTH 6U + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct hetBase + * @brief HET Register Definition + * + * This structure is used to access the HET module registers. + */ + +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +enum hetPinSelect +{ + PIN_HET_0 = 0U, + PIN_HET_1 = 1U, + PIN_HET_2 = 2U, + PIN_HET_3 = 3U, + PIN_HET_4 = 4U, + PIN_HET_5 = 5U, + PIN_HET_6 = 6U, + PIN_HET_7 = 7U, + PIN_HET_8 = 8U, + PIN_HET_9 = 9U, + PIN_HET_10 = 10U, + PIN_HET_11 = 11U, + PIN_HET_12 = 12U, + PIN_HET_13 = 13U, + PIN_HET_14 = 14U, + PIN_HET_15 = 15U, + PIN_HET_16 = 16U, + PIN_HET_17 = 17U, + PIN_HET_18 = 18U, + PIN_HET_19 = 19U, + PIN_HET_20 = 20U, + PIN_HET_21 = 21U, + PIN_HET_22 = 22U, + PIN_HET_23 = 23U, + PIN_HET_24 = 24U, + PIN_HET_25 = 25U, + PIN_HET_26 = 26U, + PIN_HET_27 = 27U, + PIN_HET_28 = 28U, + PIN_HET_29 = 29U, + PIN_HET_30 = 30U, + PIN_HET_31 = 31U +}; + +/** @struct hetSignal + * @brief HET Signal Definition + * + * This structure is used to define a pwm signal. + */ + +/** @typedef hetSIGNAL_t + * @brief HET Signal Type Definition + * + * This type is used to access HET Signal Information. + */ +typedef struct hetSignal +{ + uint32 duty; /**< Duty cycle in % of the period */ + float64 period; /**< Period in us */ +} hetSIGNAL_t; + +/* Configuration registers */ +typedef struct het_config_reg +{ + uint32 CONFIG_GCR; + uint32 CONFIG_PFR; + uint32 CONFIG_INTENAS; + uint32 CONFIG_INTENAC; + uint32 CONFIG_PRY; + uint32 CONFIG_AND; + uint32 CONFIG_HRSH; + uint32 CONFIG_XOR; + uint32 CONFIG_DIR; + uint32 CONFIG_PDR; + uint32 CONFIG_PULDIS; + uint32 CONFIG_PSL; + uint32 CONFIG_PCR; +} het_config_reg_t; + +/* Configuration registers initial value for HET1*/ +#define HET1_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET1_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_PFR_CONFIGVALUE ( ( ( uint32 ) 7U << 8U ) | ( uint32 ) 0U ) + +#define HET1_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET1_GCR_CONFIGVALUE 0x00030001U + +/* Configuration registers initial value for HET2*/ +#define HET2_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000008U \ + | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U ) + +#define HET2_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PFR_CONFIGVALUE ( ( ( uint32 ) 7U << 8U ) | ( uint32 ) 0U ) + +#define HET2_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET2_GCR_CONFIGVALUE 0x00030001U + +/** + * @defgroup HET HET + * @brief HighEnd Timer Module. + * + * The HET is a software-controlled timer with a dedicated specialized timer micromachine + *and a set of 30 instructions. The HET micromachine is connected to a port of up to 32 + *input/output (I/O) pins. + * + * Related Files + * - reg_het.h + * - het.h + * - het.c + * - reg_htu.h + * - htu.h + * - std_nhet.h + * @addtogroup HET + * @{ + */ + +/* HET Interface Functions */ +void hetInit( void ); + +/* PWM Interface Functions */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ); +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ); +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ); +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); + +/* Edge Interface Functions */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeNotification( hetBASE_t * hetREG, uint32 edge ); + +/* Captured Signal Interface Functions */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ); + +/* Timestamp Interface Functions */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ); +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ); +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void hetNotification(hetBASE_t *het, uint32 offset) + * @brief het interrupt callback + * @param[in] het - Het module base address + * - hetREG1: HET1 module base address pointer + * - hetREG2: HET2 module base address pointer + * @param[in] offset - het interrupt offset / Source number + * + * @note This function has to be provide by the user. + * + * This is a interrupt callback that is provided by the application and is call upon + * an het interrupt. The parameter passed to the callback is a copy of the interrupt + * offset register which is used to decode the interrupt source. + */ +void hetNotification( hetBASE_t * het, uint32 offset ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __HET_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/htu.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/htu.h new file mode 100644 index 00000000000..4555067f468 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/htu.h @@ -0,0 +1,69 @@ +/** @file htu.h + * @brief HTU Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HTU_H__ +#define __HTU_H__ + +#include "reg_htu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* HTU General Definitions */ + +#define HTU1PARLOC ( *( volatile uint32 * ) 0xFF4E0200U ) +#define HTU2PARLOC ( *( volatile uint32 * ) 0xFF4C0200U ) + +#define HTU1RAMLOC ( *( volatile uint32 * ) 0xFF4E0000U ) +#define HTU2RAMLOC ( *( volatile uint32 * ) 0xFF4C0000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __HTU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_emac.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_emac.h new file mode 100644 index 00000000000..66cc3ae6499 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_emac.h @@ -0,0 +1,1305 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_H_ +#define _HW_EMAC_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_BASE ( 0xFCF78000U ) +#define EMAC_CTRL_BASE ( 0xFCF78800U ) +#define EMAC_CTRL_RAM_BASE ( 0xFC520000U ) + +#define EMAC_TXREVID ( 0x0U ) +#define EMAC_TXCONTROL ( 0x4U ) +#define EMAC_TXTEARDOWN ( 0x8U ) +#define EMAC_RXREVID ( 0x10U ) +#define EMAC_RXCONTROL ( 0x14U ) +#define EMAC_RXTEARDOWN ( 0x18U ) +#define EMAC_TXINTSTATRAW ( 0x80U ) +#define EMAC_TXINTSTATMASKED ( 0x84U ) +#define EMAC_TXINTMASKSET ( 0x88U ) +#define EMAC_TXINTMASKCLEAR ( 0x8CU ) +#define EMAC_MACINVECTOR ( 0x90U ) +#define EMAC_MACEOIVECTOR ( 0x94U ) +#define EMAC_RXINTSTATRAW ( 0xA0U ) +#define EMAC_RXINTSTATMASKED ( 0xA4U ) +#define EMAC_RXINTMASKSET ( 0xA8U ) +#define EMAC_RXINTMASKCLEAR ( 0xACU ) +#define EMAC_MACINTSTATRAW ( 0xB0U ) +#define EMAC_MACINTSTATMASKED ( 0xB4U ) +#define EMAC_MACINTMASKSET ( 0xB8U ) +#define EMAC_MACINTMASKCLEAR ( 0xBCU ) +#define EMAC_RXMBPENABLE ( 0x100U ) +#define EMAC_RXUNICASTSET ( 0x104U ) +#define EMAC_RXUNICASTCLEAR ( 0x108U ) +#define EMAC_RXMAXLEN ( 0x10CU ) +#define EMAC_RXBUFFEROFFSET ( 0x110U ) +#define EMAC_RXFILTERLOWTHRESH ( 0x114U ) +#define EMAC_RXFLOWTHRESH( n ) ( ( uint32 ) 0x120U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXFREEBUFFER( n ) ( ( uint32 ) 0x140U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_MACCONTROL ( 0x160U ) +#define EMAC_MACSTATUS ( 0x164U ) +#define EMAC_EMCONTROL ( 0x168U ) +#define EMAC_FIFOCONTROL ( 0x16CU ) +#define EMAC_MACCONFIG ( 0x170U ) +#define EMAC_SOFTRESET ( 0x174U ) +#define EMAC_MACSRCADDRLO ( 0x1D0U ) +#define EMAC_MACSRCADDRHI ( 0x1D4U ) +#define EMAC_MACHASH1 ( 0x1D8U ) +#define EMAC_MACHASH2 ( 0x1DCU ) +#define EMAC_BOFFTEST ( 0x1E0U ) +#define EMAC_TPACETEST ( 0x1E4U ) +#define EMAC_RXPAUSE ( 0x1E8U ) +#define EMAC_TXPAUSE ( 0x1ECU ) +#define EMAC_RXGOODFRAMES ( 0x200U ) +#define EMAC_RXBCASTFRAMES ( 0x204U ) +#define EMAC_RXMCASTFRAMES ( 0x208U ) +#define EMAC_RXPAUSEFRAMES ( 0x20CU ) +#define EMAC_RXCRCERRORS ( 0x210U ) +#define EMAC_RXALIGNCODEERRORS ( 0x214U ) +#define EMAC_RXOVERSIZED ( 0x218U ) +#define EMAC_RXJABBER ( 0x21CU ) +#define EMAC_RXUNDERSIZED ( 0x220U ) +#define EMAC_RXFRAGMENTS ( 0x224U ) +#define EMAC_RXFILTERED ( 0x228U ) +#define EMAC_RXQOSFILTERED ( 0x22CU ) +#define EMAC_RXOCTETS ( 0x230U ) +#define EMAC_TXGOODFRAMES ( 0x234U ) +#define EMAC_TXBCASTFRAMES ( 0x238U ) +#define EMAC_TXMCASTFRAMES ( 0x23CU ) +#define EMAC_TXPAUSEFRAMES ( 0x240U ) +#define EMAC_TXDEFERRED ( 0x244U ) +#define EMAC_TXCOLLISION ( 0x248U ) +#define EMAC_TXSINGLECOLL ( 0x24CU ) +#define EMAC_TXMULTICOLL ( 0x250U ) +#define EMAC_TXEXCESSIVECOLL ( 0x254U ) +#define EMAC_TXLATECOLL ( 0x258U ) +#define EMAC_TXUNDERRUN ( 0x25CU ) +#define EMAC_TXCARRIERSENSE ( 0x260U ) +#define EMAC_TXOCTETS ( 0x264U ) +#define EMAC_FRAME64 ( 0x268U ) +#define EMAC_FRAME65T127 ( 0x26CU ) +#define EMAC_FRAME128T255 ( 0x270U ) +#define EMAC_FRAME256T511 ( 0x274U ) +#define EMAC_FRAME512T1023 ( 0x278U ) +#define EMAC_FRAME1024TUP ( 0x27CU ) +#define EMAC_NETOCTETS ( 0x208U ) +#define EMAC_RXSOFOVERRUNS ( 0x284U ) +#define EMAC_RXMOFOVERRUNS ( 0x288U ) +#define EMAC_RXDMAOVERRUNS ( 0x28CU ) +#define EMAC_MACADDRLO ( 0x500U ) +#define EMAC_MACADDRHI ( 0x504U ) +#define EMAC_MACINDEX ( 0x508U ) +#define EMAC_TXHDP( n ) ( ( uint32 ) 0x600U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXHDP( n ) ( ( uint32 ) 0x620U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_TXCP( n ) ( ( uint32 ) 0x640U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXCP( n ) ( ( uint32 ) 0x660U + ( uint32 ) ( ( n ) * 4U ) ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* TXREVID */ + +#define EMAC_TXREVID_TXREV ( 0xFFFFFFFFU ) +#define EMAC_TXREVID_TXREV_SHIFT ( 0x00000000U ) + +/* TXCONTROL */ + +#define EMAC_TXCONTROL_TXEN ( 0x00000001U ) +#define EMAC_TXCONTROL_TXEN_SHIFT ( 0x00000000U ) +#define EMAC_TXCONTROL_TXDIS ( 0x00000000U ) + +/* TXTEARDOWN */ + +#define EMAC_TXTEARDOWN_TXTDNCH ( 0x00000007U ) +#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 ( 0x00000007U ) + +/* RXREVID */ + +#define EMAC_RXREVID_RXREV ( 0xFFFFFFFFU ) +#define EMAC_RXREVID_RXREV_SHIFT ( 0x00000000U ) + +/* RXCONTROL */ + +#define EMAC_RXCONTROL_RXEN ( 0x00000001U ) +#define EMAC_RXCONTROL_RXEN_SHIFT ( 0x00000000U ) +#define EMAC_RXCONTROL_RXDIS ( 0x00000000U ) + +/* RXTEARDOWN */ + +#define EMAC_RXTEARDOWN_RXTDNCH ( 0x00000007U ) +#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 ( 0x00000007U ) + +/* TXINTSTATRAW */ + +#define EMAC_TXINTSTATRAW_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATRAW_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATRAW_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATRAW_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATRAW_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATRAW_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATRAW_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATRAW_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTSTATMASKED */ + +#define EMAC_TXINTSTATMASKED_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATMASKED_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATMASKED_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATMASKED_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATMASKED_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATMASKED_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATMASKED_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATMASKED_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTMASKSET */ + +#define EMAC_TXINTMASKSET_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKSET_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKSET_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKSET_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKSET_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKSET_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKSET_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKSET_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKSET_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKSET_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKSET_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKSET_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKSET_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKSET_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKSET_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKSET_TX0MASK_SHIFT ( 0x00000000U ) + +/* TXINTMASKCLEAR */ + +#define EMAC_TXINTMASKCLEAR_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKCLEAR_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKCLEAR_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKCLEAR_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKCLEAR_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKCLEAR_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKCLEAR_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKCLEAR_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT ( 0x00000000U ) + +/* MACINVECTOR */ + +#define EMAC_MACINVECTOR_STATPEND ( 0x08000000U ) +#define EMAC_MACINVECTOR_STATPEND_SHIFT ( 0x0000001BU ) + +#define EMAC_MACINVECTOR_HOSTPEND ( 0x04000000U ) +#define EMAC_MACINVECTOR_HOSTPEND_SHIFT ( 0x0000001AU ) + +#define EMAC_MACINVECTOR_LINKINT0 ( 0x02000000U ) +#define EMAC_MACINVECTOR_LINKINT0_SHIFT ( 0x00000019U ) + +#define EMAC_MACINVECTOR_USERINT0 ( 0x01000000U ) +#define EMAC_MACINVECTOR_USERINT0_SHIFT ( 0x00000018U ) + +#define EMAC_MACINVECTOR_TXPEND ( 0x00FF0000U ) +#define EMAC_MACINVECTOR_TXPEND_SHIFT ( 0x00000010U ) + +#define EMAC_MACINVECTOR_RXTHRESHPEND ( 0x0000FF00U ) +#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_MACINVECTOR_RXPEND ( 0x000000FFU ) +#define EMAC_MACINVECTOR_RXPEND_SHIFT ( 0x00000000U ) + +/* MACEOIVECTOR */ + +#define EMAC_MACEOIVECTOR_INTVECT ( 0x0000001FU ) +#define EMAC_MACEOIVECTOR_INTVECT_SHIFT ( 0x00000000U ) +/*----INTVECT Tokens----*/ +#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH ( 0x00000000U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0RX ( 0x00000001U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0TX ( 0x00000002U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0MISC ( 0x00000003U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH ( 0x00000004U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RX ( 0x00000005U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1TX ( 0x00000006U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1MISC ( 0x00000007U ) + +/* RXINTSTATRAW */ + +#define EMAC_RXINTSTATRAW_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATRAW_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATRAW_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATRAW_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATRAW_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATRAW_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATRAW_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATRAW_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATRAW_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATRAW_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATRAW_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATRAW_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATRAW_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATRAW_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATRAW_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATRAW_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTSTATMASKED */ + +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATMASKED_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATMASKED_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATMASKED_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATMASKED_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATMASKED_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATMASKED_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATMASKED_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATMASKED_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTMASKSET */ + +#define EMAC_RXINTMASKSET_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKSET_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKSET_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKSET_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKSET_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKSET_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKSET_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKSET_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKSET_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKSET_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKSET_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKSET_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKSET_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKSET_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKSET_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKSET_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKSET_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKSET_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKSET_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKSET_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKSET_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKSET_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKSET_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKSET_RX0MASK_SHIFT ( 0x00000000U ) + +/* RXINTMASKCLEAR */ + +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKCLEAR_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKCLEAR_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKCLEAR_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKCLEAR_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKCLEAR_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKCLEAR_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKCLEAR_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKCLEAR_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT ( 0x00000000U ) + +/* MACINTSTATRAW */ + +#define EMAC_MACINTSTATRAW_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATRAW_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATRAW_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTSTATMASKED */ + +#define EMAC_MACINTSTATMASKED_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATMASKED_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTMASKSET */ + +#define EMAC_MACINTMASKSET_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKSET_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKSET_STATMASK_SHIFT ( 0x00000000U ) + +/* MACINTMASKCLEAR */ + +#define EMAC_MACINTMASKCLEAR_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKCLEAR_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT ( 0x00000000U ) + +/* RXMBPENABLE */ + +#define EMAC_RXMBPENABLE_RXPASSCRC ( 0x40000000U ) +#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT ( 0x0000001EU ) +#define EMAC_RXMBPENABLE_RXQOSEN ( 0x20000000U ) +#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT ( 0x0000001DU ) +#define EMAC_RXMBPENABLE_RXNOCHAIN ( 0x10000000U ) +#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT ( 0x0000001CU ) +#define EMAC_RXMBPENABLE_RXCMFEN ( 0x01000000U ) +#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT ( 0x00000018U ) +#define EMAC_RXMBPENABLE_RXCSFEN ( 0x00800000U ) +#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT ( 0x00000017U ) +#define EMAC_RXMBPENABLE_RXCEFEN ( 0x00400000U ) +#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT ( 0x00000016U ) +#define EMAC_RXMBPENABLE_RXCAFEN ( 0x00200000U ) +#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT ( 0x00000015U ) +/*----RXCAFEN Tokens----*/ +#define EMAC_RXMBPENABLE_RXPROMCH ( 0x00070000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT ( 0x00000010U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXBROADEN ( 0x00002000U ) +#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT ( 0x0000000DU ) +#define EMAC_RXMBPENABLE_RXBROADCH ( 0x00000700U ) +#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT ( 0x00000008U ) +/*----RXBROADCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXMULTEN ( 0x00000020U ) +#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH ( 0x00000007U ) +#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT ( 0x00000000U ) +/*----RXMULTCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 ( 0x00000007U ) + +/* RXUNICASTSET */ + +#define EMAC_RXUNICASTSET_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTSET_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTSET_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTSET_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTSET_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXUNICASTCLEAR */ + +#define EMAC_RXUNICASTCLEAR_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXMAXLEN */ + +#define EMAC_RXMAXLEN_RXMAXLEN ( 0x0000FFFFU ) +#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT ( 0x00000000U ) + +/* RXBUFFEROFFSET */ + +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET ( 0x0000FFFFU ) +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT ( 0x00000000U ) + +/* RXFILTERLOWTHRESH */ + +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH ( 0x000000FFU ) +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FLOWTHRESH */ + +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX1FLOWTHRESH */ + +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX2FLOWTHRESH */ + +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX3FLOWTHRESH */ + +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX4FLOWTHRESH */ + +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX5FLOWTHRESH */ + +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX6FLOWTHRESH */ + +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX7FLOWTHRESH */ + +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FREEBUFFER */ + +#define EMAC_RX0FREEBUFFER_RX0FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT ( 0x00000000U ) + +/* RX1FREEBUFFER */ + +#define EMAC_RX1FREEBUFFER_RX1FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT ( 0x00000000U ) + +/* RX2FREEBUFFER */ + +#define EMAC_RX2FREEBUFFER_RX2FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT ( 0x00000000U ) + +/* RX3FREEBUFFER */ + +#define EMAC_RX3FREEBUFFER_RX3FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT ( 0x00000000U ) + +/* RX4FREEBUFFER */ + +#define EMAC_RX4FREEBUFFER_RX4FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT ( 0x00000000U ) + +/* RX5FREEBUFFER */ + +#define EMAC_RX5FREEBUFFER_RX5FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT ( 0x00000000U ) + +/* RX6FREEBUFFER */ + +#define EMAC_RX6FREEBUFFER_RX6FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT ( 0x00000000U ) + +/* RX7FREEBUFFER */ + +#define EMAC_RX7FREEBUFFER_RX7FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT ( 0x00000000U ) + +/* MACCONTROL */ + +#define EMAC_MACCONTROL_RMIISPEED ( 0x00008000U ) +#define EMAC_MACCONTROL_RMIISPEED_SHIFT ( 0x0000000FU ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK ( 0x00004000U ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT ( 0x0000000EU ) +#define EMAC_MACCONTROL_RXOWNERSHIP ( 0x00002000U ) +#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT ( 0x0000000DU ) +#define EMAC_MACCONTROL_CMDIDLE ( 0x00000800U ) +#define EMAC_MACCONTROL_CMDIDLE_SHIFT ( 0x0000000BU ) +#define EMAC_MACCONTROL_TXSHORTGAPEN ( 0x00000400U ) +#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT ( 0x0000000AU ) +#define EMAC_MACCONTROL_TXPTYPE ( 0x00000200U ) +#define EMAC_MACCONTROL_TXPTYPE_SHIFT ( 0x00000009U ) +#define EMAC_MACCONTROL_TXPACE ( 0x00000040U ) +#define EMAC_MACCONTROL_TXPACE_SHIFT ( 0x00000006U ) +#define EMAC_MACCONTROL_GMIIEN ( 0x00000020U ) +#define EMAC_MACCONTROL_GMIIEN_SHIFT ( 0x00000005U ) +#define EMAC_MACCONTROL_TXFLOWEN ( 0x00000010U ) +#define EMAC_MACCONTROL_TXFLOWEN_SHIFT ( 0x00000004U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN ( 0x00000008U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT ( 0x00000003U ) +#define EMAC_MACCONTROL_LOOPBACK ( 0x00000002U ) +#define EMAC_MACCONTROL_LOOPBACK_SHIFT ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT ( 0x00000000U ) + +/* MACSTATUS */ + +#define EMAC_MACSTATUS_IDLE ( 0x80000000U ) +#define EMAC_MACSTATUS_IDLE_SHIFT ( 0x0000001FU ) +#define EMAC_MACSTATUS_TXERRCODE ( 0x00F00000U ) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT ( 0x00000014U ) +/*----TXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_TXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCODE_SOPERROR ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCODE_NOEOP ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLPTR ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLEN ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCODE_LENERROR ( 0x00000006U ) + +#define EMAC_MACSTATUS_TXERRCH ( 0x00070000U ) +#define EMAC_MACSTATUS_TXERRCH_SHIFT ( 0x00000010U ) +/*----TXERRCH Tokens----*/ +#define EMAC_MACSTATUS_TXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_TXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXERRCODE ( 0x0000F000U ) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT ( 0x0000000CU ) +/*----RXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_RXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCODE_NULLPTR ( 0x00000004U ) + +#define EMAC_MACSTATUS_RXERRCH ( 0x00000700U ) +#define EMAC_MACSTATUS_RXERRCH_SHIFT ( 0x00000008U ) +/*----RXERRCH Tokens----*/ +#define EMAC_MACSTATUS_RXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_RXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_RXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_RXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_RXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_RXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXQOSACT ( 0x00000004U ) +#define EMAC_MACSTATUS_RXQOSACT_SHIFT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT_SHIFT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT_SHIFT ( 0x00000000U ) + +/* EMCONTROL */ + +#define EMAC_EMCONTROL_SOFT ( 0x00000002U ) +#define EMAC_EMCONTROL_SOFT_SHIFT ( 0x00000001U ) + +#define EMAC_EMCONTROL_FREE ( 0x00000001U ) +#define EMAC_EMCONTROL_FREE_SHIFT ( 0x00000000U ) + +/* FIFOCONTROL */ + +#define EMAC_FIFOCONTROL_TXCELLTHRESH ( 0x00000003U ) +#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT ( 0x00000000U ) + +/* MACCONFIG */ + +#define EMAC_MACCONFIG_TXCELLDEPTH ( 0xFF000000U ) +#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT ( 0x00000018U ) + +#define EMAC_MACCONFIG_RXCELLDEPTH ( 0x00FF0000U ) +#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT ( 0x00000010U ) + +#define EMAC_MACCONFIG_ADDRESSTYPE ( 0x0000FF00U ) +#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT ( 0x00000008U ) + +#define EMAC_MACCONFIG_MACCFIG ( 0x000000FFU ) +#define EMAC_MACCONFIG_MACCFIG_SHIFT ( 0x00000000U ) + +/* SOFTRESET */ + +#define EMAC_SOFTRESET_SOFTRESET ( 0x00000001U ) +#define EMAC_SOFTRESET_SOFTRESET_SHIFT ( 0x00000000U ) + +/* MACSRCADDRLO */ + +#define EMAC_MACSRCADDRLO_MACSRCADDR0 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1 ( 0x000000FFU ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT ( 0x00000000U ) + +/* MACSRCADDRHI */ + +#define EMAC_MACSRCADDRHI_MACSRCADDR2 ( 0xFF000000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR3 ( 0x00FF0000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR4 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR5 ( 0x000000FFU ) +#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT ( 0x00000000U ) + +/* MACHASH1 */ + +#define EMAC_MACHASH1_MACHASH1 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH1_MACHASH1_SHIFT ( 0x00000000U ) + +/* MACHASH2 */ + +#define EMAC_MACHASH2_MACHASH2 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH2_MACHASH2_SHIFT ( 0x00000000U ) + +/* BOFFTEST */ + +#define EMAC_BOFFTEST_RNDNUM ( 0x03FF0000U ) +#define EMAC_BOFFTEST_RNDNUM_SHIFT ( 0x00000010U ) + +#define EMAC_BOFFTEST_COLLCOUNT ( 0x0000F000U ) +#define EMAC_BOFFTEST_COLLCOUNT_SHIFT ( 0x0000000CU ) + +#define EMAC_BOFFTEST_TXBACKOFF ( 0x000003FFU ) +#define EMAC_BOFFTEST_TXBACKOFF_SHIFT ( 0x00000000U ) + +/* TPACETEST */ + +#define EMAC_TPACETEST_PACEVAL ( 0x0000001FU ) +#define EMAC_TPACETEST_PACEVAL_SHIFT ( 0x00000000U ) + +/* RXPAUSE */ + +#define EMAC_RXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_RXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* TXPAUSE */ + +#define EMAC_TXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_TXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* RXGOODFRAMES */ + +#define EMAC_RXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXBCASTFRAMES */ + +#define EMAC_RXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXMCASTFRAMES */ + +#define EMAC_RXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXPAUSEFRAMES */ + +#define EMAC_RXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXCRCERRORS */ + +#define EMAC_RXCRCERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXCRCERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXALIGNCODEERRORS */ + +#define EMAC_RXALIGNCODEERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXOVERSIZED */ + +#define EMAC_RXOVERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOVERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXJABBER */ + +#define EMAC_RXJABBER_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXJABBER_COUNT_SHIFT ( 0x00000000U ) + +/* RXUNDERSIZED */ + +#define EMAC_RXUNDERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXUNDERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXFRAGMENTS */ + +#define EMAC_RXFRAGMENTS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFRAGMENTS_COUNT_SHIFT ( 0x00000000U ) + +/* RXFILTERED */ + +#define EMAC_RXFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXQOSFILTERED */ + +#define EMAC_RXQOSFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXQOSFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXOCTETS */ + +#define EMAC_RXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* TXGOODFRAMES */ + +#define EMAC_TXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXBCASTFRAMES */ + +#define EMAC_TXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXMCASTFRAMES */ + +#define EMAC_TXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXPAUSEFRAMES */ + +#define EMAC_TXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXDEFERRED */ + +#define EMAC_TXDEFERRED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXDEFERRED_COUNT_SHIFT ( 0x00000000U ) + +/* TXCOLLISION */ + +#define EMAC_TXCOLLISION_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCOLLISION_COUNT_SHIFT ( 0x00000000U ) + +/* TXSINGLECOLL */ + +#define EMAC_TXSINGLECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXSINGLECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXMULTICOLL */ + +#define EMAC_TXMULTICOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMULTICOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXEXCESSIVECOLL */ + +#define EMAC_TXEXCESSIVECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXLATECOLL */ + +#define EMAC_TXLATECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXLATECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXUNDERRUN */ + +#define EMAC_TXUNDERRUN_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXUNDERRUN_COUNT_SHIFT ( 0x00000000U ) + +/* TXCARRIERSENSE */ + +#define EMAC_TXCARRIERSENSE_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCARRIERSENSE_COUNT_SHIFT ( 0x00000000U ) + +/* TXOCTETS */ + +#define EMAC_TXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME64 */ + +#define EMAC_FRAME64_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME64_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME65T127 */ + +#define EMAC_FRAME65T127_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME65T127_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME128T255 */ + +#define EMAC_FRAME128T255_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME128T255_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME256T511 */ + +#define EMAC_FRAME256T511_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME256T511_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME512T1023 */ + +#define EMAC_FRAME512T1023_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME512T1023_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME1024TUP */ + +#define EMAC_FRAME1024TUP_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME1024TUP_COUNT_SHIFT ( 0x00000000U ) + +/* NETOCTETS */ + +#define EMAC_NETOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_NETOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* RXSOFOVERRUNS */ + +#define EMAC_RXSOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXMOFOVERRUNS */ + +#define EMAC_RXMOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXDMAOVERRUNS */ + +#define EMAC_RXDMAOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* MACADDRLO */ + +#define EMAC_MACADDRLO_VALID ( 0x00100000U ) +#define EMAC_MACADDRLO_VALID_SHIFT ( 0x00000014U ) +#define EMAC_MACADDRLO_MATCHFILT ( 0x00080000U ) +#define EMAC_MACADDRLO_MATCHFILT_SHIFT ( 0x00000013U ) +#define EMAC_MACADDRLO_CHANNEL ( 0x00070000U ) +#define EMAC_MACADDRLO_CHANNEL_SHIFT ( 0x00000010U ) +#define EMAC_MACADDRLO_MACADDR0 ( 0x0000FF00U ) +#define EMAC_MACADDRLO_MACADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACADDRLO_MACADDR1 ( 0x000000FFU ) +#define EMAC_MACADDRLO_MACADDR1_SHIFT ( 0x00000000U ) + +/* MACADDRHI */ + +#define EMAC_MACADDRHI_MACADDR2 ( 0xFF000000U ) +#define EMAC_MACADDRHI_MACADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACADDRHI_MACADDR3 ( 0x00FF0000U ) +#define EMAC_MACADDRHI_MACADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACADDRHI_MACADDR4 ( 0x0000FF00U ) +#define EMAC_MACADDRHI_MACADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACADDRHI_MACADDR5 ( 0x000000FFU ) +#define EMAC_MACADDRHI_MACADDR5_SHIFT ( 0x00000000U ) + +/* MACINDEX */ + +#define EMAC_MACINDEX_MACINDEX ( 0x0000001FU ) +#define EMAC_MACINDEX_MACINDEX_SHIFT ( 0x00000000U ) + +/* TX0HDP */ + +#define EMAC_TX0HDP_TX0HDP ( 0xFFFFFFFFU ) +#define EMAC_TX0HDP_TX0HDP_SHIFT ( 0x00000000U ) + +/* TX1HDP */ + +#define EMAC_TX1HDP_TX1HDP ( 0xFFFFFFFFU ) +#define EMAC_TX1HDP_TX1HDP_SHIFT ( 0x00000000U ) + +/* TX2HDP */ + +#define EMAC_TX2HDP_TX2HDP ( 0xFFFFFFFFU ) +#define EMAC_TX2HDP_TX2HDP_SHIFT ( 0x00000000U ) + +/* TX3HDP */ + +#define EMAC_TX3HDP_TX3HDP ( 0xFFFFFFFFU ) +#define EMAC_TX3HDP_TX3HDP_SHIFT ( 0x00000000U ) + +/* TX4HDP */ + +#define EMAC_TX4HDP_TX4HDP ( 0xFFFFFFFFU ) +#define EMAC_TX4HDP_TX4HDP_SHIFT ( 0x00000000U ) + +/* TX5HDP */ + +#define EMAC_TX5HDP_TX5HDP ( 0xFFFFFFFFU ) +#define EMAC_TX5HDP_TX5HDP_SHIFT ( 0x00000000U ) + +/* TX6HDP */ + +#define EMAC_TX6HDP_TX6HDP ( 0xFFFFFFFFU ) +#define EMAC_TX6HDP_TX6HDP_SHIFT ( 0x00000000U ) + +/* TX7HDP */ + +#define EMAC_TX7HDP_TX7HDP ( 0xFFFFFFFFU ) +#define EMAC_TX7HDP_TX7HDP_SHIFT ( 0x00000000U ) + +/* RX0HDP */ + +#define EMAC_RX0HDP_RX0HDP ( 0xFFFFFFFFU ) +#define EMAC_RX0HDP_RX0HDP_SHIFT ( 0x00000000U ) + +/* RX1HDP */ + +#define EMAC_RX1HDP_RX1HDP ( 0xFFFFFFFFU ) +#define EMAC_RX1HDP_RX1HDP_SHIFT ( 0x00000000U ) + +/* RX2HDP */ + +#define EMAC_RX2HDP_RX2HDP ( 0xFFFFFFFFU ) +#define EMAC_RX2HDP_RX2HDP_SHIFT ( 0x00000000U ) + +/* RX3HDP */ + +#define EMAC_RX3HDP_RX3HDP ( 0xFFFFFFFFU ) +#define EMAC_RX3HDP_RX3HDP_SHIFT ( 0x00000000U ) + +/* RX4HDP */ + +#define EMAC_RX4HDP_RX4HDP ( 0xFFFFFFFFU ) +#define EMAC_RX4HDP_RX4HDP_SHIFT ( 0x00000000U ) + +/* RX5HDP */ + +#define EMAC_RX5HDP_RX5HDP ( 0xFFFFFFFFU ) +#define EMAC_RX5HDP_RX5HDP_SHIFT ( 0x00000000U ) + +/* RX6HDP */ + +#define EMAC_RX6HDP_RX6HDP ( 0xFFFFFFFFU ) +#define EMAC_RX6HDP_RX6HDP_SHIFT ( 0x00000000U ) + +/* RX7HDP */ + +#define EMAC_RX7HDP_RX7HDP ( 0xFFFFFFFFU ) +#define EMAC_RX7HDP_RX7HDP_SHIFT ( 0x00000000U ) + +/* TX0CP */ + +#define EMAC_TX0CP_TX0CP ( 0xFFFFFFFFU ) +#define EMAC_TX0CP_TX0CP_SHIFT ( 0x00000000U ) + +/* TX1CP */ + +#define EMAC_TX1CP_TX1CP ( 0xFFFFFFFFU ) +#define EMAC_TX1CP_TX1CP_SHIFT ( 0x00000000U ) + +/* TX2CP */ + +#define EMAC_TX2CP_TX2CP ( 0xFFFFFFFFU ) +#define EMAC_TX2CP_TX2CP_SHIFT ( 0x00000000U ) + +/* TX3CP */ + +#define EMAC_TX3CP_TX3CP ( 0xFFFFFFFFU ) +#define EMAC_TX3CP_TX3CP_SHIFT ( 0x00000000U ) + +/* TX4CP */ + +#define EMAC_TX4CP_TX4CP ( 0xFFFFFFFFU ) +#define EMAC_TX4CP_TX4CP_SHIFT ( 0x00000000U ) + +/* TX5CP */ + +#define EMAC_TX5CP_TX5CP ( 0xFFFFFFFFU ) +#define EMAC_TX5CP_TX5CP_SHIFT ( 0x00000000U ) + +/* TX6CP */ + +#define EMAC_TX6CP_TX6CP ( 0xFFFFFFFFU ) +#define EMAC_TX6CP_TX6CP_SHIFT ( 0x00000000U ) + +/* TX7CP */ + +#define EMAC_TX7CP_TX7CP ( 0xFFFFFFFFU ) +#define EMAC_TX7CP_TX7CP_SHIFT ( 0x00000000U ) + +/* RX0CP */ + +#define EMAC_RX0CP_RX0CP ( 0xFFFFFFFFU ) +#define EMAC_RX0CP_RX0CP_SHIFT ( 0x00000000U ) + +/* RX1CP */ + +#define EMAC_RX1CP_RX1CP ( 0xFFFFFFFFU ) +#define EMAC_RX1CP_RX1CP_SHIFT ( 0x00000000U ) + +/* RX2CP */ + +#define EMAC_RX2CP_RX2CP ( 0xFFFFFFFFU ) +#define EMAC_RX2CP_RX2CP_SHIFT ( 0x00000000U ) + +/* RX3CP */ + +#define EMAC_RX3CP_RX3CP ( 0xFFFFFFFFU ) +#define EMAC_RX3CP_RX3CP_SHIFT ( 0x00000000U ) + +/* RX4CP */ + +#define EMAC_RX4CP_RX4CP ( 0xFFFFFFFFU ) +#define EMAC_RX4CP_RX4CP_SHIFT ( 0x00000000U ) + +/* RX5CP */ + +#define EMAC_RX5CP_RX5CP ( 0xFFFFFFFFU ) +#define EMAC_RX5CP_RX5CP_SHIFT ( 0x00000000U ) + +/* RX6CP */ + +#define EMAC_RX6CP_RX6CP ( 0xFFFFFFFFU ) +#define EMAC_RX6CP_RX6CP_SHIFT ( 0x00000000U ) + +/* RX7CP */ + +#define EMAC_RX7CP_RX7CP ( 0xFFFFFFFFU ) +#define EMAC_RX7CP_RX7CP_SHIFT ( 0x00000000U ) + +/**@}*/ +#ifdef __cplusplus +} +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* ifndef _HW_EMAC_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h new file mode 100644 index 00000000000..3733e60c8d9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h @@ -0,0 +1,92 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_CTRL_H_ +#define _HW_EMAC_CTRL_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_CTRL_REVID ( 0x0U ) +#define EMAC_CTRL_SOFTRESET ( 0x4U ) +#define EMAC_CTRL_INTCONTROL ( 0xCU ) +#define EMAC_CTRL_C0RXTHRESHEN ( 0x10U ) +#define EMAC_CTRL_CnRXEN( n ) ( ( uint32 ) 0x14u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnTXEN( n ) ( ( uint32 ) 0x18u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnMISCEN( n ) \ + ( ( uint32 ) 0x1Cu + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnRXTHRESHEN( n ) \ + ( ( uint32 ) 0x20u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_C0RXTHRESHSTAT ( 0x40U ) +#define EMAC_CTRL_C0RXSTAT ( 0x44U ) +#define EMAC_CTRL_C0TXSTAT ( 0x48U ) +#define EMAC_CTRL_C0MISCSTAT ( 0x4CU ) +#define EMAC_CTRL_C1RXTHRESHSTAT ( 0x50U ) +#define EMAC_CTRL_C1RXSTAT ( 0x54U ) +#define EMAC_CTRL_C1TXSTAT ( 0x58U ) +#define EMAC_CTRL_C1MISCSTAT ( 0x5CU ) +#define EMAC_CTRL_C2RXTHRESHSTAT ( 0x60U ) +#define EMAC_CTRL_C2RXSTAT ( 0x64U ) +#define EMAC_CTRL_C2TXSTAT ( 0x68U ) +#define EMAC_CTRL_C2MISCSTAT ( 0x6CU ) +#define EMAC_CTRL_C0RXIMAX ( 0x70U ) +#define EMAC_CTRL_C0TXIMAX ( 0x74U ) +#define EMAC_CTRL_C1RXIMAX ( 0x78U ) +#define EMAC_CTRL_C1TXIMAX ( 0x7CU ) +#define EMAC_CTRL_C2RXIMAX ( 0x80U ) +#define EMAC_CTRL_C2TXIMAX ( 0x84U ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +#ifdef __cplusplus +} +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* ifndef _HW_EMAC_CTRL_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_mdio.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_mdio.h new file mode 100644 index 00000000000..68694680aa1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_mdio.h @@ -0,0 +1,235 @@ +/* + * hw_mdio.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_MDIO_H_ +#define _HW_MDIO_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define MDIO_BASE ( 0xFCF78900U ) + +#define MDIO_REVID ( 0x0U ) +#define MDIO_CONTROL ( 0x4U ) +#define MDIO_ALIVE ( 0x8U ) +#define MDIO_LINK ( 0xCU ) +#define MDIO_LINKINTRAW ( 0x10U ) +#define MDIO_LINKINTMASKED ( 0x14U ) +#define MDIO_USERINTRAW ( 0x20U ) +#define MDIO_USERINTMASKED ( 0x24U ) +#define MDIO_USERINTMASKSET ( 0x28U ) +#define MDIO_USERINTMASKCLEAR ( 0x2CU ) +#define MDIO_USERACCESS0 ( 0x80U ) +#define MDIO_USERPHYSEL0 ( 0x84U ) +#define MDIO_USERACCESS1 ( 0x88U ) +#define MDIO_USERPHYSEL1 ( 0x8CU ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REVID */ + +#define MDIO_REVID_REV ( 0xFFFFFFFFU ) +#define MDIO_REVID_REV_SHIFT ( 0x00000000U ) + +/* CONTROL */ + +#define MDIO_CONTROL_IDLE ( 0x80000000U ) +#define MDIO_CONTROL_IDLE_SHIFT ( 0x0000001FU ) +/*----IDLE Tokens----*/ +#define MDIO_CONTROL_IDLE_NO ( 0x00000000U ) +#define MDIO_CONTROL_IDLE_YES ( 0x00000001U ) + +#define MDIO_CONTROL_ENABLE ( 0x40000000U ) +#define MDIO_CONTROL_ENABLE_SHIFT ( 0x0000001EU ) + +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL ( 0x1F000000U ) +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT ( 0x00000018U ) + +#define MDIO_CONTROL_PREAMBLE ( 0x00100000U ) +#define MDIO_CONTROL_PREAMBLE_SHIFT ( 0x00000014U ) +/*----PREAMBLE Tokens----*/ + +#define MDIO_CONTROL_FAULT ( 0x00080000U ) +#define MDIO_CONTROL_FAULT_SHIFT ( 0x00000013U ) + +#define MDIO_CONTROL_FAULTENB ( 0x00040000U ) +#define MDIO_CONTROL_FAULTENB_SHIFT ( 0x00000012U ) +/*----FAULTENB Tokens----*/ + +#define MDIO_CONTROL_CLKDIV ( 0x0000FFFFU ) +#define MDIO_CONTROL_CLKDIV_SHIFT ( 0x00000000U ) +/*----CLKDIV Tokens----*/ + +/* ALIVE */ + +#define MDIO_ALIVE_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_ALIVE_REGVAL_SHIFT ( 0x00000000U ) + +/* LINK */ + +#define MDIO_LINK_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_LINK_REGVAL_SHIFT ( 0x00000000U ) + +/* LINKINTRAW */ + +#define MDIO_LINKINTRAW_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTRAW_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTRAW_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTRAW_USERPHY0_SHIFT ( 0x00000000U ) + +/* LINKINTMASKED */ + +#define MDIO_LINKINTMASKED_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTMASKED_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTMASKED_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTMASKED_USERPHY0_SHIFT ( 0x00000000U ) + +/* USERINTRAW */ + +#define MDIO_USERINTRAW_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTRAW_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTRAW_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTRAW_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKED */ + +#define MDIO_USERINTMASKED_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKED_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKED_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKED_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKSET */ + +#define MDIO_USERINTMASKSET_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKSET_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKCLEAR */ + +#define MDIO_USERINTMASKCLEAR_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKCLEAR_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERACCESS0 */ + +#define MDIO_USERACCESS0_GO ( 0x80000000U ) +#define MDIO_USERACCESS0_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS0_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS0_READ ( 0x00000000U ) +#define MDIO_USERACCESS0_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS0_ACK ( 0x20000000U ) +#define MDIO_USERACCESS0_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS0_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS0_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS0_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS0_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS0_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS0_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL0 */ + +#define MDIO_USERPHYSEL0_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL0_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL0_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL0_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USERACCESS1 */ + +#define MDIO_USERACCESS1_GO ( 0x80000000U ) +#define MDIO_USERACCESS1_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS1_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS1_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS1_ACK ( 0x20000000U ) +#define MDIO_USERACCESS1_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS1_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS1_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS1_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS1_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS1_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS1_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL1 */ + +#define MDIO_USERPHYSEL1_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL1_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL1_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL1_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HW_MDIO_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_reg_access.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_reg_access.h new file mode 100644 index 00000000000..f1417768169 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_reg_access.h @@ -0,0 +1,80 @@ +/* + * hw_reg_access.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_REG_ACCESS_H_ +#define _HW_REG_ACCESS_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * + * Macros for hardware access, both direct and via the bit-band region. + * + *****************************************************************************/ +#define HWREG( x ) ( *( ( volatile uint32 * ) ( x ) ) ) +#define HWREGH( x ) ( *( ( volatile uint16 * ) ( x ) ) ) +#define HWREGB( x ) ( *( ( volatile uint8 * ) ( x ) ) ) +#define HWREGBITW( x, b ) \ + ( HWREG( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITH( x, b ) \ + ( HWREGH( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITB( x, b ) \ + ( HWREGB( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HW_TYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_usb.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_usb.h new file mode 100644 index 00000000000..80febfe5bca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/hw_usb.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * + * hw_usb.h - Macros for use in accessing the USB registers. + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_USB_H__ +#define __HW_USB_H__ + +/** @brief Base address of memmory mapped Registers */ +#define USBD_0_BASE 0xFCF78A00u +#define USB0_BASE USBD_0_BASE + +typedef volatile struct +{ + uint16 rev; /* Revision */ + + /** Endpoint registers ***************************************************/ + uint16 epnum; /* Endpoint selection */ + uint16 data; /* Data */ + uint16 ctrl; /* Control */ + uint16 stat_flag; /* Status */ + uint16 rxf_stat; /* RX FIFO Status */ + uint16 syscon1; /* System configuration 1 */ + uint16 syscon2; /* System configuration 2 */ + uint16 dev_stat; /* Device status */ + uint16 sof; /* Start of frame */ + uint16 irq_en; /* Interrupt enable */ + uint16 dma_irqen; /* DMA Interrupt enable */ + uint16 irqsrc; /* Interrupt source */ + uint16 epn_stat; /* Non-ISO EP interrupt enable */ + uint16 dman_stat; /* Non-ISO DMA interrupt enable */ + uint16 _rsvd1[ 1 ]; /* Reserved for reg holes */ + + /** DMA Configuration ***************************************************/ + uint16 rxdma_cfg; /* DMA Rx channels configuration */ + uint16 txdma_cfg; /* DMA Tx channels configuration */ + uint16 data_dma; /* DMA FIFO data */ + uint16 txdma0; /* Transmit DMA control 0 */ + uint16 txdma1; /* Transmit DMA control 1 */ + uint16 txdma2; /* Transmit DMA control 2 */ + uint16 _rsvd2[ 2 ]; /* Reserved for reg holes */ + + uint16 dman_rxdma0; /* Receive DMA control 0 */ + uint16 dman_rxdma1; /* Receive DMA control 1 */ + uint16 dman_rxdma2; /* Receive DMA control 2 */ + uint16 _rsvd3[ 5 ]; /* Reserved */ + + /** Endpoint Configuration ***********************************************/ + uint16 ep0; /* Endpoint 0 Configuration */ + + uint16 epn_rx[ 15 ]; /* RX EP configurations... */ + uint16 _rsvd4[ 1 ]; /* Reserved for reg holes */ + + uint16 epn_tx[ 15 ]; /* TX EP configurations... */ +} usbdRegs; + +/******************************************************************************\ +* Register Bit Masks +* (USBD___ +\******************************************************************************/ + +/* Endpoint selection *********************************************************/ +#define USBD_EP_NUM_SETUP_SEL ( 0x0040u ) +#define USBD_EP_NUM_EP_SEL ( 0x0020u ) +#define USBD_EP_NUM_EP_DIR ( 0x0010u ) +#define USBD_EP_NUM_EP_NUM_MASK ( 0x000Fu ) + +/* Data ***********************************************************************/ +#define USBD_DATA_DATA ( 0xFFFFu ) + +/* Control ********************************************************************/ +#define USBD_CTRL_CLR_HALT ( 0x0080u ) +#define USBD_CTRL_SET_HALT ( 0x0040u ) +#define USBD_CTRL_SET_FIFO_EN ( 0x0004u ) +#define USBD_CTRL_CLR_EP ( 0x0002u ) +#define USBD_CTRL_RESET_EP ( 0x0001u ) + +/* Status *********************************************************************/ +#define USBD_STAT_FLG_NO_RXPACKET ( 0x8000u ) +#define USBD_STAT_FLG_MISS_IN ( 0x4000u ) +#define USBD_STAT_FLG_DATA_FLUSH ( 0x2000u ) +#define USBD_STAT_FLG_ISO_ERR ( 0x1000u ) +#define USBD_STAT_FLG_ISO_FIFO_EMPTY ( 0x0200u ) +#define USBD_STAT_FLG_ISO_FIFO_FULL ( 0x0100u ) +#define USBD_STAT_FLG_EP_HALTED ( 0x0040u ) +#define USBD_STAT_FLG_STALL ( 0x0020u ) +#define USBD_STAT_FLG_NAK ( 0x0010u ) +#define USBD_STAT_FLG_ACK ( 0x0008u ) +#define USBD_STAT_FLG_FIFO_EN ( 0x0004u ) +#define USBD_STAT_FLG_NON_ISO_FIFO_EMPTY ( 0x0002u ) +#define USBD_STAT_FLG_NON_ISO_FIFO_FULL ( 0x0001u ) + +/* RX FIFO Status */ +#define USBD_RXFSTAT_RXF_COUNT ( 0x03FFu ) + +/* System configuration 1 *****************************************************/ +#define USBD_SYSCON1_CFG_LOCK ( 0x0100u ) +#define USBD_SYSCON1_DATA_ENDIAN ( 0x0080u ) +#define USBD_SYSCON1_DMA_ENDIAN ( 0x0040u ) +#define USBD_SYSCON1_NAK_EN ( 0x0010u ) +#define USBD_SYSCON1_AUTODEC_DIS ( 0x0008u ) +#define USBD_SYSCON1_SELF_PWR ( 0x0004u ) +#define USBD_SYSCON1_SOFF_DIS ( 0x0002u ) +#define USBD_SYSCON1_PULLUP_EN ( 0x0001u ) + +/* System configuration 2 *****************************************************/ +#define USBD_SYSCON2_RMT_WKP ( 0x0040u ) +#define USBD_SYSCON2_STALL_CMD ( 0x0020u ) +#define USBD_SYSCON2_DEV_CFG ( 0x0008u ) +#define USBD_SYSCON2_CLR_CFG ( 0x0004u ) + +/* Device status **************************************************************/ +#define USBD_DEVSTAT_B_HNP_ENABLE ( 0x0200u ) +#define USBD_DEVSTAT_A_HNP_SUPPORT ( 0x0100u ) +#define USBD_DEVSTAT_A_ALT_HNP_SUPPORT ( 0x0080u ) +#define USBD_DEVSTAT_R_WK_OK ( 0x0040u ) +#define USBD_DEVSTAT_USB_RESET ( 0x0020u ) +#define USBD_DEVSTAT_SUS ( 0x0010u ) +#define USBD_DEVSTAT_CFG ( 0x0008u ) +#define USBD_DEVSTAT_ADD ( 0x0004u ) +#define USBD_DEVSTAT_DEF ( 0x0002u ) +#define USBD_DEVSTAT_ATT ( 0x0001u ) + +/* Start of frame *************************************************************/ +#define USBD_SOF_FT_LOCK ( 0x1000u ) +#define USBD_SOF_TS_OK ( 0x0800u ) +#define USBD_SOF_TS ( 0x07FFu ) + +/* Interrupt enable ***********************************************************/ +#define USBD_IRQ_EN_SOF_IE ( 0x0080u ) +#define USBD_IRQ_EN_EPN_RX_IE ( 0x0020u ) +#define USBD_IRQ_EN_EPN_TX_IE ( 0x0010u ) +#define USBD_IRQ_EN_DS_CHG_IE ( 0x0008u ) +#define USBD_IRQ_EN_EP0_IE ( 0x0001u ) + +/* DMA Interrupt enable *******************************************************/ +#define USBD_DMA_IRQ_EN_TX2_DONE_IE ( 0x0400u ) +#define USBD_DMA_IRQ_EN_RX2_CNT_IE ( 0x0200u ) +#define USBD_DMA_IRQ_EN_RX2_EOT_IE ( 0x0100u ) +#define USBD_DMA_IRQ_EN_TX1_DONE_IE ( 0x0040u ) +#define USBD_DMA_IRQ_EN_RX1_CNT_IE ( 0x0020u ) +#define USBD_DMA_IRQ_EN_RX1_EOT_IE ( 0x0010u ) +#define USBD_DMA_IRQ_EN_TX0_DONE_IE ( 0x0004u ) +#define USBD_DMA_IRQ_EN_RX0_CNT_IE ( 0x0002u ) +#define USBD_DMA_IRQ_EN_RX0_EOT_IE ( 0x0001u ) + +/* Interrupt source ***********************************************************/ +#define USBD_IRQ_SRC_TXN_DONE ( 0x0400u ) +#define USBD_IRQ_SRC_RXN_CNT ( 0x0200u ) +#define USBD_IRQ_SRC_RXN_EOT ( 0x0100u ) +#define USBD_IRQ_SRC_SOF ( 0x0080u ) +#define USBD_IRQ_SRC_EPN_RX ( 0x0020u ) +#define USBD_IRQ_SRC_EPN_TX ( 0x0010u ) +#define USBD_IRQ_SRC_DS_CHG ( 0x0008u ) +#define USBD_IRQ_SRC_SETUP ( 0x0004u ) +#define USBD_IRQ_SRC_EP0_RX ( 0x0002u ) +#define USBD_IRQ_SRC_EP0_TX ( 0x0001u ) + +/* Non-ISO endpoint interrupt enable ******************************************/ +#define USBD_EPN_STAT_RX_IT_SRC ( 0x0F00u ) +#define USBD_EPN_STAT_TX_IT_SRC ( 0x000Fu ) + +/* Non-ISO DMA interrupt enable ***********************************************/ +#define USBD_DMAN_STAT_RX_SB ( 0x1000u ) +#define USBD_DMAN_STAT_RX_IT_SRC ( 0x0F00u ) +#define USBD_DMAN_STAT_TX_IT_SRC ( 0x000Fu ) + +/* DMA Receive channels configuration *****************************************/ +#define USBD_RXDMA_CFG_RX_REQ ( 0x1000u ) +#define USBD_RXDMA_CFG_RXDMA2_EP ( 0x0F00u ) +#define USBD_RXDMA_CFG_RXDMA1_EP ( 0x00F0u ) +#define USBD_RXDMA_CFG_RXDMA0_EP ( 0x000Fu ) + +/* DMA Transmit channels configuration ****************************************/ +#define USBD_TXDMA_CFG_TX_REQ ( 0x1000u ) +#define USBD_TXDMA_CFG_TXDMA2_EP ( 0x0F00u ) +#define USBD_TXDMA_CFG_TXDMA1_EP ( 0x00F0u ) +#define USBD_TXDMA_CFG_TXDMA0_EP ( 0x000Fu ) + +/* DMA FIFO data **************************************************************/ +#define USBD_DATA_DMA_DATA_DMA ( 0xFFFFu ) + +/* Transmit DMA control 0 *****************************************************/ +#define USBD_TXDMA0_TX0_EOT ( 0x8000u ) +#define USBD_TXDMA0_TX0_START ( 0x4000u ) +#define USBD_TXDMA0_TX0_TSC ( 0x03FFu ) + +/* Transmit DMA control 1 *****************************************************/ +#define USBD_TXDMA1_TX1_EOT ( 0x8000u ) +#define USBD_TXDMA1_TX1_START ( 0x4000u ) +#define USBD_TXDMA1_TX1_TSC ( 0x03FFu ) +#define USBD_TXDMA1_TX1_TSC_SHIFT ( 0x0000u ) + +/* Transmit DMA control 2 *****************************************************/ +#define USBD_TXDMA2_TX2_EOT ( 0x8000u ) +#define USBD_TXDMA2_TX2_START ( 0x4000u ) +#define USBD_TXDMA2_TX2_TSC ( 0x03FFu ) + +/* Receive DMA control 0 ******************************************************/ +#define USBD_RXDMA0_RX0_STOP ( 0x8000u ) +#define USBD_RXDMA0_RX0_TC ( 0x00FFu ) + +/* Receive DMA control 1 ******************************************************/ +#define USBD_RXDMA1_RX10_STOP ( 0x8000u ) +#define USBD_RXDMA1_RX1_TC ( 0x00FFu ) + +/* Receive DMA control 2 ******************************************************/ +#define USBD_RXDMA2_RX2_STOP ( 0x8000u ) +#define USBD_RXDMA2_RX2_TC ( 0x00FFu ) + +/* Endpoint 0 Configuration ***************************************************/ +#define USBD_EP0_SIZE ( 0x3000u ) +#define USBD_EP0_PTR ( 0x07FFu ) + +/* Receive endpoint configurations... *****************************************/ +#define USBD_RX_EP_VALID ( 0x8000u ) +#define USBD_RX_EP_SIZEDB ( 0x4000u ) +#define USBD_RX_EP_SIZE ( 0x3000u ) +#define USBD_RX_EP_ISO ( 0x0800u ) +#define USBD_RX_EP_PTR ( 0x07FFu ) + +/* Transmit endpoint configurations... ****************************************/ +#define USBD_TX_EP_VALID ( 0x8000u ) +#define USBD_TX_EP_SIZEDB ( 0x4000u ) +#define USBD_TX_EP_SIZE ( 0x3000u ) +#define USBD_TX_EP_ISO ( 0x0800u ) +#define USBD_TX_EP_PTR ( 0x07FFu ) + +#define USBD_MAX_EP0_PTR ( 0xFFu ) +#define USBD_EP_RX_MAX ( 15u ) +#define USBD_EP_TX_MAX ( 15u ) + +/** @brief Macro for setting a bit/s in a register (read, modify & write) */ +#define USBD_REG_BIT_SET( reg, bit ) reg |= ( ( uint16 ) ( bit ) ) +/** @brief Macro for clearing a bit/s in a register (read, modify & write) */ +#define USBD_REG_BIT_CLR( reg, bit ) reg &= ( ( uint16 ) ~( ( uint16 ) bit ) ) +/** @brief Macro for setting a bit/s in a register (write) */ +#define USBD_REG_SET_ONE( reg, value ) reg = ( ( uint16 ) value ) + +#endif /* __HW_USB_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/i2c.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/i2c.h new file mode 100644 index 00000000000..6b987fc3b3a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/i2c.h @@ -0,0 +1,226 @@ +/** @file I2C.h + * @brief I2C Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +#include "reg_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum i2cMode + * @brief Alias names for i2c modes + * This enumeration is used to provide alias names for I2C modes: + */ + +enum i2cMode +{ + I2C_FD_FORMAT = 0x0008U, /* Free Data Format */ + I2C_START_BYTE = 0x0010U, + I2C_RESET_OUT = 0x0020U, + I2C_RESET_IN = 0x0000U, + I2C_DLOOPBACK = 0x0040U, + I2C_REPEATMODE = 0x0080U, /* In Master Mode only */ + I2C_10BIT_AMODE = 0x0100U, + I2C_7BIT_AMODE = 0x0000U, + I2C_TRANSMITTER = 0x0200U, + I2C_RECEIVER = 0x0000U, + I2C_MASTER = 0x0400U, + I2C_SLAVE = 0x0000U, + I2C_STOP_COND = 0x0800U, /* In Master Mode only */ + I2C_START_COND = 0x2000U, /* In Master Mode only */ + I2C_FREE_RUN = 0x4000U, + I2C_NACK_MODE = 0x8000U +}; + +/** @enum i2cBitCount + * @brief Alias names for i2c bit count + * This enumeration is used to provide alias names for I2C bit count: + */ + +enum i2cBitCount +{ + I2C_2_BIT = 0x2U, + I2C_3_BIT = 0x3U, + I2C_4_BIT = 0x4U, + I2C_5_BIT = 0x5U, + I2C_6_BIT = 0x6U, + I2C_7_BIT = 0x7U, + I2C_8_BIT = 0x0U +}; + +/** @enum i2cIntFlags + * @brief Interrupt Flag Definitions + * + * Used with I2CEnableNotification, I2CDisableNotification + */ +enum i2cIntFlags +{ + I2C_AL_INT = 0x0001U, /* arbitration lost */ + I2C_NACK_INT = 0x0002U, /* no acknowledgment */ + I2C_ARDY_INT = 0x0004U, /* access ready */ + I2C_RX_INT = 0x0008U, /* receive data ready */ + I2C_TX_INT = 0x0010U, /* transmit data ready */ + I2C_SCD_INT = 0x0020U, /* stop condition detect */ + I2C_AAS_INT = 0x0040U /* address as slave */ +}; + +/** @enum i2cStatFlags + * @brief Interrupt Status Definitions + * + */ +enum i2cStatFlags +{ + I2C_AL = 0x0001U, /* arbitration lost */ + I2C_NACK = 0x0002U, /* no acknowledgement */ + I2C_ARDY = 0x0004U, /* access ready */ + I2C_RX = 0x0008U, /* receive data ready */ + I2C_TX = 0x0010U, /* transmit data ready */ + I2C_SCD = 0x0020U, /* stop condition detect */ + I2C_AD0 = 0x0100U, /* address Zero Status */ + I2C_AAS = 0x0200U, /* address as slave */ + I2C_XSMT = 0x0400U, /* Transmit shift empty not */ + I2C_RXFULL = 0x0800U, /* receive full */ + I2C_BUSBUSY = 0x1000U, /* bus busy */ + I2C_NACKSNT = 0x2000U, /* No Ack Sent */ + I2C_SDIR = 0x4000U /* Slave Direction */ +}; + +/** @enum i2cDMA + * @brief I2C DMA definitions + * + * Used before i2c transfer + */ +enum i2cDMA +{ + I2C_TXDMA = 0x20U, + I2C_RXDMA = 0x10U +}; + +/* Configuration registers */ +typedef struct i2c_config_reg +{ + uint32 CONFIG_OAR; + uint32 CONFIG_IMR; + uint32 CONFIG_CLKL; + uint32 CONFIG_CLKH; + uint32 CONFIG_CNT; + uint32 CONFIG_SAR; + uint32 CONFIG_MDR; + uint32 CONFIG_EMDR; + uint32 CONFIG_PSC; + uint32 CONFIG_DMAC; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; +} i2c_config_reg_t; + +/** + * @defgroup I2C I2C + * @brief Inter-Integrated Circuit Module. + * + * The I2C is a multi-master communication module providing an interface between the + *Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor + *I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support + *any slave or master I2C compatible device. + * + * Related Files + * - reg_i2c.h + * - i2c.h + * - i2c.c + * @addtogroup I2C + * @{ + */ + +/* I2C Interface Functions */ +void i2cInit( void ); +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ); +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ); +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ); +uint32 i2cIsTxReady( i2cBASE_t * i2c ); +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ); +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ); +uint32 i2cIsRxReady( i2cBASE_t * i2c ); +uint32 i2cIsStopDetected( i2cBASE_t * i2c ); +void i2cClearSCD( i2cBASE_t * i2c ); +uint32 i2cRxError( i2cBASE_t * i2c ); +uint8 i2cReceiveByte( i2cBASE_t * i2c ); +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ); +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cSetStart( i2cBASE_t * i2c ); +void i2cSetStop( i2cBASE_t * i2c ); +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ); +void i2cEnableLoopback( i2cBASE_t * i2c ); +void i2cDisableLoopback( i2cBASE_t * i2c ); +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ); +void i2cGetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ); +bool i2cIsMasterReady( i2cBASE_t * i2c ); +bool i2cIsBusBusy( i2cBASE_t * i2c ); + +/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Interrupt callback + * @param[in] i2c - I2C module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __I2C_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/lin.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/lin.h new file mode 100644 index 00000000000..549b4c84579 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/lin.h @@ -0,0 +1,292 @@ +/** @file lin.h + * @brief LIN Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __LIN_H__ +#define __LIN_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "reg_lin.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @def LIN_BREAK_INT + * @brief Alias for break detect interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BREAK_INT 0x00000001U + +/** @def LIN_WAKEUP_INT + * @brief Alias for wakeup interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_WAKEUP_INT 0x00000002U + +/** @def LIN_TO_INT + * @brief Alias for time out interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TO_INT 0x00000010U + +/** @def LIN_TOAWUS_INT + * @brief Alias for time out after wakeup signal interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOAWUS_INT 0x00000040U + +/** @def LIN_TOA3WUS_INT + * @brief Alias for time out after 3 wakeup signals interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOA3WUS_INT 0x00000080U + +/** @def LIN_TX_READY + * @brief Alias for transmit buffer ready flag + * + * Used with linIsTxReady. + */ +#define LIN_TX_READY 0x00000100U + +/** @def LIN_RX_INT + * @brief Alias for receive buffer ready interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_RX_INT 0x00000200U + +/** @def LIN_ID_INT + * @brief Alias for received matching identifier interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ID_INT 0x00002000U + +/** @def LIN_PE_INT + * @brief Alias for parity error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PE_INT 0x01000000U + +/** @def LIN_OE_INT + * @brief Alias for overrun error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_OE_INT 0x02000000U + +/** @def LIN_FE_INT + * @brief Alias for framing error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_FE_INT 0x04000000U + +/** @def LIN_NRE_INT + * @brief Alias for no response error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_NRE_INT 0x08000000U + +/** @def LIN_ISFE_INT + * @brief Alias for inconsistent sync field error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ISFE_INT 0x10000000U + +/** @def LIN_CE_INT + * @brief Alias for checksum error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_CE_INT 0x20000000U + +/** @def LIN_PBE_INT + * @brief Alias for physical bus error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PBE_INT 0x40000000U + +/** @def LIN_BE_INT + * @brief Alias for bit error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BE_INT 0x80000000U + +/** @struct linBase + * @brief LIN Register Definition + * + * This structure is used to access the LIN module registers. + */ + +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +enum linPinSelect +{ + PIN_LIN_TX = 4U, + PIN_LIN_RX = 2U +}; + +/* Configuration registers */ +typedef struct lin_config_reg +{ + uint32 CONFIG_GCR0; + uint32 CONFIG_GCR1; + uint32 CONFIG_GCR2; + uint32 CONFIG_SETINT; + uint32 CONFIG_SETINTLVL; + uint32 CONFIG_FORMAT; + uint32 CONFIG_BRSR; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; + uint32 CONFIG_COMP; + uint32 CONFIG_MASK; + uint32 CONFIG_MBRSR; +} lin_config_reg_t; + +/* Configuration registers initial value for LIN*/ +#define LIN_GCR0_CONFIGVALUE 0x00000001U +#define LIN_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN_GCR2_CONFIGVALUE 0x00000000U +#define LIN_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN_BRSR_CONFIGVALUE ( 343U ) +#define LIN_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN_MBRSR_CONFIGVALUE ( 4954U ) +#define LIN_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/** + * @defgroup LIN LIN + * @brief Local Interconnect Network Module. + * + * The LIN standard is based on the SCI (UART) serial data link format. The communication + *concept is single-master/multiple-slave with a message identification for multi-cast + *transmission between any network nodes. + * + * Related Files + * - reg_lin.h + * - lin.h + * - lin.c + * @addtogroup LIN + * @{ + */ + +/* LIN Interface Functions */ +void linInit( void ); +void linSetFunctional( linBASE_t * lin, uint32 port ); +void linSendHeader( linBASE_t * lin, uint8 identifier ); +void linSendWakupSignal( linBASE_t * lin ); +void linEnterSleep( linBASE_t * lin ); +void linSoftwareReset( linBASE_t * lin ); +uint32 linIsTxReady( linBASE_t * lin ); +void linSetLength( linBASE_t * lin, uint32 length ); +void linSend( linBASE_t * lin, uint8 * data ); +uint32 linIsRxReady( linBASE_t * lin ); +uint32 linTxRxError( linBASE_t * lin ); +uint32 linGetIdentifier( linBASE_t * lin ); +void linGetData( linBASE_t * lin, uint8 * const data ); +void linEnableNotification( linBASE_t * lin, uint32 flags ); +void linDisableNotification( linBASE_t * lin, uint32 flags ); +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ); +void linDisableLoopback( linBASE_t * lin ); +void linGetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +uint32 linGetStatusFlag( linBASE_t * lin ); +void linClearStatusFlag( linBASE_t * lin, uint32 flags ); + +/** @fn void linNotification(linBASE_t *lin, uint32 flags) + * @brief Interrupt callback + * @param[in] lin - lin module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void linNotification( linBASE_t * lin, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __LIN_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/mdio.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/mdio.h new file mode 100644 index 00000000000..09e0e705940 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/mdio.h @@ -0,0 +1,95 @@ +/** + * \file mdio.h + * + * \brief MDIO APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MDIO_H__ +#define __MDIO_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "system.h" +#include "hw_mdio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* MDIO input and output frequencies in Hz */ +#define MDIO_FREQ_INPUT ( ( uint32 ) ( VCLK3_FREQ * 1000000.00F ) ) +#define MDIO_FREQ_OUTPUT 1000000U +/*****************************************************************************/ + +/** + * @addtogroup EMACMDIO + * @{ + */ + +/* +** Prototypes for the APIs +*/ +extern uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ); +extern uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ); +extern void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ); +extern boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ); +extern void MDIOPhyRegWrite( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + uint16 RegVal ); +extern void MDIOEnable( uint32 baseAddr ); +extern void MDIODisable( uint32 baseAddr ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __MDIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/mibspi.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/mibspi.h new file mode 100644 index 00000000000..d2b24d99e88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/mibspi.h @@ -0,0 +1,664 @@ +/** @file mibspi.h + * @brief MIBSPI Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MIBSPI_H__ +#define __MIBSPI_H__ + +#include "reg_mibspi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum triggerEvent + * @brief Transfer Group Trigger Event + */ +enum triggerEvent +{ + TRG_NEVER = 0U, + TRG_RISING = 1U, + TRG_FALLING = 2U, + TRG_BOTH = 3U, + TRG_HIGH = 5U, + TRG_LOW = 6U, + TRG_ALWAYS = 7U +}; + +/** @enum triggerSource + * @brief Transfer Group Trigger Source + */ +enum triggerSource +{ + TRG_DISABLED, + TRG_GIOA0, + TRG_GIOA1, + TRG_GIOA2, + TRG_GIOA3, + TRG_GIOA4, + TRG_GIOA5, + TRG_GIOA6, + TRG_GIOA7, + TRG_HET1_8, + TRG_HET1_10, + TRG_HET1_12, + TRG_HET1_14, + TRG_HET1_16, + TRG_HET1_18, + TRG_TICK +}; + +/** @enum mibspiPinSelect + * @brief mibspi Pin Select + */ +enum mibspiPinSelect +{ + PIN_CS0 = 0U, + PIN_CS1 = 1U, + PIN_CS2 = 2U, + PIN_CS3 = 3U, + PIN_CS4 = 4U, + PIN_CS5 = 5U, + PIN_CS6 = 6U, + PIN_CS7 = 7U, + PIN_ENA = 8U, + PIN_CLK = 9U, + PIN_SIMO = 10U, + PIN_SOMI = 11U, + PIN_SIMO_1 = 17U, + PIN_SIMO_2 = 18U, + PIN_SIMO_3 = 19U, + PIN_SIMO_4 = 20U, + PIN_SIMO_5 = 21U, + PIN_SIMO_6 = 22U, + PIN_SIMO_7 = 23U, + PIN_SOMI_1 = 25U, + PIN_SOMI_2 = 26U, + PIN_SOMI_3 = 27U, + PIN_SOMI_4 = 28U, + PIN_SOMI_5 = 29U, + PIN_SOMI_6 = 30U, + PIN_SOMI_7 = 31U +}; + +/** @enum chipSelect + * @brief Transfer Group Chip Select + */ +enum chipSelect +{ + CS_NONE = 0xFFU, + CS_0 = 0xFEU, + CS_1 = 0xFDU, + CS_2 = 0xFBU, + CS_3 = 0xF7U, + CS_4 = 0xEFU, + CS_5 = 0xDFU, + CS_6 = 0xBFU, + CS_7 = 0x7FU +}; + +/** @typedef mibspiPmode_t + * @brief Mibspi Parellel mode Type Definition + * + * This type is used to represent Mibspi Parellel mode. + */ +typedef enum mibspiPmode +{ + PMODE_NORMAL = 0x0U, + PMODE_2_DATALINE = 0x1U, + PMODE_4_DATALINE = 0x2U, + PMODE_8_DATALINE = 0x3U +} mibspiPmode_t; + +/** @typedef mibspiDFMT_t + * @brief Mibspi Data format selection Type Definition + * + * This type is used to represent Mibspi Data format selection. + */ +typedef enum mibspiDFMT +{ + DATA_FORMAT0 = 0x0U, + DATA_FORMAT1 = 0x1U, + DATA_FORMAT2 = 0x2U, + DATA_FORMAT3 = 0x3U +} mibspiDFMT_t; + +typedef struct mibspi_config_reg +{ + uint32 CONFIG_GCR1; + uint32 CONFIG_INT0; + uint32 CONFIG_LVL; + uint32 CONFIG_PCFUN; + uint32 CONFIG_PCDIR; + uint32 CONFIG_PCPDR; + uint32 CONFIG_PCDIS; + uint32 CONFIG_PCPSL; + uint32 CONFIG_DELAY; + uint32 CONFIG_FMT0; + uint32 CONFIG_FMT1; + uint32 CONFIG_FMT2; + uint32 CONFIG_FMT3; + uint32 CONFIG_MIBSPIE; + uint32 CONFIG_LTGPEND; + uint32 CONFIG_TGCTRL[ 8U ]; + uint32 CONFIG_UERRCTRL; +} mibspi_config_reg_t; + +#define MIBSPI1_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI1_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI1_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) +#define MIBSPI1_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) + +#define MIBSPI1_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI1_MIBSPIE_CONFIGVALUE 1U +#define MIBSPI1_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI1_TGCTRL0_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI1_TGCTRL1_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI1_TGCTRL2_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL3_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL4_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL5_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL6_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL7_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI1_UERRCTRL_CONFIGVALUE ( 0x00000005U ) + +#define MIBSPI3_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI3_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI3_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI3_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI3_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI3_MIBSPIE_CONFIGVALUE 1U +#define MIBSPI3_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI3_TGCTRL0_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI3_TGCTRL1_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI3_TGCTRL2_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL3_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL4_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL5_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL6_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL7_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI3_UERRCTRL_CONFIGVALUE ( 0x00000005U ) + +#define MIBSPI5_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI5_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI5_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) +#define MIBSPI5_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) + +#define MIBSPI5_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI5_MIBSPIE_CONFIGVALUE 1U +#define MIBSPI5_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI5_TGCTRL0_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI5_TGCTRL1_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI5_TGCTRL2_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL3_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL4_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL5_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL6_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL7_CONFIGVALUE \ + ( 0xFFFF7FFFU \ + & ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI5_UERRCTRL_CONFIGVALUE ( 0x00000005U ) + +/** + * @defgroup MIBSPI MIBSPI + * @brief Multi-Buffered Serial Peripheral Interface Module. + * + * The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a + * serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the + * device at a programmed bit-transfer rate. The MibSPI has a programmable buffer memory + * that enables programmed transmission to be completed without CPU intervention + * + * Related Files + * - reg_mibspi.h + * - mibspi.h + * - mibspi.c + * @addtogroup MIBSPI + * @{ + */ + +/* MIBSPI Interface Functions */ +void mibspiInit( void ); +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ); +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ); +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ); +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ); +void mibspiDisableLoopback( mibspiBASE_t * mibspi ); +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ); +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) + * @brief Error interrupt callback + * @param[in] mibspi - mibSpi module base address + * @param[in] flags - Copy of error interrupt flags + * + * This is a error callback that is provided by the application and is call upon + * an error interrupt. The paramer passed to the callback is a copy of the error + * interrupt flag register. + */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ); + +/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Transfer complete notification callback + * @param[in] mibspi - mibSpi module base address + * @param[in] group - Transfer group + * + * This is a callback function provided by the application. It is call when + * a transfer is complete. The parameter is the transfer group that triggered + * the interrupt. + */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __MIBSPI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/phy_dp83640.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/phy_dp83640.h new file mode 100644 index 00000000000..fca79c729b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/phy_dp83640.h @@ -0,0 +1,139 @@ +/* + * DP83640.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _PHY_DP83640_H_ +#define _PHY_DP83640_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Dp83640GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define DP83640_PHY_ID ( 0x0007C0F0u ) +#define DP83640_PHY_ID_REV_MASK ( 0x0000000Fu ) + +/* Pause operations */ +#define DP83640_PAUSE_NIL ( 0x0000u ) +#define DP83640_PAUSE_SYM ( 0x0400u ) +#define DP83640_PAUSE_ASYM ( 0x0800u ) +#define DP83640_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define DP83640_100BTX_HD ( 0x0000u ) +#define DP83640_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define DP83640_NO_100BTX ( 0x0000u ) +#define DP83640_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define DP83640_10BT_HD ( 0x0000u ) +#define DP83640_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define DP83640_NO_10BT ( 0x0000u ) +#define DP83640_10BT ( 0x0020u ) + +/************************************************************************** + * API function Prototypes + ***************************************************************************/ +extern uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif +#endif /* ifndef _PHY_DP83640_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/pinmux.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/pinmux.h new file mode 100644 index 00000000000..9f3f27cae48 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/pinmux.h @@ -0,0 +1,746 @@ +/** @file pinmux.h + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __PINMUX_H__ +#define __PINMUX_H__ + +#include "reg_pinmux.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PINMUX_BALL_A4_SHIFT 0U +#define PINMUX_BALL_A5_SHIFT 8U +#define PINMUX_BALL_A11_SHIFT 8U +#define PINMUX_BALL_A14_SHIFT 0U +#define PINMUX_BALL_B2_SHIFT 24U +#define PINMUX_BALL_B3_SHIFT 8U +#define PINMUX_BALL_B4_SHIFT 16U +#define PINMUX_BALL_B5_SHIFT 24U +#define PINMUX_BALL_B11_SHIFT 8U +#define PINMUX_BALL_B12_SHIFT 0U +#define PINMUX_BALL_C1_SHIFT 0U +#define PINMUX_BALL_C2_SHIFT 0U +#define PINMUX_BALL_C3_SHIFT 16U +#define PINMUX_BALL_C4_SHIFT 16U +#define PINMUX_BALL_C5_SHIFT 8U +#define PINMUX_BALL_C6_SHIFT 0U +#define PINMUX_BALL_D3_SHIFT 0U +#define PINMUX_BALL_D4_SHIFT 0U +#define PINMUX_BALL_D5_SHIFT 0U +#define PINMUX_BALL_D16_SHIFT 24U +#define PINMUX_BALL_D17_SHIFT 16U +#define PINMUX_BALL_D19_SHIFT 0U +#define PINMUX_BALL_E1_SHIFT 16U +#define PINMUX_BALL_E3_SHIFT 8U +#define PINMUX_BALL_E18_SHIFT 0U +#define PINMUX_BALL_E19_SHIFT 0U +#define PINMUX_BALL_F3_SHIFT 16U +#define PINMUX_BALL_G3_SHIFT 8U +#define PINMUX_BALL_G19_SHIFT 16U +#define PINMUX_BALL_H3_SHIFT 16U +#define PINMUX_BALL_H18_SHIFT 24U +#define PINMUX_BALL_H19_SHIFT 16U +#define PINMUX_BALL_J1_SHIFT 8U +#define PINMUX_BALL_J3_SHIFT 24U +#define PINMUX_BALL_J18_SHIFT 0U +#define PINMUX_BALL_J19_SHIFT 8U +#define PINMUX_BALL_K2_SHIFT 8U +#define PINMUX_BALL_K17_SHIFT 0U +#define PINMUX_BALL_K18_SHIFT 0U +#define PINMUX_BALL_K19_SHIFT 8U +#define PINMUX_BALL_M1_SHIFT 0U +#define PINMUX_BALL_M2_SHIFT 24U +#define PINMUX_BALL_N1_SHIFT 16U +#define PINMUX_BALL_N2_SHIFT 0U +#define PINMUX_BALL_N17_SHIFT 16U +#define PINMUX_BALL_N19_SHIFT 0U +#define PINMUX_BALL_P1_SHIFT 24U +#define PINMUX_BALL_P2_SHIFT 16U +#define PINMUX_BALL_R2_SHIFT 24U +#define PINMUX_BALL_T1_SHIFT 0U +#define PINMUX_BALL_U1_SHIFT 24U +#define PINMUX_BALL_V2_SHIFT 16U +#define PINMUX_BALL_V5_SHIFT 8U +#define PINMUX_BALL_V6_SHIFT 16U +#define PINMUX_BALL_V7_SHIFT 16U +#define PINMUX_BALL_V8_SHIFT 8U +#define PINMUX_BALL_V9_SHIFT 24U +#define PINMUX_BALL_V10_SHIFT 16U +#define PINMUX_BALL_W3_SHIFT 16U +#define PINMUX_BALL_W5_SHIFT 8U +#define PINMUX_BALL_W8_SHIFT 16U +#define PINMUX_BALL_W9_SHIFT 8U +#define PINMUX_BALL_W10_SHIFT 0U + +#define PINMUX_GATE_EMIF_CLK_SHIFT 8U +#define PINMUX_GIOB_DISABLE_HET2_SHIFT 16U +#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0U +#define PINMUX_ETHERNET_SHIFT 24U +#define PINMUX_ETPWM1_SHIFT 0U +#define PINMUX_ETPWM2_SHIFT 8U +#define PINMUX_ETPWM3_SHIFT 16U +#define PINMUX_ETPWM4_SHIFT 24U +#define PINMUX_ETPWM5_SHIFT 0U +#define PINMUX_ETPWM6_SHIFT 8U +#define PINMUX_ETPWM7_SHIFT 16U +#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT 24U +#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT 0U +#define PINMUX_TZ1_SHIFT 16U +#define PINMUX_TZ2_SHIFT 24U +#define PINMUX_TZ3_SHIFT 0U +#define PINMUX_EPWM1SYNCI_SHIFT 8U + +#define PINMUX_BALL_A4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A5_SHIFT ) ) +#define PINMUX_BALL_A11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A11_SHIFT ) ) +#define PINMUX_BALL_A14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_B2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_B4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_C1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C2_SHIFT ) ) +#define PINMUX_BALL_C3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_D3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_D16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_D19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_E1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_E3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_F3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_G3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_H3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_J1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_K2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K2_SHIFT ) ) +#define PINMUX_BALL_K17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_M1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M2_SHIFT ) ) +#define PINMUX_BALL_N1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_P1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_R2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_T1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_U1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_V2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_W3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W10_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EPWM1SYNCI_SHIFT ) ) + +#define PINMUX_BALL_A4_HET1_16 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCI \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A4_SHIFT ) ) + +#define PINMUX_BALL_A5_GIOA_0 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A5_SHIFT ) ) +#define PINMUX_BALL_A5_OHCI_PRT_RcvDpls_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A5_SHIFT ) ) +#define PINMUX_BALL_A5_W2FC_RXDPI \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A5_SHIFT ) ) + +#define PINMUX_BALL_A11_HET1_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A11_SHIFT ) ) +#define PINMUX_BALL_A11_OHCI_RCFG_txSe0_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A11_SHIFT ) ) + +#define PINMUX_BALL_A14_HET1_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_MII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_RMII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A14_SHIFT ) ) + +#define PINMUX_BALL_B2_MIBSPI3NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_I2C_SDA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_HET1_27 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_nTZ2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B2_SHIFT ) ) + +#define PINMUX_BALL_B3_HET1_22 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_B3_OHCI_RCFG_txSe0_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_B3_W2FC_SE0O \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B3_SHIFT ) ) + +#define PINMUX_BALL_B4_HET1_12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MII_CRS ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_RMII_CRS_DV \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B4_SHIFT ) ) + +#define PINMUX_BALL_B5_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_EXTCLKIN ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_ETPWM1A ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B5_SHIFT ) ) + +#define PINMUX_BALL_B11_HET1_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_MII_RX_DV \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_OHCI_RCFG_speed_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_EQEP2S ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B11_SHIFT ) ) + +#define PINMUX_BALL_B12_HET1_04 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_ETPWM4B \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B12_SHIFT ) ) + +#define PINMUX_BALL_C1_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_OHCI_RCFG_txdPls_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_W2FC_TXDO \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_HET2_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_EQEP2I ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_C1_SHIFT ) ) + +#define PINMUX_BALL_C2_GIOA_1 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C2_SHIFT ) ) +#define PINMUX_BALL_C2_OHCI_PRT_RcvDmns_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C2_SHIFT ) ) +#define PINMUX_BALL_C2_W2FC_RXDMI \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C2_SHIFT ) ) + +#define PINMUX_BALL_C3_MIBSPI3NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_I2C_SCL ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_HET1_29 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_nTZ1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_C3_SHIFT ) ) + +#define PINMUX_BALL_C4_EMIF_ADDR_6 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_HET2_11 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C4_SHIFT ) ) + +#define PINMUX_BALL_C5_EMIF_ADDR_7 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_HET2_13 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C5_SHIFT ) ) + +#define PINMUX_BALL_C6_EMIF_ADDR_8 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_HET2_15 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C6_SHIFT ) ) + +#define PINMUX_BALL_D3_SPI2NENA ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_SPI2NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D3_SHIFT ) ) + +#define PINMUX_BALL_D4_EMIF_ADDR_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D4_HET2_1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D4_SHIFT ) ) + +#define PINMUX_BALL_D5_EMIF_ADDR_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_D5_HET2_3 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D5_SHIFT ) ) + +#define PINMUX_BALL_D16_EMIF_BA_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_HET2_5 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D16_SHIFT ) ) + +#define PINMUX_BALL_D17_EMIF_nWE \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_D17_EMIF_RNW \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D17_SHIFT ) ) + +#define PINMUX_BALL_D19_HET1_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_OHCI_RCFG_txEnL_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_nTZ3 ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D19_SHIFT ) ) + +#define PINMUX_BALL_E1_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_E1_HET2_02 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E1_SHIFT ) ) + +#define PINMUX_BALL_E3_HET1_11 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_MIBSPI3NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_HET2_18 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_OHCI_PRT_OvrCurrent_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_W2FC_VBUSI \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E3_SHIFT ) ) + +#define PINMUX_BALL_E18_HET1_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MIBSPI1SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MII_TXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_OHCI_PRT_OvrCurrent_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_E18_SHIFT ) ) + +#define PINMUX_BALL_E19_MIBSPI5NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_ETPWM4A \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E19_SHIFT ) ) + +#define PINMUX_BALL_F3_MIBSPI1NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_HET1_17 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_MII_COL ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_OHCI_RCFG_suspend_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_EQEP1S ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_F3_SHIFT ) ) + +#define PINMUX_BALL_G3_MIBSPI1NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_HET1_19 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_MDIO ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G3_SHIFT ) ) + +#define PINMUX_BALL_G19_MIBSPI1NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_MII_RXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_OHCI_PRT_RcvDpls_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_ECAP4 ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G19_SHIFT ) ) + +#define PINMUX_BALL_H3_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_HET2_04 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_ETPWM1B ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H3_SHIFT ) ) + +#define PINMUX_BALL_H18_MIBSPI5NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_MII_RXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_OHCI_PRT_RcvDmns_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_MIBSPI5SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_ECAP5 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H18_SHIFT ) ) + +#define PINMUX_BALL_H19_MIBSPI5CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_MII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_RMII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_H19_SHIFT ) ) + +#define PINMUX_BALL_J1_HET1_18 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_ETPWM6A ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J1_SHIFT ) ) + +#define PINMUX_BALL_J3_MIBSPI1NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_HET1_21 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J3_SHIFT ) ) + +#define PINMUX_BALL_J18_MIBSPI5SOMI_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_MII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_RMII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J18_SHIFT ) ) + +#define PINMUX_BALL_J19_MIBSPI5SIMO_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_MII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_RMII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_MIBSPI5SOMI_2 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_J19_SHIFT ) ) + +#define PINMUX_BALL_K2_GIOB_1 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K2_SHIFT ) ) +#define PINMUX_BALL_K2_OHCI_RCFG_PrtPower_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K2_SHIFT ) ) + +#define PINMUX_BALL_K17_EMIF_nCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_HET2_09 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K17_SHIFT ) ) + +#define PINMUX_BALL_K18_HET1_0 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_SPI4CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_ETPWM2B \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K18_SHIFT ) ) + +#define PINMUX_BALL_K19_HET1_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_RMII_REFCLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_K19_SHIFT ) ) + +#define PINMUX_BALL_M1_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_HET2_06 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_ETPWM2A ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M1_SHIFT ) ) + +#define PINMUX_BALL_M2_GIOB_0 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M2_SHIFT ) ) +#define PINMUX_BALL_M2_OHCI_RCFG_txDpls_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M2_SHIFT ) ) + +#define PINMUX_BALL_N1_HET1_15 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_MIBSPI1NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_ECAP1 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N1_SHIFT ) ) + +#define PINMUX_BALL_N2_HET1_13 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_SCITX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_ETPWM5B ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N2_SHIFT ) ) + +#define PINMUX_BALL_N17_EMIF_nCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N17_SHIFT ) ) + +#define PINMUX_BALL_N19_AD1EVT ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_MII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_RMII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N19_SHIFT ) ) + +#define PINMUX_BALL_P1_HET1_24 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MIBSPI1NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_RMII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_P1_SHIFT ) ) + +#define PINMUX_BALL_P2_HET1_20 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_ETPWM6B ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P2_SHIFT ) ) + +#define PINMUX_BALL_R2_MIBSPI1NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MIBSPI1SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MII_TXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_OHCI_PRT_RcvData_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_ECAP6 ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_R2_SHIFT ) ) + +#define PINMUX_BALL_T1_HET1_07 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_OHCI_RCFG_PrtPower_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_W2FC_GZO ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_HET2_14 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_ETPWM7B ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_T1_SHIFT ) ) + +#define PINMUX_BALL_U1_HET1_03 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_SPI4NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_OHCI_RCFG_speed_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_W2FC_PUENON \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_HET2_10 ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_EQEP2B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_U1_SHIFT ) ) + +#define PINMUX_BALL_V2_HET1_01 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_SPI4NENA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_OHCI_RCFG_txEnL_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_W2FC_PUENO \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_HET2_08 ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_EQEP2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V2_SHIFT ) ) + +#define PINMUX_BALL_V5_MIBSPI3NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_HET1_25 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_MDCLK ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V5_SHIFT ) ) + +#define PINMUX_BALL_V6_HET1_05 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_SPI4SOMI ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_HET2_12 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_ETPWM3B ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V6_SHIFT ) ) + +#define PINMUX_BALL_V7_HET1_09 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_HET2_16 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_OHCI_RCFG_suspend_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_W2FC_SUSPENDO \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_ETPWM7A ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_V7_SHIFT ) ) + +#define PINMUX_BALL_V8_MIBSPI3SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_AWM_EXT_ENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_ECAP2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V8_SHIFT ) ) + +#define PINMUX_BALL_V9_MIBSPI3CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_AWM_EXT_SEL_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_EQEP1A ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V9_SHIFT ) ) + +#define PINMUX_BALL_V10_MIBSPI3NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_AD2EVT ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_EQEP1I ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V10_SHIFT ) ) + +#define PINMUX_BALL_W3_HET1_06 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_SCIRX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_ETPWM5A ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_W3_SHIFT ) ) + +#define PINMUX_BALL_W5_HET1_02 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_SPI4SIMO ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_ETPWM3A ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_W5_SHIFT ) ) + +#define PINMUX_BALL_W8_MIBSPI3SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_AWM_EXT_SEL_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_ECAP3 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_W8_SHIFT ) ) + +#define PINMUX_BALL_W9_MIBSPI3NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_MIBSPI3NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_HET1_31 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_EQEP1B ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W9_SHIFT ) ) + +#define PINMUX_BALL_W10_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_W10_OHCI_PRT_RcvData_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_W10_W2FC_RXDI \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_W10_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_ON \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_GATE_EMIF_CLK_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MII ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETHERNET_SHIFT ) ) +#define PINMUX_ETHERNET_RMII ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_ASYNC \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_SYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_FILTERED \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_EPWM1SYNCI_SHIFT ) ) + +typedef struct pinmux_config_reg +{ + uint32 CONFIG_PINMMR0; + uint32 CONFIG_PINMMR1; + uint32 CONFIG_PINMMR2; + uint32 CONFIG_PINMMR3; + uint32 CONFIG_PINMMR4; + uint32 CONFIG_PINMMR5; + uint32 CONFIG_PINMMR6; + uint32 CONFIG_PINMMR7; + uint32 CONFIG_PINMMR8; + uint32 CONFIG_PINMMR9; + uint32 CONFIG_PINMMR10; + uint32 CONFIG_PINMMR11; + uint32 CONFIG_PINMMR12; + uint32 CONFIG_PINMMR13; + uint32 CONFIG_PINMMR14; + uint32 CONFIG_PINMMR15; + uint32 CONFIG_PINMMR16; + uint32 CONFIG_PINMMR17; + uint32 CONFIG_PINMMR18; + uint32 CONFIG_PINMMR19; + uint32 CONFIG_PINMMR20; + uint32 CONFIG_PINMMR21; + uint32 CONFIG_PINMMR22; + uint32 CONFIG_PINMMR23; + uint32 CONFIG_PINMMR24; + uint32 CONFIG_PINMMR25; + uint32 CONFIG_PINMMR26; + uint32 CONFIG_PINMMR27; + uint32 CONFIG_PINMMR28; + uint32 CONFIG_PINMMR29; + uint32 CONFIG_PINMMR30; + uint32 CONFIG_PINMMR31; + uint32 CONFIG_PINMMR32; + uint32 CONFIG_PINMMR33; + uint32 CONFIG_PINMMR34; + uint32 CONFIG_PINMMR35; + uint32 CONFIG_PINMMR36; + uint32 CONFIG_PINMMR37; + uint32 CONFIG_PINMMR38; + uint32 CONFIG_PINMMR39; + uint32 CONFIG_PINMMR40; + uint32 CONFIG_PINMMR41; + uint32 CONFIG_PINMMR42; + uint32 CONFIG_PINMMR43; + uint32 CONFIG_PINMMR44; + uint32 CONFIG_PINMMR45; + uint32 CONFIG_PINMMR46; + uint32 CONFIG_PINMMR47; +} pinmux_config_reg_t; + +/** + * @defgroup IOMM IOMM + * @brief I/O Multiplexing and Control Module. + * + * The IOMM contains memory-mapped registers (MMR) that control device-specific + * multiplexed functions. The safety and diagnostic features of the IOMM are: + * - Kicker mechanism to protect the MMRs from accidental writes + * - Master-id checker to only allow the CPU to write to the MMRs + * - Error indication for access violations + * + * Related Files + * - reg_pinmux.h + * - pinmux.h + * - pinmux.c + * @addtogroup IOMM + * @{ + */ + +/** @fn void muxInit(void) + * @brief Initializes the PINMUX Driver + * + * This function initializes the PINMUX module and configures the selected + * pinmux settings as per the user selection in the GUI + */ +void muxInit( void ); +void pinmuxGetConfigValue( pinmux_config_reg_t * config_reg, config_value_type_t type ); +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ +#endif /* ifndef __PINMUX_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/pom.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/pom.h new file mode 100644 index 00000000000..72adb4df8cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/pom.h @@ -0,0 +1,238 @@ +/** @file pom.h + * @brief POM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __POM_H__ +#define __POM_H__ + +#include "reg_pom.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pom_region_size + * @brief Alias names for pom region size + * This enumeration is used to provide alias names for POM region size: + */ +enum pom_region_size +{ + SIZE_32BYTES = 0U, + SIZE_64BYTES = 1U, + SIZE_128BYTES = 2U, + SIZE_256BYTES = 3U, + SIZE_512BYTES = 4U, + SIZE_1KB = 5U, + SIZE_2KB = 6U, + SIZE_4KB = 7U, + SIZE_8KB = 8U, + SIZE_16KB = 9U, + SIZE_32KB = 10U, + SIZE_64KB = 11U, + SIZE_128KB = 12U, + SIZE_256KB = 13U +}; + +/** @def INTERNAL_RAM + * @brief Alias name for Internal RAM + */ +#define INTERNAL_RAM 0x08000000U + +/** @def SDRAM + * @brief Alias name for SD RAM + */ +#define SDRAM 0x80000000U + +/** @def ASYNC_MEMORY + * @brief Alias name for Async RAM + */ +#define ASYNC_MEMORY 0x60000000U + +typedef uint32 REGION_t; + +/** @struct REGION_CONFIG_ST + * @brief POM region configuration + */ +typedef struct +{ + uint32 Prog_Reg_Sta_Addr; + uint32 Ovly_Reg_Sta_Addr; + uint32 Reg_Size; +} REGION_CONFIG_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct pom_config_reg +{ + uint32 CONFIG_POMGLBCTRL; + uint32 CONFIG_POMPROGSTART0; + uint32 CONFIG_POMOVLSTART0; + uint32 CONFIG_POMREGSIZE0; + uint32 CONFIG_POMPROGSTART1; + uint32 CONFIG_POMOVLSTART1; + uint32 CONFIG_POMREGSIZE1; + uint32 CONFIG_POMPROGSTART2; + uint32 CONFIG_POMOVLSTART2; + uint32 CONFIG_POMREGSIZE2; + uint32 CONFIG_POMPROGSTART3; + uint32 CONFIG_POMOVLSTART3; + uint32 CONFIG_POMREGSIZE3; + uint32 CONFIG_POMPROGSTART4; + uint32 CONFIG_POMOVLSTART4; + uint32 CONFIG_POMREGSIZE4; + uint32 CONFIG_POMPROGSTART5; + uint32 CONFIG_POMOVLSTART5; + uint32 CONFIG_POMREGSIZE5; + uint32 CONFIG_POMPROGSTART6; + uint32 CONFIG_POMOVLSTART6; + uint32 CONFIG_POMREGSIZE6; + uint32 CONFIG_POMPROGSTART7; + uint32 CONFIG_POMOVLSTART7; + uint32 CONFIG_POMREGSIZE7; + uint32 CONFIG_POMPROGSTART8; + uint32 CONFIG_POMOVLSTART8; + uint32 CONFIG_POMREGSIZE8; + uint32 CONFIG_POMPROGSTART9; + uint32 CONFIG_POMOVLSTART9; + uint32 CONFIG_POMREGSIZE9; + uint32 CONFIG_POMPROGSTART10; + uint32 CONFIG_POMOVLSTART10; + uint32 CONFIG_POMREGSIZE10; + uint32 CONFIG_POMPROGSTART11; + uint32 CONFIG_POMOVLSTART11; + uint32 CONFIG_POMREGSIZE11; + uint32 CONFIG_POMPROGSTART12; + uint32 CONFIG_POMOVLSTART12; + uint32 CONFIG_POMREGSIZE12; + uint32 CONFIG_POMPROGSTART13; + uint32 CONFIG_POMOVLSTART13; + uint32 CONFIG_POMREGSIZE13; + uint32 CONFIG_POMPROGSTART14; + uint32 CONFIG_POMOVLSTART14; + uint32 CONFIG_POMREGSIZE14; + uint32 CONFIG_POMPROGSTART15; + uint32 CONFIG_POMOVLSTART15; + uint32 CONFIG_POMREGSIZE15; + uint32 CONFIG_POMPROGSTART16; + uint32 CONFIG_POMOVLSTART16; + uint32 CONFIG_POMREGSIZE16; + uint32 CONFIG_POMPROGSTART17; + uint32 CONFIG_POMOVLSTART17; + uint32 CONFIG_POMREGSIZE17; + uint32 CONFIG_POMPROGSTART18; + uint32 CONFIG_POMOVLSTART18; + uint32 CONFIG_POMREGSIZE18; + uint32 CONFIG_POMPROGSTART19; + uint32 CONFIG_POMOVLSTART19; + uint32 CONFIG_POMREGSIZE19; + uint32 CONFIG_POMPROGSTART20; + uint32 CONFIG_POMOVLSTART20; + uint32 CONFIG_POMREGSIZE20; + uint32 CONFIG_POMPROGSTART21; + uint32 CONFIG_POMOVLSTART21; + uint32 CONFIG_POMREGSIZE21; + uint32 CONFIG_POMPROGSTART22; + uint32 CONFIG_POMOVLSTART22; + uint32 CONFIG_POMREGSIZE22; + uint32 CONFIG_POMPROGSTART23; + uint32 CONFIG_POMOVLSTART23; + uint32 CONFIG_POMREGSIZE23; + uint32 CONFIG_POMPROGSTART24; + uint32 CONFIG_POMOVLSTART24; + uint32 CONFIG_POMREGSIZE24; + uint32 CONFIG_POMPROGSTART25; + uint32 CONFIG_POMOVLSTART25; + uint32 CONFIG_POMREGSIZE25; + uint32 CONFIG_POMPROGSTART26; + uint32 CONFIG_POMOVLSTART26; + uint32 CONFIG_POMREGSIZE26; + uint32 CONFIG_POMPROGSTART27; + uint32 CONFIG_POMOVLSTART27; + uint32 CONFIG_POMREGSIZE27; + uint32 CONFIG_POMPROGSTART28; + uint32 CONFIG_POMOVLSTART28; + uint32 CONFIG_POMREGSIZE28; + uint32 CONFIG_POMPROGSTART29; + uint32 CONFIG_POMOVLSTART29; + uint32 CONFIG_POMREGSIZE29; + uint32 CONFIG_POMPROGSTART30; + uint32 CONFIG_POMOVLSTART30; + uint32 CONFIG_POMREGSIZE30; + uint32 CONFIG_POMPROGSTART31; + uint32 CONFIG_POMOVLSTART31; + uint32 CONFIG_POMREGSIZE31; +} pom_config_reg_t; + +/** + * @defgroup POM POM + * @brief Parameter Overlay Module. + * + * The POM provides a mechanism to redirect accesses to non-volatile memory into a + * volatile memory internal or external to the device. The data requested by the CPU will + * be fetched from the overlay memory instead of the main non-volatile memory. + * + * Related Files + * - reg_pom.h + * - pom.h + * - pom.c + * @addtogroup POM + * @{ + */ + +/* POM Interface Functions */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ); +void POM_Reset( void ); +void POM_Init( void ); +void POM_Enable( void ); +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ +#endif /* __POM_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_adc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_adc.h new file mode 100644 index 00000000000..a42f6748fa5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_adc.h @@ -0,0 +1,263 @@ +/** @file reg_adc.h + * @brief ADC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ADC_H__ +#define __REG_ADC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Adc Register Frame Definition */ + +/** @struct adcBase + * @brief ADC Register Frame Definition + * + * This type is used to access the ADC Registers. + */ + +/** @typedef adcBASE_t + * @brief ADC Register Frame Type Definition + * + * This type is used to access the ADC Registers. + */ +typedef volatile struct adcBase +{ + uint32 RSTCR; /**< 0x0000: Reset control register */ + uint32 OPMODECR; /**< 0x0004: Operating mode control register */ + uint32 CLOCKCR; /**< 0x0008: Clock control register */ + uint32 CALCR; /**< 0x000C: Calibration control register */ + uint32 GxMODECR[ 3U ]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */ + uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */ + uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */ + uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */ + uint32 GxINTENA[ 3U ]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register + */ + uint32 GxINTFLG[ 3U ]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */ + uint32 GxINTCR[ 3U ]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */ + uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */ + uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */ + uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */ + uint32 BNDCR; /**< 0x0058: Buffer boundary control register */ + uint32 BNDEND; /**< 0x005C: Buffer boundary end register */ + uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */ + uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */ + uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */ + uint32 EVSR; /**< 0x006C: Group 0 status register */ + uint32 G1SR; /**< 0x0070: Group 1 status register */ + uint32 G2SR; /**< 0x0074: Group 2 status register */ + uint32 GxSEL[ 3U ]; /**< 0x0078-0x007C: Group 0-2 channel select register */ + uint32 CALR; /**< 0x0084: Calibration register */ + uint32 SMSTATE; /**< 0x0088: State machine state register */ + uint32 LASTCONV; /**< 0x008C: Last conversion register */ + struct + { + uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */ + uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */ + uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */ + uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */ + uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */ + uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */ + uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */ + uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */ + } GxBUF[ 3U ]; + uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */ + uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */ + uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */ + uint32 EVTDIR; /**< 0x00FC: Event pin direction register */ + uint32 EVTOUT; /**< 0x0100: Event pin digital output register */ + uint32 EVTIN; /**< 0x0104: Event pin digital input register */ + uint32 EVTSET; /**< 0x0108: Event pin set register */ + uint32 EVTCLR; /**< 0x010C: Event pin clear register */ + uint32 EVTPDR; /**< 0x0110: Event pin open drain register */ + uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */ + uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */ + uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */ + uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */ + uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */ + uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */ + uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */ + uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */ + uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */ + uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */ + uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */ + uint32 rsvd1; /**< 0x0140: Reserved */ + uint32 rsvd2; /**< 0x0144: Reserved */ + uint32 rsvd3; /**< 0x0148: Reserved */ + uint32 rsvd4; /**< 0x014C: Reserved */ + uint32 rsvd5; /**< 0x0150: Reserved */ + uint32 rsvd6; /**< 0x0154: Reserved */ + uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */ + uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */ + uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */ + uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */ + uint32 GxFIFORESETCR[ 3U ]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register + */ + uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */ + uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */ + uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */ + uint32 PARCR; /**< 0x0180: Parity control register */ + uint32 PARADDR; /**< 0x0184: Parity error address register */ + uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */ + uint32 rsvd7; /**< 0x018C: Reserved */ + uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control + Register */ + uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register + */ + uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register + */ + uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */ + uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */ + uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */ + uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */ + uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */ + uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */ +} adcBASE_t; + +/** @struct adcLUTEntry + * @brief ADC Look-Up Table Entry + * + * This type is used to access ADC Look-Up Table Entry + */ + +/** @typedef adcLUTEntry_t + * @brief ADC Look-Up Table Entry + * + * This type is used to access the Look-Up Table Entry. + */ +typedef struct adcLUTEntry +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 EV_INT_CHN_MUX_SEL; + uint8 EV_EXT_CHN_MUX_SEL; + uint16 rsvd; +#else + uint16 rsvd; + uint8 EV_EXT_CHN_MUX_SEL; + uint8 EV_INT_CHN_MUX_SEL; +#endif +} adcLUTEntry_t; + +/** @struct adcLUT + * @brief ADC Look-Up Table + * + * This type is used to access ADC Look-Up Table + */ + +/** @typedef adcLUT_t + * @brief ADC Look-Up Table + * + * This type is used to access the ADC Look-Up Table. + */ +typedef volatile struct adcLUT +{ + adcLUTEntry_t eventGroup[ 32 ]; + adcLUTEntry_t Group1[ 32 ]; + adcLUTEntry_t Group2[ 32 ]; +} adcLUT_t; + +/** @def adcREG1 + * @brief ADC1 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC1 registers. + */ +#define adcREG1 ( ( adcBASE_t * ) 0xFFF7C000U ) + +/** @def adcREG2 + * @brief ADC2 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC2 registers. + */ +#define adcREG2 ( ( adcBASE_t * ) 0xFFF7C200U ) + +/** @def adcRAM1 + * @brief ADC1 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 RAM. + */ +#define adcRAM1 ( *( volatile uint32 * ) 0xFF3E0000U ) + +/** @def adcRAM2 + * @brief ADC2 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 RAM. + */ +#define adcRAM2 ( *( volatile uint32 * ) 0xFF3A0000U ) + +/** @def adcPARRAM1 + * @brief ADC1 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 Parity RAM. + */ +#define adcPARRAM1 ( *( volatile uint32 * ) ( 0xFF3E0000U + 0x1000U ) ) + +/** @def adcPARRAM2 + * @brief ADC2 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 Parity RAM. + */ +#define adcPARRAM2 ( *( volatile uint32 * ) ( 0xFF3A0000U + 0x1000U ) ) + +/** @def adcLUT1 + * @brief ADC1 Look-Up Table + * + * This pointer is used by the ADC driver to access the ADC1 Look-Up Table. + */ +#define adcLUT1 ( ( adcLUT_t * ) 0xFF3E2000U ) + +/** @def adcLUT2 + * @brief ADC2 Look-Up Table + * + * This pointer is used by the ADC driver to access the ADC2 Look-Up Table. + */ +#define adcLUT2 ( ( adcLUT_t * ) 0xFF3A2000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_ADC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_can.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_can.h new file mode 100644 index 00000000000..2fcffcf10fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_can.h @@ -0,0 +1,205 @@ +/** @file reg_can.h + * @brief CAN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CAN_H__ +#define __REG_CAN_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Can Register Frame Definition */ + +/** @struct canBase + * @brief CAN Register Frame Definition + * + * This type is used to access the CAN Registers. + */ + +/** @typedef canBASE_t + * @brief CAN Register Frame Type Definition + * + * This type is used to access the CAN Registers. + */ +typedef volatile struct canBase +{ + uint32 CTL; /**< 0x0000: Control Register */ + uint32 ES; /**< 0x0004: Error and Status Register */ + uint32 EERC; /**< 0x0008: Error Counter Register */ + uint32 BTR; /**< 0x000C: Bit Timing Register */ + uint32 INT; /**< 0x0010: Interrupt Register */ + uint32 TEST; /**< 0x0014: Test Register */ + uint32 rsvd1; /**< 0x0018: Reserved */ + uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */ + uint32 rsvd2[ 24 ]; /**< 0x002C - 0x7C: Reserved */ + uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */ + uint32 TXRQX; /**< 0x0084: Transmission Request X Register */ + uint32 TXRQx[ 4U ]; /**< 0x0088-0x0094: Transmission Request Registers */ + uint32 NWDATX; /**< 0x0098: New Data X Register */ + uint32 NWDATx[ 4U ]; /**< 0x009C-0x00A8: New Data Registers */ + uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */ + uint32 INTPNDx[ 4U ]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */ + uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */ + uint32 MSGVALx[ 4U ]; /**< 0x00C4-0x00D0: Message Valid Registers */ + uint32 rsvd3; /**< 0x00D4: Reserved */ + uint32 INTMUXx[ 4U ]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */ + uint32 rsvd4[ 6 ]; /**< 0x00E8: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ +#else + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ +#endif + uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */ + uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */ + uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */ + uint8 IF1DATx[ 8U ]; /**< 0x0110-0x0114: IF1 Data A and B Registers */ + uint32 rsvd5[ 2 ]; /**< 0x0118: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ +#else + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */ +#endif + uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */ + uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */ + uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */ + uint8 IF2DATx[ 8U ]; /**< 0x0130-0x0134: IF2 Data A and B Registers */ + uint32 rsvd6[ 2 ]; /**< 0x0138: Reserved */ + uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */ + uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */ + uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */ + uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */ + uint8 IF3DATx[ 8U ]; /**< 0x0150-0x0154: IF3 Data A and B Registers */ + uint32 rsvd7[ 2 ]; /**< 0x0158: Reserved */ + uint32 IF3UEy[ 4U ]; /**< 0x0160-0x016C: IF3 Update Enable Registers */ + uint32 rsvd8[ 28 ]; /**< 0x0170: Reserved */ + uint32 TIOC; /**< 0x01E0: TX IO Control Register */ + uint32 RIOC; /**< 0x01E4: RX IO Control Register */ +} canBASE_t; + +/** @def canREG1 + * @brief CAN1 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN1 registers. + */ +#define canREG1 ( ( canBASE_t * ) 0xFFF7DC00U ) + +/** @def canREG2 + * @brief CAN2 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN2 registers. + */ +#define canREG2 ( ( canBASE_t * ) 0xFFF7DE00U ) + +/** @def canREG3 + * @brief CAN3 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN3 registers. + */ +#define canREG3 ( ( canBASE_t * ) 0xFFF7E000U ) + +/** @def canRAM1 + * @brief CAN1 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 RAM. + */ +#define canRAM1 ( *( volatile uint32 * ) 0xFF1E0000U ) + +/** @def canRAM2 + * @brief CAN2 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 RAM. + */ +#define canRAM2 ( *( volatile uint32 * ) 0xFF1C0000U ) + +/** @def canRAM3 + * @brief CAN3 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 RAM. + */ +#define canRAM3 ( *( volatile uint32 * ) 0xFF1A0000U ) + +/** @def canPARRAM1 + * @brief CAN1 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM1 ( *( volatile uint32 * ) ( 0xFF1E0000U + 0x10U ) ) + +/** @def canPARRAM2 + * @brief CAN2 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM2 ( *( volatile uint32 * ) ( 0xFF1C0000U + 0x10U ) ) + +/** @def canPARRAM3 + * @brief CAN3 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM3 ( *( volatile uint32 * ) ( 0xFF1A0000U + 0x10U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_CAN_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_crc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_crc.h new file mode 100644 index 00000000000..6dd20a2b2a8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_crc.h @@ -0,0 +1,127 @@ +/** @file reg_crc.h + * @brief CRC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CRC_H__ +#define __REG_CRC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Crc Register Frame Definition */ + +/** @struct crcBase + * @brief CRC Register Frame Definition + * + * This type is used to access the CRC Registers. + */ + +/** @typedef crcBASE_t + * @brief CRC Register Frame Type Definition + * + * This type is used to access the CRC Registers. + */ +typedef volatile struct crcBase +{ + uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/ + uint32 rvd1; /**< 0x0004: reserved >**/ + uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/ + uint32 rvd2; /**< 0x000C: reserved >**/ + uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/ + uint32 rvd3; /**< 0x0014: reserved >**/ + uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/ + uint32 rvd4; /**< 0x001C: reserved >**/ + uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/ + uint32 rvd5; /**< 0x0024: reserved >**/ + uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/ + uint32 rvd6; /**< 0x002C: reserved >**/ + uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/ + uint32 rvd7; /**< 0x0034: reserved >**/ + uint32 BUSY; /**< 0x0038: CRC Busy Register >**/ + uint32 rvd8; /**< 0x003C: reserved >**/ + uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/ + uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/ + uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/ + uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/ + uint32 rvd9[ 3 ]; /**< 0x0054: reserved >**/ + uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/ + uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/ + uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/ + uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/ + uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/ + uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/ + uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/ + uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/ + uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/ + uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/ + uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/ + uint32 rvd10[ 3 ]; /**< 0x0094: reserved >**/ + uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/ + uint32 PSA_SIGREGH2; /**< 0x00A4: Channel 2 PSA signature high register >**/ + uint32 REGL2; /**< 0x00A8: Channel 2 CRC value low register >**/ + uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/ + uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/ + uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/ + uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/ +} crcBASE_t; + +/** @def crcREG + * @brief CRC Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC registers. + */ +#define crcREG ( ( crcBASE_t * ) 0xFE000000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_CRC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_dcc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_dcc.h new file mode 100644 index 00000000000..b7a8cc61ff9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_dcc.h @@ -0,0 +1,101 @@ +/** @file reg_dcc.h + * @brief DCC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DCC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DCC_H__ +#define __REG_DCC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dcc Register Frame Definition */ + +/** @struct dccBase + * @brief DCC Base Register Definition + * + * This structure is used to access the DCC module registers. + */ + +/** @typedef dccBASE_t + * @brief DCC Register Frame Type Definition + * + * This type is used to access the DCC Registers. + */ +typedef volatile struct dccBase +{ + uint32 GCTRL; /**< 0x0000: DCC Control Register */ + uint32 REV; /**< 0x0004: DCC Revision Id Register */ + uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */ + uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */ + uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */ + uint32 STAT; /**< 0x0014: DCC Status Register */ + uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */ + uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */ + uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */ + uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */ + uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */ +} dccBASE_t; + +/** @def dccREG1 + * @brief DCC1 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U ) + +/** @def dccREG2 + * @brief DCC2 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG2 ( ( dccBASE_t * ) 0xFFFFF400U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_DCC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_dma.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_dma.h new file mode 100644 index 00000000000..16f6861a51e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_dma.h @@ -0,0 +1,186 @@ +/** @file reg_dma.h + * @brief DMA Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMA_H__ +#define __REG_DMA_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DMA Register Frame Definition */ + +/** @struct dmaBase + * @brief DMA Register Frame Definition + * + * This type is used to access the DMA Registers. + */ + +/** @struct dmaBASE_t + * @brief DMA Register Definition + * + * This structure is used to access the DMA module egisters. + */ +typedef volatile struct dmaBase +{ + uint32 GCTRL; /**< 0x0000: Global Control Register */ + uint32 PEND; /**< 0x0004: Channel Pending Register */ + uint32 FBREG; /**< 0x0008: Fall Back Register */ + uint32 DMASTAT; /**< 0x000C: Status Register */ + uint32 rsvd1; /**< 0x0010: Reserved */ + uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */ + uint32 rsvd2; /**< 0x0018: Reserved */ + uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */ + uint32 rsvd3; /**< 0x0020: Reserved */ + uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */ + uint32 rsvd4; /**< 0x0028: Reserved */ + uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */ + uint32 rsvd5; /**< 0x0030: Reserved */ + uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */ + uint32 rsvd6; /**< 0x0038: Reserved */ + uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */ + uint32 rsvd7; /**< 0x0040: Reserved */ + uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */ + uint32 rsvd8; /**< 0x0048: Reserved */ + uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Reset */ + uint32 rsvd9; /**< 0x0050: Reserved */ + uint32 DREQASI[ 8U ]; /**< 0x0054 - 0x70: DMA Request Assignment Register */ + uint32 rsvd10[ 8U ]; /**< 0x0074 - 0x90: Reserved */ + uint32 PAR[ 4U ]; /**< 0x0094 - 0xA0: Port Assignment Register */ + uint32 rsvd11[ 4U ]; /**< 0x00A4 - 0xB0: Reserved */ + uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */ + uint32 rsvd12; /**< 0x00B8: Reserved */ + uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */ + uint32 rsvd13; /**< 0x00C0: Reserved */ + uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */ + uint32 rsvd14; /**< 0x00C8: Reserved */ + uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */ + uint32 rsvd15; /**< 0x00D0: Reserved */ + uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */ + uint32 rsvd16; /**< 0x00D8: Reserved */ + uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */ + uint32 rsvd17; /**< 0x00E0: Reserved */ + uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */ + uint32 rsvd18; /**< 0x00E8: Reserved */ + uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */ + uint32 rsvd19; /**< 0x00F0: Reserved */ + uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */ + uint32 rsvd20; /**< 0x00F8: Reserved */ + uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */ + uint32 rsvd21; /**< 0x0100: Reserved */ + uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */ + uint32 rsvd22; /**< 0x0108: Reserved */ + uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */ + uint32 rsvd23; /**< 0x0110: Reserved */ + uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */ + uint32 rsvd24; /**< 0x0118: Reserved */ + uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */ + uint32 rsvd25; /**< 0x0120: Reserved */ + uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */ + uint32 rsvd26; /**< 0x0128: Reserved */ + uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */ + uint32 rsvd27; /**< 0x0130: Reserved */ + uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */ + uint32 rsvd28; /**< 0x0138: Reserved */ + uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */ + uint32 rsvd29; /**< 0x0140: Reserved */ + uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */ + uint32 rsvd30; /**< 0x0148: Reserved */ + uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */ + uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */ + uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */ + uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */ + uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */ + uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */ + uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */ + uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */ + uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */ + uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */ + uint32 rsvd31; /**< 0x0174: Reserved */ + uint32 PTCRL; /**< 0x0178: Port Control Register */ + uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */ + uint32 DCTRL; /**< 0x0180: Debug Control */ + uint32 WPR; /**< 0x0184: Watch Point Register */ + uint32 WMR; /**< 0x0188: Watch Mask Register */ + uint32 PAACSADDR; /**< 0x018C: */ + uint32 PAACDADDR; /**< 0x0190: */ + uint32 PAACTC; /**< 0x0194: */ + uint32 PBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */ + uint32 PBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */ + uint32 PBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */ + uint32 rsvd32; /**< 0x01A4: Reserved */ + uint32 DMAPCR; /**< 0x01A8: Parity Control Register */ + uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */ + uint32 DMAMPCTRL; /**< 0x01B0: DMA Memory Protection Control Register */ + uint32 DMAMPST; /**< 0x01B4: DMA Memory Protection Status Register */ + struct + { + uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + } DMAMPR[ 4U ]; +} dmaBASE_t; + +/** @def dmaREG + * @brief DMA1 Register Frame Pointer + * + * This pointer is used by the DMA driver to access the DMA module registers. + */ +#define dmaREG ( ( dmaBASE_t * ) 0xFFFFF000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __REG_DMA_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_ecap.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_ecap.h new file mode 100644 index 00000000000..9a7e25eac9c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_ecap.h @@ -0,0 +1,156 @@ +/** @file reg_ecap.h + * @brief ECAP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ECAP_H__ +#define __REG_ECAP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Ecap Register Frame Definition */ + +/** @struct ecapBASE + * @brief ECAP Register Frame Definition + * + * This type is used to access the ECAP Registers. + */ + +/** @typedef ecapBASE_t + * @brief ECAP Register Frame Type Definition + * + * This type is used to access the ECAP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ +} ecapBASE_t; + +#else /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ +} ecapBASE_t; + +#endif /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + +/** @def ecapREG1 + * @brief ECAP1 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP1 registers. + */ +#define ecapREG1 ( ( ecapBASE_t * ) 0xFCF79300U ) + +/** @def ecapREG2 + * @brief ECAP2 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP2 registers. + */ +#define ecapREG2 ( ( ecapBASE_t * ) 0xFCF79400U ) + +/** @def ecapREG3 + * @brief ECAP3 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP3 registers. + */ +#define ecapREG3 ( ( ecapBASE_t * ) 0xFCF79500U ) + +/** @def ecapREG4 + * @brief ECAP4 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP4 registers. + */ +#define ecapREG4 ( ( ecapBASE_t * ) 0xFCF79600U ) + +/** @def ecapREG5 + * @brief ECAP5 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP5 registers. + */ +#define ecapREG5 ( ( ecapBASE_t * ) 0xFCF79700U ) + +/** @def ecapREG6 + * @brief ECAP6 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP6 registers. + */ +#define ecapREG6 ( ( ecapBASE_t * ) 0xFCF79800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_ECAP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_efc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_efc.h new file mode 100644 index 00000000000..22266ba062e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_efc.h @@ -0,0 +1,96 @@ +/** @file reg_efc.h + * @brief EFC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EFC_H__ +#define __REG_EFC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ + +/** @struct efcBase + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ + +/** @typedef efcBASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct efcBase +{ + uint32 INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */ + uint32 ADDRESS; /* 0x4 ADDRESS REGISTER */ + uint32 DATA_UPPER; /* 0x8 DATA UPPER REGISTER */ + uint32 DATA_LOWER; /* 0xc DATA LOWER REGISTER */ + uint32 SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */ + uint32 SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */ + uint32 ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */ + uint32 BOUNDARY; /* 0x1C BOUNDARY REGISTER */ + uint32 KEY_FLAG; /* 0x20 KEY FLAG REGISTER */ + uint32 KEY; /* 0x24 KEY REGISTER */ + uint32 rsvd1; /* 0x28 RESERVED */ + uint32 PINS; /* 0x2C PINS REGISTER */ + uint32 CRA; /* 0x30 CRA */ + uint32 READ; /* 0x34 READ REGISTER */ + uint32 PROGRAMME; /* 0x38 PROGRAMME REGISTER */ + uint32 ERROR; /* 0x3C ERROR STATUS REGISTER */ + uint32 SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */ + uint32 TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */ + uint32 SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */ + uint32 SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */ +} efcBASE_t; + +#define efcREG ( ( efcBASE_t * ) 0xFFF8C000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_EFC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_emif.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_emif.h new file mode 100644 index 00000000000..47f25b773b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_emif.h @@ -0,0 +1,97 @@ +/** @file reg_emif.h + * @brief EMIF Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EMIF driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EMIF_H__ +#define __REG_EMIF_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Emif Register Frame Definition */ + +/** @struct emifBASE_t + * @brief emifBASE Register Definition + * + * This structure is used to access the EMIF module registers. + */ +typedef volatile struct emifBase +{ + uint32 MIDR; /**< 0x0000 Module ID Register */ + uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/ + uint32 SDCR; /**< 0x0008 SDRAM configuration register */ + uint32 SDRCR; /**< 0x000C Set Interrupt Enable Register */ + uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */ + uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */ + uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */ + uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */ + uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */ + uint32 dummy1[ 6 ]; /** reserved **/ + uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */ + uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/ + uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */ + uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */ + uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */ + uint32 dummy2[ 6 ]; /** reserved **/ + uint32 PMCR; /**< 0x0068 Page Mode Control Register*/ +} emifBASE_t; + +#define emifREG ( ( emifBASE_t * ) 0xFCFFE800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __REG_EMIF_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_eqep.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_eqep.h new file mode 100644 index 00000000000..e1a22d34527 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_eqep.h @@ -0,0 +1,150 @@ +/** @file reg_eqep.h + * @brief EQEP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EQEP_H__ +#define __REG_EQEP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Eqep Register Frame Definition */ + +/** @struct eqepBASE + * @brief EQEP Register Frame Definition + * + * This type is used to access the EQEP Registers. + */ + +/** @typedef eqepBASE_t + * @brief EQEP Register Frame Type Definition + * + * This type is used to access the EQEP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ +} eqepBASE_t; + +#else /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ +} eqepBASE_t; + +#endif /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + +/** @def eqepREG1 + * @brief eQEP1 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP1 registers. + */ +#define eqepREG1 ( ( eqepBASE_t * ) 0xFCF79900U ) + +/** @def eqepREG2 + * @brief eQEP2 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP2 registers. + */ +#define eqepREG2 ( ( eqepBASE_t * ) 0xFCF79A00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_EQEP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_esm.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_esm.h new file mode 100644 index 00000000000..6235d157147 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_esm.h @@ -0,0 +1,104 @@ +/** @file reg_esm.h + * @brief ESM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ESM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ESM_H__ +#define __REG_ESM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Esm Register Frame Definition */ + +/** @struct esmBase + * @brief Esm Register Frame Definition + * + * This type is used to access the Esm Registers. + */ + +/** @typedef esmBASE_t + * @brief Esm Register Frame Type Definition + * + * This type is used to access the Esm Registers. + */ +typedef volatile struct esmBase +{ + uint32 EEPAPR1; /* 0x0000 */ + uint32 DEPAPR1; /* 0x0004 */ + uint32 IESR1; /* 0x0008 */ + uint32 IECR1; /* 0x000C */ + uint32 ILSR1; /* 0x0010 */ + uint32 ILCR1; /* 0x0014 */ + uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */ + uint32 EPSR; /* 0x0024 */ + uint32 IOFFHR; /* 0x0028 */ + uint32 IOFFLR; /* 0x002C */ + uint32 LTCR; /* 0x0030 */ + uint32 LTCPR; /* 0x0034 */ + uint32 EKR; /* 0x0038 */ + uint32 SSR2; /* 0x003C */ + uint32 IEPSR4; /* 0x0040 */ + uint32 IEPCR4; /* 0x0044 */ + uint32 IESR4; /* 0x0048 */ + uint32 IECR4; /* 0x004C */ + uint32 ILSR4; /* 0x0050 */ + uint32 ILCR4; /* 0x0054 */ + uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */ +} esmBASE_t; + +/** @def esmREG + * @brief Esm Register Frame Pointer + * + * This pointer is used by the Esm driver to access the Esm registers. + */ +#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_ESM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_etpwm.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_etpwm.h new file mode 100644 index 00000000000..a437431f1d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_etpwm.h @@ -0,0 +1,221 @@ +/** @file reg_etpwm.h + * @brief ETPWM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ETPWM_H__ +#define __REG_ETPWM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ETPWM Register Frame Definition */ + +/** @struct etpwmBASE + * @brief ETPWM Register Frame Definition + * + * This type is used to access the ETPWM Registers. + */ + +/** @typedef etpwmBASE_t + * @brief ETPWM Register Frame Type Definition + * + * This type is used to access the ETPWM Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct etpwmBASE +{ + uint16 TBCTL; /**< 0x0000 Time-Base Control Register*/ + uint16 TBSTS; /**< 0x0002 Time-Base Status Register*/ + uint16 rsvd1; /**< 0x0004 Reserved*/ + uint16 TBPHS; /**< 0x0006 Time-Base Phase Register*/ + uint16 TBCTR; /**< 0x0008 Time-Base Counter Register*/ + uint16 TBPRD; /**< 0x000A Time-Base Period Register*/ + uint16 rsvd2; /**< 0x000C Reserved*/ + uint16 CMPCTL; /**< 0x000E Counter-Compare Control Register*/ + uint16 rsvd3; /**< 0x0010 Reserved*/ + uint16 CMPA; /**< 0x0012 Counter-Compare A Register*/ + uint16 CMPB; /**< 0x0014 Counter-Compare B Register*/ + uint16 AQCTLA; /**< 0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 AQCTLB; /**< 0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 AQSFRC; /**< 0x001A Action-Qualifier Software Force Register*/ + uint16 AQCSFRC; /**< 0x001C Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBCTL; /**< 0x001E Dead-Band Generator Control Register*/ + uint16 DBRED; /**< 0x0020 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 DBFED; /**< 0x0022 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 TZSEL; /**< 0x0024 Trip-Zone Select Register*/ + uint16 TZDCSEL; /**< 0x0026 Trip Zone Digital Compare Select Register*/ + uint16 TZCTL; /**< 0x0028 Trip-Zone Control Register*/ + uint16 TZEINT; /**< 0x002A Trip-Zone Enable Interrupt Register*/ + uint16 TZFLG; /**< 0x002C Trip-Zone Flag Register*/ + uint16 TZCLR; /**< 0x002E Trip-Zone Clear Register*/ + uint16 TZFRC; /**< 0x0030 Trip-Zone Force Register*/ + uint16 ETSEL; /**< 0x0032 Event-Trigger Selection Register*/ + uint16 ETPS; /**< 0x0034 Event-Trigger Pre-Scale Register*/ + uint16 ETFLG; /**< 0x0036 Event-Trigger Flag Register*/ + uint16 ETCLR; /**< 0x0038 Event-Trigger Clear Register*/ + uint16 ETFRC; /**< 0x003A Event-Trigger Force Register*/ + uint16 PCCTL; /**< 0x003C PWM-Chopper Control Register*/ + uint16 rsvd4; /**< 0x003E Reserved*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCTRIPSEL; /**< 0x0060 Digital Compare Trip Select Register*/ + uint16 DCACTL; /**< 0x0062 Digital Compare A Control Register*/ + uint16 DCBCTL; /**< 0x0064 Digital Compare B Control Register*/ + uint16 DCFCTL; /**< 0x0066 Digital Compare Filter Control Register*/ + uint16 DCCAPCTL; /**< 0x0068 Digital Compare Capture Control Register*/ + uint16 DCFOFFSET; /**< 0x006A Digital Compare Filter Offset Register*/ + uint16 DCFOFFSETCNT; /**< 0x006C Digital Compare Filter Offset Counter Register*/ + uint16 DCFWINDOW; /**< 0x006E Digital Compare Filter Window Register*/ + uint16 DCFWINDOWCNT; /**< 0x0070 Digital Compare Filter Window Counter Register*/ + uint16 DCCAP; /**< 0x0072 Digital Compare Counter Capture Register*/ +} etpwmBASE_t; + +#else /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + +typedef volatile struct etpwmBASE +{ + uint16 TBSTS; /**< 0x0000 Time-Base Status Register*/ + uint16 TBCTL; /**< 0x0002 Time-Base Control Register*/ + uint16 TBPHS; /**< 0x0004 Time-Base Phase Register*/ + uint16 rsvd1; /**< 0x0006 Reserved*/ + uint16 TBPRD; /**< 0x0008 Time-Base Period Register*/ + uint16 TBCTR; /**< 0x000A Time-Base Counter Register*/ + uint16 CMPCTL; /**< 0x000C Counter-Compare Control Register*/ + uint16 rsvd2; /**< 0x000E Reserved*/ + uint16 CMPA; /**< 0x0010 Counter-Compare A Register*/ + uint16 rsvd3; /**< 0x0012 Reserved*/ + uint16 AQCTLA; /**< 0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 CMPB; /**< 0x0016 Counter-Compare B Register*/ + uint16 AQSFRC; /**< 0x0018 Action-Qualifier Software Force Register*/ + uint16 AQCTLB; /**< 0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 DBCTL; /**< 0x001C Dead-Band Generator Control Register*/ + uint16 AQCSFRC; /**< 0x001E Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBFED; /**< 0x0020 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 DBRED; /**< 0x0022 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 TZDCSEL; /**< 0x0024 Trip Zone Digital Compare Select Register*/ + uint16 TZSEL; /**< 0x0026 Trip-Zone Select Register*/ + uint16 TZEINT; /**< 0x0028 Trip-Zone Enable Interrupt Register*/ + uint16 TZCTL; /**< 0x002A Trip-Zone Control Register*/ + uint16 TZCLR; /**< 0x002C Trip-Zone Clear Register*/ + uint16 TZFLG; /**< 0x002E Trip-Zone Flag Register*/ + uint16 ETSEL; /**< 0x0030 Event-Trigger Selection Register*/ + uint16 TZFRC; /**< 0x0032 Trip-Zone Force Register*/ + uint16 ETFLG; /**< 0x0034 Event-Trigger Flag Register*/ + uint16 ETPS; /**< 0x0036 Event-Trigger Pre-Scale Register*/ + uint16 ETFRC; /**< 0x0038 Event-Trigger Force Register*/ + uint16 ETCLR; /**< 0x003A Event-Trigger Clear Register*/ + uint16 rsvd4; /**< 0x003C Reserved*/ + uint16 PCCTL; /**< 0x003E PWM-Chopper Control Register*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCACTL; /**< 0x0060 Digital Compare A Control Register*/ + uint16 DCTRIPSEL; /**< 0x0062 Digital Compare Trip Select Register*/ + uint16 DCFCTL; /**< 0x0064 Digital Compare Filter Control Register*/ + uint16 DCBCTL; /**< 0x0066 Digital Compare B Control Register*/ + uint16 DCFOFFSET; /**< 0x0068 Digital Compare Filter Offset Register*/ + uint16 DCCAPCTL; /**< 0x006A Digital Compare Capture Control Register*/ + uint16 DCFWINDOW; /**< 0x006C Digital Compare Filter Window Register*/ + uint16 DCFOFFSETCNT; /**< 0x006E Digital Compare Filter Offset Counter Register*/ + uint16 DCCAP; /**< 0x0070 Digital Compare Counter Capture Register*/ + uint16 DCFWINDOWCNT; /**< 0x0072 Digital Compare Filter Window Counter Register*/ +} etpwmBASE_t; + +#endif /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + +/** @def etpwmREG1 + * @brief ETPWM1 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM1 registers. + */ +#define etpwmREG1 ( ( etpwmBASE_t * ) 0xFCF78C00U ) + +/** @def etpwmREG2 + * @brief ETPWM2 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM2 registers. + */ +#define etpwmREG2 ( ( etpwmBASE_t * ) 0xFCF78D00U ) + +/** @def etpwmREG3 + * @brief ETPWM3 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM3 registers. + */ +#define etpwmREG3 ( ( etpwmBASE_t * ) 0xFCF78E00U ) + +/** @def etpwmREG4 + * @brief ETPWM4 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM4 registers. + */ +#define etpwmREG4 ( ( etpwmBASE_t * ) 0xFCF78F00U ) + +/** @def etpwmREG5 + * @brief ETPWM5 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM5 registers. + */ +#define etpwmREG5 ( ( etpwmBASE_t * ) 0xFCF79000U ) + +/** @def etpwmREG6 + * @brief ETPWM6 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM6 registers. + */ +#define etpwmREG6 ( ( etpwmBASE_t * ) 0xFCF79100U ) + +/** @def etpwmREG7 + * @brief ETPWM7 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM7 registers. + */ +#define etpwmREG7 ( ( etpwmBASE_t * ) 0xFCF79200U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_ETPWM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_flash.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_flash.h new file mode 100644 index 00000000000..728431247b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_flash.h @@ -0,0 +1,135 @@ +/** @file reg_flash.h + * @brief Flash Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_FLASH_H__ +#define __REG_FLASH_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Flash Register Frame Definition */ + +/** @struct flashWBase + * @brief Flash Wrapper Register Frame Definition + * + * This type is used to access the Flash Wrapper Registers. + */ + +/** @typedef flashWBASE_t + * @brief Flash Wrapper Register Frame Type Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +typedef volatile struct flashWBase +{ + uint32 FRDCNTL; /* 0x0000 */ + uint32 rsvd1; /* 0x0004 */ + uint32 FEDACCTRL1; /* 0x0008 */ + uint32 FEDACCTRL2; /* 0x000C */ + uint32 FCORERRCNT; /* 0x0010 */ + uint32 FCORERRADD; /* 0x0014 */ + uint32 FCORERRPOS; /* 0x0018 */ + uint32 FEDACSTATUS; /* 0x001C */ + uint32 FUNCERRADD; /* 0x0020 */ + uint32 FEDACSDIS; /* 0x0024 */ + uint32 FPRIMADDTAG; /* 0x0028 */ + uint32 FREDUADDTAG; /* 0x002C */ + uint32 FBPROT; /* 0x0030 */ + uint32 FBSE; /* 0x0034 */ + uint32 FBBUSY; /* 0x0038 */ + uint32 FBAC; /* 0x003C */ + uint32 FBFALLBACK; /* 0x0040 */ + uint32 FBPRDY; /* 0x0044 */ + uint32 FPAC1; /* 0x0048 */ + uint32 FPAC2; /* 0x004C */ + uint32 FMAC; /* 0x0050 */ + uint32 FMSTAT; /* 0x0054 */ + uint32 FEMUDMSW; /* 0x0058 */ + uint32 FEMUDLSW; /* 0x005C */ + uint32 FEMUECC; /* 0x0060 */ + uint32 FLOCK; /* 0x0064 */ + uint32 FEMUADDR; /* 0x0068 */ + uint32 FDIAGCTRL; /* 0x006C */ + uint32 FRAWDATAH; /* 0x0070 */ + uint32 FRAWDATAL; /* 0x0074 */ + uint32 FRAWECC; /* 0x0078 */ + uint32 FPAROVR; /* 0x007C */ + uint32 rsvd2[ 16U ]; /* 0x009C */ + uint32 FEDACSDIS2; /* 0x00C0 */ + uint32 rsvd3[ 15U ]; /* 0x00C4 */ + uint32 rsvd4[ 13U ]; /* 0x0100 */ + uint32 rsvd5[ 85U ]; /* 0x0134 */ + uint32 FSMWRENA; /* 0x0288 */ + uint32 rsvd6[ 6U ]; /* 0x028C */ + uint32 FSMSECTOR; /* 0x02A4 */ + uint32 rsvd7[ 4U ]; /* 0x02A8 */ + uint32 EEPROMCONFIG; /* 0x02B8 */ + uint32 rsvd8[ 19U ]; /* 0x02BC */ + uint32 EECTRL1; /* 0x0308 */ + uint32 EECTRL2; /* 0x030C */ + uint32 EECORRERRCNT; /* 0x0310 */ + uint32 EECORRERRADD; /* 0x0314 */ + uint32 EECORRERRPOS; /* 0x0318 */ + uint32 EESTATUS; /* 0x031C */ + uint32 EEUNCERRADD; /* 0x0320 */ +} flashWBASE_t; + +/** @def flashWREG + * @brief Flash Wrapper Register Frame Pointer + * + * This pointer is used by the system driver to access the flash wrapper registers. + */ +#define flashWREG ( ( flashWBASE_t * ) ( 0xFFF87000U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* ifndef __REG_FLASH_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_gio.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_gio.h new file mode 100644 index 00000000000..83d88153c01 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_gio.h @@ -0,0 +1,131 @@ +/** @file reg_gio.h + * @brief GIO Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the GIO driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_GIO_H__ +#define __REG_GIO_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Gio Register Frame Definition */ + +/** @struct gioBase + * @brief GIO Base Register Definition + * + * This structure is used to access the GIO module registers. + */ + +/** @typedef gioBASE_t + * @brief GIO Register Frame Type Definition + * + * This type is used to access the GIO Registers. + */ +typedef volatile struct gioBase +{ + uint32 GCR0; /**< 0x0000: Global Control Register */ + uint32 rsvd; /**< 0x0004: Reserved*/ + uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/ + uint32 POL; /**< 0x000C: Interrupt Polarity Register */ + uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */ + uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */ + uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */ + uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */ + uint32 FLG; /**< 0x0020: Interrupt Flag Register */ + uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */ + uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */ + uint32 EMU1; /**< 0x002C: Emulation 1 Register */ + uint32 EMU2; /**< 0x0030: Emulation 2 Register */ +} gioBASE_t; + +/** @struct gioPort + * @brief GIO Port Register Definition + */ + +/** @typedef gioPORT_t + * @brief GIO Port Register Type Definition + * + * This type is used to access the GIO Port Registers. + */ +typedef volatile struct gioPort +{ + uint32 DIR; /**< 0x0000: Data Direction Register */ + uint32 DIN; /**< 0x0004: Data Input Register */ + uint32 DOUT; /**< 0x0008: Data Output Register */ + uint32 DSET; /**< 0x000C: Data Output Set Register */ + uint32 DCLR; /**< 0x0010: Data Output Clear Register */ + uint32 PDR; /**< 0x0014: Open Drain Register */ + uint32 PULDIS; /**< 0x0018: Pullup Disable Register */ + uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */ +} gioPORT_t; + +/** @def gioREG + * @brief GIO Register Frame Pointer + * + * This pointer is used by the GIO driver to access the gio module registers. + */ +#define gioREG ( ( gioBASE_t * ) 0xFFF7BC00U ) + +/** @def gioPORTA + * @brief GIO Port (A) Register Pointer + * + * Pointer used by the GIO driver to access PORTA + */ +#define gioPORTA ( ( gioPORT_t * ) 0xFFF7BC34U ) + +/** @def gioPORTB + * @brief GIO Port (B) Register Pointer + * + * Pointer used by the GIO driver to access PORTB + */ +#define gioPORTB ( ( gioPORT_t * ) 0xFFF7BC54U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_GIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_het.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_het.h new file mode 100644 index 00000000000..861275a12be --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_het.h @@ -0,0 +1,201 @@ +/** @file reg_het.h + * @brief HET Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HET driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HET_H__ +#define __REG_HET_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Het Register Frame Definition */ + +/** @struct hetBase + * @brief HET Base Register Definition + * + * This structure is used to access the HET module registers. + */ + +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +typedef volatile struct hetBase +{ + uint32 GCR; /**< 0x0000: Global control register */ + uint32 PFR; /**< 0x0004: Prescale factor register */ + uint32 ADDR; /**< 0x0008: Current address register */ + uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */ + uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */ + uint32 INTENAS; /**< 0x0014: Interrupt enable set register */ + uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */ + uint32 EXC1; /**< 0x001C: Exception control register 1 */ + uint32 EXC2; /**< 0x0020: Exception control register 2 */ + uint32 PRY; /**< 0x0024: Interrupt priority register */ + uint32 FLG; /**< 0x0028: Interrupt flag register */ + uint32 AND; /**< 0x002C: AND share control register */ + uint32 rsvd1; /**< 0x0030: Reserved */ + uint32 HRSH; /**< 0x0034: High resolution share register */ + uint32 XOR; /**< 0x0038: XOR share register */ + uint32 REQENS; /**< 0x003C: Request enable set register */ + uint32 REQENC; /**< 0x0040: Request enable clear register */ + uint32 REQDS; /**< 0x0044: Request destination select register */ + uint32 rsvd2; /**< 0x0048: Reserved */ + uint32 DIR; /**< 0x004C: Direction register */ + uint32 DIN; /**< 0x0050: Data input register */ + uint32 DOUT; /**< 0x0054: Data output register */ + uint32 DSET; /**< 0x0058: Data output set register */ + uint32 DCLR; /**< 0x005C: Data output clear register */ + uint32 PDR; /**< 0x0060: Open drain register */ + uint32 PULDIS; /**< 0x0064: Pull disable register */ + uint32 PSL; /**< 0x0068: Pull select register */ + uint32 rsvd3; /**< 0x006C: Reserved */ + uint32 rsvd4; /**< 0x0070: Reserved */ + uint32 PCR; /**< 0x0074: Parity control register */ + uint32 PAR; /**< 0x0078: Parity address register */ + uint32 PPR; /**< 0x007C: Parity pin select register */ + uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */ + uint32 SFENA; /**< 0x0084: Suppression filter enable register */ + uint32 rsvd5; /**< 0x0088: Reserved */ + uint32 LBPSEL; /**< 0x008C: Loop back pair select register */ + uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */ + uint32 PINDIS; /**< 0x0094: Pin disable register */ +} hetBASE_t; + +/** @struct hetInstructionBase + * @brief HET Instruction Definition + * + * This structure is used to access the HET RAM. + */ + +/** @typedef hetINSTRUCTION_t + * @brief HET Instruction Type Definition + * + * This type is used to access a HET Instruction. + */ +typedef volatile struct hetInstructionBase +{ + uint32 Program; + uint32 Control; + uint32 Data; + uint32 rsvd1; +} hetINSTRUCTION_t; + +/** @struct hetRamBase + * @brief HET RAM Definition + * + * This structure is used to access the HET RAM. + */ + +/** @typedef hetRAMBASE_t + * @brief HET RAM Type Definition + * + * This type is used to access the HET RAM. + */ +typedef volatile struct het1RamBase +{ + hetINSTRUCTION_t Instruction[ 160U ]; +} hetRAMBASE_t; + +/** @def hetREG1 + * @brief HET Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG1 ( ( hetBASE_t * ) 0xFFF7B800U ) + +/** @def hetPORT1 + * @brief HET GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET1 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT1 ( ( gioPORT_t * ) 0xFFF7B84CU ) + +/** @def hetRAM1 + * @brief NHET1 RAM Pointer + * + * This pointer is used by the HET driver to access the NHET1 memory. + */ +#define hetRAM1 ( ( hetRAMBASE_t * ) 0xFF460000U ) + +#define NHET1RAMPARLOC ( *( volatile uint32 * ) 0xFF462000U ) +#define NHET1RAMLOC ( *( volatile uint32 * ) 0xFF460000U ) + +/** @def hetREG2 + * @brief HET2 Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG2 ( ( hetBASE_t * ) 0xFFF7B900U ) + +/** @def hetPORT2 + * @brief HET2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET2 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT2 ( ( gioPORT_t * ) 0xFFF7B94CU ) + +/** @def hetRAM2 + * @brief NHET1 RAM Pointer + * + * This pointer is used by the HET driver to access the NHET2 memory. + */ +#define hetRAM2 ( ( hetRAMBASE_t * ) 0xFF440000U ) + +#define NHET2RAMPARLOC ( *( volatile uint32 * ) 0xFF442000U ) +#define NHET2RAMLOC ( *( volatile uint32 * ) 0xFF440000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_HET_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_htu.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_htu.h new file mode 100644 index 00000000000..a8e1396ae6f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_htu.h @@ -0,0 +1,137 @@ +/** @file reg_htu.h + * @brief HTU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HTU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HTU_H__ +#define __REG_HTU_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* htu Register Frame Definition */ + +/** @struct htuBase + * @brief HTU Base Register Definition + * + * This structure is used to access the HTU module registers. + */ + +/** @typedef htuBASE_t + * @brief HTU Register Frame Type Definition + * + * This type is used to access the HTU Registers. + */ +typedef volatile struct htuBase +{ + uint32 GC; /** 0x00 */ + uint32 CPENA; /** 0x04 */ + uint32 BUSY0; /** 0x08 */ + uint32 BUSY1; /** 0x0C */ + uint32 BUSY2; /** 0x10 */ + uint32 BUSY3; /** 0x14 */ + uint32 ACPE; /** 0x18 */ + uint32 rsvd1; /** 0x1C */ + uint32 RLBECTRL; /** 0x20 */ + uint32 BFINTS; /** 0x24 */ + uint32 BFINTC; /** 0x28 */ + uint32 INTMAP; /** 0x2C */ + uint32 rsvd2; /** 0x30 */ + uint32 INTOFF0; /** 0x34 */ + uint32 INTOFF1; /** 0x38 */ + uint32 BIM; /** 0x3C */ + uint32 RLOSTFL; /** 0x40 */ + uint32 BFINTFL; /** 0x44 */ + uint32 BERINTFL; /** 0x48 */ + uint32 MP1S; /** 0x4C */ + uint32 MP1E; /** 0x50 */ + uint32 DCTRL; /** 0x54 */ + uint32 WPR; /** 0x58 */ + uint32 WMR; /** 0x5C */ + uint32 ID; /** 0x60 */ + uint32 PCR; /** 0x64 */ + uint32 PAR; /** 0x68 */ + uint32 rsvd3; /** 0x6C */ + uint32 MPCS; /** 0x70 */ + uint32 MP0S; /** 0x74 */ + uint32 MP0E; /** 0x78 */ +} htuBASE_t; + +typedef volatile struct +{ + struct /* 0x00-0x7C */ + { + uint32 IFADDRA; + uint32 IFADDRB; + uint32 IHADDRCT; + uint32 ITCOUNT; + } DCP[ 8U ]; + + struct /* 0x80-0xFC */ + { + uint32 res[ 32U ]; + } RESERVED; + + struct /* 0x100-0x17C */ + { + uint32 CFADDRA; + uint32 CFADDRB; + uint32 CFCOUNT; + uint32 rsvd4; + } CDCP[ 8U ]; +} htuRAMBASE_t; + +#define htuREG1 ( ( htuBASE_t * ) 0xFFF7A400U ) +#define htuREG2 ( ( htuBASE_t * ) 0xFFF7A500U ) + +#define htuRAM1 ( ( htuRAMBASE_t * ) 0xFF4E0000U ) +#define htuRAM2 ( ( htuRAMBASE_t * ) 0xFF4C0000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_HTU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_i2c.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_i2c.h new file mode 100644 index 00000000000..849da91a912 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_i2c.h @@ -0,0 +1,143 @@ +/** @file reg_i2c.h + * @brief I2C Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the I2C driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* I2c Register Frame Definition */ + +/** @struct i2cBase + * @brief I2C Base Register Definition + * + * This structure is used to access the I2C module registers. + */ + +/** @typedef i2cBASE_t + * @brief I2C Register Frame Type Definition + * + * This type is used to access the I2C Registers. + */ +typedef volatile struct i2cBase +{ + uint32 OAR; /**< 0x0000 I2C Own Address register */ + uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */ + uint32 STR; /**< 0x0008 I2C Interrupt Status register */ + uint32 CKL; /**< 0x000C I2C Clock Divider Low register */ + uint32 CKH; /**< 0x0010 I2C Clock Divider High register */ + uint32 CNT; /**< 0x0014 I2C Data Count register */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 DRR; /**< 0x0018: I2C Data Receive register, */ + uint8 rsvd1; /**< 0x0018: I2C Data Receive register, Reserved */ + uint8 rsvd2; /**< 0x0018: I2C Data Receive register, Reserved */ + uint8 rsvd3; /**< 0x0018: I2C Data Receive register, Reserved */ +#else + uint8 rsvd3; /**< 0x0018: I2C Data Receive register, Reserved */ + uint8 rsvd2; /**< 0x0018: I2C Data Receive register, Reserved */ + uint8 rsvd1; /**< 0x0018: I2C Data Receive register, Reserved */ + uint8 DRR; /**< 0x0018: I2C Data Receive register, */ +#endif + uint32 SAR; /**< 0x001C I2C Slave Address register */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 DXR; /**< 0x0020: I2C Data Transmit register, */ + uint8 rsvd4; /**< 0x0020: I2C Data Transmit register, Reserved */ + uint8 rsvd5; /**< 0x0020: I2C Data Transmit register, Reserved */ + uint8 rsvd6; /**< 0x0020: I2C Data Transmit register, Reserved */ +#else + uint8 rsvd6; /**< 0x0020: I2C Data Transmit register, Reserved */ + uint8 rsvd5; /**< 0x0020: I2C Data Transmit register, Reserved */ + uint8 rsvd4; /**< 0x0020: I2C Data Transmit register, Reserved */ + uint8 DXR; /**< 0x0020: I2C Data Transmit register, */ +#endif + uint32 MDR; /**< 0x0024 I2C Mode register */ + uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */ + uint32 EMDR; /**< 0x002C I2C Extended Mode register */ + uint32 PSC; /**< 0x0030 I2C Prescaler register */ + uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */ + uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */ + uint32 DMACR; /**< 0x003C I2C DMA Control Register */ + uint32 rsvd7; /**< 0x0040 Reserved */ + uint32 rsvd8; /**< 0x0044 Reserved */ + uint32 PFNC; /**< 0x0048 Pin Function Register */ + uint32 DIR; /**< 0x004C Pin Direction Register */ + uint32 DIN; /**< 0x0050 Pin Data In Register */ + uint32 DOUT; /**< 0x0054 Pin Data Out Register */ + uint32 SET; /**< 0x0058 Pin Data Set Register */ + uint32 CLR; /**< 0x005C Pin Data Clr Register */ + uint32 PDR; /**< 0x0060 Pin Open Drain Output Enable Register */ + uint32 PDIS; /**< 0x0064 Pin Pullup/Pulldown Disable Register */ + uint32 PSEL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */ + uint32 PSRS; /**< 0x006C Pin Slew Rate Select Register */ +} i2cBASE_t; + +/** @def i2cREG1 + * @brief I2C Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C module registers. + */ +#define i2cREG1 ( ( i2cBASE_t * ) 0xFFF7D400U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @def i2cPORT1 + * @brief I2C GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT1 ( ( gioPORT_t * ) 0xFFF7D44CU ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* ifndef __REG_I2C_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_lin.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_lin.h new file mode 100644 index 00000000000..bd845f5f53f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_lin.h @@ -0,0 +1,125 @@ +/** @file reg_lin.h + * @brief LIN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the LIN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_LIN_H__ +#define __REG_LIN_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Lin Register Frame Definition */ + +/** @struct linBase + * @brief LIN Base Register Definition + * + * This structure is used to access the LIN module registers. + */ + +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +typedef volatile struct linBase +{ + uint32 GCR0; /**< 0x0000: Global control register 0 */ + uint32 GCR1; /**< 0x0004: Global control register 1 */ + uint32 GCR2; /**< 0x0008: Global control register 2 */ + uint32 SETINT; /**< 0x000C: Set interrupt enable register */ + uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */ + uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */ + uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */ + uint32 FLR; /**< 0x001C: interrupt flag register */ + uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */ + uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */ + uint32 FORMAT; /**< 0x0028: Format Control Register */ + uint32 BRS; /**< 0x002C: Baud rate selection register */ + uint32 ED; /**< 0x0030: Emulation register */ + uint32 RD; /**< 0x0034: Receive data register */ + uint32 TD; /**< 0x0038: Transmit data register */ + uint32 PIO0; /**< 0x003C: Pin function register */ + uint32 PIO1; /**< 0x0040: Pin direction register */ + uint32 PIO2; /**< 0x0044: Pin data in register */ + uint32 PIO3; /**< 0x0048: Pin data out register */ + uint32 PIO4; /**< 0x004C: Pin data set register */ + uint32 PIO5; /**< 0x0050: Pin data clr register */ + uint32 PIO6; /**< 0x0054: Pin open drain output enable register */ + uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */ + uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */ + uint32 COMP; /**< 0x0060: Compare register */ + uint8 RDx[ 8U ]; /**< 0x0064-0x0068: RX buffer register */ + uint32 MASK; /**< 0x006C: Mask register */ + uint32 ID; /**< 0x0070: Identification Register */ + uint8 TDx[ 8U ]; /**< 0x0074-0x0078: TX buffer register */ + uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */ + uint32 rsvd1[ 4U ]; /**< 0x0080 - 0x8C: Reserved */ + uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */ +} linBASE_t; + +/** @def linREG + * @brief LIN Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin module registers. + */ +#define linREG ( ( linBASE_t * ) 0xFFF7E400U ) + +/** @def linPORT + * @brief LIN GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN + * (use the GIO drivers to access the port pins). + */ +#define linPORT ( ( gioPORT_t * ) 0xFFF7E440U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_LIN_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_mibspi.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_mibspi.h new file mode 100644 index 00000000000..7481631fc2b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_mibspi.h @@ -0,0 +1,249 @@ +/** @file reg_mibspi.h + * @brief MIBSPI Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the MIBSPI driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_MIBSPI_H__ +#define __REG_MIBSPI_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Mibspi Register Frame Definition */ + +/** @struct mibspiBase + * @brief MIBSPI Register Definition + * + * This structure is used to access the MIBSPI module registers. + */ + +/** @typedef mibspiBASE_t + * @brief MIBSPI Register Frame Type Definition + * + * This type is used to access the MIBSPI Registers. + */ +typedef volatile struct mibspiBase +{ + uint32 GCR0; /**< 0x0000: Global Control 0 */ + uint32 GCR1; /**< 0x0004: Global Control 1 */ + uint32 INT0; /**< 0x0008: Interrupt Register */ + uint32 LVL; /**< 0x000C: Interrupt Level */ + uint32 FLG; /**< 0x0010: Interrupt flags */ + uint32 PC0; /**< 0x0014: Function Pin Enable */ + uint32 PC1; /**< 0x0018: Pin Direction */ + uint32 PC2; /**< 0x001C: Pin Input Latch */ + uint32 PC3; /**< 0x0020: Pin Output Latch */ + uint32 PC4; /**< 0x0024: Output Pin Set */ + uint32 PC5; /**< 0x0028: Output Pin Clr */ + uint32 PC6; /**< 0x002C: Open Drain Output Enable */ + uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */ + uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */ + uint32 DAT0; /**< 0x0038: Transmit Data */ + uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ + uint32 BUF; /**< 0x0040: Receive Buffer */ + uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ + uint32 DELAY; /**< 0x0048: Delays */ + uint32 DEF; /**< 0x004C: Default Chip Select */ + uint32 FMT0; /**< 0x0050: Data Format 0 */ + uint32 FMT1; /**< 0x0054: Data Format 1 */ + uint32 FMT2; /**< 0x0058: Data Format 2 */ + uint32 FMT3; /**< 0x005C: Data Format 3 */ + uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ + uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ + uint32 SRSEL; /**< 0x0068: Slew Rate Select */ + uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */ + uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */ + uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */ + uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */ + uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */ + uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */ + uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */ + uint32 rsvd1[ 2U ]; /**< 0x0088: Reserved */ + uint32 TICKCNT; /**< 0x0090: Tick Counter */ + uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */ + uint32 TGCTRL[ 16U ]; /**< 0x0098 - 0x00D4: Transfer Group Control */ + uint32 DMACTRL[ 8U ]; /**< 0x00D8 - 0x00F4: DMA Control */ + uint32 DMACOUNT[ 8U ]; /**< 0x00F8 - 0x0114: DMA Count */ + uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */ + uint32 rsvd2; /**< 0x011C: Reserved */ + uint32 UERRCTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */ + uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */ + uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */ + uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */ + uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */ + uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ + uint32 EXT_PRESCALE1; /**< 0x0138: */ + uint32 EXT_PRESCALE2; /**< 0x013C: */ +} mibspiBASE_t; + +/** @def mibspiREG1 + * @brief MIBSPI1 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG1 ( ( mibspiBASE_t * ) 0xFFF7F400U ) + +/** @def mibspiPORT1 + * @brief MIBSPI1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI1 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U ) + +/** @def mibspiREG3 + * @brief MIBSPI3 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG3 ( ( mibspiBASE_t * ) 0xFFF7F800U ) + +/** @def mibspiPORT3 + * @brief MIBSPI3 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI3 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U ) + +/** @def mibspiREG5 + * @brief MIBSPI5 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG5 ( ( mibspiBASE_t * ) 0xFFF7FC00U ) + +/** @def mibspiPORT5 + * @brief MIBSPI5 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI5 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U ) + +/** @struct mibspiRamBase + * @brief MIBSPI Buffer RAM Definition + * + * This structure is used to access the MIBSPI buffer memory. + */ + +/** @typedef mibspiRAM_t + * @brief MIBSPI RAM Type Definition + * + * This type is used to access the MIBSPI RAM. + */ +typedef volatile struct mibspiRamBase +{ + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< tx buffer data */ + uint16 control; /**< tx buffer control */ +#else + uint16 control; /**< tx buffer control */ + uint16 data; /**< tx buffer data */ +#endif + } tx[ 128 ]; + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< rx buffer data */ + uint16 flags; /**< rx buffer flags */ +#else + uint16 flags; /**< rx buffer flags */ + uint16 data; /**< rx buffer data */ +#endif + } rx[ 128 ]; +} mibspiRAM_t; + +/** @def mibspiRAM1 + * @brief MIBSPI1 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM1 ( ( mibspiRAM_t * ) 0xFF0E0000U ) + +/** @def mibspiRAM3 + * @brief MIBSPI3 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM3 ( ( mibspiRAM_t * ) 0xFF0C0000U ) + +/** @def mibspiRAM5 + * @brief MIBSPI5 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM5 ( ( mibspiRAM_t * ) 0xFF0A0000U ) + +/** @def mibspiPARRAM1 + * @brief MIBSPI1 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM1 ( *( volatile uint32 * ) ( 0xFF0E0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM3 + * @brief MIBSPI3 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM3 ( *( volatile uint32 * ) ( 0xFF0C0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM5 + * @brief MIBSPI5 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM5 ( *( volatile uint32 * ) ( 0xFF0A0000U + 0x00000400U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_MIBSPI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pbist.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pbist.h new file mode 100644 index 00000000000..0879a7ece6d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pbist.h @@ -0,0 +1,98 @@ +/** @file reg_pbist.h + * @brief PBIST Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PBIST_H__ +#define __REG_PBIST_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* PBIST Register Frame Definition */ + +/** @struct pbistBase + * @brief PBIST Base Register Definition + * + * This structure is used to access the PBIST module registers. + */ + +/** @typedef pbistBASE_t + * @brief PBIST Register Frame Type Definition + * + * This type is used to access the PBIST Registers. + */ +typedef volatile struct pbistBase +{ + uint32 RAMT; /* 0x0160: RAM Configuration Register */ + uint32 DLR; /* 0x0164: Datalogger Register */ + uint32 rsvd1[ 6U ]; /* 0x0168 */ + uint32 PACT; /* 0x0180: PBIST Activate Register */ + uint32 PBISTID; /* 0x0184: PBIST ID Register */ + uint32 OVER; /* 0x0188: Override Register */ + uint32 rsvd2; /* 0x018C */ + uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */ + uint32 rsvd5; /* 0x0194 */ + uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */ + uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */ + uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */ + uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */ + uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */ + uint32 rsvd3; /* 0x01AC */ + uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */ + uint32 rsvd4[ 3U ]; /* 0x01B4 */ + uint32 ROM; /* 0x01C0: ROM Mask Register */ + uint32 ALGO; /* 0x01C4: Algorithm Mask Register */ + uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */ + uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */ +} pbistBASE_t; + +#define pbistREG ( ( pbistBASE_t * ) 0xFFFFE560U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_PBIST_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pcr.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pcr.h new file mode 100644 index 00000000000..a8804c26e6a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pcr.h @@ -0,0 +1,113 @@ +/** @file reg_pcr.h + * @brief PCR Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PCR_H__ +#define __REG_PCR_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Pcr Register Frame Definition */ + +/** @struct pcrBase + * @brief Pcr Register Frame Definition + * + * This type is used to access the Pcr Registers. + */ + +/** @typedef pcrBASE_t + * @brief PCR Register Frame Type Definition + * + * This type is used to access the PCR Registers. + */ +typedef volatile struct pcrBase +{ + uint32 PMPROTSET0; /* 0x0000 */ + uint32 PMPROTSET1; /* 0x0004 */ + uint32 rsvd1[ 2U ]; /* 0x0008 */ + uint32 PMPROTCLR0; /* 0x0010 */ + uint32 PMPROTCLR1; /* 0x0014 */ + uint32 rsvd2[ 2U ]; /* 0x0018 */ + uint32 PPROTSET0; /* 0x0020 */ + uint32 PPROTSET1; /* 0x0024 */ + uint32 PPROTSET2; /* 0x0028 */ + uint32 PPROTSET3; /* 0x002C */ + uint32 rsvd3[ 4U ]; /* 0x0030 */ + uint32 PPROTCLR0; /* 0x0040 */ + uint32 PPROTCLR1; /* 0x0044 */ + uint32 PPROTCLR2; /* 0x0048 */ + uint32 PPROTCLR3; /* 0x004C */ + uint32 rsvd4[ 4U ]; /* 0x0050 */ + uint32 PCSPWRDWNSET0; /* 0x0060 */ + uint32 PCSPWRDWNSET1; /* 0x0064 */ + uint32 rsvd5[ 2U ]; /* 0x0068 */ + uint32 PCSPWRDWNCLR0; /* 0x0070 */ + uint32 PCSPWRDWNCLR1; /* 0x0074 */ + uint32 rsvd6[ 2U ]; /* 0x0078 */ + uint32 PSPWRDWNSET0; /* 0x0080 */ + uint32 PSPWRDWNSET1; /* 0x0084 */ + uint32 PSPWRDWNSET2; /* 0x0088 */ + uint32 PSPWRDWNSET3; /* 0x008C */ + uint32 rsvd7[ 4U ]; /* 0x0090 */ + uint32 PSPWRDWNCLR0; /* 0x00A0 */ + uint32 PSPWRDWNCLR1; /* 0x00A4 */ + uint32 PSPWRDWNCLR2; /* 0x00A8 */ + uint32 PSPWRDWNCLR3; /* 0x00AC */ +} pcrBASE_t; + +/** @def pcrREG + * @brief Pcr Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr registers. + */ +#define pcrREG ( ( pcrBASE_t * ) 0xFFFFE000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_PCR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pinmux.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pinmux.h new file mode 100644 index 00000000000..d819ea9812c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pinmux.h @@ -0,0 +1,178 @@ +/** @file reg_pinmux.h + * @brief PINMUX Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PINMUX driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PINMUX_H__ +#define __REG_PINMUX_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* IOMM Revision and Boot Register */ +#define REVISION_REG ( *( volatile uint32 * ) 0xFFFFEA00U ) +#define ENDIAN_REG ( *( volatile uint32 * ) 0xFFFFEA20U ) + +/* IOMM Error and Fault Registers */ + +/** @struct iommErrFault + * @brief IOMM Error and Fault Register Definition + * + * This structure is used to access the IOMM Error and Fault registers. + */ +typedef volatile struct iommErrFault +{ + uint32 ERR_RAW_STATUS_REG; /* Error Raw Status / Set Register */ + uint32 ERR_ENABLED_STATUS_REG; /* Error Enabled Status / Clear Register */ + uint32 ERR_ENABLE_REG; /* Error Signaling Enable Register */ + uint32 ERR_ENABLE_CLR_REG; /* Error Signaling Enable Clear Register */ + uint32 rsvd; /* Reserved */ + uint32 FAULT_ADDRESS_REG; /* Fault Address Register */ + uint32 FAULT_STATUS_REG; /* Fault Status Register */ + uint32 FAULT_CLEAR_REG; /* Fault Clear Register */ +} iommErrFault_t; +/* Pinmux Register Frame Definition */ + +/** @struct pinMuxKicker + * @brief Pin Muxing Kicker Register Definition + * + * This structure is used to access the Pin Muxing Kicker registers. + */ +typedef volatile struct pinMuxKicker +{ + uint32 KICKER0; /* kicker 0 register */ + uint32 KICKER1; /* kicker 1 register */ +} pinMuxKICKER_t; + +/** @struct pinMuxBase + * @brief PINMUX Register Definition + * + * This structure is used to access the PINMUX module registers. + */ + +/** @typedef pinMuxBASE_t + * @brief PINMUX Register Frame Type Definition + * + * This type is used to access the PINMUX Registers. + */ +typedef volatile struct pinMuxBase +{ + uint32 PINMMR0; /**< 0xEB10 Pin Mux 0 register*/ + uint32 PINMMR1; /**< 0xEB14 Pin Mux 1 register*/ + uint32 PINMMR2; /**< 0xEB18 Pin Mux 2 register*/ + uint32 PINMMR3; /**< 0xEB1C Pin Mux 3 register*/ + uint32 PINMMR4; /**< 0xEB20 Pin Mux 4 register*/ + uint32 PINMMR5; /**< 0xEB24 Pin Mux 5 register*/ + uint32 PINMMR6; /**< 0xEB28 Pin Mux 6 register*/ + uint32 PINMMR7; /**< 0xEB2C Pin Mux 7 register*/ + uint32 PINMMR8; /**< 0xEB30 Pin Mux 8 register*/ + uint32 PINMMR9; /**< 0xEB34 Pin Mux 9 register*/ + uint32 PINMMR10; /**< 0xEB38 Pin Mux 10 register*/ + uint32 PINMMR11; /**< 0xEB3C Pin Mux 11 register*/ + uint32 PINMMR12; /**< 0xEB40 Pin Mux 12 register*/ + uint32 PINMMR13; /**< 0xEB44 Pin Mux 13 register*/ + uint32 PINMMR14; /**< 0xEB48 Pin Mux 14 register*/ + uint32 PINMMR15; /**< 0xEB4C Pin Mux 15 register*/ + uint32 PINMMR16; /**< 0xEB50 Pin Mux 16 register*/ + uint32 PINMMR17; /**< 0xEB54 Pin Mux 17 register*/ + uint32 PINMMR18; /**< 0xEB58 Pin Mux 18 register*/ + uint32 PINMMR19; /**< 0xEB5C Pin Mux 19 register*/ + uint32 PINMMR20; /**< 0xEB60 Pin Mux 20 register*/ + uint32 PINMMR21; /**< 0xEB64 Pin Mux 21 register*/ + uint32 PINMMR22; /**< 0xEB68 Pin Mux 22 register*/ + uint32 PINMMR23; /**< 0xEB6C Pin Mux 23 register*/ + uint32 PINMMR24; /**< 0xEB70 Pin Mux 24 register*/ + uint32 PINMMR25; /**< 0xEB74 Pin Mux 25 register*/ + uint32 PINMMR26; /**< 0xEB78 Pin Mux 26 register*/ + uint32 PINMMR27; /**< 0xEB7C Pin Mux 27 register*/ + uint32 PINMMR28; /**< 0xEB80 Pin Mux 28 register*/ + uint32 PINMMR29; /**< 0xEB84 Pin Mux 29 register*/ + uint32 PINMMR30; /**< 0xEB88 Pin Mux 30 register*/ + uint32 PINMMR31; /**< 0xEB8C Pin Mux 31 register*/ + uint32 PINMMR32; /**< 0xEB90 Pin Mux 32 register*/ + uint32 PINMMR33; /**< 0xEB94 Pin Mux 33 register*/ + uint32 PINMMR34; /**< 0xEB98 Pin Mux 34 register*/ + uint32 PINMMR35; /**< 0xEB9C Pin Mux 35 register*/ + uint32 PINMMR36; /**< 0xEBA0 Pin Mux 36 register*/ + uint32 PINMMR37; /**< 0xEBA4 Pin Mux 37 register*/ + uint32 PINMMR38; /**< 0xEBA8 Pin Mux 38 register*/ + uint32 PINMMR39; /**< 0xEBAC Pin Mux 39 register*/ + uint32 PINMMR40; /**< 0xEBB0 Pin Mux 40 register*/ + uint32 PINMMR41; /**< 0xEBB4 Pin Mux 41 register*/ + uint32 PINMMR42; /**< 0xEBB8 Pin Mux 42 register*/ + uint32 PINMMR43; /**< 0xEBBC Pin Mux 43 register*/ + uint32 PINMMR44; /**< 0xEBC0 Pin Mux 44 register*/ + uint32 PINMMR45; /**< 0xEBC4 Pin Mux 45 register*/ + uint32 PINMMR46; /**< 0xEBC8 Pin Mux 46 register*/ + uint32 PINMMR47; /**< 0xEBCC Pin Mux 47 register*/ +} pinMuxBASE_t; + +/** @def iommErrFaultReg + * @brief IOMM Error Fault Register Frame Pointer + * + * This pointer is used to control IOMM Error and Fault across the device. + */ +#define iommErrFaultReg ( ( iommErrFault_t * ) 0xFFFFEAE0U ) + +/** @def kickerReg + * @brief Pin Muxing Kicker Register Frame Pointer + * + * This pointer is used to enable and disable muxing accross the device. + */ +#define kickerReg ( ( pinMuxKICKER_t * ) 0xFFFFEA38U ) + +/** @def pinMuxReg + * @brief Pin Muxing Control Register Frame Pointer + * + * This pointer is used to set the muxing registers accross the device. + */ +#define pinMuxReg ( ( pinMuxBASE_t * ) 0xFFFFEB10U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_PINMUX_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pmm.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pmm.h new file mode 100644 index 00000000000..47040a3c037 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pmm.h @@ -0,0 +1,114 @@ +/** @file reg_pmm.h + * @brief PMM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the PMM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PMM_H__ +#define __REG_PMM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Pmm Register Frame Definition */ + +/** @struct pmmBase + * @brief Pmm Register Frame Definition + * + * This type is used to access the Pmm Registers. + */ + +/** @typedef pmmBase_t + * @brief Pmm Register Frame Type Definition + * + * This type is used to access the Pmm Registers. + */ +typedef volatile struct pmmBase +{ + uint32 LOGICPDPWRCTRL0; /**< 0x0000: Logic Power Domain Control Register 0 */ + uint32 rsvd1[ 3U ]; /**< 0x0004: Reserved*/ + uint32 MEMPDPWRCTRL0; /**< 0x0010: Memory Power Domain Control Register 0 */ + uint32 rsvd2[ 3U ]; /**< 0x0014: Reserved*/ + uint32 PDCLKDISREG; /**< 0x0020: Power Domain Clock Disable Register */ + uint32 PDCLKDISSETREG; /**< 0x0024: Power Domain Clock Disable Set Register */ + uint32 PDCLKDISCLRREG; /**< 0x0028: Power Domain Clock Disable Clear Register */ + uint32 rsvd3[ 5U ]; /**< 0x002C: Reserved */ + uint32 LOGICPDPWRSTAT[ 4U ]; /**< 0x0040, 0x0044, 0x0048, 0x004C: Logic Power Domain + * Power Status Register + * - 0: PD2 + * - 1: PD3 + * - 2: PD4 + * - 3: PD5 */ + uint32 rsvd4[ 12U ]; /**< 0x0050: Reserved*/ + uint32 MEMPDPWRSTAT[ 3U ]; /**< 0x0080, 0x0084, 0x0088: Memory Power Domain Power + * Status Register + * - 0: RAM_PD1 + * - 1: RAM_PD2 + * - 2: RAM_PD3 */ + uint32 rsvd5[ 5U ]; /**< 0x008C: Reserved */ + uint32 GLOBALCTRL1; /**< 0x00A0: Global Control Register 1 */ + uint32 rsvd6; /**< 0x00A4: Reserved */ + uint32 GLOBALSTAT; /**< 0x00A8: Global Status Register */ + uint32 PRCKEYREG; /**< 0x00AC: PSCON Diagnostic Compare Key Register */ + uint32 LPDDCSTAT1; /**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */ + uint32 LPDDCSTAT2; /**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */ + uint32 MPDDCSTAT1; /**< 0x00B8: Memory PD PSCON Diagnostic Compare Status Register 1 + */ + uint32 MPDDCSTAT2; /**< 0x00BC: Memory PD PSCON Diagnostic Compare Status Register 2 + */ + uint32 ISODIAGSTAT; /**< 0x00C0: Isolation Diagnostic Status Register */ +} pmmBase_t; + +/** @def pmmREG + * @brief Pmm Register Frame Pointer + * + * This pointer is used by the Pmm driver to access the Pmm registers. + */ +#define pmmREG ( ( pmmBase_t * ) 0xFFFF0000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_PMM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pom.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pom.h new file mode 100644 index 00000000000..0e6e4c2b52d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_pom.h @@ -0,0 +1,122 @@ +/** @file reg_pom.h + * @brief POM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the POM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_POM_H__ +#define __REG_POM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Pom Register Frame Definition */ + +/** @struct POMBase + * @brief POM Register Frame Definition + * + * This structure is used to access the POM module registers(POM Register Map). + */ +typedef struct +{ + uint32 POMGLBCTRL; /* 0x00 */ + uint32 POMREV; /* 0x04 */ + uint32 POMCLKCTRL; /* 0x08 */ + uint32 POMFLG; /* 0x0C */ + struct + { + uint32 rsdv1; + } RESERVED_REG[ 124U ]; + struct /* 0x200 ... */ + { + uint32 POMPROGSTART; + uint32 POMOVLSTART; + uint32 POMREGSIZE; + uint32 rsdv2; + } POMRGNCONF_ST[ 32U ]; +} pomBASE_t; + +/** @struct POM_CORESIGHT_ST + * @brief POM_CORESIGHT_ST Register Definition + * + * This structure is used to access the POM module registers(POM CoreSight Registers ). + */ +typedef struct +{ + uint32 POMITCTRL; /* 0xF00 */ + struct /* 0xF04 to 0xF9C */ + { + uint32 Reserved_Reg; + } Reserved1_ST[ 39U ]; + uint32 POMCLAIMSET; /* 0xFA0 */ + uint32 POMCLAIMCLR; /* 0xFA4 */ + uint32 rsvd1[ 2U ]; /* 0xFA8 */ + uint32 POMLOCKACCESS; /* 0xFB0 */ + uint32 POMLOCKSTATUS; /* 0xFB4 */ + uint32 POMAUTHSTATUS; /* 0xFB8 */ + uint32 rsvd2[ 3U ]; /* 0xFBC */ + uint32 POMDEVID; /* 0xFC8 */ + uint32 POMDEVTYPE; /* 0xFCC */ + uint32 POMPERIPHERALID4; /* 0xFD0 */ + uint32 POMPERIPHERALID5; /* 0xFD4 */ + uint32 POMPERIPHERALID6; /* 0xFD8 */ + uint32 POMPERIPHERALID7; /* 0xFDC */ + uint32 POMPERIPHERALID0; /* 0xFE0 */ + uint32 POMPERIPHERALID1; /* 0xFE4 */ + uint32 POMPERIPHERALID2; /* 0xFE8 */ + uint32 POMPERIPHERALID3; /* 0xFEC */ + uint32 POMCOMPONENTID0; /* 0xFF0 */ + uint32 POMCOMPONENTID1; /* 0xFF4 */ + uint32 POMCOMPONENTID2; /* 0xFF8 */ + uint32 POMCOMPONENTID3; /* 0xFFC */ +} POM_CORESIGHT_ST; + +#define pomREG ( ( pomBASE_t * ) 0xFFA04000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_POM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_sci.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_sci.h new file mode 100644 index 00000000000..418d2108610 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_sci.h @@ -0,0 +1,134 @@ +/** @file reg_sci.h + * @brief SCI Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the SCI driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_SCI_H__ +#define __REG_SCI_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Sci Register Frame Definition */ + +/** @struct sciBase + * @brief SCI Base Register Definition + * + * This structure is used to access the SCI module registers. + */ + +/** @typedef sciBASE_t + * @brief SCI Register Frame Type Definition + * + * This type is used to access the SCI Registers. + */ +typedef volatile struct sciBase +{ + uint32 GCR0; /**< 0x0000 Global Control Register 0 */ + uint32 GCR1; /**< 0x0004 Global Control Register 1 */ + uint32 GCR2; /**< 0x0008 Global Control Register 2. Note: Applicable only to LIN – SCI + Compatibility Mode,Reserved for standalone SCI*/ + uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */ + uint32 CLEARINT; /**< 0x0010 Clear Interrupt Enable Register */ + uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */ + uint32 CLEARINTLVL; /**< 0x0018 Set Interrupt Level Register */ + uint32 FLR; /**< 0x001C Interrupt Flag Register */ + uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */ + uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */ + uint32 FORMAT; /**< 0x0028 Format Control Register */ + uint32 BRS; /**< 0x002C Baud Rate Selection Register */ + uint32 ED; /**< 0x0030 Emulation Register */ + uint32 RD; /**< 0x0034 Receive Data Buffer */ + uint32 TD; /**< 0x0038 Transmit Data Buffer */ + uint32 PIO0; /**< 0x003C Pin Function Register */ + uint32 PIO1; /**< 0x0040 Pin Direction Register */ + uint32 PIO2; /**< 0x0044 Pin Data In Register */ + uint32 PIO3; /**< 0x0048 Pin Data Out Register */ + uint32 PIO4; /**< 0x004C Pin Data Set Register */ + uint32 PIO5; /**< 0x0050 Pin Data Clr Register */ + uint32 PIO6; /**< 0x0054: Pin Open Drain Output Enable Register */ + uint32 PIO7; /**< 0x0058: Pin Pullup/Pulldown Disable Register */ + uint32 PIO8; /**< 0x005C: Pin Pullup/Pulldown Selection Register */ + uint32 rsdv2[ 12U ]; /**< 0x0060: Reserved */ + uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */ +} sciBASE_t; + +/** @def sciREG + * @brief Register Frame Pointer + * + * This pointer is used by the SCI driver to access the sci module registers. + */ +#define sciREG ( ( sciBASE_t * ) 0xFFF7E500U ) + +/** @def sciPORT + * @brief SCI GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of SCI + * (use the GIO drivers to access the port pins). + */ +#define sciPORT ( ( gioPORT_t * ) 0xFFF7E540U ) + +/** @def scilinREG + * @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer + * + * This pointer is used by the SCI driver to access the sci module registers. + */ +#define scilinREG ( ( sciBASE_t * ) 0xFFF7E400U ) + +/** @def scilinPORT + * @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN + * (use the GIO drivers to access the port pins). + */ +#define scilinPORT ( ( gioPORT_t * ) 0xFFF7E440U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_SCI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_spi.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_spi.h new file mode 100644 index 00000000000..ef7e8b2f680 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_spi.h @@ -0,0 +1,180 @@ +/** @file reg_spi.h + * @brief SPI Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the SPI driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_SPI_H__ +#define __REG_SPI_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Spi Register Frame Definition */ + +/** @struct spiBase + * @brief SPI Register Definition + * + * This structure is used to access the SPI module registers. + */ + +/** @typedef spiBASE_t + * @brief SPI Register Frame Type Definition + * + * This type is used to access the SPI Registers. + */ +typedef volatile struct spiBase +{ + uint32 GCR0; /**< 0x0000: Global Control 0 */ + uint32 GCR1; /**< 0x0004: Global Control 1 */ + uint32 INT0; /**< 0x0008: Interrupt Register */ + uint32 LVL; /**< 0x000C: Interrupt Level */ + uint32 FLG; /**< 0x0010: Interrupt flags */ + uint32 PC0; /**< 0x0014: Function Pin Enable */ + uint32 PC1; /**< 0x0018: Pin Direction */ + uint32 PC2; /**< 0x001C: Pin Input Latch */ + uint32 PC3; /**< 0x0020: Pin Output Latch */ + uint32 PC4; /**< 0x0024: Output Pin Set */ + uint32 PC5; /**< 0x0028: Output Pin Clr */ + uint32 PC6; /**< 0x002C: Open Drain Output Enable */ + uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */ + uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */ + uint32 DAT0; /**< 0x0038: Transmit Data */ + uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ + uint32 BUF; /**< 0x0040: Receive Buffer */ + uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ + uint32 DELAY; /**< 0x0048: Delays */ + uint32 DEF; /**< 0x004C: Default Chip Select */ + uint32 FMT0; /**< 0x0050: Data Format 0 */ + uint32 FMT1; /**< 0x0054: Data Format 1 */ + uint32 FMT2; /**< 0x0058: Data Format 2 */ + uint32 FMT3; /**< 0x005C: Data Format 3 */ + uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ + uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ + uint32 RESERVED[ 51U ]; /**< 0x0068 to 0x0130: Reserved */ + uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ +} spiBASE_t; + +/** @def spiREG1 + * @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer + * + * This pointer is used by the SPI driver to access the spi module registers. + */ +#define spiREG1 ( ( spiBASE_t * ) 0xFFF7F400U ) + +/** @def spiPORT1 + * @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of SPI1 + * (use the GIO drivers to access the port pins). + */ +#define spiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U ) + +/** @def spiREG2 + * @brief SPI2 Register Frame Pointer + * + * This pointer is used by the SPI driver to access the spi module registers. + */ +#define spiREG2 ( ( spiBASE_t * ) 0xFFF7F600U ) + +/** @def spiPORT2 + * @brief SPI2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of SPI2 + * (use the GIO drivers to access the port pins). + */ +#define spiPORT2 ( ( gioPORT_t * ) 0xFFF7F618U ) + +/** @def spiREG3 + * @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer + * + * This pointer is used by the SPI driver to access the spi module registers. + */ +#define spiREG3 ( ( spiBASE_t * ) 0xFFF7F800U ) + +/** @def spiPORT3 + * @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of SPI3 + * (use the GIO drivers to access the port pins). + */ +#define spiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U ) + +/** @def spiREG4 + * @brief SPI4 Register Frame Pointer + * + * This pointer is used by the SPI driver to access the spi module registers. + */ +#define spiREG4 ( ( spiBASE_t * ) 0xFFF7FA00U ) + +/** @def spiPORT4 + * @brief SPI4 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of SPI4 + * (use the GIO drivers to access the port pins). + */ +#define spiPORT4 ( ( gioPORT_t * ) 0xFFF7FA18U ) + +/** @def spiREG5 + * @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer + * + * This pointer is used by the SPI driver to access the spi module registers. + */ +#define spiREG5 ( ( spiBASE_t * ) 0xFFF7FC00U ) + +/** @def spiPORT5 + * @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of SPI5 + * (use the GIO drivers to access the port pins). + */ +#define spiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_SPI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_stc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_stc.h new file mode 100644 index 00000000000..f718f1ada01 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_stc.h @@ -0,0 +1,93 @@ +/** @file reg_stc.h + * @brief STC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_STC_H__ +#define __REG_STC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Stc Register Frame Definition */ + +/** @struct stcBase + * @brief STC Base Register Definition + * + * This structure is used to access the STC module registers. + */ + +/** @typedef stcBASE_t + * @brief STC Register Frame Type Definition + * + * This type is used to access the STC Registers. + */ +typedef volatile struct stcBase +{ + uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */ + uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */ + uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */ + uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */ + uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */ + uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */ + uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */ + uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */ + uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */ + uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */ + uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */ + uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */ + uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */ + uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */ + uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */ + uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */ +} stcBASE_t; + +#define stcREG ( ( stcBASE_t * ) 0xFFFFE600U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_STC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_system.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_system.h new file mode 100644 index 00000000000..0f4a0ccc884 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_system.h @@ -0,0 +1,191 @@ +/** @file reg_system.h + * @brief System Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_SYSTEM_H__ +#define __REG_SYSTEM_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* System Register Frame 1 Definition */ + +/** @struct systemBase1 + * @brief System Register Frame 1 Definition + * + * This type is used to access the System 1 Registers. + */ + +/** @typedef systemBASE1_t + * @brief System Register Frame 1 Type Definition + * + * This type is used to access the System 1 Registers. + */ +typedef volatile struct systemBase1 +{ + uint32 SYSPC1; /* 0x0000 */ + uint32 SYSPC2; /* 0x0004 */ + uint32 SYSPC3; /* 0x0008 */ + uint32 SYSPC4; /* 0x000C */ + uint32 SYSPC5; /* 0x0010 */ + uint32 SYSPC6; /* 0x0014 */ + uint32 SYSPC7; /* 0x0018 */ + uint32 SYSPC8; /* 0x001C */ + uint32 SYSPC9; /* 0x0020 */ + uint32 SSWPLL1; /* 0x0024 */ + uint32 SSWPLL2; /* 0x0028 */ + uint32 SSWPLL3; /* 0x002C */ + uint32 CSDIS; /* 0x0030 */ + uint32 CSDISSET; /* 0x0034 */ + uint32 CSDISCLR; /* 0x0038 */ + uint32 CDDIS; /* 0x003C */ + uint32 CDDISSET; /* 0x0040 */ + uint32 CDDISCLR; /* 0x0044 */ + uint32 GHVSRC; /* 0x0048 */ + uint32 VCLKASRC; /* 0x004C */ + uint32 RCLKSRC; /* 0x0050 */ + uint32 CSVSTAT; /* 0x0054 */ + uint32 MSTGCR; /* 0x0058 */ + uint32 MINITGCR; /* 0x005C */ + uint32 MSINENA; /* 0x0060 */ + uint32 MSTFAIL; /* 0x0064 */ + uint32 MSTCGSTAT; /* 0x0068 */ + uint32 MINISTAT; /* 0x006C */ + uint32 PLLCTL1; /* 0x0070 */ + uint32 PLLCTL2; /* 0x0074 */ + uint32 SYSPC10; /* 0x0078 */ + uint32 DIEIDL; /* 0x007C */ + uint32 DIEIDH; /* 0x0080 */ + uint32 VRCTL; /* 0x0084 */ + uint32 LPOMONCTL; /* 0x0088 */ + uint32 CLKTEST; /* 0x008C */ + uint32 DFTCTRLREG1; /* 0x0090 */ + uint32 DFTCTRLREG2; /* 0x0094 */ + uint32 rsvd1; /* 0x0098 */ + uint32 rsvd2; /* 0x009C */ + uint32 GPREG1; /* 0x00A0 */ + uint32 BTRMSEL; /* 0x00A4 */ + uint32 IMPFASTS; /* 0x00A8 */ + uint32 IMPFTADD; /* 0x00AC */ + uint32 SSISR1; /* 0x00B0 */ + uint32 SSISR2; /* 0x00B4 */ + uint32 SSISR3; /* 0x00B8 */ + uint32 SSISR4; /* 0x00BC */ + uint32 RAMGCR; /* 0x00C0 */ + uint32 BMMCR1; /* 0x00C4 */ + uint32 BMMCR2; /* 0x00C8 */ + uint32 CPURSTCR; /* 0x00CC */ + uint32 CLKCNTL; /* 0x00D0 */ + uint32 ECPCNTL; /* 0x00D4 */ + uint32 DSPGCR; /* 0x00D8 */ + uint32 DEVCR1; /* 0x00DC */ + uint32 SYSECR; /* 0x00E0 */ + uint32 SYSESR; /* 0x00E4 */ + uint32 SYSTASR; /* 0x00E8 */ + uint32 GBLSTAT; /* 0x00EC */ + uint32 DEV; /* 0x00F0 */ + uint32 SSIVEC; /* 0x00F4 */ + uint32 SSIF; /* 0x00F8 */ +} systemBASE1_t; + +/** @def systemREG1 + * @brief System Register Frame 1 Pointer + * + * This pointer is used by the system driver to access the system frame 1 registers. + */ +#define systemREG1 ( ( systemBASE1_t * ) 0xFFFFFF00U ) + +/** @def systemPORT + * @brief ECLK GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of System/Eclk + * (use the GIO drivers to access the port pins). + */ +#define systemPORT ( ( gioPORT_t * ) 0xFFFFFF04U ) + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* System Register Frame 2 Definition */ + +/** @struct systemBase2 + * @brief System Register Frame 2 Definition + * + * This type is used to access the System 2 Registers. + */ + +/** @typedef systemBASE2_t + * @brief System Register Frame 2 Type Definition + * + * This type is used to access the System 2 Registers. + */ +typedef volatile struct systemBase2 +{ + uint32 PLLCTL3; /* 0x0000 */ + uint32 rsvd1; /* 0x0004 */ + uint32 STCCLKDIV; /* 0x0008 */ + uint32 rsvd2[ 6U ]; /* 0x000C */ + uint32 ECPCNTRL0; /* 0x0024 */ + uint32 rsvd3[ 5U ]; /* 0x0028 */ + uint32 CLK2CNTL; /* 0x003C */ + uint32 VCLKACON1; /* 0x0040 */ + uint32 rsvd4[ 11U ]; /* 0x0044 */ + uint32 CLKSLIP; /* 0x0070 */ + uint32 rsvd5[ 30U ]; /* 0x0074 */ + uint32 EFC_CTLEN; /* 0x00EC */ + uint32 DIEIDL_REG0; /* 0x00F0 */ + uint32 DIEIDH_REG1; /* 0x00F4 */ + uint32 DIEIDL_REG2; /* 0x00F8 */ + uint32 DIEIDH_REG3; /* 0x00FC */ +} systemBASE2_t; + +/** @def systemREG2 + * @brief System Register Frame 2 Pointer + * + * This pointer is used by the system driver to access the system frame 2 registers. + */ +#define systemREG2 ( ( systemBASE2_t * ) 0xFFFFE100U ) + +#endif /* ifndef __REG_SYSTEM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_tcram.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_tcram.h new file mode 100644 index 00000000000..c1339e58679 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_tcram.h @@ -0,0 +1,95 @@ +/** @file reg_tcram.h + * @brief TCRAM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_TCRAM_H__ +#define __REG_TCRAM_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Tcram Register Frame Definition */ + +/** @struct tcramBase + * @brief TCRAM Wrapper Register Frame Definition + * + * This type is used to access the TCRAM Wrapper Registers. + */ + +/** @typedef tcramBASE_t + * @brief TCRAM Wrapper Register Frame Type Definition + * + * This type is used to access the TCRAM Wrapper Registers. + */ + +typedef volatile struct tcramBase +{ + uint32 RAMCTRL; /* 0x0000 */ + uint32 RAMTHRESHOLD; /* 0x0004 */ + uint32 RAMOCCUR; /* 0x0008 */ + uint32 RAMINTCTRL; /* 0x000C */ + uint32 RAMERRSTATUS; /* 0x0010 */ + uint32 RAMSERRADDR; /* 0x0014 */ + uint32 rsvd1; /* 0x0018 */ + uint32 RAMUERRADDR; /* 0x001C */ + uint32 rsvd2[ 4U ]; /* 0x0020 */ + uint32 RAMTEST; /* 0x0030 */ + uint32 rsvd3; /* 0x0034 */ + uint32 RAMADDRDECVECT; /* 0x0038 */ + uint32 RAMPERADDR; /* 0x003C */ +} tcramBASE_t; + +#define tcram1REG ( ( tcramBASE_t * ) ( 0xFFFFF800U ) ) +#define tcram2REG ( ( tcramBASE_t * ) ( 0xFFFFF900U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* ifndef __REG_TCRAM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_vim.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_vim.h new file mode 100644 index 00000000000..6d030851e2d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/reg_vim.h @@ -0,0 +1,110 @@ +/** @file reg_vim.h + * @brief VIM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_VIM_H__ +#define __REG_VIM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Vim Register Frame Definition */ + +/** @struct vimBase + * @brief Vim Register Frame Definition + * + * This type is used to access the Vim Registers. + */ + +/** @typedef vimBASE_t + * @brief VIM Register Frame Type Definition + * + * This type is used to access the VIM Registers. + */ +typedef volatile struct vimBase +{ + uint32 IRQINDEX; /* 0x0000 */ + uint32 FIQINDEX; /* 0x0004 */ + uint32 rsvd1; /* 0x0008 */ + uint32 rsvd2; /* 0x000C */ + uint32 FIRQPR0; /* 0x0010 */ + uint32 FIRQPR1; /* 0x0014 */ + uint32 FIRQPR2; /* 0x0018 */ + uint32 FIRQPR3; /* 0x001C */ + uint32 INTREQ0; /* 0x0020 */ + uint32 INTREQ1; /* 0x0024 */ + uint32 INTREQ2; /* 0x0028 */ + uint32 INTREQ3; /* 0x002C */ + uint32 REQMASKSET0; /* 0x0030 */ + uint32 REQMASKSET1; /* 0x0034 */ + uint32 REQMASKSET2; /* 0x0038 */ + uint32 REQMASKSET3; /* 0x003C */ + uint32 REQMASKCLR0; /* 0x0040 */ + uint32 REQMASKCLR1; /* 0x0044 */ + uint32 REQMASKCLR2; /* 0x0048 */ + uint32 REQMASKCLR3; /* 0x004C */ + uint32 WAKEMASKSET0; /* 0x0050 */ + uint32 WAKEMASKSET1; /* 0x0054 */ + uint32 WAKEMASKSET2; /* 0x0058 */ + uint32 WAKEMASKSET3; /* 0x005C */ + uint32 WAKEMASKCLR0; /* 0x0060 */ + uint32 WAKEMASKCLR1; /* 0x0064 */ + uint32 WAKEMASKCLR2; /* 0x0068 */ + uint32 WAKEMASKCLR3; /* 0x006C */ + uint32 IRQVECREG; /* 0x0070 */ + uint32 FIQVECREG; /* 0x0074 */ + uint32 CAPEVT; /* 0x0078 */ + uint32 rsvd3; /* 0x007C */ + uint32 CHANCTRL[ 32U ]; /* 0x0080-0x0FC */ +} vimBASE_t; + +#define vimREG ( ( vimBASE_t * ) 0xFFFFFE00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* ifndef __REG_VIM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sci.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sci.h new file mode 100644 index 00000000000..6f4c70c0645 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sci.h @@ -0,0 +1,254 @@ +/** @file sci.h + * @brief SCI Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SCI_H__ +#define __SCI_H__ + +#include "reg_sci.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum sciIntFlags + * @brief Interrupt Flag Definitions + * + * Used with sciEnableNotification, sciDisableNotification + */ +enum sciIntFlags +{ + SCI_FE_INT = 0x04000000U, /* framing error */ + SCI_OE_INT = 0x02000000U, /* overrun error */ + SCI_PE_INT = 0x01000000U, /* parity error */ + SCI_RX_INT = 0x00000200U, /* receive buffer ready */ + SCI_TX_INT = 0x00000100U, /* transmit buffer ready */ + SCI_WAKE_INT = 0x00000002U, /* wakeup */ + SCI_BREAK_INT = 0x00000001U /* break detect */ +}; + +/** @def SCI_IDLE + * @brief Alias name for the SCI IDLE Flag + * + * This is an alias name for the SCI IDLE Flag. + * + */ +#define SCI_IDLE 0x00000004U + +/** @struct sciBase + * @brief SCI Register Definition + * + * This structure is used to access the SCI module registers. + */ + +/** @typedef sciBASE_t + * @brief SCI Register Frame Type Definition + * + * This type is used to access the SCI Registers. + */ + +enum sciPinSelect +{ + PIN_SCI_TX = 4U, + PIN_SCI_RX = 2U +}; + +/* Configuration registers */ +typedef struct sci_config_reg +{ + uint32 CONFIG_GCR0; + uint32 CONFIG_GCR1; + uint32 CONFIG_SETINT; + uint32 CONFIG_SETINTLVL; + uint32 CONFIG_FORMAT; + uint32 CONFIG_BRS; + uint32 CONFIG_PIO0; + uint32 CONFIG_PIO1; + uint32 CONFIG_PIO6; + uint32 CONFIG_PIO7; + uint32 CONFIG_PIO8; +} sci_config_reg_t; + +/* Configuration registers initial value for SCI*/ +#define SCI_GCR0_CONFIGVALUE 0x00000001U +#define SCI_GCR1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 5U ) | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( 0x03000080U ) ) + +#define SCI_SETINTLVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SCI_SETINT_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SCI_FORMAT_CONFIGVALUE ( 8U - 1U ) +#define SCI_BRS_CONFIGVALUE ( 59U ) +#define SCI_PIO0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) +#define SCI_PIO1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define SCI_PIO6_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define SCI_PIO7_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define SCI_PIO8_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) + +/* Configuration registers initial value for SCI*/ +#define SCILIN_GCR0_CONFIGVALUE 0x00000001U +#define SCILIN_GCR1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 5U ) | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( 0x03000080U ) ) + +#define SCILIN_SETINTLVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define SCILIN_SETINT_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SCILIN_FORMAT_CONFIGVALUE ( 8U - 1U ) +#define SCILIN_BRS_CONFIGVALUE ( 59U ) +#define SCILIN_PIO0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) +#define SCILIN_PIO1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define SCILIN_PIO6_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define SCILIN_PIO7_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define SCILIN_PIO8_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) ) + +/** + * @defgroup SCI SCI + * @brief Serial Communication Interface Module. + * + * The SCI module is a universal asynchronous receiver-transmitter that implements the + *standard nonreturn to zero format. The SCI can be used to communicate, for example, + *through an RS-232 port or over a K-line. + * + * Related Files + * - reg_sci.h + * - sci.h + * - sci.c + * @addtogroup SCI + * @{ + */ + +/* SCI Interface Functions */ +void sciInit( void ); +void sciSetFunctional( sciBASE_t * sci, uint32 port ); +void sciSetBaudrate( sciBASE_t * sci, uint32 baud ); +uint32 sciIsTxReady( sciBASE_t * sci ); +void sciSendByte( sciBASE_t * sci, uint8 byte ); +void sciSend( sciBASE_t * sci, uint32 length, uint8 * data ); +uint32 sciIsRxReady( sciBASE_t * sci ); +uint32 sciIsIdleDetected( sciBASE_t * sci ); +uint32 sciRxError( sciBASE_t * sci ); +uint32 sciReceiveByte( sciBASE_t * sci ); +void sciReceive( sciBASE_t * sci, uint32 length, uint8 * data ); +void sciEnableNotification( sciBASE_t * sci, uint32 flags ); +void sciDisableNotification( sciBASE_t * sci, uint32 flags ); +void sciEnableLoopback( sciBASE_t * sci, loopBackType_t Loopbacktype ); +void sciDisableLoopback( sciBASE_t * sci ); +void sciEnterResetState( sciBASE_t * sci ); +void sciExitResetState( sciBASE_t * sci ); +void sciGetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ); +void scilinGetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ); + +/** @brief Interrupt callback + * @fn void sciNotification(sciBASE_t *sci, uint32 flags) + * @param[in] sci - sci module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void sciNotification( sciBASE_t * sci, uint32 flags ); + +/* USER CODE BEGIN (1) */ + +/** @brief Write data out to UART using the given SCI register + * @fn void sciDisplayData(sciBASE_t *sci, uint8 *text,uint32 length) + * @param[in] sci - SCI module base address + * @param[in] text - Pointer to the data that is going to be displayed on console + * @param[in] length - Number of bytes of data that are to be written + */ +void sciDisplayData( sciBASE_t * sci, uint8_t * text, uint32 length ); + +/** @brief Write text out to UART using the given SCI register + * @fn void sciDisplayText(sciBASE_t *sci, uint8 *text,uint32 length) + * @param[in] sci - SCI module base address + * @param[in] text - Pointer to the string that is going to be displayed on console + * @param[in] length - Number of characters that are to be written + */ +void sciDisplayText( sciBASE_t * sci, char * text, uint32 length ); + +/** @brief Simple print function that takes in a str and prints to SCI/UART + * @fn void sci_print(char * str) + * @param[in] str - String that is going to written out to UART + */ +void sci_print( char * str ); + +/* USER CODE END */ +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __SCI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/spi.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/spi.h new file mode 100644 index 00000000000..71ab34d6a4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/spi.h @@ -0,0 +1,370 @@ +/** @file spi.h + * @brief SPI Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SPI_H__ +#define __SPI_H__ + +#include "reg_spi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @enum chipSelect + * @brief Transfer Group Chip Select + */ +enum spiChipSelect +{ + SPI_CS_NONE = 0xFFU, + SPI_CS_0 = 0xFEU, + SPI_CS_1 = 0xFDU, + SPI_CS_2 = 0xFBU, + SPI_CS_3 = 0xF7U, + SPI_CS_4 = 0xEFU, + SPI_CS_5 = 0xDFU, + SPI_CS_6 = 0xBFU, + SPI_CS_7 = 0x7FU +}; + +/** @enum spiPinSelect + * @brief spi Pin Select + */ +enum spiPinSelect +{ + SPI_PIN_CS0 = 0U, + SPI_PIN_CS1 = 1U, + SPI_PIN_CS2 = 2U, + SPI_PIN_CS3 = 3U, + SPI_PIN_CS4 = 4U, + SPI_PIN_CS5 = 5U, + SPI_PIN_CS6 = 6U, + SPI_PIN_CS7 = 7U, + SPI_PIN_ENA = 8U, + SPI_PIN_CLK = 9U, + SPI_PIN_SIMO = 10U, + SPI_PIN_SOMI = 11U, + SPI_PIN_SIMO_1 = 17U, + SPI_PIN_SIMO_2 = 18U, + SPI_PIN_SIMO_3 = 19U, + SPI_PIN_SIMO_4 = 20U, + SPI_PIN_SIMO_5 = 21U, + SPI_PIN_SIMO_6 = 22U, + SPI_PIN_SIMO_7 = 23U, + SPI_PIN_SOMI_1 = 25U, + SPI_PIN_SOMI_2 = 26U, + SPI_PIN_SOMI_3 = 27U, + SPI_PIN_SOMI_4 = 28U, + SPI_PIN_SOMI_5 = 29U, + SPI_PIN_SOMI_6 = 30U, + SPI_PIN_SOMI_7 = 31U +}; + +/** @enum dataformat + * @brief SPI dataformat register select + */ +typedef enum dataformat +{ + SPI_FMT_0 = 0U, + SPI_FMT_1 = 1U, + SPI_FMT_2 = 2U, + SPI_FMT_3 = 3U +} SPIDATAFMT_t; + +/** @struct spiDAT1RegConfig + * @brief SPI data register configuration + */ +typedef struct spiDAT1RegConfig +{ + boolean CS_HOLD; + boolean WDEL; + SPIDATAFMT_t DFSEL; + uint8 CSNR; +} spiDAT1_t; + +/** @enum SpiTxRxDataStatus + * @brief SPI Data Status + */ +typedef enum SpiTxRxDataStatus +{ + SPI_READY = 0U, + SPI_PENDING = 1U, + SPI_COMPLETED = 2U +} SpiDataStatus_t; + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef struct spi_config_reg +{ + uint32 CONFIG_GCR1; + uint32 CONFIG_INT0; + uint32 CONFIG_LVL; + uint32 CONFIG_PC0; + uint32 CONFIG_PC1; + uint32 CONFIG_PC6; + uint32 CONFIG_PC7; + uint32 CONFIG_PC8; + uint32 CONFIG_DELAY; + uint32 CONFIG_FMT0; + uint32 CONFIG_FMT1; + uint32 CONFIG_FMT2; + uint32 CONFIG_FMT3; +} spi_config_reg_t; + +#define SPI2_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) + +#define SPI2_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define SPI2_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SPI2_PC0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define SPI2_PC1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define SPI2_PC6_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define SPI2_PC7_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define SPI2_PC8_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define SPI2_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SPI2_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define SPI2_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define SPI2_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define SPI2_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define SPI4_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) + +#define SPI4_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define SPI4_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SPI4_PC0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) | ( uint32 ) ( ( uint32 ) 1U << 10U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define SPI4_PC1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) | ( uint32 ) ( ( uint32 ) 1U << 10U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define SPI4_PC6_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define SPI4_PC7_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define SPI4_PC8_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) | ( uint32 ) ( ( uint32 ) 1U << 10U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define SPI4_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define SPI4_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define SPI4_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define SPI4_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define SPI4_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 109U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +/** + * @defgroup SPI SPI + * @brief Serial Peripheral Interface Module. + * + * SPI is a high-speed synchronous serial input/output port that allows a serial bit + * stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a + * programmed bit-transfer rate. + * + * Related Files + * - reg_spi.h + * - spi.h + * - spi.c + * @addtogroup SPI + * @{ + */ + +/* SPI Interface Functions */ +void spiInit( void ); +void spiSetFunctional( spiBASE_t * spi, uint32 port ); +void spiEnableNotification( spiBASE_t * spi, uint32 flags ); +void spiDisableNotification( spiBASE_t * spi, uint32 flags ); +uint32 spiTransmitData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff ); +void spiSendData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff ); +uint32 spiReceiveData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * destbuff ); +void spiGetData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * destbuff ); +uint32 spiTransmitAndReceiveData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff, + uint16 * destbuff ); +void spiSendAndGetData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff, + uint16 * destbuff ); +void spiEnableLoopback( spiBASE_t * spi, loopBackType_t Loopbacktype ); +void spiDisableLoopback( spiBASE_t * spi ); +SpiDataStatus_t SpiTxStatus( spiBASE_t * spi ); +SpiDataStatus_t SpiRxStatus( spiBASE_t * spi ); +void spi2GetConfigValue( spi_config_reg_t * config_reg, config_value_type_t type ); +void spi4GetConfigValue( spi_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void spiNotification(spiBASE_t *spi, uint32 flags) + * @brief Interrupt callback + * @param[in] spi - Spi module base address + * @param[in] flags - Copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void spiNotification( spiBASE_t * spi, uint32 flags ); + +/** @fn void spiEndNotification(spiBASE_t *spi) + * @brief Interrupt callback for End of TX or RX data length. + * @param[in] spi - Spi module base address + * + * This is a callback that is provided by the application and is called upon + * an interrupt at the End of TX or RX data length. + */ +void spiEndNotification( spiBASE_t * spi ); + +/**@}*/ +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __SPI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/std_nhet.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/std_nhet.h new file mode 100644 index 00000000000..58725acd295 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/std_nhet.h @@ -0,0 +1,2288 @@ +/** @file std_nhet.h + * @brief NHET Instruction Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __STD_NHET_H__ + #define __STD_NHET_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + #include "sys_common.h" + + #ifdef __cplusplus +extern "C" { + #endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + #ifndef HET_v2 + #define HET_v2 0 + #endif + + #if( ( __little_endian__ == 0 ) || ( __LITTLE_ENDIAN__ == 0 ) \ + || defined( _TMS470_BIG ) || defined( __big_endian__ ) ) + + #ifndef HETBYTE + #define HETBYTE uint8 + #endif + +typedef struct memory_format +{ + uint32 program_word; + uint32 control_word; + uint32 data_word; + uint32 reserved_word; +} HET_MEMORY; + +/*---------------------------------------------*/ +/* ACMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct acmp_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 9; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 coutprv : 1; + uint32 : 2; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 ext_reg : 1; + uint32 : 2; + uint32 pin_action : 1; + uint32 : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 : 7; +} ACMP_FIELDS; + +typedef union +{ + ACMP_FIELDS acmp; + HET_MEMORY memory; +} ACMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* ECMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ecmp_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 hr_lr : 1; + uint32 angle_compare : 1; + uint32 : 7; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 sub_opcode : 2; + uint32 pin_action : 1; + uint32 opposite_action : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} ECMP_FIELDS; + +typedef union +{ + ECMP_FIELDS ecmp; + HET_MEMORY memory; +} ECMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* SCMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct scmp_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 2; + uint32 : 2; + uint32 : 5; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 coutprv : 1; + uint32 : 2; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 compare_mode : 2; + uint32 pin_action : 1; + uint32 : 2; + uint32 restart_en : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 : 7; +} SCMP_FIELDS; + +typedef union +{ + SCMP_FIELDS scmp; + HET_MEMORY memory; +} SCMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* MCMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct mcmp_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 hr_lr : 1; + uint32 angle_compare : 1; + uint32 : 1; + uint32 save_subtract : 1; + uint32 : 5; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 sub_opcode : 1; + uint32 order : 1; + uint32 pin_action : 1; + uint32 opposite_action : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} MCMP_FIELDS; + +typedef union +{ + MCMP_FIELDS mcmp; + HET_MEMORY memory; +} MCMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* MOV64 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct mov64_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 compare_mode : 2; + uint32 pin_action : 1; + uint32 opposite_action : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} MOV64_FIELDS; + +typedef union +{ + MOV64_FIELDS mov64; + HET_MEMORY memory; +} MOV64_INSTRUCTION; + +/*---------------------------------------------*/ +/* DADM64 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct dadm64_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 compare_mode : 2; + uint32 pin_action : 1; + uint32 opposite_action : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} DADM64_FIELDS; + +typedef union +{ + DADM64_FIELDS dadm64; + HET_MEMORY memory; +} DADM64_INSTRUCTION; + +/*---------------------------------------------*/ +/* RADM64 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct RADM64_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 compare_mode : 2; + uint32 pin_action : 1; + uint32 opposite_action : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} RADM64_FIELDS; + +typedef union +{ + RADM64_FIELDS radm64; + HET_MEMORY memory; +} RADM64_INSTRUCTION; + +/*---------------------------------------------*/ +/* MOV32 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct MOV32_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 z_flag : 1; + uint32 : 15; + uint32 init_flag : 1; + uint32 sub_opcode : 1; + uint32 move_type : 2; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} MOV32_FIELDS; + +typedef union +{ + MOV32_FIELDS mov32; + HET_MEMORY memory; +} MOV32_INSTRUCTION; + +/*---------------------------------------------*/ +/* ADM32 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ADM32_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 auto_read_clear : 1; + uint32 : 19; + uint32 init_flag : 1; + uint32 sub_opcode : 1; + uint32 move_type : 2; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} ADM32_FIELDS; + +typedef union +{ + ADM32_FIELDS adm32; + HET_MEMORY memory; +} ADM32_INSTRUCTION; + +/*---------------------------------------------*/ +/* ADCNST INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ADCNST_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; /* pk */ + uint32 : 1; + uint32 constant : 25; + + uint32 data : 25; + uint32 hr_data : 7; +} ADCNST_FIELDS; + +typedef union +{ + ADCNST_FIELDS adcnst; + HET_MEMORY memory; +} ADCNST_INSTRUCTION; + +/*----------------------------------------------*/ +/* ADD INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct ADD_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} ADD_FIELDS; + +typedef union +{ + ADD_FIELDS add; + HET_MEMORY memory; +} ADD_INSTRUCTION; + +/*----------------------------------------------*/ +/* ADC INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct ADC_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} ADC_FIELDS; + +typedef union +{ + ADC_FIELDS adc; + HET_MEMORY memory; +} ADC_INSTRUCTION; + +/*----------------------------------------------*/ +/* SUB INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct SUB_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} SUB_FIELDS; + +typedef union +{ + SUB_FIELDS sub; + HET_MEMORY memory; +} SUB_INSTRUCTION; + +/*----------------------------------------------*/ +/* SBB INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct SBB_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} SBB_FIELDS; + +typedef union +{ + SBB_FIELDS sbb; + HET_MEMORY memory; +} SBB_INSTRUCTION; + +/*----------------------------------------------*/ +/* AND INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct AND_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} AND_FIELDS; + +typedef union +{ + #ifdef __cplusplus + AND_FIELDS and_cpp; + #else + AND_FIELDS and; + #endif + HET_MEMORY memory; +} AND_INSTRUCTION; + +/*----------------------------------------------*/ +/* OR INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct OR_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} OR_FIELDS; + +typedef union +{ + #ifdef __cplusplus + OR_FIELDS or_cpp; + #else + OR_FIELDS or ; + #endif + HET_MEMORY memory; +} OR_INSTRUCTION; + +/*----------------------------------------------*/ +/* XOR INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct XOR_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 remote_address : 9; + + uint32 : 5; + uint32 control : 1; + uint32 sub_opcode3 : 3; + uint32 src_1 : 4; + uint32 src_2 : 3; + uint32 shft_mode : 3; + uint32 shft_cnt : 5; + uint32 reg_ext : 1; + uint32 init_flag : 1; + uint32 sub_opcode1 : 1; + uint32 rem_dest : 2; + uint32 reg : 2; + uint32 : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} XOR_FIELDS; + +typedef union +{ + #ifdef __cplusplus + XOR_FIELDS xor_cpp; + #else + XOR_FIELDS xor ; + #endif + HET_MEMORY memory; +} XOR_INSTRUCTION; + +/*---------------------------------------------*/ +/* CNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct CNT_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 angle_cnt : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 : 4; + uint32 interrupt_enable : 1; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 1; + uint32 max : 25; + + uint32 data : 25; + uint32 : 7; +} CNT_FIELDS; + +typedef union +{ + CNT_FIELDS cnt; + HET_MEMORY memory; +} CNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* APCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct apcnt_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 interrupt_enable : 1; + uint32 edge_select : 2; + uint32 : 6; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 count : 25; + + uint32 data : 25; + uint32 : 7; +} APCNT_FIELDS; + +typedef union +{ + APCNT_FIELDS apcnt; + HET_MEMORY memory; +} APCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* PCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct pcnt_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 interrupt_enable : 1; + uint32 period_pulse_select : 2; + uint32 : 1; + uint32 pin_select : 5; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 count : 25; + + uint32 data : 25; + uint32 hr_data : 7; +} PCNT_FIELDS; + +typedef union +{ + PCNT_FIELDS pcnt; + HET_MEMORY memory; +} PCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* SCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct scnt_format +{ + uint32 : 9; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 1; + uint32 count_mode : 2; + uint32 step_width : 2; + uint32 : 4; + + uint32 : 5; + uint32 auto_read_clear : 1; + uint32 : 1; + uint32 gap_start : 25; + + uint32 data : 25; + uint32 : 7; +} SCNT_FIELDS; + +typedef union +{ + SCNT_FIELDS scnt; + HET_MEMORY memory; +} SCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* ACNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct acnt_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 edge_select : 1; + uint32 : 7; + uint32 interrupt_enable : 1; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 gap_end : 25; + + uint32 data : 25; + uint32 : 7; +} ACNT_FIELDS; + +typedef union +{ + ACNT_FIELDS acnt; + HET_MEMORY memory; +} ACNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* ECNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ecnt_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 1; + uint32 count_mode : 2; + uint32 : 6; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 : 3; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 count_cond : 3; + uint32 : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 : 7; +} ECNT_FIELDS; + +typedef union +{ + ECNT_FIELDS ecnt; + HET_MEMORY memory; +} ECNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* RCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct rcnt_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 1; + uint32 count_mode : 2; + uint32 : 5; + uint32 count_mode1 : 1; + + uint32 : 3; + uint32 : 2; + uint32 control : 1; + uint32 : 1; + uint32 divisor : 25; + + uint32 data : 25; + uint32 : 7; +} RCNT_FIELDS; + +typedef union +{ + RCNT_FIELDS rcnt; + HET_MEMORY memory; +} RCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* DJNZ INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct djnz_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 1; + uint32 sub_opcode : 2; + uint32 : 6; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 4; + uint32 cond_addr : 9; + uint32 : 10; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 : 7; +} DJNZ_FIELDS; + +typedef union +{ + DJNZ_FIELDS djnz; + HET_MEMORY memory; +} DJNZ_INSTRUCTION; + +/*---------------------------------------------*/ +/* DJZ INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct djz_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 1; + uint32 sub_opcode : 2; + uint32 : 6; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 4; + uint32 cond_addr : 9; + uint32 : 10; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 : 7; +} DJZ_FIELDS; + +typedef union +{ + DJZ_FIELDS djz; + HET_MEMORY memory; +} DJZ_INSTRUCTION; + +/*---------------------------------------------*/ +/* PWCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct pwcnt_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 hr_lr : 1; + uint32 count_mode : 2; + uint32 : 6; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 : 3; + uint32 en_pin_action : 1; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 3; + uint32 pin_action : 1; + uint32 opposite_action : 1; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} PWCNT_FIELDS; + +typedef union +{ + PWCNT_FIELDS pwcnt; + HET_MEMORY memory; +} PWCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* WCAP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct wcap_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 hr_lr : 1; + uint32 : 8; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 : 3; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 capture_condition : 2; + uint32 : 2; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} WCAP_FIELDS; + +typedef union +{ + WCAP_FIELDS wcap; + HET_MEMORY memory; +} WCAP_INSTRUCTION; + +/*----------------------------------------------*/ +/* WCAPE INSTRUCTION */ +/*----------------------------------------------*/ +typedef struct wcape_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 9; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 : 3; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 capture_condition : 2; + uint32 : 2; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 ts_data : 25; + uint32 ec_data : 7; +} WCAPE_FIELDS; + +typedef union +{ + WCAPE_FIELDS wcape; + HET_MEMORY memory; +} WCAPE_INSTRUCTION; + +/*---------------------------------------------*/ +/* BR INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct br_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 9; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 : 3; + uint32 cond_addr : 9; + uint32 pin_select : 5; + + #if HET_v2 + uint32 branch_condition : 5; + #else + uint32 branch_condition : 3; + uint32 : 1; + uint32 : 1; + #endif + + uint32 : 2; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 hr_data : 7; +} BR_FIELDS; + +typedef union +{ + BR_FIELDS br; + HET_MEMORY memory; +} BR_INSTRUCTION; + +/*---------------------------------------------*/ +/* SHFT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct shft_format +{ + uint32 : 6; + uint32 reqnum : 3; + uint32 brk : 1; + uint32 next_program_address : 9; + uint32 op_code : 4; + uint32 : 5; + uint32 shift_mode : 4; + + uint32 : 3; + uint32 request : 2; + uint32 auto_read_clear : 1; + uint32 previous_bit : 1; + uint32 : 3; + uint32 cond_addr : 9; + uint32 pin_select : 5; + uint32 : 1; + uint32 shift_condition : 2; + uint32 : 2; + uint32 t_register_select : 1; + uint32 ab_register_select : 1; + uint32 interrupt_enable : 1; + + uint32 data : 25; + uint32 : 7; +} SHFT_FIELDS; + +typedef union +{ + SHFT_FIELDS shft; + HET_MEMORY memory; +} SHFT_INSTRUCTION; + + /* ---------------------------------------------------------------------------------------------------- + */ + + #else /* if ( ( __little_endian__ == 0 ) || ( __LITTLE_ENDIAN__ == 0 ) || defined( \ + _TMS470_BIG ) || defined( __big_endian__ ) ) */ + + #ifndef HETBYTE + #define HETBYTE uint8 + #endif + +typedef struct memory_format +{ + uint32 program_word; + uint32 control_word; + uint32 data_word; + uint32 reserved_word; +} HET_MEMORY; + +/*---------------------------------------------*/ +/* ACMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct acmp_format +{ + uint32 : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 1; + uint32 pin_action : 1; + uint32 : 3; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 2; + uint32 coutprv : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} ACMP_FIELDS; + +typedef union +{ + ACMP_FIELDS acmp; + HET_MEMORY memory; +} ACMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* ECMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ecmp_format +{ + uint32 : 7; + uint32 angle_compare : 1; + uint32 hr_lr : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 opposite_action : 1; + uint32 pin_action : 1; + uint32 sub_opcode : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} ECMP_FIELDS; + +typedef union +{ + ECMP_FIELDS ecmp; + HET_MEMORY memory; +} ECMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* SCMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct scmp_format +{ + uint32 : 5; + uint32 : 2; + uint32 : 2; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 restart_en : 1; + uint32 : 2; + uint32 pin_action : 1; + uint32 compare_mode : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 2; + uint32 coutprv : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} SCMP_FIELDS; + +typedef union +{ + SCMP_FIELDS scmp; + HET_MEMORY memory; +} SCMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* MCMP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct mcmp_format +{ + uint32 : 5; + uint32 save_subtract : 1; + uint32 : 1; + uint32 angle_compare : 1; + uint32 hr_lr : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 opposite_action : 1; + uint32 pin_action : 1; + uint32 order : 1; + uint32 sub_opcode : 1; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} MCMP_FIELDS; + +typedef union +{ + MCMP_FIELDS mcmp; + HET_MEMORY memory; +} MCMP_INSTRUCTION; + +/*---------------------------------------------*/ +/* MOV64 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct mov64_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 opposite_action : 1; + uint32 pin_action : 1; + uint32 compare_mode : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} MOV64_FIELDS; + +typedef union +{ + MOV64_FIELDS mov64; + HET_MEMORY memory; +} MOV64_INSTRUCTION; + +/*---------------------------------------------*/ +/* DADM64 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct dadm64_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 opposite_action : 1; + uint32 pin_action : 1; + uint32 compare_mode : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} DADM64_FIELDS; + +typedef union +{ + DADM64_FIELDS dadm64; + HET_MEMORY memory; +} DADM64_INSTRUCTION; + +/*---------------------------------------------*/ +/* RADM64 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct RADM64_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 opposite_action : 1; + uint32 pin_action : 1; + uint32 compare_mode : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} RADM64_FIELDS; + +typedef union +{ + RADM64_FIELDS radm64; + HET_MEMORY memory; +} RADM64_INSTRUCTION; + +/*---------------------------------------------*/ +/* MOV32 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct MOV32_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 move_type : 2; + uint32 sub_opcode : 1; + uint32 init_flag : 1; + uint32 : 15; + uint32 z_flag : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} MOV32_FIELDS; + +typedef union +{ + MOV32_FIELDS mov32; + HET_MEMORY memory; +} MOV32_INSTRUCTION; + +/*---------------------------------------------*/ +/* ADM32 INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ADM32_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 move_type : 2; + uint32 sub_opcode : 1; + uint32 init_flag : 1; + uint32 : 19; + uint32 auto_read_clear : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} ADM32_FIELDS; + +typedef union +{ + ADM32_FIELDS adm32; + HET_MEMORY memory; +} ADM32_INSTRUCTION; + +/*---------------------------------------------*/ +/* ADCNST INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ADCNST_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 constant : 25; + uint32 : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} ADCNST_FIELDS; + +typedef union +{ + ADCNST_FIELDS adcnst; + HET_MEMORY memory; +} ADCNST_INSTRUCTION; + +/*----------------------------------------------*/ +/* ADD INSTRUCTION */ +/*----------------------------------------------*/ +typedef struct ADD_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} ADD_FIELDS; + +typedef union +{ + ADD_FIELDS add; + HET_MEMORY memory; +} ADD_INSTRUCTION; + +/*----------------------------------------------*/ +/* ADC INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct ADC_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} ADC_FIELDS; + +typedef union +{ + ADC_FIELDS adc; + HET_MEMORY memory; +} ADC_INSTRUCTION; + +/*----------------------------------------------*/ +/* SUB INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct SUB_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} SUB_FIELDS; + +typedef union +{ + SUB_FIELDS sub; + HET_MEMORY memory; +} SUB_INSTRUCTION; + +/*----------------------------------------------*/ +/* SBB INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct SBB_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} SBB_FIELDS; + +typedef union +{ + SBB_FIELDS sbb; + HET_MEMORY memory; +} SBB_INSTRUCTION; + +/*----------------------------------------------*/ +/* AND INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct AND_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} AND_FIELDS; + +typedef union +{ + #ifdef __cplusplus + AND_FIELDS and_cpp; + #else + AND_FIELDS and; + #endif + HET_MEMORY memory; +} AND_INSTRUCTION; + +/*----------------------------------------------*/ +/* OR INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct OR_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} OR_FIELDS; + +typedef union +{ + #ifdef __cplusplus + OR_FIELDS or_cpp; + #else + OR_FIELDS or ; + #endif + HET_MEMORY memory; +} OR_INSTRUCTION; + +/*----------------------------------------------*/ +/* XOR INSTRUCTION */ +/*----------------------------------------------*/ + +typedef struct XOR_format +{ + uint32 remote_address : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 : 1; + uint32 reg : 2; + uint32 rem_dest : 2; + uint32 sub_opcode1 : 1; + uint32 init_flag : 1; + uint32 reg_ext : 1; + uint32 shft_cnt : 5; + uint32 shft_mode : 3; + uint32 src_2 : 3; + uint32 src_1 : 4; + uint32 sub_opcode3 : 3; + uint32 control : 1; + uint32 : 5; + + uint32 hr_data : 7; + uint32 data : 25; +} XOR_FIELDS; + +typedef union +{ + #ifdef __cplusplus + XOR_FIELDS xor_cpp; + #else + XOR_FIELDS xor ; + #endif + HET_MEMORY memory; +} XOR_INSTRUCTION; + +/*---------------------------------------------*/ +/* CNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct CNT_format +{ + uint32 interrupt_enable : 1; + uint32 : 4; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 angle_cnt : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 max : 25; + uint32 : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} CNT_FIELDS; + +typedef union +{ + CNT_FIELDS cnt; + HET_MEMORY memory; +} CNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* APCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct apcnt_format +{ + uint32 : 6; + uint32 edge_select : 2; + uint32 interrupt_enable : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 count : 25; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} APCNT_FIELDS; + +typedef union +{ + APCNT_FIELDS apcnt; + HET_MEMORY memory; +} APCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* PCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct pcnt_format +{ + uint32 pin_select : 5; + uint32 : 1; + uint32 period_pulse_select : 2; + uint32 interrupt_enable : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 count : 25; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} PCNT_FIELDS; + +typedef union +{ + PCNT_FIELDS pcnt; + HET_MEMORY memory; +} PCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* SCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct scnt_format +{ + uint32 : 4; + uint32 step_width : 2; + uint32 count_mode : 2; + uint32 : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 : 9; + + uint32 gap_start : 25; + uint32 : 1; + uint32 auto_read_clear : 1; + uint32 : 5; + + uint32 : 7; + uint32 data : 25; +} SCNT_FIELDS; + +typedef union +{ + SCNT_FIELDS scnt; + HET_MEMORY memory; +} SCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* ACNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct acnt_format +{ + uint32 interrupt_enable : 1; + uint32 : 7; + uint32 edge_select : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 gap_end : 25; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} ACNT_FIELDS; + +typedef union +{ + ACNT_FIELDS acnt; + HET_MEMORY memory; +} ACNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* ECNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct ecnt_format +{ + uint32 : 6; + uint32 count_mode : 2; + uint32 : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 1; + uint32 count_cond : 3; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 : 3; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} ECNT_FIELDS; + +typedef union +{ + ECNT_FIELDS ecnt; + HET_MEMORY memory; +} ECNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* RCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct rcnt_format +{ + uint32 count_mode1 : 1; + uint32 : 5; + uint32 count_mode : 2; + uint32 : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 divisor : 25; + uint32 : 1; + uint32 control : 1; + uint32 : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} RCNT_FIELDS; + +typedef union +{ + RCNT_FIELDS rcnt; + HET_MEMORY memory; +} RCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* DJNZ INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct djnz_format +{ + uint32 : 6; + uint32 sub_opcode : 2; + uint32 : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 10; + uint32 cond_addr : 9; + uint32 : 4; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} DJNZ_FIELDS; + +typedef union +{ + DJNZ_FIELDS djnz; + HET_MEMORY memory; +} DJNZ_INSTRUCTION; + +/*---------------------------------------------*/ +/* DJZ INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct djz_format +{ + uint32 : 6; + uint32 sub_opcode : 2; + uint32 : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 10; + uint32 cond_addr : 9; + uint32 : 4; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} DJZ_FIELDS; + +typedef union +{ + DJZ_FIELDS djz; + HET_MEMORY memory; +} DJZ_INSTRUCTION; + +/*---------------------------------------------*/ +/* PWCNT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct pwcnt_format +{ + uint32 : 6; + uint32 count_mode : 2; + uint32 hr_lr : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 opposite_action : 1; + uint32 pin_action : 1; + uint32 : 3; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 en_pin_action : 1; + uint32 : 3; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} PWCNT_FIELDS; + +typedef union +{ + PWCNT_FIELDS pwcnt; + HET_MEMORY memory; +} PWCNT_INSTRUCTION; + +/*---------------------------------------------*/ +/* WCAP INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct wcap_format +{ + uint32 : 8; + uint32 hr_lr : 1; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 2; + uint32 capture_condition : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 : 3; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} WCAP_FIELDS; + +typedef union +{ + WCAP_FIELDS wcap; + HET_MEMORY memory; +} WCAP_INSTRUCTION; + +/*----------------------------------------------*/ +/* WCAPE INSTRUCTION */ +/*----------------------------------------------*/ +typedef struct wcape_format +{ + uint32 : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 2; + uint32 capture_condition : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 ec_data : 7; + uint32 ts_data : 25; +} WCAPE_FIELDS; + +typedef union +{ + WCAPE_FIELDS wcape; + HET_MEMORY memory; +} WCAPE_INSTRUCTION; + +/*---------------------------------------------*/ +/* BR INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct br_format +{ + uint32 : 9; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 : 2; + uint32 : 1; + uint32 : 1; + uint32 branch_condition : 3; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 : 3; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 hr_data : 7; + uint32 data : 25; +} BR_FIELDS; + +typedef union +{ + BR_FIELDS br; + HET_MEMORY memory; +} BR_INSTRUCTION; + +/*---------------------------------------------*/ +/* SHFT INSTRUCTION */ +/*---------------------------------------------*/ +typedef struct shft_format +{ + uint32 shift_mode : 4; + uint32 : 5; + uint32 op_code : 4; + uint32 next_program_address : 9; + uint32 brk : 1; + uint32 reqnum : 3; + uint32 : 6; + + uint32 interrupt_enable : 1; + uint32 ab_register_select : 1; + uint32 t_register_select : 1; + uint32 : 2; + uint32 shift_condition : 2; + uint32 : 1; + uint32 pin_select : 5; + uint32 cond_addr : 9; + uint32 : 3; + uint32 previous_bit : 1; + uint32 auto_read_clear : 1; + uint32 request : 2; + uint32 : 3; + + uint32 : 7; + uint32 data : 25; +} SHFT_FIELDS; + +typedef union +{ + SHFT_FIELDS shft; + HET_MEMORY memory; +} SHFT_INSTRUCTION; + + #endif /* if ( ( __little_endian__ == 0 ) || ( __LITTLE_ENDIAN__ == 0 ) || defined( \ + _TMS470_BIG ) || defined( __big_endian__ ) ) */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + #ifdef __cplusplus +} + #endif /*extern "C" */ + +#endif /* ifndef __STD_NHET_H__ */ +/*--------------------------- End Of File ----------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_common.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_common.h new file mode 100644 index 00000000000..4a9acb10ea3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_common.h @@ -0,0 +1,131 @@ +/** @file sys_common.h + * @brief Common Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - General Definitions + * . + * which are relevant for all drivers. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_COMMON_H__ +#define __SYS_COMMON_H__ + +#include "hal_stdtypes.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/************************************************************/ +/* Type Definitions */ +/************************************************************/ + +#ifndef _TBOOLEAN_DECLARED +typedef boolean tBoolean; + #define _TBOOLEAN_DECLARED +#endif + +/** @enum loopBackType + * @brief Loopback type definition + */ + +/** @typedef loopBackType_t + * @brief Loopback type Type Definition + * + * This type is used to select the module Loopback type Digital or Analog loopback. + */ +typedef enum loopBackType +{ + Digital_Lbk = 0U, + Analog_Lbk = 1U +} loopBackType_t; + +/** @enum config_value_type + * @brief config type definition + */ + +/** @typedef config_value_type_t + * @brief config type Type Definition + * + * This type is used to specify the Initial and Current value. + */ +typedef enum config_value_type +{ + InitialValue, + CurrentValue +} config_value_type_t; + +#ifndef __little_endian__ + #define __little_endian__ 1 +#endif +#ifndef __LITTLE_ENDIAN__ + #define __LITTLE_ENDIAN__ 1 +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/********************************************************************************/ +/* The ASSERT macro, which does the actual assertion checking. Typically, this */ +/* will be for procedure arguments. */ +/********************************************************************************/ +#ifdef DEBUG + #define ASSERT( expr ) \ + { \ + if( !( expr ) ) \ + { \ + __error__( __FILE__, __LINE__ ); \ + } \ + } +#else + #define ASSERT( expr ) +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __SYS_COMMON_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_core.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_core.h new file mode 100644 index 00000000000..86cd11512a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_core.h @@ -0,0 +1,362 @@ +/** @file sys_core.h + * @brief System Core Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Core Interface Functions + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_CORE_H__ +#define __SYS_CORE_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def USER_STACK_LENGTH + * @brief USER Mode Stack length (in bytes) + * + * Alias for USER Mode Stack length (in bytes) + * + * @note: Use this macro for USER Mode Stack length (in bytes) + */ +#define USER_STACK_LENGTH 0x00000300U + +/** @def SVC_STACK_LENGTH + * @brief SVC Mode Stack length (in bytes) + * + * Alias for SVC Mode Stack length (in bytes) + * + * @note: Use this macro for SVC Mode Stack length (in bytes) + */ +#define SVC_STACK_LENGTH 0x00000100U + +/** @def FIQ_STACK_LENGTH + * @brief FIQ Mode Stack length (in bytes) + * + * Alias for FIQ Mode Stack length (in bytes) + * + * @note: Use this macro for FIQ Mode Stack length (in bytes) + */ +#define FIQ_STACK_LENGTH 0x00000100U + +/** @def IRQ_STACK_LENGTH + * @brief IRQ Mode Stack length (in bytes) + * + * Alias for IRQ Mode Stack length (in bytes) + * + * @note: Use this macro for IRQ Mode Stack length (in bytes) + */ +#define IRQ_STACK_LENGTH 0x00000100U + +/** @def ABORT_STACK_LENGTH + * @brief ABORT Mode Stack length (in bytes) + * + * Alias for ABORT Mode Stack length (in bytes) + * + * @note: Use this macro for ABORT Mode Stack length (in bytes) + */ +#define ABORT_STACK_LENGTH 0x00000100U + +/** @def UNDEF_STACK_LENGTH + * @brief UNDEF Mode Stack length (in bytes) + * + * Alias for UNDEF Mode Stack length (in bytes) + * + * @note: Use this macro for UNDEF Mode Stack length (in bytes) + */ +#define UNDEF_STACK_LENGTH 0x00000100U + +/* System Core Interface Functions */ + +/** @fn void _coreInitRegisters_(void) + * @brief Initialize Core register + */ +void _coreInitRegisters_( void ); + +/** @fn void _coreInitStackPointer_(void) + * @brief Initialize Core stack pointer + */ +void _coreInitStackPointer_( void ); + +/** @fn void _getCPSRValue_(void) + * @brief Get CPSR Value + */ +uint32 _getCPSRValue_( void ); + +/** @fn void _gotoCPUIdle_(void) + * @brief Take CPU to Idle state + */ +void _gotoCPUIdle_( void ); + +/** @fn void _coreEnableIrqVicOffset_(void) + * @brief Enable Irq offset propagation via Vic controller + */ +void _coreEnableIrqVicOffset_( void ); + +/** @fn void _coreEnableVfp_(void) + * @brief Enable vector floating point unit + */ +void _coreEnableVfp_( void ); + +/** @fn void _coreEnableEventBusExport_(void) + * @brief Enable event bus export for external monitoring modules + * @note It is required to enable event bus export to process ecc issues. + * + * This function enables event bus exports to external monitoring modules + * like tightly coupled RAM wrapper, Flash wrapper and error signaling module. + */ +void _coreEnableEventBusExport_( void ); + +/** @fn void _coreDisableEventBusExport_(void) + * @brief Disable event bus export for external monitoring modules + * + * This function disables event bus exports to external monitoring modules + * like tightly coupled RAM wrapper, Flash wrapper and error signaling module. + */ +void _coreDisableEventBusExport_( void ); + +/** @fn void _coreEnableRamEcc_(void) + * @brief Enable external ecc error for RAM odd and even bank + * @note It is required to enable event bus export to process ecc issues. + */ +void _coreEnableRamEcc_( void ); + +/** @fn void _coreDisableRamEcc_(void) + * @brief Disable external ecc error for RAM odd and even bank + */ +void _coreDisableRamEcc_( void ); + +/** @fn void _coreEnableFlashEcc_(void) + * @brief Enable external ecc error for the Flash + * @note It is required to enable event bus export to process ecc issues. + */ +void _coreEnableFlashEcc_( void ); + +/** @fn void _coreDisableFlashEcc_(void) + * @brief Disable external ecc error for the Flash + */ +void _coreDisableFlashEcc_( void ); + +/** @fn uint32 _coreGetDataFault_(void) + * @brief Get core data fault status register + * @return The function will return the data fault status register value: + * - bit [10,3..0]: + * - 0b00001: Alignment -> address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [11]: + * - 0: Read + * - 1: Write + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetDataFault_( void ); + +/** @fn void _coreClearDataFault_(void) + * @brief Clear core data fault status register + */ +void _coreClearDataFault_( void ); + +/** @fn uint32 _coreGetInstructionFault_(void) + * @brief Get core instruction fault status register + * @return The function will return the instruction fault status register value: + * - bit [10,3..0]: + * - 0b00001: Alignment -> address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetInstructionFault_( void ); + +/** @fn void _coreClearInstructionFault_(void) + * @brief Clear core instruction fault status register + */ +void _coreClearInstructionFault_( void ); + +/** @fn uint32 _coreGetDataFaultAddress_(void) + * @brief Get core data fault address register + * @return The function will return the data fault address: + */ +uint32 _coreGetDataFaultAddress_( void ); + +/** @fn void _coreClearDataFaultAddress_(void) + * @brief Clear core data fault address register + */ +void _coreClearDataFaultAddress_( void ); + +/** @fn uint32 _coreGetInstructionFaultAddress_(void) + * @brief Get core instruction fault address register + * @return The function will return the instruction fault address: + */ +uint32 _coreGetInstructionFaultAddress_( void ); + +/** @fn void _coreClearInstructionFaultAddress_(void) + * @brief Clear core instruction fault address register + */ +void _coreClearInstructionFaultAddress_( void ); + +/** @fn uint32 _coreGetAuxiliaryDataFault_(void) + * @brief Get core auxiliary data fault status register + * @return The function will return the auxiliary data fault status register value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryDataFault_( void ); + +/** @fn void _coreClearAuxiliaryDataFault_(void) + * @brief Clear core auxiliary data fault status register + */ +void _coreClearAuxiliaryDataFault_( void ); + +/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void) + * @brief Get core auxiliary instruction fault status register + * @return The function will return the auxiliary instruction fault status register + * value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryInstructionFault_( void ); + +/** @fn void _coreClearAuxiliaryInstructionFault_(void) + * @brief Clear core auxiliary instruction fault status register + */ +void _coreClearAuxiliaryInstructionFault_( void ); + +/** @fn void _disable_interrupt_(void) + * @brief Disable IRQ and FIQ Interrupt mode in CPSR register + * + * This function disables IRQ and FIQ Interrupt mode in CPSR register. + */ +void _disable_interrupt_( void ); + +/** @fn void _disable_IRQ_interrupt_(void) + * @brief Disable IRQ Interrupt mode in CPSR register + * + * This function disables IRQ Interrupt mode in CPSR register. + */ +void _disable_IRQ_interrupt_( void ); + +/** @fn void _disable_FIQ_interrupt_(void) + * @brief Disable FIQ Interrupt mode in CPSR register + * + * This function disables IRQ Interrupt mode in CPSR register. + */ +void _disable_FIQ_interrupt_( void ); + +/** @fn void _enable_interrupt_(void) + * @brief Enable IRQ and FIQ Interrupt mode in CPSR register + * + * This function Enables IRQ and FIQ Interrupt mode in CPSR register. + * User must call this function to enable Interrupts in non-OS environments. + */ +void _enable_interrupt_( void ); + +/** @fn void _esmCcmErrorsClear_(void) + * @brief Clears ESM Error caused due to CCM Errata in RevA Silicon + * + * This function Clears ESM Error caused due to CCM Errata + * in RevA Silicon immediately after powerup. + */ +void _esmCcmErrorsClear_( void ); + +/** @fn void _errata_CORTEXR4_66_(void) + * @brief Work Around for Errata CORTEX-R4#66 + * + * This function Disable out-of-order completion for divide + * instructions in Auxiliary Control register. + */ +void _errata_CORTEXR4_66_( void ); + +/** @fn void _errata_CORTEXR4_57_(void) + * @brief Work Around for Errata CORTEX-R4#57 + * + * Disable out-of-order single-precision floating point + * multiply-accumulate instruction completion. + */ +void _errata_CORTEXR4_57_( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __SYS_CORE_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_dma.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_dma.h new file mode 100644 index 00000000000..dd2d59a09ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_dma.h @@ -0,0 +1,357 @@ +/** @file dma.h + * @brief DMA Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "reg_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @def BLOCK_TRANSFER + * @brief Alias name for DMA Block transfer + * @note This value should be used while setting the DMA control packet + */ +#define BLOCK_TRANSFER 1U + +/** @def FRAME_TRANSFER + * @brief Alias name for DMA Frame transfer + * @note This value should be used while setting the DMA control packet + */ +#define FRAME_TRANSFER 0U + +/** @def AUTOINIT_ON + * @brief Alias name for Auto Initialization ON + * @note This value should be used while setting the DMA control packet + */ +#define AUTOINIT_ON 1U + +/** @def AUTOINIT_OFF + * @brief Alias name for Auto Initialization OFF + * @note This value should be used while setting the DMA control packet + */ +#define AUTOINIT_OFF 0U + +/** @def ADDR_FIXED + * @brief Alias name for Fixed Addressing mode + * @note This value should be used while setting the DMA control packet + */ +#define ADDR_FIXED 0U + +/** @def ADDR_INC1 + * @brief Alias name for Post-increment Addressing mode + * @note This value should be used while setting the DMA control packet + */ +#define ADDR_INC1 1U + +/** @def ADDR_OFFSET + * @brief Alias name for Offset Addressing mode + * @note This value should be used while setting the DMA control packet + */ +#define ADDR_OFFSET 3U + +/** @def INTERRUPT_ENABLE + * @brief Alias name for Interrupt enable + * @note @note This value should be used for API argument @a intenable + */ +#define INTERRUPT_ENABLE 1U + +/** @def INTERRUPT_DISABLE + * @brief Alias name for Interrupt disable + * @note @note This value should be used for API argument @a intenable + */ +#define INTERRUPT_DISABLE 0U + +/** @def DMA_GCTRL_BUSBUSY + * @brief Bit mask for BUS BUSY in GCTRL Register + * @note @note This value should be used for API argument @a intenable + */ +#define DMA_GCTRL_BUSBUSY ( 0x00004000U ) + +/** @enum dmaREQTYPE + * @brief DMA TRANSFER Type definitions + * + * Used to define DMA transfer type + */ +enum dmaREQTYPE +{ + DMA_HW = 0x0U, /**< Hardware trigger */ + DMA_SW = 0x1U /**< Software trigger */ +}; + +/** @enum dmaCHANNEL + * @brief DMA CHANNEL definitions + * + * Used to define DMA Channel Number + */ +enum dmaCHANNEL +{ + DMA_CH0 = 0x00U, + DMA_CH1 = 0x01U, + DMA_CH2 = 0x02U, + DMA_CH3 = 0x03U, + DMA_CH4 = 0x04U, + DMA_CH5 = 0x05U, + DMA_CH6 = 0x06U, + DMA_CH7 = 0x07U, + DMA_CH8 = 0x08U, + DMA_CH9 = 0x09U, + DMA_CH10 = 0x0AU, + DMA_CH11 = 0x0BU, + DMA_CH12 = 0x0CU, + DMA_CH13 = 0x0DU, + DMA_CH14 = 0x0EU, + DMA_CH15 = 0x0FU, + DMA_CH16 = 0x10U, + DMA_CH17 = 0x11U, + DMA_CH18 = 0x12U, + DMA_CH19 = 0x13U, + DMA_CH20 = 0x14U, + DMA_CH21 = 0x15U, + DMA_CH22 = 0x16U, + DMA_CH23 = 0x17U, + DMA_CH24 = 0x18U, + DMA_CH25 = 0x19U, + DMA_CH26 = 0x1AU, + DMA_CH27 = 0x1BU, + DMA_CH28 = 0x1CU, + DMA_CH29 = 0x1DU, + DMA_CH30 = 0x1EU, + DMA_CH31 = 0x1FU +}; + +/** @enum dmaACCESS + * @brief DMA ACESS WIDTH definitions + * + * Used to define DMA access width + */ +typedef enum dmaACCESS +{ + ACCESS_8_BIT = 0U, + ACCESS_16_BIT = 1U, + ACCESS_32_BIT = 2U, + ACCESS_64_BIT = 3U +} dmaACCESS_t; + +/** @enum dmaPRIORITY + * @brief DMA Channel Priority + * + * Used to define to which priority queue a DMA channel is assigned to + */ +typedef enum dmaPRIORITY +{ + LOWPRIORITY = 0U, + HIGHPRIORITY = 1U +} dmaPRIORITY_t; + +/** @enum dmaREGION + * @brief DMA Memory Protection Region + * + * Used to define DMA Memory Protection Region + */ +typedef enum dmaREGION +{ + DMA_REGION0 = 0U, + DMA_REGION1 = 1U, + DMA_REGION2 = 2U, + DMA_REGION3 = 3U +} dmaREGION_t; + +/** @enum dmaRegionAccess + * @brief DMA Memory Protection Region Access + * + * Used to define access permission of DMA memory protection regions + */ +typedef enum dmaRegionAccess +{ + FULLACCESS = 0U, + READONLY = 1U, + WRITEONLY = 2U, + NOACCESS = 3U +} dmaRegionAccess_t; + +/** @enum dmaInterrupt + * @brief DMA Interrupt + * + * Used to define DMA interrupts + */ +typedef enum dmaInterrupt +{ + FTC = 1U, /**< Frame transfer complete Interrupt */ + LFS = 2U, /**< Last frame transfer started Interrupt */ + HBC = 3U, /**< First half of block complete Interrupt */ + BTC = 4U /**< Block transfer complete Interrupt */ +} dmaInterrupt_t; + +/** @struct g_dmaCTRL + * @brief Interrupt mode globals + * + */ +typedef struct dmaCTRLPKT +{ + uint32 SADD; /* initial source address */ + uint32 DADD; /* initial destination address */ + uint32 CHCTRL; /* next ctrl packet to be trigger + 1 */ + uint32 FRCNT; /* frame count */ + uint32 ELCNT; /* element count */ + uint32 ELDOFFSET; /* element destination offset */ + uint32 ELSOFFSET; /* element source offset */ + uint32 FRDOFFSET; /* frame detination offset */ + uint32 FRSOFFSET; /* frame source offset */ + uint32 PORTASGN; /* dma port */ + uint32 RDSIZE; /* read element size */ + uint32 WRSIZE; /* write element size */ + uint32 TTYPE; /* trigger type - frame/block */ + uint32 ADDMODERD; /* addresssing mode for source */ + uint32 ADDMODEWR; /* addresssing mode for destination */ + uint32 AUTOINIT; /* auto-init mode */ + uint32 COMBO; /* next ctrl packet trigger(Not used) */ +} g_dmaCTRL; + +typedef volatile struct +{ + struct /* 0x000-0x400 */ + { + uint32 ISADDR; + uint32 IDADDR; + uint32 ITCOUNT; + uint32 rsvd1; + uint32 CHCTRL; + uint32 EIOFF; + uint32 FIOFF; + uint32 rsvd2; + } PCP[ 32U ]; + + struct /* 0x400-0x800 */ + { + uint32 res[ 256U ]; + } RESERVED; + + struct /* 0x800-0xA00 */ + { + uint32 CSADDR; + uint32 CDADDR; + uint32 CTCOUNT; + uint32 rsvd3; + } WCP[ 32U ]; +} dmaRAMBASE_t; + +#define dmaRAMREG ( ( dmaRAMBASE_t * ) 0xFFF80000U ) + +typedef struct dma_config_reg +{ + uint32 CONFIG_CHPRIOS; + uint32 CONFIG_GCHIENAS; + uint32 CONFIG_DREQASI[ 8U ]; + uint32 CONFIG_FTCINTENAS; + uint32 CONFIG_LFSINTENAS; + uint32 CONFIG_HBCINTENAS; + uint32 CONFIG_BTCINTENAS; + uint32 CONFIG_DMAPCR; + uint32 CONFIG_DMAMPCTRL; +} dma_config_reg_t; + +/** + * @defgroup DMA DMA + * @brief Direct Memory Access Controller + * + * The DMA controller is used to transfer data between two locations in the memory map in + * the background of CPU operations. Typically, the DMA is used to: + * - Transfer blocks of data between external and internal data memories + * - Restructure portions of internal data memory + * - Continually service a peripheral + * - Page program sections to internal program memory + * + * Related files: + * - reg_dma.h + * - sys_dma.h + * - sys_dma.c + * + * @addtogroup DMA + * @{ + */ +/* DMA Interface Functions */ +void dmaEnable( void ); +void dmaDisable( void ); +void dmaSetCtrlPacket( uint32 channel, g_dmaCTRL g_dmaCTRLPKT ); +void dmaSetChEnable( uint32 channel, uint32 type ); +void dmaReqAssign( uint32 channel, uint32 reqline ); +uint32 dmaGetReq( uint32 channel ); +void dmaSetPriority( uint32 channel, dmaPRIORITY_t priority ); +void dmaEnableInterrupt( uint32 channel, dmaInterrupt_t inttype ); +void dmaDisableInterrupt( uint32 channel, dmaInterrupt_t inttype ); +void dmaDefineRegion( dmaREGION_t region, uint32 start_add, uint32 end_add ); +void dmaEnableRegion( dmaREGION_t region, dmaRegionAccess_t access, boolean intenable ); +void dmaDisableRegion( dmaREGION_t region ); +void dmaEnableParityCheck( void ); +void dmaDisableParityCheck( void ); +void dmaGetConfigValue( dma_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) + * @brief Interrupt callback + * @param[in] inttype Interrupt type + * - FTC + * - LFS + * - HBC + * - BTC + * @param[in] channel channel number 0..15 + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __DMA_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_mpu.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_mpu.h new file mode 100644 index 00000000000..047be46b212 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_mpu.h @@ -0,0 +1,582 @@ +/** @file sys_mpu.h + * @brief System Mpu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Mpu Interface Functions + * . + * which are relevant for the memory protection unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_MPU_H__ +#define __SYS_MPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def mpuREGION1 + * @brief Mpu region 1 + * + * Alias for Mpu region 1 + */ +#define mpuREGION1 0U + +/** @def mpuREGION2 + * @brief Mpu region 2 + * + * Alias for Mpu region 1 + */ +#define mpuREGION2 1U + +/** @def mpuREGION3 + * @brief Mpu region 3 + * + * Alias for Mpu region 3 + */ +#define mpuREGION3 2U + +/** @def mpuREGION4 + * @brief Mpu region 4 + * + * Alias for Mpu region 4 + */ +#define mpuREGION4 3U + +/** @def mpuREGION5 + * @brief Mpu region 5 + * + * Alias for Mpu region 5 + */ +#define mpuREGION5 4U + +/** @def mpuREGION6 + * @brief Mpu region 6 + * + * Alias for Mpu region 6 + */ +#define mpuREGION6 5U + +/** @def mpuREGION7 + * @brief Mpu region 7 + * + * Alias for Mpu region 7 + */ +#define mpuREGION7 6U + +/** @def mpuREGION8 + * @brief Mpu region 8 + * + * Alias for Mpu region 8 + */ +#define mpuREGION8 7U + +/** @def mpuREGION9 + * @brief Mpu region 9 + * + * Alias for Mpu region 9 + */ +#define mpuREGION9 8U + +/** @def mpuREGION10 + * @brief Mpu region 10 + * + * Alias for Mpu region 10 + */ +#define mpuREGION10 9U + +/** @def mpuREGION11 + * @brief Mpu region 11 + * + * Alias for Mpu region 11 + */ +#define mpuREGION11 10U + +/** @def mpuREGION12 + * @brief Mpu region 12 + * + * Alias for Mpu region 12 + */ +#define mpuREGION12 11U + +/** @def mpuREGION_ENABLE + * @brief Enable MPU Region + * + * Alias for MPU region enable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_ENABLE 1U + +/** @def mpuREGION_DISABLE + * @brief Disable MPU Region + * + * Alias for MPU region disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_DISABLE 0U + +/** @def mpuSUBREGION0_DISABLE + * @brief Disable MPU Sub Region0 + * + * Alias for MPU subregion0 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION0_DISABLE 0x100U + +/** @def mpuSUBREGION1_DISABLE + * @brief Disable MPU Sub Region1 + * + * Alias for MPU subregion1 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION1_DISABLE 0x200U + +/** @def mpuSUBREGION2_DISABLE + * @brief Disable MPU Sub Region2 + * + * Alias for MPU subregion2 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION2_DISABLE 0x400U + +/** @def mpuSUBREGION3_DISABLE + * @brief Disable MPU Sub Region3 + * + * Alias for MPU subregion3 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION3_DISABLE 0x800U + +/** @def mpuSUBREGION4_DISABLE + * @brief Disable MPU Sub Region4 + * + * Alias for MPU subregion4 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION4_DISABLE 0x1000U + +/** @def mpuSUBREGION5_DISABLE + * @brief Disable MPU Sub Region5 + * + * Alias for MPU subregion5 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION5_DISABLE 0x2000U + +/** @def mpuSUBREGION6_DISABLE + * @brief Disable MPU Sub Region6 + * + * Alias for MPU subregion6 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION6_DISABLE 0x4000U + +/** @def mpuSUBREGION7_DISABLE + * @brief Disable MPU Sub Region7 + * + * Alias for MPU subregion7 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION7_DISABLE 0x8000U + +/** @enum mpuRegionAccessPermission + * @brief Alias names for mpu region access permissions + * + * This enumeration is used to provide alias names for the mpu region access permission: + * - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode + * and execute + * - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode + * and execute + * - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode + * and execute + * - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and + * execute + * - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode + * and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode + * and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode + * and no execution + * + */ +enum mpuRegionAccessPermission +{ + MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access + in user mode and execute */ + MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias no read/write in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias no read/write in privileged mode, read + only in user mode and execute */ + MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias no read/write in privileged mode, + read/write in user mode and execute */ + MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias no read only in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias no read only in privileged mode, read + only in user mode and execute */ + MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, + read only in user mode and no execution */ + MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, + read/write in user mode and no execution */ + MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias no read only in privileged mode, read + only in user mode and no execution */ +}; + +/** @enum mpuRegionType + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_DEVICE_SHAREABLE Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, + * no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, + * no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no + * write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no + * write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cachable and + * non shared + * - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cachable and + * shared + * - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, + * write allocate and non shared + * - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, + * write allocate and shared + * - MPU_DEVICE_NONSHAREABLE Memory type device and non sharable + */ +enum mpuRegionType +{ + MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and + sharable */ + MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */ + MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner + write-through, no write allocate and non + shared */ + MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner + write-back, no write allocate and non + shared */ + MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner + write-through, no write allocate and shared + */ + MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner + write-back, no write allocate and shared */ + MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner + non-cachable and non shared */ + MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner + write-back, write allocate and non shared */ + MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner non-cachable + and shared */ + MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner + write-back, write allocate and shared */ + MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */ +}; + +/** @enum mpuRegionSize + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_32_BYTES Memory size in bytes + * - MPU_64_BYTES Memory size in bytes + * - MPU_128_BYTES Memory size in bytes + * - MPU_256_BYTES Memory size in bytes + * - MPU_512_BYTES Memory size in bytes + * - MPU_1_KB Memory size in kB + * - MPU_2_KB Memory size in kB + * - MPU_4_KB Memory size in kB + * - MPU_8_KB Memory size in kB + * - MPU_16_KB Memory size in kB + * - MPU_32_KB Memory size in kB + * - MPU_64_KB Memory size in kB + * - MPU_128_KB Memory size in kB + * - MPU_256_KB Memory size in kB + * - MPU_512_KB Memory size in kB + * - MPU_1_MB Memory size in MB + * - MPU_2_MB Memory size in MB + * - MPU_4_MB Memory size in MB + * - MPU_8_MBv Memory size in MB + * - MPU_16_MB Memory size in MB + * - MPU_32_MB Memory size in MB + * - MPU_64_MB Memory size in MB + * - MPU_128_MB Memory size in MB + * - MPU_256_MB Memory size in MB + * - MPU_512_MB Memory size in MB + * - MPU_1_GB Memory size in GB + * - MPU_2_GB Memory size in GB + * - MPU_4_GB Memory size in GB + */ +enum mpuRegionSize +{ + MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */ + MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */ + MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */ + MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */ + MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */ + MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */ + MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */ + MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */ + MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */ + MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */ + MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */ + MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */ + MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */ + MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */ + MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */ + MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */ + MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */ + MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */ + MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */ + MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */ + MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */ + MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */ + MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */ + MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */ + MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */ + MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */ + MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */ + MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */ +}; + +/** @fn void _mpuInit_(void) + * @brief Initialize Mpu + * + * This function initializes memory protection unit. + */ +void _mpuInit_( void ); + +/** @fn void _mpuEnable_(void) + * @brief Enable Mpu + * + * This function enables memory protection unit. + */ +void _mpuEnable_( void ); + +/** @fn void _mpuDisable_(void) + * @brief Disable Mpu + * + * This function disables memory protection unit. + */ +void _mpuDisable_( void ); + +/** @fn void _mpuEnableBackgroundRegion_(void) + * @brief Enable Mpu background region + * + * This function enables background region of the memory protection unit. + */ +void _mpuEnableBackgroundRegion_( void ); + +/** @fn void _mpuDisableBackgroundRegion_(void) + * @brief Disable Mpu background region + * + * This function disables background region of the memory protection unit. + */ +void _mpuDisableBackgroundRegion_( void ); + +/** @fn uint32 _mpuGetNumberOfRegions_(void) + * @brief Returns number of implemented Mpu regions + * @return Number of implemented mpu regions + * + * This function returns the number of implemented mpu regions. + */ +uint32 _mpuGetNumberOfRegions_( void ); + +/** @fn uint32 _mpuAreRegionsSeparate_(void) + * @brief Returns the type of the implemented mpu regions + * @return Mpu type of regions + * + * This function returns 0 when mpu regions are of type unified otherwise regions are of + * type separate. + */ +uint32 _mpuAreRegionsSeparate_( void ); + +/** @fn void _mpuSetRegion_(uint32 region) + * @brief Set mpu region number + * @param[in] region Region number: mpuREGION1..mpuREGION12 + * + * This function selects one of the implemented mpu regions. + */ +void _mpuSetRegion_( uint32 region ); + +/** @fn uint32 _mpuGetRegion_(void) + * @brief Returns the currently selected mpu region + * @return Mpu region number + * + * This function returns currently selected mpu region number. + */ +uint32 _mpuGetRegion_( void ); + +/** @fn void _mpuSetRegionBaseAddress_(uint32 address) + * @brief Set base address of currently selected mpu region + * @param[in] address Base address of the MPU region + * @note The base address must always aligned with region size + * + * This function sets the base address of currently selected mpu region. + */ +void _mpuSetRegionBaseAddress_( uint32 address ); + +/** @fn uint32 _mpuGetRegionBaseAddress_(void) + * @brief Returns base address of currently selected mpu region + * @return Current base address of selected mpu region + * + * This function returns the base address of currently selected mpu region. + */ +uint32 _mpuGetRegionBaseAddress_( void ); + +/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission) + * @brief Set type of currently selected mpu region + * @param[in] type Region Type + * - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and + * sharable + * - MPU_DEVICE_SHAREABLE : Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and + * inner write-through, no write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and + * inner write-back, no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and + * inner write-through, no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and + * inner write-back, no write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and + * inner non-cachable and non shared + * - MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and + * inner write-back, write allocate and non shared + * - MPU_NORMAL_OINC_SHARED : Memory type normal outer and + * inner non-cachable and shared + * - MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and + * inner write-back, write allocate and shared + * - MPU_DEVICE_NONSHAREABLE : Memory type device and non + * sharable + * + * @param[in] permission Region Access permission + * - MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged + * mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_NA_EXEC : Alias no read/write in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_RO_EXEC : Alias no read/write in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_RW_USER_RW_EXEC : Alias no read/write in + * privileged mode, read/write in user mode and execute + * - MPU_PRIV_RO_USER_NA_EXEC : Alias no read only in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RO_USER_RO_EXEC : Alias no read only in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged + * mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in + * privileged mode, read only in user mode and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in + * privileged mode, read/write in user mode and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in + * privileged mode, read only in user mode and no execution + * + * This function sets the type of currently selected mpu region. + */ +void _mpuSetRegionTypeAndPermission_( uint32 type, uint32 permission ); + +/** @fn uint32 _mpuGetRegionType_(void) + * @brief Returns the type of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns the type of currently selected mpu region. + */ +uint32 _mpuGetRegionType_( void ); + +/** @fn uint32 _mpuGetRegionPermission_(void) + * @brief Returns permission of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns permission of currently selected mpu region. + */ +uint32 _mpuGetRegionPermission_( void ); + +/** @fn void _mpuSetRegionSizeRegister_(uint32 value) + * @brief Set mpu region size register value + * @param[in] value Value to be written in the MPU Region Size and Enable register + * + * This function sets mpu region size register value. + * + * Sample usuage: + * _mpuSetRegion_(mpuREGION5); + * _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE | + * mpuSUBREGION4_DISABLE); + */ +void _mpuSetRegionSizeRegister_( uint32 value ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __SYS_MPU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pcr.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pcr.h new file mode 100644 index 00000000000..9e7ccf0aa9f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pcr.h @@ -0,0 +1,306 @@ +/** @file sys_pcr.h + * @brief PCR Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PCR_H__ +#define __SYS_PCR_H__ + +#include "reg_pcr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* PCR General Definitions */ + +typedef uint32 peripheralFrame_CS_t; + +#define PeripheralFrame_CS0 0U +#define PeripheralFrame_CS1 1U +#define PeripheralFrame_CS2 2U +#define PeripheralFrame_CS3 3U +#define PeripheralFrame_CS4 4U +#define PeripheralFrame_CS5 5U +#define PeripheralFrame_CS6 6U +#define PeripheralFrame_CS7 7U +#define PeripheralFrame_CS8 8U +#define PeripheralFrame_CS9 9U +#define PeripheralFrame_CS10 10U +#define PeripheralFrame_CS11 11U +#define PeripheralFrame_CS12 12U +#define PeripheralFrame_CS13 13U +#define PeripheralFrame_CS14 14U +#define PeripheralFrame_CS15 15U +#define PeripheralFrame_CS16 16U +#define PeripheralFrame_CS17 17U +#define PeripheralFrame_CS18 18U +#define PeripheralFrame_CS19 19U +#define PeripheralFrame_CS20 20U +#define PeripheralFrame_CS21 21U +#define PeripheralFrame_CS22 22U +#define PeripheralFrame_CS23 23U +#define PeripheralFrame_CS24 24U +#define PeripheralFrame_CS25 25U +#define PeripheralFrame_CS26 26U +#define PeripheralFrame_CS27 27U +#define PeripheralFrame_CS28 28U +#define PeripheralFrame_CS29 29U +#define PeripheralFrame_CS30 30U +#define PeripheralFrame_CS31 31U + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +typedef uint32 quadrant_Select_t; +#define Quadrant0 1U +#define Quadrant1 2U +#define Quadrant2 4U +#define Quadrant3 8U + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @typedef peripheral_Frame_Select_t + * @brief PCR Peripheral Frame Type Definition + * + * This type is used to access the PCR peripheral Frame configuration register. + */ +typedef struct peripheral_Frame_Select +{ + peripheralFrame_CS_t Peripheral_CS; + quadrant_Select_t Peripheral_Quadrant; +} peripheral_Frame_Select_t; + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/** @typedef peripheral_Quad_ChipSelect_t + * @brief PCR Peripheral Frame registers Type Definition + * + * This type is used to access all the PCR peripheral Frame configuration registers. + */ +typedef struct peripheral_Quad_ChipSelect +{ + uint32 Peripheral_Quad0_3_CS0_7; + uint32 Peripheral_Quad4_7_CS8_15; + uint32 Peripheral_Quad8_11_CS16_23; + uint32 Peripheral_Quad12_15_CS24_31; +} peripheral_Quad_ChipSelect_t; + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/** @typedef peripheral_Memory_ChipSelect_t + * @brief PCR Peripheral Memory Frame registers Type Definition + * + * This type is used to access all the PCR peripheral Memory Frame configuration + * registers. + */ +typedef struct peripheral_Memory_ChipSelect +{ + uint32 Peripheral_Mem_CS0_31; + uint32 Peripheral_Mem_CS32_63; +} peripheral_Memory_ChipSelect_t; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +typedef uint32 peripheral_MemoryFrame_CS_t; + +#define PeripheralMemoryFrame_CS0 0U +#define PeripheralMemoryFrame_CS1 1U +#define PeripheralMemoryFrame_CS2 2U +#define PeripheralMemoryFrame_CS3 3U +#define PeripheralMemoryFrame_CS4 4U +#define PeripheralMemoryFrame_CS5 5U +#define PeripheralMemoryFrame_CS6 6U +#define PeripheralMemoryFrame_CS7 7U +#define PeripheralMemoryFrame_CS8 8U +#define PeripheralMemoryFrame_CS9 9U +#define PeripheralMemoryFrame_CS10 10U +#define PeripheralMemoryFrame_CS11 11U +#define PeripheralMemoryFrame_CS12 12U +#define PeripheralMemoryFrame_CS13 13U +#define PeripheralMemoryFrame_CS14 14U +#define PeripheralMemoryFrame_CS15 15U +#define PeripheralMemoryFrame_CS16 16U +#define PeripheralMemoryFrame_CS17 17U +#define PeripheralMemoryFrame_CS18 18U +#define PeripheralMemoryFrame_CS19 19U +#define PeripheralMemoryFrame_CS20 20U +#define PeripheralMemoryFrame_CS21 21U +#define PeripheralMemoryFrame_CS22 22U +#define PeripheralMemoryFrame_CS23 23U +#define PeripheralMemoryFrame_CS24 24U +#define PeripheralMemoryFrame_CS25 25U +#define PeripheralMemoryFrame_CS26 26U +#define PeripheralMemoryFrame_CS27 27U +#define PeripheralMemoryFrame_CS28 28U +#define PeripheralMemoryFrame_CS29 29U +#define PeripheralMemoryFrame_CS30 30U +#define PeripheralMemoryFrame_CS31 31U +#define PeripheralMemoryFrame_CS32 32U +#define PeripheralMemoryFrame_CS33 33U +#define PeripheralMemoryFrame_CS34 34U +#define PeripheralMemoryFrame_CS35 35U +#define PeripheralMemoryFrame_CS36 36U +#define PeripheralMemoryFrame_CS37 37U +#define PeripheralMemoryFrame_CS38 38U +#define PeripheralMemoryFrame_CS39 39U +#define PeripheralMemoryFrame_CS40 40U +#define PeripheralMemoryFrame_CS41 41U +#define PeripheralMemoryFrame_CS42 42U +#define PeripheralMemoryFrame_CS43 43U +#define PeripheralMemoryFrame_CS44 44U +#define PeripheralMemoryFrame_CS45 45U +#define PeripheralMemoryFrame_CS46 46U +#define PeripheralMemoryFrame_CS47 47U +#define PeripheralMemoryFrame_CS48 48U +#define PeripheralMemoryFrame_CS49 49U +#define PeripheralMemoryFrame_CS50 50U +#define PeripheralMemoryFrame_CS51 51U +#define PeripheralMemoryFrame_CS52 52U +#define PeripheralMemoryFrame_CS53 53U +#define PeripheralMemoryFrame_CS54 54U +#define PeripheralMemoryFrame_CS55 55U +#define PeripheralMemoryFrame_CS56 56U +#define PeripheralMemoryFrame_CS57 57U +#define PeripheralMemoryFrame_CS58 58U +#define PeripheralMemoryFrame_CS59 59U +#define PeripheralMemoryFrame_CS60 60U +#define PeripheralMemoryFrame_CS61 61U +#define PeripheralMemoryFrame_CS62 62U +#define PeripheralMemoryFrame_CS63 63U + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +typedef struct pcr_config_reg +{ + uint32 CONFIG_PMPROTSET0; + uint32 CONFIG_PMPROTSET1; + uint32 CONFIG_PPROTSET0; + uint32 CONFIG_PPROTSET1; + uint32 CONFIG_PPROTSET2; + uint32 CONFIG_PPROTSET3; + uint32 CONFIG_PCSPWRDWNSET0; + uint32 CONFIG_PCSPWRDWNSET1; + uint32 CONFIG_PSPWRDWNSET0; + uint32 CONFIG_PSPWRDWNSET1; + uint32 CONFIG_PSPWRDWNSET2; + uint32 CONFIG_PSPWRDWNSET3; +} pcr_config_reg_t; + +/** + * @defgroup PCR PCR + * @brief Peripheral Central Resource Controller + * + * The PCR manages the accesses to the peripheral registers and peripheral + * memories. It provides a global reset for all the peripherals. It also supports the + * capability to selectively enable or disable the clock for each peripheral + * individually. The PCR also manages the accesses to the system module + * registers required to configure the device’s clocks, interrupts, and so on. The + * system module registers also include status flags for indicating exception + * conditions – resets, aborts, errors, interrupts. + * + * Related files: + * - reg_pcr.h + * - sys_pcr.h + * - sys_pcr.c + * + * @addtogroup PCR + * @{ + */ + +/* PCR Interface Functions */ + +void peripheral_Frame_Protection_Set( peripheral_Frame_Select_t peripheral_Frame ); +void peripheral_Frame_Protection_Clr( peripheral_Frame_Select_t peripheral_Frame ); +void peripheral_Frame_Powerdown_Set( peripheral_Frame_Select_t peripheral_Frame ); +void peripheral_Frame_Powerdown_Clr( peripheral_Frame_Select_t peripheral_Frame ); + +void peripheral_Protection_Set( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ); +void peripheral_Protection_Clr( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ); +void peripheral_Protection_Status( peripheral_Quad_ChipSelect_t * peripheral_Quad_CS ); +void peripheral_Powerdown_Set( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ); +void peripheral_Powerdown_Clr( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ); +void peripheral_Powerdown_Status( peripheral_Quad_ChipSelect_t * peripheral_Quad_CS ); + +void peripheral_Memory_Protection_Set( + peripheral_Memory_ChipSelect_t peripheral_Memory_CS ); +void peripheral_Memory_Protection_Clr( + peripheral_Memory_ChipSelect_t peripheral_Memory_CS ); +void peripheral_Memory_Protection_Status( + peripheral_Memory_ChipSelect_t * peripheral_Memory_CS ); +void peripheral_Memory_Powerdown_Set( + peripheral_Memory_ChipSelect_t peripheral_Memory_CS ); +void peripheral_Memory_Powerdown_Clr( + peripheral_Memory_ChipSelect_t peripheral_Memory_CS ); +void peripheral_Memory_Powerdown_Status( + peripheral_Memory_ChipSelect_t * peripheral_Memory_CS ); + +void peripheral_Mem_Frame_Prot_Set( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ); +void peripheral_Mem_Frame_Prot_Clr( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ); +void peripheral_Mem_Frame_Pwrdwn_Set( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ); +void peripheral_Mem_Frame_Pwrdwn_Clr( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ); + +void pcrGetConfigValue( pcr_config_reg_t * config_reg, config_value_type_t type ); + +/**@}*/ +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef __SYS_PCR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pmm.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pmm.h new file mode 100644 index 00000000000..823dd919cd1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pmm.h @@ -0,0 +1,176 @@ +/** @file sys_pmm.h + * @brief PMM Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMM_H__ +#define __SYS_PMM_H__ + +#include "reg_pmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Bit Masks */ +#define PMM_LOGICPDPWRCTRL0_LOGICPDON0 0x0F000000U /*PD2*/ +#define PMM_LOGICPDPWRCTRL0_LOGICPDON1 0x000F0000U /*PD3*/ +#define PMM_LOGICPDPWRCTRL0_LOGICPDON2 0x00000F00U /*PD4*/ +#define PMM_LOGICPDPWRCTRL0_LOGICPDON3 0x0000000FU /*PD5*/ + +#define PMM_MEMPDPWRCTRL0_MEMPDON0 0x0F000000U /*RAM_PD1*/ +#define PMM_MEMPDPWRCTRL0_MEMPDON1 0x000F0000U /*RAM_PD2*/ +#define PMM_MEMPDPWRCTRL0_MEMPDON2 0x00000F00U /*RAM_PD3*/ + +#define PMM_LOGICPDPWRSTAT_DOMAINON 0x00000100U +#define PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT 0x00000003U +#define PMM_MEMPDPWRSTAT_DOMAINON 0x00000100U +#define PMM_MEMPDPWRSTAT_MEMPDPWRSTAT 0x00000003U +#define PMM_GLOBALCTRL1_AUTOCLKWAKEENA 0x00000001U + +/* Configuration registers initial value */ +#define PMM_LOGICPDPWRCTRL0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0x5U << 24U ) | ( uint32 ) ( ( uint32 ) 0x5U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | ( uint32 ) ( ( uint32 ) 0x5U << 0U ) ) +#define PMM_MEMPDPWRCTRL0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0x5U << 24U ) | ( uint32 ) ( ( uint32 ) 0x5U << 16U ) ) + +#define PMM_PDCLKDISREG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 0U ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 1U ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 0U ) << 2U ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 3U ) ) + +#define PMM_GLOBALCTRL1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +/** @enum pmmLogicPDTag + * @brief PMM Logic Power Domain + * + * Used to define PMM Logic Power Domain + */ +typedef enum pmmLogicPDTag +{ + PMM_LOGICPD1 = 4U, /*-- NOT USED*/ + PMM_LOGICPD2 = 0U, + PMM_LOGICPD3 = 1U, + PMM_LOGICPD4 = 2U, + PMM_LOGICPD5 = 3U +} pmm_LogicPD_t; + +/** @enum pmmMemPDTag + * @brief PMM Memory-Only Power Domain + * + * Used to define PMM Memory-Only Power Domain + */ +typedef enum pmmMemPDTag +{ + PMM_MEMPD1 = 0U, + PMM_MEMPD2 = 1U, + PMM_MEMPD3 = 2U +} pmm_MemPD_t; + +/** @enum pmmModeTag + * @brief PSCON operating mode + * + * Used to define the operating mode of PSCON Compare Block + */ +typedef enum pmmModeTag +{ + LockStep = 0x0U, + SelfTest = 0x6U, + ErrorForcing = 0x9U, + SelfTestErrorForcing = 0xFU +} pmm_Mode_t; + +typedef struct pmm_config_reg +{ + uint32 CONFIG_LOGICPDPWRCTRL0; + uint32 CONFIG_MEMPDPWRCTRL0; + uint32 CONFIG_PDCLKDISREG; + uint32 CONFIG_GLOBALCTRL1; +} pmm_config_reg_t; + +/** + * @defgroup PMM PMM + * @brief Power Management Module + * + * The PMM provides memory-mapped registers that control the states of the supported power + * domains. The PMM includes interfaces to the Power Mode Controller (PMC) and the Power + * State Controller (PSCON). The PMC and PSCON control the power up/down sequence of each + * power domain. + * + * Related files: + * - reg_pmm.h + * - sys_pmm.h + * - sys_pmm.c + * + * @addtogroup PMM + * @{ + */ + +/* Pmm Interface Functions */ +void pmmInit( void ); +void pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ); +void pmmTurnONMemPowerDomain( pmm_MemPD_t memPD ); +void pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ); +void pmmTurnOFFMemPowerDomain( pmm_MemPD_t memPD ); +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ); +boolean pmmIsMemPowerDomainActive( pmm_MemPD_t memPD ); +void pmmGetConfigValue( pmm_config_reg_t * config_reg, config_value_type_t type ); +void pmmSetMode( pmm_Mode_t mode ); +boolean pmmPerformSelfTest( void ); + +/**@}*/ +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* ifndef __SYS_PMM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pmu.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pmu.h new file mode 100644 index 00000000000..93605e2e584 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_pmu.h @@ -0,0 +1,244 @@ +/** @file sys_pmu.h + * @brief System Pmu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Pmu Interface Functions + * . + * which are relevant for the performance monitor unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMU_H__ +#define __SYS_PMU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def pmuCOUNTER0 + * @brief pmu event counter 0 mask + * + * Alias for pmu event counter 0 mask + * + * @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and + *_pmuStopCounters_ + */ +#define pmuCOUNTER0 0x00000001U + +/** @def pmuCOUNTER1 + * @brief pmu event counter 1 mask + * + * Alias for pmu event counter 1 mask + * + * @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and + *_pmuStopCounters_ + */ +#define pmuCOUNTER1 0x00000002U + +/** @def pmuCOUNTER2 + * @brief pmu event counter 2 mask + * + * Alias for pmu event counter 2 mask + * + * @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and + *_pmuStopCounters_ + */ +#define pmuCOUNTER2 0x00000004U + +/** @def pmuCYCLE_COUNTER + * @brief pmu cycle counter mask + * + * Alias for pmu event counter mask + * + * @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and + *_pmuStopCounters_ + */ +#define pmuCYCLE_COUNTER 0x80000000U + +/** @enum pmuEvent + * @brief pmu event + * + * Alias for pmu event counter increment source + */ +enum pmuEvent +{ + PMU_INST_CACHE_MISS = 0x01U, + PMU_DATA_CACHE_MISS = 0x03U, + PMU_DATA_CACHE_ACCESS = 0x04U, + PMU_DATA_READ_ARCH_EXECUTED = 0x06U, + PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U, + PMU_INST_ARCH_EXECUTED = 0x08U, + PMU_EXCEPTION_TAKEN = 0x09U, + PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU, + PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU, + PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU, + PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU, + PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU, + PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU, + PMU_BRANCH_MISSPREDICTED = 0x10U, + PMU_CYCLE_COUNT = 0x11U, + PMU_PREDICTABLE_BRANCHES = 0x12U, + PMU_INST_BUFFER_STALL = 0x40U, + PMU_DATA_DEPENDENCY_INST_STALL = 0x41U, + PMU_DATA_CACHE_WRITE_BACK = 0x42U, + PMU_EXT_MEMORY_REQUEST = 0x43U, + PMU_LSU_BUSY_STALL = 0x44U, + PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U, + PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U, + PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U, + PMU_ETMEXTOUT_0 = 0x48U, + PMU_ETMEXTOUT_1 = 0x49U, + PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU, + PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU, + PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU, + PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU, + PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU, + PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU, + PMU_STORE_BUFFER_MERGE = 0x50U, + PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U, + PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U, + PMU_INTEGER_DIV_EXECUTED = 0x53U, + PMU_STALL_INTEGER_DIV = 0x54U, + PMU_PLD_INST_LINE_FILL = 0x55U, + PMU_PLD_INST_NO_LINE_FILL = 0x56U, + PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U, + PMU_INST_CACHE_ACCESS = 0x58U, + PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U, + PMU_DUAL_ISSUE_CASE_A = 0x5AU, + PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU, + PMU_DUAL_ISSUE_OTHER = 0x5CU, + PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU, + PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU, + PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U, + PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U, + PMU_PROCESSOR_LIVE_LOCK = 0x62U, + PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U, + PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U, + PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U, + PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U, + PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U, + PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U, + PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU, + PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU, + PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU, + PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU +}; + +/** @fn void _pmuInit_(void) + * @brief Initialize Performance Monitor Unit + */ +void _pmuInit_( void ); + +/** @fn void _pmuEnableCountersGlobal_(void) + * @brief Enable and reset cycle counter and all 3 event counters + */ +void _pmuEnableCountersGlobal_( void ); + +/** @fn void _pmuDisableCountersGlobal_(void) + * @brief Disable cycle counter and all 3 event counters + */ +void _pmuDisableCountersGlobal_( void ); + +/** @fn void _pmuResetCycleCounter_(void) + * @brief Reset cycle counter + */ +void _pmuResetCycleCounter_( void ); + +/** @fn void _pmuResetEventCounters_(void) + * @brief Reset event counters 0-2 + */ +void _pmuResetEventCounters_( void ); + +/** @fn void _pmuResetCounters_(void) + * @brief Reset cycle counter and event counters 0-2 + */ +void _pmuResetCounters_( void ); + +/** @fn void _pmuStartCounters_(uint32 counters) + * @brief Starts selected counters + * @param[in] counters - Counter mask + */ +void _pmuStartCounters_( uint32 counters ); + +/** @fn void _pmuStopCounters_(uint32 counters) + * @brief Stops selected counters + * @param[in] counters - Counter mask + */ +void _pmuStopCounters_( uint32 counters ); + +/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event) + * @brief Set event counter count event + * @param[in] counter - Counter select 0..2 + * @param[in] event - Count event + */ +void _pmuSetCountEvent_( uint32 counter, uint32 event ); + +/** @fn uint32 _pmuGetCycleCount_(void) + * @brief Returns current cycle counter value + * + * @return cycle count. + */ +uint32 _pmuGetCycleCount_( void ); + +/** @fn uint32 _pmuGetEventCount_(uint32 counter) + * @brief Returns current event counter value + * @param[in] counter - Counter select 0..2 + * + * @return event counter count. + */ +uint32 _pmuGetEventCount_( uint32 counter ); + +/** @fn uint32 _pmuGetOverflow_(void) + * @brief Returns current overflow register and clear flags + * + * @return overflow flags. + */ +uint32 _pmuGetOverflow_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ +#endif /* ifndef __SYS_PMU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_selftest.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_selftest.h new file mode 100644 index 00000000000..5463202ceaf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/sys_selftest.h @@ -0,0 +1,484 @@ +/** @file sys_selftest.h + * @brief System Memory Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Efuse Self Test Functions + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __sys_selftest_H__ +#define __sys_selftest_H__ + +#include "reg_pbist.h" +#include "reg_stc.h" +#include "reg_efc.h" +#include "sys_core.h" +#include "system.h" +#include "sys_vim.h" +#include "adc.h" +#include "can.h" +#include "mibspi.h" +#include "het.h" +#include "htu.h" +#include "esm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define flash1bitError ( *( volatile uint32 * ) ( 0xF00803F0U ) ) +#define flash2bitError ( *( volatile uint32 * ) ( 0xF00803F8U ) ) + +#define tcramA1bitError ( *( volatile uint32 * ) ( 0x08400000U ) ) +#define tcramA2bitError ( *( volatile uint32 * ) ( 0x08400010U ) ) + +#define tcramB1bitError ( *( volatile uint32 * ) ( 0x08400008U ) ) +#define tcramB2bitError ( *( volatile uint32 * ) ( 0x08400018U ) ) + +#define tcramA1bit ( *( volatile uint64 * ) ( 0x08000000U ) ) +#define tcramA2bit ( *( volatile uint64 * ) ( 0x08000010U ) ) + +#define tcramB1bit ( *( volatile uint64 * ) ( 0x08000008U ) ) +#define tcramB2bit ( *( volatile uint64 * ) ( 0x08000018U ) ) + +#define flashBadECC1 ( *( volatile uint32 * ) ( 0x20000000U ) ) +#define flashBadECC2 ( *( volatile uint32 * ) ( 0x20000010U ) ) + +#define CCMSR ( *( volatile uint32 * ) ( 0xFFFFF600U ) ) +#define CCMKEYR ( *( volatile uint32 * ) ( 0xFFFFF604U ) ) + +#define DMA_PARCR ( *( volatile uint32 * ) ( 0xFFFFF1A8U ) ) +#define DMA_PARADDR ( *( volatile uint32 * ) ( 0xFFFFF1ACU ) ) +#define DMARAMLOC ( *( volatile uint32 * ) ( 0xFFF80000U ) ) +#define DMARAMPARLOC ( *( volatile uint32 * ) ( 0xFFF80A00U ) ) + +#define MIBSPI1RAMLOC ( *( volatile uint32 * ) ( 0xFF0E0000U ) ) +#define MIBSPI3RAMLOC ( *( volatile uint32 * ) ( 0xFF0C0000U ) ) +#define MIBSPI5RAMLOC ( *( volatile uint32 * ) ( 0xFF0A0000U ) ) + +#ifndef __PBIST_H__ + #define __PBIST_H__ + +/** @enum pbistPort + * @brief Alias names for pbist Port number + * + * This enumeration is used to provide alias names for the pbist Port number + * - PBIST_PORT0 + * - PBIST_PORT1 + * + * @note Check the datasheet for the port avaiability + */ +enum pbistPort +{ + PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */ + PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability + > */ +}; + +/** @enum pbistAlgo + * @brief Alias names for pbist Algorithm + * + * This enumeration is used to provide alias names for the pbist Algorithm + */ +enum pbistAlgo +{ + PBIST_TripleReadSlow = 0x00000001U, /**> 16U ) +#define SYS_EXCEPTION ( *( volatile uint32 * ) 0xFFFFFFE4U ) + +#define POWERON_RESET 0x8000U +#define OSC_FAILURE_RESET 0x4000U +#define WATCHDOG_RESET 0x2000U +#define ICEPICK_RESET 0x2000U +#define CPU_RESET 0x0020U +#define SW_RESET 0x0010U + +#define WATCHDOG_STATUS ( *( volatile uint32 * ) 0xFFFFFC98U ) +#define DEVICE_ID_REV ( *( volatile uint32 * ) 0xFFFFFFF0U ) + +/** @def OSC_FREQ + * @brief Oscillator clock source exported from HALCoGen GUI + * + * Oscillator clock source exported from HALCoGen GUI + */ +#define OSC_FREQ 16.0F + +/** @def PLL1_FREQ + * @brief PLL 1 clock source exported from HALCoGen GUI + * + * PLL 1 clock source exported from HALCoGen GUI + */ +#define PLL1_FREQ 220.00F + +/** @def LPO_LF_FREQ + * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI + * + * LPO Low Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_LF_FREQ 0.080F + +/** @def LPO_HF_FREQ + * @brief LPO High Freq Oscillator source exported from HALCoGen GUI + * + * LPO High Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_HF_FREQ 10.000F + +/** @def PLL1_FREQ + * @brief PLL 2 clock source exported from HALCoGen GUI + * + * PLL 2 clock source exported from HALCoGen GUI + */ +#define PLL2_FREQ 220.00F + +/** @def GCLK_FREQ + * @brief GCLK domain frequency exported from HALCoGen GUI + * + * GCLK domain frequency exported from HALCoGen GUI + */ +#define GCLK_FREQ 220.000F + +/** @def HCLK_FREQ + * @brief HCLK domain frequency exported from HALCoGen GUI + * + * HCLK domain frequency exported from HALCoGen GUI + */ +#define HCLK_FREQ 220.000F + +/** @def RTI_FREQ + * @brief RTI Clock frequency exported from HALCoGen GUI + * + * RTI Clock frequency exported from HALCoGen GUI + */ +#define RTI_FREQ 110.000F + +/** @def AVCLK1_FREQ + * @brief AVCLK1 Domain frequency exported from HALCoGen GUI + * + * AVCLK Domain frequency exported from HALCoGen GUI + */ +#define AVCLK1_FREQ 110.000F + +/** @def AVCLK2_FREQ + * @brief AVCLK2 Domain frequency exported from HALCoGen GUI + * + * AVCLK2 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK2_FREQ 0.000F + +/** @def AVCLK3_FREQ + * @brief AVCLK3 Domain frequency exported from HALCoGen GUI + * + * AVCLK3 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK3_FREQ 110.000F + +/** @def AVCLK4_FREQ + * @brief AVCLK4 Domain frequency exported from HALCoGen GUI + * + * AVCLK4 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK4_FREQ 110.000F + +/** @def VCLK1_FREQ + * @brief VCLK1 Domain frequency exported from HALCoGen GUI + * + * VCLK1 Domain frequency exported from HALCoGen GUI + */ +#define VCLK1_FREQ 110.000F + +/** @def VCLK2_FREQ + * @brief VCLK2 Domain frequency exported from HALCoGen GUI + * + * VCLK2 Domain frequency exported from HALCoGen GUI + */ +#define VCLK2_FREQ 110.000F + +/** @def VCLK3_FREQ + * @brief VCLK3 Domain frequency exported from HALCoGen GUI + * + * VCLK3 Domain frequency exported from HALCoGen GUI + */ +#define VCLK3_FREQ 110.000F + +/** @def VCLK4_FREQ + * @brief VCLK4 Domain frequency exported from HALCoGen GUI + * + * VCLK4 Domain frequency exported from HALCoGen GUI + */ +#define VCLK4_FREQ 110.000F + +/** @def SYS_PRE1 + * @brief Alias name for RTI1CLK PRE clock source + * + * This is an alias name for the RTI1CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 " Value comes from GUI drop down option " */ +#define SYS_PRE1 ( SYS_PLL1 ) + +/** @def SYS_PRE2 + * @brief Alias name for RTI2CLK pre clock source + * + * This is an alias name for the RTI2CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 " Value comes from GUI drop down option " */ +#define SYS_PRE2 ( SYS_PLL1 ) + +/* Configuration registers */ +typedef struct system_config_reg +{ + uint32 CONFIG_SYSPC1; + uint32 CONFIG_SYSPC2; + uint32 CONFIG_SYSPC7; + uint32 CONFIG_SYSPC8; + uint32 CONFIG_SYSPC9; + uint32 CONFIG_CSDIS; + uint32 CONFIG_CDDIS; + uint32 CONFIG_GHVSRC; + uint32 CONFIG_VCLKASRC; + uint32 CONFIG_RCLKSRC; + uint32 CONFIG_MSTGCR; + uint32 CONFIG_MINITGCR; + uint32 CONFIG_MSINENA; + uint32 CONFIG_PLLCTL1; + uint32 CONFIG_PLLCTL2; + uint32 CONFIG_UERFLAG; + uint32 CONFIG_LPOMONCTL; + uint32 CONFIG_CLKTEST; + uint32 CONFIG_DFTCTRLREG1; + uint32 CONFIG_DFTCTRLREG2; + uint32 CONFIG_GPREG1; + uint32 CONFIG_RAMGCR; + uint32 CONFIG_BMMCR1; + uint32 CONFIG_MMUGCR; + uint32 CONFIG_CLKCNTL; + uint32 CONFIG_ECPCNTL; + uint32 CONFIG_DEVCR1; + uint32 CONFIG_SYSECR; + uint32 CONFIG_PLLCTL3; + uint32 CONFIG_STCCLKDIV; + uint32 CONFIG_CLK2CNTL; + uint32 CONFIG_VCLKACON1; + uint32 CONFIG_CLKSLIP; + uint32 CONFIG_EFC_CTLEN; +} system_config_reg_t; + +/* Configuration registers initial value */ +#define SYS_SYSPC1_CONFIGVALUE 0U + +#define SYS_SYSPC2_CONFIGVALUE 1U + +#define SYS_SYSPC7_CONFIGVALUE 0U + +#define SYS_SYSPC8_CONFIGVALUE 0U + +#define SYS_SYSPC9_CONFIGVALUE 1U + +#define SYS_CSDIS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x4U ) + +#define SYS_CDDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) ) + +#define SYS_GHVSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_OSC << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_OSC << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ) ) + +#define SYS_VCLKASRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_RCLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_MSTGCR_CONFIGVALUE 0x00000105U + +#define SYS_MINITGCR_CONFIGVALUE 0x5U + +#define SYS_MSINENA_CONFIGVALUE 0U + +#define SYS_PLLCTL1_CONFIGVALUE_1 \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) ( 6U - 1U ) << 16U ) | ( uint32 ) ( 0xA400U ) ) + +#define SYS_PLLCTL1_CONFIGVALUE_2 \ + ( ( ( SYS_PLLCTL1_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) + +#define SYS_PLLCTL2_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 255U << 22U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 9U ) | ( uint32 ) 61U ) + +#define SYS_UERFLAG_CONFIGVALUE 0U + +#define SYS_LPOMONCTL_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | LPO_TRIM_VALUE ) +#define SYS_LPOMONCTL_CONFIGVALUE_2 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 16U << 8U ) | 16U ) + +#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U + +#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U + +#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U + +#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU + +#define SYS_RAMGCR_CONFIGVALUE 0x00050000U + +#define SYS_BMMCR1_CONFIGVALUE 0xAU + +#define SYS_MMUGCR_CONFIGVALUE 0U + +#define SYS_CLKCNTL_CONFIGVALUE \ + ( 0x00000100U | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define SYS_ECPCNTL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ) ) + +#define SYS_DEVCR1_CONFIGVALUE 0xAU + +#define SYS_SYSECR_CONFIGVALUE 0x00004000U +#define SYS2_PLLCTL3_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) \ + | ( uint32 ) ( ( uint32 ) ( 6U - 1U ) << 16U ) | ( uint32 ) ( 0xA400U ) ) + +#define SYS2_PLLCTL3_CONFIGVALUE_2 \ + ( ( ( SYS2_PLLCTL3_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) +#define SYS2_STCCLKDIV_CONFIGVALUE 0U +#define SYS2_CLK2CNTL_CONFIGVALUE ( 1U | 0x00000100U ) +#define SYS2_VCLKACON1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 1U << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) +#define SYS2_CLKSLIP_CONFIGVALUE 0x5U +#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U + +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* FlashW General Definitions */ + +/** @enum flashWPowerModes + * @brief Alias names for flash bank power modes + * + * This enumeration is used to provide alias names for the flash bank power modes: + * - sleep + * - standby + * - active + */ +enum flashWPowerModes +{ + SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ + SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ + SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ +}; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define FSM_WR_ENA_HL ( *( volatile uint32 * ) 0xFFF87288U ) +#define EEPROM_CONFIG_HL ( *( volatile uint32 * ) 0xFFF872B8U ) + +/* Configuration registers */ +typedef struct tcmflash_config_reg +{ + uint32 CONFIG_FRDCNTL; + uint32 CONFIG_FEDACCTRL1; + uint32 CONFIG_FEDACCTRL2; + uint32 CONFIG_FEDACSDIS; + uint32 CONFIG_FBPROT; + uint32 CONFIG_FBSE; + uint32 CONFIG_FBAC; + uint32 CONFIG_FBFALLBACK; + uint32 CONFIG_FPAC1; + uint32 CONFIG_FPAC2; + uint32 CONFIG_FMAC; + uint32 CONFIG_FLOCK; + uint32 CONFIG_FDIAGCTRL; + uint32 CONFIG_FEDACSDIS2; +} tcmflash_config_reg_t; + +/* Configuration registers initial value */ +#define TCMFLASH_FRDCNTL_CONFIGVALUE \ + ( 0x00000000U | ( uint32 ) ( ( uint32 ) 3U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | 1U ) +#define TCMFLASH_FEDACCTRL1_CONFIGVALUE 0x000A0005U +#define TCMFLASH_FEDACCTRL2_CONFIGVALUE 0U +#define TCMFLASH_FEDACSDIS_CONFIGVALUE 0U +#define TCMFLASH_FBPROT_CONFIGVALUE 0U +#define TCMFLASH_FBSE_CONFIGVALUE 0U +#define TCMFLASH_FBAC_CONFIGVALUE 0xFU +#define TCMFLASH_FBFALLBACK_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) | ( uint32 ) ( ( uint32 ) 3U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 10U ) | ( uint32 ) ( ( uint32 ) 3U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 6U ) | ( uint32 ) ( ( uint32 ) 3U << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ) ) + +#define TCMFLASH_FPAC1_CONFIGVALUE 0x00C80001U +#define TCMFLASH_FPAC2_CONFIGVALUE 0U +#define TCMFLASH_FMAC_CONFIGVALUE 0U +#define TCMFLASH_FLOCK_CONFIGVALUE 0x55AAU +#define TCMFLASH_FDIAGCTRL_CONFIGVALUE 0x000A0000U +#define TCMFLASH_FEDACSDIS2_CONFIGVALUE 0U + +void tcmflashGetConfigValue( tcmflash_config_reg_t * config_reg, + config_value_type_t type ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/* System Interface Functions */ +void setupPLL( void ); +void trimLPO( void ); +void customTrimLPO( void ); +void setupFlash( void ); +void periphInit( void ); +void mapClocks( void ); +void systemInit( void ); +void systemPowerDown( uint32 mode ); + +/*Configuration registers + * index 0: Even RAM + * index 1: Odd RAM + */ +typedef struct sram_config_reg +{ + uint32 CONFIG_RAMCTRL[ 2U ]; + uint32 CONFIG_RAMTHRESHOLD[ 2U ]; + uint32 CONFIG_RAMINTCTRL[ 2U ]; + uint32 CONFIG_RAMTEST[ 2U ]; + uint32 CONFIG_RAMADDRDECVECT[ 2U ]; +} sram_config_reg_t; + +/* Configuration registers initial value */ +#define SRAM_RAMCTRL_CONFIGVALUE 0x0005000AU +#define SRAM_RAMTHRESHOLD_CONFIGVALUE 1U +#define SRAM_RAMINTCTRL_CONFIGVALUE 1U +#define SRAM_RAMTEST_CONFIGVALUE 0x5U +#define SRAM_RAMADDRDECVECT_CONFIGVALUE 0U + +void sramGetConfigValue( sram_config_reg_t * config_reg, config_value_type_t type ); +#ifdef __cplusplus +} +#endif /*extern "C" */ +#endif /* ifndef __SYS_SYSTEM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee.h new file mode 100644 index 00000000000..955c465d5e7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee.h @@ -0,0 +1,571 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.01 29Oct2012 Vishwanath Reddy 0000000000000 Changes for + *implementing Error Recovery 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 + *Misra Fixes, Memory segmentation changes. 00.01.03 14Jan2013 Vishwanath Reddy + *SDOCM00098510 Changes as requested by Vector. 00.01.04 12Feb2012 Vishwanath + *Reddy SDOCM00099152 Integration issues fix. 00.01.05 04Mar2013 Vishwanath + *Reddy SDOCM00099152 Added Deleting a block feature, bug fixes. 00.01.06 + *11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : copying of + *unconfigured blocks. 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 + *Added feature : Number of 8 bytes writes, fixed issue with copy blocks. 00.01.08 + *05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature : CRC check for + *unconfigured blocks, Main function modified to complete writes as fast as possible, + *Added Non polling mode support. 00.01.09 19Apr2013 Vishwanath Reddy + *SDOCM00099152 Warning removal, Added feature comparision of data during write. + * 00.01.10 11Jun2013 Vishwanath Reddy SDOCM00101845 Updated version + *information. 00.01.11 05Jul2013 Vishwanath Reddy SDOCM00101643 Updated + *version information. 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 + *Traceability tags added. MISRA C fixes. Version info corrected. 01.13.00 30Dec2013 + *Vishwanath Reddy 0000000000000 Undated version info for SDOCM00107976 and + *SDOCM00105795. 01.13.01 19May2014 Vishwanath Reddy 0000000000000 + *Updated version info for SDOCM00107913 and SDOCM00107622. 01.13.02 12Jun2014 + *Vishwanath Reddy 0000000000000 Updated version info for SDOCM00108238 01.14.00 + *26Mar2014 Vishwanath Reddy Update version info for + *SDOCM00107161. 01.15.00 06Jun2014 Vishwanath Reddy Support for Conqueror. + * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA + *warnings. 01.16.01 12Sep2014 Vishwanath Reddy SDOCM00112930 Prototype + *for TI_Fee_SuspendResumeErase added. TI_Fee_EraseCommandType enum added. extern added + *for TI_Fee_bEraseSuspended. 01.17.00 15Oct2014 Vishwanath Reddy SDOCM00113379 + *RAM Optimization changes. 01.17.01 30Oct2014 Vishwanath Reddy SDOCM00113536 + *Support for TMS570LS07xx,TMS570LS09xx, TMS570LS05xx, RM44Lx. 01.17.02 26Dec2014 + *Vishwanath Reddy SDOCM00114102 FLEE Errata Fix. SDOCM00114104 Change ALL 1's + *OK check condition. Updated version info. Added new macros. SDOCM00114423 Add new enum + *TI_Fee_DeviceType. Add new variable TI_Fee_MaxSectors and prototype + *TI_FeeInternal_PopulateStructures. 01.18.00 12Oct2015 Vishwanath Reddy + *SDOCM00119455 Update version history. Update ti_fee_util.c file for the bugfix "If + *morethan one data set is config- ured, then a valid block may get invalidated if + * multiple valid blocks + *are present in FEE memory. 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 + *Update version history. In TI_FeeInternal_FeeManager, do not change the state to + *IDLE,after completing the copy operation. 01.18.02 05Feb2016 Vishwanath + *Reddy SDOCM00121158 Update version history. Add a call of + *TI_FeeInternal_PollFlashStatus() before reading data from FEE bank in + * TI_FeeInternal_UpdateBlockOffsetArray(), + * TI_Fee_WriteAsync(),TI_Fee_WriteSync(), + * TI_Fee_ReadSync(), + *TI_Fee_Read() 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update + *patch version TI_FEE_SW_PATCH_VERSION. TI_FEE_FLASH_CRC_ENABLE is renamed to + * TI_FEE_FLASH_CHECKSUM_ENABLE. + * SDOCM00122429 In ti_fee_types.h, + *add error when endianess is not defined. 01.19.00 08Augu2016 Vishwanath Reddy + *SDOCM00122592 Update patch version TI_FEE_MINOR_VERSION. Code for using partially + *ersed sector is now removed. Bugfix for FEE reading from unimplemented memory space. + * 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update patch version + *TI_FEE_MINOR_VERSION. Synchronous write API modified to avoid copy of already copied + *block. 01.19.02 25Janu2017 Vishwanath Reddy SDOCM00122832 Update patch + *version TI_FEE_MINOR_VERSION. Format API modified to erase all configured VS. + * SDOCM00122833 In API + *TI_Fee_ErrorRecovery, added polling for flash status before calling TI_Fee_Init. + * 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Added + *TI_Fee_bIsMainFunctionCalled Global Variable. 01.19.04 05Dec2017 Prathap + *Srinivasan HERCULES_SW-5082 Update version history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_H + #define TI_FEE_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "hal_stdtypes.h" + #include "fee_interface.h" + #include "ti_fee_types.h" + #include "ti_fee_cfg.h" + + /********************************************************************************************************************** + * GLOBAL CONSTANT MACROS + *********************************************************************************************************************/ + /* Fee Published Information */ + #define TI_FEE_MAJOR_VERSION 3U + #define TI_FEE_MINOR_VERSION 0U + #define TI_FEE_PATCH_VERSION 2U + #define TI_FEE_SW_MAJOR_VERSION 1U + #define TI_FEE_SW_MINOR_VERSION 19U + #define TI_FEE_SW_PATCH_VERSION 4U + + #define TI_FEE_VIRTUAL_SECTOR_VERSION 1U + + /* Virtual sector states */ + #define ActiveVSHi 0x0000FFFFU + #define ActiveVSLo 0x00000000U + #define CopyVSHi 0xFFFFFFFFU + #define CopyVSLo 0x00000000U + #define EmptyVSHi 0xFFFFFFFFU + #define EmptyVSLo 0x0000FFFFU + #define InvalidVSHi 0xFFFFFFFFU + #define InvalidVSLo 0xFFFFFFFFU + #define ReadyforEraseVSHi 0x00000000U + #define ReadyforEraseVSLo 0x00000000U + + /* Data Block states*/ + #define EmptyBlockHi 0xFFFFFFFFU + #define EmptyBlockLo 0xFFFFFFFFU + #define StartProgramBlockHi 0xFFFF0000U + #define StartProgramBlockLo 0xFFFFFFFFU + #define ValidBlockHi 0x00000000U + #define ValidBlockLo 0xFFFFFFFFU + #define InvalidBlockHi 0x00000000U + #define InvalidBlockLo 0xFFFF0000U + #define CorruptBlockHi 0x00000000U + #define CorruptBlockLo 0x00000000U + + #define FEE_BANK 0U + + /* Enable/Disable FEE sectors */ + #define FEE_DISABLE_SECTORS_31_00 0x00000000U + #define FEE_DISABLE_SECTORS_63_32 0x00000000U + #define FEE_ENABLE_SECTORS_31_00 0xFFFFFFFFU + #define FEE_ENABLE_SECTORS_63_32 0xFFFFFFFFU + +/********************************************************************************************************************** + * GLOBAL DATA TYPES AND STRUCTURES + *********************************************************************************************************************/ +/* Structures used */ +/* Enum to describe the Fee Status types */ +typedef enum +{ + TI_FEE_OK = 0U, /* Function returned no error */ + TI_FEE_ERROR = 1U /* Function returned an error */ +} TI_Fee_StatusType; + +/* Enum to describe the Virtual Sector State */ +typedef enum +{ + VsState_Invalid = 1U, + VsState_Empty = 2U, + VsState_Copy = 3U, + VsState_Active = 4U, + VsState_ReadyForErase = 5U +} VirtualSectorStatesType; + +/* Enum to describe the Block State */ +typedef enum +{ + Block_StartProg = 1U, + Block_Valid = 2U, + Block_Invalid = 3U +} BlockStatesType; + +/* Enum for error trpes */ +typedef enum +{ + Error_Nil = 0U, + Error_TwoActiveVS = 1U, + Error_TwoCopyVS = 2U, + Error_SetupStateMachine = 3U, + Error_CopyButNoActiveVS = 4U, + Error_NoActiveVS = 5U, + Error_BlockInvalid = 6U, + Error_NullDataPtr = 7U, + Error_NoFreeVS = 8U, + Error_InvalidVirtualSectorParameter = 9U, + Error_ExceedSectorOnBank = 10U, + Error_EraseVS = 11U, + Error_BlockOffsetGtBlockSize = 12U, + Error_LengthParam = 13U, + Error_FeeUninit = 14U, + Error_Suspend = 15U, + Error_InvalidBlockIndex = 16U, + Error_NoErase = 17U, + Error_CurrentAddress = 18U, + Error_Exceed_No_Of_DataSets = 19U +} TI_Fee_ErrorCodeType; + +typedef enum +{ + Suspend_Erase = 0U, + Resume_Erase +} TI_Fee_EraseCommandType; + +/* Enum to describe the Device types */ +typedef enum +{ + CHAMPION = 0U, /* Function returned no error */ + ARCHER = 1U /* Function returned an error */ +} TI_Fee_DeviceType; + +typedef uint32 TI_Fee_AddressType; /* Used for defining variables to indicate number of + * bytes for address offset */ +typedef uint32 TI_Fee_LengthType; /* Used for defining variables to indicate number of + * bytes per read/write/erase */ +typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType; + +/* Structure used when defining virtual sectors */ +/* The following error checks need to be performed: */ +/* Virtual Sector definitions are not allowed to overlap */ +/* Virtual Sector definition is at least twice the size in bytes of the total size of all + * defined blocks */ +/* We will need to define a formula to indicate if the number of write cycles indicated in + * the block definitions */ +/* is possible in the defined Virtual Sector. */ +/* Ending sector cannot be less than Starting sector */ +typedef struct +{ + uint16 FeeVirtualSectorNumber; /* Virtual Sector's Number - 0 and 0xFFFF values are + not allowed*/ + /* Minimum 1, Maximum 4 */ + uint16 FeeFlashBank; /* Flash Bank to use for virtual sector. */ + + /* As we do not allow Flash EEPROM Emulation in Bank 0, + * 0 is not a valid option */ + /* Defaultvalue 1, Minimum 1, Maxiumum 7 */ + Fapi_FlashSectorType FeeStartSector; /* Defines the Starting Sector inthe Bank for + this VirtualSector*/ + Fapi_FlashSectorType FeeEndSector; /* Defines the Ending Sector inthe Bank for this + Virtual Sector */ + + /* Start and End sectors can be the same, which indicates only + * one sector */ + /* is the entire virtual sector. */ + /* Values are based on the FLASH_SECT enum */ + + /* Defaultvalue and Min is the same sector defined as the starting + * sector */ + /* Max values are based onthe device definition file being used.*/ +} Fee_VirtualSectorConfigType; + +/* Structure used when defining blocks */ +typedef struct +{ + uint16 FeeBlockNumber; /* Block's Number - 0 and 0xFFFF values are not allowed */ + /* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */ + uint16 FeeBlockSize; /* Block's Size - Actual number of bits used is reduced */ + /* by number of bits used for dataset. */ + /* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */ + boolean FeeImmediateData; /* Indicates if the block is used for immediate data */ + /* Default: False */ + uint32 FeeNumberOfWriteCycles; /* Number of write cycles this block requires */ + + /* Default: 0, but this will not be a valid number. + * Force customer to select a value */ + /* Min 1, Max (2^32)-1 */ + uint8 FeeDeviceIndex; /* Device Index - This will always be 0 */ + /* Fixed value: 0 */ + uint8 FeeNumberOfDataSets; /* Number of DataSets for the Block */ + /* Default value: 1 */ + uint8 FeeEEPNumber; +} Fee_BlockConfigType; + +/* Structure used for Global variables */ +typedef struct +{ + TI_Fee_AddressType Fee_oFlashNextAddress; /* The next Flash Address to write to */ + TI_Fee_AddressType Fee_oCopyCurrentAddress; /* Indicates the Address within the Active + * VS which will be copied to Copy VS */ + TI_Fee_AddressType Fee_oCopyNextAddress; /* Indicates the Address within the Copy VS + * to which the data from Active VS will be + * copied to */ + TI_Fee_AddressType Fee_u32nextwriteaddress; /* Indicates the next free Address within + * the curent VS to which the data will be + * written */ + TI_Fee_AddressType Fee_oVirtualSectorStartAddress; /* Start Address of the current + Virtual Sector */ + TI_Fee_AddressType Fee_oVirtualSectorEndAddress; /* End Address of the current Virtual + Sector */ + TI_Fee_AddressType Fee_oCopyVirtualSectorAddress; /* Start Address of the Copy Virtual + Address */ + TI_Fee_AddressType Fee_oCurrentStartAddress; /* Start Address of the Previous Block */ + TI_Fee_AddressType Fee_oCurrentBlockHeader; /* Start Address of the Block which is + * being currently written*/ + TI_Fee_AddressType Fee_oWriteAddress; /* Address within the VS where data is to be + written */ + TI_Fee_AddressType Fee_oCopyWriteAddress; /* Address within the VS where data is to be + copied */ + TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; /* Start Address of the Active VS + */ + TI_Fee_AddressType Fee_oBlankFailAddress; /* Address of first non-blank location */ + TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress; /* Start Address of the + active VS */ + TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress; /* End Address of the active VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress; /* Start Address of the Copy VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress; /* End Address of the Copy VS */ + TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress; /* Next write address in Active VS + */ + TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress; /* Next write address in Copy VS */ + uint16 Fee_u16CopyBlockSize; /* Indicates the size of current block in bytes which is + * been copied from Active to Copy VS */ + uint8 Fee_u8VirtualSectorStart; /* Index of the Start Sector of the VS */ + uint8 Fee_u8VirtualSectorEnd; /* Index of the End Sector of the VS */ + uint32 Fee_au32VirtualSectorStateValue[ TI_FEE_VIRTUAL_SECTOR_OVERHEAD + >> 2U ]; /* Array to store the Virtual + * Sector Header and + * Information record */ + uint8 Fee_au8VirtualSectorState[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Stores the + * state of each + * Virtual sector + */ + uint32 Fee_au32VirtualSectorEraseCount[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Array + * to + * store + * the + * erase + * count + * of each + * Virtual + * Sector*/ + uint16 Fee_au16BlockOffset[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to store within + the VS */ + uint32 Fee_au32BlockHeader[ TI_FEE_BLOCK_OVERHEAD >> 2U ]; /* Array to store the Block + Header value */ + uint8 Fee_au8BlockCopyStatus[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to storeblock + copy status */ + uint8 Fee_u8InternalVirtualSectorStart; /* Indicates internal VS start index */ + uint8 Fee_u8InternalVirtualSectorEnd; /* Indicates internal VS end index */ + TI_FeeModuleStatusType Fee_ModuleState; /* Indicates the state of the FEE module */ + TI_FeeJobResultType Fee_u16JobResult; /* Stores the Job Result of the current command + */ + TI_Fee_StatusType Fee_oStatus; /* Indicates the status of FEE */ + TI_Fee_ErrorCodeType Fee_Error; /* Indicates the Error code */ + uint16 Fee_u16CopyBlockNumber; /* Block number which is currently being copied */ + uint16 Fee_u16BlockIndex; /* Index of the Current Block */ + uint16 Fee_u16BlockCopyIndex; /* Index of the Block being copied from Copy to Active + VS */ + uint16 Fee_u16DataSetIndex; /* Index of the Current DataSet */ + uint16 Fee_u16ArrayIndex; /* Index of the Current DataSet */ + uint16 Fee_u16BlockSize; /* Size of the current block in bytes */ + uint16 Fee_u16BlockSizeinBlockHeader; /* Size of the current block. Used to write into + Block Header */ + uint16 Fee_u16BlockNumberinBlockHeader; /* Number of the current block. Used to write + into Block Header */ + uint8 Fee_u8ActiveVirtualSector; /* Indicates the FeeVirtualSectorNumber for the + Active VS */ + uint8 Fee_u8CopyVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Copy VS + */ + uint32 Fee_u32InternalEraseQueue; /* Indicates which VS can be erased when the FEE is + * in BusyInternal State*/ + uint8 Fee_u8WriteCopyVSHeader; /* Indicates the number of bytes of the Copy VS Header + * being written */ + uint8 Fee_u8WriteCount; /* Indicates the number of bytes of the Block Header being + * written */ + uint8 * Fee_pu8ReadDataBuffer; /* Pointer to read data */ + uint8 * Fee_pu8ReadAddress; /* Pointer to read address */ + uint8 * Fee_pu8Data; /* Pointer to the next data to be written to the VS */ + uint8 * Fee_pu8CopyData; /* Pointer to the next data to be copied to the VS */ + uint8 * Fee_pu8DataStart; /* Pointer to the first data to be written to the VS */ + boolean Fee_bInvalidWriteBit; /* Indicates whether the block is + * written/invalidated/erased for the first time */ + boolean Fee_bWriteData; /* Indicates that there is data which is pending to be written + * to the Block */ + boolean Fee_bWriteBlockHeader; /* Indicates whether the Block Header has been written + or not */ + boolean bWriteFirstTime; /* Indicates if the block is being written first time */ + boolean Fee_bFindNextVirtualSector; /* Indicates if there is aneed to find next free + VS */ + boolean Fee_bWriteVSHeader; /* Indicates if block header needs to be written */ + boolean Fee_bWriteStartProgram; /* Indicates if start program block header needs to be + written */ + boolean Fee_bWritePartialBlockHeader; /* Indicates if start program block header needs + to be written */ + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) + uint16 Fee_au16UnConfiguredBlockAddress + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Indicates + * number of unconfigured blocks to + * copy */ + uint8 Fee_au8UnConfiguredBlockCopyStatus + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Array to store block + * copy status */ + #endif +} TI_Fee_GlobalVarsType; + +/********************************************************************************************************************** + * EXTERN Declarations + *********************************************************************************************************************/ +/* Fee Global Variables */ +extern const Fee_BlockConfigType Fee_BlockConfiguration[ TI_FEE_NUMBER_OF_BLOCKS ]; + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF ) +extern const Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern const Device_FlashType Device_FlashDevice; + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +extern Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern Device_FlashType Device_FlashDevice; +extern uint8 TI_Fee_MaxSectors; + #endif +extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[ TI_FEE_NUMBER_OF_EEPS ]; +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[ TI_FEE_NUMBER_OF_EEPS ]; + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +extern uint32 TI_Fee_u32FletcherChecksum; + #endif +extern uint32 TI_Fee_u32BlockEraseCount; +extern uint8 TI_Fee_u8DataSets; +extern uint8 TI_Fee_u8DeviceIndex; +extern uint32 TI_Fee_u32ActCpyVS; +extern uint8 TI_Fee_u8ErrEraseVS; + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) +extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[ TI_FEE_NUMBER_OF_EEPS ]; + #endif + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern boolean Fee_bDoubleBitError; +extern boolean Fee_bSingleBitError; + #endif + #if( TI_FEE_NUMBER_OF_EEPS == 2U ) +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global; + #endif +extern boolean TI_Fee_FapiInitCalled; +extern boolean TI_Fee_bEraseSuspended; +extern boolean TI_Fee_bIsMainFunctionCalled; + +/********************************************************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + *********************************************************************************************************************/ +/* Interface Functions */ +extern void TI_Fee_Cancel( uint8 u8EEPIndex ); +extern Std_ReturnType TI_Fee_EraseImmediateBlock( uint16 BlockNumber ); +extern TI_FeeModuleStatusType TI_Fee_GetStatus( uint8 u8EEPIndex ); +extern void TI_Fee_GetVersionInfo( Std_VersionInfoType * VersionInfoPtr ); +extern void TI_Fee_Init( void ); +extern Std_ReturnType TI_Fee_InvalidateBlock( uint16 BlockNumber ); +extern Std_ReturnType TI_Fee_Read( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); +extern Std_ReturnType TI_Fee_WriteAsync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern void TI_Fee_MainFunction( void ); +extern TI_Fee_ErrorCodeType TI_FeeErrorCode( uint8 u8EEPIndex ); +extern void TI_Fee_ErrorRecovery( TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector ); +extern TI_FeeJobResultType TI_Fee_GetJobResult( uint8 u8EEPIndex ); +extern void TI_Fee_SuspendResumeErase( TI_Fee_EraseCommandType Command ); + + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern void TI_Fee_ErrorHookSingleBitError( void ); +extern void TI_Fee_ErrorHookDoubleBitError( void ); + #endif + + #if( TI_FEE_DRIVER == 1U ) +extern Std_ReturnType TI_Fee_WriteSync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern Std_ReturnType TI_Fee_Shutdown( void ); +extern boolean TI_Fee_Format( uint32 u32FormatKey ); +extern Std_ReturnType TI_Fee_ReadSync( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); + #endif + +/* TI Fee Internal Functions */ +TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress( uint8 u8EEPIndex ); +TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC( TI_Fee_AddressType oAddress ); +TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - + * TI_FeeInternal_GetVirtualSectorParameter name is required here."*/ +uint32 TI_FeeInternal_GetVirtualSectorParameter( Fapi_FlashSectorType oSector, + uint16 u16Bank, + boolean VirtualSectorInfo, + uint8 u8EEPIndex ); +uint32 TI_FeeInternal_PollFlashStatus( void ); +uint16 TI_FeeInternal_GetBlockSize( uint16 BlockIndex ); +uint16 TI_FeeInternal_GetBlockIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetDataSetIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetBlockNumber( uint16 BlockNumber ); +uint8 TI_FeeInternal_FindNextVirtualSector( uint8 u8EEPIndex ); +uint8 TI_FeeInternal_WriteDataF021( boolean bCopy, + uint16 u16WriteSize, + uint8 u8EEPIndex ); +boolean TI_FeeInternal_BlankCheck( uint32 u32StartAddress, + uint32 u32EndAddress, + uint16 u16Bank, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckReadParameters( uint32 u32BlockSize, + uint16 BlockOffset, + const uint8 * DataBufferPtr, + uint16 Length, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckModuleState( uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_InvalidateErase( uint16 BlockNumber ); +TI_Fee_StatusType TI_FeeInternal_FeeManager( uint8 u8EEPIndex ); +void TI_FeeInternal_WriteVirtualSectorHeader( uint8 FeeVirtualSectorNumber, + VirtualSectorStatesType VsState, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - TI_FeeInternal_GetVirtualSectorIndex + * name is required here."*/ +void TI_FeeInternal_GetVirtualSectorIndex( Fapi_FlashSectorType oSectorStart, + Fapi_FlashSectorType oSectorEnd, + uint16 u16Bank, + boolean bOperation, + uint8 u8EEPIndex ); +void TI_FeeInternal_WritePreviousBlockHeader( boolean bWrite, uint8 u8EEPIndex ); +void TI_FeeInternal_WriteBlockHeader( boolean bWrite, + uint8 u8EEPIndex, + uint16 Fee_BlockSize_u16, + uint16 u16BlockNumber ); +void TI_FeeInternal_SetClearCopyBlockState( uint8 u8EEPIndex, boolean bSetClear ); +void TI_FeeInternal_SanityCheck( uint16 BlockSize, uint8 u8EEPIndex ); +void TI_FeeInternal_StartProgramBlock( uint8 u8EEPIndex ); +void TI_FeeInternal_UpdateBlockOffsetArray( uint8 u8EEPIndex, + boolean bActCpyVS, + uint8 u8VirtualSector ); +void TI_FeeInternal_WriteInitialize( TI_Fee_AddressType oFlashNextAddress, + uint8 * DataBufferPtr, + uint8 u8EEPIndex ); +void TI_FeeInternal_CheckForError( uint8 u8EEPIndex ); +void TI_FeeInternal_EnableRequiredFlashSector( uint32 u32VirtualSectorStartAddress ); +uint16 TI_FeeInternal_GetArrayIndex( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex, + boolean bCallContext ); + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +uint32 TI_FeeInternal_Fletcher16( uint8 const * pu8data, uint16 u16Length ); + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +void TI_FeeInternal_PopulateStructures( TI_Fee_DeviceType DeviceType ); + #endif +#endif /* TI_FEE_H */ + +/********************************************************************************************************************** + * END OF FILE: ti_fee.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h new file mode 100644 index 00000000000..60e8117e6c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h @@ -0,0 +1,55 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_cfg.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: HALCoGen + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.00.01 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + *history. + * + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee_types.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee_types.h new file mode 100644 index 00000000000..ca8cf2dd996 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/ti_fee_types.h @@ -0,0 +1,259 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 03.00.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + *segmentation changes. 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 + *MISRA C fixes. 01.15.00 06Jun2014 Vishwanath Reddy Support for LC Varients. + * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA + *warnings. 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update + *version history. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + *history. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + *history. 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update + *version history. SDOCM00122429 Added error when endianess is not defined. 01.19.00 + *08Augu2016 Vishwanath Reddy SDOCM00122592 Update version history. 01.19.01 + *12Augu2016 Vishwanath Reddy SDOCM00122543 Update version history. 01.19.03 + *15May2017 Prathap Srinivasan SDOCM00122917 Update version history. 01.19.04 + *05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_TYPES_H + #define TI_FEE_TYPES_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "Device_header.h" + + #ifndef TI_Fee_None + #define TI_Fee_None \ + 0x00U /*Take no action on single bit errors, (respond with corrected data), \ + */ + /*return error for uncorrectable error reads (multibit errors for ECC or parity + * failures)*/ + /*For devices with no ECC (they may have parity or not) the only valid option is none. + */ + #endif + + #ifndef TI_Fee_Fix + #define TI_Fee_Fix 0x01U /* single bit error will be fixed by reprogramming */ + + /* return previous valid data for uncorrectable error reads (multi bit errors for ECC + * or parity failures). */ + #endif + + #if !defined( _LITTLE_ENDIAN ) && !defined( _BIG_ENDIAN ) + #error "Target Endianess is not defined. Include F021 header files and library." + #endif + +/*SAFETYMCUSW 74 S MR:18.4 "Reason - union declaration is necessary here."*/ +typedef union +{ + uint16 Fee_u16StatusWord; + #ifdef _BIG_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + } Fee_StatusWordType_ST; + #endif /* ifdef _BIG_ENDIAN */ + #ifdef _LITTLE_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + } Fee_StatusWordType_ST; + #endif /* ifdef _LITTLE_ENDIAN */ +} TI_Fee_StatusWordType_UN; + +typedef enum +{ + UNINIT, + IDLE, + /*SAFETYMCUSW 91 S MR:5.2,5.6,5.7 "Reason - BUSY in F021 is a member of + * structure."*/ + BUSY, + BUSY_INTERNAL +} TI_FeeModuleStatusType; + +typedef enum +{ + JOB_OK, + JOB_FAILED, + JOB_PENDING, + JOB_CANCELLED, + BLOCK_INCONSISTENT, + BLOCK_INVALID +} TI_FeeJobResultType; + +#endif /* TI_FEE_TYPES_H */ + +/********************************************************************************************************************** + * END OF FILE: ti_fee_types.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb-ids.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb-ids.h new file mode 100644 index 00000000000..6309eae6217 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb-ids.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file usb-ids.h + * + * @brief Definitions of VIDs and PIDs used by Stellaris USB examples. + * + */ + +#ifndef __USBIDS_H__ +#define __USBIDS_H__ + +/** *************************************************************************** + * + * TI Vendor ID. + * + *****************************************************************************/ +#define USB_VID_TI 0x0000 + +/** *************************************************************************** + * + * Product IDs. + * + *****************************************************************************/ +#define USB_PID_MOUSE 0x0000 +#define USB_PID_KEYBOARD 0x0001 +#define USB_PID_SERIAL 0x0000 +#define USB_PID_BULK 0x0003 +#define USB_PID_SCOPE 0x0004 +#define USB_PID_MSC 0x0005 +#define USB_PID_AUDIO 0x0006 +#define USB_PID_COMP_SERIAL 0x0007 +#define USB_PID_COMP_AUDIO_HID 0x0008 +#define USB_PID_COMP_HID_SER 0x0009 +#define USB_PID_DFU 0x00FF + +#endif /* __USBIDS_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb.h new file mode 100644 index 00000000000..8a1a237b48d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb.h @@ -0,0 +1,667 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef USB_H_ +#define USB_H_ + +/****************************************************************************** + * + * These macros allow conversion between 0-based endpoint indices and the + * USB_EP_x values required when calling various USB APIs. + * + *****************************************************************************/ +#define INDEX_TO_USB_EP( x ) ( ( x ) << 4u ) +#define USB_EP_TO_INDEX( x ) ( ( x ) >> 4u ) + +/****************************************************************************** + * + * The following are values that can be passed to USBFIFOConfigSet() as the + * uFIFOSize parameter. + * + *****************************************************************************/ +#define USB_FIFO_SZ_8 0x00U /* 8 byte FIFO */ +#define USB_FIFO_SZ_16 0x01U /* 16 byte FIFO */ +#define USB_FIFO_SZ_32 0x02U /* 32 byte FIFO */ +#define USB_FIFO_SZ_64 0x03U /* 64 byte FIFO */ +#define USB_FIFO_SZ_128 0x04U /* 128 byte FIFO */ +#define USB_FIFO_SZ_256 0x05U /* 256 byte FIFO */ +#define USB_FIFO_SZ_512 0x06U /* 512 byte FIFO */ +#define USB_FIFO_SZ_1024 0x07U /* 1024 byte FIFO */ + +/****************************************************************************** + * + * This macro allow conversion from a FIFO size label as defined above to + * a number of bytes + * + *****************************************************************************/ +#define USB_FIFO_SIZE_DB_FLAG 0x10U +#define USB_FIFO_SZ_TO_BYTES( x ) \ + ( uint16_t )( \ + ( uint8_t ) 8U \ + << ( ( ( uint8_t ) ( x ) & ( uint8_t ) ( ~( uint8_t ) USB_FIFO_SIZE_DB_FLAG ) ) \ + + ( uint8_t ) ( ( ( uint8_t ) ( x ) & ( uint8_t ) USB_FIFO_SIZE_DB_FLAG ) \ + >> 4U ) ) ) + +/****************************************************************************** + * + * The maximum number of independent interfaces that any single device + * implementation can support. Independent interfaces means interface + * descriptors with different bInterfaceNumber values - several interface + * descriptors offering different alternative settings but the same interface + * number count as a single interface. + * + *****************************************************************************/ +#define USB_MAX_INTERFACES_PER_DEVICE 8u + +/****************************************************************************** + * + * Following macro directives can be used for the configuring the USB device. + * Note that these directives map directly to the hardware bit definitions and + * cannot be modified to any other value. + * + *****************************************************************************/ +#define USBD_PWR_BUS_PWR ( 0x0000u ) /* Device is bus powered */ +#define USBD_PWR_SELF_PWR ( 0x0004u ) /* Device is self powered */ +#define USBD_DATA_ENDIAN_LITTLE ( 0x0000u ) /* Little Endian Data (RM48x) */ +#define USBD_DATA_ENDIAN_BIG ( 0x0080u ) /* Bit Endian Data */ +#define USBD_DMA_ENDIAN_LITTLE ( 0x0000u ) /* DMA is Little Endian */ +#define USBD_DMA_ENDIAN_BIG ( 0x0040u ) /* DMA is Big Endian */ + +/****************************************************************************** + * + * Following macro directives can be used for the configuring the Endpoints + * Note that these directives map directly to the hardware bit definitions and + * cannot be modified to any other value. + * + *****************************************************************************/ + +#define USBD_EP_DIR_IN ( 0x0010u ) /* IN Endpoint */ +#define USBD_EP_DIR_OUT ( 0x0000u ) /* OUT Endpoint */ +#define USB_EP_DEV_IN ( USBD_EP_DIR_IN ) /* IN Endpoint */ +#define USB_EP_DEV_OUT ( USBD_EP_DIR_OUT ) /* OUT Endpoint */ +#define USB_TRANS_IN ( USBD_EP_DIR_IN ) /* IN Endpoint */ +#define USB_TRANS_OUT ( USBD_EP_DIR_OUT ) /* OUT Endpoint */ +#define USB_EP_DIR_IN ( USBD_EP_DIR_IN ) +#define USB_EP_DIR_OUT ( USBD_EP_DIR_OUT ) +#define USB_TRANS_IN_LAST \ + 0u /* Used to indicate the last transaction \ + * (NOT USED in this port of USB) */ + +#define USBD_TXRX_EP_VALID_VALID ( 0x8000u ) /* EP is valid & configured */ +#define USBD_TXRX_EP_VALID_NOTVALID ( 0x0000u ) /* EP is not valid & not configured */ +#define USBD_TXRX_EP_ISO_ISO ( 0x0800u ) /* EP is of ISO type */ +#define USBD_TXRX_EP_ISO_NONISO ( 0x0000u ) /* EP is either Bulk/Interrup/Control */ +#define USBD_TXRX_EP_DB_ENABLED ( 0x4000u ) /* EP has double buffering enabled */ +/* For IN EPs DB should be enabled only in DMA mode */ +#define USBD_TXRX_EP_DB_DISABLED ( 0x0000u ) /* EP has double buffering disabled */ + +/****************************************************************************** + * + * Following macro directives are to be used for enabling/disabling interrupts + * Note that these directives map directly to the hardware bit definitions and + * cannot be modified to any other value. + * + *****************************************************************************/ +#define USBD_INT_EN_SOF_IE ( 0x0080u ) /* Start-of-Frame Interrupt */ +#define USBD_INT_EN_EPN_RX_IE ( 0x0020u ) /* Non-EP0 RX Interrupt */ +#define USBD_INT_EN_EPN_TX_IE ( 0x0010u ) /* Non-EP0 TX Interrupt */ +#define USBD_INT_EN_DS_CHG_IE ( 0x0008u ) /* Device State change interrupt */ +#define USBD_INT_EN_EP0_IE ( 0x0001u ) /* EP0 Interrupt */ +#define USBD_INT_EN_ALL \ + ( USBD_IRQ_EN_SOF_IE | USBD_IRQ_EN_EPN_RX_IE | USBD_IRQ_EN_EPN_TX_IE \ + | USBD_IRQ_EN_DS_CHG_IE | USBD_IRQ_EN_EP0_IE ) + +/****************************************************************************** + * + * Following macro directives are to be used for decoding the interrupt source + * Note that these directives map directly to the hardware bit definitions and + * cannot be modified to any other value. + * + *****************************************************************************/ +#define USBD_INT_SRC_TXN_DONE ( 0x0400u ) /* non-EP0 TX done interrupt */ +#define USBD_INT_SRC_RXN_CNT ( 0x0200u ) /* non-EP0 RX Count */ +#define USBD_INT_SRC_RXN_EOT ( 0x0100u ) /* non-EP0 RX end of transfer */ +#define USBD_INT_SRC_SOF ( 0x0080u ) /* Start-of-frame interrupt */ +#define USBD_INT_SRC_EPN_RX ( 0x0020u ) /* non-EP0 RX interrupt */ +#define USBD_INT_SRC_EPN_TX ( 0x0010u ) /* non-EP0 TX interrupt */ +#define USBD_INT_SRC_DS_CHG ( 0x0008u ) /* Device State change interrupt */ +#define USBD_INT_SRC_SETUP ( 0x0004u ) /* Setup interrupt */ +#define USBD_INT_SRC_EP0_RX ( 0x0002u ) /* EP0 RX Interrupt */ +#define USBD_INT_SRC_EP0_TX ( 0x0001u ) /* EP0 TX Interrupt */ + +/****************************************************************************** + * + * These values are used to indicate which endpoint to access. + * + *****************************************************************************/ +#define USB_EP_0 0x00000000u /* Endpoint 0 */ +#define USB_EP_1 0x00000010u /* Endpoint 1 */ +#define USB_EP_2 0x00000020u /* Endpoint 2 */ +#define USB_EP_3 0x00000030u /* Endpoint 3 */ +#define USB_EP_4 0x00000040u /* Endpoint 4 */ +#define USB_EP_5 0x00000050u /* Endpoint 5 */ +#define USB_EP_6 0x00000060u /* Endpoint 6 */ +#define USB_EP_7 0x00000070u /* Endpoint 7 */ +#define USB_EP_8 0x00000080u /* Endpoint 8 */ +#define USB_EP_9 0x00000090u /* Endpoint 9 */ +#define USB_EP_10 0x000000A0u /* Endpoint 10 */ +#define USB_EP_11 0x000000B0u /* Endpoint 11 */ +#define USB_EP_12 0x000000C0u /* Endpoint 12 */ +#define USB_EP_13 0x000000D0u /* Endpoint 13 */ +#define USB_EP_14 0x000000E0u /* Endpoint 14 */ +#define USB_EP_15 0x000000F0u /* Endpoint 15 */ +#define NUM_USB_EP 16u /* Number of supported endpoints */ + +/****************************************************************************** + * + * The following are values that can be passed to USBHostEndpointConfig() and + * USBDevEndpointConfigSet() as the ulFlags parameter. + * + *****************************************************************************/ +#define USB_EP_AUTO_SET 0x00000001u /* Auto set feature enabled */ +#define USB_EP_AUTO_REQUEST 0x00000002u /* Auto request feature enabled */ +#define USB_EP_AUTO_CLEAR 0x00000004u /* Auto clear feature enabled */ +#define USB_EP_DMA_MODE_0 0x00000008u /* Enable DMA access using mode 0 */ +#define USB_EP_DMA_MODE_1 0x00000010u /* Enable DMA access using mode 1 */ +#define USB_EP_MODE_ISOC 0x00000000u /* Isochronous endpoint */ +#define USB_EP_MODE_BULK 0x00000100u /* Bulk endpoint */ +#define USB_EP_MODE_INT 0x00000200u /* Interrupt endpoint */ +#define USB_EP_MODE_CTRL 0x00000300u /* Control endpoint */ +#define USB_EP_MODE_MASK 0x00000300u /* Mode Mask */ +#define USB_EP_SPEED_LOW 0x00000000u /* Low Speed */ +#define USB_EP_SPEED_FULL 0x00001000u /* Full Speed */ + +/****************************************************************************** + * + * The following are values that are returned from USBEndpointStatus(). The + * USB_HOST_* values are used when the USB controller is in host mode and the + * USB_DEV_* values are used when the USB controller is in device mode. + * + *****************************************************************************/ +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001u /* Receive data packet ready */ +#define USB_DEV_RX_PKT_RDY 0x00010000u /* Data packet ready */ +#define USB_DEV_TX_TXPKTRDY 0x00000001u +#define USB_DEV_TX_FIFO_NE 0x00000002u + +/****************************************************************************** + * + * This value specifies the maximum size of transfers on endpoint 0 as 64 + * bytes. This value is fixed in hardware as the FIFO size for endpoint 0. + * + *****************************************************************************/ +#define MAX_PACKET_SIZE_EP0 64u + +/****************************************************************************** + * + * Macros for hardware access, both direct and via the bit-band region. + * + *****************************************************************************/ +#define HWREG( x ) ( *( ( volatile uint32_t * ) ( x ) ) ) + +/****************************************************************************** + * + * Initialize the USB Device + * + * \param ulBase specifies the USB module base address. + * \param usFlags specifies the bus/self powered and endianness for data & dma. + * Should be a combination of the following flags + * USBD_PWR_BUS_PWR or USBD_PWR_SELF_PWR + * USBD_DATA_ENDIAN_LITTLE or USBD_DATA_ENDIAN_BIG + * USBD_DMA_ENDIAN_LITTLE or USBD_DMA_ENDIAN_BIG + * \param usFifoPtr specifies the start of the EP0 FIFO. + * + * This function will initialize the USB Device controller specified by the + * \e ulBase parameter. + * + * \return None + * + * Note This function does not intiate a device connect (pull ups are + * not enabled). Also the EP0 is intialized with FIFO size of 64Bytes. + * + * + *****************************************************************************/ +void USBDevInit( uint32 ulBase, uint16 usFlags, uint16 usFifoPtr ); + +/****************************************************************************** + * + * Initialize the USB Device's EP0 + * + * \param ulBase specifies the USB module base address. + * \param usSize FIFO size. Supported values are USB_FIFO_SZ_8/USB_FIFO_SZ_16/ + * USB_FIFO_SZ_32/USB_FIFO_SZ_64. + * \param usFifoPtr specifies the start of the EP0 FIFO. + * + * This function will initialize the USB Device controller specified by the + * \e ulBase parameter. The \e uFlags parameter is not used by this + * implementation. + * + * \return None + * + * + *****************************************************************************/ +void USBDevEp0Config( uint32 ulBase, uint16 usSize, uint16 usFifoPtr ); + +/****************************************************************************** + * + * Disable control interrupts on a given USB device controller. + * + * \param ulBase specifies the USB module base address. + * \param usFlags specifies which control interrupts to disable. + * + * This function will disable the interrupts for the USB device controller + * specified by the \e ulBase parameter. The \e usFlags parameter specifies + * which control interrupts to disable. The flags passed in the \e usFlags + * parameters should be the definitions that start with \b USBD_INT_EN_* + * + * \return None. + * + *****************************************************************************/ +void USBIntDisable( uint32 ulBase, uint16 usFlags ); + +/****************************************************************************** + * + * Enable control interrupts on a given USB device controller. + * + * \param ulBase specifies the USB module base address. + * \param usFlags specifies which control interrupts to enable. + * + * This function will enable the control interrupts for the USB device controller + * specified by the \e ulBase parameter. The \e usFlags parameter specifies + * which control interrupts to enable. The flags passed in the \e usFlags + * parameters should be the definitions that start with \b USBD_INT_EN_* and + * not any other \b USB_INT flags. + * + * \return None. + * + *****************************************************************************/ +void USBIntEnable( uint32 ulBase, uint16 usFlags ); + +/****************************************************************************** + * + * Returns the control interrupt status on a given USB device controller. + * + * \param ulBase specifies the USB module base address. + * + * This function will read interrupt status for a USB device controller. + * The bit values returned should be compared against the \b USBD_INT_SRC_* + * values. + * + * \return Returns the status of the control interrupts for a USB device controller. + * + *****************************************************************************/ +uint16 USBIntStatus( uint32 ulBase ); + +/****************************************************************************** + * + * Stalls the specified endpoint in device mode. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint specifies the endpoint to stall. + * \param usFlags specifies whether to stall the IN or OUT endpoint. + * + * This function will cause to endpoint number passed in to go into a stall + * condition. If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall + * will be issued on the IN portion of this endpoint. If the \e usFlags + * parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT + * portion of this endpoint. + * + * \note This function should only be called in device mode. + * + * \return None. + * + *****************************************************************************/ +void USBDevEndpointStall( uint32 ulBase, uint16 usEndpoint, uint16 usFlags ); + +/****************************************************************************** + * + * Clears the stall condition on the specified endpoint in device mode. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint specifies which endpoint to remove the stall condition. + * \param usFlags specifies whether to remove the stall condition from the IN + * or the OUT portion of this endpoint. + * + * This function will cause the endpoint number passed in to exit the stall + * condition. If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall + * will be cleared on the IN portion of this endpoint. If the \e usFlags + * parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT + * portion of this endpoint. + * + * \note This function should only be called in device mode. + * + * \return None. + * + *****************************************************************************/ +void USBDevEndpointStallClear( uint32 ulBase, uint16 usEndpoint, uint16 usFlags ); + +/****************************************************************************** + * + * Connects the USB device controller to the bus in device mode. + * + * \param ulBase specifies the USB module base address. + * + * This function will cause the soft connect feature of the USB device controller to + * be enabled. Call USBDisconnect() to remove the USB device from the bus. + * + * + * \return None. + * + *****************************************************************************/ +void USBDevConnect( uint32 ulBase ); + +/****************************************************************************** + * + * Removes the USB device controller from the bus in device mode. + * + * \param ulBase specifies the USB module base address. + * + * This function will cause the soft disconnect feature of the USB device controller to + * remove the device from the USB bus. A call to USBDevConnect() is needed to + * reconnect to the bus. + * + * + * \return None. + * + *****************************************************************************/ +void USBDevDisconnect( uint32 ulBase ); + +/****************************************************************************** + * + * Sets the address in device mode. + * + * \param ulBase specifies the USB module base address. + * \param ulAddress is the address to use for a device. + * + * This function will set the device address on the USB bus. This address was + * likely received via a SET ADDRESS command from the host controller. + * + * \note This function is not available on this controller. This is maintained + * for compatibility. + * + * \return None. + * + *****************************************************************************/ +void USBDevAddrSet( uint32 ulBase, uint32 ulAddress ); + +/****************************************************************************** + * + * Determine the number of bytes of data available in a given endpoint's FIFO. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * + * This function will return the number of bytes of data currently available + * in the FIFO for the given receive (OUT) endpoint. It may be used prior to + * calling USBEndpointDataGet() to determine the size of buffer required to + * hold the newly-received packet. + * + * \return This call will return the number of bytes available in a given + * endpoint FIFO. + * + *****************************************************************************/ +uint16 USBEndpointDataAvail( uint32 ulBase, uint16 usEndpoint ); + +/****************************************************************************** + * + * Retrieves data from the given endpoint's FIFO. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param pucData is a pointer to the data area used to return the data from + * the FIFO. + * \param pulSize is initially the size of the buffer passed into this call + * via the \e pucData parameter. It will be set to the amount of data + * returned in the buffer. + * + * This function will return the data from the FIFO for the given endpoint. + * The \e pulSize parameter should indicate the size of the buffer passed in + * the \e pulData parameter. The data in the \e pulSize parameter will be + * changed to match the amount of data returned in the \e pucData parameter. + * If a zero byte packet was received this call will not return a error but + * will instead just return a zero in the \e pulSize parameter. The only + * error case occurs when there is no data packet available. + * + * \return This call will return 0, or -1 if no packet was received. + * + *****************************************************************************/ +sint32 USBEndpointDataGet( uint32 ulBase, + uint16 usEndpoint, + uint8 * pucData, + uint32 * pulSize ); + +/****************************************************************************** + * + * Retrieves the setup packet from EP0 Setup FIFO + * + * \param ulBase specifies the USB module base address. + * \param sPkt Pointer to the data area for storing the setup packet. + * Atleast 8 bytes should be available. + * \param pusPktSize On return this contains the size of the setup packet (8Bytes) + * + * This function will retrieves the 8Byte long setup packet from the EP0 setup + * FIFO. + * + * \return None. + * + *****************************************************************************/ +void USBDevGetSetupPacket( uint32 ulBase, uint8 * sPkt, uint16 * pusPktSize ); + +/****************************************************************************** + * + * Acknowledge that data was read from the given endpoint's FIFO in device + * mode. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param bIsLastPacket This parameter is not used. + * + * This function acknowledges that the data was read from the endpoint's FIFO. + * The \e bIsLastPacket parameter is set to a \b true value if this is the + * last in a series of data packets on endpoint zero. The \e bIsLastPacket + * parameter is not used for endpoints other than endpoint zero. This call + * can be used if processing is required between reading the data and + * acknowledging that the data has been read. + * + * + * \return None. + * + *****************************************************************************/ +void USBDevEndpointDataAck( uint32 ulBase, uint16 usEndpoint, tBoolean bIsLastPacket ); + +/****************************************************************************** + * + * Puts data into the given endpoint's FIFO. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param pucData is a pointer to the data area used as the source for the + * data to put into the FIFO. + * \param ulSize is the amount of data to put into the FIFO. + * + * This function will put the data from the \e pucData parameter into the FIFO + * for this endpoint. If a packet is already pending for transmission then + * this call will not put any of the data into the FIFO and will return -1. + * Care should be taken to not write more data than can fit into the FIFO + * allocated by the call to USBFIFOConfig(). + * + * \return This call will return 0 on success, or -1 to indicate that the FIFO + * is in use and cannot be written. + * + *****************************************************************************/ +uint32 USBEndpointDataPut( uint32 ulBase, + uint16 usEndpoint, + uint8 * pucData, + uint32 ulSize ); + +/****************************************************************************** + * + * Starts the transfer of data from an endpoint's FIFO. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param ulTransType Not used. + * + * This function will start the transfer of data from the FIFO for a given + * endpoint. + * + * \return This call will return 0 on success, or -1 if a transmission is + * already in progress. + * + *****************************************************************************/ +uint32 USBEndpointDataSend( uint32 ulBase, uint16 usEndpoint, uint32 ulTransType ); + +/****************************************************************************** + * + * Resets the USB Device Controller + * + * \param void + * + * \return None. + * + * \note Since the USB Device reset is handled by the host, this is a dummy + * function & maintained for compatibility purpose. + * + *****************************************************************************/ +void USBReset( void ); + +/****************************************************************************** + * + * Sets the FIFO configuration for an endpoint. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param uFIFOAddress is the starting address for the FIFO. + * \param uFIFOSize is the size of the FIFO in bytes. + * \param uFlags specifies what information to set in the FIFO configuration. + * + * This function will set the starting FIFO RAM address and size of the FIFO + * for a given endpoint. Endpoint zero does not have a dynamically + * configurable FIFO so this function should not be called for endpoint zero. + * The \e uFIFOSize parameter should be one of the values in the + * \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering + * it should use the values with the \b _DB at the end of the value. For + * example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16 + * byte double buffered FIFO. If a double buffered FIFO is used, then the + * actual size of the FIFO will be twice the size indicated by the + * \e uFIFOSize parameter. This means that the \b USB_FIFO_SZ_16_DB value + * will use 32 bytes of the USB controller's FIFO memory. + * + * The \e uFIFOAddress value should be a multiple of 8 bytes and directly + * indicates the starting address in the USB controller's FIFO RAM. For + * example, a value of 64 indicates that the FIFO should start 64 bytes into + * the USB controller's FIFO memory. The \e uFlags value specifies whether + * the endpoint's OUT or IN FIFO should be configured. If in host mode, use + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use + * \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. + * + * \return None. + * + *****************************************************************************/ +void USBFIFOConfigSet( uint32 ulBase, + uint32 usEndpoint, + uint32 uFIFOAddress, + uint32 uFIFOSize, + uint16 uFlags ); + +/****************************************************************************** + * + * Gets the current configuration for an endpoint. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param pulMaxPacketSize is a pointer which will be written with the + * maximum packet size for this endpoint. + * \param puFlags is a pointer which will be written with the current + * endpoint settings. On entry to the function, this pointer must contain + * either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or + * OUT endpoint is to be queried. + * + * This function will return the basic configuration for an endpoint in device + * mode. The values returned in \e *pulMaxPacketSize and \e *puFlags are + * equivalent to the \e ulMaxPacketSize and \e uFlags previously passed to + * USBDevEndpointConfigSet() for this endpoint. + * + * \note This function should only be called in device mode. + * + * \return None. + * + *****************************************************************************/ +void USBDevEndpointConfigGet( uint32 ulBase, + uint16 usEndpoint, + uint32 * pulMaxPacketSize, + uint32 * puFlags ); + +/****************************************************************************** + * + * Sets the configuration for an endpoint. + * + * \param ulBase specifies the USB module base address. + * \param usEndpoint is the endpoint to access. + * \param ulMaxPacketSize is the maximum packet size for this endpoint. + * \param uFlags are used to configure other endpoint settings. + * + * This function will set the basic configuration for an endpoint in device + * mode. Endpoint zero does not have a dynamic configuration, so this + * function should not be called for endpoint zero. The \e uFlags parameter + * determines some of the configuration while the other parameters provide the + * rest. + * + * The \b USB_EP_MODE_ flags define what the type is for the given endpoint. + * + * - \b USB_EP_MODE_CTRL is a control endpoint. + * - \b USB_EP_MODE_ISOC is an isochronous endpoint. + * - \b USB_EP_MODE_BULK is a bulk endpoint. + * - \b USB_EP_MODE_INT is an interrupt endpoint. + * + * + * \note This function should only be called in device mode. + * + * \return None. + * + *****************************************************************************/ +void USBDevEndpointConfigSet( uint32 ulBase, + uint16 usEndpoint, + uint32 ulMaxPacketSize, + uint32 uFlags ); + +void USBDevSetDevCfg( uint32 ulBase ); +void USBDevClearDevCfg( uint32 ulBase ); +uint16 USBDevGetEPnStat( uint32 ulBase ); +void USBDevPullEnableDisable( uint32 ulBase, uint32 ulSet ); +void USBIntStatusClear( uint16 uFlag ); +uint16 USBDevGetDevStat( uint32 ulBase ); +void USBDevCfgUnlock( uint32 ulBase ); +void USBDevCfgLock( uint32 ulBase ); + +#endif /*USB_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb_serial_structs.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb_serial_structs.h new file mode 100644 index 00000000000..a0e3ffa2bc3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usb_serial_structs.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file usb_serial_structs.h + * + * @brief Data structures defining this USB CDC device. + * + */ + +#ifndef _USB_SERIAL_STRUCTS_H_ +#define _USB_SERIAL_STRUCTS_H_ + +/****************************************************************************** + * + * The size of the transmit and receive buffers used for the redirected UART. + * This number should be a power of 2 for best performance. 256 is chosen + * pretty much at random though the buffer should be at least twice the size of + * a maxmum-sized USB packet. + * + *****************************************************************************/ +#define UART_BUFFER_SIZE 0x0001 + +/** *************************************************************************** + * + * CDC device callback function prototypes. + * + *****************************************************************************/ +uint32 RxHandler( void * pvCBData, uint32 ulEvent, uint32 ulMsgValue, void * pvMsgData ); +uint32 TxHandler( void * pvCBData, uint32 ulEvent, uint32 ulMsgValue, void * pvMsgData ); +uint32 ControlHandler( void * pvCBData, + uint32 ulEvent, + uint32 ulMsgValue, + void * pvMsgData ); + +extern const tUSBBuffer g_sTxBuffer; +extern const tUSBBuffer g_sRxBuffer; +extern const tUSBDCDCDevice g_sCDCDevice; +extern uint8 g_pucUSBTxBuffer[]; +extern uint8 g_pucUSBRxBuffer[]; + +#endif /* ifndef _USB_SERIAL_STRUCTS_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbcdc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbcdc.h new file mode 100644 index 00000000000..25329e29239 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbcdc.h @@ -0,0 +1,756 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/****************************************************************************** + * + * Note: This header contains definitions related to the USB Communication + * Device Class specification. The header is complete for ACM model + * devices but request and notification definitions specific to other + * modem types, ISDN, ATM and Ethernet are currently incomplete or + * omitted. + * + *****************************************************************************/ + +#ifndef __USBCDC_H__ +#define __USBCDC_H__ + +/****************************************************************************** + * + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + * + *****************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * + * \ingroup cdc_device_class_api + * @{ + * + *****************************************************************************/ + +/****************************************************************************** + * + * Generic macros to read a byte, word or long from a character pointer. + * + *****************************************************************************/ + +/* #define BYTE(pucData) (*(uint8 *)(pucData)) + #define SHORT(pucData) (*(uint16 *)(pucData)) + #define LONG(pucData) (*(uint32 *)(pucData)) */ + +/****************************************************************************** + * + * USB CDC subclass codes. Used in interface descriptor, bInterfaceClass + * + *****************************************************************************/ +#define USB_CDC_SUBCLASS_DIRECT_LINE_MODEL 0x01 +#define USB_CDC_SUBCLASS_ABSTRACT_MODEL 0x02 +#define USB_CDC_SUBCLASS_TELEPHONE_MODEL 0x03 +#define USB_CDC_SUBCLASS_MULTI_CHANNEL_MODEL 0x04 +#define USB_CDC_SUBCLASS_CAPI_MODEL 0x05 +#define USB_CDC_SUBCLASS_ETHERNET_MODEL 0x06 +#define USB_CDC_SUBCLASS_ATM_MODEL 0x07 + +/****************************************************************************** + * + * USB CDC control interface protocols. Used in control interface descriptor, + * bInterfaceProtocol + * + *****************************************************************************/ +#define USB_CDC_PROTOCOL_NONE 0x00 +#define USB_CDC_PROTOCOL_V25TER 0x01 +#define USB_CDC_PROTOCOL_VENDOR 0xFF + +/****************************************************************************** + * + * USB CDC data interface protocols. Used in data interface descriptor, + * bInterfaceProtocol + * + *****************************************************************************/ +/* USB_CDC_PROTOCOL_NONE 0x00 */ +#define USB_CDC_PROTOCOL_I420 0x30 +#define USB_CDC_PROTOCOL_TRANSPARENT 0x32 +#define USB_CDC_PROTOCOL_Q921M 0x50 +#define USB_CDC_PROTOCOL_Q921 0x51 +#define USB_CDC_PROTOCOL_Q921TM 0x52 +#define USB_CDC_PROTOCOL_V42BIS 0x90 +#define USB_CDC_PROTOCOL_Q921EURO 0x91 +#define USB_CDC_PROTOCOL_V120 0x92 +#define USB_CDC_PROTOCOL_CAPI20 0x93 +#define USB_CDC_PROTOCOL_HOST_DRIVER 0xFD +#define USB_CDC_PROTOCOL_CDC_SPEC 0xFE +/* USB_CDC_PROTOCOL_VENDOR 0xFF */ + +/****************************************************************************** + * + * Functional descriptor definitions + * + *****************************************************************************/ + +/****************************************************************************** + * + * Functional descriptor types + * + *****************************************************************************/ +#define USB_CDC_CS_INTERFACE 0x24 +#define USB_CDC_CS_ENDPOINT 0x25 + +/****************************************************************************** + * + * Functional descriptor subtypes + * + *****************************************************************************/ +#define USB_CDC_FD_SUBTYPE_HEADER 0x00 +#define USB_CDC_FD_SUBTYPE_CALL_MGMT 0x01 +#define USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT 0x02 +#define USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT 0x03 +#define USB_CDC_FD_SUBTYPE_TELEPHONE_RINGER 0x04 +#define USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS 0x05 +#define USB_CDC_FD_SUBTYPE_UNION 0x06 +#define USB_CDC_FD_SUBTYPE_COUNTRY 0x07 +#define USB_CDC_FD_SUBTYPE_TELEPHONE_MODES 0x08 +#define USB_CDC_FD_SUBTYPE_USB_TERMINAL 0x09 +#define USB_CDC_FD_SUBTYPE_NETWORK_TERMINAL 0x0A +#define USB_CDC_FD_SUBTYPE_PROTOCOL_UNIT 0x0B +#define USB_CDC_FD_SUBTYPE_EXTENSION_UNIT 0x0C +#define USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT 0x0D +#define USB_CDC_FD_SUBTYPE_CAPI_MGMT 0x0E +#define USB_CDC_FD_SUBTYPE_ETHERNET 0x0F +#define USB_CDC_FD_SUBTYPE_ATM 0x10 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_CALL_MGMT, Header functional descriptor, bmCapabilities + * + *****************************************************************************/ +#define USB_CDC_CALL_MGMT_VIA_DATA 0x02 +#define USB_CDC_CALL_MGMT_HANDLED 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT, Abstract Control Management functional + * descriptor, bmCapabilities + * + *****************************************************************************/ +#define USB_CDC_ACM_SUPPORTS_NETWORK_CONNECTION 0x08 +#define USB_CDC_ACM_SUPPORTS_SEND_BREAK 0x04 +#define USB_CDC_ACM_SUPPORTS_LINE_PARAMS 0x02 +#define USB_CDC_ACM_SUPPORTS_COMM_FEATURE 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT, Direct Line Management functional + * descriptor, bmCapabilities + * + *****************************************************************************/ +#define USB_CDC_DLM_NEEDS_EXTRA_PULSE_SETUP 0x04 +#define USB_CDC_DLM_SUPPORTS_AUX 0x02 +#define USB_CDC_DLM_SUPPORTS_PULSE 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_TELEPHONE_MODES, Telephone Operational Modes functional + * descriptor, bmCapabilities + * + *****************************************************************************/ +#define USB_CDC_TELEPHONE_SUPPORTS_COMPUTER 0x04 +#define USB_CDC_TELEPHONE_SUPPORTS_STANDALONE 0x02 +#define USB_CDC_TELEPHONE_SUPPORTS_SIMPLE 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS, Telephone Call and Line State Reporting + * Capabilities descriptor + * + *****************************************************************************/ +#define USB_CDC_LINE_STATE_CHANGES_NOTIFIED 0x20 +#define USB_CDC_LINE_STATE_REPORTS_DTMF 0x10 +#define USB_CDC_LINE_STATE_REPORTS_DIST_RING 0x08 +#define USB_CDC_LINE_STATE_REPORTS_CALLERID 0x04 +#define USB_CDC_LINE_STATE_REPORTS_BUSY 0x02 +#define USB_CDC_LINE_STATE_REPORTS_INT_DIALTONE 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_USB_TERMINAL, USB Terminal functional descriptor, + * bmOptions + * + *****************************************************************************/ +#define USB_CDC_TERMINAL_NO_WRAPPER_USED 0x00 +#define USB_CDC_TERMINAL_WRAPPER_USED 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT, Multi-Channel Management functional + * descriptor, bmCapabilities + * + *****************************************************************************/ +#define USB_CDC_MCM_SUPPORTS_SET_UNIT_PARAM 0x04 +#define USB_CDC_MCM_SUPPORTS_CLEAR_UNIT_PARAM 0x02 +#define USB_CDC_MCM_UNIT_PARAMS_NON_VOLATILE 0x01 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_CAPI_MGMT, CAPI Control Management functional descriptor, + * bmCapabilities + * + *****************************************************************************/ +#define USB_CDC_CAPI_INTELLIGENT 0x01 +#define USB_CDC_CAPI_SIMPLE 0x00 + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_ETHERNET, Ethernet Networking functional descriptor, + * bmEthernetStatistics + * + *****************************************************************************/ +#define USB_CDC_ENET_XMIT_OK 0x01000000U +#define USB_CDC_ENET_RCV_OK 0x02000000U +#define USB_CDC_ENET_XMIT_ERROR 0x04000000U +#define USB_CDC_ENET_RCV_ERROR 0x08000000U +#define USB_CDC_ENET_RCV_NO_BUFFER 0x10000000U +#define USB_CDC_ENET_DIRECTED_BYTES_XMIT 0x20000000U +#define USB_CDC_ENET_DIRECTED_FRAMES_XMIT 0x40000000U +#define USB_CDC_ENET_MULTICAST_BYTES_XMIT 0x80000000U +#define USB_CDC_ENET_MULTICAST_FRAMES_XMIT 0x00010000U +#define USB_CDC_ENET_BROADCAST_BYTES_XMIT 0x00020000U +#define USB_CDC_ENET_BROADCAST_FRAMES_XMIT 0x00040000U +#define USB_CDC_ENET_DIRECTED_BYTES_RCV 0x00080000U +#define USB_CDC_ENET_DIRECTED_FRAMES_RCV 0x00100000U +#define USB_CDC_ENET_MULTICAST_BYTES_RCV 0x00200000U +#define USB_CDC_ENET_MULTICAST_FRAMES_RCV 0x00400000U +#define USB_CDC_ENET_BROADCAST_BYTES_RCV 0x00800000U +#define USB_CDC_ENET_BROADCAST_FRAMES_RCV 0x00000100U +#define USB_CDC_ENET_RCV_CRC_ERROR 0x00000200U +#define USB_CDC_ENET_TRANSMIT_QUEUE_LENGTH 0x00000400U +#define USB_CDC_ENET_RCV_ERROR_ALIGNMENT 0x00000800U +#define USB_CDC_ENET_XMIT_ONE_COLLISION 0x00001000U +#define USB_CDC_ENET_XMIT_MORE_COLLISIONS 0x00002000U +#define USB_CDC_ENET_XMIT_DEFERRED 0x00004000U +#define USB_CDC_ENET_XMIT_MAX_COLLISIONS 0x00008000U +#define USB_CDC_ENET_RCV_OVERRUN 0x00000001U +#define USB_CDC_ENET_XMIT_UNDERRUN 0x00000002U +#define USB_CDC_ENET_XMIT_HEARTBEAT_FAILURE 0x00000004U +#define USB_CDC_ENET_XMIT_TIMES_CRS_LOST 0x00000008U +#define USB_CDC_ENET_XMIT_LATE_COLLISIONS 0x00000010U + +/****************************************************************************** + * + * USB_CDC_FD_SUBTYPE_ATM, ATM Networking functional descriptor, + * bmDataCapabilities + * + *****************************************************************************/ +#define USB_CDC_ATM_TYPE_3 0x08 +#define USB_CDC_ATM_TYPE_2 0x04 +#define USB_CDC_ATM_TYPE_1 0x02 + +/****************************************************************************** + * + * bmATMDeviceStatistics + * + *****************************************************************************/ +#define USB_CDC_ATM_VC_US_CELLS_SENT 0x10 +#define USB_CDC_ATM_VC_US_CELLS_RECEIVED 0x08 +#define USB_CDC_ATM_DS_CELLS_HEC_ERR_CORRECTED 0x04 +#define USB_CDC_ATM_US_CELLS_SENT 0x02 +#define USB_CDC_ATM_US_CELLS_RECEIVED 0x01 + +/****************************************************************************** + * + * Management Element Requests (provided in tUSBRequest.ucRequest) + * + *****************************************************************************/ +#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00u +#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01u +#define USB_CDC_SET_COMM_FEATURE 0x02u +#define USB_CDC_GET_COMM_FEATURE 0x03u +#define USB_CDC_CLEAR_COMM_FEATURE 0x04u +#define USB_CDC_SET_AUX_LINE_STATE 0x10u +#define USB_CDC_SET_HOOK_STATE 0x11u +#define USB_CDC_PULSE_SETUP 0x12u +#define USB_CDC_SEND_PULSE 0x13u +#define USB_CDC_SET_PULSE_TIME 0x14u +#define USB_CDC_RING_AUX_JACK 0x15u +#define USB_CDC_SET_LINE_CODING 0x20u +#define USB_CDC_GET_LINE_CODING 0x21u +#define USB_CDC_SET_CONTROL_LINE_STATE 0x22u +#define USB_CDC_SEND_BREAK 0x23u +#define USB_CDC_SET_RINGER_PARMS 0x30u +#define USB_CDC_GET_RINGER_PARMS 0x31u +#define USB_CDC_SET_OPERATION_PARMS 0x32u +#define USB_CDC_GET_OPERATION_PARMS 0x33u +#define USB_CDC_SET_LINE_PARMS 0x34u +#define USB_CDC_GET_LINE_PARMS 0x35u +#define USB_CDC_DIAL_DIGITS 0x36u +#define USB_CDC_SET_UNIT_PARAMETER 0x37u +#define USB_CDC_GET_UNIT_PARAMETER 0x38u +#define USB_CDC_CLEAR_UNIT_PARAMETER 0x39u +#define USB_CDC_GET_PROFILE 0x3Au +#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40u +#define USB_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x41u +#define USB_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x42u +#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43u +#define USB_CDC_GET_ETHERNET_STATISTIC 0x44u +#define USB_CDC_SET_ATM_DATA_FORMAT 0x50u +#define USB_CDC_GET_ATM_DEVICE_STATISTICS 0x51u +#define USB_CDC_SET_ATM_DEFAULT_VC 0x52u +#define USB_CDC_GET_ATM_VC_STATISTICS 0x53u + +/****************************************************************************** + * + * In cases where a request defined above results in the return of a fixed size + * data block, the following group of labels define the size of that block. In + * each of these cases, an access macro is also provided to write the response + * data into an appropriately-sized array of uint8acters. + * + *****************************************************************************/ +#define USB_CDC_SIZE_COMM_FEATURE 2 +#define USB_CDC_SIZE_LINE_CODING 7 +#define USB_CDC_SIZE_RINGER_PARMS 4 +#define USB_CDC_SIZE_OPERATION_PARMS 2 +#define USB_CDC_SIZE_UNIT_PARAMETER 2 +#define USB_CDC_SIZE_PROFILE 64 +#define USB_CDC_SIZE_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 2 +#define USB_CDC_SIZE_ETHERNET_STATISTIC 4 +#define USB_CDC_SIZE_ATM_DEVICE_STATISTICS 4 +#define USB_CDC_SIZE_ATM_VC_STATISTICS 4 +#define USB_CDC_SIZE_LINE_PARMS 10 + +/****************************************************************************** + * + * NB: USB_CDC_SIZE_LINE_PARAMS assumes only a single call. For multiple + * calls, add 4 bytes per additional call. + * + *****************************************************************************/ + +/****************************************************************************** + * + * USB_CDC_GET_COMM_FEATURE & USB_CDC_SET_COMM_FEATURE + * + *****************************************************************************/ + +/****************************************************************************** + * + * wValue (Feature Selector) + * + *****************************************************************************/ +#define USB_CDC_ABSTRACT_STATE 0x0001 +#define USB_CDC_COUNTRY_SETTING 0x0002 + +/****************************************************************************** + * + * Data when feature selector is USB_DCD_ABSTRACT_STATE + * + *****************************************************************************/ +#define USB_CDC_ABSTRACT_CALL_DATA_MULTIPLEXED 0x0002 +#define USB_CDC_ABSTRACT_ENDPOINTS_IDLE 0x0001 + +/****************************************************************************** + * + * Macros to populate the response data buffer (whose size in bytes is defined + * by USB_CDC_SIZE_COMM_FEATURE). + * + *****************************************************************************/ + +/* + * Add code for macro SetResponseCommFeature. + */ + +/****************************************************************************** + * + * USB_CDC_SET_AUX_LINE_STATE, wValue + * + *****************************************************************************/ +#define USB_CDC_AUX_DISCONNECT 0x0000 +#define USB_CDC_AUX_CONNECT 0x0001 + +/****************************************************************************** + * + * USB_CDC_SET_HOOK_STATE, wValue + * + *****************************************************************************/ +#define USB_CDC_ON_HOOK 0x0000 +#define USB_CDC_OFF_HOOK 0x0001 +#define USB_CDC_SNOOPING 0x0002 + +/****************************************************************************** + * + * USB_CDC_GET_LINE_CODING + * + *****************************************************************************/ +#define USB_CDC_STOP_BITS_1 0x00 +#define USB_CDC_STOP_BITS_1_5 0x01 +#define USB_CDC_STOP_BITS_2 0x02 + +#define USB_CDC_PARITY_NONE 0x00 +#define USB_CDC_PARITY_ODD 0x01 +#define USB_CDC_PARITY_EVEN 0x02 +#define USB_CDC_PARITY_MARK 0x03 +#define USB_CDC_PARITY_SPACE 0x04 + +/****************************************************************************** + * + * Macro to populate the response data buffer (whose size in bytes is defined + * by USB_CDC_SIZE_LINE_CODING). + * + *****************************************************************************/ + +/* + * Add code for macro SetResponseLineCoding. + */ + +/****************************************************************************** + * + * USB_CDC_SET_CONTROL_LINE_STATE, wValue + * + *****************************************************************************/ +#define USB_CDC_DEACTIVATE_CARRIER 0x00 +#define USB_CDC_ACTIVATE_CARRIER 0x02 +#define USB_CDC_DTE_NOT_PRESENT 0x00 +#define USB_CDC_DTE_PRESENT 0x01 + +/****************************************************************************** + * + * USB_CDC_SET_RINGER_PARMS, USB_CDC_GET_RINGER_PARMS and + * USB_CDC_GET_LINE_PARMS (ulRingerBmp) + * + *****************************************************************************/ +#define USB_CDC_RINGER_EXISTS 0x80000000U +#define USB_CDC_RINGER_DOES_NOT_EXIST 0x00000000 + +/****************************************************************************** + * + * Macro to populate the response data buffer to USB_CDC_GET_RINGER_PARMS. + * Parameter buf points to a buffer of size USB_CDC_SIZE_RINGER_PARMS bytes. + * + *****************************************************************************/ + +/* + * Add code for macro SetResponseRingerParms. + */ + +/****************************************************************************** + * + * Macros to extract fields from the USB_CDC_SET_RINGER_PARMS data + * + *****************************************************************************/ +/* #define GetRingerVolume(pcData) (BYTE((pcData)+1)) */ +/* #define GetRingerPattern(pcData) (BYTE(pcData)) */ +/* #define GetRingerExists(pcData) ((LONG(pcData)) & USB_CDC_RINGER_EXISTS) */ + +/****************************************************************************** + * + * USB_CDC_SET_OPERATION_PARMS, wValue + * + *****************************************************************************/ +#define USB_CDC_SIMPLE_MODE 0x0000 +#define USB_CDC_STANDALONE_MODE 0x0001 +#define USB_CDC_HOST_CENTRIC_MODE 0x0002 + +/****************************************************************************** + * + * Macro to populate the response data buffer to USB_CDC_GET_OPERATION_PARMS. + * Parameter buf points to a buffer of size USB_CDC_SIZE_OPERATION_PARMS + * bytes. + * + *****************************************************************************/ + +/* + * Add code for macro SetResponseOperationParms. + */ + +/****************************************************************************** + * + * USB_CDC_SET_LINE_PARMS, wParam - Line State Change + * + *****************************************************************************/ +#define USB_CDC_DROP_ACTIVE_CALL 0x0000 +#define USB_CDC_START_NEW_CALL 0x0001 +#define USB_CDC_APPLY_RINGING 0x0002 +#define USB_CDC_REMOVE_RINGING 0x0003 +#define USB_CDC_SWITCH_CALL 0x0004 + +/****************************************************************************** + * + * Line state bitmap in USB_CDC_GET_LINE_PARMS response + * + *****************************************************************************/ +#define USB_CDC_LINE_IS_ACTIVE 0x80000000U +#define USB_CDC_LINE_IS_IDLE 0x00000000U +#define USB_CDC_LINE_NO_ACTIVE_CALL 0x000000FFU + +#define USB_CDC_CALL_ACTIVE 0x80000000U + +/****************************************************************************** + * + * Call state value definitions + * + *****************************************************************************/ +#define USB_CDC_CALL_IDLE 0x00000000 +#define USB_CDC_CALL_TYPICAL_DIALTONE 0x00000001 +#define USB_CDC_CALL_INTERRUPTED_DIALTONE 0x00000002 +#define USB_CDC_CALL_DIALING 0x00000003 +#define USB_CDC_CALL_RINGBACK 0x00000004 +#define USB_CDC_CALL_CONNECTED 0x00000005 +#define USB_CDC_CALL_INCOMING 0x00000006 + +/****************************************************************************** + * + * Call state change value definitions + * + *****************************************************************************/ +#define USB_CDC_CALL_STATE_IDLE 0x01 +#define USB_CDC_CALL_STATE_DIALING 0x02 +#define USB_CDC_CALL_STATE_RINGBACK 0x03 +#define USB_CDC_CALL_STATE_CONNECTED 0x04 +#define USB_CDC_CALL_STATE_INCOMING 0x05 + +/****************************************************************************** + * + * Extra byte of data describing the connection type for + * USB_CDC_CALL_STATE_CONNECTED. + * + *****************************************************************************/ +#define USB_CDC_VOICE 0x00 +#define USB_CDC_ANSWERING_MACHINE 0x01 +#define USB_CDC_FAX 0x02 +#define USB_CDC_MODEM 0x03 +#define USB_CDC_UNKNOWN 0xFF + +/****************************************************************************** + * + * Macro to extract call index from request in cases where wParam is + * USB_CDC_SWITCH_CALL. + * + *****************************************************************************/ +/* #define GetCallIndex(pcData) (BYTE(pcData)) */ + +/****************************************************************************** + * + * Macro to populate the CallState entries in response to request + * USB_CDC_GET_LINE_PARMS. The ucIndex parameter is a zero based index + * indicating which call entry in the pcBuf response buffer to fill in. Note + * that pcBuf points to the first byte of the buffer (the wLength field). + * + *****************************************************************************/ + +/* + * Add code for macro SetResponseCallState. + */ + +/****************************************************************************** + * + * Macro to populate the response data buffer (whose size in bytes is defined + * by USB_CDC_SIZE_LINE_PARMS). Note that this macro only populates fields for + * a single call. If multiple calls are being managed, additional 4 byte + * fields must be appended to provide call state for each call after the first. + * This may be done using the SetResponseCallState macro with the appropriate + * call index supplied. + * + *****************************************************************************/ + +/* + * Add code for macro SetResponseLineParms. + */ + +/****************************************************************************** + * + * Notification Element definitions + * + *****************************************************************************/ +#define USB_CDC_NOTIFY_NETWORK_CONNECTION 0x00 +#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE 0x01 +#define USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE 0x08 +#define USB_CDC_NOTIFY_RING_DETECT 0x09 +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 +#define USB_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 +#define USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE 0x2A + +/****************************************************************************** + * + * USB_CDC_NOTIFY_NETWORK_CONNECTION, wValue + * + *****************************************************************************/ +#define USB_CDC_NETWORK_DISCONNECTED 0x0000 +#define USB_CDC_NETWORK_CONNECTED 0x0001 + +/****************************************************************************** + * + * USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE, wValue + * + *****************************************************************************/ +#define USB_CDC_AUX_JACK_ON_HOOK 0x0000 +#define USB_CDC_AUX_JACK_OFF_HOOK 0x0001 + +/****************************************************************************** + * + * USB_CDC_NOTIFY_SERIAL_STATE, Data + * + *****************************************************************************/ + +/****************************************************************************** + * + * Number of bytes of data returned alongside this notification. + * + *****************************************************************************/ +#define USB_CDC_NOTIFY_SERIAL_STATE_SIZE 2u + +#define USB_CDC_SERIAL_STATE_OVERRUN 0x0040U +#define USB_CDC_SERIAL_STATE_PARITY 0x0020U +#define USB_CDC_SERIAL_STATE_FRAMING 0x0010U +#define USB_CDC_SERIAL_STATE_RING_SIGNAL 0x0008U +#define USB_CDC_SERIAL_STATE_BREAK 0x0004U +#define USB_CDC_SERIAL_STATE_TXCARRIER 0x0002U +#define USB_CDC_SERIAL_STATE_RXCARRIER 0x0001U + +/****************************************************************************** + * + * USB_CDC_NOTIFY_CALL_STATE_CHANGE, wValue + * + * Call state values are defined above in the group beginning + * USB_CDC_CALL_STATE_IDLE. Note that the data returned alongside this + * notification are heavily dependent upon the call state being reported so no + * specific lengths or access macros are provided here. + * + * Macro to construct the correct wValue for this notification given a state + * and call index. + * + *****************************************************************************/ + +/* + * Add code for macro SetNotifyCallStatewValue. + */ + +/****************************************************************************** + * + * USB_CDC_NOTIFY_LINE_STATE_CHANGE, wValue + * + * Note that the data returned alongside this notification are heavily + * dependent upon the call state being reported so no specific lengths or + * access macros are provided here. + * + *****************************************************************************/ +#define USB_CDC_LINE_STATE_IDLE 0x0000 +#define USB_CDC_LINE_STATE_HOLD 0x0001 +#define USB_CDC_LINE_STATE_OFF_HOOK 0x0002 +#define USB_CDC_LINE_STATE_ON_HOOK 0x0003 + +/****************************************************************************** + * + * USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE, Data + * + * Macro to populate the 8 byte data structure returned alongside this + * notification. + * + *****************************************************************************/ + +/* + * Add code for macro SetNotifyConnectionSpeedChange. + */ + +/****************************************************************************** + * + * Packed structure definitions for request/response data blocks + * + *****************************************************************************/ + +/****************************************************************************** + * + * All structures defined in this section of the header require byte packing of + * fields. This is usually accomplished using the PACKED macro but, for IAR + * Embedded Workbench, this requires a pragma. + * + *****************************************************************************/ +#if defined( ewarm ) || defined( __IAR_SYSTEMS_ICC__ ) + #pragma pack( 1 ) +#endif + +/** + * @brief USB_CDC_GET/SET_LINE_CODING request-specific data. + */ +typedef struct +{ + /** + * @brief The data terminal rate in bits per second. + */ + uint32 ulRate; + + /** + * @brief The number of stop bits. Valid values are USB_CDC_STOP_BITS_1, + * USB_CDC_STOP_BITS_1_5 or USB_CDC_STOP_BITS_2 + */ + uint8 ucStop; + + /** + * @brief The parity setting. Valid values are USB_CDC_PARITY_NONE, + * USB_CDC_PARITY_ODD, USB_CDC_PARITY_EVEN, USB_CDC_PARITY_MARK + * and USB_CDC_PARITY_SPACE. + */ + uint8 ucParity; + + /** + * @brief The number of data bits per character. Valid values are + * 5, 6, 7 and 8 in this implementation. + */ + uint8 ucDatabits; +} PACKED tLineCoding; + +/****************************************************************************** + * + * Return to default packing when using the IAR Embedded Workbench compiler. + * + *****************************************************************************/ +#if defined( ewarm ) || defined( __IAR_SYSTEMS_ICC__ ) + #pragma pack() +#endif + +/** + * Close the Doxygen group. + * @} + */ + +/****************************************************************************** + * + * Mark the end of the C bindings section for C++ compilers. + * + *****************************************************************************/ +#ifdef __cplusplus +} +#endif + +#endif /* __USBCDC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdcdc.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdcdc.h new file mode 100644 index 00000000000..06342c8d4f7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdcdc.h @@ -0,0 +1,375 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file usbdcdc.h + * + * @brief USBLib support for generic CDC ACM (serial) device. + * + */ + +#ifndef __USBDCDC_H__ +#define __USBDCDC_H__ + +/****************************************************************************** + * + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + * + *****************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** *************************************************************************** + * + * \ingroup cdc_device_class_api + * @{ + * + *****************************************************************************/ + +/****************************************************************************** + * + * PRIVATE + * + * The first few sections of this header are private defines that are used by + * the USB CDC Serial code and are here only to help with the application + * allocating the correct amount of memory for the CDC Serial device code. + * + *****************************************************************************/ + +/****************************************************************************** + * + * PRIVATE + * + * This enumeration holds the various states that the device can be in during + * normal operation. + * + *****************************************************************************/ +typedef enum +{ + /** + * @brief Unconfigured. + */ + CDC_STATE_UNCONFIGURED, + + /** + * @brief No outstanding transaction remains to be completed. + */ + CDC_STATE_IDLE, + + /** + * @brief Waiting on completion of a send or receive transaction. + */ + CDC_STATE_WAIT_DATA, + + /** + * @brief Waiting for client to process data. + */ + CDC_STATE_WAIT_CLIENT +} tCDCState; + +/****************************************************************************** + * + * PRIVATE + * + * This structure defines the private instance data and state variables for the + * CDC Serial device. The memory for this structure is pointed to by the + * psPrivateCDCSerData field in the tUSBDCDCDevice structure passed on + * USBDCDCInit(). + * + *****************************************************************************/ +typedef struct +{ + uint32 ulUSBBase; + tDeviceInfo * psDevInfo; + tConfigDescriptor * psConfDescriptor; + volatile tCDCState eCDCRxState; + volatile tCDCState eCDCTxState; + volatile tCDCState eCDCRequestState; + volatile tCDCState eCDCInterruptState; + volatile uint8 ucPendingRequest; + uint16 usBreakDuration; + uint16 usControlLineState; + uint16 usSerialState; + volatile uint32 usDeferredOpFlags; + uint16 usLastTxSize; + tLineCoding sLineCoding; + volatile tBoolean bRxBlocked; + volatile tBoolean bControlBlocked; + volatile tBoolean bConnected; + uint8 ucControlEndpoint; + uint8 ucBulkINEndpoint; + uint8 ucBulkOUTEndpoint; + uint8 ucInterfaceControl; + uint8 ucInterfaceData; +} tCDCSerInstance; + +#ifndef DEPRECATED + + /** *************************************************************************** + * + * @brief The number of bytes of workspace required by the CDC device class + * driver. The client must provide a block of RAM of at least this + * size in the psPrivateCDCSerData field of the tUSBCDCDevice + * structure passed on USBDCDCInit(). + * + * This value is deprecated and should not be used, any new code + * should just pass in a tUSBCDCDevice structure in the + * psPrivateCDCSerData field. + * + *****************************************************************************/ + #define USB_CDCSER_WORKSPACE_SIZE ( sizeof( tCDCSerInstance ) ) +#endif + +/** *************************************************************************** + * + * The following defines are used when working with composite devices. + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief The size of the memory that should be allocated to create a + * configuration descriptor for a single instance of the USB Serial + * CDC Device. This does not include the configuration descriptor + * which is automatically ignored by the composite device class. + * + * For reference this is sizeof(g_pIADSerDescriptor) + + * sizeof(g_pCDCSerCommInterface) + sizeof(g_pCDCSerDataInterface) + * + *****************************************************************************/ +#define COMPOSITE_DCDC_SIZE ( 8u + 35u + 23u ) + +/** *************************************************************************** + * + * CDC-specific events These events are provided to the application in the + * \e ulMsg parameter of the tUSBCallback function. + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief The host requests that the device send a BREAK condition on its + * serial communication channel. The BREAK should remain active until + * a USBD_CDC_EVENT_CLEAR_BREAK event is received. + */ +#define USBD_CDC_EVENT_SEND_BREAK ( USBD_CDC_EVENT_BASE + 0u ) + +/** *************************************************************************** + * + * @brief The host requests that the device stop sending a BREAK condition on + * its serial communication channel. + */ +#define USBD_CDC_EVENT_CLEAR_BREAK ( USBD_CDC_EVENT_BASE + 1u ) + +/** *************************************************************************** + * + * @brief The host requests that the device set the RS232 signaling lines to + * a particular state. The ulMsgValue parameter contains the RTS and + * DTR control line states as defined in table 51 of the USB CDC class + * definition and is a combination of the following values: + * + * (RTS) USB_CDC_DEACTIVATE_CARRIER or USB_CDC_ACTIVATE_CARRIER + * (DTR) USB_CDC_DTE_NOT_PRESENT or USB_CDC_DTE_PRESENT + */ +#define USBD_CDC_EVENT_SET_CONTROL_LINE_STATE ( USBD_CDC_EVENT_BASE + 2u ) + +/** *************************************************************************** + * + * @brief The host requests that the device set the RS232 communication + * parameters. The pvMsgData parameter points to a tLineCoding + * structure defining the required number of bits per character, + * parity mode, number of stop bits and the baud rate. + */ +#define USBD_CDC_EVENT_SET_LINE_CODING ( USBD_CDC_EVENT_BASE + 3u ) + +/** *************************************************************************** + * + * @brief The host is querying the current RS232 communication parameters. + * The pvMsgData parameter points to a tLineCoding structure that the + * application must fill with the current settings prior to returning + * from the callback. + */ +#define USBD_CDC_EVENT_GET_LINE_CODING ( USBD_CDC_EVENT_BASE + 4u ) + +/** *************************************************************************** + * + * @brief The structure used by the application to define operating + * parameters for the CDC device. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The vendor ID that this device is to present in the device + * descriptor. + */ + uint16 usVID; + + /** + * @brief The product ID that this device is to present in the device + * descriptor. + */ + uint16 usPID; + + /** + * @brief The maximum power consumption of the device, expressed in + * milliamps. + */ + uint16 usMaxPowermA; + + /** + * @brief Indicates whether the device is self- or bus-powered and + * whether or not it supports remote wakeup. Valid values are + * USB_CONF_ATTR_SELF_PWR or USB_CONF_ATTR_BUS_PWR, optionally + * ORed with USB_CONF_ATTR_RWAKE. + */ + uint8 ucPwrAttributes; + + /** + * @brief A pointer to the callback function which will be called to + * notify the application of all asynchronous control events + * related to the operation of the device. + */ + tUSBCallback pfnControlCallback; + + /** + * @brief A client-supplied pointer which will be sent as the first + * parameter in all calls made to the control channel callback, + * pfnControlCallback. + */ + void * pvControlCBData; + + /** + * @brief A pointer to the callback function which will be called to + * notify the application of events related to the device's data + * receive channel. + */ + tUSBCallback pfnRxCallback; + + /** + * @brief A client-supplied pointer which will be sent as the first + * parameter in all calls made to the receive channel callback, + * pfnRxCallback. + */ + void * pvRxCBData; + + /** + * @brief A pointer to the callback function which will be called to + * notify the application of events related to the device's data + * transmit channel. + */ + tUSBCallback pfnTxCallback; + + /** + * @brief A client-supplied pointer which will be sent as the first + * parameter in all calls made to the transmit channel callback, + * pfnTxCallback. + */ + void * pvTxCBData; + + /** + * @brief A pointer to the string descriptor array for this device. This + * array must contain the following string descriptor pointers in + * this order. Language descriptor, Manufacturer name string + * (language 1), Product name string (language 1), Serial number + * Control interface description string (language 1), + * Configuration description string (language 1). + * + * If supporting more than 1 language, the strings for indices + * 1 through 5 must be repeated for each of the other languages + * defined in the language descriptor. + */ + const uint8 * const * ppStringDescriptors; + + /** + * @brief The number of descriptors provided in the ppStringDescriptors + * array. This must be 1 + (5 * number of supported languages). + */ + uint32 ulNumStringDescriptors; + + /** + * @brief A pointer to the private instance data for this device. This + * memory must remain accessible for as long as the CDC device is + * in use and must not be modified by any code outside the CDC + * class driver. + */ + tCDCSerInstance * psPrivateCDCSerData; +} tUSBDCDCDevice; + +extern tDeviceInfo g_sCDCSerDeviceInfo; + +/** *************************************************************************** + * + * API Function Prototypes + * + *****************************************************************************/ +extern void * USBDCDCCompositeInit( uint32 ulIndex, const tUSBDCDCDevice * psCDCDevice ); +extern void * USBDCDCInit( uint32 ulIndex, const tUSBDCDCDevice * psCDCDevice ); +extern void USBDCDCTerm( void * pvInstance ); +extern void * USBDCDCSetControlCBData( tUSBDCDCDevice * pvInstance, void * pvCBData ); +extern void * USBDCDCSetRxCBData( void * pvInstance, void * pvCBData ); +extern void * USBDCDCSetTxCBData( void * pvInstance, void * pvCBData ); +extern uint32 USBDCDCPacketWrite( void * pvInstance, + uint8 * pcData, + uint32 ulLength, + tBoolean bLast ); +extern uint32 USBDCDCPacketRead( void * pvInstance, + uint8 * pcData, + uint32 ulLength, + tBoolean bLast ); +extern uint32 USBDCDCTxPacketAvailable( void * pvInstance ); +extern uint32 USBDCDCRxPacketAvailable( void * pvInstance ); +extern void USBDCDCSerialStateChange( void * pvInstance, uint16 usState ); +extern void USBDCDCPowerStatusSet( void * pvInstance, uint8 ucPower ); +extern tBoolean USBDCDCRemoteWakeupRequest( void * pvInstance ); + +/** *************************************************************************** + * + * Close the Doxygen group. + * @} + * + *****************************************************************************/ + +/****************************************************************************** + * + * Mark the end of the C bindings section for C++ compilers. + * + *****************************************************************************/ +#ifdef __cplusplus +} +#endif + +#endif /* __USBDCDC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdevice.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdevice.h new file mode 100644 index 00000000000..4a220077a2a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdevice.h @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file usbdevice.h + * + * @brief Types and definitions used during USB enumeration. + * + */ + +#ifndef __USBDEVICE_H__ +#define __USBDEVICE_H__ + +/****************************************************************************** + * + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + * + *****************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/** *************************************************************************** + * + * \ingroup device_api + * @{ + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief The maximum number of independent interfaces that any single device + * implementation can support. Independent interfaces means interface + * descriptors with different bInterfaceNumber values - several + * interface descriptors offering different alternative settings but + * the same interface number count as a single interface. + * + *****************************************************************************/ +/*#define USB_MAX_INTERFACES_PER_DEVICE 8u*/ + +/** *************************************************************************** + * + * Close the Doxygen group. + * @} + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief The default USB endpoint FIFO configuration structure. This + * structure contains definitions to set all USB FIFOs into single + * buffered mode with no DMA use. Each endpoint's FIFO is sized to + * hold the largest maximum packet size for any interface alternate + * setting in the current config descriptor. A pointer to this + * structure may be passed in the psFIFOConfig field of the + * tDeviceInfo structure passed to USBCDCInit if the application does + * not require any special handling of the USB controller FIFO. + * + *****************************************************************************/ +extern const tFIFOConfig g_sUSBDefaultFIFOConfig; + +/** *************************************************************************** + * + * Public APIs offered by the USB library device control driver. + * + *****************************************************************************/ +extern void USBDCDInit( uint32 ulIndex, tDeviceInfo * psDevice ); +extern void USBDCDTerm( uint32 ulIndex ); +extern void USBDCDStallEP0( uint32 ulIndex ); +extern void USBDCDRequestDataEP0( uint32 ulIndex, uint8 * pucData, uint32 ulSize ); +extern void USBDCDSendDataEP0( uint32 ulIndex, uint8 * pucData, uint32 ulSize ); +extern void USBDCDSetDefaultConfiguration( uint32 ulIndex, uint32 ulDefaultConfig ); +extern uint32 USBDCDConfigDescGetSize( const tConfigHeader * psConfig ); +extern uint32 USBDCDConfigDescGetNum( const tConfigHeader * psConfig, uint32 ulType ); +extern tDescriptorHeader * USBDCDConfigDescGet( const tConfigHeader * psConfig, + uint32 ulType, + uint32 ulIndex, + uint32 * pulSection ); +extern uint32 USBDCDConfigGetNumAlternateInterfaces( const tConfigHeader * psConfig, + uint8 ucInterfaceNumber ); +extern tInterfaceDescriptor * USBDCDConfigGetInterface( const tConfigHeader * psConfig, + uint32 ulIndex, + uint32 ulAltCfg, + uint32 * pulSection ); +extern tEndpointDescriptor * USBDCDConfigGetInterfaceEndpoint( + const tConfigHeader * psConfig, + uint32 ulInterfaceNumber, + uint32 ulAltCfg, + uint32 ulIndex ); +extern void USBDCDPowerStatusSet( uint32 ulIndex, uint8 ucPower ); +extern tBoolean USBDCDRemoteWakeupRequest( uint32 ulIndex ); + +/** *************************************************************************** + * + * Early releases of the USB library had the following function named + * incorrectly. This macro ensures that any code which used the previous name + * will still operate as expected. + * + *****************************************************************************/ +#ifndef DEPRECATED + #define USBCDCConfigGetInterfaceEndpoint( a, b, c, d ) \ + USBDCDConfigGetInterfaceEndpoint( ( a ), ( b ), ( c ), ( d ) ) +#endif + +/** *************************************************************************** + * + * Mark the end of the C bindings section for C++ compilers. + * + *****************************************************************************/ +#ifdef __cplusplus +} +#endif + +#endif /* __USBENUM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdevicepriv.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdevicepriv.h new file mode 100644 index 00000000000..35dfb91dea1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usbdevicepriv.h @@ -0,0 +1,88 @@ +/****************************************************************************** + * FILE DESCRIPTION + * --------------------------------------------------------------------------- + * File: usbdevicepriv.h + * Component: + * Module: usb + * Generator: - + * + * Description: Private header file used to share internal variables and + * function prototypes between the various device-related + * modules in the USB library. This header MUST NOT be + * used by application code. + * + *****************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __USBDEVICEPRIV_H__ +#define __USBDEVICEPRIV_H__ + +/****************************************************************************** + * + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + * + *****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * + * Device enumeration functions provided by device/usbenum.c and called from + * the interrupt handler in device/usbhandler.c + * + *****************************************************************************/ +extern tBoolean USBDeviceConfig( uint32 ulIndex, + const tConfigHeader * psConfig, + const tFIFOConfig * psFIFOConfig ); +extern tBoolean USBDeviceConfigAlternate( uint32 ulIndex, + const tConfigHeader * psConfig, + uint8 ucInterfaceNum, + uint8 ucAlternateSetting ); +extern void USBDeviceResumeTickHandler( uint32 ulIndex ); + +/****************************************************************************** + * + * Mark the end of the C bindings section for C++ compilers. + * + *****************************************************************************/ +#ifdef __cplusplus +} +#endif + +#endif /* __USBDEVICEPRIV_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usblib.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usblib.h new file mode 100644 index 00000000000..0aa0595ea0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/include/usblib.h @@ -0,0 +1,1875 @@ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file usblib.h + * + * @brief Main header file for the USB Library. + * + */ + +#ifndef __USBLIB_H__ +#define __USBLIB_H__ + +/****************************************************************************** + * + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + * + *****************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/* standard device requests -- USB_SetupDataPacket::bRequest */ +#define USB_REQUEST_GETSTATUS ( 0u ) +#define USB_REQUEST_CLEARFEATURE ( 1u ) +#define USB_REQUEST_SETFEATURE ( 3u ) +#define USB_REQUEST_SETADDRESS ( 5u ) +#define USB_REQUEST_GETDESCRIPTOR ( 6u ) +#define USB_REQUEST_SETDESCRIPTOR ( 7u ) +#define USB_REQUEST_GETCONFIGURATION ( 8u ) +#define USB_REQUEST_SETCONFIGURATION ( 9u ) +#define USB_REQUEST_GETINTERFACE ( 10u ) +#define USB_REQUEST_SETINTERFACE ( 11u ) +#define USB_REQUEST_SYNCHFRAME ( 12u ) + +/** *************************************************************************** + * + * This is the maximum number of endpoints supported by the usblib. + * + *****************************************************************************/ +#define USBLIB_NUM_EP 16u /* Number of supported endpoints. */ + +/****************************************************************************** + * + * The following macro allows compiler-independent syntax to be used to + * define packed structures. A typical structure definition using these + * macros will look similar to the following example: + * + * #ifdef ewarm + * #pragma pack(1) + * #endif + * + * typedef struct _PackedStructName + * { + * uint32 ulFirstField; + * char cCharMember; + * uint16 usShort; + * } + * PACKED tPackedStructName; + * + * #ifdef ewarm + * #pragma pack() + * #endif + * + * The conditional blocks related to ewarm include the #pragma pack() lines + * only if the IAR Embedded Workbench compiler is being used. Unfortunately, + * it is not possible to emit a #pragma from within a macro definition so this + * must be done explicitly. + * + *****************************************************************************/ +#if defined( ccs ) || defined( codered ) || defined( gcc ) || defined( rvmdk ) \ + || defined( __ARMCC_VERSION ) || defined( sourcerygxx ) + #define PACKED __attribute__( ( packed ) ) +#elif defined( ewarm ) || defined( __IAR_SYSTEMS_ICC__ ) + #define PACKED +#elif( __TMS470__ ) + #define PACKED __attribute__( ( packed ) ) +#else /* if defined( ccs ) || defined( codered ) || defined( gcc ) || defined( rvmdk ) \ + || defined( __ARMCC_VERSION ) || defined( sourcerygxx ) */ + #error Unrecognized COMPILER! +#endif /* if defined( ccs ) || defined( codered ) || defined( gcc ) || defined( rvmdk ) \ + || defined( __ARMCC_VERSION ) || defined( sourcerygxx ) */ + +/****************************************************************************** + * + * Assorted language IDs from the document "USB_LANGIDs.pdf" provided by the + * USB Implementers' Forum (Version 1.0). + * + *****************************************************************************/ +#define USB_LANG_CHINESE_PRC 0x0804u /**< Chinese (PRC) */ +#define USB_LANG_CHINESE_TAIWAN 0x0404u /**< Chinese (Taiwan) */ +#define USB_LANG_EN_US 0x0409u /**< English (United States) */ +#define USB_LANG_EN_UK 0x0809u /**< English (United Kingdom) */ +#define USB_LANG_EN_AUS 0x0C09u /**< English (Australia) */ +#define USB_LANG_EN_CA 0x1009u /**< English (Canada) */ +#define USB_LANG_EN_NZ 0x1409u /**< English (New Zealand) */ +#define USB_LANG_FRENCH 0x040Cu /**< French (Standard) */ +#define USB_LANG_GERMAN 0x0407u /**< German (Standard) */ +#define USB_LANG_HINDI 0x0439u /**< Hindi */ +#define USB_LANG_ITALIAN 0x0410u /**< Italian (Standard) */ +#define USB_LANG_JAPANESE 0x0411u /**< Japanese */ +#define USB_LANG_KOREAN 0x0412u /**< Korean */ +#define USB_LANG_ES_TRAD 0x040Au /**< Spanish (Traditional) */ +#define USB_LANG_ES_MODERN 0x0C0Au /**< Spanish (Modern) */ +#define USB_LANG_SWAHILI 0x0441u /**< Swahili (Kenya) */ +#define USB_LANG_URDU_IN 0x0820u /**< Urdu (India) */ +#define USB_LANG_URDU_PK 0x0420u /**< Urdu (Pakistan) */ + +/** *************************************************************************** + * + * @ingroup usbchap9_src + * @{ + * + *****************************************************************************/ + +/****************************************************************************** + * + * Note: + * + * Structure definitions which are derived directly from the USB specification + * use field names from the specification. Since a somewhat different version + * of Hungarian prefix notation is used from the Stellaris standard, beware of + * making assumptions about field sizes based on the field prefix when using + * these structures. Of particular note is the difference in the meaning of + * the 'i' prefix. In USB structures, this indicates a single byte index + * whereas in Stellaris code, this is a 32 bit integer. + * + *****************************************************************************/ + +/****************************************************************************** + * + * All structures defined in this section of the header require byte packing of + * fields. This is usually accomplished using the PACKED macro but, for IAR + * Embedded Workbench, this requires a pragma. + * + *****************************************************************************/ +#if defined( ewarm ) || defined( __IAR_SYSTEMS_ICC__ ) + #pragma pack( 1 ) +#endif + +/****************************************************************************** + * + * Definitions related to standard USB device requests (sections 9.3 & 9.4) + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief The standard USB request header as defined in section 9.3 of the + * USB 2.0 specification. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief Determines the type and direction of the request. + */ + uint8 bmRequestType; + + /** + * @brief Identifies the specific request being made. + */ + uint8 bRequest; + + /** + * @brief Word-sized field that varies according to the request. + */ + uint16 wValue; + + /** + * @brief Word-sized field that varies according to the request; typically used + * to pass an index or offset. + */ + uint16 wIndex; + + /** + * @brief The number of bytes to transfer if there is a data stage to the + * request. + */ + uint16 wLength; +} PACKED tUSBRequest; + +/****************************************************************************** + * + * The following defines are used with the bmRequestType member of tUSBRequest. + * + * Request types have 3 bit fields: + * 4:0 - Is the recipient type. + * 6:5 - Is the request type. + * 7 - Is the direction of the request. + * + *****************************************************************************/ +#define USB_RTYPE_DIR_IN 0x80u +#define USB_RTYPE_DIR_OUT 0x00u + +#define USB_RTYPE_TYPE_M 0x60u +#define USB_RTYPE_VENDOR 0x40u +#define USB_RTYPE_CLASS 0x20u +#define USB_RTYPE_STANDARD 0x00u + +#define USB_RTYPE_RECIPIENT_M 0x1fu +#define USB_RTYPE_OTHER 0x03u +#define USB_RTYPE_ENDPOINT 0x02u +#define USB_RTYPE_INTERFACE 0x01u +#define USB_RTYPE_DEVICE 0x00u + +/****************************************************************************** + * + * Standard USB requests IDs used in the bRequest field of tUSBRequest. + * + *****************************************************************************/ +#define USBREQ_GET_STATUS 0x00u +#define USBREQ_CLEAR_FEATURE 0x01u +#define USBREQ_SET_FEATURE 0x03u +#define USBREQ_SET_ADDRESS 0x05u +#define USBREQ_GET_DESCRIPTOR 0x06u +#define USBREQ_SET_DESCRIPTOR 0x07u +#define USBREQ_GET_CONFIG 0x08u +#define USBREQ_SET_CONFIG 0x09u +#define USBREQ_GET_INTERFACE 0x0au +#define USBREQ_SET_INTERFACE 0x0bu +#define USBREQ_SYNC_FRAME 0x0cu + +#define USBREQ_COUNT ( USBREQ_SYNC_FRAME + 1u ) + +/****************************************************************************** + * + * Data returned from a USBREQ_GET_STATUS request to a device. + * + *****************************************************************************/ +#define USB_STATUS_SELF_PWR 0x0001u /**< Currently self powered. */ +#define USB_STATUS_BUS_PWR 0x0000u /**< Currently bus-powered. */ +#define USB_STATUS_PWR_M 0x0001u /**< Mask for power mode. */ +#define USB_STATUS_REMOTE_WAKE \ + 0x0002u /**< Remote wake-up is currently \ + * enabled. */ + +/****************************************************************************** + * + * Feature Selectors (tUSBRequest.wValue) passed on USBREQ_CLEAR_FEATURE and + * USBREQ_SET_FEATURE. + * + *****************************************************************************/ +#define USB_FEATURE_EP_HALT 0x0000u /**< Endpoint halt feature. */ +#define USB_FEATURE_REMOTE_WAKE 0x0001u /**< Remote wake feature, device only. */ +#define USB_FEATURE_TEST_MODE 0x0002u /**< Test mode */ + +/****************************************************************************** + * + * Endpoint Selectors (tUSBRequest.wIndex) passed on USBREQ_CLEAR_FEATURE, + * USBREQ_SET_FEATURE and USBREQ_GET_STATUS. + * + *****************************************************************************/ +#define USB_REQ_EP_NUM_M 0x007Fu +#define USB_REQ_EP_DIR_M 0x0080u +#define USB_REQ_EP_DIR_IN 0x0080u +#define USB_REQ_EP_DIR_OUT 0x0000u + +/****************************************************************************** + * + * Standard USB descriptor types. These values are passed in the upper bytes + * of tUSBRequest.wValue on USBREQ_GET_DESCRIPTOR and also appear in the + * bDescriptorType field of standard USB descriptors. + * + *****************************************************************************/ +#define USB_DTYPE_DEVICE 1u +#define USB_DTYPE_CONFIGURATION 2u +#define USB_DTYPE_STRING 3u +#define USB_DTYPE_INTERFACE 4u +#define USB_DTYPE_ENDPOINT 5u +#define USB_DTYPE_DEVICE_QUAL 6u +#define USB_DTYPE_OSPEED_CONF 7u +#define USB_DTYPE_INTERFACE_PWR 8u +#define USB_DTYPE_OTG 9u +#define USB_DTYPE_INTERFACE_ASC 11u +#define USB_DTYPE_CS_INTERFACE 36u + +/****************************************************************************** + * + * Definitions related to USB descriptors (sections 9.5 & 9.6) + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief This structure describes a generic descriptor header. These + * fields are to be found at the beginning of all valid USB + * descriptors. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor (including this length byte) expressed + * in bytes. + */ + uint8 bLength; + + /** + * @brief The type identifier of the descriptor whose information follows. + * For standard descriptors, this field could contain, for example, + * USB_DTYPE_DEVICE to identify a device descriptor or + * USB_DTYPE_ENDPOINT to identify an endpoint descriptor. + */ + uint8 bDescriptorType; +} PACKED tDescriptorHeader; + +/** *************************************************************************** + * + * @brief This structure describes the USB device descriptor as defined in USB + * 2.0 specification section 9.6.1. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. All device descriptors + * are 18 bytes long. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For a device descriptor, this will + * be USB_DTYPE_DEVICE (1). + */ + uint8 bDescriptorType; + + /** + * @brief The USB Specification Release Number in BCD format. + * For USB 2.0, this will be 0x0200. + */ + uint16 bcdUSB; + + /** + * @brief The device class code. + */ + uint8 bDeviceClass; + + /** + * @brief The device subclass code. This value qualifies the value + * found in the bDeviceClass field. + */ + uint8 bDeviceSubClass; + + /** + * @brief The device protocol code. This value is qualified by the + * values of bDeviceClass and bDeviceSubClass. + */ + uint8 bDeviceProtocol; + + /** + * @brief The maximum packet size for endpoint zero. Valid values + * are 8, 16, 32 and 64. + */ + uint8 bMaxPacketSize0; + + /** + * @brief The device Vendor ID (VID) as assigned by the USB-IF. + */ + uint16 idVendor; + + /** + * @brief The device Product ID (PID) as assigned by the manufacturer. + */ + uint16 idProduct; + + /** + * @brief The device release number in BCD format. + */ + uint16 bcdDevice; + + /** + * @brief The index of a string descriptor describing the manufacturer. + */ + uint8 iManufacturer; + + /** + * @brief The index of a string descriptor describing the product. + */ + uint8 iProduct; + + /** + * @brief The index of a string descriptor describing the device's serial + * number. + */ + uint8 iSerialNumber; + + /** + * @brief The number of possible configurations offered by the device. + * This field indicates the number of distinct configuration + * descriptors that the device offers. + */ + uint8 bNumConfigurations; +} PACKED tDeviceDescriptor; + +/****************************************************************************** + * + * USB Device Class codes used in the tDeviceDescriptor.bDeviceClass field. + * Definitions for the bDeviceSubClass and bDeviceProtocol fields are device + * specific and can be found in the appropriate device class header files. + * + *****************************************************************************/ +#define USB_CLASS_DEVICE 0x00u +#define USB_CLASS_AUDIO 0x01u +#define USB_CLASS_CDC 0x02u +#define USB_CLASS_HID 0x03u +#define USB_CLASS_PHYSICAL 0x05u +#define USB_CLASS_IMAGE 0x06u +#define USB_CLASS_PRINTER 0x07u +#define USB_CLASS_MASS_STORAGE 0x08u +#define USB_CLASS_HUB 0x09u +#define USB_CLASS_CDC_DATA 0x0au +#define USB_CLASS_SMART_CARD 0x0bu +#define USB_CLASS_SECURITY 0x0du +#define USB_CLASS_VIDEO 0x0eu +#define USB_CLASS_HEALTHCARE 0x0fu +#define USB_CLASS_DIAG_DEVICE 0xdcu +#define USB_CLASS_WIRELESS 0xe0u +#define USB_CLASS_MISC 0xefu +#define USB_CLASS_APP_SPECIFIC 0xfeu +#define USB_CLASS_VEND_SPECIFIC 0xffu +#define USB_CLASS_EVENTS 0xffffffffU + +/****************************************************************************** + * + * Generic values for undefined subclass and protocol. + * + *****************************************************************************/ +#define USB_SUBCLASS_UNDEFINED 0x00u +#define USB_PROTOCOL_UNDEFINED 0x00u + +/****************************************************************************** + * + * The following are the miscellaneous subclass values. + * + *****************************************************************************/ +#define USB_MISC_SUBCLASS_SYNC 0x01u +#define USB_MISC_SUBCLASS_COMMON 0x02u + +/****************************************************************************** + * + * These following are miscellaneous protocol values. + * + *****************************************************************************/ +#define USB_MISC_PROTOCOL_IAD 0x01u + +/** *************************************************************************** + * + * @brief This structure describes the USB device qualifier descriptor as + * defined in the USB 2.0 specification, section 9.6.2. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. All device qualifier + * descriptors are 10 bytes long. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For a device descriptor, this will + * be USB_DTYPE_DEVICE_QUAL (6). + */ + uint8 bDescriptorType; + + /** + * @brief The USB Specification Release Number in BCD format. + * For USB 2.0, this will be 0x0200. + */ + uint16 bcdUSB; + + /** + * @brief The device class code. + */ + uint8 bDeviceClass; + + /** + * @brief The device subclass code. This value qualifies the value + * found in the bDeviceClass field. + */ + uint8 bDeviceSubClass; + + /** + * @brief The device protocol code. This value is qualified by the + * values of bDeviceClass and bDeviceSubClass. + */ + uint8 bDeviceProtocol; + + /** + * @brief The maximum packet size for endpoint zero when operating at + * a speed other than high speed. + */ + uint8 bMaxPacketSize0; + + /** + * @brief The number of other-speed configurations supported. + */ + uint8 bNumConfigurations; + + /** + * @brief Reserved for future use. Must be set to zero. + */ + uint8 bReserved; +} PACKED tDeviceQualifierDescriptor; + +/** *************************************************************************** + * + * This structure describes the USB configuration descriptor as defined in + * USB 2.0 specification section 9.6.3. This structure also applies to the + * USB other speed configuration descriptor defined in section 9.6.4. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. All configuration + * descriptors are 9 bytes long. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For a configuration descriptor, + * this will be USB_DTYPE_CONFIGURATION (2). + */ + uint8 bDescriptorType; + + /** + * @brief The total length of data returned for this configuration. + * This includes the combined length of all descriptors + * (configuration, interface, endpoint and class- or + * vendor-specific) returned for this configuration. + */ + uint16 wTotalLength; + + /** + * @brief The number of interface supported by this configuration. + */ + uint8 bNumInterfaces; + + /** + * @brief The value used as an argument to the SetConfiguration standard + * request to select this configuration. + */ + uint8 bConfigurationValue; + + /** + * @brief The index of a string descriptor describing this configuration. + */ + uint8 iConfiguration; + + /** + * @brief Attributes of this configuration. + */ + uint8 bmAttributes; + + /** + * @brief The maximum power consumption of the USB device from the bus + * in this configuration when the device is fully operational. + * This is expressed in units of 2mA so, for example, + * 100 represents 200mA. + */ + uint8 bMaxPower; +} PACKED tConfigDescriptor; + +/****************************************************************************** + * + * Flags used in constructing the value assigned to the field + * tConfigDescriptor.bmAttributes. Note that bit 7 is reserved and must be set + * to 1. + * + *****************************************************************************/ +#define USB_CONF_ATTR_PWR_M 0xC0u + +#define USB_CONF_ATTR_SELF_PWR 0xC0u +#define USB_CONF_ATTR_BUS_PWR 0x80u +#define USB_CONF_ATTR_RWAKE 0xA0u + +/** *************************************************************************** + * + * This structure describes the USB interface descriptor as defined in USB + * 2.0 specification section 9.6.5. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. All interface + * descriptors are 9 bytes long. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For an interface descriptor, this + * will be USB_DTYPE_INTERFACE (4). + */ + uint8 bDescriptorType; + + /** + * @brief The number of this interface. This is a zero based index into + * the array of concurrent interfaces supported by this + * configuration. + */ + uint8 bInterfaceNumber; + + /** + * @brief The value used to select this alternate setting for the + * interface defined in bInterfaceNumber. + */ + uint8 bAlternateSetting; + + /** + * @brief The number of endpoints used by this interface (excluding + * endpoint zero). + */ + uint8 bNumEndpoints; + + /** + * @brief The interface class code as assigned by the USB-IF. + */ + uint8 bInterfaceClass; + + /** + * @brief The interface subclass code as assigned by the USB-IF. + */ + uint8 bInterfaceSubClass; + + /** + * @brief The interface protocol code as assigned by the USB-IF. + */ + uint8 bInterfaceProtocol; + + /** + * @brief The index of a string descriptor describing this interface. + */ + uint8 iInterface; +} PACKED tInterfaceDescriptor; + +/** *************************************************************************** + * + * This structure describes the USB endpoint descriptor as defined in USB + * 2.0 specification section 9.6.6. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. All endpoint + * descriptors are 7 bytes long. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For an endpoint descriptor, this + * will be USB_DTYPE_ENDPOINT (5). + */ + uint8 bDescriptorType; + + /** + * @brief The address of the endpoint. This field contains the endpoint + * number ORed with flag USB_EP_DESC_OUT or USB_EP_DESC_IN to + * indicate the endpoint direction. + */ + uint8 bEndpointAddress; + + /** + * @brief The endpoint transfer type, USB_EP_ATTR_CONTROL, + * USB_EP_ATTR_ISOC, USB_EP_ATTR_BULK or USB_EP_ATTR_INT and, + * if isochronous, additional flags indicating usage type and + * synchronization method. + */ + uint8 bmAttributes; + + /** + * @brief The maximum packet size this endpoint is capable of sending or + * receiving when this configuration is selected. For high speed + * isochronous or interrupt endpoints, bits 11 and 12 are used to + * pass additional information. + */ + uint16 wMaxPacketSize; + + /** + * @brief The polling interval for data transfers expressed in frames or + * micro frames depending upon the operating speed. + */ + uint8 bInterval; +} PACKED tEndpointDescriptor; + +/****************************************************************************** + * + * Flags used in constructing the value assigned to the field + * tEndpointDescriptor.bEndpointAddress. + * + *****************************************************************************/ +#define USB_EP_DESC_OUT 0x00u +#define USB_EP_DESC_IN 0x80u +#define USB_EP_DESC_NUM_M 0x0fu + +/****************************************************************************** + * + * Mask used to extract the maximum packet size (in bytes) from the + * wMaxPacketSize field of the endpoint descriptor. + * + *****************************************************************************/ +#define USB_EP_MAX_PACKET_COUNT_M 0x07FFu + +/****************************************************************************** + * + * Endpoint attributes used in tEndpointDescriptor.bmAttributes. + * + *****************************************************************************/ +#define USB_EP_ATTR_CONTROL 0x00u +#define USB_EP_ATTR_ISOC 0x01u +#define USB_EP_ATTR_BULK 0x02u +#define USB_EP_ATTR_INT 0x03u +#define USB_EP_ATTR_TYPE_M 0x03u + +#define USB_EP_ATTR_ISOC_M 0x0cu +#define USB_EP_ATTR_ISOC_NOSYNC 0x00u +#define USB_EP_ATTR_ISOC_ASYNC 0x04u +#define USB_EP_ATTR_ISOC_ADAPT 0x08u +#define USB_EP_ATTR_ISOC_SYNC 0x0cu +#define USB_EP_ATTR_USAGE_M 0x30u +#define USB_EP_ATTR_USAGE_DATA 0x00u +#define USB_EP_ATTR_USAGE_FEEDBACK 0x10u +#define USB_EP_ATTR_USAGE_IMPFEEDBACK 0x20u + +/** *************************************************************************** + * + * @brief This structure describes the USB string descriptor for index 0 as + * defined in USB 2.0 specification section 9.6.7. Note that the + * number of language IDs is variable and can be determined by + * examining bLength. The number of language IDs present in the + * descriptor is given by ((bLength - 2) / 2). + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. This value will vary + * depending upon the number of language codes provided in the + * descriptor. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For a string descriptor, this will + * be USB_DTYPE_STRING (3). + */ + uint8 bDescriptorType; + + /** + * @brief The language code (LANGID) for the first supported language. + * Note that this descriptor may support multiple languages, in + * which case, the number of elements in the wLANGID array will + * increase and bLength will be updated accordingly. + */ + uint16 wLANGID[ 1 ]; +} PACKED tString0Descriptor; + +/** *************************************************************************** + * + * @brief This structure describes the USB string descriptor for all string + * indexes other than 0 as defined in USB 2.0 specification + * section 9.6.7. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The length of this descriptor in bytes. This value will be + * 2 greater than the number of bytes comprising the UNICODE + * string that the descriptor contains. + */ + uint8 bLength; + + /** + * @brief The type of the descriptor. For a string descriptor, this will + * be USB_DTYPE_STRING (3). + */ + uint8 bDescriptorType; + + /** + * @brief The first byte of the UNICODE string. This string is not NULL + * terminated. Its length (in bytes) can be computed by + * subtracting 2 from the value in the bLength field. + */ + uint8 bString; +} PACKED tStringDescriptor; + +/** *************************************************************************** + * + * Write a 2 byte uint16 value to a USB descriptor block. + * + * @param usValue is the two byte uint16 that is to be written to + * the descriptor. + * + * This helper macro is used in descriptor definitions to write two-byte + * values. Since the configuration descriptor contains all interface and + * endpoint descriptors in a contiguous block of memory, these descriptors are + * typically defined using an array of bytes rather than as packed structures. + * + * @return Not a function. + * + *****************************************************************************/ +#define USBShort( usValue ) \ + ( uint8_t )( ( uint16_t ) ( usValue ) & ( uint16_t ) 0x00ffU ), \ + ( uint8_t ) ( ( uint16_t ) ( usValue ) >> 8U ) + +/** *************************************************************************** + * + * Write a 3 byte uint32 value to a USB descriptor block. + * + * @param ulValue is the three byte unsigned value that is to be written to the + * descriptor. + * + * This helper macro is used in descriptor definitions to write three-byte + * values. Since the configuration descriptor contains all interface and + * endpoint descriptors in a contiguous block of memory, these descriptors are + * typically defined using an array of bytes rather than as packed structures. + * + * @return Not a function. + * + *****************************************************************************/ +#define USB3Byte( ulValue ) \ + ( ulValue & 0xff ), ( ( ulValue >> 8 ) & 0xff ), ( ( ulValue >> 16 ) & 0xff ) + +/** *************************************************************************** + * + * Write a 4 byte uint32 value to a USB descriptor block. + * + * @param ulValue is the four byte uint32 that is to be written to the + * descriptor. + * + * This helper macro is used in descriptor definitions to write four-byte + * values. Since the configuration descriptor contains all interface and + * endpoint descriptors in a contiguous block of memory, these descriptors are + * typically defined using an array of bytes rather than as packed structures. + * + * @return Not a function. + * + *****************************************************************************/ +#define USBLong( ulValue ) \ + ( ulValue & 0xff ), ( ( ulValue >> 8 ) & 0xff ), ( ( ulValue >> 16 ) & 0xff ), \ + ( ( ulValue >> 24 ) & 0xff ) + +/** *************************************************************************** + * + * Traverse to the next USB descriptor in a block. + * + * @param ptr points to the first byte of a descriptor in a block of + * USB descriptors. + * + * This macro aids in traversing lists of descriptors by returning a pointer + * to the next descriptor in the list given a pointer to the current one. + * + * @return Returns a pointer to the next descriptor in the block following + * @e ptr. + * + *****************************************************************************/ +#define NEXT_USB_DESCRIPTOR( ptr ) \ + ( tDescriptorHeader * ) ( ( ( uint8 * ) ( ptr ) ) + ( ptr )->bLength ) + +/****************************************************************************** + * + * Return to default packing when using the IAR Embedded Workbench compiler. + * + *****************************************************************************/ +#if defined( ewarm ) || defined( __IAR_SYSTEMS_ICC__ ) + #pragma pack() +#endif + +/** *************************************************************************** + * + * Close the usbchap9_src Doxygen group. + * @} + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @ingroup device_api + * @{ + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief Function prototype for any standard USB request. + * + *****************************************************************************/ +typedef void ( *tStdRequest )( void * pvInstance, tUSBRequest * pUSBRequest ); + +/** *************************************************************************** + * + * @brief Data callback for receiving data from an endpoint. + * + *****************************************************************************/ +typedef void ( *tInfoCallback )( void * pvInstance, uint32 ulInfo ); + +/** *************************************************************************** + * + * @brief Callback made to indicate that an interface alternate setting + * change has occurred. + * + *****************************************************************************/ +typedef void ( *tInterfaceCallback )( void * pvInstance, + uint8 ucInterfaceNum, + uint8 ucAlternateSetting ); + +/** *************************************************************************** + * + * @brief Generic interrupt handler callbacks. + * + *****************************************************************************/ +typedef void ( *tUSBIntHandler )( void * pvInstance ); + +/** *************************************************************************** + * + * @brief Interrupt handler callbacks that have status information. + * + *****************************************************************************/ +typedef void ( *tUSBEPIntHandler )( void * pvInstance, uint32 ulStatus ); + +/** *************************************************************************** + * + * @brief Generic handler callbacks that are used when the callers needs to + * call into an instance of class. + * + *****************************************************************************/ +typedef void ( *tUSBDeviceHandler )( void * pvInstance, + uint32 ulRequest, + void * pvRequestData ); + +/** *************************************************************************** + * + * @brief USB event handler functions used during enumeration and operation + * of the device stack. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief This callback is made whenever the USB host requests a + * non-standard descriptor from the device. + */ + tStdRequest pfnGetDescriptor; + + /** + * @brief This callback is made whenever the USB host makes a + * non-standard request. + */ + tStdRequest pfnRequestHandler; + + /** + * @brief This callback is made in response to a SetInterface request + * from the host. + */ + tInterfaceCallback pfnInterfaceChange; + + /** + * @brief This callback is made in response to a SetConfiguration + * request from the host. + */ + tInfoCallback pfnConfigChange; + + /** + * @brief This callback is made when data has been received following + * to a call to USBDCDRequestDataEP0. + */ + tInfoCallback pfnDataReceived; + + /** + * @brief This callback is made when data has been transmitted following + * a call to USBDCDSendDataEP0. + */ + tInfoCallback pfnDataSent; + + /** + * @brief This callback is made when a USB reset is detected. + */ + tUSBIntHandler pfnResetHandler; + + /** + * @brief This callback is made when the bus has been inactive long + * enough to trigger a suspend condition. + */ + tUSBIntHandler pfnSuspendHandler; + + /** + * @brief This is called when resume signaling is detected. + */ + tUSBIntHandler pfnResumeHandler; + + /** + * @brief This callback is made when the device is disconnected from + * the USB bus. + */ + tUSBIntHandler pfnDisconnectHandler; + + /** + * @brief This callback is made to inform the device of activity on + * all endpoints other than endpoint zero. + */ + tUSBEPIntHandler pfnEndpointHandler; + + /** + * @brief This generic handler is provided to allow requests based on + * a given instance to be passed into a device. This is commonly + * used by a top level composite device that is using multiple + * instances of a class. + */ + tUSBDeviceHandler pfnDeviceHandler; +} tCustomHandlers; + +/** *************************************************************************** + * + * @brief This structure defines how a given endpoint's FIFO is configured in + * relation to the maximum packet size for the endpoint as specified + * in the endpoint descriptor. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The multiplier to apply to an endpoint's maximum packet size + * when configuring the FIFO for that endpoint. For example, + * setting this value to 2 will result in a 128 byte FIFO being + * configured if bDoubleBuffer is FALSE and the associated + * endpoint is set to use a 64 byte maximum packet size. + */ + uint8 cMultiplier; + + /** + * @brief This field indicates whether to configure an endpoint's FIFO + * to be double- or single-buffered. If TRUE, a double-buffered + * FIFO is created and the amount of required FIFO storage is + * multiplied by two. + */ + tBoolean bDoubleBuffer; + + /** + * @brief This field defines endpoint mode flags which cannot be deduced + * from the configuration descriptor, namely any in the set + * USB_EP_AUTO_xxx or USB_EP_DMA_MODE_x. USBDCDConfig adds these + * flags to the endpoint mode and direction determined from the + * config descriptor before it configures the endpoint using a + * call to USBDevEndpointConfigSet(). + */ + uint16 usEPFlags; +} tFIFOEntry; + +/** *************************************************************************** + * + * @brief This structure defines endpoint and FIFO configuration information + * for all endpoints that the device wishes to use. This information + * cannot be determined by examining the USB configuration descriptor + * and is provided to USBDCDConfig by the application to allow the USB + * controller endpoints to be correctly configured. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief An array containing one FIFO entry for each of the IN + * endpoints. Note that endpoint 0 is configured and managed by + * the USB device stack so is excluded from this array. The + * index 0 entry of the array corresponds to endpoint 1, + * index 1 to endpoint 2, etc. + */ + tFIFOEntry sIn[ USBLIB_NUM_EP - 1 ]; + + /** + * @brief An array containing one FIFO entry for each of the OUT + * endpoints. Note that endpoint 0 is configured and managed by + * the USB device stack so is excluded from this array. + * The index 0 entry of the array corresponds to endpoint 1, + * index 1 to endpoint 2, etc. + */ + tFIFOEntry sOut[ USBLIB_NUM_EP - 1 ]; +} tFIFOConfig; + +/** *************************************************************************** + * + * @brief This structure defines a contiguous block of data which contains a + * group of descriptors that form part of a configuration descriptor + * for a device. It is assumed that a config section contains only + * whole descriptors. It is not valid to split a single descriptor + * across multiple sections. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The number of bytes of descriptor data pointed to by pucData. + */ + uint8 ucSize; + + /** + * @brief A pointer to a block of data containing an integral number of + * SB descriptors which form part of a larger configuration + * descriptor. + */ + const uint8 * pucData; +} tConfigSection; + +/** *************************************************************************** + * + * @brief This is the top level structure defining a USB device configuration + * descriptor. A configuration descriptor contains a collection of + * device-specific descriptors in addition to the basic config, + * interface and endpoint descriptors. To allow flexibility in + * constructing the configuration, the descriptor is described in + * terms of a list of data blocks. The first block must contain the + * configuration descriptor itself and the following blocks are + * appended to this in order to produce the full descriptor sent to + * the host in response to a GetDescriptor request for the + * configuration descriptor. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The number of sections comprising the full descriptor for this + * configuration. + */ + uint8 ucNumSections; + + /** + * @brief A pointer to an array of ucNumSections section pointers which + * must be concatenated to form the configuration descriptor. + */ + const tConfigSection * const * psSections; +} tConfigHeader; + +/** *************************************************************************** + * + * @brief This structure is passed to the USB library on a call to USBDCDInit + * and provides the library with information about the device that the + * application is implementing. It contains functions pointers for + * the various USB event handlers and pointers to each of the standard + * device descriptors. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief A pointer to a structure containing pointers to event handler + * functions provided by the client to support the operation of + * this device. + */ + tCustomHandlers sCallbacks; + + /** + * @brief A pointer to the device descriptor for this device. + */ + const uint8 * pDeviceDescriptor; + + /** + * @brief A pointer to an array of configuration descriptor pointers. + * Each entry in the array corresponds to one configuration that + * the device may be set to use by the USB host. The number of + * entries in the array must match the bNumConfigurations value + * in the device descriptor array, pDeviceDescriptor. + */ + const tConfigHeader * const * ppConfigDescriptors; + + /** + * @brief A pointer to the string descriptor array for this device. + * This array must be arranged as follows: + * + * - [0] - Standard descriptor containing supported language codes. + * - [1] - String 1 for the first language listed in descriptor 0. + * - [2] - String 2 for the first language listed in descriptor 0. + * - ... + * - [n] - String n for the first language listed in descriptor 0. + * - [n+1] - String 1 for the second language listed in descriptor 0. + * - ... + * - [2n] - String n for the second language listed in descriptor 0. + * - [2n+1]- String 1 for the third language listed in descriptor 0. + * - ... + * - [3n] - String n for the third language listed in descriptor 0. + * + * and so on. + */ + const uint8 * const * ppStringDescriptors; + + /** + * @brief The total number of descriptors provided in the ppStringDescriptors + * array. + */ + uint32 ulNumStringDescriptors; + + /** + * @brief A structure defining how the USB controller FIFO is to be + * partitioned between the various endpoints. This member can be + * set to point to g_sUSBDefaultFIFOConfig if the default FIFO + * configuration is acceptable. This configuration sets each + * endpoint FIFO to be single buffered and sized to hold the + * maximum packet size for the endpoint. + */ + const tFIFOConfig * psFIFOConfig; + + /** + * @brief This value will be passed back to all call back functions so + * that they have access to individual instance data based on the + * this pointer. + */ + void * pvInstance; +} tDeviceInfo; + +/** *************************************************************************** + * + * Close the Doxygen group. + * @} + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @ingroup general_usblib_api + * @{ + * + *****************************************************************************/ + +/****************************************************************************** + * + * USB descriptor parsing functions found in usbdesc.c + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief The USB_DESC_ANY label is used as a wild card in several of the + * descriptor parsing APIs to determine whether or not particular + * search criteria should be ignored. + * + *****************************************************************************/ +#define USB_DESC_ANY 0xFFFFFFFFu + +extern uint32 USBDescGetNum( tDescriptorHeader * psDesc, uint32 ulSize, uint32 ulType ); +extern tDescriptorHeader * USBDescGet( tDescriptorHeader * psDesc, + uint32 ulSize, + uint32 ulType, + uint32 ulIndex ); +extern uint32 USBDescGetNumAlternateInterfaces( tConfigDescriptor * psConfig, + uint8 ucInterfaceNumber ); +extern tInterfaceDescriptor * USBDescGetInterface( tConfigDescriptor * psConfig, + uint32 ulIndex, + uint32 ulAltCfg ); +extern tEndpointDescriptor * USBDescGetInterfaceEndpoint( + tInterfaceDescriptor * psInterface, + uint32 ulIndex, + uint32 ulSize ); + +/** *************************************************************************** + * + * The operating mode required by the USB library client. This type is used + * by applications which wish to be able to switch between host and device + * modes by calling the USBStackModeSet() API. + * + *****************************************************************************/ +typedef enum +{ + /** + * @brief The application wishes to operate as a USB device. + */ + USB_MODE_DEVICE = 0, + + /** + * @brief The application wishes to operate as a USB host. + */ + USB_MODE_HOST, + + /** + * @brief The application wishes to operate as both a host and device + * using On-The-Go protocols to negotiate. + */ + USB_MODE_OTG, + + /** + * @brief A marker indicating that no USB mode has yet been set by the + * application. + */ + USB_MODE_NONE +} tUSBMode; + +/** *************************************************************************** + * + * A pointer to a USB mode callback function. This function is called by the + * USB library to indicate to the application which operating mode it should + * use, host or device. + * + *****************************************************************************/ +typedef void ( *tUSBModeCallback )( uint32 ulIndex, tUSBMode eMode ); + +/** *************************************************************************** + * + * Mode selection and dual mode interrupt steering functions. + * + *****************************************************************************/ +extern void USBStackModeSet( uint32 ulIndex, + tUSBMode eUSBMode, + tUSBModeCallback pfnCallback ); +extern void USBDualModeInit( uint32 ulIndex ); +extern void USBDualModeTerm( uint32 ulIndex ); +extern void USBOTGMain( uint32 ulMsTicks ); +extern void USBOTGPollRate( uint32 ulIndex, uint32 ulPollRate ); +extern void USBOTGModeInit( uint32 ulIndex, + uint32 ulPollRate, + void * pHostData, + uint32 ulHostDataSize ); +extern void USBOTGModeTerm( uint32 ulIndex ); +extern void USB0OTGModeIntHandler( void ); +extern void USB0DualModeIntHandler( void ); + +/** *************************************************************************** + * + * USB callback function. + * + * @param pvCBData is the callback pointer associated with the instance + * generating the callback. This is a value provided by the client during + * initialization of the instance making the callback. + * @param ulEvent is the identifier of the asynchronous event which is being + * notified to the client. + * @param ulMsgParam is an event-specific parameter. + * @param pvMsgData is an event-specific data pointer. + * + * A function pointer provided to the USB layer by the application + * which will be called to notify it of all asynchronous events relating to + * data transmission or reception. This callback is used by device class + * drivers and host pipe functions. + * + * @return Returns an event-dependent value. + * + *****************************************************************************/ +typedef uint32 ( *tUSBCallback )( void * pvCBData, + uint32 ulEvent, + uint32 ulMsgParam, + void * pvMsgData ); + +/** *************************************************************************** + * + * Base identifiers for groups of USB events. These are used by both the + * device class drivers and host layer. + * + * USB_CLASS_EVENT_BASE is the lowest identifier that should be used for + * a class-specific event. Individual event bases are defined for each + * of the supported device class drivers. Events with IDs between + * USB_EVENT_BASE and USB_CLASS_EVENT_BASE are reserved for stack use. + * + *****************************************************************************/ +#define USB_EVENT_BASE 0x0000u +#define USB_CLASS_EVENT_BASE 0x8000u + +/** *************************************************************************** + * + * Event base identifiers for the various device classes supported in host + * and device modes. + * The first 0x800 values of a range are reserved for the device specific + * messages and the second 0x800 values of a range are used for the host + * specific messages for a given class. + * + *****************************************************************************/ +#define USBD_CDC_EVENT_BASE ( USB_CLASS_EVENT_BASE + 0u ) +#define USBD_HID_EVENT_BASE ( USB_CLASS_EVENT_BASE + 0x1000u ) +#define USBD_HID_KEYB_EVENT_BASE ( USBD_HID_EVENT_BASE + 0x100u ) +#define USBD_BULK_EVENT_BASE ( USB_CLASS_EVENT_BASE + 0x2000u ) +#define USBD_MSC_EVENT_BASE ( USB_CLASS_EVENT_BASE + 0x3000u ) +#define USBD_AUDIO_EVENT_BASE ( USB_CLASS_EVENT_BASE + 0x4000u ) + +#define USBH_CDC_EVENT_BASE ( USBD_CDC_EVENT_BASE + 0x800u ) +#define USBH_HID_EVENT_BASE ( USBD_HID_EVENT_BASE + 0x800u ) +#define USBH_BULK_EVENT_BASE ( USBD_BULK_EVENT_BASE + 0x800u ) +#define USBH_MSC_EVENT_BASE ( USBD_MSC_EVENT_BASE + 0x800u ) +#define USBH_AUDIO_EVENT_BASE ( USBD_AUDIO_EVENT_BASE + 0x800u ) + +/** *************************************************************************** + * + * General events supported by device classes and host pipes. + * + *****************************************************************************/ + +/** + * @brief The device is now attached to a USB host and ready to begin sending + * and receiving data (used by device classes only). + */ +#define USB_EVENT_CONNECTED ( USB_EVENT_BASE + 0u ) + +/** + * @brief The device has been disconnected from the USB host (used by device + * classes only). + * + * Note: Due to a hardware erratum in revision A of LM3S3748, this + * event is not posted to self-powered USB devices when they are disconnected + * from the USB host. + */ +#define USB_EVENT_DISCONNECTED ( USB_EVENT_BASE + 1u ) + +/** + * @brief Data has been received and is in the buffer provided. + */ +#define USB_EVENT_RX_AVAILABLE ( USB_EVENT_BASE + 2u ) + +/** + * @brief This event is sent by a lower layer to inquire about the amount of + * unprocessed data buffered in the layers above. It is used in + * cases where a low level driver needs to ensure that all preceding + * data has been processed prior to performing some action or making + * some notification. Clients receiving this event should return the + * number of bytes of data that are unprocessed or 0 if no outstanding + * data remains. + */ +#define USB_EVENT_DATA_REMAINING ( USB_EVENT_BASE + 3u ) + +/** + * @brief This event is sent by a lower layer supporting DMA to request a + * buffer in which the next received packet may be stored. + * The \e ulMsgValue parameter indicates the maximum size of packet + * that can be received in this channel and \e pvMsgData points to + * storage which should be written with the returned buffer pointer. + * The return value from the callback should be the size of the buffer + * allocated (which may be less than the maximum size passed in + * \e ulMsgValue if the client knows that fewer bytes are expected + * to be received) or 0 if no buffer is being returned. + */ +#define USB_EVENT_REQUEST_BUFFER ( USB_EVENT_BASE + 4u ) + +/** + * @brief Data has been sent and acknowledged. If this event is received via + * the USB buffer callback, the \e ulMsgValue parameter indicates the + * number of bytes from the transmit buffer that have been successfully + * transmitted and acknowledged. + */ +#define USB_EVENT_TX_COMPLETE ( USB_EVENT_BASE + 5u ) + +/** + * @brief An error has been reported on the channel or pipe. The + * \e ulMsgValue parameter indicates the source(s) of the error and + * is the logical OR combination of "USBERR_" flags defined below. + */ +#define USB_EVENT_ERROR ( USB_EVENT_BASE + 6u ) + +/** + * @brief The bus has entered suspend state. + */ +#define USB_EVENT_SUSPEND ( USB_EVENT_BASE + 7u ) + +/** + * @brief The bus has left suspend state. + */ +#define USB_EVENT_RESUME ( USB_EVENT_BASE + 8u ) + +/** + * @brief A scheduler event has occurred. + */ +#define USB_EVENT_SCHEDULER ( USB_EVENT_BASE + 9u ) + +/** + * @brief A device or host has detected a stall condition. + */ +#define USB_EVENT_STALL ( USB_EVENT_BASE + 10u ) + +/** + * @brief The host detected a power fault condition. + */ +#define USB_EVENT_POWER_FAULT ( USB_EVENT_BASE + 11u ) + +/** + * @brief The controller has detected a A-Side cable and needs power applied. + * This is only generated on OTG parts if automatic power control is + * disabled. + */ +#define USB_EVENT_POWER_ENABLE ( USB_EVENT_BASE + 12u ) + +/** + * @brief The controller needs power removed, This is only generated on OTG + * parts if automatic power control is disabled. + */ +#define USB_EVENT_POWER_DISABLE ( USB_EVENT_BASE + 13u ) + +/** + * @brief Used with pfnDeviceHandler handler function is classes to indicate + * changes in the interface number by a class outside the class being + * accessed. Typically this is when composite device class is in use. + * + * The \e pvInstance value should point to an instance of the device being + * accessed. + * + * The \e ulRequest should be USB_EVENT_COMP_IFACE_CHANGE. + * + * The \e pvRequestData should point to a two byte array where the first value + * is the old interface number and the second is the new interface number. + */ +#define USB_EVENT_COMP_IFACE_CHANGE ( USB_EVENT_BASE + 14u ) + +/** + * @brief Used with pfnDeviceHandler handler function is classes to indicate + * changes in endpoint number by a class outside the class being + * accessed. Typically this is when composite device class is in use. + * + * The \e pvInstance value should point to an instance of the device being + * accessed. + * + * The \e ulRequest should be USB_EVENT_COMP_EP_CHANGE. + * + * The \e pvRequestData should point to a two byte array where the first value + * is the old endpoint number and the second is the new endpoint number. The + * endpoint numbers should be exactly as USB specification defines them and + * bit 7 set indicates an IN endpoint and bit 7 clear indicates an OUT + * endpoint. + */ +#define USB_EVENT_COMP_EP_CHANGE ( USB_EVENT_BASE + 15u ) + +/** + * @brief Used with pfnDeviceHandler handler function is classes to indicate + * changes in string index number by a class outside the class being + * accessed. Typically this is when composite device class is in use. + * + * The \e pvInstance value should point to an instance of the device being + * accessed. + * + * The \e ulRequest should be USB_EVENT_COMP_STR_CHANGE. + * + * The \e pvRequestData should point to a two byte array where the first value + * is the old string index and the second is the new string index. + */ +#define USB_EVENT_COMP_STR_CHANGE ( USB_EVENT_BASE + 16u ) + +/** + * @brief Used with pfnDeviceHandler handler function is classes to allow the + * device class to make final adjustments to the configuration + * descriptor. This is only used when a device class is used in a + * composite device class is in use. + * + * The \e pvInstance value should point to an instance of the device being + * accessed. + * + * The \e ulRequest should be USB_EVENT_COMP_CONFIG. + * + * The \e pvRequestData should point to the beginning of the configuration + * descriptor for the device instance. + */ +#define USB_EVENT_COMP_CONFIG ( USB_EVENT_BASE + 17u ) + +/** *************************************************************************** + * + * Error sources reported via USB_EVENT_ERROR. + * + *****************************************************************************/ + +/** + * @brief The host received an invalid PID in a transaction. + */ +#define USBERR_HOST_IN_PID_ERROR 0x01000000u + +/** + * @brief The host did not receive a response from a device. + */ +#define USBERR_HOST_IN_NOT_COMP 0x00100000u + +/** + * @brief The host received a stall on an IN endpoint. + */ +#define USBERR_HOST_IN_STALL 0x00400000u + +/** + * @brief The host detected a CRC or bit-stuffing error (isochronous mode). + */ +#define USBERR_HOST_IN_DATA_ERROR 0x00080000u + +/** + * @brief The host received NAK on an IN endpoint for longer than the + * specified timeout period (interrupt, bulk and control modes). + */ +#define USBERR_HOST_IN_NAK_TO 0x00080000u + +/** + * @brief The host failed to communicate with a device via an IN endpoint. + */ +#define USBERR_HOST_IN_ERROR 0x00040000u + +/** + * @brief The host receive FIFO is full. + */ +#define USBERR_HOST_IN_FIFO_FULL 0x00020000u /* RX FIFO full */ + +/** + * @brief The host received NAK on an OUT endpoint for longer than the + * specified timeout period (bulk, interrupt and control modes). + */ +#define USBERR_HOST_OUT_NAK_TO 0x00000080u + +/** + * @brief The host did not receive a response from a device (isochronous mode). + */ +#define USBERR_HOST_OUT_NOT_COMP 0x00000080u + +/** + * @brief The host received a stall on an OUT endpoint. + */ +#define USBERR_HOST_OUT_STALL 0x00000020u + +/** + * @brief The host failed to communicate with a device via an OUT endpoint. + */ +#define USBERR_HOST_OUT_ERROR 0x00000004u + +/** + * @brief The host received NAK on endpoint 0 for longer than the configured + * timeout. + */ +#define USBERR_HOST_EP0_NAK_TO 0x00000080u + +/** + * @brief The host failed to communicate with a device via an endpoint zero. + */ +#define USBERR_HOST_EP0_ERROR 0x00000010u + +/** + * @brief The device detected a CRC error in received data. + */ +#define USBERR_DEV_RX_DATA_ERROR 0x00080000u + +/** + * @brief The device was unable to receive a packet from the host since the + * receive FIFO is full. + */ +#define USBERR_DEV_RX_OVERRUN 0x00040000u + +/** + * @brief The device receive FIFO is full. + */ +#define USBERR_DEV_RX_FIFO_FULL 0x00020000u /* RX FIFO full */ + +/** *************************************************************************** + * + * Close the general_usblib_api Doxygen group. + * @} + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @ingroup usblib_buffer_api + * @{ + * + *****************************************************************************/ + +/** *************************************************************************** + * + * @brief A function pointer type which describes either a class driver + * packet read or packet write function (both have the same prototype) + * to the USB buffer object. + * + *****************************************************************************/ +typedef uint32 ( *tUSBPacketTransfer )( void * pvHandle, + uint8 * pcData, + uint32 ulLength, + tBoolean bLast ); + +/** *************************************************************************** + * + * @brief A function pointer type which describes either a class driver + * transmit or receive packet available function (both have the same + * prototype) to the USB buffer object. + * + *****************************************************************************/ +typedef uint32 ( *tUSBPacketAvailable )( void * pvHandle ); + +/** *************************************************************************** + * + * @brief The number of bytes of workspace that each USB buffer object + * requires. This workspace memory is provided to the buffer on + * USBBufferInit() in the \e pvWorkspace field of the \e tUSBBuffer + * structure. + * + *****************************************************************************/ +#define USB_BUFFER_WORKSPACE_SIZE 16 + +/** *************************************************************************** + * + * @brief The structure used by the application to initialize a buffer object + * that will provide buffered access to either a transmit or receive + * channel. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief This field sets the mode of the buffer. If TRUE, the buffer + * operates as a transmit buffer and supports calls to + * USBBufferWrite by the client. If FALSE, the buffer operates + * as a receive buffer and supports calls to USBBufferRead. + */ + tBoolean bTransmitBuffer; + + /** + * @brief A pointer to the callback function which will be called to + * notify the application of all asynchronous events related to + * the operation of the buffer. + */ + tUSBCallback pfnCBack; + + /** + * @brief A pointer that the buffer will pass back to the client in the + * first parameter of all callbacks related to this instance. + */ + void * pvCBData; + + /** + * @brief The function which should be called to transmit a packet of + * data in transmit mode or receive a packet in receive mode. + */ + tUSBPacketTransfer pfnTransfer; + + /** + * @brief The function which should be called to determine if the + * endpoint is ready to accept a new packet for transmission in + * transmit mode or to determine the size of the buffer required + * to read a packet in receive mode. + */ + tUSBPacketAvailable pfnAvailable; + + /** + * @brief The handle to pass to the low level function pointers provided + * in the pfnTransfer and pfnAvailable members. For USB device + * use, this is the psDevice parameter required by the relevant + * device class driver APIs. For USB host use, this is the pipe + * identifier returned by USBHCDPipeAlloc. + */ + void * pvHandle; + + /** + * @brief A pointer to memory to be used as the ring buffer for this + * instance. + */ + uint8 * pcBuffer; + + /** + * @brief The size, in bytes, of the buffer pointed to by pcBuffer. + */ + uint32 ulBufferSize; + + /** + * @brief A pointer to USB_BUFFER_WORKSPACE_SIZE bytes of RAM that the + * buffer object can use for workspace. + */ + void * pvWorkspace; +} tUSBBuffer; + +/** *************************************************************************** + * + * @brief The structure used for encapsulating all the items associated with + * a ring buffer. + * + *****************************************************************************/ +typedef struct +{ + /** + * @brief The ring buffer size. + */ + uint32 ulSize; + + /** + * @brief The ring buffer write index. + */ + volatile uint32 ulWriteIndex; + + /** + * @brief The ring buffer read index. + */ + volatile uint32 ulReadIndex; + + /** + * @brief The ring buffer. + */ + uint8 * pucBuf; +} tUSBRingBufObject; + +/** *************************************************************************** + * + * USB buffer API function prototypes. + * + *****************************************************************************/ +extern const tUSBBuffer * USBBufferInit( const tUSBBuffer * psBuffer ); +extern void USBBufferInfoGet( const tUSBBuffer * psBuffer, + tUSBRingBufObject * psRingBuf ); +extern void * USBBufferCallbackDataSet( tUSBBuffer * psBuffer, void * pvCBData ); +extern uint32 USBBufferWrite( const tUSBBuffer * psBuffer, + const uint8 * pucData, + uint32 ulLength ); +extern void USBBufferDataWritten( const tUSBBuffer * psBuffer, uint32 ulLength ); +extern void USBBufferDataRemoved( const tUSBBuffer * psBuffer, uint32 ulLength ); +extern void USBBufferFlush( const tUSBBuffer * psBuffer ); +extern uint32 USBBufferRead( const tUSBBuffer * psBuffer, + uint8 * pucData, + uint32 ulLength ); +extern uint32 USBBufferDataAvailable( const tUSBBuffer * psBuffer ); +extern uint32 USBBufferSpaceAvailable( const tUSBBuffer * psBuffer ); +extern uint32 USBBufferEventCallback( void * pvCBData, + uint32 ulEvent, + uint32 ulMsgValue, + void * pvMsgData ); +extern tBoolean USBRingBufFull( tUSBRingBufObject * ptUSBRingBuf ); +extern tBoolean USBRingBufEmpty( tUSBRingBufObject * ptUSBRingBuf ); +extern void USBRingBufFlush( tUSBRingBufObject * ptUSBRingBuf ); +extern uint32 USBRingBufUsed( tUSBRingBufObject * ptUSBRingBuf ); +extern uint32 USBRingBufFree( tUSBRingBufObject * ptUSBRingBuf ); +extern uint32 USBRingBufContigUsed( tUSBRingBufObject * ptUSBRingBuf ); +extern uint32 USBRingBufContigFree( tUSBRingBufObject * ptUSBRingBuf ); +extern uint32 USBRingBufSize( tUSBRingBufObject * ptUSBRingBuf ); +extern uint8 USBRingBufReadOne( tUSBRingBufObject * ptUSBRingBuf ); +extern void USBRingBufRead( tUSBRingBufObject * ptUSBRingBuf, + uint8 * pucData, + uint32 ulLength ); +extern void USBRingBufWriteOne( tUSBRingBufObject * ptUSBRingBuf, uint8 ucData ); +extern void USBRingBufWrite( tUSBRingBufObject * ptUSBRingBuf, + const uint8 pucData[], + uint32 ulLength ); +extern void USBRingBufAdvanceWrite( tUSBRingBufObject * ptUSBRingBuf, uint32 ulNumBytes ); +extern void USBRingBufAdvanceRead( tUSBRingBufObject * ptUSBRingBuf, uint32 ulNumBytes ); +extern void USBRingBufInit( tUSBRingBufObject * ptUSBRingBuf, + uint8 * pucBuf, + uint32 ulSize ); + +/** *************************************************************************** + * + * Close the Doxygen group. + * @} + * + *****************************************************************************/ + +/****************************************************************************** + * + * Mark the end of the C bindings section for C++ compilers. + * + *****************************************************************************/ +#ifdef __cplusplus +} +#endif + +#endif /* __USBLIB_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/adc.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/adc.c new file mode 100644 index 00000000000..10dcc0adf98 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/adc.c @@ -0,0 +1,1039 @@ +/** @file adc.c + * @brief ADC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "adc.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void adcInit(void) + * @brief Initializes ADC Driver + * + * This function initializes the ADC driver. + * + */ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ADC_SourceId_001 */ +/* DesignId : ADC_DesignId_001 */ +/* Requirements : HL_SR185 */ +void adcInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b Initialize @b ADC1: */ + + /** - Reset ADC module */ + adcREG1->RSTCR = 1U; + adcREG1->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG1->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG1->CLOCKCR = 10U; + + /** - Setup memory boundaries */ + adcREG1->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG1->BNDEND = ( adcREG1->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup event group sample window */ + adcREG1->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 1 sample window */ + adcREG1->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 2 sample window */ + adcREG1->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC1 EVT pin output value */ + adcREG1->EVTOUT = 0U; + + /** - ADC1 EVT pin direction */ + adcREG1->EVTDIR = 0U; + + /** - ADC1 EVT pin open drain enable */ + adcREG1->EVTPDR = 0U; + + /** - ADC1 EVT pin pullup / pulldown selection */ + adcREG1->EVTPSEL = 1U; + + /** - ADC1 EVT pin pullup / pulldown enable*/ + adcREG1->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG1->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG1->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG1->PARCR = 0x00000005U; + + /** @b Initialize @b ADC2: */ + + /** - Reset ADC module */ + adcREG2->RSTCR = 1U; + adcREG2->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG2->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG2->CLOCKCR = 10U; + + /** - Setup memory boundaries */ + adcREG2->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG2->BNDEND = ( adcREG2->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup event group sample window */ + adcREG2->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 1 sample window */ + adcREG2->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 2 sample window */ + adcREG2->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC2 EVT pin output value */ + adcREG2->EVTOUT = 0U; + + /** - ADC2 EVT pin direction */ + adcREG2->EVTDIR = 0U; + + /** - ADC2 EVT pin open drain enable */ + adcREG2->EVTPDR = 0U; + + /** - ADC2 EVT pin pullup / pulldown selection */ + adcREG2->EVTPSEL = 1U; + + /** - ADC2 EVT pin pullup / pulldown enable*/ + adcREG2->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG2->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG2->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG2->PARCR = 0x00000005U; + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** - s_adcSelect is used as constant table for channel selection */ +static const uint32 s_adcSelect[ 2U ][ 3U ] = { + { 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U }, + { 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U } +}; + +/** - s_adcFiFoSize is used as constant table for channel selection */ +static const uint32 s_adcFiFoSize[ 2U ][ 3U ] = { { 16U, 16U, 16U }, { 16U, 16U, 16U } }; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) + * @brief Starts an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function starts a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_002 */ +/* DesignId : ADC_DesignId_002 */ +/* Requirements : HL_SR186 */ +void adcStartConversion( adcBASE_t * adc, uint32 group ) +{ + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Setup FiFo size */ + adc->GxINTCR[ group ] = s_adcFiFoSize[ index ][ group ]; + + /** - Start Conversion */ + adc->GxSEL[ group ] = s_adcSelect[ index ][ group ]; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) + * @brief Stops an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function stops a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_003 */ +/* DesignId : ADC_DesignId_003 */ +/* Requirements : HL_SR187 */ +void adcStopConversion( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Stop Conversion */ + adc->GxSEL[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) + * @brief Resets FiFo read and write pointer. + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function resets the FiFo read and write pointers. + * + */ +/* SourceId : ADC_SourceId_004 */ +/* DesignId : ADC_DesignId_004*/ +/* Requirements : HL_SR188 */ +void adcResetFiFo( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Reset FiFo */ + adc->GxFIFORESETCR[ group ] = 1U; + + /** @note The function adcInit has to be called before this function can be used.\n + * the conversion should be stopped before calling this function. + */ + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) + * @brief Gets converted a ADC values + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @param[out] data Pointer to store ADC converted data + * @return The function will return the number of converted values copied into data + * buffer: + * + * This function writes a ADC message into a ADC message box. + * + */ +/* SourceId : ADC_SourceId_005 */ +/* DesignId : ADC_DesignId_005 */ +/* Requirements : HL_SR189 */ +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ) +{ + uint32 i; + uint32 buf; + uint32 mode; + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + uint32 intcr_reg = adc->GxINTCR[ group ]; + uint32 count = ( intcr_reg >= 256U ) ? s_adcFiFoSize[ index ][ group ] + : ( s_adcFiFoSize[ index ][ group ] + - ( uint32 ) ( intcr_reg & 0xFFU ) ); + adcData_t * ptr = data; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mode = ( adc->OPMODECR & ADC_12_BIT_MODE ); + + if( mode == ADC_12_BIT_MODE ) + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0xFFFU ); + ptr->id = ( uint32 ) ( ( buf >> 16U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + else + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0x3FFU ); + ptr->id = ( uint32 ) ( ( buf >> 10U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + + adc->GxINTFLG[ group ] = 9U; + + /** @note The function adcInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return count; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) + * @brief Checks if FiFo buffer is full + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When FiFo buffer is not full + * - 1: When FiFo buffer is full + * - 3: When FiFo buffer overflow occurred + * + * This function checks FiFo buffer status. + * + */ +/* SourceId : ADC_SourceId_006 */ +/* DesignId : ADC_DesignId_006 */ +/* Requirements : HL_SR190 */ +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read FiFo flags */ + flags = adc->GxINTFLG[ group ] & 3U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) + * @brief Checks if Conversion is complete + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When is not finished + * - 8: When conversion is complete + * + * This function checks if conversion is complete. + * + */ +/* SourceId : ADC_SourceId_007 */ +/* DesignId : ADC_DesignId_007 */ +/* Requirements : HL_SR191 */ +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Read conversion flags */ + flags = adc->GxINTFLG[ group ] & 8U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn void adcCalibration(adcBASE_t *adc) + * @brief Computes offset error using Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * This function computes offset error using Calibration mode + * + */ +/* SourceId : ADC_SourceId_008 */ +/* DesignId : ADC_DesignId_010 */ +/* Requirements : HL_SR194 */ +void adcCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + uint32 conv_val[ 5U ] = { 0U, 0U, 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 4U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + case 2U: /* Test 1 : Bride En = 1 , HiLo =0 */ + adc->CALCR = 0x0200U; + break; + + case 3U: /* Test 1 : Bride En = 1 , HiLo =1 */ + adc->CALCR = 0x0300U; + break; + + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 4U ] = conv_val[ 0U ] + conv_val[ 1U ] + conv_val[ 2U ] + conv_val[ 3U ]; + + conv_val[ 4U ] = ( conv_val[ 4U ] / 4U ); + + offset_error = conv_val[ 4U ] - 0x7FFU; + + /*Write the offset error to the Calibration register */ + /* Load 2;s complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error & 0xFFFU; + offset_error = offset_error + 1U; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + /** @note The function adcInit has to be called before using this function. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/** @fn void adcMidPointCalibration(adcBASE_t *adc) + * @brief Computes offset error using Mid Point Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @return This function will return offset error using Mid Point Calibration mode + * + * This function computes offset error using Mid Point Calibration mode + * + */ +/* SourceId : ADC_SourceId_009 */ +/* DesignId : ADC_DesignId_011 */ +/* Requirements : HL_SR195 */ +uint32 adcMidPointCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + uint32 conv_val[ 3U ] = { 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 2U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 2U ] = ( conv_val[ 0U ] ) + ( conv_val[ 1U ] ); + + conv_val[ 2U ] = ( conv_val[ 2U ] / 2U ); + + offset_error = conv_val[ 2U ] - 0x7FFU; + + /* Write the offset error to the Calibration register */ + /* Load 2's complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error + 1U; + offset_error = offset_error & 0xFFFU; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + return ( offset_error ); + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) + * @brief Enable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will enable the notification of a conversion. + * In single conversion mode for conversion complete and + * in continuous conversion mode when the FiFo buffer is full. + * + */ +/* SourceId : ADC_SourceId_010 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : HL_SR192 */ +void adcEnableNotification( adcBASE_t * adc, uint32 group ) +{ + uint32 notif = ( ( ( uint32 ) ( adc->GxMODECR[ group ] ) & 2U ) == 2U ) ? 1U : 8U; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = notif; + + /** @note The function adcInit has to be called before this function can be used.\n + * This function should be called before the conversion is started + */ + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + +/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) + * @brief Disable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will disable the notification of a conversion. + */ +/* SourceId : ADC_SourceId_011 */ +/* DesignId : ADC_DesignId_009 */ +/* Requirements : HL_SR193 */ +void adcDisableNotification( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} + +/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @param[in] value Value to be set: 0 or 1 + * + * This function will set the ADC EVT pin if configured as an output pin. + */ +/* SourceId : ADC_SourceId_020 */ +/* DesignId : ADC_DesignId_014 */ +/* Requirements : HL_SR529 */ +void adcSetEVTPin( adcBASE_t * adc, uint32 value ) +{ + adc->EVTOUT = value; +} + +/** @fn uint32 adcGetEVTPin(adcBASE_t *adc) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @return Value of the ADC EVT pin: 0 or 1 + * + * This function will return the value of ADC EVT pin. + */ +/* SourceId : ADC_SourceId_021 */ +/* DesignId : ADC_DesignId_015 */ +/* Requirements : HL_SR529 */ +uint32 adcGetEVTPin( adcBASE_t * adc ) +{ + return adc->EVTIN; +} + +/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_012 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : HL_SR203 */ +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC1_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC1_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC1_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; + } + else + { + config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG1->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG1->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG1->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG1->EVSRC; + config_reg->CONFIG_G1SRC = adcREG1->G1SRC; + config_reg->CONFIG_G2SRC = adcREG1->G2SRC; + config_reg->CONFIG_BNDCR = adcREG1->BNDCR; + config_reg->CONFIG_BNDEND = adcREG1->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG1->PARCR; + } +} + +/** @fn void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_013 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : HL_SR203 */ +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC2_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC2_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC2_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC2_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC2_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC2_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC2_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC2_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC2_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC2_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC2_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC2_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC2_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC2_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC2_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC2_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC2_PARCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_OPMODECR = adcREG2->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG2->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG2->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG2->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG2->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG2->EVSRC; + config_reg->CONFIG_G1SRC = adcREG2->G1SRC; + config_reg->CONFIG_G2SRC = adcREG2->G2SRC; + config_reg->CONFIG_BNDCR = adcREG2->BNDCR; + config_reg->CONFIG_BNDEND = adcREG2->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG2->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG2->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG2->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG2->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG2->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG2->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG2->PARCR; + } +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/can.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/can.c new file mode 100644 index 00000000000..1fe1400766c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/can.c @@ -0,0 +1,1519 @@ +/** @file can.c + * @brief CAN Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "can.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Global and Static Variables */ + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) +#else +static const uint32 s_canByteOrder[ 8U ] = { 3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U }; +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void canInit(void) + * @brief Initializes CAN Driver + * + * This function initializes the CAN driver. + * + */ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +/* SourceId : CAN_SourceId_001 */ +/* DesignId : CAN_DesignId_001 */ +/* Requirements : HL_SR207 */ +void canInit( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG1->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG1->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG1->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG1->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG1->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + canREG1->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + canREG1->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG1->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 4U + 3U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 6U ) | ( uint32 ) 19U; + + /** - CAN1 Port output values */ + canREG1->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 1U ); + + canREG1->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG1->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN2: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG2->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG2->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG2->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG2->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG2->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + canREG2->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + canREG2->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG2->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 4U + 3U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 6U ) | ( uint32 ) 19U; + + /** - CAN2 Port output values */ + canREG2->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 1U ); + + canREG2->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG2->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN3: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG3->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG3->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG3->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG3->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG3->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + canREG3->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + canREG3->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG3->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 4U + 3U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 3U - 1U ) << 6U ) + | ( uint32 ) ( uint32 ) 19U; + + /** - CAN3 Port output values */ + canREG3->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 1U ); + + canREG3->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG3->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data) + * @brief Transmits a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of the TX message box wasn't successful + * - 1: When the setup of the TX message box was successful + * + * This function writes a CAN message into a CAN message box. + * This function is not reentrant. However, if a CAN interrupt occurs, the values of + * the IF registers are backup up and restored at the end of the ISR, since these are a + *shared resource. + * + */ +/* SourceId : CAN_SourceId_002 */ +/* DesignId : CAN_DesignId_002 */ +/* Requirements : HL_SR208 */ +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + * - Start Transmission + */ + node->IF1CMD = 0x87U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return success; +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/** @fn uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return: + * - 0: When RX message box hasn't received new data + * - 1: When RX data are stored in the data buffer + * - 3: When RX data are stored in the data buffer and a message was lost + * + * This function writes a CAN message into a CAN message box. + * + */ +/* SourceId : CAN_SourceId_003 */ +/* DesignId : CAN_DesignId_003 */ +/* Requirements : HL_SR209 */ +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ) +{ + uint32 i; + uint32 size; + uint8 * pData = data; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Check if new data have been arrived: + * - no new data, return 0 + * - new data, get received message + */ + if( ( node->NWDATx[ regIndex ] & bitIndex ) == 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF2 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x17U; + + /** - Copy data into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Get number of received bytes + * - Value from 0x8 to 0xF equals length 8. + */ + size = node->IF2MCTL & 0xFU; + + if( size > 0x8U ) + { + size = 0x8U; + } + + /** - Copy RX data into destination buffer */ + for( i = 0U; i < size; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ s_canByteOrder[ i ] ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData++; +#endif /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + } + + success = 1U; + } + + /** - Check if data have been lost: + * - no data lost, return 1 + * - data lost, return 3 + */ + if( ( node->IF2MCTL & 0x4000U ) == 0x4000U ) + { + success = 3U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetID(canBASE_t *node, uint32 messageBox) + * @brief Gets the Message Box's ID + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return the ID of the message box. + * + * This function gets the identifier of a CAN message box. + * + */ +/* SourceId : CAN_SourceId_026 */ +/* DesignId : CAN_DesignId_020 */ +/* Requirements : HL_SR537 */ +uint32 canGetID( canBASE_t * node, uint32 messageBox ) +{ + uint32 msgBoxID = 0U; + + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x20U; + + /** - Copy message box number into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /* Read Message Box ID from Arbitration register. */ + msgBoxID = ( node->IF2ARB & 0x1FFFFFFFU ); + + return msgBoxID; +} + +/** @fn uint32 canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal) + * @brief Change CAN Message Box ID. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] msgBoxArbitVal (32 bit value): + * Bit 31 - Not used. + * Bit 30 - 0 - The 11-bit ("standard") identifier is used for this message + *object. 1 - The 29-bit ("extended") identifier is used for this message object. Bit 29 - + *0 - Direction = Receive 1 - Direction = Transmit Bit 28:0 - Message Identifier. + * @return + * + * + * This function changes the Identifier and other arbitration parameters of a CAN + *Message Box. + * + */ +/* SourceId : CAN_SourceId_027 */ +/* DesignId : CAN_DesignId_021 */ +/* Requirements : HL_SR538 */ +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ) +{ + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0xA0U; + /* Copy passed value into the arbitration register. */ + node->IF2ARB &= 0x80000000U; + node->IF2ARB |= ( msgBoxArbitVal & 0x7FFFFFFFU ); + + /** - Update message box number. */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/** @fn uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox) + * @brief Transmits a CAN Remote Frame. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of Send Remote Frame from message box wasn't successful + * - 1: When the setup of Send Remote Frame from message box was successful + * + * This function triggers Remote Frame Transmission from CAN message box. + * Note : Enable RTR must be set in the Message x Configuration in the GUI( x: 1 - 64) + * + */ +/* SourceId : CAN_SourceId_028 */ +/* DesignId : CAN_DesignId_022 */ +/* Requirements : HL_SR531 */ +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ) +{ + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Request Transmission by setting TxRqst in message box */ + node->IF1CMD = ( uint8 ) 0x84U; + + /** - Trigger Remote Frame Transmit from message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + return success; +} + +/** @fn uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * + * data) + * @brief Fills the Message Object with the data but does not initiate transmission. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return: + * - 0: When the Fill up of the TX message box wasn't successful + * - 1: When the Fill up of the TX message box was successful + * + * This function fills the Message Object with the data but does not initiate + * transmission. + * + */ +/* SourceId : CAN_SourceId_029 */ +/* DesignId : CAN_DesignId_023 */ +/* Requirements : HL_SR532 */ +uint32 canFillMessageObjectData( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + */ + node->IF1CMD = 0x83U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif /* if ( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) */ + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + + return success; +} + +/** @fn uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox) + * @brief Gets Tx message box transmission status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the tx request flag + * + * Checks to see if the Tx message box has a pending Tx request, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ +/* SourceId : CAN_SourceId_004 */ +/* DesignId : CAN_DesignId_004 */ +/* Requirements : HL_SR210 */ +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->TXRQx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return flag; +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/** @fn uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox) + * @brief Gets Rx message box reception status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the Rx message box has pending Rx data, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ +/* SourceId : CAN_SourceId_005 */ +/* DesignId : CAN_DesignId_005 */ +/* Requirements : HL_SR211 */ +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->NWDATx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return flag; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/** @fn uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox) + * @brief Checks if message box is valid + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the message box is valid for operation, returns + * 0 is flag not set otherwise will return the validation flag itself. + */ +/* SourceId : CAN_SourceId_006 */ +/* DesignId : CAN_DesignId_006 */ +/* Requirements : HL_SR212 */ +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->MSGVALx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flag; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/** @fn uint32 canGetLastError(canBASE_t *node) + * @brief Gets last RX/TX-Error of CAN message traffic + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @return The function will return: + * - canERROR_OK (0): When no CAN error occurred + * - canERROR_STUFF (1): When a stuff error occurred on RX message + * - canERROR_FORMAT (2): When a form/format error occurred on RX message + * - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged + * - canERROR_BIT1 (4): When a TX message monitored dominant level where + * recessive is expected + * - canERROR_BIT0 (5): When a TX message monitored recessive level where + * dominant is expected + * - canERROR_CRC (6): When a RX message has wrong CRC value + * - canERROR_NO (7): When no error occurred since last call of this function + * + * This function returns the last occurred error code of an RX or TX message, + * since the last call of this function. + * + */ +/* SourceId : CAN_SourceId_007 */ +/* DesignId : CAN_DesignId_007 */ +/* Requirements : HL_SR213 */ +uint32 canGetLastError( canBASE_t * node ) +{ + uint32 errorCode; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Get last error code */ + errorCode = node->ES & 7U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return errorCode; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn uint32 canGetErrorLevel(canBASE_t *node) + * @brief Gets error level of a CAN node + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @return The function will return: + * - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and + * 255 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * + * This function returns the current error level of a CAN node. + * + */ +/* SourceId : CAN_SourceId_008 */ +/* DesignId : CAN_DesignId_008 */ +/* Requirements : HL_SR214 */ +uint32 canGetErrorLevel( canBASE_t * node ) +{ + uint32 errorLevel; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + /** - Get error level */ + errorLevel = node->ES & 0xE0U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + return errorLevel; +} + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + +/** @fn void canEnableErrorNotification(canBASE_t *node) + * @brief Enable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * This function will enable the notification for the reaching the error levels warning, + * passive and bus off. + */ +/* SourceId : CAN_SourceId_009 */ +/* DesignId : CAN_DesignId_009 */ +/* Requirements : HL_SR215 */ +void canEnableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + node->CTL |= 8U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + +/** @fn void canEnableStatusChangeNotification(canBASE_t *node) + * @brief Enable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * This function will enable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_030 */ +/* DesignId : CAN_DesignId_024 */ +/* Requirements : HL_SR533 */ +void canEnableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL |= 4U; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableStatusChangeNotification(canBASE_t *node) + * @brief Disable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * This function will disable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_031 */ +/* DesignId : CAN_DesignId_025 */ +/* Requirements : HL_SR534 */ +void canDisableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL &= ~( uint32 ) ( 4U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/** @fn void canDisableErrorNotification(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * This function will disable the notification for the reaching the error levels + * warning, passive and bus off. + */ +/* SourceId : CAN_SourceId_010 */ +/* DesignId : CAN_DesignId_010 */ +/* Requirements : HL_SR216 */ +void canDisableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + node->CTL &= ~( uint32 ) ( 8U ); + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] Loopbacktype Type of Loopback: + * - Internal_Lbk: Internal Loop Back + * - External_Lbk: External Loop Back + * - Internal_Silent_Lbk: Internal Loop Back with Silent mode. + * + * This function will enable can loopback mode + */ +/* SourceId : CAN_SourceId_011 */ +/* DesignId : CAN_DesignId_011 */ +/* Requirements : HL_SR521 */ +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ) +{ + /* Enter Test Mode */ + node->CTL |= ( uint32 ) ( ( uint32 ) 1U << 7U ); + + /* Configure Loopback */ + node->TEST |= ( uint32 ) Loopbacktype; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableloopback(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * This function will disable can loopback mode + */ +/* SourceId : CAN_SourceId_012 */ +/* DesignId : CAN_DesignId_012 */ +/* Requirements : HL_SR522 */ +void canDisableloopback( canBASE_t * node ) +{ + node->TEST &= ~( uint32 ) ( 0x00000118U ); + + /* Exit Test Mode */ + node->CTL &= ~( uint32 ) ( ( uint32 ) 1U << 7U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir) + * @brief Set Port Direction + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] TxDir - TX Pin direction + * @param[in] RxDir - RX Pin direction + * + * Set the direction of CAN pins at runtime when configured as IO pins. + */ +/* SourceId : CAN_SourceId_013 */ +/* DesignId : CAN_DesignId_013 */ +/* Requirements : HL_SR217 */ +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ) +{ + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFBU ) | ( TxDir << 2U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFBU ) | ( RxDir << 2U ) ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue) + * @brief Write Port Value + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] TxValue - TX Pin value 0 or 1 + * @param[in] RxValue - RX Pin value 0 or 1 + * + * Writes a value to TX and RX pin of a given CAN module when configured as IO pins. + */ +/* SourceId : CAN_SourceId_014 */ +/* DesignId : CAN_DesignId_014 */ +/* Requirements : HL_SR218 */ +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFDU ) | ( TxValue << 1U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFDU ) | ( RxValue << 1U ) ); + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn uint32 canIoTxGetBit(canBASE_t *node) + * @brief Read TX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the TX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_015 */ +/* DesignId : CAN_DesignId_015 */ +/* Requirements : HL_SR219 */ +uint32 canIoTxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + return ( node->TIOC & 1U ); +} + +/** @fn uint32 canIoRxGetBit(canBASE_t *node) + * @brief Read RX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the RX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_016 */ +/* DesignId : CAN_DesignId_016 */ +/* Requirements : HL_SR220 */ +uint32 canIoRxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + + return ( node->RIOC & 1U ); +} + +/** @fn void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_017 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : HL_SR224 */ +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN1_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN1_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN1_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN1_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN1_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN1_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN1_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN1_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN1_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTL = canREG1->CTL; + config_reg->CONFIG_ES = canREG1->ES; + config_reg->CONFIG_BTR = canREG1->BTR; + config_reg->CONFIG_TEST = canREG1->TEST; + config_reg->CONFIG_ABOTR = canREG1->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG1->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG1->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG1->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG1->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG1->TIOC; + config_reg->CONFIG_RIOC = canREG1->RIOC; + } +} + +/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_018 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : HL_SR224 */ +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTL = canREG2->CTL; + config_reg->CONFIG_ES = canREG2->ES; + config_reg->CONFIG_BTR = canREG2->BTR; + config_reg->CONFIG_TEST = canREG2->TEST; + config_reg->CONFIG_ABOTR = canREG2->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG2->TIOC; + config_reg->CONFIG_RIOC = canREG2->RIOC; + } +} + +/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_019 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : HL_SR224 */ +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTL = canREG3->CTL; + config_reg->CONFIG_ES = canREG3->ES; + config_reg->CONFIG_BTR = canREG3->BTR; + config_reg->CONFIG_TEST = canREG3->TEST; + config_reg->CONFIG_ABOTR = canREG3->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG3->TIOC; + config_reg->CONFIG_RIOC = canREG3->RIOC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/dabort.S b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/dabort.S new file mode 100644 index 00000000000..2721421d647 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/dabort.S @@ -0,0 +1,167 @@ +/*-------------------------------------------------------------------------- + dabort.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +--------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + + +/*-------------------------------------------------------------------------------*/ +@ Run Memory Test + + .extern custom_dabort + .extern vHandleMemoryFault + .weak _dabort + .type _dabort, %function + +_dabort: + stmfd r13!, {r0 - r12, lr}@ push registers and link register on to stack + ldr r12, esmsr3 @ ESM Group3 status register + ldr r0, [r12] + tst r0, #0x8 @ check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM + bne ramErrorFound + tst r0, #0x20 @ check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM + bne ramErrorFound2 + +noRAMerror: + tst r0, #0x80 @ check if bit 7 is set, this indicates uncorrectable ECC error on ATCM + bne flashErrorFound + +/* Create a Exception Fault Stack similiar to the way it is created by the ARMvM + * architecture. The auto-pushed exception stack will contain: + * +-------+-----+----------+----------+------+ + * | R0-R3 | R12 | LR (R14) | PC (R15) | CPSR | + * +-------+-----+----------+----------+------+ + * + * <-------><----><---------><---------><-----> + * 4 1 1 1 1 +*/ +MemManage_Handler: + /* Pop the pushed values so we can re-do the stack the way we need it to be */ + LDMFD R13!, {R0 - R12, LR} + /* Abort exceptions increment the LR 0x8 after the fault-inducing instruction */ + SUB LR, #0x8 + + SRSDB SP!, #0x17 /* Save the pre-exception PC and CPSR */ + STMDB SP, { R0-R3, R12, LR }^ /* Save the user R0-R3, R12, and LR */ + SUB SP, SP, #0x18 /* Can't auto-increment SP with ^ operator */ + /* Need the SP in R0 */ + MOV R0, SP + + /* Call vHandleMemoryFault - This will modify the return state if necessary */ + BLX vHandleMemoryFault + + POP { R0-R3, R12, LR } /* Pop the original values off the stack */ + /* Return to the next instruction after the fault was generated */ + RFEIA SP! + +ramErrorFound: + ldr r1, ramctrl @ RAM control register for B0TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x08 + str r2, [r12] @ clear ESM group3 channel3 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + +ramErrorFound2: + ldr r1, ram2ctrl @ RAM control register for B1TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x20 + str r2, [r12] @ clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +ramErrorReal: + b ramErrorReal @ branch here forever as continuing operation is not recommended + +flashErrorFound: + ldr r1, flashbase + ldr r2, [r1, #0x6C] @ read FDIAGCTRL register + + mov r2, r2, lsr #16 + tst r2, #5 @ check if bits 19:16 are 5, this indicates diagnostic mode is enabled + beq flashErrorReal + mov r2, #1 + mov r2, r2, lsl #8 + + str r2, [r1, #0x1C] @ clear FEDACSTATUS error flag + + mov r2, #0x80 + str r2, [r12] @ clear ESM group3 flag for uncorrectable flash ECC error + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +flashErrorReal: + b flashErrorReal @ branch here forever as continuing operation is not recommended + +esmsr3: .word 0xFFFFF520 +ramctrl: .word 0xFFFFF800 +ram2ctrl: .word 0xFFFFF900 +ram1errstat: .word 0xFFFFF810 +ram2errstat: .word 0xFFFFF910 +flashbase: .word 0xFFF87000 + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/emac.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/emac.c new file mode 100644 index 00000000000..0a88081dbe7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/emac.c @@ -0,0 +1,1947 @@ +/** + * \file emac.c + * + * \brief EMAC APIs. + * + * This file contains the device abstraction layer APIs for EMAC. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emac.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Defining interface for all the emac instances */ +hdkif_t hdkif_data[ MAX_EMAC_INSTANCE ]; +/*SAFETYMCUSW 25 D MR:8.7 "Statically allocated memory needs to be available to + * entire application." */ +static uint8_t pbuf_array[ MAX_RX_PBUF_ALLOC ][ MAX_TRANSFER_UNIT ]; + +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define EMAC_CONTROL_RESET ( 0x01U ) +#define EMAC_SOFT_RESET ( 0x01U ) +#define EMAC_MAX_HEADER_DESC ( 8U ) +#define EMAC_UNICAST_DISABLE ( 0xFFU ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ + +/** + * \brief Enables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_001 */ +/* DesignId : ETH_DesignId_001*/ +/* Requirements : HL_ETH_SR15 */ +void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_TXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnTXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_002 */ +/* DesignId : ETH_DesignId_002*/ +/* Requirements : HL_ETH_SR15 */ +void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnTXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Enables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be enabled. + * \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_003 */ +/* DesignId : ETH_DesignId_003*/ +/* Requirements : HL_ETH_SR15 */ +void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnRXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be disabled. + * \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_004 */ +/* DesignId : ETH_DesignId_004*/ +/* Requirements : HL_ETH_SR15 */ +void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnRXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or + * 100 Mbps + * + * \param emacBase Base address of the EMAC Module registers. + * \param speed speed for setting. + * speed can take the following values. \n + * EMAC_RMIISPEED_10MBPS - 10 Mbps \n + * EMAC_RMIISPEED_100MBPS - 100 Mbps. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_005 */ +/* DesignId : ETH_DesignId_005*/ +/* Requirements : HL_ETH_SR19 */ +void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RMIISPEED ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= speed; +} +/* SourceId : ETH_SourceId_006 */ +/* DesignId : ETH_DesignId_006*/ +/* Requirements : HL_ETH_SR18 */ + +/** + * \brief This API set the GMII bit, RX and TX are enabled for receive and transmit. + * Note: This is not the API to enable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +void EMACMIIEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_GMIIEN; +} + +/** + * \brief This API clears the GMII bit, Rx and Tx are held in reset. + * Note: This is not the API to disable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_007 */ +/* DesignId : ETH_DesignId_007*/ +/* Requirements : HL_ETH_SR18 */ +void EMACMIIDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); +} + +/** + * \brief This API sets the duplex mode of operation(full/half) for MAC. + * + * \param emacBase Base address of the EMAC Module registers. + * \param duplexMode duplex mode of operation. + * duplexMode can take the following values. \n + * EMAC_DUPLEX_FULL - Full Duplex \n + * EMAC_DUPLEX_HALF - Half Duplex. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_008 */ +/* DesignId : ETH_DesignId_008*/ +/* Requirements : HL_ETH_SR21 */ +void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_FULLDUPLEX ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= duplexMode; +} + +/** + * \brief API to enable the transmit in the TX Control Register + * After the transmit is enabled, any write to TXHDP of + * a channel will start transmission + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_009 */ +/* DesignId : ETH_DesignId_009*/ +/* Requirements : HL_ETH_SR21 */ +void EMACTxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXEN; +} + +/** + * \brief API to disable the transmit in the TX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_010 */ +/* DesignId : ETH_DesignId_010*/ +/* Requirements : HL_ETH_SR21 */ +void EMACTxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXDIS; +} + +/** + * \brief API to enable the receive in the RX Control Register + * After the receive is enabled, and write to RXHDP of + * a channel, the data can be received in the destination + * specified by the corresponding RX buffer descriptor. + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_011*/ +/* DesignId : ETH_DesignId_011*/ +/* Requirements : HL_ETH_SR21 */ +void EMACRxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXEN; +} + +/** + * \brief API to disable the receive in the RX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_012*/ +/* DesignId : ETH_DesignId_012*/ +/* Requirements : HL_ETH_SR21 */ +void EMACRxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXDIS; +} + +/** + * \brief API to write the TX HDP register. If transmit is enabled, + * write to the TX HDP will immediately start transmission. + * The data will be taken from the buffer pointer of the TX buffer + * descriptor written to the TX HDP + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the TX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_013*/ +/* DesignId : ETH_DesignId_013*/ +/* Requirements : HL_ETH_SR16 */ +void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXHDP( channel ) ) = descHdr; +} + +/** + * \brief API to write the RX HDP register. If receive is enabled, + * write to the RX HDP will enable data reception to point to + * the corresponding RX buffer descriptor's buffer pointer. + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the RX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_014 */ +/* DesignId : ETH_DesignId_014*/ +/* Requirements : HL_ETH_SR16 */ +void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXHDP( channel ) ) = descHdr; +} + +/** + * \brief This API Initializes the EMAC and EMAC Control modules. The + * EMAC Control module is reset, the CPPI RAM is cleared. also, + * all the interrupts are disabled. This API does not enable any + * interrupt or operation of the EMAC. + * + * \param emacCtrlBase Base Address of the EMAC Control module + * registers.\n + * \param emacBase Base address of the EMAC module registers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_015 */ +/* DesignId : ETH_DesignId_015*/ +/* Requirements : HL_ETH_SR6 */ +void EMACInit( uint32 emacCtrlBase, uint32 emacBase ) +{ + uint32 cnt; + + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + } /* Wait */ + + /* Reset the EMAC Module. This clears the CPPI RAM also */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + } /* Wait */ + + HWREG( emacBase + EMAC_MACCONTROL ) = 0U; + HWREG( emacBase + EMAC_RXCONTROL ) = 0U; + HWREG( emacBase + EMAC_TXCONTROL ) = 0U; + + /* Initialize all the header descriptor pointer registers */ + for( cnt = 0U; cnt < EMAC_MAX_HEADER_DESC; cnt++ ) + { + HWREG( emacBase + EMAC_RXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXFREEBUFFER( cnt ) ) = 0xFFU; + } + + /* Clear the interrupt enable for all the channels */ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) = 0xFFU; + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) = 0xFFU; + + HWREG( emacBase + EMAC_MACHASH1 ) = 0U; + HWREG( emacBase + EMAC_MACHASH2 ) = 0U; + + HWREG( emacBase + EMAC_RXBUFFEROFFSET ) = 0U; +} + +/** + * \brief Sets the MAC Address in MACSRCADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_016 */ +/* DesignId : ETH_DesignId_016*/ +/* Requirements : HL_ETH_SR7 */ +void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ) +{ + HWREG( emacBase + EMAC_MACSRCADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACSRCADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) ); +} + +/** + * \brief Sets the MAC Address in MACADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param matchFilt Match or Filter + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * matchFilt can take the following values \n + * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match + * or filter incoming packet. \n + * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n + * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_017 */ +/* DesignId : ETH_DesignId_017*/ +/* Requirements : HL_ETH_SR7 */ +void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ) +{ + HWREG( emacBase + EMAC_MACINDEX ) = channel; + + HWREG( emacBase + EMAC_MACADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) + | matchFilt | ( channel << 16U ) ); +} + +/** + * \brief Acknowledges an interrupt processed to the EMAC Control Core. + * + * \param emacBase Base Address of the EMAC module registers. + * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control + * module. + * eoiFlag can take the following values \n + * EMAC_INT_CORE0_TX - Core 0 TX Interrupt + * EMAC_INT_CORE1_TX - Core 1 TX Interrupt + * EMAC_INT_CORE2_TX - Core 2 TX Interrupt + * EMAC_INT_CORE0_RX - Core 0 RX Interrupt + * EMAC_INT_CORE1_RX - Core 1 RX Interrupt + * EMAC_INT_CORE2_RX - Core 2 RX Interrupt + * \return None + * + **/ +/* SourceId : ETH_SourceId_018 */ +/* DesignId : ETH_DesignId_018*/ +/* Requirements : HL_ETH_SR15 */ +void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ) +{ + /* Acknowledge the EMAC Control Core */ + HWREG( emacBase + EMAC_MACEOIVECTOR ) = eoiFlag; +} + +/** + * \brief Writes the the TX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_019 */ +/* DesignId : ETH_DesignId_019*/ +/* Requirements : HL_ETH_SR27 */ +void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_TXCP( channel ) ) = comPtr; +} + +/** + * \brief Writes the the RX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_020 */ +/* DesignId : ETH_DesignId_020*/ +/* Requirements : HL_ETH_SR27 */ +void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_RXCP( channel ) ) = comPtr; +} + +/** + * \brief Enables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_021 */ +/* DesignId : ETH_DesignId_021*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + + HWREG( + emacBase + + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXBROADEN + | ( ( uint32 ) channel + << ( uint32 ) EMAC_RXMBPENABLE_RXBROADCH_SHIFT ) ); +} + +/** + * \brief Disables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_022 */ +/* DesignId : ETH_DesignId_022*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + /* Broadcast Frames are filtered. */ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADEN ); +} + +/** + * \brief Enables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_023 */ +/* DesignId : ETH_DesignId_023*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXMULTEN + | ( channel ) ); +} + +/** + * \brief Disables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_024 */ +/* DesignId : ETH_DesignId_024*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTEN ); +} + +/** + * \brief Enables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_025 */ +/* DesignId : ETH_DesignId_025*/ +/* Requirements : HL_ETH_SR14 */ +void EMACRxUnicastSet( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXUNICASTSET ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_026 */ +/* DesignId : ETH_DesignId_026*/ +/* Requirements : HL_ETH_SR14 */ +void EMACRxUnicastClear( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXUNICASTCLEAR ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Set the free buffers for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param nBuf Number of free buffers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_027 */ +/* DesignId : ETH_DesignId_027*/ +/* Requirements : HL_ETH_SR20 */ +void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ) +{ + HWREG( emacBase + EMAC_RXFREEBUFFER( channel ) ) = nBuf; +} + +/** + * \brief Gets the interrupt vectors of EMAC, which are pending + * + * \param emacBase Base Address of the EMAC module registers. + * + * \return Vectors + * + **/ +/* SourceId : ETH_SourceId_028 */ +/* DesignId : ETH_DesignId_028*/ +/* Requirements : HL_ETH_SR15 */ +uint32 EMACIntVectorGet( uint32 emacBase ) +{ + return ( HWREG( emacBase + EMAC_MACINVECTOR ) ); +} + +/** + * Function to setup the instance parameters inside the interface + * @param hdkif Network interface structure + * @return none. + */ +/* SourceId : ETH_SourceId_029 */ +/* DesignId : ETH_DesignId_029*/ +/* Requirements : HL_ETH_SR6 */ +void EMACInstConfig( hdkif_t * hdkif ) +{ + hdkif->emac_base = EMAC_0_BASE; + hdkif->emac_ctrl_base = EMAC_CTRL_0_BASE; + hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE; + hdkif->mdio_base = MDIO_BASE; + hdkif->phy_addr = 1U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker. + */ + hdkif->phy_autoneg = &Dp83640AutoNegotiate; + hdkif->phy_partnerability = &Dp83640PartnerAbilityGet; +} + +/** + * Function to setup the link. AutoNegotiates with the phy for link + * setup and set the EMAC with the result of autonegotiation. + * @param hdkif Network interface structure. + * @return ERR_OK if everything passed + * others if not passed + */ +/* SourceId : ETH_SourceId_030 */ +/* DesignId : ETH_DesignId_030*/ +/* Requirements : HL_ETH_SR6 */ +uint32 EMACLinkSetup( hdkif_t * hdkif ) +{ + uint32 linkstat = EMAC_ERR_CONNECT; + uint16 partnr_ablty = 0U; + uint32 phyduplex = EMAC_DUPLEX_HALF; + volatile uint32 delay = 0xFFFFFU; + + if( Dp83640AutoNegotiate( ( uint32 ) hdkif->mdio_base, + ( uint32 ) hdkif->phy_addr, + ( uint16 ) ( ( uint16 ) DP83640_100BTX + | ( uint16 ) DP83640_100BTX_FD + | ( uint16 ) DP83640_10BT + | ( uint16 ) DP83640_10BT_FD ) ) + == TRUE ) + { + linkstat = EMAC_ERR_OK; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA + * checker (due to use of & ?) */ + ( void ) Dp83640PartnerAbilityGet( hdkif->mdio_base, + hdkif->phy_addr, + &partnr_ablty ); + + /* Check for 100 Mbps and duplex capability */ + if( ( partnr_ablty & DP83640_100BTX_FD ) != 0U ) + { + phyduplex = EMAC_DUPLEX_FULL; + } + } + + else + { + linkstat = EMAC_ERR_CONNECT; + } + + /* Set the EMAC with the negotiation results if it is successful */ + if( linkstat == EMAC_ERR_OK ) + { + EMACDuplexSet( hdkif->emac_base, phyduplex ); + } + + /* Wait for the MII to settle down */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + delay--; + } + + return linkstat; +} + +/** + * \brief Perform a transmit queue teardown, that is, transmission is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_031 */ +/* DesignId : ETH_DesignId_031*/ +/* Requirements : HL_ETH_SR22 */ +void EMACTxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform a receive queue teardown, that is, reception is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_032 */ +/* DesignId : ETH_DesignId_032*/ +/* Requirements : HL_ETH_SR22 */ +void EMACRxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform multicast frame filtering using the MAC Hash Registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param hashTable The hash table which specifies which bits are to be accepted. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_033 */ +/* DesignId : ETH_DesignId_033*/ +/* Requirements : HL_ETH_SR24 */ +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ) +{ + HWREG( emacBase + EMAC_MACHASH1 ) = ( uint32 ) ( hashTable & 0xFFFFFFFFU ); + HWREG( emacBase + EMAC_MACHASH2 ) = ( uint32 ) ( hashTable >> 32U ); +} + +/** + * \brief Sets the Transmit Queue Priority type in the MACCONTROL Register + * + * \param emacBase Base Address of the EMAC module registers. + * \param txPType The Transmit Queue Priority Type. + * 0 results in a round-robin scheme being used to select the next + *channel, while 1 results in a fixed-priority scheme( channel 7 highest priority). + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_034 */ +/* DesignId : ETH_DesignId_034*/ +/* Requirements : HL_ETH_SR25 */ +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ) +{ + /* 1- The queue uses a fixed-priority (channel 7 highest priority) scheme */ + if( txPType == 1U ) + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXPTYPE; + } + else + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + } +} + +/** + * \brief Performs a soft reset of the EMAC and EMAC Control Modules. + * + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_035 */ +/* DesignId : ETH_DesignId_035*/ +/* Requirements : HL_ETH_SR26 */ +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ) +{ + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + /* Wait for the reset to complete */ + } + + /* Reset the EMAC Module. */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + /* Wait for the Reset to complete */ + } +} + +/** + * \brief Enable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_036 */ +/* DesignId : ETH_DesignId_036*/ +/* Requirements : HL_ETH_SR32 */ +void EMACEnableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_CMDIDLE; +} + +/** + * \brief Disable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_037 */ +/* DesignId : ETH_DesignId_037*/ +/* Requirements : HL_ETH_SR32 */ +void EMACDisableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_CMDIDLE ) ); +} + +/** + * \brief Enables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_038 */ +/* DesignId : ETH_DesignId_038*/ +/* Requirements : HL_ETH_SR50 */ +void EMACEnableLoopback( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + uint32 GMIIENval = 0U; + + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Enable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_LOOPBACK; + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Disables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_039 */ +/* DesignId : ETH_DesignId_039*/ +/* Requirements : HL_ETH_SR50 */ +void EMACDisableLoopback( uint32 emacBase ) +{ + uint32 GMIIENval = 0U; + + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Disable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_LOOPBACK ); + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Enable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_040 */ +/* DesignId : ETH_DesignId_040*/ +/* Requirements : HL_ETH_SR20 */ +void EMACTxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXFLOWEN; +} + +/** + * \brief Disable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_041 */ +/* DesignId : ETH_DesignId_041*/ +/* Requirements : HL_ETH_SR20 */ +void EMACTxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_TXFLOWEN ); +} + +/** + * \brief Enable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_042 */ +/* DesignId : ETH_DesignId_042*/ +/* Requirements : HL_ETH_SR20 */ +void EMACRxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_RXBUFFERFLOWEN; +} + +/** + * \brief Disable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_043 */ +/* DesignId : ETH_DesignId_043*/ +/* Requirements : HL_ETH_SR20 */ +void EMACRxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RXBUFFERFLOWEN ); +} + +/** + * \brief Receive flow threshold. These bits contain the threshold value for issuing + *flow control on incoming frames for channel n (when enabled). + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param threshold threshold value for issuing flow control on incoming frames for + *the given channel \return None + * + **/ +/* SourceId : ETH_SourceId_044 */ +/* DesignId : ETH_DesignId_044*/ +/* Requirements : HL_ETH_SR20 */ +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ) +{ + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) &= ( 0x0U ); + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) |= threshold; +} + +/** + * \brief This function reads the contents of the 36 network statistics + *registers that are present in the module. \param emacBase Base Address of the EMAC + *module registers. \param statRegNo The number of the register with RXGOODFRAMES + *(Offset= 0x200) being 0. Refer the Technical Reference Manual for the list of registers + *and their contents. \return uint32 + **/ +/* SourceId : ETH_SourceId_045 */ +/* DesignId : ETH_DesignId_045*/ +/* Requirements : HL_ETH_SR29 */ +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ) +{ + return HWREG( emacBase + EMAC_NETSTATREGS( statRegNo ) ); +} + +/** + * \brief Function to read values of Transmit Interrupt Status registers + *(TXINTSTATMASKED and TXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param txintstat pointer to the emac_tx_int_status Structure that will store the + *register values that have been read \return None + * + **/ +/* SourceId : ETH_SourceId_046 */ +/* DesignId : ETH_DesignId_046*/ +/* Requirements : HL_ETH_SR23 */ +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ) +{ + txintstat->intstatmasked = ( HWREG( emacBase + EMAC_TXINTSTATMASKED ) + & ( ( uint32 ) 1U << channel ) ); + txintstat->intstatraw = ( HWREG( emacBase + EMAC_TXINTSTATRAW ) + & ( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Function to read values of Receive Interrupt Status registers + *(RXINTSTATMASKED, RXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param rxintstat pointer to the emac_rx_int_status Structure that will store the + *register values that have been read. \return None + **/ +/* SourceId : ETH_SourceId_047 */ +/* DesignId : ETH_DesignId_047*/ +/* Requirements : HL_ETH_SR23 */ +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ) +{ + rxintstat->intstatmasked_pend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatmasked_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); + + rxintstat->intstatraw_pend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatraw_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); +} + +/** + * \brief Tx and Rx Buffer Descriptors are initialized. Buffer pointers are allocated to + *the Rx Descriptors. + * + * \param hdkif network interface structure + * \return None + * + **/ +/* SourceId : ETH_SourceId_048 */ +/* DesignId : ETH_DesignId_048*/ +/* Requirements : HL_ETH_SR17,HL_ETH_SR30 */ +void EMACDMAInit( hdkif_t * hdkif ) +{ + uint32 num_bd, pbuf_cnt = 0U; + volatile emac_tx_bd_t *curr_txbd, *last_txbd; + volatile emac_rx_bd_t *curr_bd, *last_bd; + txch_t * txch_dma; + rxch_t * rxch_dma; + uint8_t * p; + + txch_dma = &( hdkif->txchptr ); + + /** + * Initialize the Descriptor Memory For TX and RX + * Only single channel is supported for both TX and RX + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + txch_dma->free_head = ( volatile emac_tx_bd_t * ) ( hdkif->emac_ctrl_ram ); + txch_dma->next_bd_to_process = txch_dma->free_head; + txch_dma->active_tail = NULL; + + /* Set the number of descriptors for the channel */ + num_bd = ( SIZE_EMAC_CTRL_RAM >> 1U ) / sizeof( emac_tx_bd_t ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_txbd = txch_dma->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd = curr_txbd; + + /* Initialize all the TX buffer Descriptors */ + while( num_bd != 0U ) + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list + * is incremented." */ + curr_txbd->next = curr_txbd + 1U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd->flags_pktlen = 0U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_txbd = curr_txbd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd = curr_txbd->next; + num_bd--; + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd->next = txch_dma->free_head; + + /* Initialize the descriptors for the RX channel */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma = &( hdkif->rxchptr ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is + * incremented." */ + curr_txbd++; + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "Linked List pointer needs to be + * assigned." */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "Linked List pointer needs to be assigned." + */ + /*SAFETYMCUSW 344 S MR:11.5 "Linked List pointer needs to be assigned to a + * different structure." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_head = ( volatile emac_rx_bd_t * ) curr_txbd; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->free_head = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_dma->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = curr_bd; + + /* + ** Static allocation of a specific number of packet buffers as specified by + *MAX_RX_PBUF_ALLOC, whose value is entered by the user in HALCoGen GUI. + */ + + /*Commented part of allocation of pbufs need to check whether its true*/ + + for( pbuf_cnt = 0U; pbuf_cnt < MAX_RX_PBUF_ALLOC; pbuf_cnt++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + p = pbuf_array[ pbuf_cnt ]; + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = ( uint32 ) p; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = MAX_TRANSFER_UNIT; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMAC_BUF_DESC_OWNER; + + if( pbuf_cnt == ( MAX_RX_PBUF_ALLOC - 1U ) ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + else + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd->next = ( curr_bd + 1U ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd++; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_tail = last_bd; +} + +/** + * \brief Initializes the EMAC module for transmission and reception. + * + * \param macaddr MAC Address of the Module. + * \param channel Channel Number. + * + * \return EMAC_ERR_OK if everything gets initialized + * EMAC_ERR_CONN in case of an error in connecting. + * + **/ +/* SourceId : ETH_SourceId_049 */ +/* DesignId : ETH_DesignId_049*/ +/* Requirements : HL_ETH_SR6 */ +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ) +{ + uint32 temp, channel; + volatile uint32 phyID = 0U; + volatile uint32 delay = 0xFFFU; + uint32 phyIdReadCount = 0xFFFFU; + volatile uint32 phyLinkRetries = 0xFFFFU; + hdkif_t * hdkif; + rxch_t * rxch; + uint32 retVal = EMAC_ERR_OK; + uint32 emacBase = 0U; + +#if( EMAC_MII_ENABLE == 0U ) + uint16 partnr_spd; +#endif + + hdkif = &hdkif_data[ 0U ]; + EMACInstConfig( hdkif ); + + /* set MAC hardware address */ + for( temp = 0U; temp < EMAC_HWADDR_LEN; temp++ ) + { + hdkif->mac_addr[ temp ] = macaddr[ ( EMAC_HWADDR_LEN - 1U ) - temp ]; + } + + /*Initialize the EMAC, EMAC Control and MDIO modules. */ + EMACInit( hdkif->emac_ctrl_base, hdkif->emac_base ); + MDIOInit( hdkif->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + delay--; + } + + /* Set the MAC Addresses in EMAC hardware */ + emacBase = hdkif->emac_base; /* MISRA Code Fix (12.2) */ + EMACMACSrcAddrSet( emacBase, hdkif->mac_addr ); + + for( channel = 0U; channel < 8U; channel++ ) + { + emacBase = hdkif->emac_base; + EMACMACAddrSet( emacBase, channel, hdkif->mac_addr, EMAC_MACADDR_MATCH ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( phyID == 0U ) && ( phyIdReadCount > 0U ) ) + { + phyID = Dp83640IDGet( hdkif->mdio_base, hdkif->phy_addr ); + phyIdReadCount--; + } + + if( 0U == phyID ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( ( uint32 ) 0U + == ( ( MDIOPhyAliveStatusGet( hdkif->mdio_base ) >> hdkif->phy_addr ) + & ( uint32 ) 0x01U ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + +#if( EMAC_MII_ENABLE == 0U ) + Dp83640PartnerSpdGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_spd ); + + if( ( partnr_spd & 2U ) == 0U ) + { + EMACRMIISpeedSet( hdkif->emac_base, EMAC_MACCONTROL_RMIISPEED ); + } +#endif + + if( !Dp83640LinkStatusGet( hdkif->mdio_base, + ( uint32 ) EMAC_PHYADDRESS, + ( uint32 ) phyLinkRetries ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( EMACLinkSetup( hdkif ) != EMAC_ERR_OK ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + /* The transmit and receive buffer descriptors are initialized here. + * Also, packet buffers are allocated to the receive buffer descriptors. + */ + + EMACDMAInit( hdkif ); + + /* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/ + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_RX ); + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_TX ); + + /* Enable GMII bit in the MACCONTROL Rgister*/ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ + EMACMIIEnable( hdkif->emac_base ); + +/* Enable Broadcast if enabled in the GUI. */ +/*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_BROADCAST_ENABLE ) + EMACRxBroadCastEnable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxBroadCastDisable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + +/* Enable Broadcast if enabled in the GUI. */ +/*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_UNICAST_ENABLE ) + EMACRxUnicastSet( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxUnicastClear( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + +/*Enable Full Duplex or Half-Duplex mode based on GUI Input. */ +/*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_FULL_DUPLEX_ENABLE ) + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_FULL ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition arameter is taken as input from + * GUI." */ + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_HALF ); +#endif + +/* Enable Loopback based on GUI Input */ +/*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_LOOPBACK_ENABLE ) + EMACEnableLoopback( hdkif->emac_base ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACDisableLoopback( hdkif->emac_base ); +#endif + +/* Enable Transmit and Transmit Interrupt */ +/*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_TX_ENABLE ) + EMACTxEnable( hdkif->emac_base ); + EMACTxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACTxDisable( hdkif->emac_base ); + EMACTxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + +/* Enable Receive and Receive Interrupt. Then start receiving by writing to the HDP + * register. */ +/*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_RX_ENABLE ) + EMACNumFreeBufSet( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) MAX_RX_PBUF_ALLOC ); + EMACRxEnable( hdkif->emac_base ); + EMACRxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); + rxch = &( hdkif->rxchptr ); + /* Write to the RX HDP for channel 0 */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) rxch->active_head, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxDisable( hdkif->emac_base ); + EMACRxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif /* if ( EMAC_RX_ENABLE ) */ + + return retVal; +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf might be + * chained. That is, one pbuf can span more than one tx buffer descriptors + * + * @param hdkif network interface structure + * @param pbuf the pbuf structure which contains the data to be sent using EMAC + * @return boolean. + * -Returns FALSE if a Null pointer was passed for transmission + * -Returns TRUE if valid data is sent and is transmitted. + */ +/* SourceId : ETH_SourceId_050 */ +/* DesignId : ETH_DesignId_050*/ +/* Requirements : HL_ETH_SR31 */ +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ) +{ + txch_t * txch; + pbuf_t * q; + uint16 totLen; + uint16 qLen; + volatile emac_tx_bd_t *curr_bd, *active_head, *bd_end; + boolean retValue = FALSE; + + if( ( pbuf != NULL ) && ( hdkif != NULL ) ) + { + txch = &( hdkif->txchptr ); + + /* Get the buffer descriptor which is free to transmit */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + active_head = curr_bd; + + /* Update the total packet length */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen &= ( ~( ( uint32 ) 0xFFFFU ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + totLen = pbuf->tot_len; + curr_bd->flags_pktlen |= ( uint32 ) ( totLen ); + + /* Indicate the start of the packet */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen |= ( EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER ); + + /* Copy pbuf information into TX buffer descriptors */ + q = pbuf; + + while( q != NULL ) + { + /* Initialize the buffer pointer and length */ + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = ( uint32 ) ( q->payload ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + qLen = q->len; + curr_bd->bufoff_len = ( ( uint32 ) ( qLen ) & 0xFFFFU ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = curr_bd->next; + q = q->next; + } + + /* Indicate the start and end of the packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end->next = NULL; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + bd_end->flags_pktlen |= EMAC_BUF_DESC_EOP; + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." + */ + txch->free_head = curr_bd; + + /* For the first time, write the HDP with the filled bd */ + if( txch->active_tail == NULL ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /* + * Chain the bd's. If the DMA engine, already reached the end of the chain, + * the EOQ will be set. In that case, the HDP shall be written again. + */ + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->active_tail; + + /* Wait for the EOQ bit is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( EMAC_BUF_DESC_EOQ != ( curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ ) ) + { + } + + /* Don't write to TXHDP0 until it turns to zero */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( ( uint32 ) 0U != *( ( uint32 * ) 0xFCF78600U ) ) ) + { + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = active_head; + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( EMAC_BUF_DESC_EOQ == ( curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ ) ) + { + /* Write the Header Descriptor Pointer and start DMA */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch->active_tail = bd_end; + retValue = TRUE; + } + else + { + retValue = FALSE; + } + + return retValue; +} + +/** + * Function for processing Tx buffer descriptors. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_051 */ +/* DesignId : ETH_DesignId_051*/ +/* Requirements : HL_ETH_SR15 */ +void EMACTxIntHandler( hdkif_t * hdkif ) +{ + txch_t * txch_int; + volatile emac_tx_bd_t *curr_bd, *next_bd_to_process; + + txch_int = &( hdkif->txchptr ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = next_bd_to_process; + + /* Check for correct start of packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( ( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_SOP ) == EMAC_BUF_DESC_SOP ) + { + /* Make sure that the transmission is over */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_OWNER ) + == EMAC_BUF_DESC_OWNER ) + { + } + + /* Traverse till the end of packet is reached */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOP ) != EMAC_BUF_DESC_EOP ) + { + curr_bd = curr_bd->next; + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process->flags_pktlen &= ~( EMAC_BUF_DESC_SOP ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen &= ~( EMAC_BUF_DESC_EOP ); + + /** + * If there are no more data transmitted, the next interrupt + * shall happen with the pbuf associated with the free_head + */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( curr_bd->next == NULL ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = txch_int->free_head; + } + + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = curr_bd->next; + } + + /* Acknowledge the EMAC and free the corresponding pbuf */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as + * an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 344 S MR:11.5 "Address stored in pointer is passed as as + * an int parameter." */ + EMACTxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) curr_bd ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = next_bd_to_process; + } +} + +/** + * Function for processing received packets. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_052 */ +/* DesignId : ETH_DesignId_052*/ +/* Requirements : HL_ETH_SR31 */ +void EMACReceive( hdkif_t * hdkif ) +{ + rxch_t * rxch_int; + volatile emac_rx_bd_t *curr_bd, *curr_tail, *last_bd; + + /* The receive structure that holds data about a particular receive channel */ + rxch_int = &( hdkif->rxchptr ); + + /* Get the buffer descriptors which contain the earliest filled data */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_int->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = rxch_int->active_tail; + + /** + * Process the descriptors as long as data is available + * when the DMA is receiving data, SOP flag will be set + */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( curr_bd->flags_pktlen & EMAC_BUF_DESC_SOP ) == EMAC_BUF_DESC_SOP ) + { + /* Start processing once the packet is loaded */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( curr_bd->flags_pktlen & EMAC_BUF_DESC_OWNER ) != EMAC_BUF_DESC_OWNER ) + { + /* this bd chain will be freed after processing */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + + /* Get the total length of the packet. curr_bd points to the start + * of the packet. + */ + + /* + * The loop runs till it reaches the end of the packet. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( curr_bd->flags_pktlen & EMAC_BUF_DESC_EOP ) != EMAC_BUF_DESC_EOP ) + { + /*Update the flags for the descriptor again and the length of the buffer*/ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = ( uint32 ) EMAC_BUF_DESC_OWNER; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = ( uint32 ) MAX_TRANSFER_UNIT; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = curr_bd->next; + } + + /* Updating the last descriptor (which contained the EOP flag) */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = ( uint32 ) EMAC_BUF_DESC_OWNER; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = ( uint32 ) MAX_TRANSFER_UNIT; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = curr_bd->next; + + /* Acknowledge that this packet is processed */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) last_bd ); + + /* The next buffer descriptor is the new head of the linked list. */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->active_head = curr_bd; + + /* The processed descriptor is now the tail of the linked list. */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail = rxch_int->active_tail; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail->next = rxch_int->free_head; + + /* The last element in the already processed Rx descriptor chain is now the + * end of list. */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd->next = NULL; + + /** + * Check if the reception has ended. If the EOQ flag is set, the NULL + * Pointer is taken by the DMA engine. So we need to write the RX HDP + * with the next descriptor. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( curr_tail->flags_pktlen & EMAC_BUF_DESC_EOQ ) == EMAC_BUF_DESC_EOQ ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( rxch_int->free_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + rxch_int->active_tail = last_bd; + } + } +} + +/** @fn void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETH_SourceId_053 */ +/* DesignId : ETH_DesignId_053*/ +/* Requirements : HL_ETH_SR52 */ +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->TXCONTROL = EMAC_TXCONTROL_CONFIGVALUE; + config_reg->RXCONTROL = EMAC_RXCONTROL_CONFIGVALUE; + config_reg->TXINTMASKSET = EMAC_TXINTMASKSET_CONFIGVALUE; + config_reg->TXINTMASKCLEAR = EMAC_TXINTMASKCLEAR_CONFIGVALUE; + config_reg->RXINTMASKSET = EMAC_RXINTMASKSET_CONFIGVALUE; + config_reg->RXINTMASKCLEAR = EMAC_RXINTMASKCLEAR_CONFIGVALUE; + config_reg->MACSRCADDRHI = EMAC_MACSRCADDRHI_CONFIGVALUE; + config_reg->MACSRCADDRLO = EMAC_MACSRCADDRLO_CONFIGVALUE; + config_reg->MDIOCONTROL = EMAC_MDIOCONTROL_CONFIGVALUE; + config_reg->C0RXEN = EMAC_C0RXEN_CONFIGVALUE; + config_reg->C0TXEN = EMAC_C0TXEN_CONFIGVALUE; + } + else + { + config_reg->TXCONTROL = HWREG( EMAC_0_BASE + EMAC_TXCONTROL ); + config_reg->RXCONTROL = HWREG( EMAC_0_BASE + EMAC_RXCONTROL ); + config_reg->TXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_TXINTMASKSET ); + config_reg->TXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_TXINTMASKCLEAR ); + config_reg->RXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_RXINTMASKSET ); + config_reg->RXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_RXINTMASKCLEAR ); + config_reg->MACSRCADDRHI = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRHI ); + config_reg->MACSRCADDRLO = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRLO ); + config_reg->MDIOCONTROL = HWREG( MDIO_0_BASE + MDIO_CONTROL ); + config_reg->C0RXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnRXEN( 0U ) ); + config_reg->C0TXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnTXEN( 0U ) ); + } +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/emif.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/emif.c new file mode 100644 index 00000000000..1403fd2706b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/emif.c @@ -0,0 +1,318 @@ +/** @file emif.c + * @brief emif Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void emif_SDRAMInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function has been deprecated. + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF clock + * below 40MHz. Hence the init function needs to be called from the startup before the PLL + * is configured. A new function emif_SDRAM_StartupInit has been added and is called from + * the startup. This function need not be called from the main, and is preserved for + * compatibilty. + */ + +void emif_SDRAMInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC1Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_002 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements: HL_SR335 */ +void emif_ASYNC1Init( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + emifREG->CE2CFG = 0x00000000U; + emifREG->CE2CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFFFF00U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) + | ( uint32 ) ( ( uint32 ) 0U ); + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC2Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_003 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements: HL_SR335 */ +void emif_ASYNC2Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + emifREG->CE3CFG = 0x00000000U; + emifREG->CE3CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFF00FFU ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ); + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC3Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_004 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements: HL_SR335 */ +void emif_ASYNC3Init( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + emifREG->CE4CFG = 0x00000000U; + emifREG->CE4CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFF00FFFFU ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void emifGetConfigValue(emif_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the EMIF configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EMIF_SourceId_005 */ +/* DesignId : EMIF_DesignId_003 */ +/* Requirements: HL_SR336 */ +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_AWCC = EMIF_AWCC_CONFIGVALUE; + config_reg->CONFIG_SDCR = EMIF_SDCR_CONFIGVALUE; + config_reg->CONFIG_SDRCR = EMIF_SDRCR_CONFIGVALUE; + config_reg->CONFIG_CE2CFG = EMIF_CE2CFG_CONFIGVALUE; + config_reg->CONFIG_CE3CFG = EMIF_CE3CFG_CONFIGVALUE; + config_reg->CONFIG_CE4CFG = EMIF_CE4CFG_CONFIGVALUE; + config_reg->CONFIG_CE5CFG = EMIF_CE5CFG_CONFIGVALUE; + config_reg->CONFIG_SDTIMR = EMIF_SDTIMR_CONFIGVALUE; + config_reg->CONFIG_SDSRETR = EMIF_SDSRETR_CONFIGVALUE; + config_reg->CONFIG_INTMSK = EMIF_INTMSK_CONFIGVALUE; + config_reg->CONFIG_PMCR = EMIF_PMCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_AWCC = emifREG->AWCC; + config_reg->CONFIG_SDCR = emifREG->SDCR; + config_reg->CONFIG_SDRCR = emifREG->SDRCR; + config_reg->CONFIG_CE2CFG = emifREG->CE2CFG; + config_reg->CONFIG_CE3CFG = emifREG->CE3CFG; + config_reg->CONFIG_CE4CFG = emifREG->CE4CFG; + config_reg->CONFIG_CE5CFG = emifREG->CE5CFG; + config_reg->CONFIG_SDTIMR = emifREG->SDTIMR; + config_reg->CONFIG_SDSRETR = emifREG->SDSRETR; + config_reg->CONFIG_INTMSK = emifREG->INTMSK; + config_reg->CONFIG_PMCR = emifREG->PMCR; + } +} + +/** @fn void emif_SDRAM_StartupInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function initializes the emif driver for SDRAM (SDRAM initialization function). + * SDRAM Configuration Procedure B as documented in the TRM is implemented. + * + * Note: This function is called in the startup. Do not call the function inside main. + */ + +/* SourceId : EMIF_SourceId_001 */ +/* DesignId : EMIF_DesignId_001 */ +/* Requirements: HL_SR334 */ +void emif_SDRAM_StartupInit( void ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + volatile uint32 buffer; + + /* Procedure B Step 1: EMIF Clock Frequency is assumed to be configured in the + * startup */ + + /* Procedure B Step 2: Program SDTIMR and SDSRETR to satisfy requirements of SDRAM + * Device */ + emifREG->SDTIMR = ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ); + + emifREG->SDSRETR = ( uint32 ) 0U; + + /* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of + * initialization time */ + emifREG->SDRCR = 8000005U; + + /* Procedure B Step 4: Program SDRCR to Trigger Initialization Sequence */ + + /** -general clearing of register + * -for NM for setting 16 bit data bus + * -cas latency + * -BIT11_9CLOCK to allow the cl field to be written + * -selecting the banks + * -setting the pagesize + */ + emifREG->SDCR = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 1U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) elements_256 ); + + /* Procedure B Step 5: Read of SDRAM memory location causes processor to wait until + * SDRAM Initialization completes */ + buffer = *PTR; + /* prevents optimization */ + buffer = buffer; + + /* Procedure B Step 6: Program the RR field to the default Refresh Interval of the + * SDRAM*/ + emifREG->SDRCR = 0U; + + /* Place the EMIF in Self Refresh Mode For Clock Change */ + /* Must only write to the upper byte of the SDCR to avoid */ + /* a second intiialization sequence */ + /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */ + *( ( unsigned char * ) ( &emifREG->SDCR ) + 0x3U ) = 0x80U; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c new file mode 100644 index 00000000000..80315738a45 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c @@ -0,0 +1,402 @@ +/** @file errata_SSWF021_45.c + * @brief errata for PLLs + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "errata_SSWF021_45_defs.h" +#include "errata_SSWF021_45.h" + +static uint32 check_frequency( uint32 cnt1_clksrc ); +static uint32 disable_plls( uint32 plls ); + +/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count) + * @brief This handles the errata for PLL1 and PLL2. This function is called in device + * startup + * + * @param[in] count : Number of retries until both PLLs are locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 1 = PLL1 failed to successfully lock in "count" tries 2 = PLL2 failed to + * successfully lock in "count" tries 3 = Neither PLL1 nor PLL2 successfully locked in + * "count" tries 4 = The workaround function was not able to disable at least one of the + * PLLs. The most likely reason is that a PLL is already being used as a clock source. + * This can be caused by the workaround function being called from the wrong place in the + * code. + */ +uint32 _errata_SSWF021_45_both_plls( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while( ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + || ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) == 0U ) ) ) + { + /* Wait */ + } + + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + + if( failCode == 0U ) + { + break; + } + } + + /* To avoid MISRA violation 382S + * (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count) + * @brief This handles the errata for PLL1. This function is called in device startup + * + * @param[in] count : Number of retries until both PLL1 is locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 1 = PLL1 failed to successfully lock in "count" tries 2 = PLL2 failed to + * successfully lock in "count" tries 3 = Neither PLL1 nor PLL2 successfully locked in + * "count" tries 4 = The workaround function was not able to disable at least one of the + * PLLs. The most likely reason is that a PLL is already being used as a clock source. + * This can be caused by the workaround function being called from the wrong place in the + * code. + */ +uint32 _errata_SSWF021_45_pll1( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1; + + /* Check for PLL1 valid or PLL1 slip*/ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + { + /* Wait */ + } + + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + + if( failCode == 0U ) + { + break; + } + } + + /* To avoid MISRA violation 382S + * (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count) + * @brief This handles the errata for PLL2. This function is called in device startup + * + * @param[in] count : Number of retries until PLL2 is locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 1 = PLL1 failed to successfully lock in "count" tries 2 = PLL2 failed to + * successfully lock in "count" tries 3 = Neither PLL1 nor PLL2 successfully locked in + * "count" tries 4 = The workaround function was not able to disable at least one of the + * PLLs. The most likely reason is that a PLL is already being used as a clock source. + * This can be caused by the workaround function being called from the wrong place in the + * code. + */ +uint32 _errata_SSWF021_45_pll2( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL2; + + /* Check for PLL2 valid or PLL2 slip */ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) == 0U ) ) + { + /* Wait */ + } + + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + + if( failCode == 0U ) + { + break; + } + } + + /* To avoid MISRA violation 382S + * (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32 check_frequency(uint32 cnt1_clksrc) + * @brief This function checks for the PLL frequency. + * + * @param[in] cnt1_clksrc : Clock source for Counter1 + * 0U - PLL1 (clock source 0) + * 1U - PLL2 (clock source 1) + * + * @return DCC Error status + * 0 - DCC error has not occurred + * 1 - DCC error has occurred + */ +static uint32 check_frequency( uint32 cnt1_clksrc ) +{ + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0x5U | /** Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + dccREG1->STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) cnt1_clksrc; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + + while( dccREG1->STAT == 0U ) + { + /* Wait */ + } + + return ( dccREG1->STAT & 0x01U ); +} + +/** @fn uint32 disable_plls(uint32 plls) + * @brief This function disables plls and clears the respective ESM flags. + * + * @param[in] plls : Clock source for Counter1 + * 2U - PLL1 + * 40U - PLL2 + * + * @return failCode + * 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 4 = The workaround function was not able to disable at least one of the PLLs. + * The most likely reason is that a PLL is already being used as a clock source. This can + * be caused by the workaround function being called from the wrong place in the code. + */ +static uint32 disable_plls( uint32 plls ) +{ + uint32 timeout, failCode; + + systemREG1->CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout--; + + while( ( ( systemREG1->CSVSTAT & ( plls ) ) != 0U ) && ( timeout != 0U ) ) + { + /* Clear ESM and GLBSTAT PLL slip flags */ + systemREG1->GBLSTAT = 0x00000300U; + + if( ( plls & SYS_CLKSRC_PLL1 ) == SYS_CLKSRC_PLL1 ) + { + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + } + + if( ( plls & SYS_CLKSRC_PLL2 ) == SYS_CLKSRC_PLL2 ) + { + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + } + + timeout--; + /* Wait */ + } + + if( timeout == 0U ) + { + failCode = 4U; + } + else + { + failCode = 0U; + } + + return failCode; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/esm.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/esm.c new file mode 100644 index 00000000000..1e4ae3214d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/esm.c @@ -0,0 +1,792 @@ +/** @file esm.c + * @brief Esm Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the Esm driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "esm.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void esmInit(void) + * @brief Initializes Esm Driver + * + * This function initializes the Esm driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ESM_SourceId_001 */ +/* DesignId : ESM_DesignId_001 */ +/* Requirements : HL_SR4 */ +void esmInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Disable error pin channels */ + esmREG->DEPAPR1 = 0xFFFFFFFFU; + esmREG->IEPCR4 = 0xFFFFFFFFU; + + /** - Disable interrupts */ + esmREG->IECR1 = 0xFFFFFFFFU; + esmREG->IECR4 = 0xFFFFFFFFU; + + /** - Clear error status flags */ + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SSR2 = 0xFFFFFFFFU; + esmREG->SR1[ 2U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + + /** - Setup LPC preload */ + esmREG->LTCPR = 16384U - 1U; + + /** - Reset error pin */ + if( esmREG->EPSR == 0U ) + { + esmREG->EKR = 0x00000005U; + } + else + { + esmREG->EKR = 0x00000000U; + } + + /** - Clear interrupt level */ + esmREG->ILCR1 = 0xFFFFFFFFU; + esmREG->ILCR4 = 0xFFFFFFFFU; + + /** - Set interrupt level */ + esmREG->ILSR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable error pin channels */ + esmREG->EEPAPR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable interrupts */ + esmREG->IESR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn uint32 esmError(void) + * @brief Return Error status + * + * @return The error status + * + * Returns the error status. + */ +/* SourceId : ESM_SourceId_002 */ +/* DesignId : ESM_DesignId_002 */ +/* Requirements : HL_SR5 */ +uint32 esmError( void ) +{ + uint32 status; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + status = esmREG->EPSR; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_003 */ +/* DesignId : ESM_DesignId_003 */ +/* Requirements : HL_SR6 */ +void esmEnableError( uint64 channels ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + esmREG->IEPSR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->EEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_004 */ +/* DesignId : ESM_DesignId_004 */ +/* Requirements : HL_SR7 */ +void esmDisableError( uint64 channels ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + esmREG->IEPCR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->DEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/** @fn void esmTriggerErrorPinReset(void) + * @brief Trigger error pin reset and switch back to normal operation + * + * Trigger error pin reset and switch back to normal operation. + */ +/* SourceId : ESM_SourceId_005 */ +/* DesignId : ESM_DesignId_005 */ +/* Requirements : HL_SR8 */ +void esmTriggerErrorPinReset( void ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + esmREG->EKR = 5U; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn void esmActivateNormalOperation(void) + * @brief Activate normal operation + * + * Activates normal operation mode. + */ +/* SourceId : ESM_SourceId_006 */ +/* DesignId : ESM_DesignId_006 */ +/* Requirements : HL_SR9 */ +void esmActivateNormalOperation( void ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + esmREG->EKR = 0U; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_007 */ +/* DesignId : ESM_DesignId_007 */ +/* Requirements : HL_SR10 */ +void esmEnableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + esmREG->IESR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IESR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void esmDisableInterrupt(uint64 channels) + * @brief Disable Group 1 Channels Interrupts + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_008 */ +/* DesignId : ESM_DesignId_008 */ +/* Requirements : HL_SR11 */ +void esmDisableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + esmREG->IECR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IECR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_009 */ +/* DesignId : ESM_DesignId_009 */ +/* Requirements : HL_SR12 */ +void esmSetInterruptLevel( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + esmREG->ILCR4 = ( uint32 ) ( ( ( channels & ( ~flags ) ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILSR4 = ( uint32 ) ( ( ( channels & flags ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILCR1 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR1 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatus(uint32 group, uint64 channels) + * @brief Clear Group error status + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_010 */ +/* DesignId : ESM_DesignId_010 */ +/* Requirements : HL_SR13 */ +void esmClearStatus( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + esmREG->SR1[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + if( group == 0U ) + { + esmREG->SR4[ group ] = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + } + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatusBuffer(uint64 channels) + * @brief Clear Group 2 error status buffer + * + * @param[in] channels - Channel mask + * + * Clear Group 2 error status buffer. + */ +/* SourceId : ESM_SourceId_011 */ +/* DesignId : ESM_DesignId_011 */ +/* Requirements : HL_SR14 */ +void esmClearStatusBuffer( uint64 channels ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + esmREG->SSR2 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void esmSetCounterPreloadValue(uint32 value) + * @brief Set counter preload value + * + * @param[in] value - Counter preload value + * + * Set counter preload value. + */ +/* SourceId : ESM_SourceId_012 */ +/* DesignId : ESM_DesignId_012 */ +/* Requirements : HL_SR15 */ +void esmSetCounterPreloadValue( uint32 value ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + esmREG->LTCPR = value & 0xC000U; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/** @fn uint64 esmGetStatus(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_013 */ +/* DesignId : ESM_DesignId_013 */ +/* Requirements : HL_SR16 */ +uint64 esmGetStatus( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + + if( group == 0U ) + { + ESM_ESTATUS4 = esmREG->SR4[ group ]; + } + else + { + ESM_ESTATUS4 = 0U; + } + + ESM_ESTATUS1 = esmREG->SR1[ group ]; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + status = ( ( ( uint64 ) ( ESM_ESTATUS4 ) << 32U ) | ( uint64 ) ESM_ESTATUS1 ) + & channels; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusBuffer(uint64 channels) + * @brief Return Group 2 channel x Error status buffer + * + * @param[in] channels - Error Channels + * + * @return The channels status + * + * Returns the group 2 buffered status of selected channels. + */ +/* SourceId : ESM_SourceId_014 */ +/* DesignId : ESM_DesignId_014 */ +/* Requirements : HL_SR17 */ +uint64 esmGetStatusBuffer( uint64 channels ) +{ + uint64 status; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + status = ( ( uint64 ) esmREG->SSR2 ) & channels; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmEnterSelfTest(void) + * @brief Return ESM Self test status + * + * @return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_015 */ +/* DesignId : ESM_DesignId_015 */ +/* Requirements : HL_SR19 */ +esmSelfTestFlag_t esmEnterSelfTest( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + uint32 errPinStat = esmREG->EPSR & 0x1U; + uint32 esmKeyReg = esmREG->EKR; + + if( ( errPinStat == 0x0U ) && ( esmKeyReg == 0x0U ) ) + { + status = esmSelfTest_NotStarted; + } + else + { + esmREG->EKR = 0xAU; + status = esmSelfTest_Active; + + if( ( esmREG->EPSR & 0x1U ) != 0x0U ) + { + status = esmSelfTest_Failed; + } + + esmREG->EKR = 0x5U; + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmSelfTestStatus(void) + * @brief Return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_016 */ +/* DesignId : ESM_DesignId_016 */ +/* Requirements : HL_SR18 */ +esmSelfTestFlag_t esmSelfTestStatus( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + if( ( esmREG->EPSR & 0x1U ) == 0x0U ) + { + if( esmREG->EKR == 0x5U ) + { + status = esmSelfTest_Active; + } + else + { + status = esmSelfTest_Failed; + } + } + else + { + status = esmSelfTest_Passed; + } + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ESM_SourceId_017 */ +/* DesignId : ESM_DesignId_017 */ +/* Requirements : HL_SR20, HL_SR24 */ +void esmGetConfigValue( esm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE; + config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE; + config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE; + config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE; + config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE; + config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1; + config_reg->CONFIG_IESR1 = esmREG->IESR1; + config_reg->CONFIG_ILSR1 = esmREG->ILSR1; + config_reg->CONFIG_LTCPR = esmREG->LTCPR; + config_reg->CONFIG_EKR = esmREG->EKR; + config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4; + config_reg->CONFIG_IESR4 = esmREG->IESR4; + config_reg->CONFIG_ILSR4 = esmREG->ILSR4; + } +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + +/** @fn void esmHighInterrupt(void) + * @brief High Level Interrupt for ESM + */ +/* SourceId : ESM_SourceId_018 */ +/* DesignId : ESM_DesignId_018 */ +/* Requirements : HL_SR21, HL_SR22 */ +void esmHighInterrupt( void ) +{ + uint32 vec = esmREG->IOFFHR - 1U; + + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( vec ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( vec - 32U ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( vec - 32U ); + } + else + { + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/gio.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/gio.c new file mode 100644 index 00000000000..253fbd7df65 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/gio.c @@ -0,0 +1,505 @@ +/** @file gio.c + * @brief GIO Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "gio.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void gioInit(void) + * @brief Initializes the GIO Driver + * + * This function initializes the GIO module and set the GIO ports + * to the initial values. + */ +/* SourceId : GIO_SourceId_001 */ +/* DesignId : GIO_DesignId_001 */ +/* Requirements : HL_SR26 */ +void gioInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** bring GIO module out of reset */ + gioREG->GCR0 = 1U; + gioREG->ENACLR = 0xFFU; + gioREG->LVLCLR = 0xFFU; + + /** @b initialize @b Port @b A */ + + /** - Port A output values */ + gioPORTA->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A direction */ + gioPORTA->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A open drain enable */ + gioPORTA->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown selection */ + gioPORTA->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown enable*/ + gioPORTA->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** @b initialize @b Port @b B */ + + /** - Port B output values */ + gioPORTB->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B direction */ + gioPORTB->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B open drain enable */ + gioPORTB->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown selection */ + gioPORTB->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown enable*/ + gioPORTB->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b interrupts */ + + /** - interrupt polarity */ + gioREG->POL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - interrupt level */ + gioREG->LVLSET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - clear all pending interrupts */ + gioREG->FLG = 0xFFU; + + /** - enable interrupts */ + gioREG->ENASET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir) + * @brief Set Port Direction + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] dir value to write to DIR register + * + * Set the direction of GIO pins at runtime. + */ +/* SourceId : GIO_SourceId_002 */ +/* DesignId : GIO_DesignId_002 */ +/* Requirements : HL_SR27 */ +void gioSetDirection( gioPORT_t * port, uint32 dir ) +{ + port->DIR = dir; +} + +/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * @param[in] value binary value to write to bit + * + * Writes a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_003 */ +/* DesignId : GIO_DesignId_003 */ +/* Requirements : HL_SR28 */ +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( value != 0U ) + { + port->DSET = ( uint32 ) 1U << bit; + } + else + { + port->DCLR = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioSetPort(gioPORT_t *port, uint32 value) + * @brief Write Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] value value to write to port + * + * Writes a value to all pin of a given GIO port + */ +/* SourceId : GIO_SourceId_004 */ +/* DesignId : GIO_DesignId_004 */ +/* Requirements : HL_SR29 */ +void gioSetPort( gioPORT_t * port, uint32 value ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + port->DOUT = value; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit) + * @brief Read Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Reads a the current value from the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_005 */ +/* DesignId : GIO_DesignId_005 */ +/* Requirements : HL_SR30 */ +uint32 gioGetBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return ( port->DIN >> bit ) & 1U; +} + +/** @fn uint32 gioGetPort(gioPORT_t *port) + * @brief Read Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * + * Reads a the current value of a given GIO port + */ +/* SourceId : GIO_SourceId_006 */ +/* DesignId : GIO_DesignId_006 */ +/* Requirements : HL_SR31 */ +uint32 gioGetPort( gioPORT_t * port ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return port->DIN; +} + +/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Toggle a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_007 */ +/* DesignId : GIO_DesignId_007 */ +/* Requirements : HL_SR32 */ +void gioToggleBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( port->DIN & ( uint32 ) ( ( uint32 ) 1U << bit ) ) != 0U ) + { + port->DCLR = ( uint32 ) 1U << bit; + } + else + { + port->DSET = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioEnableNotification(uint32 bit) + * @brief Enable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Enables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_008 */ +/* DesignId : GIO_DesignId_008 */ +/* Requirements : HL_SR33 */ +void gioEnableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENASET = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENASET = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioDisableNotification(uint32 bit) + * @brief Disable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Disables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_009 */ +/* DesignId : GIO_DesignId_009 */ +/* Requirements : HL_SR34 */ +void gioDisableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENACLR = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENACLR = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : GIO_SourceId_010 */ +/* DesignId : GIO_DesignId_010 */ +/* Requirements : HL_SR37 */ +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_INTDET = GIO_INTDET_CONFIGVALUE; + config_reg->CONFIG_POL = GIO_POL_CONFIGVALUE; + config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE; + config_reg->CONFIG_LVLSET = GIO_LVLSET_CONFIGVALUE; + + config_reg->CONFIG_PORTADIR = GIO_PORTADIR_CONFIGVALUE; + config_reg->CONFIG_PORTAPDR = GIO_PORTAPDR_CONFIGVALUE; + config_reg->CONFIG_PORTAPSL = GIO_PORTAPSL_CONFIGVALUE; + config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE; + + config_reg->CONFIG_PORTBDIR = GIO_PORTBDIR_CONFIGVALUE; + config_reg->CONFIG_PORTBPDR = GIO_PORTBPDR_CONFIGVALUE; + config_reg->CONFIG_PORTBPSL = GIO_PORTBPSL_CONFIGVALUE; + config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_INTDET = gioREG->INTDET; + config_reg->CONFIG_POL = gioREG->POL; + config_reg->CONFIG_INTENASET = gioREG->ENASET; + config_reg->CONFIG_LVLSET = gioREG->LVLSET; + + config_reg->CONFIG_PORTADIR = gioPORTA->DIR; + config_reg->CONFIG_PORTAPDR = gioPORTA->PDR; + config_reg->CONFIG_PORTAPSL = gioPORTA->PSL; + config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PORTBDIR = gioPORTB->DIR; + config_reg->CONFIG_PORTBPDR = gioPORTB->PDR; + config_reg->CONFIG_PORTBPSL = gioPORTB->PSL; + config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS; + } +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/het.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/het.c new file mode 100644 index 00000000000..e25b353dada --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/het.c @@ -0,0 +1,3000 @@ +/** @file het.c + * @brief HET Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "het.h" +#include "sys_vim.h" +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Global variables */ + +static const uint32 s_het1pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +static const uint32 s_het2pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het1PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het1PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het2PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het2PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 55296U, + /* Reserved */ + 0x00000000U }, + + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 109952U, + /* Reserved */ + 0x00000000U }, + + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/** @fn void hetInit(void) + * @brief Initializes the het Driver + * + * This function initializes the het 1 module. + */ +/* SourceId : HET_SourceId_001 */ +/* DesignId : HET_DesignId_001 */ +/* Requirements : HL_SR363 */ +void hetInit( void ) +{ + /** @b initialize @b HET */ + + /** - Set HET pins default output value */ + hetREG1 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG1->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG1->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG1->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG1->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG1->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG1->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG1->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG1->PFR = ( uint32 ) ( ( uint32 ) 7U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG1->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM1, + ( const void * ) het1PROGRAM, + sizeof( het1PROGRAM ) ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + * + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG1->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG1->INTENAC = 0xFFFFFFFFU; + hetREG1->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG1->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @b initialize @b HET 2 */ + + /** - Set HET pins default output value */ + hetREG2 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG2->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG2->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG2->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG2->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG2->HRSH = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000008U + | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U + | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG2->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG2->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 7U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG2->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Release from reset */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM2, + ( const void * ) het2PROGRAM, + sizeof( het2PROGRAM ) ); + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 7U << 8U ) | ( ( uint32 ) 0U ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + * + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG2->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG2->INTENAC = 0xFFFFFFFFU; + hetREG2->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG2->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ +} + +/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Start pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Start the given pwm signal + */ +/* SourceId : HET_SourceId_002 */ +/* DesignId : HET_DesignId_002 */ +/* Requirements : HL_SR364 */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control |= 0x00400000U; +} + +/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Stop pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Stop the given pwm signal + */ +/* SourceId : HET_SourceId_003 */ +/* DesignId : HET_DesignId_003 */ +/* Requirements : HL_SR365 */ +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control &= ~( uint32 ) 0x00400000U; +} + +/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty) + * @brief Set duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] pwmDuty duty cycle in %. + * + * Sets a new duty cycle on the given pwm signal + */ +/* SourceId : HET_SourceId_004 */ +/* DesignId : HET_DesignId_004 */ +/* Requirements : HL_SR366 */ +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + uint32 pwmPeriod = hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U; + + pwmPeriod = pwmPeriod >> 7U; + + if( hetRAM == hetRAM1 ) + { + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + + if( pwmDuty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( pwmDuty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data = ( ( ( pwmPeriod * pwmDuty ) / 100U ) + << 7U ) + + 128U; +} + +/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) + * @brief Set period + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Sets a new pwm signal + */ +/* SourceId : HET_SourceId_005 */ +/* DesignId : HET_DesignId_005 */ +/* Requirements : HL_SR367 */ +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + float64 pwmPeriod = 0.0F; + + if( hetRAM == hetRAM1 ) + { + pwmPeriod = ( signal.period * 1000.0F ) / 1163.636F; + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPeriod = ( signal.period * 1000.0F ) / 1163.636F; + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + + if( signal.duty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( signal.duty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Data = ( ( ( ( uint32 ) pwmPeriod * signal.duty ) / 100U ) << 7U ) + 128U; + hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data = ( ( uint32 ) pwmPeriod << 7U ) + - 128U; +} + +/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) + * @brief Get duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given pwm signal. + */ +/* SourceId : HET_SourceId_006 */ +/* DesignId : HET_DesignId_006 */ +/* Requirements : HL_SR368 */ +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data - 128U ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 1163.636F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 1163.636F ) / 1000.0F; + } +} + +/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_007 */ +/* DesignId : HET_DesignId_007 */ +/* Requirements : HL_SR369 */ +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->FLG = notification << ( pwm << 1U ); + hetREG->INTENAS = notification << ( pwm << 1U ); +} + +/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_008 */ +/* DesignId : HET_DesignId_008 */ +/* Requirements : HL_SR370 */ +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->INTENAC = notification << ( pwm << 1U ); +} + +/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Resets edge counter to 0 + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Reset edge counter to 0. + */ +/* SourceId : HET_SourceId_009 */ +/* DesignId : HET_DesignId_009 */ +/* Requirements : HL_SR372 */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + hetRAM->Instruction[ edge + 17U ].Data = 0U; +} + +/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Get current edge counter value + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Gets current edge counter value. + */ +/* SourceId : HET_SourceId_010 */ +/* DesignId : HET_DesignId_010 */ +/* Requirements : HL_SR373 */ +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + return hetRAM->Instruction[ edge + 17U ].Data >> 7U; +} + +/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_011 */ +/* DesignId : HET_DesignId_011 */ +/* Requirements : HL_SR374 */ +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->FLG = ( uint32 ) 0x20000U << edge; + hetREG->INTENAS = ( uint32 ) 0x20000U << edge; +} + +/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_012 */ +/* DesignId : HET_DesignId_012 */ +/* Requirements : HL_SR375 */ +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->INTENAC = ( uint32 ) 0x20000U << edge; +} + +/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal) + * @brief Get capture signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] cap captured signal: + * - cap0: Captured signal 0 + * - cap1: Captured signal 1 + * - cap2: Captured signal 2 + * - cap3: Captured signal 3 + * - cap4: Captured signal 4 + * - cap5: Captured signal 5 + * - cap6: Captured signal 6 + * - cap7: Captured signal 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given capture signal. + */ +/* SourceId : HET_SourceId_013 */ +/* DesignId : HET_DesignId_013 */ +/* Requirements : HL_SR377 */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( cap << 1U ) + 25U ].Data ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( cap << 1U ) + 26U ].Data ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 1163.636F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 1163.636F ) / 1000.0F; + } +} + +/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Resets timestamp + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * + * Resets loop count based timestamp. + */ +/* SourceId : HET_SourceId_014 */ +/* DesignId : HET_DesignId_014 */ +/* Requirements : HL_SR378 */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ) +{ + hetRAM->Instruction[ 0U ].Data = 0U; +} + +/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Returns timestamp + * + * Returns loop count based timestamp. + */ +/* SourceId : HET_SourceId_015 */ +/* DesignId : HET_DesignId_015 */ +/* Requirements : HL_SR379 */ +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ) +{ + return hetRAM->Instruction[ 57U ].Data; +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_016 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : HL_SR379 */ +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET1_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET1_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET1_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET1_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET1_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET1_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET1_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET1_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET1_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET1_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET1_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG1->GCR; + config_reg->CONFIG_PFR = hetREG1->PFR; + config_reg->CONFIG_INTENAS = hetREG1->INTENAS; + config_reg->CONFIG_INTENAC = hetREG1->INTENAC; + config_reg->CONFIG_PRY = hetREG1->PRY; + config_reg->CONFIG_AND = hetREG1->AND; + config_reg->CONFIG_HRSH = hetREG1->HRSH; + config_reg->CONFIG_XOR = hetREG1->XOR; + config_reg->CONFIG_DIR = hetREG1->DIR; + config_reg->CONFIG_PDR = hetREG1->PDR; + config_reg->CONFIG_PULDIS = hetREG1->PULDIS; + config_reg->CONFIG_PSL = hetREG1->PSL; + config_reg->CONFIG_PCR = hetREG1->PCR; + } +} + +/** @fn void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_017 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : HL_SR379 */ +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET2_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET2_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET2_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET2_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET2_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET2_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET2_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET2_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET2_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET2_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET2_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET2_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET2_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG2->GCR; + config_reg->CONFIG_PFR = hetREG2->PFR; + config_reg->CONFIG_INTENAS = hetREG2->INTENAS; + config_reg->CONFIG_INTENAC = hetREG2->INTENAC; + config_reg->CONFIG_PRY = hetREG2->PRY; + config_reg->CONFIG_AND = hetREG2->AND; + config_reg->CONFIG_HRSH = hetREG2->HRSH; + config_reg->CONFIG_XOR = hetREG2->XOR; + config_reg->CONFIG_DIR = hetREG2->DIR; + config_reg->CONFIG_PDR = hetREG2->PDR; + config_reg->CONFIG_PULDIS = hetREG2->PULDIS; + config_reg->CONFIG_PSL = hetREG2->PSL; + config_reg->CONFIG_PCR = hetREG2->PCR; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/lin.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/lin.c new file mode 100644 index 00000000000..6cb4b0b9bb4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/lin.c @@ -0,0 +1,732 @@ +/** @file lin.c + * @brief LIN Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "lin.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void linInit(void) + * @brief Initializes the lin Driver + * + * This function initializes the lin module. + */ +/* SourceId : LIN_SourceId_001 */ +/* DesignId : LIN_DesignId_001 */ +/* Requirements : HL_SR253 */ +void linInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module as master + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG->MBRSR = ( uint32 ) 4954U; + + /** - Setup baud rate prescaler */ + linREG->BRS = ( uint32 ) 343U; + + /** - Setup RX and TX reception masks */ + linREG->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG->FORMAT = ( ( linREG->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void linSetFunctional(linBASE_t *lin, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] lin - lin module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCFUN register at runtime, this allows to + * dynamically change the functionality of the LIN pins between functional + * and GIO mode. + */ +/* SourceId : LIN_SourceId_002 */ +/* DesignId : LIN_DesignId_002 */ +/* Requirements : HL_SR254 */ +void linSetFunctional( linBASE_t * lin, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + lin->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void linSendHeader(linBASE_t *lin, uint8 identifier) + * @brief Send lin header. + * @param[in] lin - lin module base address + * @param[in] identifier - lin header id + * + * Send lin header including sync break field, sync field and identifier. + */ +/* SourceId : LIN_SourceId_003 */ +/* DesignId : LIN_DesignId_003 */ +/* Requirements : HL_SR255 */ +void linSendHeader( linBASE_t * lin, uint8 identifier ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + lin->ID = ( ( lin->ID & 0xFFFFFF00U ) | ( uint32 ) identifier ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void linSendWakupSignal(linBASE_t *lin) + * @brief Send lin wakeup signal. + * @param[in] lin - lin module base address + * + * Send lin wakeup signal to terminate the sleep mode of any lin node connected to the + * BUS. + */ +/* SourceId : LIN_SourceId_004 */ +/* DesignId : LIN_DesignId_004 */ +/* Requirements : HL_SR256 */ +void linSendWakupSignal( linBASE_t * lin ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + lin->TDx[ 0U ] = 0xF0U; + lin->GCR2 |= 0x00000100U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void linEnterSleep(linBASE_t *lin) + * @brief Take Module to Sleep. + * @param[in] lin - lin module base address + * + * Application must call this function to take Module to Sleep when Sleep command is + * received. This function can also be called to forcefully enter Sleep when no activity + * on BUS. + */ +/* SourceId : LIN_SourceId_005 */ +/* DesignId : LIN_DesignId_005 */ +/* Requirements : HL_SR257 */ +void linEnterSleep( linBASE_t * lin ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + lin->GCR2 |= 0x00000001U; + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void linSoftwareReset(linBASE_t *lin) + * @brief Perform software reset. + * @param[in] lin - lin module base address + * + * Perform software reset of lin module. + * This function will reset the lin state machine and clear all pending flags. + * It is required to call this function after a wakeup signal has been sent. + */ +/* SourceId : LIN_SourceId_006 */ +/* DesignId : LIN_DesignId_006 */ +/* Requirements : HL_SR258 */ +void linSoftwareReset( linBASE_t * lin ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + lin->GCR1 &= ~( uint32 ) ( 0x00000080U ); + lin->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn uint32 linIsTxReady(linBASE_t *lin) + * @brief Check if Tx buffer empty + * @param[in] lin - lin module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +/* SourceId : LIN_SourceId_007 */ +/* DesignId : LIN_DesignId_007 */ +/* Requirements : HL_SR259 */ +uint32 linIsTxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return lin->FLR & LIN_TX_READY; +} + +/** @fn void linSetLength(linBASE_t *lin, uint32 length) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] length - number of data words in bytes. Range: 1-8. + * + * Send data response length in bytes. + */ +/* SourceId : LIN_SourceId_008 */ +/* DesignId : LIN_DesignId_008 */ +/* Requirements : HL_SR260 */ +void linSetLength( linBASE_t * lin, uint32 length ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + lin->FORMAT = ( ( lin->FORMAT & 0xFFF8FFFFU ) | ( ( length - 1U ) << 16U ) ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void linSend(linBASE_t *lin, uint8 * data) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data'. + * The number of data to transmit must be set with 'linSetLength' before. + */ +/* SourceId : LIN_SourceId_009 */ +/* DesignId : LIN_DesignId_009 */ +/* Requirements : HL_SR261 */ +void linSend( linBASE_t * lin, uint8 * data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + uint8 * pData = data + length; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + lin->TDx[ length - i ] = *pData; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData--; + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn uint32 linIsRxReady(linBASE_t *lin) + * @brief Check if Rx buffer full + * @param[in] lin - lin module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +/* SourceId : LIN_SourceId_010 */ +/* DesignId : LIN_DesignId_010 */ +/* Requirements : HL_SR262 */ +uint32 linIsRxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return lin->FLR & LIN_RX_INT; +} + +/** @fn uint32 linTxRxError(linBASE_t *lin) + * @brief Return Tx and Rx Error flags + * @param[in] lin - lin module base address + * + * @return The Tx and Rx error flags + * + * Returns the bit, physical bus, checksum, inconsistent sync field, + * no response, framing, overrun, parity and timeout error flags. + * It also clears the error flags before returning. + */ +/* SourceId : LIN_SourceId_011 */ +/* DesignId : LIN_DesignId_011 */ +/* Requirements : HL_SR263 */ +uint32 linTxRxError( linBASE_t * lin ) +{ + uint32 status = lin->FLR + & ( LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT + | LIN_TOAWUS_INT | LIN_TO_INT ); + + lin->FLR = LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT | LIN_TOAWUS_INT + | LIN_TO_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint32 linGetIdentifier(linBASE_t *lin) + * @brief Get last received identifier + * @param[in] lin - lin module base address + * + * @return Identifier + * + * Read last received identifier. + */ +/* SourceId : LIN_SourceId_012 */ +/* DesignId : LIN_DesignId_012 */ +/* Requirements : HL_SR262 */ +uint32 linGetIdentifier( linBASE_t * lin ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + return ( uint32 ) ( ( uint32 ) ( lin->ID & 0x00FF0000U ) >> 16U ); +} + +/** @fn void linGetData(linBASE_t *lin, uint8 * const data) + * @brief Read received data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data buffer + * + * Read a block of bytes and place it into the data buffer pointed to by 'data'. + */ +/* SourceId : LIN_SourceId_013 */ +/* DesignId : LIN_DesignId_013 */ +/* Requirements : HL_SR265 */ +void linGetData( linBASE_t * lin, uint8 * const data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + uint8 * pData = data; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *pData = lin->RDx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData++; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +/* SourceId : LIN_SourceId_014 */ +/* DesignId : LIN_DesignId_016 */ +/* Requirements : HL_SR268 */ +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + lin->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + lin->IODFTCTRL = ( ( uint32 ) ( 0x00000A00U ) + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn void linDisableLoopback(linBASE_t *lin) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * + * This function disable the Loopback mode. + */ +/* SourceId : LIN_SourceId_015 */ +/* DesignId : LIN_DesignId_017 */ +/* Requirements : HL_SR269 */ +void linDisableLoopback( linBASE_t * lin ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + lin->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/** @fn linEnableNotification(linBASE_t *lin, uint32 flags) + * @brief Enable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +/* SourceId : LIN_SourceId_016 */ +/* DesignId : LIN_DesignId_014 */ +/* Requirements : HL_SR266 */ +void linEnableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + lin->SETINT = flags; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/** @fn linDisableNotification(linBASE_t *lin, uint32 flags) + * @brief Disable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be or'ed value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +/* SourceId : LIN_SourceId_017 */ +/* DesignId : LIN_DesignId_015 */ +/* Requirements : HL_SR267 */ +void linDisableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + lin->CLEARINT = flags; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/** @fn void linGetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : LIN_SourceId_018 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : HL_SR272 */ +void linGetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR0 = linREG->GCR0; + config_reg->CONFIG_GCR1 = linREG->GCR1; + config_reg->CONFIG_GCR2 = linREG->GCR2; + config_reg->CONFIG_SETINT = linREG->SETINT; + config_reg->CONFIG_SETINTLVL = linREG->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG->FORMAT; + config_reg->CONFIG_BRSR = linREG->BRS; + config_reg->CONFIG_FUN = linREG->PIO0; + config_reg->CONFIG_DIR = linREG->PIO1; + config_reg->CONFIG_ODR = linREG->PIO6; + config_reg->CONFIG_PD = linREG->PIO7; + config_reg->CONFIG_PSL = linREG->PIO8; + config_reg->CONFIG_COMP = linREG->COMP; + config_reg->CONFIG_MASK = linREG->MASK; + config_reg->CONFIG_MBRSR = linREG->MBRSR; + } +} + +/** @fn uint32 linGetStatusFlag(linBASE_t *lin) + * @brief Get LIN status register value + * @param[in] lin - lin module base address + * + * @return Status Flag register content + * + * Read current Status Flag register. + */ +/* SourceId : LIN_SourceId_021 */ +/* DesignId : LIN_DesignId_020 */ +/* Requirements : HL_SR544 */ +uint32 linGetStatusFlag( linBASE_t * lin ) +{ + return lin->FLR; +} + +/** @fn void linClearStatusFlag(linBASE_t *lin, uint32 flags) + * @brief Clear LIN status register + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be or'ed value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect, + * LIN_BUSY_FLAG - Bus Busy Flag, + * LIN_TXEMPTY_INT - Transmit Empty Flag + * + * Clear Status Flags passed as parameter. + */ +/* SourceId : LIN_SourceId_022 */ +/* DesignId : LIN_DesignId_021 */ +/* Requirements : HL_SR545 */ +void linClearStatusFlag( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + lin->FLR = flags; + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/mdio.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/mdio.c new file mode 100644 index 00000000000..fcf74e57a63 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/mdio.c @@ -0,0 +1,254 @@ +/** + * \file mdio.c + * + * \brief MDIO APIs. + * + * This file contains the device abstraction layer APIs for MDIO. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "hw_reg_access.h" +#include "mdio.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define PHY_REG_MASK ( 0x1FU ) +#define PHY_ADDR_MASK ( 0x1FU ) +#define PHY_DATA_MASK ( 0xFFFFU ) +#define PHY_REG_SHIFT ( 21U ) +#define PHY_ADDR_SHIFT ( 16U ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ + +/** + * \brief Reads a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param dataPtr Pointer where the read value shall be written. + * + * \return status of the read \n + * TRUE - read is successful.\n + * FALSE - read is not acknowledged properly. + * + **/ +/* SourceId : ETH_SourceId_059 */ +/* DesignId : ETH_DesignId_059*/ +/* Requirements : HL_ETH_SR41, HL_ETH_SR45 */ +boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ) +{ + boolean retVal = FALSE; + + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( ( ( uint32 ) MDIO_USERACCESS0_READ ) + | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) ); + + /* wait for command completion */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + /* Store the data if the read is acknowledged */ + if( ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) & MDIO_USERACCESS0_ACK ) + == MDIO_USERACCESS0_ACK ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Output is a 16 bit Value to be stored - + * Advisory as per MISRA" */ + *dataPtr = ( uint16 ) ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) + & PHY_DATA_MASK ); + retVal = TRUE; + } + + return retVal; +} + +/** + * \brief Writes a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param RegVal Value to be written. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_058 */ +/* DesignId : ETH_DesignId_058*/ +/* Requirements : HL_ETH_SR41 */ +void MDIOPhyRegWrite( uint32 baseAddr, uint32 phyAddr, uint32 regNum, uint16 RegVal ) +{ + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( MDIO_USERACCESS0_WRITE | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) + | RegVal ); + + /* wait for command completion*/ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ +} + +/** + * \brief Reads the alive status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * is alive. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO alive register state + * + **/ +/* SourceId : ETH_SourceId_062 */ +/* DesignId : ETH_DesignId_062*/ +/* Requirements : HL_ETH_SR42 */ +uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_ALIVE ) ); +} + +/** + * \brief Reads the link status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * link is active. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO link register state + * + **/ +/* SourceId : ETH_SourceId_061 */ +/* DesignId : ETH_DesignId_061*/ +/* Requirements : HL_ETH_SR42 */ +uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_LINK ) ); +} + +/** + * \brief Initializes the MDIO peripheral. This enables the MDIO state + * machine, uses standard pre-amble and set the clock divider value. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param mdioInputFreq The clock input to the MDIO module + * \param mdioOutputFreq The clock output required on the MDIO bus + * \return None + * + **/ +/* SourceId : ETH_SourceId_060 */ +/* DesignId : ETH_DesignId_060*/ +/* Requirements : HL_ETH_SR39 */ +void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ) +{ + uint32 clkDiv = ( mdioInputFreq / mdioOutputFreq ) - 1U; + + HWREG( baseAddr + MDIO_CONTROL ) = ( ( clkDiv & MDIO_CONTROL_CLKDIV ) + | MDIO_CONTROL_ENABLE | MDIO_CONTROL_PREAMBLE + | MDIO_CONTROL_FAULTENB ); +} + +/** + * \brief Function to enable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : HL_ETH_SR40 */ +void MDIOEnable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + | MDIO_CONTROL_ENABLE; +} + +/** + * \brief Function to disable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_057 */ +/* DesignId : ETH_DesignId_057*/ +/* Requirements : HL_ETH_SR40 */ +void MDIODisable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + & ( ~MDIO_CONTROL_ENABLE ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/mibspi.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/mibspi.c new file mode 100644 index 00000000000..740daee224f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/mibspi.c @@ -0,0 +1,2202 @@ +/** @file mibspi.c + * @brief MIBSPI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "mibspi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void mibspiInit(void) + * @brief Initializes the MIBSPI Driver + * + * This function initializes the MIBSPI module. + */ +/* SourceId : MIBSPI_SourceId_001 */ +/* DesignId : MIBSPI_DesignId_001 */ +/* Requirements : HL_SR153 */ +void mibspiInit( void ) +{ + uint32 i; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b MIBSPI1 */ + + /** bring MIBSPI out of reset */ + mibspiREG1->GCR0 = 0U; + mibspiREG1->GCR0 = 1U; + + /** enable MIBSPI1 multibuffered mode and enable buffer RAM */ + mibspiREG1->MIBSPIE = ( mibspiREG1->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI1 master mode and clock configuration */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI1 enable pin configuration */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG1->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG1->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG1->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG1->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG1->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG1->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG1->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG1->UERRCTRL = ( mibspiREG1->UERRCTRL & 0xFFFFFFF0U ) | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG1->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG1->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG1->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG1->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG1->LTGPEND = ( mibspiREG1->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + while( i < ( 8U - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif /* if ( 8U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 8U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif /* if ( 0U > 0U ) */ + } + + /** - set interrupt levels */ + mibspiREG1->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG1->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI1 @b Port */ + + /** - MIBSPI1 Port output values */ + mibspiREG1->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port direction */ + mibspiREG1->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port open drain enable */ + mibspiREG1->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown selection */ + mibspiREG1->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown enable*/ + mibspiREG1->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /* MIBSPI1 set all pins to functional */ + mibspiREG1->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - Finally start MIBSPI1 */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI3 */ + + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = ( mibspiREG3->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG3->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG3->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->UERRCTRL = ( mibspiREG3->UERRCTRL & 0xFFFFFFF0U ) | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG3->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG3->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG3->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + while( i < ( 8U - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif /* if ( 8U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 8U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif /* if ( 0U > 0U ) */ + } + + /** - set interrupt levels */ + mibspiREG3->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI5 */ + + /** bring MIBSPI out of reset */ + mibspiREG5->GCR0 = 0U; + mibspiREG5->GCR0 = 1U; + + /** enable MIBSPI5 multibuffered mode and enable buffer RAM */ + mibspiREG5->MIBSPIE = ( mibspiREG5->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI5 master mode and clock configuration */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI5 enable pin configuration */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG5->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG5->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG5->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG5->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG5->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG5->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG5->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG5->UERRCTRL = ( mibspiREG5->UERRCTRL & 0xFFFFFFF0U ) | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG5->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG5->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG5->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG5->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG5->LTGPEND = ( mibspiREG5->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + while( i < ( 8U - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif /* if ( 8U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 8U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif /* if ( 0U > 0U ) */ + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif /* if ( 0U > 1U ) */ + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif /* if ( 0U > 0U ) */ + } + + /** - set interrupt levels */ + mibspiREG5->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG5->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI5 @b Port */ + + /** - MIBSPI5 Port output values */ + mibspiREG5->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port direction */ + mibspiREG5->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port open drain enable */ + mibspiREG5->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown selection */ + mibspiREG5->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown enable*/ + mibspiREG5->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /* MIBSPI5 set all pins to functional */ + mibspiREG5->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - Finally start MIBSPI5 */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] mibspi - mibspi module base address + * @param[in] port - Value to write to PC0 register + * + * Change the value of the PC0 register at runtime, this allows to + * dynamically change the functionality of the MIBSPI pins between functional + * and GIO mode. + */ +/* SourceId : MIBSPI_SourceId_002 */ +/* DesignId : MIBSPI_DesignId_002 */ +/* Requirements : HL_SR154 */ +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + mibspi->PC0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Set Buffer Data + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] data - new data for transfer group + * + * This function updates the data for the specified transfer group, + * the length of the data must match the length of the transfer group. + */ +/* SourceId : MIBSPI_SourceId_003 */ +/* DesignId : MIBSPI_DesignId_003 */ +/* Requirements : HL_SR155 */ +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + mibspiRAM_t * ram = ( mibspi == mibspiREG1 ) + ? mibspiRAM1 + : ( ( mibspi == mibspiREG3 ) ? mibspiRAM3 : mibspiRAM5 ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + ram->tx[ start ].data = *data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + start++; + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Retrieves Buffer Data from receive buffer + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[out] data - pointer to data array + * + * @return error flags from data buffer, if there was a receive error on + * one of the buffers this will be reflected in the return value. + * + * This function transfers the data from the specified transfer group receive + * buffers to the data array, the length of the data must match the length + * of the transfer group. + */ +/* SourceId : MIBSPI_SourceId_004 */ +/* DesignId : MIBSPI_DesignId_004 */ +/* Requirements : HL_SR156 */ +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + mibspiRAM_t * ram = ( mibspi == mibspiREG1 ) + ? mibspiRAM1 + : ( ( mibspi == mibspiREG3 ) ? mibspiRAM3 : mibspiRAM5 ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + uint16 mibspiFlags = 0U; + uint32 ret; + + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + mibspiFlags |= ram->rx[ start ].flags; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *data = ram->rx[ start ].data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + start++; + } + + ret = ( ( uint32 ) mibspiFlags >> 8U ) & 0x5FU; + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return ret; +} + +/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) + * @brief Transmit Transfer Group + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * Initiates a transfer for the specified transfer group. + */ +/* SourceId : MIBSPI_SourceId_005 */ +/* DesignId : MIBSPI_DesignId_005 */ +/* Requirements : HL_SR157 */ +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + mibspi->TGCTRL[ group ] |= 0x80000000U; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) + * @brief Check for Transfer Group Ready + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * @return TRUE is transfer complete, otherwise FALSE. + * + * Checks to see if the transfer for the specified transfer group + * has finished. + */ +/* SourceId : MIBSPI_SourceId_006 */ +/* DesignId : MIBSPI_DesignId_006 */ +/* Requirements : HL_SR158 */ +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ) +{ + boolean status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( ( ( ( ( mibspi->TGINTFLG & 0xFFFF0000U ) >> 16U ) >> group ) & 1U ) == 1U ) + { + mibspi->TGINTFLG = ( mibspi->TGINTFLG & 0x0000FFFFU ) + | ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return ( status ); +} + +/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +/* SourceId : MIBSPI_SourceId_007 */ +/* DesignId : MIBSPI_DesignId_009 */ +/* Requirements : HL_SR161 */ +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + mibspi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + mibspi->IOLPKTSTCR = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * + * This function disable the Loopback mode. + */ +/* SourceId : MIBSPI_SourceId_008 */ +/* DesignId : MIBSPI_DesignId_010 */ +/* Requirements : HL_SR162 */ +void mibspiDisableLoopback( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + mibspi->IOLPKTSTCR = 0x00000500U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) + * @brief Set the Pmode for the selected Data Format register + * @param[in] mibspi - Mibspi module base address + * @param[in] Pmode - Mibspi Parellel mode + * PMODE_NORMAL + * PMODE_2_DATALINE + * PMODE_4_DATALINE + * PMODE_8_DATALINE + * @param[in] DFMT - Mibspi Data Format register + * DATA_FORMAT0 + * DATA_FORMAT1 + * DATA_FORMAT2 + * DATA_FORMAT3 + * + * This function sets the Pmode for the selected Data Format register. + */ +/* SourceId : MIBSPI_SourceId_009 */ +/* DesignId : MIBSPI_DesignId_011 */ +/* Requirements : HL_SR524 */ +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ) +{ + uint32 pmctrl_reg; + + /* Set the Pmode for the selected Data Format register */ + pmctrl_reg = ( mibspi->PMCTRL + & ( ~( uint32 ) ( ( uint32 ) 0xFFU << ( 8U * DFMT ) ) ) ); + mibspi->PMCTRL = ( pmctrl_reg + | ( uint32 ) ( ( uint32 ) Pmode << ( ( 8U * DFMT ) ) ) ); +} + +/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 + * level) + * @brief Enable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] level - Interrupt level + * + * This function enables the transfer group finished interrupt. + */ +/* SourceId : MIBSPI_SourceId_010 */ +/* DesignId : MIBSPI_DesignId_007 */ +/* Requirements : HL_SR159 */ +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( level != 0U ) + { + mibspi->TGITLVST = ( mibspi->TGITLVST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + else + { + mibspi->TGITLVCR = ( mibspi->TGITLVCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + + mibspi->TGITENST = ( mibspi->TGITENST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Disable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * This function disables the transfer group finished interrupt. + */ +/* SourceId : MIBSPI_SourceId_011 */ +/* DesignId : MIBSPI_DesignId_008 */ +/* Requirements : HL_SR160 */ +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + mibspi->TGITENCR = ( mibspi->TGITENCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : MIBSPI_SourceId_012 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI1_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI1_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI1_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI1_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI1_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI1_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI1_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI1_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI1_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI1_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI1_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI1_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI1_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI1_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI1_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI1_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI1_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI1_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI1_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI1_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI1_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI1_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI1_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI1_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG1->GCR1; + config_reg->CONFIG_INT0 = mibspiREG1->INT0; + config_reg->CONFIG_LVL = mibspiREG1->LVL; + config_reg->CONFIG_PCFUN = mibspiREG1->PC0; + config_reg->CONFIG_PCDIR = mibspiREG1->PC1; + config_reg->CONFIG_PCPDR = mibspiREG1->PC6; + config_reg->CONFIG_PCDIS = mibspiREG1->PC7; + config_reg->CONFIG_PCPSL = mibspiREG1->PC8; + config_reg->CONFIG_DELAY = mibspiREG1->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG1->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG1->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG1->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG1->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG1->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG1->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG1->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG1->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG1->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG1->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG1->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG1->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG1->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG1->TGCTRL[ 7U ]; + config_reg->CONFIG_UERRCTRL = mibspiREG1->UERRCTRL; + } +} + +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI3_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG3->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG3->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG3->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG3->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG3->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG3->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG3->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG3->TGCTRL[ 7U ]; + config_reg->CONFIG_UERRCTRL = mibspiREG3->UERRCTRL; + } +} + +/** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : MIBSPI_SourceId_014 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI5_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI5_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI5_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI5_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI5_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI5_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI5_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI5_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI5_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI5_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI5_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI5_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI5_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI5_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI5_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI5_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI5_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI5_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI5_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI5_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI5_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI5_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI5_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI5_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG5->GCR1; + config_reg->CONFIG_INT0 = mibspiREG5->INT0; + config_reg->CONFIG_LVL = mibspiREG5->LVL; + config_reg->CONFIG_PCFUN = mibspiREG5->PC0; + config_reg->CONFIG_PCDIR = mibspiREG5->PC1; + config_reg->CONFIG_PCPDR = mibspiREG5->PC6; + config_reg->CONFIG_PCDIS = mibspiREG5->PC7; + config_reg->CONFIG_PCPSL = mibspiREG5->PC8; + config_reg->CONFIG_DELAY = mibspiREG5->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG5->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG5->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG5->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG5->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG5->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG5->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG5->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG5->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG5->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG5->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG5->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG5->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG5->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG5->TGCTRL[ 7U ]; + config_reg->CONFIG_UERRCTRL = mibspiREG5->UERRCTRL; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/notification.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/notification.c new file mode 100644 index 00000000000..c5a8864f405 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/notification.c @@ -0,0 +1,261 @@ +/** @file notification.c + * @brief User Notification Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file defines empty notification routines to avoid + * linker errors, Driver expects user to define the notification. + * The user needs to either remove this file and use their custom + * notification function or place their code sequence in this file + * between the provided USER CODE BEGIN and USER CODE END. + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include "esm.h" +#include "sys_selftest.h" +#include "adc.h" +#include "can.h" +#include "gio.h" +#include "mibspi.h" +#include "sci.h" +#include "spi.h" +#include "het.h" +#include "sys_dma.h" +#include "emac.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ +void esmGroup1Notification( uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +void esmGroup2Notification( uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +void memoryPort0TestFailNotification( uint32 groupSelect, + uint32 dataSelect, + uint32 address, + uint32 data ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +void memoryPort1TestFailNotification( uint32 groupSelect, + uint32 dataSelect, + uint32 address, + uint32 data ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +void adcNotification( adcBASE_t * adc, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +void canErrorNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +void canStatusChangeNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +void canMessageNotification( canBASE_t * node, uint32 messageBox ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ +void gioNotification( gioPORT_t * port, uint32 bit ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +void sciNotification( sciBASE_t * sci, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ +void spiNotification( spiBASE_t * spi, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ +void spiEndNotification( spiBASE_t * spi ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (36) */ +/* USER CODE END */ +void edgeNotification( hetBASE_t * hetREG, uint32 edge ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (38) */ +/* USER CODE END */ +void hetNotification( hetBASE_t * het, uint32 offset ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +/* USER CODE BEGIN (47) */ +/* USER CODE END */ + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (54) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ +void emacTxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (57) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ +void emacRxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (59) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (60) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/phy_dp83640.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/phy_dp83640.c new file mode 100644 index 00000000000..58aa9de0a3b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/phy_dp83640.c @@ -0,0 +1,436 @@ +/** + * \file phy_dp83640.c + * + * \brief APIs for configuring DP83640. + * + * This file contains the device abstraction APIs for PHY DP83640. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ + +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : HL_ETH_SR49 */ +uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : HL_ETH_SR47 */ +boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * DP83640_100BTX - 100BaseTX + * DP83640_100BTX_FD - Full duplex capabilty for 100BaseTX + * DP83640_10BT - 10BaseT + * DP83640_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : HL_ETH_SR46 */ +boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : HL_ETH_SR48 */ +boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : HL_ETH_SR44 */ +void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint16 regVal = 0U; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET ); + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, ®Val ); + + /* : This bit is self-clearing and returns 1 until the reset process is complete. */ + while( ( regVal & PHY_SOFTRESET ) != 0U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, ®Val ); + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : HL_ETH_SR51 */ +void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : HL_ETH_SR51 */ +void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : HL_ETH_SR53 */ +uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/pinmux.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/pinmux.c new file mode 100644 index 00000000000..49dd6e196b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/pinmux.c @@ -0,0 +1,396 @@ +/** @file pinmux.c + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include "reg_system.h" +#include "pinmux.h" + +/*LDRA_INSPECTWINDOW 50 */ +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +#define PINMUX_SET( REG, BALLID, MUX ) \ + ( pinMuxReg->PINMMR##REG = ( pinMuxReg->PINMMR##REG & PINMUX_BALL_##BALLID##_MASK ) \ + | ( PINMUX_BALL_##BALLID##_##MUX ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_GATE_EMIF_CLK_ENABLE( state ) \ + ( pinMuxReg->PINMMR29 = ( pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK ) \ + | ( PINMUX_GATE_EMIF_CLK_##state ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_GIOB_DISABLE_HET2_ENABLE( state ) \ + ( pinMuxReg->PINMMR29 = ( pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ALT_ADC_TRIGGER_SELECT( num ) \ + ( pinMuxReg->PINMMR30 = ( pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK ) \ + | ( PINMUX_ALT_ADC_TRIGGER_##num ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETHERNET_SELECT( interface ) \ + ( pinMuxReg->PINMMR29 = ( pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK ) \ + | ( PINMUX_ETHERNET_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM1_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR41 = ( pinMuxReg->PINMMR41 & PINMUX_ETPWM1_MASK ) \ + | ( PINMUX_ETPWM1_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM2_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR41 = ( pinMuxReg->PINMMR41 & PINMUX_ETPWM2_MASK ) \ + | ( PINMUX_ETPWM2_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM3_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR41 = ( pinMuxReg->PINMMR41 & PINMUX_ETPWM3_MASK ) \ + | ( PINMUX_ETPWM3_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM4_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR41 = ( pinMuxReg->PINMMR41 & PINMUX_ETPWM4_MASK ) \ + | ( PINMUX_ETPWM4_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM5_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR42 = ( pinMuxReg->PINMMR42 & PINMUX_ETPWM5_MASK ) \ + | ( PINMUX_ETPWM5_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM6_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR42 = ( pinMuxReg->PINMMR42 & PINMUX_ETPWM6_MASK ) \ + | ( PINMUX_ETPWM6_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM7_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMMR42 = ( pinMuxReg->PINMMR42 & PINMUX_ETPWM7_MASK ) \ + | ( PINMUX_ETPWM7_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ1_ENABLE( interface ) \ + ( pinMuxReg->PINMMR46 = ( pinMuxReg->PINMMR46 & PINMUX_TZ1_SHIFT ) \ + | ( PINMUX_TZ1_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ2_ENABLE( interface ) \ + ( pinMuxReg->PINMMR46 = ( pinMuxReg->PINMMR46 & PINMUX_TZ2_SHIFT ) \ + | ( PINMUX_TZ2_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ3_ENABLE( interface ) \ + ( pinMuxReg->PINMMR47 = ( pinMuxReg->PINMMR47 & PINMUX_TZ3_SHIFT ) \ + | ( PINMUX_TZ3_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE( interface ) \ + ( pinMuxReg->PINMMR47 = ( pinMuxReg->PINMMR47 & PINMUX_EPWM1SYNCI_SHIFT ) \ + | ( PINMUX_EPWM1SYNCI_##interface ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( state ) \ + ( pinMuxReg->PINMMR36 = ( pinMuxReg->PINMMR36 & PINMUX_ETPWM_TIME_BASE_SYNC_MASK ) \ + | ( PINMUX_ETPWM_TIME_BASE_SYNC_##state ) ) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TBCLK_SYNC_ENABLE( state ) \ + ( pinMuxReg->PINMMR37 = ( pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK ) \ + | ( PINMUX_ETPWM_TBCLK_SYNC_##state ) ) + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* SourceId : PINMUX_SourceId_001 */ +/* DesignId : PINMUX_DesignId_001 */ +/* Requirements : HL_SR325 */ +void muxInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 + | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2; + + pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11; + + pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 + | PINMUX_BALL_B5_GIOA_5; + + pinMuxReg->PINMMR3 = PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6; + + pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_V2_HET1_01 + | PINMUX_BALL_U1_HET1_03; + + pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 + | PINMUX_BALL_V6_HET1_05; + + pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_V7_HET1_09; + + pinMuxReg->PINMMR7 = PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06; + + pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 + | PINMUX_BALL_N1_HET1_15; + + pinMuxReg->PINMMR9 = ( ( ~( pinMuxReg->PINMMR9 >> 18U ) & 0x00000001U ) << 18U ) + | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 + | PINMUX_BALL_J3_MIBSPI1NCS_3; + + pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N17_EMIF_nCS_0; + + pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_P1_HET1_24; + + pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_G19_MIBSPI1NENA + | PINMUX_BALL_H18_MIBSPI5NENA; + + pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 + | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0; + + pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 + | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1; + + pinMuxReg->PINMMR15 = 0x01010101U; + + pinMuxReg->PINMMR16 = 0x01010101U; + + pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_B4_HET1_12; + + pinMuxReg->PINMMR18 = PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_M2_GIOB_0; + + pinMuxReg->PINMMR19 = PINMUX_BALL_B11_HET1_30; + + pinMuxReg->PINMMR20 = PINMUX_BALL_F3_MIBSPI1NCS_1; + + pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1; + + pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 + | PINMUX_BALL_C4_EMIF_ADDR_6; + + pinMuxReg->PINMMR23 = ( ( ~( pinMuxReg->PINMMR5 >> 1U ) & 0x00000001U ) << 8U ) + | ( ( ~( pinMuxReg->PINMMR5 >> 9U ) & 0x00000001U ) << 16U ) + | ( ( ~( pinMuxReg->PINMMR5 >> 17U ) & 0x00000001U ) << 24U ) + | PINMUX_BALL_C6_EMIF_ADDR_8; + + pinMuxReg->PINMMR24 = ( ( ~( pinMuxReg->PINMMR20 >> 17U ) & 0x00000001U ) << 16U ) + | ( ( ~( pinMuxReg->PINMMR8 >> 9U ) & 0x00000001U ) << 24U ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pinMuxReg->PINMMR25 = ( ( ~( pinMuxReg->PINMMR9 >> 25U ) & 0x00000001U ) << 0U ) + | ( ( ~( pinMuxReg->PINMMR12 >> 17U ) & 0x00000001U ) << 8U ) + | ( ( ~( pinMuxReg->PINMMR7 >> 9U ) & 0x00000001U ) << 16U ) + | ( ( ~( pinMuxReg->PINMMR0 >> 26U ) & 0x00000001U ) << 24U ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pinMuxReg->PINMMR26 = ( ( ~( pinMuxReg->PINMMR0 >> 18U ) & 0x00000001U ) << 0U ) + | ( ( ~( pinMuxReg->PINMMR9 >> 10U ) & 0x00000001U ) << 8U ); + + pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0; + + pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA; + + pinMuxReg->PINMMR30 = 0x01010100U; + + pinMuxReg->PINMMR31 = 0x01010101U; + + pinMuxReg->PINMMR32 = 0x00010101U; + + pinMuxReg->PINMMR33 = PINMUX_BALL_B12_HET1_04 | PINMUX_BALL_V8_MIBSPI3SOMI + | PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V9_MIBSPI3CLK; + + pinMuxReg->PINMMR34 = PINMUX_BALL_A4_HET1_16 | PINMUX_BALL_J1_HET1_18 + | PINMUX_BALL_P2_HET1_20; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + PINMUX_GATE_EMIF_CLK_ENABLE( OFF ); + PINMUX_GIOB_DISABLE_HET2_ENABLE( OFF ); + PINMUX_ALT_ADC_TRIGGER_SELECT( 1 ); + PINMUX_ETHERNET_SELECT( RMII ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + PINMUX_ETPWM1_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM2_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM3_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM4_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM5_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM6_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM7_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( OFF ); + PINMUX_ETPWM_TZ1_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ2_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ3_ENABLE( ASYNC ); + PINMUX_ETPWM_EPWM1SYNCI_ENABLE( ASYNC ); + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; + + /* Bit 31 of register GPREG1 is used to gate off the + * EMIF module outputs */ + systemREG1->GPREG1 |= 0x80000000U; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/** @fn void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : PINMUX_SourceId_002 */ +/* DesignId : PINMUX_DesignId_002 */ +/* Requirements : HL_SR328 */ +void pinmuxGetConfigValue( pinmux_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { /* Do not pass Initial Value as parameter */ + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PINMMR0 = pinMuxReg->PINMMR0; + config_reg->CONFIG_PINMMR1 = pinMuxReg->PINMMR1; + config_reg->CONFIG_PINMMR2 = pinMuxReg->PINMMR2; + config_reg->CONFIG_PINMMR3 = pinMuxReg->PINMMR3; + config_reg->CONFIG_PINMMR4 = pinMuxReg->PINMMR4; + config_reg->CONFIG_PINMMR5 = pinMuxReg->PINMMR5; + config_reg->CONFIG_PINMMR6 = pinMuxReg->PINMMR6; + config_reg->CONFIG_PINMMR7 = pinMuxReg->PINMMR7; + config_reg->CONFIG_PINMMR8 = pinMuxReg->PINMMR8; + config_reg->CONFIG_PINMMR9 = pinMuxReg->PINMMR9; + config_reg->CONFIG_PINMMR10 = pinMuxReg->PINMMR10; + config_reg->CONFIG_PINMMR11 = pinMuxReg->PINMMR11; + config_reg->CONFIG_PINMMR12 = pinMuxReg->PINMMR12; + config_reg->CONFIG_PINMMR13 = pinMuxReg->PINMMR13; + config_reg->CONFIG_PINMMR14 = pinMuxReg->PINMMR14; + config_reg->CONFIG_PINMMR15 = pinMuxReg->PINMMR15; + config_reg->CONFIG_PINMMR16 = pinMuxReg->PINMMR16; + config_reg->CONFIG_PINMMR17 = pinMuxReg->PINMMR17; + config_reg->CONFIG_PINMMR18 = pinMuxReg->PINMMR18; + config_reg->CONFIG_PINMMR19 = pinMuxReg->PINMMR19; + config_reg->CONFIG_PINMMR20 = pinMuxReg->PINMMR20; + config_reg->CONFIG_PINMMR21 = pinMuxReg->PINMMR21; + config_reg->CONFIG_PINMMR22 = pinMuxReg->PINMMR22; + config_reg->CONFIG_PINMMR23 = pinMuxReg->PINMMR23; + config_reg->CONFIG_PINMMR24 = pinMuxReg->PINMMR24; + config_reg->CONFIG_PINMMR25 = pinMuxReg->PINMMR25; + config_reg->CONFIG_PINMMR26 = pinMuxReg->PINMMR26; + config_reg->CONFIG_PINMMR27 = pinMuxReg->PINMMR27; + config_reg->CONFIG_PINMMR28 = pinMuxReg->PINMMR28; + config_reg->CONFIG_PINMMR29 = pinMuxReg->PINMMR29; + config_reg->CONFIG_PINMMR30 = pinMuxReg->PINMMR30; + config_reg->CONFIG_PINMMR31 = pinMuxReg->PINMMR31; + config_reg->CONFIG_PINMMR32 = pinMuxReg->PINMMR32; + config_reg->CONFIG_PINMMR33 = pinMuxReg->PINMMR33; + config_reg->CONFIG_PINMMR34 = pinMuxReg->PINMMR34; + config_reg->CONFIG_PINMMR35 = pinMuxReg->PINMMR35; + config_reg->CONFIG_PINMMR36 = pinMuxReg->PINMMR36; + config_reg->CONFIG_PINMMR37 = pinMuxReg->PINMMR37; + config_reg->CONFIG_PINMMR38 = pinMuxReg->PINMMR38; + config_reg->CONFIG_PINMMR39 = pinMuxReg->PINMMR39; + config_reg->CONFIG_PINMMR40 = pinMuxReg->PINMMR40; + config_reg->CONFIG_PINMMR41 = pinMuxReg->PINMMR41; + config_reg->CONFIG_PINMMR42 = pinMuxReg->PINMMR42; + config_reg->CONFIG_PINMMR43 = pinMuxReg->PINMMR43; + config_reg->CONFIG_PINMMR44 = pinMuxReg->PINMMR44; + config_reg->CONFIG_PINMMR45 = pinMuxReg->PINMMR45; + config_reg->CONFIG_PINMMR46 = pinMuxReg->PINMMR46; + config_reg->CONFIG_PINMMR47 = pinMuxReg->PINMMR47; + } +} + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sci.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sci.c new file mode 100644 index 00000000000..add0d6b664b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sci.c @@ -0,0 +1,893 @@ +/** @file sci.c + * @brief SCI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +#include +/* USER CODE END */ + +#include "sci.h" +#include "sys_vim.h" +#include "math.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_sciTransfer + * @brief Interrupt mode globals + * + */ +static volatile struct g_sciTransfer +{ + uint32 mode; /* Used to check for TX interrupt Enable */ + uint32 tx_length; /* Transmit data length in number of Bytes */ + uint32 rx_length; /* Receive data length in number of Bytes */ + uint8 * tx_data; /* Transmit data pointer */ + uint8 * rx_data; /* Receive data pointer */ +} g_sciTransfer_t[ 2U ]; + +/** @fn void sciInit(void) + * @brief Initializes the SCI Driver + * + * This function initializes the SCI module. + */ +/* SourceId : SCI_SourceId_001 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : HL_SR230 */ +void sciInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b SCI */ + + /** - bring SCI out of reset */ + sciREG->GCR0 = 0U; + sciREG->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG->CLEARINT = 0xFFFFFFFFU; + sciREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG->BRS = 59U; /* baudrate */ + + /** - transmission length */ + sciREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + sciREG->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI pins default output value */ + sciREG->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins output direction */ + sciREG->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins open drain enable */ + sciREG->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown enable */ + sciREG->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown select */ + sciREG->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 0U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 0U ].tx_length = 0U; + g_sciTransfer_t[ 0U ].rx_length = 0U; + + /** - Finaly start SCI */ + sciREG->GCR1 |= 0x80U; + + /** @b initialize @b SCILIN */ + + /** - bring SCI out of reset */ + scilinREG->GCR0 = 0U; + scilinREG->GCR0 = 1U; + + /** - Disable all interrupts */ + scilinREG->CLEARINT = 0xFFFFFFFFU; + scilinREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + scilinREG->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has + no clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits + */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + scilinREG->BRS = 59U; /* baudrate */ + + /** - transmission length */ + scilinREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + scilinREG->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI pins default output value */ + scilinREG->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins output direction */ + scilinREG->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins open drain enable */ + scilinREG->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown enable */ + scilinREG->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown select */ + scilinREG->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + scilinREG->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - set interrupt enable */ + scilinREG->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 1U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 1U ].tx_length = 0U; + g_sciTransfer_t[ 1U ].rx_length = 0U; + + /** - Finaly start SCILIN */ + scilinREG->GCR1 |= 0x80U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] sci - sci module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCPIO0 register at runtime, this allows to + * dynamically change the functionality of the SCI pins between functional + * and GIO mode. + */ +/* SourceId : SCI_SourceId_002 */ +/* DesignId : SCI_DesignId_002 */ +/* Requirements : HL_SR231 */ +void sciSetFunctional( sciBASE_t * sci, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + sci->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] sci - sci module base address + * @param[in] baud - baudrate in Hz + * + * Change the SCI baudrate at runtime. + */ +/* SourceId : SCI_SourceId_003 */ +/* DesignId : SCI_DesignId_003 */ +/* Requirements : HL_SR232 */ +void sciSetBaudrate( sciBASE_t * sci, uint32 baud ) +{ + float64 vclk = 110.000 * 1000000.0; + uint32 f = ( ( sci->GCR1 & 2U ) == 2U ) ? 16U : 1U; + uint32 temp; + float64 temp2; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /*SAFETYMCUSW 96 S MR:6.1 "Calculations including int and float cannot be + * avoided" */ + temp = ( f * ( baud ) ); + temp2 = ( ( vclk ) / ( ( float64 ) temp ) ) - 1U; + /*temp2 = floor(temp2 + 0.5); / * Rounding-off to the closest integer * / */ + temp2 = temp2 + 0.5; + sci->BRS = ( uint32 ) ( ( uint32 ) temp2 & 0x00FFFFFFU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn uint32 sciIsTxReady(sciBASE_t *sci) + * @brief Check if Tx buffer empty + * @param[in] sci - sci module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +/* SourceId : SCI_SourceId_004 */ +/* DesignId : SCI_DesignId_004 */ +/* Requirements : HL_SR233 */ +uint32 sciIsTxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_TX_INT; +} + +/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) + * @brief Send Byte + * @param[in] sci - sci module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use sciIsTxReady to check for Tx buffer empty + * before calling sciSendByte to avoid waiting. + */ +/* SourceId : SCI_SourceId_005 */ +/* DesignId : SCI_DesignId_005 */ +/* Requirements : HL_SR234 */ +void sciSendByte( sciBASE_t * sci, uint8 byte ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + sci->TD = byte; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, sciSend must not be called again until the + * transfer is complete, when the sciNotification callback will + * be called. In polling mode, sciSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +/* SourceId : SCI_SourceId_006 */ +/* DesignId : SCI_DesignId_006 */ +/* Requirements : HL_SR235 */ +void sciSend( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + uint32 index = ( sci == sciREG ) ? 0U : 1U; + uint8 txdata; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + /*SAFETYMCUSW 139 S MR:13.7 "Mode variable is configured in + * sciEnableNotification()" */ + if( ( g_sciTransfer_t[ index ].mode & ( uint32 ) SCI_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + + g_sciTransfer_t[ index ].tx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].tx_data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + txdata = *g_sciTransfer_t[ index ].tx_data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[ index ].tx_data++; + sci->SETINT = ( uint32 ) SCI_TX_INT; + } + else + { + /* send the data */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + txdata = *data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn uint32 sciIsRxReady(sciBASE_t *sci) + * @brief Check if Rx buffer full + * @param[in] sci - sci module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +/* SourceId : SCI_SourceId_007 */ +/* DesignId : SCI_DesignId_007 */ +/* Requirements : HL_SR236 */ +uint32 sciIsRxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_RX_INT; +} + +/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) + * @brief Check if Idle Period is Detected + * @param[in] sci - sci module base address + * + * @return The Idle flag + * + * Checks to see if the SCI Idle flag is set, returns 0 if idle + * period has been detected and SCI is ready to receive, otherwise returns the Idle flag + *itself. + */ +/* SourceId : SCI_SourceId_008 */ +/* DesignId : SCI_DesignId_008 */ +/* Requirements : HL_SR237 */ +uint32 sciIsIdleDetected( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_IDLE; +} + +/** @fn uint32 sciRxError(sciBASE_t *sci) + * @brief Return Rx Error flags + * @param[in] sci - sci module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +/* SourceId : SCI_SourceId_009 */ +/* DesignId : SCI_DesignId_009 */ +/* Requirements : HL_SR238 */ +uint32 sciRxError( sciBASE_t * sci ) +{ + uint32 status = ( sci->FLR + & ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ) ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT | ( uint32 ) SCI_PE_INT ); + return status; +} + +/** @fn uint32 sciReceiveByte(sciBASE_t *sci) + * @brief Receive Byte + * @param[in] sci - sci module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use sciIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +/* SourceId : SCI_SourceId_010 */ +/* DesignId : SCI_DesignId_010 */ +/* Requirements : HL_SR239 */ +uint32 sciReceiveByte( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + return ( sci->RD & ( uint32 ) 0x000000FFU ); +} + +/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer to receive data + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, sciReceive must not be called + * again until the transfer is complete, when the sciNotification + * callback will be called. In polling mode, sciReceive will not + * return until the transfer is complete. + */ +/* SourceId : SCI_SourceId_011 */ +/* DesignId : SCI_DesignId_011 */ +/* Requirements : HL_SR240 */ +void sciReceive( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( sci->SETINT & ( uint32 ) SCI_RX_INT ) == ( uint32 ) SCI_RX_INT ) + { + /* we are in interrupt mode */ + uint32 index = ( sci == sciREG ) ? 0U : 1U; + + /* clear error flags */ + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ); + + g_sciTransfer_t[ index ].rx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].rx_data = data; + } + else + { + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( uint8 ) ( sci->RD & 0x000000FFU ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +/* SourceId : SCI_SourceId_012 */ +/* DesignId : SCI_DesignId_014 */ +/* Requirements : HL_SR243 */ +void sciEnableLoopback( sciBASE_t * sci, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + sci->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + sci->IODFTCTRL = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn void sciDisableLoopback(sciBASE_t *sci) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * + * This function disable the Loopback mode. + */ +/* SourceId : SCI_SourceId_013 */ +/* DesignId : SCI_DesignId_015 */ +/* Requirements : HL_SR244 */ +void sciDisableLoopback( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + sci->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) + * @brief Enable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +/* SourceId : SCI_SourceId_014 */ +/* DesignId : SCI_DesignId_012 */ +/* Requirements : HL_SR241 */ +void sciEnableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG ) ? 0U : 1U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode |= ( flags & ( uint32 ) SCI_TX_INT ); + sci->SETINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) + * @brief Disable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +/* SourceId : SCI_SourceId_015 */ +/* DesignId : SCI_DesignId_013 */ +/* Requirements : HL_SR242 */ +void sciDisableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG ) ? 0U : 1U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode &= ( uint32 ) ( ~( flags & ( uint32 ) SCI_TX_INT ) ); + sci->CLEARINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/** @fn sciEnterResetState(sciBASE_t *sci) + * @brief Enter reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +/* SourceId : SCI_SourceId_022 */ +/* DesignId : SCI_DesignId_018 */ +/* Requirements : HL_SR548 */ +void sciEnterResetState( sciBASE_t * sci ) +{ + sci->GCR1 &= 0xFFFFFF7FU; +} + +/** @fn scixitResetState(sciBASE_t *sci) + * @brief Exit reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +/* SourceId : SCI_SourceId_023 */ +/* DesignId : SCI_DesignId_018 */ +/* Requirements : HL_SR548 */ +void sciExitResetState( sciBASE_t * sci ) +{ + sci->GCR1 |= 0x00000080U; +} + +/** @fn void sciGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SCI_SourceId_016 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : HL_SR247 */ +void sciGetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR0 = sciREG->GCR0; + config_reg->CONFIG_GCR1 = sciREG->GCR1; + config_reg->CONFIG_SETINT = sciREG->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG->FORMAT; + config_reg->CONFIG_BRS = sciREG->BRS; + config_reg->CONFIG_PIO0 = sciREG->PIO0; + config_reg->CONFIG_PIO1 = sciREG->PIO1; + config_reg->CONFIG_PIO6 = sciREG->PIO6; + config_reg->CONFIG_PIO7 = sciREG->PIO7; + config_reg->CONFIG_PIO8 = sciREG->PIO8; + } +} + +/** @fn void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCILIN ( SCI2) configuration + *registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SCI_SourceId_017 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : HL_SR247 */ +void scilinGetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCILIN_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCILIN_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCILIN_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCILIN_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCILIN_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCILIN_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCILIN_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCILIN_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCILIN_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCILIN_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCILIN_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR0 = scilinREG->GCR0; + config_reg->CONFIG_GCR1 = scilinREG->GCR1; + config_reg->CONFIG_SETINT = scilinREG->SETINT; + config_reg->CONFIG_SETINTLVL = scilinREG->SETINTLVL; + config_reg->CONFIG_FORMAT = scilinREG->FORMAT; + config_reg->CONFIG_BRS = scilinREG->BRS; + config_reg->CONFIG_PIO0 = scilinREG->PIO0; + config_reg->CONFIG_PIO1 = scilinREG->PIO1; + config_reg->CONFIG_PIO6 = scilinREG->PIO6; + config_reg->CONFIG_PIO7 = scilinREG->PIO7; + config_reg->CONFIG_PIO8 = scilinREG->PIO8; + } +} + +/* USER CODE BEGIN (37) */ + +void sci_print( char * str ) +{ + sciDisplayText( scilinREG, str, strlen( str ) ); +} + +void sciDisplayText( sciBASE_t * sci, char * text, uint32_t length ) +{ + while( length-- ) + { + /* Wait until we hit an idle state */ + while( ( sci->FLR & ( uint32_t ) SCI_IDLE ) == 4U ) + { + /* Wait */ + } + + /* Send out text */ + sciSendByte( sci, *text++ ); + } +} + +void sciDisplayData( sciBASE_t * sci, uint8_t * text, uint32_t length ) +{ + uint8_t txt = 0; + uint8_t txt1 = 0; + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + text = text + ( length - 1 ); +#endif + + while( length-- ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + txt = *text--; +#else + txt = *text++; +#endif + + txt1 = txt; + + txt &= ~( 0xF0 ); + txt1 &= ~( 0x0F ); + txt1 = txt1 >> 4; + + if( txt <= 0x9 ) + { + txt += 0x30; + } + else if( ( txt > 0x9 ) && ( txt < 0xF ) ) + { + txt += 0x37; + } + else + { + txt = 0x30; + } + + if( txt1 <= 0x9 ) + { + txt1 += 0x30; + } + else if( ( txt1 > 0x9 ) && ( txt1 <= 0xF ) ) + { + txt1 += 0x37; + } + else + { + txt1 = 0x30; + } + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt1 ); /* send out text */ + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt ); /* send out text */ + } +} + +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/spi.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/spi.c new file mode 100644 index 00000000000..a98fb9304ba --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/spi.c @@ -0,0 +1,992 @@ +/** @file spi.c + * @brief SPI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "spi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_spiPacket + * @brief globals + * + */ +static volatile struct g_spiPacket +{ + spiDAT1_t g_spiDataFormat; + uint32 tx_length; + uint32 rx_length; + uint16 * txdata_ptr; + uint16 * rxdata_ptr; + SpiDataStatus_t tx_data_status; + SpiDataStatus_t rx_data_status; +} g_spiPacket_t[ 5U ]; + +/** @fn void spiInit(void) + * @brief Initializes the SPI Driver + * + * This function initializes the SPI module. + */ +/* SourceId : SPI_SourceId_001 */ +/* DesignId : SPI_DesignId_001 */ +/* Requirements : HL_SR126 */ +void spiInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b SPI2 */ + + /** bring SPI out of reset */ + spiREG2->GCR0 = 0U; + spiREG2->GCR0 = 1U; + + /** SPI2 master mode and clock configuration */ + spiREG2->GCR1 = ( spiREG2->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** SPI2 enable pin configuration */ + spiREG2->INT0 = ( spiREG2->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ */ + + /** - Delays */ + spiREG2->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + spiREG2->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + /** - Data Format 1 */ + spiREG2->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + spiREG2->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + spiREG2->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - set interrupt levels */ + spiREG2->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + spiREG2->FLG |= 0xFFFFU; + + /** - enable interrupts */ + spiREG2->INT0 = ( spiREG2->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b SPI2 @b Port */ + + /** - SPI2 Port output values */ + spiREG2->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - SPI2 Port direction */ + spiREG2->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - SPI2 Port open drain enable */ + spiREG2->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - SPI2 Port pullup / pulldown selection */ + spiREG2->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - SPI2 Port pullup / pulldown enable*/ + spiREG2->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* SPI2 set all pins to functional */ + spiREG2->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Initialize TX and RX data buffer Status */ + g_spiPacket_t[ 1U ].tx_data_status = SPI_READY; + g_spiPacket_t[ 1U ].rx_data_status = SPI_READY; + + /** - Finally start SPI2 */ + spiREG2->GCR1 = ( spiREG2->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b SPI4 */ + + /** bring SPI out of reset */ + spiREG4->GCR0 = 0U; + spiREG4->GCR0 = 1U; + + /** SPI4 master mode and clock configuration */ + spiREG4->GCR1 = ( spiREG4->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** SPI4 enable pin configuration */ + spiREG4->INT0 = ( spiREG4->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ */ + + /** - Delays */ + spiREG4->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + spiREG4->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + spiREG4->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + spiREG4->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + spiREG4->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 109U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - set interrupt levels */ + spiREG4->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + spiREG4->FLG |= 0xFFFFU; + + /** - enable interrupts */ + spiREG4->INT0 = ( spiREG4->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b SPI4 @b Port */ + + /** - SPI4 Port output values */ + spiREG4->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - SPI4 Port direction */ + spiREG4->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - SPI4 Port open drain enable */ + spiREG4->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - SPI4 Port pullup / pulldown selection */ + spiREG4->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - SPI4 Port pullup / pulldown enable*/ + spiREG4->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* SPI4 set all pins to functional */ + spiREG4->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Initialize TX and RX data buffer Status */ + g_spiPacket_t[ 3U ].tx_data_status = SPI_READY; + g_spiPacket_t[ 3U ].rx_data_status = SPI_READY; + + /** - Finally start SPI4 */ + spiREG4->GCR1 = ( spiREG4->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void spiSetFunctional(spiBASE_t *spi, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] spi - Spi module base address + * @param[in] port - Value to write to PC0 register + * + * Change the value of the PC0 register at runtime, this allows to + * dynamically change the functionality of the SPI pins between functional + * and GIO mode. + */ +/* SourceId : SPI_SourceId_002 */ +/* DesignId : SPI_DesignId_002 */ +/* Requirements : HL_SR128 */ +void spiSetFunctional( spiBASE_t * spi, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + spi->PC0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn uint32 spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, + * uint16 * destbuff) + * @brief Receives Data using polling method + * @param[in] spi - Spi module base address + * @param[in] dataconfig_t - Spi DAT1 register configuration + * @param[in] blocksize - number of data + * @param[in] destbuff - Pointer to the destination data (16 bit). + * + * @return flag register value. + * + * This function transmits blocksize number of data from source buffer using polling + * method. + */ +/* SourceId : SPI_SourceId_003 */ +/* DesignId : SPI_DesignId_007 */ +/* Requirements : HL_SR133 */ +uint32 spiReceiveData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * destbuff ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + uint32 Chip_Select_Hold = ( dataconfig_t->CS_HOLD ) ? 0x10000000U : 0U; + uint32 WDelay = ( dataconfig_t->WDEL ) ? 0x04000000U : 0U; + SPIDATAFMT_t DataFormat = dataconfig_t->DFSEL; + uint8 ChipSelect = dataconfig_t->CSNR; + + while( blocksize != 0U ) + { + if( ( spi->FLG & 0x000000FFU ) != 0U ) + { + break; + } + + if( blocksize == 1U ) + { + Chip_Select_Hold = 0U; + } + + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 32-bit value" */ + spi->DAT1 = ( ( uint32 ) DataFormat << 24U ) | ( ( uint32 ) ChipSelect << 16U ) + | ( WDelay ) | ( Chip_Select_Hold ) | ( 0x00000000U ); + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( spi->FLG & 0x00000100U ) != 0x00000100U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *destbuff = ( uint16 ) spi->BUF; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + destbuff++; + blocksize--; + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + return ( spi->FLG & 0xFFU ); +} + +/** @fn uint32 spiGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, + * uint16 * destbuff) + * @brief Receives Data using interrupt method + * @param[in] spi - Spi module base address + * @param[in] dataconfig_t - Spi DAT1 register configuration + * @param[in] blocksize - number of data + * @param[in] destbuff - Pointer to the destination data (16 bit). + * + * @return flag register value. + * + * This function transmits blocksize number of data from source buffer using interrupt + * method. + */ +/* SourceId : SPI_SourceId_004 */ +/* DesignId : SPI_DesignId_008 */ +/* Requirements : HL_SR134 */ +void spiGetData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * destbuff ) +{ + uint32 index = ( spi == spiREG1 ) + ? 0U + : ( ( spi == spiREG2 ) + ? 1U + : ( ( spi == spiREG3 ) + ? 2U + : ( ( spi == spiREG4 ) ? 3U : 4U ) ) ); + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + g_spiPacket_t[ index ].rx_length = blocksize; + g_spiPacket_t[ index ].rxdata_ptr = destbuff; + g_spiPacket_t[ index ].g_spiDataFormat = *dataconfig_t; + g_spiPacket_t[ index ].rx_data_status = SPI_PENDING; + + spi->INT0 |= 0x0100U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn uint32 spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, + * uint16 * srcbuff) + * @brief Transmits Data using polling method + * @param[in] spi - Spi module base address + * @param[in] dataconfig_t - Spi DAT1 register configuration + * @param[in] blocksize - number of data + * @param[in] srcbuff - Pointer to the source data ( 16 bit). + * + * @return flag register value. + * + * This function transmits blocksize number of data from source buffer using polling + * method. + */ +/* SourceId : SPI_SourceId_005 */ +/* DesignId : SPI_DesignId_005 */ +/* Requirements : HL_SR131 */ +uint32 spiTransmitData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff ) +{ + volatile uint32 SpiBuf; + uint16 Tx_Data; + uint32 Chip_Select_Hold = ( dataconfig_t->CS_HOLD ) ? 0x10000000U : 0U; + uint32 WDelay = ( dataconfig_t->WDEL ) ? 0x04000000U : 0U; + SPIDATAFMT_t DataFormat = dataconfig_t->DFSEL; + uint8 ChipSelect = dataconfig_t->CSNR; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + while( blocksize != 0U ) + { + if( ( spi->FLG & 0x000000FFU ) != 0U ) + { + break; + } + + if( blocksize == 1U ) + { + Chip_Select_Hold = 0U; + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + Tx_Data = *srcbuff; + + spi->DAT1 = ( ( uint32 ) DataFormat << 24U ) | ( ( uint32 ) ChipSelect << 16U ) + | ( WDelay ) | ( Chip_Select_Hold ) | ( uint32 ) Tx_Data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + srcbuff++; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( spi->FLG & 0x00000100U ) != 0x00000100U ) + { + } /* Wait */ + + SpiBuf = spi->BUF; + ( void ) SpiBuf; + + blocksize--; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return ( spi->FLG & 0xFFU ); +} + +/** @fn void spiSendData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 + * * srcbuff) + * @brief Transmits Data using interrupt method + * @param[in] spi - Spi module base address + * @param[in] dataconfig_t - Spi DAT1 register configuration + * @param[in] blocksize - number of data + * @param[in] srcbuff - Pointer to the source data ( 16 bit). + * + * @return flag register value. + * + * This function transmits blocksize number of data from source buffer using interrupt + * method. + */ +/* SourceId : SPI_SourceId_006 */ +/* DesignId : SPI_DesignId_006 */ +/* Requirements : HL_SR132 */ +void spiSendData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff ) +{ + uint32 index = ( spi == spiREG1 ) + ? 0U + : ( ( spi == spiREG2 ) + ? 1U + : ( ( spi == spiREG3 ) + ? 2U + : ( ( spi == spiREG4 ) ? 3U : 4U ) ) ); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + g_spiPacket_t[ index ].tx_length = blocksize; + g_spiPacket_t[ index ].txdata_ptr = srcbuff; + g_spiPacket_t[ index ].g_spiDataFormat = *dataconfig_t; + g_spiPacket_t[ index ].tx_data_status = SPI_PENDING; + + spi->INT0 |= 0x0200U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn uint32 spiTransmitAndReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 + * blocksize, uint16 * srcbuff, uint16 * destbuff) + * @brief Transmits and Receive Data using polling method + * @param[in] spi - Spi module base address + * @param[in] dataconfig_t - Spi DAT1 register configuration + * @param[in] blocksize - number of data + * @param[in] srcbuff - Pointer to the source data ( 16 bit). + * @param[in] destbuff - Pointer to the destination data ( 16 bit). + * + * @return flag register value. + * + * This function transmits and receives blocksize number of data from source buffer + * using polling method. + */ +/* SourceId : SPI_SourceId_007 */ +/* DesignId : SPI_DesignId_009 */ +/* Requirements : HL_SR135 */ +uint32 spiTransmitAndReceiveData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff, + uint16 * destbuff ) +{ + uint16 Tx_Data; + uint32 Chip_Select_Hold = ( dataconfig_t->CS_HOLD ) ? 0x10000000U : 0U; + uint32 WDelay = ( dataconfig_t->WDEL ) ? 0x04000000U : 0U; + SPIDATAFMT_t DataFormat = dataconfig_t->DFSEL; + uint8 ChipSelect = dataconfig_t->CSNR; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + while( blocksize != 0U ) + { + if( ( spi->FLG & 0x000000FFU ) != 0U ) + { + break; + } + + if( blocksize == 1U ) + { + Chip_Select_Hold = 0U; + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + Tx_Data = *srcbuff; + + spi->DAT1 = ( ( uint32 ) DataFormat << 24U ) | ( ( uint32 ) ChipSelect << 16U ) + | ( WDelay ) | ( Chip_Select_Hold ) | ( uint32 ) Tx_Data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + srcbuff++; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( spi->FLG & 0x00000100U ) != 0x00000100U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *destbuff = ( uint16 ) spi->BUF; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + destbuff++; + + blocksize--; + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + return ( spi->FLG & 0xFFU ); +} + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + +/** @fn void spiSendAndGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, + * uint16 * srcbuff, uint16 * destbuff) + * @brief Initiate SPI Transmits and receive Data using Interrupt mode. + * @param[in] spi - Spi module base address + * @param[in] dataconfig_t - Spi DAT1 register configuration + * @param[in] blocksize - number of data + * @param[in] srcbuff - Pointer to the source data ( 16 bit). + * @param[in] destbuff - Pointer to the destination data ( 16 bit). + * + * Initiate SPI Transmits and receive Data using Interrupt mode.. + */ +/* SourceId : SPI_SourceId_008 */ +/* DesignId : SPI_DesignId_010 */ +/* Requirements : HL_SR136 */ +void spiSendAndGetData( spiBASE_t * spi, + spiDAT1_t * dataconfig_t, + uint32 blocksize, + uint16 * srcbuff, + uint16 * destbuff ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + uint32 index = ( spi == spiREG1 ) + ? 0U + : ( ( spi == spiREG2 ) + ? 1U + : ( ( spi == spiREG3 ) + ? 2U + : ( ( spi == spiREG4 ) ? 3U : 4U ) ) ); + + g_spiPacket_t[ index ].tx_length = blocksize; + g_spiPacket_t[ index ].rx_length = blocksize; + g_spiPacket_t[ index ].txdata_ptr = srcbuff; + g_spiPacket_t[ index ].rxdata_ptr = destbuff; + g_spiPacket_t[ index ].g_spiDataFormat = *dataconfig_t; + g_spiPacket_t[ index ].tx_data_status = SPI_PENDING; + g_spiPacket_t[ index ].rx_data_status = SPI_PENDING; + + spi->INT0 |= 0x0300U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn SpiDataStatus_t SpiTxStatus(spiBASE_t *spi) + * @brief Get the status of the SPI Transmit data block. + * @param[in] spi - Spi module base address + * + * @return Spi Transmit block data status. + * + * Get the status of the SPI Transmit data block. + */ +/* SourceId : SPI_SourceId_009 */ +/* DesignId : SPI_DesignId_013 */ +/* Requirements : HL_SR139 */ +SpiDataStatus_t SpiTxStatus( spiBASE_t * spi ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + uint32 index = ( spi == spiREG1 ) + ? 0U + : ( ( spi == spiREG2 ) + ? 1U + : ( ( spi == spiREG3 ) + ? 2U + : ( ( spi == spiREG4 ) ? 3U : 4U ) ) ); + + return ( g_spiPacket_t[ index ].tx_data_status ); +} + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + +/** @fn SpiDataStatus_t SpiRxStatus(spiBASE_t *spi) + * @brief Get the status of the SPI Receive data block. + * @param[in] spi - Spi module base address + * + * @return Spi Receive block data status. + * + * Get the status of the SPI Receive data block. + */ +/* SourceId : SPI_SourceId_010 */ +/* DesignId : SPI_DesignId_014 */ +/* Requirements : HL_SR140 */ +SpiDataStatus_t SpiRxStatus( spiBASE_t * spi ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + uint32 index = ( spi == spiREG1 ) + ? 0U + : ( ( spi == spiREG2 ) + ? 1U + : ( ( spi == spiREG3 ) + ? 2U + : ( ( spi == spiREG4 ) ? 3U : 4U ) ) ); + + return ( g_spiPacket_t[ index ].rx_data_status ); +} + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + +/** @fn void spiEnableLoopback(spiBASE_t *spi, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] spi - spi module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +/* SourceId : SPI_SourceId_011 */ +/* DesignId : SPI_DesignId_011 */ +/* Requirements : HL_SR137 */ +void spiEnableLoopback( spiBASE_t * spi, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + spi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + spi->IOLPKTSTCR = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + +/** @fn void spiDisableLoopback(spiBASE_t *spi) + * @brief Enable Loopback mode for self test + * @param[in] spi - spi module base address + * + * This function disable the Loopback mode. + */ +/* SourceId : SPI_SourceId_012 */ +/* DesignId : SPI_DesignId_012 */ +/* Requirements : HL_SR138 */ +void spiDisableLoopback( spiBASE_t * spi ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + spi->IOLPKTSTCR = 0x00000500U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +/** @fn spiEnableNotification(spiBASE_t *spi, uint32 flags) + * @brief Enable interrupts + * @param[in] spi - spi module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + */ +/* SourceId : SPI_SourceId_013 */ +/* DesignId : SPI_DesignId_003 */ +/* Requirements : HL_SR129 */ +void spiEnableNotification( spiBASE_t * spi, uint32 flags ) +{ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + spi->INT0 = ( spi->INT0 & 0xFFFF0000U ) | flags; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/** @fn spiDisableNotification(spiBASE_t *spi, uint32 flags) + * @brief Enable interrupts + * @param[in] spi - spi module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + */ +/* SourceId : SPI_SourceId_014 */ +/* DesignId : SPI_DesignId_004 */ +/* Requirements : HL_SR130 */ +void spiDisableNotification( spiBASE_t * spi, uint32 flags ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + spi->INT0 = ( spi->INT0 & ( ~( flags ) ) ); + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void spi2GetConfigValue(spi_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SPI_SourceId_016 */ +/* DesignId : SPI_DesignId_015 */ +/* Requirements : HL_SR144 */ +void spi2GetConfigValue( spi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = SPI2_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = SPI2_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = SPI2_LVL_CONFIGVALUE; + config_reg->CONFIG_PC0 = SPI2_PC0_CONFIGVALUE; + config_reg->CONFIG_PC1 = SPI2_PC1_CONFIGVALUE; + config_reg->CONFIG_PC6 = SPI2_PC6_CONFIGVALUE; + config_reg->CONFIG_PC7 = SPI2_PC7_CONFIGVALUE; + config_reg->CONFIG_PC8 = SPI2_PC8_CONFIGVALUE; + config_reg->CONFIG_DELAY = SPI2_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = SPI2_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = SPI2_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = SPI2_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = SPI2_FMT3_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = spiREG2->GCR1; + config_reg->CONFIG_INT0 = spiREG2->INT0; + config_reg->CONFIG_LVL = spiREG2->LVL; + config_reg->CONFIG_PC0 = spiREG2->PC0; + config_reg->CONFIG_PC1 = spiREG2->PC1; + config_reg->CONFIG_PC6 = spiREG2->PC6; + config_reg->CONFIG_PC7 = spiREG2->PC7; + config_reg->CONFIG_PC8 = spiREG2->PC8; + config_reg->CONFIG_DELAY = spiREG2->DELAY; + config_reg->CONFIG_FMT0 = spiREG2->FMT0; + config_reg->CONFIG_FMT1 = spiREG2->FMT1; + config_reg->CONFIG_FMT2 = spiREG2->FMT2; + config_reg->CONFIG_FMT3 = spiREG2->FMT3; + } +} + +/** @fn void spi4GetConfigValue(spi_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SPI_SourceId_018 */ +/* DesignId : SPI_DesignId_015 */ +/* Requirements : HL_SR144 */ +void spi4GetConfigValue( spi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = SPI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = SPI4_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = SPI4_LVL_CONFIGVALUE; + config_reg->CONFIG_PC0 = SPI4_PC0_CONFIGVALUE; + config_reg->CONFIG_PC1 = SPI4_PC1_CONFIGVALUE; + config_reg->CONFIG_PC6 = SPI4_PC6_CONFIGVALUE; + config_reg->CONFIG_PC7 = SPI4_PC7_CONFIGVALUE; + config_reg->CONFIG_PC8 = SPI4_PC8_CONFIGVALUE; + config_reg->CONFIG_DELAY = SPI4_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = SPI4_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = SPI4_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = SPI4_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = SPI4_FMT3_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = spiREG4->GCR1; + config_reg->CONFIG_INT0 = spiREG4->INT0; + config_reg->CONFIG_LVL = spiREG4->LVL; + config_reg->CONFIG_PC0 = spiREG4->PC0; + config_reg->CONFIG_PC1 = spiREG4->PC1; + config_reg->CONFIG_PC6 = spiREG4->PC6; + config_reg->CONFIG_PC7 = spiREG4->PC7; + config_reg->CONFIG_PC8 = spiREG4->PC8; + config_reg->CONFIG_DELAY = spiREG4->DELAY; + config_reg->CONFIG_FMT0 = spiREG4->FMT0; + config_reg->CONFIG_FMT1 = spiREG4->FMT1; + config_reg->CONFIG_FMT2 = spiREG4->FMT2; + config_reg->CONFIG_FMT3 = spiREG4->FMT3; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_core.S b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_core.S new file mode 100644 index 00000000000..c53c35b2064 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_core.S @@ -0,0 +1,640 @@ +/*-------------------------------------------------------------------------- + sys_core.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +-------------------------------------------------------------------------*/ + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize CPU Registers +@ SourceId : CORE_SourceId_001 +@ DesignId : CORE_DesignId_001 +@ Requirements: HL_SR477, HL_SR476, HL_SR492 + + .weak _coreInitRegisters_ + .type _coreInitRegisters_, %function + +_coreInitRegisters_: + + @ After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, lr + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to FIQ mode (M = 10001) + cps #17 + mov lr, r0 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to IRQ mode (M = 10010) + cps #18 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Abort mode (M = 10111) + cps #23 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Undefined Instruction Mode (M = 11011) + cps #27 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to System Mode ( Shares User Mode registers ) (M = 11111) + cps #31 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + mov r2, #0x40000000 + fmxr fpexc, r2 + + fmdrr d0, r1, r1 + fmdrr d1, r1, r1 + fmdrr d2, r1, r1 + fmdrr d3, r1, r1 + fmdrr d4, r1, r1 + fmdrr d5, r1, r1 + fmdrr d6, r1, r1 + fmdrr d7, r1, r1 + fmdrr d8, r1, r1 + fmdrr d9, r1, r1 + fmdrr d10, r1, r1 + fmdrr d11, r1, r1 + fmdrr d12, r1, r1 + fmdrr d13, r1, r1 + fmdrr d14, r1, r1 + fmdrr d15, r1, r1 + + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + bx r0 + +/*-------------------------------------------------------------------------------*/ +@ Initialize Stack Pointers +@ SourceId : CORE_SourceId_002 +@ DesignId : CORE_DesignId_002 +@ Requirements: HL_SR478 + + .weak _coreInitStackPointer_ + .type _coreInitStackPointer_, %function + +_coreInitStackPointer_: + + cps #17 + ldr sp, fiqSp + cps #18 + ldr sp, irqSp + cps #19 + ldr sp, svcSp + cps #23 + ldr sp, abortSp + cps #27 + ldr sp, undefSp + cps #31 + ldr sp, userSp + bx lr + + +irqSp: .word 0x08000000+0x00000200 +fiqSp: .word 0x08000000+0x00000400 +svcSp: .word 0x08000000+0x00000500 +undefSp: .word 0x08000000+0x00000600 +abortSp: .word 0x08000000+0x00000700 +userSp: .word 0x08000000+0x00000800 + +/*-------------------------------------------------------------------------------*/ +@ Get CPSR Value +@ SourceId : CORE_SourceId_003 +@ DesignId : CORE_DesignId_003 +@ Requirements: + + .weak _getCPSRValue_ + .type _getCPSRValue_, %function + +_getCPSRValue_: + + mrs r0, CPSR + bx lr +/*-------------------------------------------------------------------------------*/ +@ Take CPU to IDLE state +@ SourceId : CORE_SourceId_004 +@ DesignId : CORE_DesignId_004 +@ Requirements: HL_SR493 + + .weak _gotoCPUIdle_ + .type _gotoCPUIdle_, %function + +_gotoCPUIdle_: + + WFI + nop + nop + nop + nop + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable VFP Unit +@ SourceId : CORE_SourceId_005 +@ DesignId : CORE_DesignId_006 +@ Requirements: HL_SR492, HL_SR476 + + .weak _coreEnableVfp_ + .type _coreEnableVfp_, %function + +_coreEnableVfp_: + + mrc p15, #0x00, r0, c1, c0, #0x02 + orr r0, r0, #0xF00000 + mcr p15, #0x00, r0, c1, c0, #0x02 + mov r0, #0x40000000 + fmxr fpexc, r0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Event Bus Export +@ SourceId : CORE_SourceId_006 +@ DesignId : CORE_DesignId_007 +@ Requirements: HL_SR479 + + .weak _coreEnableEventBusExport_ + .type _coreEnableEventBusExport_, %function + +_coreEnableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + orr r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Event Bus Export +@ SourceId : CORE_SourceId_007 +@ DesignId : CORE_DesignId_008 +@ Requirements: HL_SR481 + + .weak _coreDisableEventBusExport_ + .type _coreDisableEventBusExport_, %function + +_coreDisableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + bic r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable RAM ECC Support +@ SourceId : CORE_SourceId_008 +@ DesignId : CORE_DesignId_009 +@ Requirements: HL_SR480 + + .weak _coreEnableRamEcc_ + .type _coreEnableRamEcc_, %function + +_coreEnableRamEcc_: + + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable RAM ECC Support +@ SourceId : CORE_SourceId_009 +@ DesignId : CORE_DesignId_010 +@ Requirements: HL_SR482 + + .weak _coreDisableRamEcc_ + .type _coreDisableRamEcc_, %function + +_coreDisableRamEcc_: + + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Flash ECC Support +@ SourceId : CORE_SourceId_010 +@ DesignId : CORE_DesignId_011 +@ Requirements: HL_SR480 + + .weak _coreEnableFlashEcc_ + .type _coreEnableFlashEcc_, %function + +_coreEnableFlashEcc_: + + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Flash ECC Support +@ SourceId : CORE_SourceId_011 +@ DesignId : CORE_DesignId_012 +@ Requirements: HL_SR482 + + .weak _coreDisableFlashEcc_ + .type _coreDisableFlashEcc_, %function + +_coreDisableFlashEcc_: + + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Offset via Vic controller +@ SourceId : CORE_SourceId_012 +@ DesignId : CORE_DesignId_005 +@ Requirements: HL_SR483 + + .weak _coreEnableIrqVicOffset_ + .type _coreEnableIrqVicOffset_, %function + +_coreEnableIrqVicOffset_: + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x01000000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault status register +@ SourceId : CORE_SourceId_013 +@ DesignId : CORE_DesignId_013 +@ Requirements: HL_SR495 + + .weak _coreGetDataFault_ + .type _coreGetDataFault_, %function + +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault status register +@ SourceId : CORE_SourceId_014 +@ DesignId : CORE_DesignId_014 +@ Requirements: HL_SR495 + + .weak _coreClearDataFault_ + .type _coreClearDataFault_, %function + +_coreClearDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault status register +@ SourceId : CORE_SourceId_015 +@ DesignId : CORE_DesignId_015 +@ Requirements: HL_SR495 + + .weak _coreGetInstructionFault_ + .type _coreGetInstructionFault_, %function + +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault status register +@ SourceId : CORE_SourceId_016 +@ DesignId : CORE_DesignId_016 +@ Requirements: HL_SR495 + + .weak _coreClearInstructionFault_ + .type _coreClearInstructionFault_, %function + +_coreClearInstructionFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault address register +@ SourceId : CORE_SourceId_017 +@ DesignId : CORE_DesignId_017 +@ Requirements: HL_SR495 + + .weak _coreGetDataFaultAddress_ + .type _coreGetDataFaultAddress_, %function + +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault address register +@ SourceId : CORE_SourceId_018 +@ DesignId : CORE_DesignId_018 +@ Requirements: HL_SR495 + + .weak _coreClearDataFaultAddress_ + .type _coreClearDataFaultAddress_, %function + +_coreClearDataFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault address register +@ SourceId : CORE_SourceId_019 +@ DesignId : CORE_DesignId_019 +@ Requirements: HL_SR495 + + .weak _coreGetInstructionFaultAddress_ + .type _coreGetInstructionFaultAddress_, %function + +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault address register +@ SourceId : CORE_SourceId_020 +@ DesignId : CORE_DesignId_020 +@ Requirements: HL_SR495 + + .weak _coreClearInstructionFaultAddress_ + .type _coreClearInstructionFaultAddress_, %function + +_coreClearInstructionFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary data fault status register +@ SourceId : CORE_SourceId_021 +@ DesignId : CORE_DesignId_021 +@ Requirements: HL_SR496 + + .weak _coreGetAuxiliaryDataFault_ + .type _coreGetAuxiliaryDataFault_, %function + +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary data fault status register +@ SourceId : CORE_SourceId_022 +@ DesignId : CORE_DesignId_022 +@ Requirements: HL_SR496 + + .weak _coreClearAuxiliaryDataFault_ + .type _coreClearAuxiliaryDataFault_, %function + +_coreClearAuxiliaryDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary instruction fault status register +@ SourceId : CORE_SourceId_023 +@ DesignId : CORE_DesignId_023 +@ Requirements: HL_SR496 + + .weak _coreGetAuxiliaryInstructionFault_ + .type _coreGetAuxiliaryInstructionFault_, %function + +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary instruction fault status register +@ SourceId : CORE_SourceId_024 +@ DesignId : CORE_DesignId_024 +@ Requirements: HL_SR496 + + .weak _coreClearAuxiliaryInstructionFault_ + .type _coreClearAuxiliaryInstructionFault_, %function + +_coreClearAuxiliaryInstructionFault_: + + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable interrupts - R4 IRQ & FIQ +@ SourceId : CORE_SourceId_025 +@ DesignId : CORE_DesignId_025 +@ Requirements: HL_SR494 + + .weak _disable_interrupt_ + .type _disable_interrupt_, %function + +_disable_interrupt_: + + cpsid if + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable IRQ interrupt + + .weak _disable_IRQ_interrupt_ + .type _disable_IRQ_interrupt_, %function + +_disable_IRQ_interrupt_: + + cpsid i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable FIQ interrupt + + .weak _disable_FIQ_interrupt_ + .type _disable_FIQ_interrupt_, %function + +_disable_FIQ_interrupt_: + + cpsid f + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - R4 IRQ & FIQ + + .weak _enable_interrupt_ + .type _enable_interrupt_, %function + +_enable_interrupt_: + + cpsie if + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear ESM CCM errorss + + .weak _esmCcmErrorsClear_ + .type _esmCcmErrorsClear_, %function + +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + + +#if 1/*-------------------------------------------------------------------------------*/ +@ Work Around for Errata CORTEX-R4#57: +@ +@ Errata Description: +@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +@ Workaround: +@ Disable out-of-order single-precision floating point +@ multiply-accumulate instruction completion + + .weak _errata_CORTEXR4_57_ + .type _errata_CORTEXR4_57_, %function + +_errata_CORTEXR4_57_: + + push {r0} + mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register + pop {r0} + bx lr +#endif + +/*-------------------------------------------------------------------------------*/ +@ Work Around for Errata CORTEX-R4#66: +@ +@ Errata Description: +@ Register Corruption During A Load-Multiple Instruction At +@ an Exception Vector +@ Workaround: +@ Disable out-of-order completion for divide instructions in +@ Auxiliary Control register + + .weak _errata_CORTEXR4_66_ + .type _errata_CORTEXR4_66_, %function + +_errata_CORTEXR4_66_: + + push {r0} + mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register + orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion + @ for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register + pop {r0} + bx lr +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_dma.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_dma.c new file mode 100644 index 00000000000..8c4731594b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_dma.c @@ -0,0 +1,461 @@ +/** @file dma.c + * @brief DMA Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_dma.h" +#include "sys_vim.h" + +/** @fn void dmaEnable(void) + * @brief enables DMA module + * + * This function brings DMA out of reset + */ +/* SourceId : DMA_SourceId_001 */ +/* DesignId : DMA_DesignId_001 */ +/* Requirements: HL_SR167 */ +void dmaEnable( void ) +{ + dmaREG->GCTRL = 0x00010000U; /* enable dma */ + dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */ +} + +/** @fn void dmaDisable(void) + * @brief disables DMA module + * + * This function disables DMA module + */ +/* SourceId : DMA_SourceId_002 */ +/* DesignId : DMA_DesignId_002 */ +/* Requirements: HL_SR168 */ +void dmaDisable( void ) +{ + /* Wait until DMA's external bus has completed data transfer */ + /*SAFETYMCUSW 134 S MR: 12.2 "Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( dmaREG->GCTRL & DMA_GCTRL_BUSBUSY ) != 0U ) + { + } /* Wait */ + + /* Disable DMA module */ + dmaREG->GCTRL = 0U; +} + +/** @fn void dmaReqAssign(uint32 channel,uint32 reqline) + * @brief Assign DMA request lines to channels + * @param[in] channel DMA channel + * @param[in] reqline DMA request line + * + * This function assigns DMA request lines to channels + */ +/* SourceId : DMA_SourceId_003 */ +/* DesignId : DMA_DesignId_005 */ +/* Requirements: HL_SR169 */ +void dmaReqAssign( uint32 channel, uint32 reqline ) +{ + register uint32 i = 0U, j = 0U; + + i = channel >> 2U; /* Find the register to configure */ + j = channel - ( i << 2U ); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /* mapping channel 'i' to request line 'j' */ + dmaREG->DREQASI[ i ] &= ~( uint32 ) ( ( uint32 ) 0xFFU << j ); + dmaREG->DREQASI[ i ] |= ( reqline << j ); +} + +/** @fn uint32 dmaGetReq(uint32 channel) + * @brief Gets the request line number mapped to the selected channel + * @param[in] channel DMA channel + * + * This function returns the request line number mapped to the selected channel + */ +/* SourceId : DMA_SourceId_004 */ +/* DesignId : DMA_DesignId_006 */ +/* Requirements: HL_SR170 */ +uint32 dmaGetReq( uint32 channel ) +{ + register uint32 i = 0U, j = 0U; + + i = channel >> 2U; /* Find the register to configure */ + j = channel - ( i << 2U ); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + return ( ( dmaREG->DREQASI[ i ] >> j ) & 0xFFU ); +} + +/** @fn void dmaSetCtrlPacket(uint32 channel) + * @brief Set control packet + * + * This function sets control packet + */ +/* SourceId : DMA_SourceId_005 */ +/* DesignId : DMA_DesignId_003 */ +/* Requirements: HL_SR171 */ +void dmaSetCtrlPacket( uint32 channel, g_dmaCTRL g_dmaCTRLPKT ) +{ + register uint32 i = 0U, j = 0U; + + dmaRAMREG->PCP[ channel ].ISADDR = g_dmaCTRLPKT.SADD; + + dmaRAMREG->PCP[ channel ].IDADDR = g_dmaCTRLPKT.DADD; + + dmaRAMREG->PCP[ channel ].ITCOUNT = ( g_dmaCTRLPKT.FRCNT << 16U ) + | g_dmaCTRLPKT.ELCNT; + + dmaRAMREG->PCP[ channel ].CHCTRL = ( g_dmaCTRLPKT.RDSIZE << 14U ) + | ( g_dmaCTRLPKT.WRSIZE << 12U ) + | ( g_dmaCTRLPKT.TTYPE << 8U ) + | ( g_dmaCTRLPKT.ADDMODERD << 3U ) + | ( g_dmaCTRLPKT.ADDMODEWR << 1U ) + | ( g_dmaCTRLPKT.AUTOINIT ); + + dmaRAMREG->PCP[ channel ].CHCTRL |= ( g_dmaCTRLPKT.CHCTRL << 16U ); + + dmaRAMREG->PCP[ channel ].EIOFF = ( g_dmaCTRLPKT.ELDOFFSET << 16U ) + | ( g_dmaCTRLPKT.ELSOFFSET ); + + dmaRAMREG->PCP[ channel ].FIOFF = ( g_dmaCTRLPKT.FRDOFFSET << 16U ) + | ( g_dmaCTRLPKT.FRSOFFSET ); + + i = channel >> 3U; /* Find the register to write */ + j = channel - ( i << 3U ); /* Find the offset of the 4th bit */ + j = 7U - j; /* Reverse the order of the 4th bit offset */ + j = j << 2U; /* Find the bit location of the 4th bit to write */ + + dmaREG->PAR[ i ] &= ~( uint32 ) ( ( uint32 ) 0xFU << j ); + dmaREG->PAR[ i ] |= ( g_dmaCTRLPKT.PORTASGN << j ); +} + +/** @fn void dmaSetChEnable(uint32 channel,uint32 type) + * @brief Enable channel + * @param[in] channel DMA channel + * @param[in] type Type of triggering + * - DMA_HW: Enables the selected DMA channel for hardware triggering + * - DMA_SW: Enables the selected DMA channel for software triggering + * + * This function enables the DMA channel for hardware or software triggering + */ +/* SourceId : DMA_SourceId_006 */ +/* DesignId : DMA_DesignId_004 */ +/* Requirements: HL_SR172 */ +void dmaSetChEnable( uint32 channel, uint32 type ) +{ + if( type == ( uint32 ) DMA_HW ) + { + dmaREG->HWCHENAS = ( uint32 ) 1U << channel; + } + else if( type == ( uint32 ) DMA_SW ) + { + dmaREG->SWCHENAS = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } +} + +/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) + * @brief Assign Priority to the channel + * @param[in] channel DMA channel + * @param[in] priority Priority queue to which channel needs to be assigned + * - LOWPRIORITY : The selected channel will be assigned to low + * priority queue + * - HIGHPRIORITY: The selected channel will be assigned to high + * priority queue + * + * This function assigns the selected priority to the selected channel + */ +/* SourceId : DMA_SourceId_007 */ +/* DesignId : DMA_DesignId_007 */ +/* Requirements: HL_SR173 */ +void dmaSetPriority( uint32 channel, dmaPRIORITY_t priority ) +{ + if( priority == LOWPRIORITY ) + { + dmaREG->CHPRIOR = ( uint32 ) 1U << channel; + } + else + { + dmaREG->CHPRIOS = ( uint32 ) 1U << channel; + } +} + +/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype) + * @brief Enable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be enabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for the + * selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled for + * the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + * for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for the + * selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + * channel + * + * This function enables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_008 */ +/* DesignId : DMA_DesignId_008 */ +/* Requirements: HL_SR174 */ +void dmaEnableInterrupt( uint32 channel, dmaInterrupt_t inttype ) +{ + dmaREG->GCHIENAS = ( uint32 ) 1U << channel; + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAS = ( uint32 ) 1U << channel; + break; + + case LFS: + dmaREG->LFSINTENAS = ( uint32 ) 1U << channel; + break; + + case HBC: + dmaREG->HBCINTENAS = ( uint32 ) 1U << channel; + break; + + case BTC: + dmaREG->BTCINTENAS = ( uint32 ) 1U << channel; + break; + + default: + break; + } +} + +/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) + * @brief Disable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be disabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for the + * selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled for + * the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + * for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for the + * selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + * channel + * + * This function disables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_009 */ +/* DesignId : DMA_DesignId_009 */ +/* Requirements: HL_SR175 */ +void dmaDisableInterrupt( uint32 channel, dmaInterrupt_t inttype ) +{ + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAR = ( uint32 ) 1U << channel; + break; + + case LFS: + dmaREG->LFSINTENAR = ( uint32 ) 1U << channel; + break; + + case HBC: + dmaREG->HBCINTENAR = ( uint32 ) 1U << channel; + break; + + case BTC: + dmaREG->BTCINTENAR = ( uint32 ) 1U << channel; + break; + + default: + break; + } +} + +/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) + * @brief Configure start and end address of the region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * @param[in] start_add Start address of the the region + * @param[in] end_add End address of the region + * + * This function configure start and end address of the selected region + */ +/* SourceId : DMA_SourceId_010 */ +/* DesignId : DMA_DesignId_010 */ +/* Requirements: HL_SR176 */ +void dmaDefineRegion( dmaREGION_t region, uint32 start_add, uint32 end_add ) +{ + dmaREG->DMAMPR[ region ].STARTADD = start_add; + dmaREG->DMAMPR[ region ].ENDADD = end_add; +} + +/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean + * intenable) + * @brief Enable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * @param[in] access Access permission of the selected region + * - FULLACCESS + * - READONLY + * - WRITEONLY + * - NOACCESS + * @param[in] intenable Interrupt to be enabled or not + * - INTERRUPT_ENABLE : Enable interrupt for the selected region + * - INTERRUPT_DISABLE: Disable interrupt for the selected region + * + * This function enables the selected region with selected access permission with or + * without interrupt enable + */ +/* SourceId : DMA_SourceId_011 */ +/* DesignId : DMA_DesignId_011 */ +/* Requirements: HL_SR177 */ +void dmaEnableRegion( dmaREGION_t region, dmaRegionAccess_t access, boolean intenable ) +{ + dmaREG->DMAMPCTRL &= ~( uint32 ) ( ( uint32 ) 0xFFU << ( region * 8U ) ); + + /* Enable the region */ + dmaREG->DMAMPCTRL |= ( uint32 ) 1U << ( region * 8U ); + + /* Set access permission for the region */ + dmaREG->DMAMPCTRL |= ( uint32 ) access << ( ( region * 8U ) + 1U ); + + if( intenable ) + { + /* Enable interrupt */ + dmaREG->DMAMPCTRL |= ( uint32 ) 1U << ( ( region * 8U ) + 3U ); + } +} + +/** @fn void dmaDisableRegion(dmaREGION_t region) + * @brief Disable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * + * This function disables the selected region(no address checking done). + */ +/* SourceId : DMA_SourceId_012 */ +/* DesignId : DMA_DesignId_012 */ +/* Requirements: HL_SR178 */ +void dmaDisableRegion( dmaREGION_t region ) +{ + dmaREG->DMAMPCTRL &= ~( uint32 ) ( ( uint32 ) 1U << ( ( uint32 ) region * 8U ) ); +} + +/** @fn void dmaEnableParityCheck(void) + * @brief Enable Parity Check + * + * This function enables parity check + */ +/* SourceId : DMA_SourceId_013 */ +/* DesignId : DMA_DesignId_013 */ +/* Requirements: HL_SR179 */ +void dmaEnableParityCheck( void ) +{ + dmaREG->DMAPCR = 0xAU; +} + +/** @fn void dmaDisableParityCheck(void) + * @brief Disable Parity Check + * + * This function disables parity check + */ +/* SourceId : DMA_SourceId_014 */ +/* DesignId : DMA_DesignId_014 */ +/* Requirements: HL_SR180 */ +void dmaDisableParityCheck( void ) +{ + dmaREG->DMAPCR = 0x5U; +} + +/** @fn void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : DMA_SourceId_015 */ +/* DesignId : DMA_DesignId_015 */ +/* Requirements: HL_SR183 */ +void dmaGetConfigValue( dma_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { /* Do not pass Initial value as parameter as there is no DMA initialization API */ + } + else + { + config_reg->CONFIG_CHPRIOS = dmaREG->CHPRIOS; + config_reg->CONFIG_GCHIENAS = dmaREG->GCHIENAS; + config_reg->CONFIG_DREQASI[ 0U ] = dmaREG->DREQASI[ 0U ]; + config_reg->CONFIG_DREQASI[ 1U ] = dmaREG->DREQASI[ 1U ]; + config_reg->CONFIG_DREQASI[ 2U ] = dmaREG->DREQASI[ 2U ]; + config_reg->CONFIG_DREQASI[ 3U ] = dmaREG->DREQASI[ 3U ]; + config_reg->CONFIG_DREQASI[ 4U ] = dmaREG->DREQASI[ 4U ]; + config_reg->CONFIG_DREQASI[ 5U ] = dmaREG->DREQASI[ 5U ]; + config_reg->CONFIG_DREQASI[ 6U ] = dmaREG->DREQASI[ 6U ]; + config_reg->CONFIG_DREQASI[ 7U ] = dmaREG->DREQASI[ 7U ]; + config_reg->CONFIG_FTCINTENAS = dmaREG->FTCINTENAS; + config_reg->CONFIG_LFSINTENAS = dmaREG->LFSINTENAS; + config_reg->CONFIG_HBCINTENAS = dmaREG->HBCINTENAS; + config_reg->CONFIG_BTCINTENAS = dmaREG->BTCINTENAS; + config_reg->CONFIG_DMAPCR = dmaREG->DMAPCR; + config_reg->CONFIG_DMAMPCTRL = dmaREG->DMAMPCTRL; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_intvecs.S b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_intvecs.S new file mode 100644 index 00000000000..6747c0d14ac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_intvecs.S @@ -0,0 +1,76 @@ +/*--------------------------------------------------------------------------- + sys_intvecs.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +----------------------------------------------------------------------------*/ + + .syntax unified + .cpu cortex-r4 + .arm + + .section .intvecs,"a",%progbits + .type resetEntry, %object + .size resetEntry, .-resetEntry + +/*-------------------------------------------------------------------------------*/ +@ import reference for interrupt routines + + .extern _c_int00 + .extern FreeRTOS_SVC_Handler + .extern FreeRTOS_IRQ_Handler + .extern _dabort + .extern phantomInterrupt + .weak resetEntry + +/*-------------------------------------------------------------------------------*/ +@ interrupt vectors + +resetEntry: + b _c_int00 +undefEntry: + b undefEntry +svcEntry: + b FreeRTOS_SVC_Handler +prefetchEntry: + b prefetchEntry +dataAbortEntry: + b _dabort + b phantomInterrupt + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * IRQVECREG: 0x18 - 0x1B0 = 0xFFFFFE70. */ + b FreeRTOS_IRQ_Handler + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * FIQVECREG: 0x1C - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_link.ld b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_link.ld new file mode 100644 index 00000000000..e94c71c18ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_link.ld @@ -0,0 +1,273 @@ +/*----------------------------------------------------------------------------*/ +/* sys_link.ld */ +/* */ +/* (c) Texas Instruments 2009-2014, All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Entry Point */ +ENTRY(_c_int00) + +/* Highest address of the stack */ +_estack = 0x8030000; /* end of 192K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1M + 256K + RAM (xrw) : ORIGIN = 0x08000000, LENGTH = 128K + 64K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/** Common sizes + * 0x0000 0001 == 1B + * 0x0000 0002 == 2B + * 0x0000 0004 == 4B + * 0x0000 0008 == 8B + * 0x0000 0010 == 16B + * 0x0000 0020 == 32B + * 0x0000 0040 == 64B + * 0x0000 0080 == 128B + * 0x0000 0100 == 256B + * 0x0000 0200 == 512B + * 0x0000 0400 == 1K + * 0x0000 0800 == 2K + * 0x0000 1000 == 4K + * 0x0000 2000 == 8K + * 0x0000 4000 == 16K + * 0x0000 8000 == 32K + * 0x0001 0000 == 64K + * 0x0002 0000 == 128K + * 0x0003 0000 == 192K + * 0x0004 0000 == 256K + * 0x0008 0000 == 512K + * 0x0010 0000 == 1024K/1MB + * 0x0014 0000 == 1280KB/1.25 MB + * 0x0020 0000 == 2048K/2MB + * 0x0040 0000 == 4096K/4MB + * 0x0080 0000 == 8192K/8MB + * 0x0100 0000 == 16MB + * 0x0200 0000 == 32MB + * 0x0400 0000 == 64MB + * 0x0800 0000 == 128MB +*/ + +/* Variables used by FreeRTOS-MPU. */ +/* Cover the entirety of flash */ +__FLASH_segment_start__ = ORIGIN( FLASH ); +__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( FLASH ); + +/* Cover the all of System RAM */ +__SRAM_segment_start__ = ORIGIN( RAM ); +__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM ); + +/* All functions marked as "PRIVILEGED_FUNCTION" get placed in this section */ +__privileged_functions_region_size__ = 64K; +__privileged_functions_start__ = ORIGIN( FLASH ); +__privileged_functions_end__ = __privileged_functions_start__ + __privileged_functions_region_size__; + +/* All variables marked as "PRIVILEGED_DATA" get placed in this section */ +__privileged_data_region_size__ = 32K; +__privileged_data_start__ = ORIGIN( RAM ); +__privileged_data_end__ = ORIGIN( RAM ) + __privileged_data_region_size__; + +/* A section of memory at the start of "PRIVILEGED_DATA" for different operating mode stacks */ +__privileged_stacks_region_size__ = 2K; +__privileged_stacks_start__ = ORIGIN( RAM ); +__privileged_stacks_end__ = ORIGIN( RAM ) + __privileged_stacks_region_size__; + +/* Memory block for various dev kit peripherals */ +__peripherals_start__ = 0xF0000000; +__peripherals_length__ = 256M; +__peripherals_end__ = __peripherals_start__ + __peripherals_length__; + +/* Seperate memory block for privileged system */ +__privileged_system_start__ = 0xFFF80000; +__privileged_system_length__ = 512K; +__privileged_system_end__ = __privileged_system_start__ + __privileged_system_length__; + + +/* The first 2K of space in RAM is used for different processor mode stacks */ +__privileged_stack_region_size = 0x800; + +/* Define output sections */ +SECTIONS +{ + /* The ISR vector goes first into RAM */ + .privileged_functions : + { + . = ALIGN(4); + KEEP(*(.intvecs)) + . = ALIGN(4); + + *(privileged_functions) + . = ALIGN(4); + /* Fill rest of the region with a known value */ + FILL(0xADDEADDE); + /* Ensure that non-privileged code is placed after the region reserved for + * privileged kernel code. This is done for MPU Region Alignment */ + /* Note that dot (.) actually refers to the byte offset from the start of + * the current section (.privileged_functions in this case). As a result, + * setting dot (.) to a value sets the size of the section. */ + . = __privileged_functions_region_size__; + } >FLASH + + .freertos_system_calls : + { + . = ALIGN(4); + /* Place the FreeRTOS System Calls first in the unprivileged region. */ + __syscalls_flash_start__ = .; + *(freertos_system_calls) + __syscalls_flash_end__ = .; + . = ALIGN(4); + + } >FLASH + + /* This variable is used in portASM.S to determine if a FreeRTOS System Call + * was raised from this specific section of flash */ + __syscalls_flash_length__ = __syscalls_flash_end__ - __syscalls_flash_start__; + + /* The program code and other data goes into RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into RAM */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _siPrivData = LOADADDR(.privileged_data); + /* FreeRTOS kernel data. */ + .privileged_data : + { + /* Leave a block of memory for different Processor mode stacks. + * These are set in sys_core.S */ + . = ALIGN(4); + /* Mark the start of the region for debugging purposes. */ + __start_privileged_stack_region = .; + . = __privileged_stack_region_size; + . = ALIGN(4); + /* Mark the end of the region for debugging purposes. */ + __end_privileged_stack_region = .; + + __start_priv_data = .; /* Create a global symbol at privileged data start. */ + *(privileged_data) + . = ALIGN(4); + __end_priv_data = .; /* Create a global symbol at privileged data end. */ + FILL(0xADDE); /* Fill RAM with known value */ + /* Ensure that non-privileged data is placed after the region reserved for + * privileged kernel data. */ + /* Note that dot (.) actually refers to the byte offset from the start of + * the current section (.privileged_data in this case). As a result, setting + * dot (.) to a value sets the size of the section. */ + . = __privileged_data_region_size__; + . = ALIGN(4); + } >RAM AT> FLASH + + /* Used by sys_startup.c to initialize data */ + _sidata = LOADADDR(.data); + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_main.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_main.c new file mode 100644 index 00000000000..d6b6ff28571 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_main.c @@ -0,0 +1,77 @@ +/** @file sys_main.c + * @brief Application main file + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains an empty main function, + * which can be used for the application. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void main(void) + * @brief Application main function + * @note This function is empty by default. + * + * This function is called after startup. + * The user can use this function to implement the application. + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +uint8 emacAddress[ 6U ] = { 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }; +uint32 emacPhyAddress = 0U; + +int auto_gen_main( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + return 0; +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pcr.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pcr.c new file mode 100644 index 00000000000..4293e280028 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pcr.c @@ -0,0 +1,731 @@ +/** @file sys_pcr.c + * @brief PCR Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pcr.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame) + * @brief Set the peripheral protection of the selected frame + * @param[in] peripheral_Frame - Peripheral frame to be protected + * + * This function sets the protection for the selected frame. + */ +/* SourceId : PCR_SourceId_001 */ +/* DesignId : PCR_DesignId_001 */ +/* Requirements : HL_SR41 */ +void peripheral_Frame_Protection_Set( peripheral_Frame_Select_t peripheral_Frame ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = ( peripheral_Frame.Peripheral_CS >> 3U ); + Quarant_selct = ( uint32 ) ( peripheral_Frame.Peripheral_Quadrant + << ( ( peripheral_Frame.Peripheral_CS & 7U ) << 2U ) ); + + if( chip_select_grp >= 3U ) + { + pcrREG->PPROTSET3 = Quarant_selct; + } + else if( chip_select_grp >= 2U ) + { + pcrREG->PPROTSET2 = Quarant_selct; + } + else if( chip_select_grp >= 1U ) + { + pcrREG->PPROTSET1 = Quarant_selct; + } + else + { + pcrREG->PPROTSET0 = Quarant_selct; + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame) + * @brief Clear the peripheral protection of the selected frame + * @param[in] peripheral_Frame - Peripheral frame to be out of protection + * + * This function clears the protection set for the selected frame. + */ +/* SourceId : PCR_SourceId_002 */ +/* DesignId : PCR_DesignId_002 */ +/* Requirements : HL_SR42 */ +void peripheral_Frame_Protection_Clr( peripheral_Frame_Select_t peripheral_Frame ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = ( peripheral_Frame.Peripheral_CS >> 3U ); + Quarant_selct = ( uint32 ) ( peripheral_Frame.Peripheral_Quadrant + << ( ( peripheral_Frame.Peripheral_CS & 7U ) << 2U ) ); + + if( chip_select_grp >= 3U ) + { + pcrREG->PPROTCLR3 = Quarant_selct; + } + else if( chip_select_grp >= 2U ) + { + pcrREG->PPROTCLR2 = Quarant_selct; + } + else if( chip_select_grp >= 1U ) + { + pcrREG->PPROTCLR1 = Quarant_selct; + } + else + { + pcrREG->PPROTCLR0 = Quarant_selct; + } + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame) + * @brief Take the selected peripheral to powerdown + * @param[in] peripheral_Frame - Peripheral frame to be taken to powerdown + * + * This function will set the selected peripheral frame to powerdown. + */ +/* SourceId : PCR_SourceId_003 */ +/* DesignId : PCR_DesignId_003 */ +/* Requirements : HL_SR43 */ +void peripheral_Frame_Powerdown_Set( peripheral_Frame_Select_t peripheral_Frame ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = ( peripheral_Frame.Peripheral_CS >> 3U ); + Quarant_selct = ( uint32 ) ( peripheral_Frame.Peripheral_Quadrant + << ( ( peripheral_Frame.Peripheral_CS & 7U ) << 2U ) ); + + if( chip_select_grp >= 3U ) + { + pcrREG->PSPWRDWNSET3 = Quarant_selct; + } + else if( chip_select_grp >= 2U ) + { + pcrREG->PSPWRDWNSET2 = Quarant_selct; + } + else if( chip_select_grp >= 1U ) + { + pcrREG->PSPWRDWNSET1 = Quarant_selct; + } + else + { + pcrREG->PSPWRDWNSET0 = Quarant_selct; + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame) + * @brief Bring the selected peripheral frame out of powerdown + * @param[in] peripheral_Frame - Peripheral frame to be taken out of powerdown + * + * This function will bring the selected peripheral frame out of powerdown. + */ +/* SourceId : PCR_SourceId_004 */ +/* DesignId : PCR_DesignId_004 */ +/* Requirements : HL_SR44 */ +void peripheral_Frame_Powerdown_Clr( peripheral_Frame_Select_t peripheral_Frame ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + uint32 chip_select_grp; + uint32 Quarant_selct; + + chip_select_grp = ( peripheral_Frame.Peripheral_CS >> 3U ); + Quarant_selct = ( uint32 ) ( peripheral_Frame.Peripheral_Quadrant + << ( ( peripheral_Frame.Peripheral_CS & 7U ) << 2U ) ); + + if( chip_select_grp >= 3U ) + { + pcrREG->PSPWRDWNCLR3 = Quarant_selct; + } + else if( chip_select_grp >= 2U ) + { + pcrREG->PSPWRDWNCLR2 = Quarant_selct; + } + else if( chip_select_grp >= 1U ) + { + pcrREG->PSPWRDWNCLR1 = Quarant_selct; + } + else + { + pcrREG->PSPWRDWNCLR0 = Quarant_selct; + } + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t + * peripheral_Memory_Frame_CS) + * @brief Set the peripheral memory protection of the selected frame + * @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be protected + * + * This function sets the protection for the selected peripheral memory frame. + */ +/* SourceId : PCR_SourceId_005 */ +/* DesignId : PCR_DesignId_017 */ +/* Requirements : HL_SR57 */ +void peripheral_Mem_Frame_Prot_Set( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = ( peripheral_Memory_Frame_CS >> 5U ); + + if( chip_select_grp >= 1U ) + { + pcrREG->PMPROTSET1 = ( uint32 ) 1U << ( peripheral_Memory_Frame_CS & 0xFU ); + } + else + { + pcrREG->PMPROTSET0 = ( uint32 ) 1U << peripheral_Memory_Frame_CS; + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t + * peripheral_Memory_Frame_CS) + * @brief Clear the peripheral memory protection of the selected frame + * @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be cleared from + * protection + * + * This function clears the protection set for the selected peripheral memory frame. + */ +/* SourceId : PCR_SourceId_006 */ +/* DesignId : PCR_DesignId_018 */ +/* Requirements : HL_SR58 */ +void peripheral_Mem_Frame_Prot_Clr( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = ( peripheral_Memory_Frame_CS >> 5U ); + + if( chip_select_grp >= 1U ) + { + pcrREG->PMPROTCLR1 = ( uint32 ) 1U << ( peripheral_Memory_Frame_CS & 0xFU ); + } + else + { + pcrREG->PMPROTCLR0 = ( uint32 ) 1U << peripheral_Memory_Frame_CS; + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t + * peripheral_Memory_Frame_CS) + * @brief Take the selected peripheral memory frame to powerdown + * @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken to + * powerdown + * + * This function will set the selected peripheral memory frame to powerdown. + */ +/* SourceId : PCR_SourceId_007 */ +/* DesignId : PCR_DesignId_019 */ +/* Requirements : HL_SR59 */ +void peripheral_Mem_Frame_Pwrdwn_Set( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = ( peripheral_Memory_Frame_CS >> 5U ); + + if( chip_select_grp >= 1U ) + { + pcrREG->PCSPWRDWNSET0 = ( uint32 ) 1U << ( peripheral_Memory_Frame_CS & 0xFU ); + } + else + { + pcrREG->PCSPWRDWNSET1 = ( uint32 ) 1U << peripheral_Memory_Frame_CS; + } + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + +/** @fn void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t + * peripheral_Memory_Frame_CS) + * @brief Bring the selected peripheral Memory frame out of powerdown + * @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken out of + * powerdown + * + * This function will bring the selected peripheral memory frame out of powerdown. + */ +/* SourceId : PCR_SourceId_008 */ +/* DesignId : PCR_DesignId_020 */ +/* Requirements : HL_SR60 */ +void peripheral_Mem_Frame_Pwrdwn_Clr( + peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + uint32 chip_select_grp; + + chip_select_grp = ( peripheral_Memory_Frame_CS >> 5U ); + + if( chip_select_grp >= 1U ) + { + pcrREG->PCSPWRDWNCLR0 = ( uint32 ) 1U << ( peripheral_Memory_Frame_CS & 0xFU ); + } + else + { + pcrREG->PCSPWRDWNCLR1 = ( uint32 ) 1U << peripheral_Memory_Frame_CS; + } + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + +/** @fn void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) + * @brief Set the peripheral protection of all the selected frames + * @param[in] peripheral_Quad_CS - All Peripheral frames to be protected + * + * This function sets the protection for all the selected frames. + */ +/* SourceId : PCR_SourceId_009 */ +/* DesignId : PCR_DesignId_005 */ +/* Requirements : HL_SR45 */ +void peripheral_Protection_Set( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + pcrREG->PPROTSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PPROTSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PPROTSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PPROTSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +/** @fn void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) + * @brief Clear the peripheral protection of all the selected frames + * @param[in] peripheral_Quad_CS - All Peripheral frames to be out of protection. + * + * This function clears the protection set for all the selected frame. + */ +/* SourceId : PCR_SourceId_010 */ +/* DesignId : PCR_DesignId_006 */ +/* Requirements : HL_SR46 */ +void peripheral_Protection_Clr( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ) +{ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + pcrREG->PPROTCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PPROTCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PPROTCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PPROTCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/** @fn void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) + * @brief Take all the selected peripheral frame to powerdown + * @param[in] peripheral_Quad_CS - Peripheral frames to be taken to powerdown + * + * This function will set all the selected peripheral frame to powerdown. + */ +/* SourceId : PCR_SourceId_011 */ +/* DesignId : PCR_DesignId_008 */ +/* Requirements : HL_SR48 */ +void peripheral_Powerdown_Set( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + pcrREG->PSPWRDWNSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PSPWRDWNSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PSPWRDWNSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PSPWRDWNSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + +/** @fn void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) + * @brief Bring all the selected peripheral frame out of powerdown + * @param[in] peripheral_Quad_CS - Peripheral frames to be taken out of powerdown + * + * This function will bring all the selected peripheral frame out of powerdown. + */ +/* SourceId : PCR_SourceId_012 */ +/* DesignId : PCR_DesignId_009 */ +/* Requirements : HL_SR49 */ +void peripheral_Powerdown_Clr( peripheral_Quad_ChipSelect_t peripheral_Quad_CS ) +{ + /* USER CODE BEGIN (35) */ + /* USER CODE END */ + + pcrREG->PSPWRDWNCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; + pcrREG->PSPWRDWNCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; + pcrREG->PSPWRDWNCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; + pcrREG->PSPWRDWNCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; + + /* USER CODE BEGIN (36) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t + * peripheral_Memory_CS) + * @brief Set the peripheral memory protection of all the selected frame + * @param[in] peripheral_Memory_CS - Peripheral memory frames to be protected + * + * This function sets the protection for all the selected peripheral memory frame. + */ +/* SourceId : PCR_SourceId_013 */ +/* DesignId : PCR_DesignId_011 */ +/* Requirements : HL_SR51 */ +void peripheral_Memory_Protection_Set( + peripheral_Memory_ChipSelect_t peripheral_Memory_CS ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + pcrREG->PMPROTSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PMPROTSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t + * peripheral_Memory_CS) + * @brief Clear the peripheral memory protection of all the selected frame + * @param[in] peripheral_Memory_CS - Peripheral memory frames to be cleared from + * protection + * + * This function clears the protection set for all the selected peripheral memory frame. + */ +/* SourceId : PCR_SourceId_014 */ +/* DesignId : PCR_DesignId_012 */ +/* Requirements : HL_SR52 */ +void peripheral_Memory_Protection_Clr( + peripheral_Memory_ChipSelect_t peripheral_Memory_CS ) +{ + /* USER CODE BEGIN (41) */ + /* USER CODE END */ + + pcrREG->PMPROTCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PMPROTCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t + * peripheral_Memory_CS) + * @brief Take all the selected peripheral memory frame to powerdown + * @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken to powerdown + * + * This function will set all the selected peripheral memory frame to powerdown. + */ +/* SourceId : PCR_SourceId_015 */ +/* DesignId : PCR_DesignId_014 */ +/* Requirements : HL_SR54 */ +void peripheral_Memory_Powerdown_Set( peripheral_Memory_ChipSelect_t peripheral_Memory_CS ) +{ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + + pcrREG->PCSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PCSPWRDWNSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + + /* USER CODE BEGIN (45) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t + * peripheral_Memory_CS) + * @brief Bring all the selected peripheral Memory frame out of powerdown + * @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken out of + * powerdown + * + * This function will bring all the selected peripheral memory frame out of powerdown. + */ +/* SourceId : PCR_SourceId_016 */ +/* DesignId : PCR_DesignId_015 */ +/* Requirements : HL_SR55 */ +void peripheral_Memory_Powerdown_Clr( peripheral_Memory_ChipSelect_t peripheral_Memory_CS ) +{ + /* USER CODE BEGIN (47) */ + /* USER CODE END */ + + pcrREG->PCSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; + pcrREG->PCSPWRDWNCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; + + /* USER CODE BEGIN (48) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/** @fn void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS) + * @brief Get the powerdown status of the peripheral frames. + * @param[out] peripheral_Quad_CS Peripheral frames power down status + * + * This function gets the powerdown status of the peripheral frames. + */ +/* SourceId : PCR_SourceId_017 */ +/* DesignId : PCR_DesignId_010 */ +/* Requirements : HL_SR50 */ +void peripheral_Powerdown_Status( peripheral_Quad_ChipSelect_t * peripheral_Quad_CS ) +{ + /* USER CODE BEGIN (50) */ + /* USER CODE END */ + + peripheral_Quad_CS->Peripheral_Quad0_3_CS0_7 = pcrREG->PSPWRDWNSET0; + peripheral_Quad_CS->Peripheral_Quad4_7_CS8_15 = pcrREG->PSPWRDWNSET1; + peripheral_Quad_CS->Peripheral_Quad8_11_CS16_23 = pcrREG->PSPWRDWNSET2; + peripheral_Quad_CS->Peripheral_Quad12_15_CS24_31 = pcrREG->PSPWRDWNSET3; + + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (52) */ +/* USER CODE END */ + +/** @fn void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS + * ) + * @brief Get the protection status of the peripheral frames + * @param[out] peripheral_Quad_CS Peripheral frames protection status + * + * This function gets the protection status of the peripheral frames. + */ +/* SourceId : PCR_SourceId_018 */ +/* DesignId : PCR_DesignId_007 */ +/* Requirements : HL_SR47 */ +void peripheral_Protection_Status( peripheral_Quad_ChipSelect_t * peripheral_Quad_CS ) +{ + /* USER CODE BEGIN (53) */ + /* USER CODE END */ + + peripheral_Quad_CS->Peripheral_Quad0_3_CS0_7 = pcrREG->PPROTSET0; + peripheral_Quad_CS->Peripheral_Quad4_7_CS8_15 = pcrREG->PPROTSET1; + peripheral_Quad_CS->Peripheral_Quad8_11_CS16_23 = pcrREG->PPROTSET2; + peripheral_Quad_CS->Peripheral_Quad12_15_CS24_31 = pcrREG->PPROTSET3; + + /* USER CODE BEGIN (54) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* + * peripheral_Memory_CS) + * @brief Get the protection set of all the peripheral Memory frame + * @param[out] peripheral_Memory_CS Peripheral memory frames protection status + * + * This function gets the protection status of all the peripheral Memory frame. + */ +/* SourceId : PCR_SourceId_019 */ +/* DesignId : PCR_DesignId_013 */ +/* Requirements : HL_SR53 */ +void peripheral_Memory_Protection_Status( + peripheral_Memory_ChipSelect_t * peripheral_Memory_CS ) +{ + /* USER CODE BEGIN (56) */ + /* USER CODE END */ + + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read" */ + peripheral_Memory_CS->Peripheral_Mem_CS0_31 = pcrREG->PMPROTSET0; + peripheral_Memory_CS->Peripheral_Mem_CS32_63 = pcrREG->PMPROTSET1; + + /* USER CODE BEGIN (57) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (58) */ +/* USER CODE END */ + +/** @fn void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* + * peripheral_Memory_CS) + * @brief Get the powerdown status of all the peripheral Memory frame + * @param[out] peripheral_Memory_CS Peripheral memory frames powerdown status + * + * This function gets the powerdown status of all the peripheral Memory frame. + */ +/* SourceId : PCR_SourceId_020 */ +/* DesignId : PCR_DesignId_016 */ +/* Requirements : HL_SR56 */ +void peripheral_Memory_Powerdown_Status( + peripheral_Memory_ChipSelect_t * peripheral_Memory_CS ) +{ + /* USER CODE BEGIN (59) */ + /* USER CODE END */ + + peripheral_Memory_CS->Peripheral_Mem_CS0_31 = pcrREG->PCSPWRDWNSET0; + peripheral_Memory_CS->Peripheral_Mem_CS32_63 = pcrREG->PCSPWRDWNSET1; + + /* USER CODE BEGIN (60) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ + +/** @fn void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : PCR_SourceId_021 */ +/* DesignId : PCR_DesignId_021 */ +/* Requirements : HL_SR61 */ +void pcrGetConfigValue( pcr_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { /* Do not pass Initial value as parameter as there is no PCR initialization API */ + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PMPROTSET0 = pcrREG->PMPROTSET0; + config_reg->CONFIG_PMPROTSET1 = pcrREG->PMPROTSET1; + config_reg->CONFIG_PPROTSET0 = pcrREG->PPROTSET0; + config_reg->CONFIG_PPROTSET1 = pcrREG->PPROTSET1; + config_reg->CONFIG_PPROTSET2 = pcrREG->PPROTSET2; + config_reg->CONFIG_PPROTSET3 = pcrREG->PPROTSET3; + config_reg->CONFIG_PCSPWRDWNSET0 = pcrREG->PCSPWRDWNSET0; + config_reg->CONFIG_PCSPWRDWNSET1 = pcrREG->PCSPWRDWNSET1; + config_reg->CONFIG_PSPWRDWNSET0 = pcrREG->PSPWRDWNSET0; + config_reg->CONFIG_PSPWRDWNSET1 = pcrREG->PSPWRDWNSET1; + config_reg->CONFIG_PSPWRDWNSET2 = pcrREG->PSPWRDWNSET2; + config_reg->CONFIG_PSPWRDWNSET3 = pcrREG->PSPWRDWNSET3; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_phantom.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_phantom.c new file mode 100644 index 00000000000..a219d0be6eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_phantom.c @@ -0,0 +1,66 @@ +/** @file sys_phantom.c + * @brief Phantom Interrupt Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Phantom Interrupt Handler + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_common.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Phantom Interrupt Handler */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +void phantomInterrupt( void ) +{ + /* USER CODE BEGIN (2) */ + for( ;; ) + { + } + + /* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pmm.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pmm.c new file mode 100644 index 00000000000..523d4b027f8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pmm.c @@ -0,0 +1,463 @@ +/** @file sys_pmm.c + * @brief PCR Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pmm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void pmmInit(void) + * @brief Initializes the PMM Driver + * + * This function initializes the PMM module. + */ +/* SourceId : PMM_SourceId_001 */ +/* DesignId : PMM_DesignId_001 */ +/* Requirements : HL_SR63 */ +void pmmInit( void ) +{ + /*Disable clocks to all logic domains*/ + pmmREG->PDCLKDISREG = 0xFU; + /*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/ + pmmREG->GLOBALCTRL1 = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0U; /*from GUI*/ + /*Power on the logic power domains*/ + pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE; + /*Power on the memory-only power domains*/ + pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE; + + /*wait till Logic Power Domain PD2 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->LOGICPDPWRSTAT[ PMM_LOGICPD2 ] & PMM_LOGICPDPWRSTAT_DOMAINON ) + == 0U ) + { + } /* Wait */ + + /*wait till Logic Power Domain PD3 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->LOGICPDPWRSTAT[ PMM_LOGICPD3 ] & PMM_LOGICPDPWRSTAT_DOMAINON ) + == 0U ) + { + } /* Wait */ + + /*wait till Logic Power Domain PD5 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->LOGICPDPWRSTAT[ PMM_LOGICPD5 ] & PMM_LOGICPDPWRSTAT_DOMAINON ) + == 0U ) + { + } /* Wait */ + + /*wait till Memory Only Power Domain RAM_PD1 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->MEMPDPWRSTAT[ PMM_MEMPD1 ] & PMM_MEMPDPWRSTAT_DOMAINON ) == 0U ) + { + } /* Wait */ + + /*wait till Memory Only Power Domain RAM_PD2 turns ON*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->MEMPDPWRSTAT[ PMM_MEMPD2 ] & PMM_MEMPDPWRSTAT_DOMAINON ) == 0U ) + { + } /* Wait */ + + if( ( pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA ) == 0U ) + { + /* Enable clocks for the selected logic domain */ + pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE; + } +} + +/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns on Logic Power Domain + * @param[in] logicPD - Power Domain to be turned on + * - PMM_LOGICPD2: Power domain PD2 will be turned on + * - PMM_LOGICPD3: Power domain PD3 will be turned on + * - PMM_LOGICPD4: Power domain PD4 will be turned on + * - PMM_LOGICPD5: Power domain PD5 will be turned on + * + * This function turns on the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_002 */ +/* DesignId : PMM_DesignId_002 */ +/* Requirements : HL_SR67 */ +void pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + if( logicPD != PMM_LOGICPD1 ) + { + /* Power on the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) + | 0x05000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) + | 0x00050000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) + | 0x00000500U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) + | 0x00000005U; + } + + /* Wait until the power domain turns on */ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LOGICPDPWRSTAT_DOMAINON ) == 0U ) + { + } /* Wait */ + + if( ( pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA ) == 0U ) + { + /* Enable clocks to the power domain */ + pmmREG->PDCLKDISCLRREG = ( uint32 ) 1U << ( uint32 ) logicPD; + } + } +} + +/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD) + * @brief Turns on Memory Power Domain + * @param[in] memPD - Power Domain to be tured on + * - PMM_MEMPD1: Power domain RAM_PD1 will be turned on + * - PMM_MEMPD2: Power domain RAM_PD2 will be turned on + * - PMM_MEMPD3: Power domain RAM_PD3 will be turned on + * + * This function turns on the selected Memory Power Domain + * + */ +/* SourceId : PMM_SourceId_003 */ +/* DesignId : PMM_DesignId_003 */ +/* Requirements : HL_SR66 */ +void pmmTurnONMemPowerDomain( pmm_MemPD_t memPD ) +{ + /* Power on the domain */ + if( memPD == PMM_MEMPD1 ) + { + pmmREG->MEMPDPWRCTRL0 = ( pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x05000000U; + } + else if( memPD == PMM_MEMPD2 ) + { + pmmREG->MEMPDPWRCTRL0 = ( pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x00050000U; + } + else + { + pmmREG->MEMPDPWRCTRL0 = ( pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000500U; + } + + /*Wait until the power domain turns on*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->MEMPDPWRSTAT[ memPD ] & PMM_MEMPDPWRSTAT_DOMAINON ) == 0U ) + { + } /* Wait */ +} + +/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns off Logic Power Domain + * @param[in] logicPD - Power Domain to be tured off + * - PMM_LOGICPD2: Power domain PD2 will be turned off + * - PMM_LOGICPD3: Power domain PD3 will be turned off + * - PMM_LOGICPD4: Power domain PD4 will be turned off + * - PMM_LOGICPD5: Power doamin PD5 will be turned off + * + * This function turns off the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_004 */ +/* DesignId : PMM_DesignId_004 */ +/* Requirements : HL_SR67 */ +void pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + if( logicPD != PMM_LOGICPD1 ) + { + /* Disable all clocks to the power domain */ + pmmREG->PDCLKDISSETREG = ( uint32 ) 1U << ( uint32 ) logicPD; + + /* Power down the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue*/ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) + | 0x0A000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) + | 0x000A0000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) + | 0x00000A00U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) + | 0x0000000AU; + } + + /* Wait until the power domain turns off */ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT ) + != 0U ) + { + } /* Wait */ + } +} + +/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD) + * @brief Turns off Memory Power Domain + * @param[in] memPD - Power Domain to be tured off + * - PMM_MEMPD1: Power domain RAM_PD1 will be turned off + * - PMM_MEMPD2: Power domain RAM_PD2 will be turned off + * - PMM_MEMPD3: Power domain RAM_PD3 will be turned off + * + * This function turns off the selected Memory Power Domain + * + */ +/* SourceId : PMM_SourceId_005 */ +/* DesignId : PMM_DesignId_005 */ +/* Requirements : HL_SR66 */ +void pmmTurnOFFMemPowerDomain( pmm_MemPD_t memPD ) +{ + /* Power down the domain */ + if( memPD == PMM_MEMPD1 ) + { + pmmREG->MEMPDPWRCTRL0 = ( pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x0A000000U; + } + else if( memPD == PMM_MEMPD2 ) + { + pmmREG->MEMPDPWRCTRL0 = ( pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x000A0000U; + } + else + { + pmmREG->MEMPDPWRCTRL0 = ( pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000A00U; + } + + /*Wait until the power domain turns off*/ + /*SAFETYMCUSW 28 D MR:NA "Wait for hardware status bit" */ + while( ( pmmREG->MEMPDPWRSTAT[ memPD ] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT ) != 0U ) + { + } /* Wait */ +} + +/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) + * @brief Check if the power domain is active or not + * @param[in] logicPD - Power Domain to be be checked + * - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not + * - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not + * - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not + * - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not + * @return The function will return: + * - TRUE : When the selected power domain is in Active state. + * - FALSE: When the selected power domain is in OFF state. + * + * This function checks whether the selected power domain is active or not. + * + */ +/* SourceId : PMM_SourceId_006 */ +/* DesignId : PMM_DesignId_006 */ +/* Requirements : HL_SR62 */ +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ) +{ + boolean status; + + if( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LOGICPDPWRSTAT_DOMAINON ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + return status; +} + +/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD) + * @brief Check if the power domain is active or not + * @param[in] memPD - Power Domain to be tured off + * - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not + * - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not + * - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not + * @return The function will return: + * - TRUE : When the selected power domain is in Active state. + * - FALSE: When the selected power domain is in OFF state. + * + * This function checks whether the selected power domain is active or not. + * + */ +/* SourceId : PMM_SourceId_007 */ +/* DesignId : PMM_DesignId_007 */ +/* Requirements : HL_SR65 */ +boolean pmmIsMemPowerDomainActive( pmm_MemPD_t memPD ) +{ + boolean status; + + if( ( pmmREG->MEMPDPWRSTAT[ memPD ] & PMM_MEMPDPWRSTAT_DOMAINON ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + return status; +} + +/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration register + * @param[in] *config_reg - pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type - whether initial or current value of the configuration + * registers need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg This function will copy the initial + * or current value (depending on the parameter 'type') of the configuration registers to + * the struct pointed by config_reg + */ +/* SourceId : PMM_SourceId_008 */ +/* DesignId : PMM_DesignId_008 */ +/* Requirements : HL_SR64 */ +void pmmGetConfigValue( pmm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE; + config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE; + config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE; + config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0; + config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0; + config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG; + config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1; + } +} + +/** @fn void pmmSetMode(pmm_Mode_t mode) + * @brief Set PSCON Compare Block Mode + * @param[in] mode - PSCON Compare Block mode + * - LockStep : PSCON compare block is set to Lock-Step mode + * - SelfTest : PSCON compare block is set to Self-Test mode + * - ErrorForcing : PSCON compare block is set to Error-Forcing + * mode + * - SelfTestErrorForcing : PSCON compare block is set to + * Self-Test-Error-Forcing mode + * + * This function sets the PSCON Compare block to the selected mode + * + */ +/* SourceId : PMM_SourceId_009 */ +/* DesignId : PMM_DesignId_009 */ +/* Requirements : HL_SR68 */ +void pmmSetMode( pmm_Mode_t mode ) +{ + /* Set PSCON Compare Block Mode */ + pmmREG->PRCKEYREG = mode; +} + +/** @fn boolean pmmPerformSelfTest(void) + * @brief Perform self test and return the result + * + * @return The function will return + * - TRUE if PSCON compare block passed self-test + * - FALSE if PSCON compare block failed in self-test + * + * This function checks whether PSCON compare block passed the self-test or not. + * + */ +/* SourceId : PMM_SourceId_010 */ +/* DesignId : PMM_DesignId_010 */ +/* Requirements : HL_SR72 */ +boolean pmmPerformSelfTest( void ) +{ + boolean status = TRUE; + + /*Enter self-test mode*/ + pmmREG->PRCKEYREG = ( uint32 ) SelfTest; + + /*Wait till self test is completed*/ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( pmmREG->LPDDCSTAT1 & 0xFU ) != 0xFU ) + { + } /* Wait */ + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( pmmREG->MPDDCSTAT1 & 0x3U ) != 0x3U ) + { + } /* Wait */ + + /*Check whether self-test passed or not*/ + if( ( pmmREG->LPDDCSTAT2 & 0xFU ) != 0U ) + { + status = FALSE; + } + + if( ( pmmREG->MPDDCSTAT2 & 0x7U ) != 0U ) + { + status = FALSE; + } + + /*Enter lock-step mode*/ + pmmREG->PRCKEYREG = ( uint32 ) LockStep; + + return status; +} + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pmu.S b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pmu.S new file mode 100644 index 00000000000..38e04c0500f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_pmu.S @@ -0,0 +1,251 @@ +/*--------------------------------------------------------------------------- + sys_pmu.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +---------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize Pmu +@ Note: It will reset all counters +@ SourceId : PMU_SourceId_001 +@ DesignId : PMU_DesignId_001 +@ Requirements : HL_SR484 + + .weak _pmuInit_ + .type _pmuInit_, %function + +_pmuInit_: + + @ set control register + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #(1 << 4) + 6 + 1 + mcr p15, #0, r0, c9, c12, #0 + @ clear flags + mov r0, #0 + sub r0, r0, #1 + mcr p15, #0, r0, c9, c12, #3 + @ select counter 0 event + mov r0, #0 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 1 event + mov r0, #1 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 2 event + mov r0, #2 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Counters Global [Cycle, Event [0..2]] +@ Note: It will reset all counters +@ SourceId : PMU_SourceId_002 +@ DesignId : PMU_DesignId_002 +@ Requirements : HL_SR485 + + .weak _pmuEnableCountersGlobal_ + .type _pmuEnableCountersGlobal_, %function + +_pmuEnableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #7 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Counters Global [Cycle, Event [0..2]] +@ SourceId : PMU_SourceId_003 +@ DesignId : PMU_DesignId_003 +@ Requirements : HL_SR485 + + .weak _pmuDisableCountersGlobal_ + .type _pmuDisableCountersGlobal_, %function + +_pmuDisableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter +@ SourceId : PMU_SourceId_004 +@ DesignId : PMU_DesignId_004 +@ Requirements : HL_SR485 + + .weak _pmuResetCycleCounter_ + .type _pmuResetCycleCounter_, %function + +_pmuResetCycleCounter_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #4 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Event Counters [0..2] +@ SourceId : PMU_SourceId_005 +@ DesignId : PMU_DesignId_005 +@ Requirements : HL_SR485 + + .weak _pmuResetEventCounters_ + .type _pmuResetEventCounters_, %function + +_pmuResetEventCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #2 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter abd Event Counters [0..2] +@ SourceId : PMU_SourceId_006 +@ DesignId : PMU_DesignId_006 +@ Requirements : HL_SR485 + + .weak _pmuResetCounters_ + .type _pmuResetCounters_, %function + +_pmuResetCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #6 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Start Counters [Cycle, 0..2] +@ SourceId : PMU_SourceId_007 +@ DesignId : PMU_DesignId_007 +@ Requirements : HL_SR485 + + .weak _pmuStartCounters_ + .type _pmuStartCounters_, %function + +_pmuStartCounters_: + + mcr p15, #0, r0, c9, c12, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Stop Counters [Cycle, 0..2] + + .weak _pmuStopCounters_ + .type _pmuStopCounters_, %function + +_pmuStopCounters_: +@ SourceId : PMU_SourceId_008 +@ DesignId : PMU_DesignId_008 +@ Requirements : HL_SR485 + + mcr p15, #0, r0, c9, c12, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Set Count event +@ SourceId : PMU_SourceId_009 +@ DesignId : PMU_DesignId_009 +@ Requirements : HL_SR485 + + .weak _pmuSetCountEvent_ + .type _pmuSetCountEvent_, %function + +_pmuSetCountEvent_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mcr p15, #0, r1, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Cycle Count +@ SourceId : PMU_SourceId_010 +@ DesignId : PMU_DesignId_010 +@ Requirements : HL_SR486 + + .weak _pmuGetCycleCount_ + .type _pmuGetCycleCount_, %function + +_pmuGetCycleCount_: + + mrc p15, #0, r0, c9, c13, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Event Counter Count Value +@ SourceId : PMU_SourceId_011 +@ DesignId : PMU_DesignId_011 +@ Requirements : HL_SR486 + + .weak _pmuGetEventCount_ + .type _pmuGetEventCount_, %function + +_pmuGetEventCount_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mrc p15, #0, r0, c9, c13, #2 @ read event counter + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Overflow Flags +@ SourceId : PMU_SourceId_012 +@ DesignId : PMU_DesignId_012 +@ Requirements : HL_SR486 + + .weak _pmuGetOverflow_ + .type _pmuGetOverflow_, %function + +_pmuGetOverflow_: + + mrc p15, #0, r0, c9, c12, #3 @ read overflow + mov r1, #0 + sub r1, r1, #1 + mcr p15, #0, r1, c9, c12, #3 @ clear flags + bx lr + +/*-------------------------------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_selftest.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_selftest.c new file mode 100644 index 00000000000..43122d68315 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_selftest.c @@ -0,0 +1,2680 @@ +/** @file sys_selftest.c + * @brief Selftest Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Selftest API's + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_selftest.h" +#include "sys_core.h" +#include "sys_pmu.h" + +/** @fn void selftestFailNotification(uint32 flag) + * @brief Self test fail service routine + * + * This function is called if there is a self test fail with appropriate flag + */ +void selftestFailNotification( uint32 flag ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void ccmSelfCheck(void) + * @brief CCM module self check Driver + * + * This function self checks the CCM module. + */ +/* SourceId : SELFTEST_SourceId_001 */ +/* DesignId : SELFTEST_DesignId_001 */ +/* Requirements : HL_SR395 */ +void ccmSelfCheck( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* Run a diagnostic check on the CCM-R4F module */ + /* This step ensures that the CCM-R4F can actually indicate an error */ + + /* Configure CCM in self-test mode */ + CCMKEYR = 0x6U; + + /* Wait for CCM self-test to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( CCMSR & 0x100U ) != 0x100U ) + { + } /* Wait */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + /* Check if there was an error during the self-test */ + if( ( CCMSR & 0x1U ) == 0x1U ) + { + /* STE is set */ + selftestFailNotification( CCMSELFCHECK_FAIL1 ); + } + else + { + /* Check CCM-R4 self-test error flag by itself (without compare error) */ + if( ( esmREG->SR1[ 0U ] & 0x80000000U ) == 0x80000000U ) + { + /* ESM flag is not set */ + selftestFailNotification( CCMSELFCHECK_FAIL2 ); + } + else + { + /* Configure CCM in error-forcing mode */ + CCMKEYR = 0x9U; + + /* Wait till error-forcing is completed. */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( CCMKEYR != 0U ) + { + } /* Wait */ + + /* check if compare error flag is set */ + if( ( esmREG->SR1[ 1U ] & 0x4U ) != 0x4U ) + { + /* ESM flag is not set */ + selftestFailNotification( CCMSELFCHECK_FAIL3 ); + } + else + { + /* Check FIQIVEC to ESM High Interrupt flag is set */ + if( ( vimREG->FIQINDEX & 0x000000FFU ) != 1U ) + { + /* ESM High Interrupt flag is not set in VIM*/ + selftestFailNotification( CCMSELFCHECK_FAIL4 ); + } + + /* clear ESM group2 channel 2 flag */ + esmREG->SR1[ 1U ] = 0x4U; + + /* clear ESM group2 shadow status flag */ + esmREG->SSR2 = 0x4U; + + /* ESM self-test error needs to also be cleared */ + esmREG->SR1[ 0U ] = 0x80000000U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + /* Configure CCM in selftest error-forcing mode */ + CCMKEYR = 0xFU; + + /* Wait till selftest error-forcing is completed. */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( CCMKEYR != 0U ) + { + } /* Wait */ + + if( ( esmREG->SR1[ 0U ] & 0x80000000U ) != 0x80000000U ) + { + /* ESM flag not set */ + selftestFailNotification( CCMSELFCHECK_FAIL2 ); + } + else + { + /* clear ESM flag */ + esmREG->SR1[ 0U ] = 0x80000000U; + } + } + } + } +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** @fn void memoryInit(uint32 ram) + * @brief Memory Initialization Driver + * + * This function is called to perform Memory initialization of selected RAM's. + */ +/* SourceId : SELFTEST_SourceId_002 */ +/* DesignId : SELFTEST_DesignId_004 */ +/* Requirements : HL_SR396 */ +void memoryInit( uint32 ram ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /* Enable Memory Hardware Initialization */ + systemREG1->MINITGCR = 0xAU; + + /* Enable Memory Hardware Initialization for selected RAM's */ + systemREG1->MSINENA = ram; + + /* Wait until Memory Hardware Initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->MSTCGSTAT & 0x00000100U ) != 0x00000100U ) + { + } /* Wait */ + + /* Disable Memory Hardware Initialization */ + systemREG1->MINITGCR = 0x5U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void stcSelfCheck(void) + * @brief STC module self check Driver + * + * This function is called to perform STC module self check. + */ +/* SourceId : SELFTEST_SourceId_003 */ +/* DesignId : SELFTEST_DesignId_002 */ +/* Requirements : HL_SR397 */ +void stcSelfCheck( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + volatile uint32 i = 0U; + + /* Run a diagnostic check on the CPU self-test controller */ + /* First set up the STC clock divider as STC is only supported up to 90MHz */ + + /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */ + systemREG2->STCCLKDIV = 0x01000000U; + + /* Select one test interval, restart self-test next time, 0x00010001 */ + stcREG->STCGCR0 = 0x00010001U; + + /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */ + stcREG->STCSCSCR = 0x1AU; + + /* Maximum time-out period */ + stcREG->STCTPR = 0xFFFFFFFFU; + + /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + for( i = 0U; i < ( 16U + ( 16U * 1U ) ); i++ ) + { /* Wait */ + } + + /* Enable self-test */ + stcREG->STCGCR1 = 0xAU; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /* Idle the CPU so that the self-test can start */ + _gotoCPUIdle_(); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/** @fn void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test) + * @brief CPU self test Driver + * @param[in] no_of_intervals - Number of Test Intervals to be + * @param[in] max_timeout - Maximum Timeout to complete selected test Intervals + * @param[in] restart_test - Restart the test from Interval 0 or Continue from where + * it stopped. + * + * This function is called to perform CPU self test using STC module. + */ +/* SourceId : SELFTEST_SourceId_004 */ +/* DesignId : SELFTEST_DesignId_003 */ +/* Requirements : HL_SR398 */ +void cpuSelfTest( uint32 no_of_intervals, uint32 max_timeout, boolean restart_test ) +{ + volatile uint32 i = 0U; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Run specified no of test intervals starting from interval 0 */ + /* Start test from interval 0 or continue the test. */ + stcREG->STCGCR0 = no_of_intervals << 16U; + + if( restart_test ) + { + stcREG->STCGCR0 |= 0x00000001U; + } + + /* Configure Maximum time-out period */ + stcREG->STCTPR = max_timeout; + + /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + for( i = 0U; i < ( 16U + ( 16U * 1U ) ); i++ ) + { /* Wait */ + } + + /* Enable self-test */ + stcREG->STCGCR1 = 0xAU; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + /* Idle the CPU so that the self-test can start */ + + _gotoCPUIdle_(); +} + +/** @fn void pbistSelfCheck(void) + * @brief PBIST self test Driver + * + * This function is called to perform PBIST self test. + * + * @note This Function uses register's which are not exposed to users through + * TRM , to run custom algorithm to make PBIST Fail. Users can use this function as + * Black box. + * + */ +/* SourceId : SELFTEST_SourceId_005 */ +/* DesignId : SELFTEST_DesignId_005 */ +/* Requirements : HL_SR399 */ +void pbistSelfCheck( void ) +{ + volatile uint32 i = 0U; + uint32 PBIST_wait_done_loop = 0U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + /* Run a diagnostic check on the memory self-test controller */ + /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */ + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST ROM clock frequency = HCLK frequency /2 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000105U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000010AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + for( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) + { /* Wait */ + } + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Custom always fail algo, this will not use the ROM and just set a fail */ + pbistREG->RAMT = 0x00002000U; + *( volatile uint32 * ) 0xFFFFE400U = 0x4C000001U; + *( volatile uint32 * ) 0xFFFFE440U = 0x00000075U; + *( volatile uint32 * ) 0xFFFFE404U = 0x4C000002U; + *( volatile uint32 * ) 0xFFFFE444U = 0x00000075U; + *( volatile uint32 * ) 0xFFFFE408U = 0x4C000003U; + *( volatile uint32 * ) 0xFFFFE448U = 0x00000075U; + *( volatile uint32 * ) 0xFFFFE40CU = 0x4C000004U; + *( volatile uint32 * ) 0xFFFFE44CU = 0x00000075U; + *( volatile uint32 * ) 0xFFFFE410U = 0x4C000005U; + *( volatile uint32 * ) 0xFFFFE450U = 0x00000075U; + *( volatile uint32 * ) 0xFFFFE414U = 0x4C000006U; + *( volatile uint32 * ) 0xFFFFE454U = 0x00000075U; + *( volatile uint32 * ) 0xFFFFE418U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE458U = 0x00000001U; + + /* PBIST_RUN */ + pbistREG->rsvd1[ 1U ] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->MSTCGSTAT & 0x1U ) != 0x1U ) + { + PBIST_wait_done_loop++; + } /* Wait */ + + /* Check for the failure */ + if( ( pbistREG->FSRF0 & 0x1U ) != 0x1U ) + { + /* No failure was indicated even if the always fail algorithm was run*/ + selftestFailNotification( PBISTSELFCHECK_FAIL1 ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + } + else + { + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected above */ + if( PBIST_wait_done_loop >= 2U ) + { + selftestFailNotification( PBISTSELFCHECK_FAIL2 ); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + } +} + +/** @fn void pbistRun(uint32 raminfoL, uint32 algomask) + * @brief CPU self test Driver + * @param[in] raminfoL - Select the list of RAM to be tested. + * @param[in] algomask - Select the list of Algorithm to be run. + * + * This function performs Memory Built-in Self test using PBIST module. + */ +/* SourceId : SELFTEST_SourceId_006 */ +/* DesignId : SELFTEST_DesignId_006 */ +/* Requirements : HL_SR400 */ +void pbistRun( uint32 raminfoL, uint32 algomask ) +{ + volatile uint32 i = 0U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* PBIST ROM clock frequency = HCLK frequency /2 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000105U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000010AU; + + /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + for( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) + { /* Wait */ + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* Select all algorithms to be tested */ + pbistREG->ALGO = algomask; + + /* Select RAM groups */ + pbistREG->RINFOL = raminfoL; + + /* Select all RAM groups */ + pbistREG->RINFOU = 0x00000000U; + + /* ROM contents will not override RINFOx settings */ + pbistREG->OVER = 0x0U; + + /* Algorithm code is loaded from ROM */ + pbistREG->ROM = 0x3U; + + /* Start PBIST */ + pbistREG->DLR = 0x14U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void pbistStop(void) + * @brief Routine to stop PBIST test enabled. + * + * This function is called to stop PBIST after test is performed. + */ +/* SourceId : SELFTEST_SourceId_007 */ +/* DesignId : SELFTEST_DesignId_007 */ +/* Requirements : HL_SR523 */ +void pbistStop( void ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + /* disable pbist clocks and ROM clock */ + pbistREG->PACT = 0x0U; + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn boolean pbistIsTestCompleted(void) + * @brief Checks to see if the PBIST test is completed. + * @return 1 if PBIST test completed, otherwise 0. + * + * Checks to see if the PBIST test is completed. + */ +/* SourceId : SELFTEST_SourceId_008 */ +/* DesignId : SELFTEST_DesignId_008 */ +/* Requirements : HL_SR401 */ +boolean pbistIsTestCompleted( void ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + return ( ( systemREG1->MSTCGSTAT & 0x1U ) != 0U ); + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn boolean pbistIsTestPassed(void) + * @brief Checks to see if the PBIST test is completed successfully. + * @return 1 if PBIST test passed, otherwise 0. + * + * Checks to see if the PBIST test is completed successfully. + */ +/* SourceId : SELFTEST_SourceId_009 */ +/* DesignId : SELFTEST_DesignId_009 */ +/* Requirements : HL_SR401 */ +boolean pbistIsTestPassed( void ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + boolean status; + + if( pbistREG->FSRF0 == 0U ) + { + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + return status; +} + +/** @fn boolean pbistPortTestStatus(uint32 port) + * @brief Checks to see if the PBIST Port test is completed successfully. + * @param[in] port - Select the port to get the status. + * @return 1 if PBIST Port test completed successfully, otherwise 0. + * + * Checks to see if the selected PBIST Port test is completed successfully. + */ +/* SourceId : SELFTEST_SourceId_010 */ +/* DesignId : SELFTEST_DesignId_010 */ +/* Requirements : HL_SR401 */ +boolean pbistPortTestStatus( uint32 port ) +{ + boolean status; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + if( port == ( uint32 ) PBIST_PORT0 ) + { + status = ( pbistREG->FSRF0 == 0U ); + } + else + { + /* Invalid Input */ + status = FALSE; + } + + return status; +} + +/** @fn uint32 efcCheck(void) + * @brief EFUSE module self check Driver + * @return Returns 0 if no error was detected during autoload and Stuck At Zero Test + * passed 1 if no error was detected during autoload but Stuck At Zero Test failed 2 if + * there was a single-bit error detected during autoload 3 if some other error occurred + * during autoload + * + * This function self checks the EFUSE module. + */ +/* SourceId : SELFTEST_SourceId_011 */ +/* DesignId : SELFTEST_DesignId_012 */ +/* Requirements : HL_SR402 */ +uint32 efcCheck( void ) +{ + uint32 efcStatus = 0U; + uint32 status; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + /* read the EFC Error Status Register */ + efcStatus = efcREG->ERROR; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + if( efcStatus == 0x0U ) + { + /* run stuck-at-zero test and check if it passed */ + if( efcStuckZeroTest() == TRUE ) + { + /* start EFC ECC logic self-test */ + efcSelfTest(); + status = 0U; + } + else + { + /* EFC output is stuck-at-zero, device operation unreliable */ + selftestFailNotification( EFCCHECK_FAIL1 ); + status = 1U; + } + } + /* EFC Error Register is not zero */ + else + { + /* one-bit error detected during autoload */ + if( efcStatus == 0x15U ) + { + /* start EFC ECC logic self-test */ + efcSelfTest(); + status = 2U; + } + else + { + /* Some other EFC error was detected */ + selftestFailNotification( EFCCHECK_FAIL1 ); + status = 3U; + } + } + + return status; +} + +/** @fn boolean efcStuckZeroTest(void) + * @brief Checks to see if the EFUSE Stuck at zero test is completed successfully. + * @return 1 if EFUSE Stuck at zero test completed, otherwise 0. + * + * Checks to see if the EFUSE Stuck at zero test is completed successfully. + */ +/* SourceId : SELFTEST_SourceId_012 */ +/* DesignId : SELFTEST_DesignId_014 */ +/* Requirements : HL_SR402 */ +boolean efcStuckZeroTest( void ) +{ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + + boolean result = FALSE; + uint32 error_checks = EFC_INSTRUCTION_INFO_EN | EFC_INSTRUCTION_ERROR_EN + | EFC_AUTOLOAD_ERROR_EN | EFC_SELF_TEST_ERROR_EN; + + /* configure the output enable for auto load error , instruction info, + * instruction error, and self test error using boundary register + * and drive values one across all the errors */ + efcREG->BOUNDARY = ( ( uint32 ) OUTPUT_ENABLE | error_checks ); + + /* Read from the pin register. This register holds the current values + * of above errors. This value should be 0x5c00.If not at least one of + * the above errors is stuck at 0. */ + if( ( efcREG->PINS & 0x5C00U ) == 0x5C00U ) + { + ESM_ESTATUS4 = esmREG->SR4[ 0U ]; + ESM_ESTATUS1 = esmREG->SR1[ 2U ]; + + /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */ + if( ( ( ESM_ESTATUS4 & 0x200U ) == 0x200U ) + && ( ( ESM_ESTATUS1 & 0x2U ) == 0x2U ) ) + { + /* stuck-at-zero test passed */ + result = TRUE; + } + } + + /* put the pins back low */ + efcREG->BOUNDARY = OUTPUT_ENABLE; + + /* clear group1 flag */ + esmREG->SR4[ 0U ] = 0x200U; + + /* clear group3 flag */ + esmREG->SR1[ 2U ] = 0x2U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + return result; +} + +/** @fn void efcSelfTest(void) + * @brief EFUSE module self check Driver + * + * This function self checks the EFSUE module. + */ +/* SourceId : SELFTEST_SourceId_013 */ +/* DesignId : SELFTEST_DesignId_013 */ +/* Requirements : HL_SR402 */ +void efcSelfTest( void ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + /* configure self-test cycles */ + efcREG->SELF_TEST_CYCLES = 0x258U; + + /* configure self-test signature */ + efcREG->SELF_TEST_SIGN = 0x5362F97FU; + + /* configure boundary register to start ECC self-test */ + efcREG->BOUNDARY = 0x0000200FU; +} + +/** @fn boolean checkefcSelfTest(void) + * @brief EFUSE module self check Driver + * @return Returns TRUE if EFC Selftest was a PASS, else FALSE + * + * This function returns the status of efcSelfTest. + * Note: This function can be called only after calling efcSelfTest + */ +/* SourceId : SELFTEST_SourceId_014 */ +/* DesignId : SELFTEST_DesignId_015 */ +/* Requirements : HL_SR403 */ +boolean checkefcSelfTest( void ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + boolean result = FALSE; + + uint32 EFC_PINS, EFC_ERROR; + uint32 esmCh40Stat, esmCh41Stat = 0U; + + /* wait until EFC self-test is done */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( efcREG->PINS & EFC_SELF_TEST_DONE ) == 0U ) + { + } /* Wait */ + + /* check if EFC self-test error occurred */ + EFC_PINS = efcREG->PINS; + EFC_ERROR = efcREG->ERROR; + + if( ( ( EFC_PINS & EFC_SELF_TEST_ERROR ) == 0U ) && ( ( EFC_ERROR & 0x1FU ) == 0U ) ) + { + /* check if EFC self-test error is set */ + esmCh40Stat = esmREG->SR4[ 0U ] & 0x100U; + esmCh41Stat = esmREG->SR4[ 0U ] & 0x200U; + + if( ( esmCh40Stat == 0U ) && ( esmCh41Stat == 0U ) ) + { + result = TRUE; + } + } + + return result; +} + +/** @fn void fmcBus2Check(void) + * @brief Self Check Flash Bus2 Interface + * + * This function self checks Flash Bus2 Interface + */ +/* SourceId : SELFTEST_SourceId_015 */ +/* DesignId : SELFTEST_DesignId_016 */ +/* Requirements : HL_SR404, HL_SR405 */ +void fmcBus2Check( void ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + /* enable ECC logic inside FMC */ + flashWREG->FEDACCTRL1 = 0x000A060AU; + + if( ( esmREG->SR1[ 0U ] & 0x40U ) == 0x40U ) + { + /* a 1-bit error was detected during flash OTP read by flash module + * run a self-check on ECC logic inside FMC */ + + /* clear ESM group1 channel 6 flag */ + esmREG->SR1[ 0U ] = 0x40U; + + fmcECCcheck(); + } + + /* no 2-bit or 1-bit error detected during power-up */ + else + { + fmcECCcheck(); + } + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void fmcECCcheck(void) + * @brief Check Flash ECC Single Bit and multi Bit errors detection logic. + * + * This function Checks Flash ECC Single Bit and multi Bit errors detection logic. + */ +/* SourceId : SELFTEST_SourceId_016 */ +/* DesignId : SELFTEST_DesignId_017 */ +/* Requirements : HL_SR404, HL_SR405 */ +void fmcECCcheck( void ) +{ + volatile uint32 otpread; + volatile uint32 temp; + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* read location with deliberate 1-bit error */ + otpread = flash1bitError; + ( void ) otpread; + + if( ( esmREG->SR1[ 0U ] & 0x40U ) == 0x40U ) + { + /* 1-bit failure was indicated and corrected */ + flashWREG->FEDACSTATUS = 0x00010006U; + + /* clear ESM group1 channel 6 flag */ + esmREG->SR1[ 0U ] = 0x40U; + + /* read location with deliberate 2-bit error */ + otpread = flash2bitError; + ( void ) otpread; + + if( ( esmREG->SR1[ 2U ] & 0x80U ) == 0x80U ) + { + /* 2-bit failure was detected correctly */ + temp = flashWREG->FUNCERRADD; + ( void ) temp; + flashWREG->FEDACSTATUS = 0x00020100U; + + /* clear ESM group3 channel 7 */ + esmREG->SR1[ 2U ] = 0x80U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + } + else + { + /* ECC logic inside FMC cannot detect 2-bit error */ + selftestFailNotification( FMCECCCHECK_FAIL1 ); + } + } + else + { + /* ECC logic inside FMC cannot detect 1-bit error */ + selftestFailNotification( FMCECCCHECK_FAIL1 ); + } + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void checkB0RAMECC(void) + * @brief Check TCRAM1 ECC error detection logic. + * + * This function checks TCRAM1 ECC error detection logic. + */ +/* SourceId : SELFTEST_SourceId_017 */ +/* DesignId : SELFTEST_DesignId_019 */ +/* Requirements : HL_SR408 */ +void checkB0RAMECC( void ) +{ + volatile uint64 ramread = 0U; + volatile uint32 regread = 0U; + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + uint64 tcramA1_bk = tcramA1bit; + uint64 tcramA2_bk = tcramA2bit; + volatile uint32 i; + + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* the first 1-bit error will cause an error response */ + tcram1REG->RAMTHRESHOLD = 0x1U; + tcram2REG->RAMTHRESHOLD = 0x1U; + + /* allow SERR to be reported to ESM */ + tcram1REG->RAMINTCTRL = 0x1U; + tcram2REG->RAMINTCTRL = 0x1U; + + /* cause a 1-bit ECC error */ + _coreDisableRamEcc_(); + tcramA1bitError ^= 0x1U; + _coreEnableRamEcc_(); + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* read from location with 1-bit ECC error */ + ramread = tcramA1bit; + ( void ) ramread; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U; + + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + if( ( tcram1ErrStat == 0U ) && ( tcram2ErrStat == 0U ) ) + { + /* TCRAM module does not reflect 1-bit error reported by CPU */ + selftestFailNotification( CHECKB0RAMECC_FAIL1 ); + } + else + { + /* clear SERR flag */ + tcram1REG->RAMERRSTATUS = 0x1U; + tcram2REG->RAMERRSTATUS = 0x1U; + + /* clear status flags for ESM group1 channels 26 and 28 */ + esmREG->SR1[ 0U ] = 0x14000000U; + } + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* cause a 2-bit ECC error */ + _coreDisableRamEcc_(); + tcramA2bitError ^= 0x3U; + _coreEnableRamEcc_(); + + /* read from location with 2-bit ECC error this will cause a data abort to be + * generated */ + ramread = tcramA2bit; + + /* delay before restoring the ram value */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + for( i = 0U; i < 10U; i++ ) + { + } /* Wait */ + + regread = tcram1REG->RAMUERRADDR; + ( void ) regread; + regread = tcram2REG->RAMUERRADDR; + ( void ) regread; + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Compute correct ECC */ + tcramA1bit = tcramA1_bk; + tcramA2bit = tcramA2_bk; + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn void checkB1RAMECC(void) + * @brief Check TCRAM2 ECC error detection logic. + * + * This function checks TCRAM2 ECC error detection logic. + */ +/* SourceId : SELFTEST_SourceId_018 */ +/* DesignId : SELFTEST_DesignId_019 */ +/* Requirements : HL_SR408 */ +void checkB1RAMECC( void ) +{ + volatile uint64 ramread = 0U; + volatile uint32 regread = 0U; + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + uint64 tcramB1_bk = tcramB1bit; + uint64 tcramB2_bk = tcramB2bit; + volatile uint32 i; + + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* the first 1-bit error will cause an error response */ + tcram1REG->RAMTHRESHOLD = 0x1U; + tcram2REG->RAMTHRESHOLD = 0x1U; + + /* allow SERR to be reported to ESM */ + tcram1REG->RAMINTCTRL = 0x1U; + tcram2REG->RAMINTCTRL = 0x1U; + + /* cause a 1-bit ECC error */ + _coreDisableRamEcc_(); + tcramB1bitError ^= 0x1U; + _coreEnableRamEcc_(); + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* read from location with 1-bit ECC error */ + ramread = tcramB1bit; + ( void ) ramread; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U; + + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + if( ( tcram1ErrStat == 0U ) && ( tcram2ErrStat == 0U ) ) + { + /* TCRAM module does not reflect 1-bit error reported by CPU */ + selftestFailNotification( CHECKB1RAMECC_FAIL1 ); + } + else + { + /* clear SERR flag */ + tcram1REG->RAMERRSTATUS = 0x1U; + tcram2REG->RAMERRSTATUS = 0x1U; + + /* clear status flags for ESM group1 channels 26 and 28 */ + esmREG->SR1[ 0U ] = 0x14000000U; + } + + /* enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* cause a 2-bit ECC error */ + _coreDisableRamEcc_(); + tcramB2bitError ^= 0x3U; + _coreEnableRamEcc_(); + + /* read from location with 2-bit ECC error this will cause a data abort to be + * generated */ + ramread = tcramB2bit; + + /* delay before restoring the ram value */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i not + * used)" */ + for( i = 0U; i < 10U; i++ ) + { + } /* Wait */ + + regread = tcram1REG->RAMUERRADDR; + ( void ) regread; + regread = tcram2REG->RAMUERRADDR; + ( void ) regread; + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Compute correct ECC */ + tcramB1bit = tcramB1_bk; + tcramB2bit = tcramB2_bk; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} + +/** @fn void checkFlashECC(void) + * @brief Check Flash ECC error detection logic. + * + * This function checks Flash ECC error detection logic. + */ +/* SourceId : SELFTEST_SourceId_019 */ +/* DesignId : SELFTEST_DesignId_020 */ +/* Requirements : HL_SR405 */ +void checkFlashECC( void ) +{ + /* Routine to check operation of ECC logic inside CPU for accesses to program flash */ + volatile uint32 flashread = 0U; + + /* USER CODE BEGIN (40) */ + /* USER CODE END */ + + /* Flash Module ECC Response enabled */ + flashWREG->FEDACCTRL1 = 0x000A060AU; + + /* Enable diagnostic mode and select diag mode 7 */ + flashWREG->FDIAGCTRL = 0x00050007U; + + /* Select ECC diagnostic mode, single-bit to be corrupted */ + flashWREG->FPAROVR = 0x00005A01U; + + /* Set the trigger for the diagnostic mode */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /* read a flash location from the mirrored memory map */ + flashread = flashBadECC1; + ( void ) flashread; + + /* disable diagnostic mode */ + flashWREG->FDIAGCTRL = 0x000A0007U; + + /* this will have caused a single-bit error to be generated and corrected by CPU */ + /* single-bit error not captured in flash module */ + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( ( flashWREG->FEDACSTATUS & 0x2U ) == 0U ) + { + selftestFailNotification( CHECKFLASHECC_FAIL1 ); + } + else + { + /* clear single-bit error flag */ + flashWREG->FEDACSTATUS = 0x2U; + + /* clear ESM flag */ + esmREG->SR1[ 0U ] = 0x40U; + + /* Enable diagnostic mode and select diag mode 7 */ + flashWREG->FDIAGCTRL = 0x00050007U; + + /* Select ECC diagnostic mode, two bits of ECC to be corrupted */ + flashWREG->FPAROVR = 0x00005A03U; + + /* Set the trigger for the diagnostic mode */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /* read from flash location from mirrored memory map this will cause a data abort + */ + flashread = flashBadECC2; + + /* Read FUNCERRADD register */ + flashread = flashWREG->FUNCERRADD; + + /* disable diagnostic mode */ + flashWREG->FDIAGCTRL = 0x000A0007U; + } + + /* USER CODE BEGIN (41) */ + /* USER CODE END */ +} + +/** @fn void custom_dabort(void) + * @brief Custom Data abort routine for the application. + * + * Custom Data abort routine for the application. + */ +void custom_dabort( void ) +{ + /* Need custom data abort handler here. + * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC + * logic. + */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/** @fn void stcSelfCheckFail(void) + * @brief STC Self test check fail service routine + * + * This function is called if STC Self test check fail. + */ +void stcSelfCheckFail( void ) +{ + /* USER CODE BEGIN (43) */ + /* USER CODE END */ + + /* CPU self-test controller's own self-test failed. + * It is not possible to verify that STC is capable of indicating a CPU self-test + * error. It is not recommended to continue operation. + */ + + /* User can add small piece of code to take system to Safe state using user code + * section. Note: Just removing the for(;;) will take the system to unknown state + * under ST failure, since it is not handled by HALCoGen driver */ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA "for(;;) can be removed by adding "# if 0" and "# + * endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA "for(;;) can be removed by adding "# if 0" and "# + * endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA "for(;;) can be removed by adding "# if 0" and "# + * endif" in the user codes above and below" */ + for( ;; ) + { + } /* Wait */ + + /* USER CODE BEGIN (45) */ + /* USER CODE END */ +} + +/** @fn void cpuSelfTestFail(void) + * @brief CPU Self test check fail service routine + * + * This function is called if CPU Self test check fail. + */ +void cpuSelfTestFail( void ) +{ + /* USER CODE BEGIN (46) */ + /* USER CODE END */ + + /* CPU self-test has failed. + * CPU operation is not reliable. + */ + /* USER CODE BEGIN (47) */ + /* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA "for(;;) can be removed by adding "# if 0" and "# + * endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA "for(;;) can be removed by adding "# if 0" and "# + * endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA "for(;;) can be removed by adding "# if 0" and "# + * endif" in the user codes above and below" */ + for( ;; ) + { + } /* Wait */ + + /* USER CODE BEGIN (48) */ + /* USER CODE END */ +} + +/** @fn void vimParityCheck(void) + * @brief Routine to check VIM RAM parity error detection and signaling mechanism + * + * Routine to check VIM RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_020 */ +/* DesignId : SELFTEST_DesignId_021 */ +/* Requirements : HL_SR385 */ +void vimParityCheck( void ) +{ + volatile uint32 vimramread = 0U; + uint32 vimparctl_bk = VIM_PARCTL; + + /* USER CODE BEGIN (49) */ + /* USER CODE END */ + + /* Enable parity checking and parity test mode */ + VIM_PARCTL = 0x0000010AU; + + /* flip a bit in the VIM RAM parity location */ + VIMRAMPARLOC ^= 0x1U; + + /* disable parity test mode */ + VIM_PARCTL = 0x0000000AU; + + /* cause parity error */ + vimramread = VIMRAMLOC; + ( void ) vimramread; + + /* check if ESM group1 channel 15 is flagged */ + if( ( esmREG->SR1[ 0U ] & 0x8000U ) == 0U ) + { + /* VIM RAM parity error was not flagged to ESM. */ + selftestFailNotification( VIMPARITYCHECK_FAIL1 ); + } + else + { + /* clear VIM RAM parity error flag in VIM */ + VIM_PARFLG = 0x1U; + + /* clear ESM group1 channel 15 flag */ + esmREG->SR1[ 0U ] = 0x8000U; + + /* Enable parity checking and parity test mode */ + VIM_PARCTL = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + VIMRAMPARLOC ^= 0x1U; + } + + /* Restore Parity Control register */ + VIM_PARCTL = vimparctl_bk; + + /* USER CODE BEGIN (50) */ + /* USER CODE END */ +} + +/** @fn void dmaParityCheck(void) + * @brief Routine to check DMA control packet RAM parity error detection and signaling + * mechanism + * + * Routine to check DMA control packet RAM parity error detection and signaling + * mechanism + */ +/* SourceId : SELFTEST_SourceId_021 */ +/* DesignId : SELFTEST_DesignId_022 */ +/* Requirements : HL_SR388 */ +void dmaParityCheck( void ) +{ + volatile uint32 dmaread = 0U; + uint32 dmaparcr_bk = DMA_PARCR; + + /* USER CODE BEGIN (51) */ + /* USER CODE END */ + + /* Enable parity checking and parity test mode */ + DMA_PARCR = 0x0000010AU; + + /* Flip a bit in DMA RAM parity location */ + DMARAMPARLOC ^= 0x1U; + + /* Disable parity test mode */ + DMA_PARCR = 0x0000000AU; + + /* Cause parity error */ + dmaread = DMARAMLOC; + ( void ) dmaread; + + /* Check if ESM group1 channel 3 is flagged */ + if( ( esmREG->SR1[ 0U ] & 0x8U ) == 0U ) + { + /* DMA RAM parity error was not flagged to ESM. */ + selftestFailNotification( DMAPARITYCHECK_FAIL1 ); + } + else + { + /* clear DMA parity error flag in DMA */ + DMA_PARADDR = 0x01000000U; + + /* clear ESM group1 channel 3 flag */ + esmREG->SR1[ 0U ] = 0x8U; + + /* Enable parity checking and parity test mode */ + DMA_PARCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + DMARAMPARLOC ^= 0x1U; + } + + /* Restrore Parity Control register */ + DMA_PARCR = dmaparcr_bk; + + /* USER CODE BEGIN (52) */ + /* USER CODE END */ +} + +/** @fn void het1ParityCheck(void) + * @brief Routine to check HET1 RAM parity error detection and signaling mechanism + * + * Routine to check HET1 RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_022 */ +/* DesignId : SELFTEST_DesignId_024 */ +/* Requirements : HL_SR389 */ +void het1ParityCheck( void ) +{ + volatile uint32 nhetread = 0U; + uint32 hetpcr_bk = hetREG1->PCR; + + /* USER CODE BEGIN (53) */ + /* USER CODE END */ + + /* Set TEST mode and enable parity checking */ + hetREG1->PCR = 0x0000010AU; + + /* flip parity bit */ + NHET1RAMPARLOC ^= 0x1U; + + /* Disable TEST mode */ + hetREG1->PCR = 0x0000000AU; + + /* read to cause parity error */ + nhetread = NHET1RAMLOC; + ( void ) nhetread; + + /* check if ESM group1 channel 7 is flagged */ + if( ( esmREG->SR1[ 0U ] & 0x80U ) == 0U ) + { + /* NHET1 RAM parity error was not flagged to ESM. */ + selftestFailNotification( HET1PARITYCHECK_FAIL1 ); + } + else + { + /* clear ESM group1 channel 7 flag */ + esmREG->SR1[ 0U ] = 0x80U; + + /* Set TEST mode and enable parity checking */ + hetREG1->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + NHET1RAMPARLOC ^= 0x1U; + } + + /* Restore Parity comtrol register */ + hetREG1->PCR = hetpcr_bk; + + /* USER CODE BEGIN (54) */ + /* USER CODE END */ +} + +/** @fn void htu1ParityCheck(void) + * @brief Routine to check HTU1 RAM parity error detection and signaling mechanism + * + * Routine to check HTU1 RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_023 */ +/* DesignId : SELFTEST_DesignId_025 */ +/* Requirements : HL_SR390 */ +void htu1ParityCheck( void ) +{ + volatile uint32 hturead = 0U; + uint32 htupcr_bk = htuREG1->PCR; + + /* USER CODE BEGIN (55) */ + /* USER CODE END */ + + /* Enable parity and TEST mode */ + htuREG1->PCR = 0x0000010AU; + + /* flip parity bit */ + HTU1PARLOC ^= 0x1U; + + /* Disable parity RAM test mode */ + htuREG1->PCR = 0x0000000AU; + + /* read to cause parity error */ + hturead = HTU1RAMLOC; + ( void ) hturead; + + /* check if ESM group1 channel 8 is flagged */ + if( ( esmREG->SR1[ 0U ] & 0x100U ) == 0U ) + { + /* HTU1 RAM parity error was not flagged to ESM. */ + selftestFailNotification( HTU1PARITYCHECK_FAIL1 ); + } + else + { + /* Clear HTU parity error flag */ + htuREG1->PAR = 0x00010000U; + esmREG->SR1[ 0U ] = 0x100U; + + /* Enable parity and TEST mode */ + htuREG1->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + HTU1PARLOC ^= 0x1U; + } + + /* Restore Parity control register */ + htuREG1->PCR = htupcr_bk; + + /* USER CODE BEGIN (56) */ + /* USER CODE END */ +} + +/** @fn void het2ParityCheck(void) + * @brief Routine to check HET2 RAM parity error detection and signaling mechanism + * + * Routine to check HET2 RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_024 */ +/* DesignId : SELFTEST_DesignId_024 */ +/* Requirements : HL_SR389 */ +void het2ParityCheck( void ) +{ + volatile uint32 nhetread = 0U; + uint32 hetpcr_bk = hetREG2->PCR; + uint32 esmCh7Stat, esmCh34Stat = 0U; + + /* USER CODE BEGIN (57) */ + /* USER CODE END */ + + /* Set TEST mode and enable parity checking */ + hetREG2->PCR = 0x0000010AU; + + /* flip parity bit */ + NHET2RAMPARLOC ^= 0x1U; + + /* Disable TEST mode */ + hetREG2->PCR = 0x0000000AU; + + /* read to cause parity error */ + nhetread = NHET2RAMLOC; + ( void ) nhetread; + + /* check if ESM group1 channel 7 or 34 (If not reserved) is flagged */ + esmCh7Stat = esmREG->SR1[ 0U ] & 0x80U; + esmCh34Stat = esmREG->SR4[ 0U ] & 0x4U; + + if( ( esmCh7Stat == 0U ) && ( esmCh34Stat == 0U ) ) + { + /* NHET2 RAM parity error was not flagged to ESM. */ + selftestFailNotification( HET2PARITYCHECK_FAIL1 ); + } + else + { + /* clear ESM group1 channel 7 flag */ + esmREG->SR1[ 0U ] = 0x80U; + + /* clear ESM group1 channel 34 flag */ + esmREG->SR4[ 0U ] = 0x4U; + + /* Set TEST mode and enable parity checking */ + hetREG2->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + NHET2RAMPARLOC ^= 0x1U; + } + + /* Restore parity control register */ + hetREG2->PCR = hetpcr_bk; + + /* USER CODE BEGIN (58) */ + /* USER CODE END */ +} + +/** @fn void htu2ParityCheck(void) + * @brief Routine to check HTU2 RAM parity error detection and signaling mechanism + * + * Routine to check HTU2 RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_025 */ +/* DesignId : SELFTEST_DesignId_025 */ +/* Requirements : HL_SR390 */ +void htu2ParityCheck( void ) +{ + volatile uint32 hturead = 0U; + uint32 htupcr_bk = htuREG2->PCR; + + /* USER CODE BEGIN (59) */ + /* USER CODE END */ + + /* Enable parity and TEST mode */ + htuREG2->PCR = 0x0000010AU; + + /* flip parity bit */ + HTU2PARLOC ^= 0x1U; + + /* Disable parity RAM test mode */ + htuREG2->PCR = 0x0000000AU; + + /* read to cause parity error */ + hturead = HTU2RAMLOC; + ( void ) hturead; + + /* check if ESM group1 channel 8 is flagged */ + if( ( esmREG->SR1[ 0U ] & 0x100U ) == 0U ) + { + /* HTU2 RAM parity error was not flagged to ESM. */ + selftestFailNotification( HTU2PARITYCHECK_FAIL1 ); + } + else + { + /* Clear HTU parity error flag */ + htuREG2->PAR = 0x00010000U; + esmREG->SR1[ 0U ] = 0x100U; + + /* Enable parity and TEST mode */ + htuREG2->PCR = 0x0000010AU; + + /* Revert back to correct data, flip bit 0 of the parity location */ + HTU2PARLOC ^= 0x1U; + } + + /* Restore parity control register*/ + htuREG2->PCR = htupcr_bk; + + /* USER CODE BEGIN (60) */ + /* USER CODE END */ +} + +/** @fn void adc1ParityCheck(void) + * @brief Routine to check ADC1 RAM parity error detection and signaling mechanism + * + * Routine to check ADC1 RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_026 */ +/* DesignId : SELFTEST_DesignId_023 */ +/* Requirements : HL_SR387 */ +void adc1ParityCheck( void ) +{ + volatile uint32 adcramread = 0U; + uint32 adcparcr_bk = adcREG1->PARCR; + + /* USER CODE BEGIN (61) */ + /* USER CODE END */ + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG1->PARCR = 0x10AU; + + /* Invert the parity bits inside the ADC1 RAM's first location */ + adcPARRAM1 = ~( adcPARRAM1 ); + + /* clear the TEST bit */ + adcREG1->PARCR = 0x00AU; + + /* This read is expected to trigger a parity error */ + adcramread = adcRAM1; + ( void ) adcramread; + + /* Check for ESM group1 channel 19 to be flagged */ + if( ( esmREG->SR1[ 0U ] & 0x80000U ) == 0U ) + { + /* no ADC1 RAM parity error was flagged to ESM */ + selftestFailNotification( ADC1PARITYCHECK_FAIL1 ); + } + else + { + /* clear ADC1 RAM parity error flag */ + esmREG->SR1[ 0U ] = 0x80000U; + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG1->PARCR = 0x10AU; + + /* Revert back the parity bits to correct data */ + adcPARRAM1 = ~( adcPARRAM1 ); + } + + /* Restore parity control register */ + adcREG1->PARCR = adcparcr_bk; + + /* USER CODE BEGIN (62) */ + /* USER CODE END */ +} + +/** @fn void adc2ParityCheck(void) + * @brief Routine to check ADC2 RAM parity error detection and signaling mechanism + * + * Routine to check ADC2 RAM parity error detection and signaling mechanism + */ +/* SourceId : SELFTEST_SourceId_027 */ +/* DesignId : SELFTEST_DesignId_023 */ +/* Requirements : HL_SR387 */ +void adc2ParityCheck( void ) +{ + volatile uint32 adcramread = 0U; + uint32 adcparcr_bk = adcREG2->PARCR; + + /* USER CODE BEGIN (63) */ + /* USER CODE END */ + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG2->PARCR = 0x10AU; + + /* Invert the parity bits inside the ADC2 RAM's first location */ + adcPARRAM2 = ~( adcPARRAM2 ); + + /* clear the TEST bit */ + adcREG2->PARCR = 0x00AU; + + /* This read is expected to trigger a parity error */ + adcramread = adcRAM2; + ( void ) adcramread; + + /* Check for ESM group1 channel 1 to be flagged */ + if( ( esmREG->SR1[ 0U ] & 0x2U ) == 0U ) + { + /* no ADC2 RAM parity error was flagged to ESM */ + selftestFailNotification( ADC2PARITYCHECK_FAIL1 ); + } + else + { + /* clear ADC2 RAM parity error flag */ + esmREG->SR1[ 0U ] = 0x2U; + + /* Set the TEST bit in the PARCR and enable parity checking */ + adcREG2->PARCR = 0x10AU; + + /* Revert back the parity bits to correct data */ + adcPARRAM2 = ~( adcPARRAM2 ); + } + + /* Restore parity control register*/ + adcREG2->PARCR = adcparcr_bk; + + /* USER CODE BEGIN (64) */ + /* USER CODE END */ +} + +/** @fn void checkRAMECC(void) + * @brief Check TCRAM ECC error detection logic. + * + * This function checks TCRAM ECC error detection logic. + */ +/* SourceId : SELFTEST_SourceId_034 */ +/* DesignId : SELFTEST_DesignId_019 */ +/* Requirements : HL_SR408 */ +void checkRAMECC( void ) +{ + volatile uint64 ramread = 0U; + volatile uint32 regread = 0U; + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + uint64 tcramA1_bk = tcramA1bit; + uint64 tcramB1_bk = tcramB1bit; + uint64 tcramA2_bk = tcramA2bit; + uint64 tcramB2_bk = tcramB2bit; + + /* Clear RAMOCUUR before setting RAMTHRESHOLD register */ + tcram1REG->RAMOCCUR = 0U; + tcram2REG->RAMOCCUR = 0U; + + /* Set Single-bit Error Threshold Count as 1 */ + tcram1REG->RAMTHRESHOLD = 1U; + tcram2REG->RAMTHRESHOLD = 1U; + + /* Enable single bit error generation */ + tcram1REG->RAMINTCTRL = 1U; + tcram2REG->RAMINTCTRL = 1U; + + /* Enable writes to ECC RAM, enable ECC error response */ + tcram1REG->RAMCTRL = 0x0005010AU; + tcram2REG->RAMCTRL = 0x0005010AU; + + /* Force a single bit error in both the banks */ + _coreDisableRamEcc_(); + tcramA1bitError ^= 1U; + tcramB1bitError ^= 1U; + _coreEnableRamEcc_(); + + /* Read the corrupted data to generate single bit error */ + ramread = tcramA1bit; + ( void ) ramread; + ramread = tcramB1bit; + ( void ) ramread; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U; + + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + if( ( tcram1ErrStat == 0U ) || ( tcram2ErrStat == 0U ) ) + { + /* TCRAM module does not reflect 1-bit error reported by CPU */ + selftestFailNotification( CHECKRAMECC_FAIL1 ); + } + else + { + if( ( esmREG->SR1[ 0U ] & 0x14000000U ) != 0x14000000U ) + { + /* TCRAM 1-bit error not flagged in ESM */ + selftestFailNotification( CHECKRAMECC_FAIL2 ); + } + else + { + /* Clear single bit error flag in TCRAM module */ + tcram1REG->RAMERRSTATUS = 0x1U; + tcram2REG->RAMERRSTATUS = 0x1U; + + /* Clear ESM status */ + esmREG->SR1[ 0U ] = 0x14000000U; + } + } + + /* Force a double bit error in both the banks */ + _coreDisableRamEcc_(); + tcramA2bitError ^= 3U; + tcramB2bitError ^= 3U; + _coreEnableRamEcc_(); + + /* Read the corrupted data to generate double bit error */ + ramread = tcramA2bit; + ( void ) ramread; + ramread = tcramB2bit; + ( void ) ramread; + + regread = tcram1REG->RAMUERRADDR; + ( void ) regread; + regread = tcram2REG->RAMUERRADDR; + ( void ) regread; + + /* disable writes to ECC RAM */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Compute correct ECC */ + tcramA1bit = tcramA1_bk; + tcramB1bit = tcramB1_bk; + tcramA2bit = tcramA2_bk; + tcramB2bit = tcramB2_bk; +} + +/** @fn void checkClockMonitor(void) + * @brief Check clock monitor failure detection logic. + * + * This function checks clock monitor failure detection logic. + */ +/* SourceId : SELFTEST_SourceId_035 */ +/* DesignId : SELFTEST_DesignId_028 */ +/* Requirements : HL_SR394 */ +void checkClockMonitor( void ) +{ + uint32 ghvsrc_bk; + + /* Enable clock monitor range detection circuitry */ + systemREG1->CLKTEST |= 0x03000000U; + + /* Backup register GHVSRC */ + ghvsrc_bk = systemREG1->GHVSRC; + + /* Switch all clock domains to HF LPO */ + systemREG1->GHVSRC = 0x05050005U; + + /* Disable oscillator to cause a oscillator fail */ + systemREG1->CSDISSET = 0x1U; + + /* Wait till oscillator fail flag is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->GBLSTAT & 0x1U ) == 0U ) + { + } /* Wait */ + + if( ( esmREG->SR1[ 0U ] & 0x800U ) != 0x800U ) + { + selftestFailNotification( CHECKCLOCKMONITOR_FAIL1 ); + } + else + { + /* Clear ESM flag */ + esmREG->SR1[ 0U ] = 0x800U; + + /* Disable clock monitor range detection circuitry */ + systemREG1->CLKTEST &= ~( 0x03000000U ); + + /* Enable oscillator */ + systemREG1->CSDISCLR = 0x1U; + + /* Wait until oscillator is enabled */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSVSTAT & 0x3U ) == 0U ) + { + } /* Wait */ + + /* Clear oscillator fail flag and PLL slip flag if any*/ + systemREG1->GBLSTAT = 0x301U; + + /* Switch back all clock domains */ + systemREG1->GHVSRC = ghvsrc_bk; + } +} + +/** @fn void checkFlashEEPROMECC(void) + * @brief Check Flash EEPROM ECC error detection logic. + * + * This function checks Flash EEPROM ECC error detection logic. + */ +/* SourceId : SELFTEST_SourceId_036 */ +/* DesignId : SELFTEST_DesignId_029 */ +/* Requirements : HL_SR406 */ +void checkFlashEEPROMECC( void ) +{ + uint32 ecc; + volatile uint32 regread; + + /* Set Single Error Correction Threshold as 1 */ + flashWREG->EECTRL2 |= 1U; + + /* Enable EEPROM Emulation Error Profiling */ + flashWREG->EECTRL1 |= 0x00000100U; + + /* Load FEMU_XX regs in order to generate ECC */ + flashWREG->FEMUADDR = 0xF0200000U; + flashWREG->FEMUDMSW = 0U; + flashWREG->FEMUDLSW = 0U; + + /* ECC for the correct data*/ + ecc = flashWREG->FEMUECC; + + /* Load data with 1 bit error */ + flashWREG->FEMUDMSW = 0U; + flashWREG->FEMUDLSW = 1U; + + /* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic + * testing */ + flashWREG->FDIAGCTRL = 0x00055001U; + + flashWREG->FEMUECC = ecc; + + /* Diagnostic trigger */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( ( flashWREG->EESTATUS & 0x1U ) != 0x1U ) + { + /* No single bit error was detected */ + selftestFailNotification( CHECKFLASHEEPROMECC_FAIL1 ); + } + else + { + if( ( esmREG->SR4[ 0U ] & 0x8U ) != 0x8U ) + { + /* EEPROM single bit error not captured in ESM */ + selftestFailNotification( CHECKFLASHEEPROMECC_FAIL2 ); + } + else + { + /* Clear single bit error flag in flash wrapper */ + flashWREG->EESTATUS = 0xFU; + + /* Clear ESM flag */ + esmREG->SR4[ 0U ] = 0x8U; + } + } + + /* Load data with 2 bit error */ + flashWREG->FEMUDMSW = 0U; + flashWREG->FEMUDLSW = 3U; + + /* Enable Diagnostic ECC data correction mode and select FEE SECDED for diagnostic + * testing */ + flashWREG->FDIAGCTRL = 0x00055001U; + + flashWREG->FEMUECC = ecc; + + /* Diagnostic trigger */ + flashWREG->FDIAGCTRL |= 0x01000000U; + + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( ( flashWREG->EESTATUS & 0x100U ) != 0x100U ) + { + /* No double bit error was detected */ + selftestFailNotification( CHECKFLASHEEPROMECC_FAIL3 ); + } + else + { + if( ( esmREG->SR4[ 0U ] & 0x10U ) != 0x10U ) + { + /* EEPROM double bit error not captured in ESM */ + selftestFailNotification( CHECKFLASHEEPROMECC_FAIL4 ); + } + else + { + /* Clear uncorrectable error flag in flash wrapper */ + flashWREG->EESTATUS = 0x1100U; + + /* Read EEUNCERRADD register */ + regread = flashWREG->EEUNCERRADD; + ( void ) regread; + + /* Clear ESM flag */ + esmREG->SR4[ 0U ] = 0x10U; + } + } +} + +/** @fn void checkPLL1Slip(void) + * @brief Check PLL1 Slip detection logic. + * + * This function checks PLL1 Slip detection logic. + */ +/* SourceId : SELFTEST_SourceId_037 */ +/* DesignId : SELFTEST_DesignId_030 */ +/* Requirements : HL_SR384 */ +void checkPLL1Slip( void ) +{ + uint32 ghvsrc_bk, pllctl1_bk; + + /* Back up the the registers GHVSRC and PLLCTRL1 */ + ghvsrc_bk = systemREG1->GHVSRC; + pllctl1_bk = systemREG1->PLLCTL1; + + /* Switch all clock domains to oscillator */ + systemREG1->GHVSRC = 0x00000000U; + + /* Disable Reset on PLL Slip and enable Bypass on PLL slip */ + systemREG1->PLLCTL1 &= 0x1FFFFFFFU; + + /* Force a PLL Slip */ + systemREG1->PLLCTL1 ^= 0x8000U; + + /* Wait till PLL slip flag is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->GBLSTAT & 0x300U ) == 0U ) + { + } /* Wait */ + + if( ( esmREG->SR1[ 0U ] & 0x400U ) != 0x400U ) + { + /* ESM flag not set */ + selftestFailNotification( CHECKPLL1SLIP_FAIL1 ); + } + else + { + /* Disable PLL1 */ + systemREG1->CSDISSET = 0x2U; + + /* Wait till PLL1 is disabled */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x2U ) == 0U ) + { + } /* Wait */ + + /* Restore the PLL multiplier value */ + systemREG1->PLLCTL1 ^= 0x8000U; + + /* Enable PLL1 */ + systemREG1->CSDISCLR = 0x2U; + + /* Wait till PLL1 is disabled */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x2U ) != 0U ) + { + } /* Wait */ + + /* Switch back to the initial clock source */ + systemREG1->GHVSRC = ghvsrc_bk; + + /* Clear PLL slip flag */ + systemREG1->GBLSTAT = 0x300U; + + /* Clear ESM flag */ + esmREG->SR1[ 0U ] = 0x400U; + + /* Restore the PLLCTL1 register */ + systemREG1->PLLCTL1 = pllctl1_bk; + } +} + +/** @fn void checkPLL2Slip(void) + * @brief Check PLL2 Slip detection logic. + * + * This function checks PLL2 Slip detection logic. + */ +/* SourceId : SELFTEST_SourceId_038 */ +/* DesignId : SELFTEST_DesignId_031 */ +/* Requirements : HL_SR384 */ +void checkPLL2Slip( void ) +{ + uint32 ghvsrc_bk; + + /* Back up the the register GHVSRC */ + ghvsrc_bk = systemREG1->GHVSRC; + + /* Switch all clock domains to oscillator */ + systemREG1->GHVSRC = 0x00000000U; + + /* Force a PLL2 Slip */ + systemREG2->PLLCTL3 ^= 0x8000U; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( esmREG->SR4[ 0U ] & 0x400U ) != 0x400U ) + { + /* Wait till ESM flag is set */ + } + + /* Disable PLL2 */ + systemREG1->CSDISSET = 0x40U; + + /* Wait till PLL2 is disabled */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x40U ) == 0U ) + { + } /* Wait */ + + /* Restore the PLL 2 multiplier value */ + systemREG2->PLLCTL3 ^= 0x8000U; + + /* Enable PLL2 */ + systemREG1->CSDISCLR = 0x40U; + + /* Wait till PLL2 is disabled */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x40U ) != 0U ) + { + } /* Wait */ + + /* Switch back to the initial clock source */ + systemREG1->GHVSRC = ghvsrc_bk; + + /* Clear PLL slip flag */ + systemREG1->GBLSTAT = 0x300U; + + /* Clear ESM flag */ + esmREG->SR4[ 0U ] = 0x400U; +} + +/** @fn void checkRAMAddrParity(void) + * @brief Check TCRAM Address parity error detection and signaling mechanism. + * + * This function TCRAM Address parity error detection and signaling mechanism. + */ +/* SourceId : SELFTEST_SourceId_039 */ +/* DesignId : SELFTEST_DesignId_032 */ +/* Requirements : HL_SR409 */ +void checkRAMAddrParity( void ) +{ + register uint64 ramread; + volatile uint32 regread; + uint32 tcram1ErrStat, tcram2ErrStat; + + /* Invert Address parity scheme */ + tcram1REG->RAMCTRL = 0x0D05000AU; + tcram2REG->RAMCTRL = 0x0D05000AU; + + /* Read from both RAM banks */ + ramread = tcramA1bit; + ramread = ramread | tcramB1bit; /* XOR-ing with ramread to avoid warnings */ + + /* Switch back to Address parity scheme */ + tcram1REG->RAMCTRL = 0x0005000AU; + tcram2REG->RAMCTRL = 0x0005000AU; + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x100U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x100U; + + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + /*SAFETYMCUSW 139 S MR:13.7 "LDRA Tool issue" */ + if( ( tcram1ErrStat == 0U ) || ( tcram2ErrStat == 0U ) ) + { + /* No Address parity error detected */ + selftestFailNotification( CHECKRAMADDRPARITY_FAIL1 ); + } + else + { + if( ( esmREG->SR1[ 1U ] & 0x1400U ) != 0x1400U ) + { + /* Address parity error not reported to ESM */ + selftestFailNotification( CHECKRAMADDRPARITY_FAIL2 ); + } + else + { + /* Clear Address parity error flag */ + tcram1REG->RAMERRSTATUS = 0x300U; + tcram2REG->RAMERRSTATUS = 0x300U; + + /* Clear ESM flag */ + esmREG->SR1[ 1U ] = 0x1400U; + + /* The nERROR pin will become inactive once the LTC counter expires */ + esmREG->EKR = 0x5U; + + regread = tcram1REG->RAMPERADDR; + ( void ) regread; + regread = tcram2REG->RAMPERADDR; + ( void ) regread; + } + } +} + +/** @fn void checkRAMUERRTest(void) + * @brief Run RAM test + * + * This function runs RAM test to test the redundant address decode and compare logic. + */ +/* SourceId : SELFTEST_SourceId_040 */ +/* DesignId : SELFTEST_DesignId_033 */ +/* Requirements : HL_SR410 */ +void checkRAMUERRTest( void ) +{ + uint32 tcram1ErrStat, tcram2ErrStat = 0U; + + /* Trigger equality check */ + tcram1REG->RAMTEST = 0x018AU; + tcram2REG->RAMTEST = 0x018AU; + + /* Wait till test is completed */ + while( tcram1REG->RAMTEST != 0x008AU ) + { + } /* Wait */ + + while( tcram2REG->RAMTEST != 0x008AU ) + { + } /* Wait */ + + /* Check for error status */ + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x10U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x10U; + + if( ( tcram1ErrStat == 0x10U ) || ( tcram2ErrStat == 0x10U ) ) + { + /* test failed */ + selftestFailNotification( CHECKRAMUERRTEST_FAIL1 ); + } + + /* Trigger inequality check */ + tcram1REG->RAMTEST = 0x014AU; + tcram2REG->RAMTEST = 0x014AU; + + /* Wait till test is completed */ + while( tcram1REG->RAMTEST != 0x004AU ) + { + } /* Wait */ + + while( tcram2REG->RAMTEST != 0x004AU ) + { + } /* Wait */ + + tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x10U; + tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x10U; + + if( ( tcram1ErrStat == 0x10U ) || ( tcram2ErrStat == 0x10U ) ) + { + /* test failed */ + selftestFailNotification( CHECKRAMUERRTEST_FAIL2 ); + } + else + { + tcram1REG->RAMERRSTATUS = 0x4U; + tcram2REG->RAMERRSTATUS = 0x4U; + + /* Clear ESM flag */ + esmREG->SR1[ 1U ] = 0x140U; + esmREG->SSR2 = 0x140U; + esmREG->EKR = 0x5U; + } + + /* Disable RAM test mode */ + tcram1REG->RAMTEST = 0x5U; + tcram2REG->RAMTEST = 0x5U; +} + +/* SourceId : SELFTEST_SourceId_041 */ +/* DesignId : SELFTEST_DesignId_018 */ +/* Requirements : HL_SR407 */ +void fmcBus1ParityCheck( void ) +{ + uint32 regBkupFparOvr, regBckupFdiagctrl; + volatile uint32 flashread = 0U; + + /* Backup registers */ + regBkupFparOvr = flashWREG->FPAROVR; + regBckupFdiagctrl = flashWREG->FDIAGCTRL; + + /* Read to unfreeze the error address registers */ + flashread = flashWREG->FUNCERRADD; + ( void ) flashread; + + /* clear status register */ + flashWREG->FEDACSTATUS = 0x400U; + + /* Enable Parity Error */ + flashWREG->FPAROVR = ( uint32 ) ( ( uint32 ) 0x5U << 9U ) + | ( uint32 ) ( ( uint32 ) 0x5U << 12U ); + + /* set Diag test mode */ + flashWREG->FDIAGCTRL = 0x00050000U | 0x00000007U; + + /* Add parity */ + flashWREG->FPAROVR |= 0x00000100U; + + /* Start Test */ + flashWREG->FDIAGCTRL |= 0x1000000U; + + /* Wait until test done */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + while( ( flashWREG->FDIAGCTRL & 0x1000000U ) == 0x1000000U ) + { + } /* Wait */ + + /* Check address Error */ + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( ( flashWREG->FEDACSTATUS & 0x400U ) != 0x400U ) + { + selftestFailNotification( FMCBUS1PARITYCHECK_FAIL1 ); + } + else + { + /* clear status register */ + flashWREG->FEDACSTATUS = 0x400U; + + /* check if ESM is flagged */ + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( ( esmREG->SR1[ 1U ] & 0x0000010U ) == 0U ) + { + selftestFailNotification( FMCBUS1PARITYCHECK_FAIL2 ); + } + else + { + /* clear ESM flag */ + esmREG->SR1[ 1U ] |= 0x0000010U; + esmREG->SSR2 |= 0x0000010U; + esmREG->EKR = 0x5U; + + /* Stop Diag test mode */ + flashWREG->FDIAGCTRL = regBckupFdiagctrl; + flashWREG->FPAROVR = regBkupFparOvr; + } + } + + /* Read to unfreeze the error address registers */ + flashread = flashWREG->FUNCERRADD; +} + +/* SourceId : SELFTEST_SourceId_042 */ +/* DesignId : SELFTEST_DesignId_011 */ +/* Requirements : HL_SR401 */ +void pbistFail( void ) +{ + uint32 PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0; + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + PBIST_RAMT = pbistREG->RAMT; + PBIST_FSRA0 = pbistREG->FSRA0; + PBIST_FSRDL0 = pbistREG->FSRDL0; + + if( pbistPortTestStatus( ( uint32 ) PBIST_PORT0 ) != TRUE ) + { + memoryPort0TestFailNotification( ( uint32 ) ( ( PBIST_RAMT & 0xFF000000U ) + >> 24U ), + ( uint32 ) ( ( PBIST_RAMT & 0x00FF0000U ) + >> 16U ), + ( uint32 ) PBIST_FSRA0, + ( uint32 ) PBIST_FSRDL0 ); + } + else + { + /* USER CODE BEGIN (77) */ + /* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA "for(;;) can be removed by adding "# if 0" and + * "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA "for(;;) can be removed by adding "# if 0" and + * "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA "for(;;) can be removed by adding "# if 0" and + * "# endif" in the user codes above and below" */ + for( ;; ) + { + } /* Wait */ + + /* USER CODE BEGIN (78) */ + /* USER CODE END */ + } +} + +/** @fn void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SELFTEST_SourceId_043 */ +/* DesignId : SELFTEST_DesignId_034 */ +/* Requirements : HL_SR506 */ +void pbistGetConfigValue( pbist_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_RAMT = PBIST_RAMT_CONFIGVALUE; + config_reg->CONFIG_DLR = PBIST_DLR_CONFIGVALUE; + config_reg->CONFIG_PACT = PBIST_PACT_CONFIGVALUE; + config_reg->CONFIG_PBISTID = PBIST_PBISTID_CONFIGVALUE; + config_reg->CONFIG_OVER = PBIST_OVER_CONFIGVALUE; + config_reg->CONFIG_FSRDL1 = PBIST_FSRDL1_CONFIGVALUE; + config_reg->CONFIG_ROM = PBIST_ROM_CONFIGVALUE; + config_reg->CONFIG_ALGO = PBIST_ALGO_CONFIGVALUE; + config_reg->CONFIG_RINFOL = PBIST_RINFOL_CONFIGVALUE; + config_reg->CONFIG_RINFOU = PBIST_RINFOU_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_RAMT = pbistREG->RAMT; + config_reg->CONFIG_DLR = pbistREG->DLR; + config_reg->CONFIG_PACT = pbistREG->PACT; + config_reg->CONFIG_PBISTID = pbistREG->PBISTID; + config_reg->CONFIG_OVER = pbistREG->OVER; + config_reg->CONFIG_FSRDL1 = pbistREG->FSRDL1; + config_reg->CONFIG_ROM = pbistREG->ROM; + config_reg->CONFIG_ALGO = pbistREG->ALGO; + config_reg->CONFIG_RINFOL = pbistREG->RINFOL; + config_reg->CONFIG_RINFOU = pbistREG->RINFOU; + } +} + +/** @fn void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SELFTEST_SourceId_044 */ +/* DesignId : SELFTEST_DesignId_035 */ +/* Requirements : HL_SR506 */ +void stcGetConfigValue( stc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_STCGCR0 = STC_STCGCR0_CONFIGVALUE; + config_reg->CONFIG_STCGCR1 = STC_STCGCR1_CONFIGVALUE; + config_reg->CONFIG_STCTPR = STC_STCTPR_CONFIGVALUE; + config_reg->CONFIG_STCSCSCR = STC_STCSCSCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_STCGCR0 = stcREG->STCGCR0; + config_reg->CONFIG_STCGCR1 = stcREG->STCGCR1; + config_reg->CONFIG_STCTPR = stcREG->STCTPR; + config_reg->CONFIG_STCSCSCR = stcREG->STCSCSCR; + } +} + +/** @fn void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SELFTEST_SourceId_045 */ +/* DesignId : SELFTEST_DesignId_036 */ +/* Requirements : HL_SR506 */ +void efcGetConfigValue( efc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_BOUNDARY = EFC_BOUNDARY_CONFIGVALUE; + config_reg->CONFIG_PINS = EFC_PINS_CONFIGVALUE; + config_reg->CONFIG_SELFTESTCYCLES = EFC_SELFTESTCYCLES_CONFIGVALUE; + config_reg->CONFIG_SELFTESTSIGN = EFC_SELFTESTSIGN_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_BOUNDARY = efcREG->BOUNDARY; + config_reg->CONFIG_PINS = efcREG->PINS; + config_reg->CONFIG_SELFTESTCYCLES = efcREG->SELF_TEST_CYCLES; + config_reg->CONFIG_SELFTESTSIGN = efcREG->SELF_TEST_SIGN; + } +} + +/** @fn void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SELFTEST_SourceId_046 */ +/* DesignId : SELFTEST_DesignId_037 */ +/* Requirements : HL_SR506 */ +void ccmr4GetConfigValue( ccmr4_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CCMKEYR = CCMR4_CCMKEYR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CCMKEYR = CCMKEYR; + } +} + +/** @fn void errata_PBIST_4(void) + * @brief Workaround for the Errata PBIST#4. + * + * This function is workaround for Errata PBIST#4. + * This function is designed to initialize the ROMs using the PBIST controller. + * The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM. + * This function should be called at startup after system init before using the ROMs. + * + * @note : This Function uses register's which are not exposed to users through + * TRM , to run custom algorithm. User can use this function as Black box. + * + */ +void errata_PBIST_4( void ) +{ + volatile uint32 i = 0U; + uint8 ROM_count; + sint32 PBIST_wait_done_loop; + uint32 pmuCalibration, pmuCount; + + /* PMU calibration */ + _pmuEnableCountersGlobal_(); + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + _pmuStopCounters_( pmuCYCLE_COUNTER ); + pmuCalibration = _pmuGetCycleCount_(); + + /* ROM_init Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + *( volatile uint32 * ) 0xFFFF0400U = 0x0000000AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000EE0AU; + + /* Loop for Executing PBIST ROM and STC ROM */ + for( ROM_count = 0U; ROM_count < 2U; ROM_count++ ) + { + PBIST_wait_done_loop = 0; + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST Clocks did not disable */ + if( pbistREG->PACT != 0x0U ) + { + selftestFailNotification( PBISTSELFCHECK_FAIL3 ); + } + else + { + /* PBIST ROM clock frequency = HCLK frequency /2 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000105U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000010AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + for( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) + { /* Wait */ + } + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Load PBIST ALGO to initialize the ROMs */ + *( volatile uint32 * ) 0xFFFFE400U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE440U = 0x00000025U; + *( volatile uint32 * ) 0xFFFFE404U = 0x62400001U; + *( volatile uint32 * ) 0xFFFFE444U = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE408U = 0x00068003U; + *( volatile uint32 * ) 0xFFFFE448U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE40CU = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE44CU = 0x00006860U; + *( volatile uint32 * ) 0xFFFFE410U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE450U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE540U = 0x000003E8U; + *( volatile uint32 * ) 0xFFFFE550U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE530U = 0x00000000U; + + /* SELECT ROM */ + if( ROM_count == 1U ) + { + /* SELECT PBIST ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0x00000002U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00000000U; + pbistREG->RAMT = 0x01002008U; + } + else + { + /* SELECT STC ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x0A63FFFFU; + pbistREG->RAMT = 0x02002008U; + } + + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; + pbistREG->rsvd1[ 0U ] = 3U; + + /* Start PMU counter */ + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + + /* PBIST_RUN */ + pbistREG->rsvd1[ 1U ] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->MSTCGSTAT & 0x1U ) != 0x1U ) + { + } /* Wait */ + + /* Stop PMU counter */ + _pmuStopCounters_( pmuCYCLE_COUNTER ); + + /* Get CPU cycle count */ + pmuCount = _pmuGetCycleCount_(); + + /* Calculate PBIST test complete time in ROM Clock */ + /* 2 - Divide value ( Default is 2 in HALCoGen) */ + /* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */ + pmuCount = pmuCount - pmuCalibration; + PBIST_wait_done_loop = ( ( sint32 ) pmuCount / 2 ) - 1000; + + /* Check PBIST status results (Address, Status, Count, etc...) */ + if( ( pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 + | pbistREG->FSRDL1 | pbistREG->rsvd4[ 0U ] | pbistREG->rsvd4[ 1U ] ) + != 0U ) + { + /* PBIST Failure for the Algorithm chosen above */ + selftestFailNotification( PBISTSELFCHECK_FAIL1 ); + } + + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected */ + if( ( PBIST_wait_done_loop <= 20 ) || ( PBIST_wait_done_loop >= 200 ) ) + { + selftestFailNotification( PBISTSELFCHECK_FAIL2 ); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + } + } /* ROM Loop */ + + /* ROM restore default setup */ + /* (must be completed before continuing) */ + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA0AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA05U; + *( volatile uint32 * ) 0xFFFF0400U = 0x00000005U; + + _pmuDisableCountersGlobal_(); +} + +/** @fn void enableParity(void) + * @brief Enable peripheral RAM parity + * + * This function enables RAM parity for all peripherals for which RAM parity check is + * enabled. This function is called before memoryInit in the startup + * + */ +void enableParity( void ) +{ +} + +/** @fn void disableParity(void) + * @brief Disable peripheral RAM parity + * + * This function disables RAM parity for all peripherals for which RAM parity check is + * enabled. This function is called after memoryInit in the startup + * + */ +void disableParity( void ) +{ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_startup.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_startup.c new file mode 100644 index 00000000000..551ca666b41 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_startup.c @@ -0,0 +1,416 @@ +/** @file sys_startup.c + * @brief Startup Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Include Files + * - Type Definitions + * - External Functions + * - VIM RAM Setup + * - Startup Routine + * . + * which are relevant for the Startup. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "sys_common.h" +#include "system.h" +#include "sys_vim.h" +#include "sys_core.h" +#include "sys_selftest.h" +#include "esm.h" +#include "mibspi.h" + +#include "errata_SSWF021_45.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* External Functions */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(main should be declared by the user)" + */ +extern void main( void ); +/*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be present)" + */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(Extern declaration present in the + * library)" */ +extern void exit( int _status ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +void handlePLLLockFail( void ); +/* Startup Routine */ +void _c_int00( void ) __attribute__( ( noreturn ) ); +#define PLL_RETRIES 5U +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +__attribute__( ( naked ) ) + +/* SourceId : STARTUP_SourceId_001 */ +/* DesignId : STARTUP_DesignId_001 */ +/* Requirements : HL_SR508 */ +void _c_int00( void ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /* Initialize Core Registers to avoid CCM Error */ + _coreInitRegisters_(); + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /* Initialize Stack Pointers */ + _coreInitStackPointer_(); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Workaround for Errata CORTEXR4 66 */ + _errata_CORTEXR4_66_(); + + /* Workaround for Errata CORTEXR4 57 */ + _errata_CORTEXR4_57_(); + + /* Reset handler: the following instructions read from the system exception status + * register to identify the cause of the CPU reset. + */ + + /* check for power-on reset condition */ + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( ( SYS_EXCEPTION & POWERON_RESET ) != 0U ) + { + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + /* Add condition to check whether PLL can be started successfully */ + if( _errata_SSWF021_45_both_plls( PLL_RETRIES ) != 0U ) + { + /* Put system in a safe state */ + handlePLLLockFail(); + } + + /* clear all reset status flags */ + SYS_EXCEPTION = 0xFFFFU; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + /* continue with normal start-up sequence */ + } + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + else if( ( SYS_EXCEPTION & OSC_FAILURE_RESET ) != 0U ) + { + /* Reset caused due to oscillator failure. + * Add user code here to handle oscillator failure */ + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + } + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + else if( ( SYS_EXCEPTION & WATCHDOG_RESET ) != 0U ) + { + /* Reset caused due + * 1) windowed watchdog violation - Add user code here to handle watchdog + * violation. 2) ICEPICK Reset - After loading code via CCS / System Reset through + * CCS + */ + /* Check the WatchDog Status register */ + if( WATCHDOG_STATUS != 0U ) + { + /* Add user code here to handle watchdog violation. */ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* Clear the Watchdog reset flag in Exception Status register */ + SYS_EXCEPTION = WATCHDOG_RESET; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + } + else + { + /* Clear the ICEPICK reset flag in Exception Status register */ + SYS_EXCEPTION = ICEPICK_RESET; + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + } + } + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + else if( ( SYS_EXCEPTION & CPU_RESET ) != 0U ) + { + /* Reset caused due to CPU reset. + * CPU reset can be caused by CPU self-test completion, or + * by toggling the "CPU RESET" bit of the CPU Reset Control Register. */ + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* clear all reset status flags */ + SYS_EXCEPTION = CPU_RESET; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + } + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + else if( ( SYS_EXCEPTION & SW_RESET ) != 0U ) + { + /* Reset caused due to software reset. + * Add user code to handle software reset. */ + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + } + else + { + /* Reset caused by nRST being driven low externally. + * Add user code to handle external reset. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + } + + /* Check if there were ESM group3 errors during power-up. + * These could occur during eFuse auto-load or during reads from flash OTP + * during power-up. Device operation is not reliable and not recommended + * in this case. + * An ESM group3 error only drives the nERROR pin low. An external circuit + * that monitors the nERROR pin must take the appropriate action to ensure that + * the system is placed in a safe state, as determined by the application. + */ + if( ( esmREG->SR1[ 2 ] ) != 0U ) + { + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + /*SAFETYMCUSW 5 C MR:NA "for(;;) can be removed by adding "# if 0" and + * "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 26 S MR:NA "for(;;) can be removed by adding "# if 0" and + * "# endif" in the user codes above and below" */ + /*SAFETYMCUSW 28 D MR:NA "for(;;) can be removed by adding "# if 0" and + * "# endif" in the user codes above and below" */ + for( ;; ) + { + } /* Wait */ + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + } + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Initialize System - Clock, Flash settings with Efuse self check */ + systemInit(); + + /* Run PBIST on STC ROM */ + pbistRun( ( uint32 ) STC_ROM_PBIST_RAM_GROUP, + ( ( uint32 ) PBIST_TripleReadSlow | ( uint32 ) PBIST_TripleReadFast ) ); + + /* Wait for PBIST for STC ROM to be completed */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( pbistIsTestCompleted() != TRUE ) + { + } /* Wait */ + + /* Check if PBIST on STC ROM passed the self-test */ + if( pbistIsTestPassed() != TRUE ) + { + /* PBIST and STC ROM failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ + + pbistFail(); + } + + /* Disable PBIST clocks and disable memory self-test mode */ + pbistStop(); + + /* Run PBIST on PBIST ROM */ + pbistRun( ( uint32 ) PBIST_ROM_PBIST_RAM_GROUP, + ( ( uint32 ) PBIST_TripleReadSlow | ( uint32 ) PBIST_TripleReadFast ) ); + + /* Wait for PBIST for PBIST ROM to be completed */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( pbistIsTestCompleted() != TRUE ) + { + } /* Wait */ + + /* Check if PBIST ROM passed the self-test */ + if( pbistIsTestPassed() != TRUE ) + { + /* PBIST and STC ROM failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ + + pbistFail(); + } + + /* Disable PBIST clocks and disable memory self-test mode */ + pbistStop(); + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ + + /* Initialize CPU RAM. + * This function uses the system module's hardware for auto-initialization of memories + * and their associated protection schemes. The CPU RAM is initialized by setting bit + * 0 of the MSIENA register. Hence the value 0x1 passed to the function. This function + * will initialize the entire CPU RAM and the corresponding ECC locations. + */ + memoryInit( 0x1U ); + + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + /* Enable ECC checking for TCRAM accesses. + * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. + */ + _coreEnableRamEcc_(); + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + + /* USER CODE BEGIN (55) */ + /* USER CODE END */ + + /* USER CODE BEGIN (68) */ + /* USER CODE END */ + + /* USER CODE BEGIN (72) */ + /* USER CODE END */ + + /* Enable IRQ offset via Vic controller */ + _coreEnableIrqVicOffset_(); + + /* USER CODE BEGIN (73) */ + /* USER CODE END */ + + /* Initialize VIM table */ + vimInit(); + + /* USER CODE BEGIN (74) */ + /* USER CODE END */ + + /* Configure system response to error conditions signaled to the ESM group1 */ + /* This function can be configured from the ESM tab of HALCoGen */ + esmInit(); + { + extern uint32 _sidata, _sdata, _edata; + extern uint32 _siPrivData, __privileged_data_start__, __privileged_data_end__; + uint32 *src, *dst; + + src = &_sidata; + dst = &_sdata; + + while( dst < &_edata ) + { + *dst++ = *src++; + } + + src = &_siPrivData; + dst = &__privileged_data_start__; + + while( dst < &__privileged_data_end__ ) + { + *dst++ = *src++; + } + } + /* USER CODE BEGIN (75) */ + /* USER CODE END */ + + /* call the application */ + /*SAFETYMCUSW 296 S MR:8.6 "Startup code(library functions at block scope)" + */ + /*SAFETYMCUSW 326 S MR:8.2 "Startup code(Declaration for main in library)" + */ + /*SAFETYMCUSW 60 D MR:8.8 "Startup code(Declaration for main in + * library;Only doing an extern for the same)" */ + main(); + + /*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be + * present)" */ + exit( 0 ); + /* USER CODE BEGIN (77) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (78) */ +/* USER CODE END */ + +/** @fn void handlePLLLockFail(void) + * @brief This function handles PLL lock fail. + */ +void handlePLLLockFail( void ) +{ + /* USER CODE BEGIN (79) */ + /* USER CODE END */ + while( 1 ) + { + } + + /* USER CODE BEGIN (80) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (81) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_vim.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_vim.c new file mode 100644 index 00000000000..b050ab9e4bd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/sys_vim.c @@ -0,0 +1,837 @@ +/** @file sys_vim.c + * @brief VIM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_vim.h" +#include "system.h" +#include "esm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Vim Ram Definition */ + +/** @struct vimRam + * @brief Vim Ram Definition + * + * This type is used to access the Vim Ram. + */ + +/** @typedef vimRAM_t + * @brief Vim Ram Type Definition + * + * This type is used to access the Vim Ram. + */ +typedef volatile struct vimRam +{ + t_isrFuncPTR ISR[ VIM_CHANNELS ]; +} vimRAM_t; + +#define vimRAM ( ( vimRAM_t * ) 0xFFF82000U ) + +static const t_isrFuncPTR s_vim_init[ 128U ] = { + &phantomInterrupt, &esmHighInterrupt, /* Channel 0 */ + &phantomInterrupt, /* Channel 1 */ + &FreeRTOS_IRQ_Handler, /* Channel 2 */ + &phantomInterrupt, /* Channel 3 */ + &phantomInterrupt, /* Channel 4 */ + &phantomInterrupt, /* Channel 5 */ + &phantomInterrupt, /* Channel 6 */ + &phantomInterrupt, /* Channel 7 */ + &phantomInterrupt, /* Channel 8 */ + &phantomInterrupt, /* Channel 9 */ + &phantomInterrupt, /* Channel 10 */ + &phantomInterrupt, /* Channel 11 */ + &phantomInterrupt, /* Channel 12 */ + &phantomInterrupt, /* Channel 13 */ + &phantomInterrupt, /* Channel 14 */ + &phantomInterrupt, /* Channel 15 */ + &phantomInterrupt, /* Channel 16 */ + &phantomInterrupt, /* Channel 17 */ + &phantomInterrupt, /* Channel 18 */ + &phantomInterrupt, /* Channel 19 */ + &phantomInterrupt, /* Channel 20 */ + &FreeRTOS_IRQ_Handler, /* Channel 21 */ + &phantomInterrupt, /* Channel 22 */ + &phantomInterrupt, /* Channel 23 */ + &phantomInterrupt, /* Channel 24 */ + &phantomInterrupt, /* Channel 25 */ + &phantomInterrupt, /* Channel 26 */ + &phantomInterrupt, /* Channel 27 */ + &phantomInterrupt, /* Channel 28 */ + &phantomInterrupt, /* Channel 29 */ + &phantomInterrupt, /* Channel 30 */ + &phantomInterrupt, /* Channel 31 */ + &phantomInterrupt, /* Channel 32 */ + &phantomInterrupt, /* Channel 33 */ + &phantomInterrupt, /* Channel 34 */ + &phantomInterrupt, /* Channel 35 */ + &phantomInterrupt, /* Channel 36 */ + &phantomInterrupt, /* Channel 37 */ + &phantomInterrupt, /* Channel 38 */ + &phantomInterrupt, /* Channel 39 */ + &phantomInterrupt, /* Channel 40 */ + &phantomInterrupt, /* Channel 41 */ + &phantomInterrupt, /* Channel 42 */ + &phantomInterrupt, /* Channel 43 */ + &phantomInterrupt, /* Channel 44 */ + &phantomInterrupt, /* Channel 45 */ + &phantomInterrupt, /* Channel 46 */ + &phantomInterrupt, /* Channel 47 */ + &phantomInterrupt, /* Channel 48 */ + &phantomInterrupt, /* Channel 49 */ + &phantomInterrupt, /* Channel 50 */ + &phantomInterrupt, /* Channel 51 */ + &phantomInterrupt, /* Channel 52 */ + &phantomInterrupt, /* Channel 53 */ + &phantomInterrupt, /* Channel 54 */ + &phantomInterrupt, /* Channel 55 */ + &phantomInterrupt, /* Channel 56 */ + &phantomInterrupt, /* Channel 57 */ + &phantomInterrupt, /* Channel 58 */ + &phantomInterrupt, /* Channel 59 */ + &phantomInterrupt, /* Channel 60 */ + &phantomInterrupt, /* Channel 61 */ + &phantomInterrupt, /* Channel 62 */ + &phantomInterrupt, /* Channel 63 */ + &phantomInterrupt, /* Channel 64 */ + &phantomInterrupt, /* Channel 65 */ + &phantomInterrupt, /* Channel 66 */ + &phantomInterrupt, /* Channel 67 */ + &phantomInterrupt, /* Channel 68 */ + &phantomInterrupt, /* Channel 69 */ + &phantomInterrupt, /* Channel 70 */ + &phantomInterrupt, /* Channel 71 */ + &phantomInterrupt, /* Channel 72 */ + &phantomInterrupt, /* Channel 73 */ + &phantomInterrupt, /* Channel 74 */ + &phantomInterrupt, /* Channel 75 */ + &phantomInterrupt, /* Channel 76 */ + &phantomInterrupt, /* Channel 77 */ + &phantomInterrupt, /* Channel 78 */ + &phantomInterrupt, /* Channel 79 */ + &phantomInterrupt, /* Channel 80 */ + &phantomInterrupt, /* Channel 81 */ + &phantomInterrupt, /* Channel 82 */ + &phantomInterrupt, /* Channel 83 */ + &phantomInterrupt, /* Channel 84 */ + &phantomInterrupt, /* Channel 85 */ + &phantomInterrupt, /* Channel 86 */ + &phantomInterrupt, /* Channel 87 */ + &phantomInterrupt, /* Channel 88 */ + &phantomInterrupt, /* Channel 89 */ + &phantomInterrupt, /* Channel 90 */ + &phantomInterrupt, /* Channel 91 */ + &phantomInterrupt, /* Channel 92 */ + &phantomInterrupt, /* Channel 93 */ + &phantomInterrupt, /* Channel 94 */ + &phantomInterrupt, /* Channel 95 */ + &phantomInterrupt, /* Channel 96 */ + &phantomInterrupt, /* Channel 97 */ + &phantomInterrupt, /* Channel 98 */ + &phantomInterrupt, /* Channel 99 */ + &phantomInterrupt, /* Channel 100 */ + &phantomInterrupt, /* Channel 101 */ + &phantomInterrupt, /* Channel 102 */ + &phantomInterrupt, /* Channel 103 */ + &phantomInterrupt, /* Channel 104 */ + &phantomInterrupt, /* Channel 105 */ + &phantomInterrupt, /* Channel 106 */ + &phantomInterrupt, /* Channel 107 */ + &phantomInterrupt, /* Channel 108 */ + &phantomInterrupt, /* Channel 109 */ + &phantomInterrupt, /* Channel 110 */ + &phantomInterrupt, /* Channel 111 */ + &phantomInterrupt, /* Channel 112 */ + &phantomInterrupt, /* Channel 113 */ + &phantomInterrupt, /* Channel 114 */ + &phantomInterrupt, /* Channel 115 */ + &phantomInterrupt, /* Channel 116 */ + &phantomInterrupt, /* Channel 117 */ + &phantomInterrupt, /* Channel 118 */ + &phantomInterrupt, /* Channel 119 */ + &phantomInterrupt, /* Channel 120 */ + &phantomInterrupt, /* Channel 121 */ + &phantomInterrupt, /* Channel 122 */ + &phantomInterrupt, /* Channel 123 */ + &phantomInterrupt, /* Channel 124 */ + &phantomInterrupt, /* Channel 125 */ + &phantomInterrupt, /* Channel 126 */ +}; +void vimParityErrorHandler( void ); + +/** @fn void vimInit(void) + * @brief Initializes VIM module + * + * This function initializes VIM RAM and registers + */ +/* SourceId : VIM_SourceId_001 */ +/* DesignId : VIM_DesignId_001 */ +/* Requirements : HL_SR100 */ +void vimInit( void ) +{ + /* VIM RAM Parity Enable */ + VIM_PARCTL = 0xAU; + + /* Initialize VIM table */ + { + uint32 i; + + for( i = 0U; i < VIM_CHANNELS; i++ ) + { + vimRAM->ISR[ i ] = s_vim_init[ i ]; + } + } + + /* Set Fall-Back Address Parity Error Register */ + /*SAFETYMCUSW 439 S MR:11.3 " Need to store the address of a function in a + * 32 bit register - Advisory as per MISRA" */ + VIM_FBPARERR = ( uint32 ) &vimParityErrorHandler; + + /* set IRQ/FIQ priorities */ + vimREG->FIRQPR0 = ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR1 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR2 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR3 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + /* enable interrupts */ + vimREG->REQMASKSET0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 1U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET1 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET2 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET3 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + /* Set Capture event sources */ + vimREG->CAPEVT = ( ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ); +} + +/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler) + * @brief Map selected interrupt request to the selected channel + * + * @param[in] request: Interrupt request number 2..127 + * @param[in] channel: VIM Channel number 2..127 + * @param[in] handler: Address of the interrupt handler + * + * This function will map selected interrupt request to the selected channel. + * + */ +/* SourceId : VIM_SourceId_002 */ +/* DesignId : VIM_DesignId_002 */ +/* Requirements : HL_SR101 */ +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ) +{ + uint32 i, j; + + i = channel >> 2U; /* Find the register to configure */ + j = channel - ( i << 2U ); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /*Mapping the required interrupt request to the required channel*/ + vimREG->CHANCTRL[ i ] &= ~( uint32 ) ( ( uint32 ) 0xFFU << j ); + vimREG->CHANCTRL[ i ] |= ( request << j ); + + /*Updating VIMRAM*/ + vimRAM->ISR[ channel + 1U ] = handler; +} + +/** @fn void vimEnableInterrupt(uint32 channel, boolean inttype) + * @brief Enable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..127 + * @param[in] inttype: Interrupt type + * - SYS_IRQ: Selected channel will be enabled as IRQ + * - SYS_FIQ: Selected channel will be enabled as FIQ + * + * This function will enable interrupt for the selected channel. + * + */ +/* SourceId : VIM_SourceId_003 */ +/* DesignId : VIM_DesignId_003 */ +/* Requirements : HL_SR102 */ +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ) +{ + if( channel >= 96U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR3 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 96U ) ); + } + else + { + vimREG->FIRQPR3 |= ( ( uint32 ) 1U << ( channel - 96U ) ); + } + + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR2 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 64U ) ); + } + else + { + vimREG->FIRQPR2 |= ( ( uint32 ) 1U << ( channel - 64U ) ); + } + + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR1 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 32U ) ); + } + else + { + vimREG->FIRQPR1 |= ( ( uint32 ) 1U << ( channel - 32U ) ); + } + + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR0 &= ~( uint32 ) ( ( uint32 ) 1U << channel ); + } + else + { + vimREG->FIRQPR0 |= ( ( uint32 ) 1U << channel ); + } + + vimREG->REQMASKSET0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } +} + +/** @fn void vimDisableInterrupt(uint32 channel) + * @brief Disable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..127 + * + * This function will disable interrupt for the selected channel. + * + */ +/* SourceId : VIM_SourceId_004 */ +/* DesignId : VIM_DesignId_004 */ +/* Requirements : HL_SR103 */ +void vimDisableInterrupt( uint32 channel ) +{ + if( channel >= 96U ) + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } +} + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : VIM_SourceId_005 */ +/* DesignId : VIM_DesignId_005 */ +/* Requirements : HL_SR104 */ +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE; + config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE; + config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE; + config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE; + config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 0U ] = VIM_CHANCTRL0_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 1U ] = VIM_CHANCTRL1_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 2U ] = VIM_CHANCTRL2_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 3U ] = VIM_CHANCTRL3_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 4U ] = VIM_CHANCTRL4_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 5U ] = VIM_CHANCTRL5_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 6U ] = VIM_CHANCTRL6_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 7U ] = VIM_CHANCTRL7_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 8U ] = VIM_CHANCTRL8_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 9U ] = VIM_CHANCTRL9_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 10U ] = VIM_CHANCTRL10_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 11U ] = VIM_CHANCTRL11_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 12U ] = VIM_CHANCTRL12_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 13U ] = VIM_CHANCTRL13_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 14U ] = VIM_CHANCTRL14_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 15U ] = VIM_CHANCTRL15_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 16U ] = VIM_CHANCTRL16_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 17U ] = VIM_CHANCTRL17_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 18U ] = VIM_CHANCTRL18_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 19U ] = VIM_CHANCTRL19_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 20U ] = VIM_CHANCTRL20_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 21U ] = VIM_CHANCTRL21_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 22U ] = VIM_CHANCTRL22_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 23U ] = VIM_CHANCTRL23_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 24U ] = VIM_CHANCTRL24_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 25U ] = VIM_CHANCTRL25_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 26U ] = VIM_CHANCTRL26_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 27U ] = VIM_CHANCTRL27_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 28U ] = VIM_CHANCTRL28_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 29U ] = VIM_CHANCTRL29_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 30U ] = VIM_CHANCTRL30_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 31U ] = VIM_CHANCTRL31_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0; + config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1; + config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2; + config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3; + config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0; + config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1; + config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2; + config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3; + config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0; + config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1; + config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2; + config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3; + config_reg->CONFIG_CAPEVT = vimREG->CAPEVT; + config_reg->CONFIG_CHANCTRL[ 0U ] = vimREG->CHANCTRL[ 0U ]; + config_reg->CONFIG_CHANCTRL[ 1U ] = vimREG->CHANCTRL[ 1U ]; + config_reg->CONFIG_CHANCTRL[ 2U ] = vimREG->CHANCTRL[ 2U ]; + config_reg->CONFIG_CHANCTRL[ 3U ] = vimREG->CHANCTRL[ 3U ]; + config_reg->CONFIG_CHANCTRL[ 4U ] = vimREG->CHANCTRL[ 4U ]; + config_reg->CONFIG_CHANCTRL[ 5U ] = vimREG->CHANCTRL[ 5U ]; + config_reg->CONFIG_CHANCTRL[ 6U ] = vimREG->CHANCTRL[ 6U ]; + config_reg->CONFIG_CHANCTRL[ 7U ] = vimREG->CHANCTRL[ 7U ]; + config_reg->CONFIG_CHANCTRL[ 8U ] = vimREG->CHANCTRL[ 8U ]; + config_reg->CONFIG_CHANCTRL[ 9U ] = vimREG->CHANCTRL[ 9U ]; + config_reg->CONFIG_CHANCTRL[ 10U ] = vimREG->CHANCTRL[ 10U ]; + config_reg->CONFIG_CHANCTRL[ 11U ] = vimREG->CHANCTRL[ 11U ]; + config_reg->CONFIG_CHANCTRL[ 12U ] = vimREG->CHANCTRL[ 12U ]; + config_reg->CONFIG_CHANCTRL[ 13U ] = vimREG->CHANCTRL[ 13U ]; + config_reg->CONFIG_CHANCTRL[ 14U ] = vimREG->CHANCTRL[ 14U ]; + config_reg->CONFIG_CHANCTRL[ 15U ] = vimREG->CHANCTRL[ 15U ]; + config_reg->CONFIG_CHANCTRL[ 16U ] = vimREG->CHANCTRL[ 16U ]; + config_reg->CONFIG_CHANCTRL[ 17U ] = vimREG->CHANCTRL[ 17U ]; + config_reg->CONFIG_CHANCTRL[ 18U ] = vimREG->CHANCTRL[ 18U ]; + config_reg->CONFIG_CHANCTRL[ 19U ] = vimREG->CHANCTRL[ 19U ]; + config_reg->CONFIG_CHANCTRL[ 20U ] = vimREG->CHANCTRL[ 20U ]; + config_reg->CONFIG_CHANCTRL[ 21U ] = vimREG->CHANCTRL[ 21U ]; + config_reg->CONFIG_CHANCTRL[ 22U ] = vimREG->CHANCTRL[ 22U ]; + config_reg->CONFIG_CHANCTRL[ 23U ] = vimREG->CHANCTRL[ 23U ]; + config_reg->CONFIG_CHANCTRL[ 24U ] = vimREG->CHANCTRL[ 24U ]; + config_reg->CONFIG_CHANCTRL[ 25U ] = vimREG->CHANCTRL[ 25U ]; + config_reg->CONFIG_CHANCTRL[ 26U ] = vimREG->CHANCTRL[ 26U ]; + config_reg->CONFIG_CHANCTRL[ 27U ] = vimREG->CHANCTRL[ 27U ]; + config_reg->CONFIG_CHANCTRL[ 28U ] = vimREG->CHANCTRL[ 28U ]; + config_reg->CONFIG_CHANCTRL[ 29U ] = vimREG->CHANCTRL[ 29U ]; + config_reg->CONFIG_CHANCTRL[ 30U ] = vimREG->CHANCTRL[ 30U ]; + config_reg->CONFIG_CHANCTRL[ 31U ] = vimREG->CHANCTRL[ 31U ]; + } +} + +/* SourceId : VIM_SourceId_006 */ +/* DesignId : VIM_DesignId_006 */ +/* Requirements : HL_SR105 */ +void vimParityErrorHandler( void ) +{ + uint32 vec; + + /* Identify the corrupted address */ + uint32 error_addr = VIM_ADDERR; + + /* Identify the channel number */ + uint32 error_channel = ( ( error_addr & 0x1FFU ) >> 2U ); + + /* Correct the corrupted location */ + vimRAM->ISR[ error_channel ] = s_vim_init[ error_channel ]; + + /* Clear Parity Error Flag */ + VIM_PARFLG = 1U; + + /* Disable and enable the highest priority pending channel */ + if( vimREG->FIQINDEX != 0U ) + { + vec = vimREG->FIQINDEX - 1U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Read 32 bit volatile register" */ + vec = vimREG->IRQINDEX - 1U; + } + + if( vec == 0U ) + { + vimREG->INTREQ0 = 1U; + vec = esmREG->IOFFHR - 1U; + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( vec ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( vec - 32U ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( vec - 32U ); + } + else + { + esmREG->SR4[ 1U ] = ( uint32 ) 1U << ( vec - 96U ); + esmGroup2Notification( vec - 64U ); + } + } + else if( vec < 32U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << vec; + vimREG->REQMASKSET0 = ( uint32 ) 1U << vec; + } + else if( vec < 64U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( vec - 32U ); + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( vec - 32U ); + } + else if( vec < 96U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( vec - 64U ); + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( vec - 64U ); + } + else + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( vec - 96U ); + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( vec - 96U ); + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/system.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/system.c new file mode 100644 index 00000000000..d218f0afb17 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/source/system.c @@ -0,0 +1,687 @@ +/** @file system.c + * @brief System Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "system.h" +#include "sys_selftest.h" +#include "sys_pcr.h" +#include "pinmux.h" +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void systemInit(void) + * @brief Initializes System Driver + * + * This function initializes the System driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_001 */ +/* DesignId : SYSTEM_DesignId_001 */ +/* Requirements : HL_SR451 */ +void setupPLL( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* Disable PLL1 and PLL2 */ + systemREG1->CSDISSET = 0x00000002U | 0x00000040U; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x42U ) != 0x42U ) + { + /* Wait */ + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x301U; + + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /** - Setup pll control register 1: + * - Setup reset on oscillator slip + * - Setup bypass on pll slip + * - setup Pll output clock divider to max before Lock + * - Setup reset on oscillator fail + * - Setup reference clock divider + * - Setup Pll multiplier + */ + systemREG1->PLLCTL1 = ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) ( 6U - 1U ) << 16U ) + | ( uint32 ) ( 0xA400U ); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider + * - Setup spreading amount + */ + systemREG1->PLLCTL2 = ( uint32 ) ( ( uint32 ) 255U << 22U ) + | ( uint32 ) ( ( uint32 ) 7U << 12U ) + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 9U ) | ( uint32 ) 61U; + + /** @b Initialize @b Pll2: */ + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + systemREG2->PLLCTL3 = ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 29U ) + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) + | ( uint32 ) ( ( uint32 ) ( 6U - 1U ) << 16U ) + | ( uint32 ) ( 0xA400U ); + + /** - Enable PLL(s) to start up or Lock */ + systemREG1->CSDIS = 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U + | 0x00000000U | 0x00000000U | 0x00000000U; +} + +/** @fn void trimLPO(void) + * @brief Initialize LPO trim values + * + * Load TRIM values from OTP if present else call customTrimLPO() function + * + */ +/* SourceId : SYSTEM_SourceId_002 */ +/* DesignId : SYSTEM_DesignId_002 */ +/* Requirements : HL_SR468 */ +void trimLPO( void ) +{ + uint32 u32clocktestConfig; + + /* Save user clocktest register configuration */ + u32clocktestConfig = systemREG1->CLKTEST; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO + * clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify + * what the maximum step is so there is no metric to use for the SW implementation - + * the routine can temporarily disable the LPOCLKMON range check so the sudden change + * will not cause a fault.*/ + /* Disable clock range detection*/ + systemREG1->CLKTEST = ( systemREG1->CLKTEST | ( uint32 ) ( ( uint32 ) 0x1U << 24U ) ) + & ( uint32 ) ( ~( ( uint32 ) 0x1U << 25U ) ); + + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) LPO_TRIM_VALUE ); + } + else + { + customTrimLPO(); + } + + /* Restore the user clocktest register value configuration */ + systemREG1->CLKTEST = u32clocktestConfig; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_003 */ +/* DesignId : SYSTEM_DesignId_003 */ +/* Requirements : HL_SR457 */ +void setupFlash( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Setup flash read mode, address wait states and data wait states */ + flashWREG->FRDCNTL = 0x00000000U | ( uint32 ) ( ( uint32 ) 3U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | 1U; + + /** - Setup flash access wait states for bank 7 */ + FSM_WR_ENA_HL = 0x5U; + EEPROM_CONFIG_HL = 0x00000002U | ( uint32 ) ( ( uint32 ) 3U << 16U ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Disable write access to flash state machine registers */ + FSM_WR_ENA_HL = 0xAU; + + /** - Setup flash bank power modes */ + flashWREG->FBFALLBACK = 0x00000000U + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) /* BANK 7 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) /* BANK 1 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ); /* BANK 0 */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_004 */ +/* DesignId : SYSTEM_DesignId_004 */ +/* Requirements : HL_SR470 */ +void periphInit( void ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /** - Disable Peripherals before peripheral powerup*/ + systemREG1->CLKCNTL &= 0xFFFFFEFFU; + + /** - Release peripherals from reset and enable clocks to all peripherals */ + /** - Power-up all peripherals */ + pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + /** - Enable Peripherals */ + systemREG1->CLKCNTL |= 0x00000100U; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : HL_SR469 */ +void mapClocks( void ) +{ + uint32 SYS_CSVSTAT, SYS_CSDIS; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /** @b Initialize @b Clock @b Tree: */ + /** - Disable / Enable clock domain */ + systemREG1->CDDIS = ( uint32 ) ( ( uint32 ) 0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* AVCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* AVCLK4 , 1 - OFF, 0 - ON + */ + + /* Work Around for Errata SYS#46: + * + * Errata Description: + * Clock Source Switching Not Qualified with Clock Source Enable And Clock + * Source Valid Workaround: Always check the CSDIS register to make sure the clock + * source is turned on and check the CSVSTAT register to make sure the clock source is + * valid. Then write to GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + + while( ( SYS_CSVSTAT & ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + != ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + { + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + } /* Wait */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and + * after wakeup */ + systemREG1->GHVSRC = ( uint32 ) ( ( uint32 ) SYS_OSC << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_OSC << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + systemREG1->RCLKSRC = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + systemREG1->VCLKASRC = ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xF0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 24U ); + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xFFF0FFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ); + + systemREG2->CLK2CNTL = ( systemREG2->CLK2CNTL & 0xFFFFF0F0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 0U ); + + systemREG2->VCLKACON1 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed + * value */ + systemREG1->PLLCTL1 = ( systemREG1->PLLCTL1 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + systemREG2->PLLCTL3 = ( systemREG2->PLLCTL3 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + + /* Enable/Disable Frequency modulation */ + systemREG1->PLLCTL2 |= 0x00000000U; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_006 */ +/* DesignId : SYSTEM_DesignId_006 */ +/* Requirements : HL_SR471 */ +void systemInit( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /* Configure PLL control registers and enable PLLs. + * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock. + * This initialization sequence performs all the tasks that are not + * required to be done at full application speed while the PLL locks. + */ + setupPLL(); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* Enable clocks to peripherals and release peripheral reset */ + periphInit(); + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /* Configure device-level multiplexing and I/O multiplexing */ + muxInit(); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /** - Set up flash address and data wait states based on the target CPU clock + * frequency The number of address and data wait states for the target CPU clock + * frequency are specified in the specific part's datasheet. + */ + setupFlash(); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */ + trimLPO(); + + /* + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF + * clock below 40MHz. Hence the init function needs to be called from the startup + * before the PLL is configured. + */ + emif_SDRAM_StartupInit(); + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + /** - Wait for PLLs to start up and map clock domains to desired clock sources */ + mapClocks(); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + /** - set ECLK pins functional mode */ + systemREG1->SYSPC1 = 0U; + + /** - set ECLK pins default output value */ + systemREG1->SYSPC4 = 0U; + + /** - set ECLK pins output direction */ + systemREG1->SYSPC2 = 1U; + + /** - set ECLK pins open drain enable */ + systemREG1->SYSPC7 = 0U; + + /** - set ECLK pins pullup/pulldown enable */ + systemREG1->SYSPC8 = 0U; + + /** - set ECLK pins pullup/pulldown select */ + systemREG1->SYSPC9 = 1U; + + /** - Setup ECLK */ + systemREG1->ECPCNTL = ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_007 */ +/* DesignId : SYSTEM_DesignId_007 */ +/* Requirements : HL_SR493 */ +void systemPowerDown( uint32 mode ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Disable clock sources */ + systemREG1->CSDISSET = mode & 0x000000FFU; + + /* Disable clock domains */ + systemREG1->CDDIS = ( mode >> 8U ) & 0x00000FFFU; + + /* Idle CPU */ + _gotoCPUIdle_(); + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + +/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SYSTEM_SourceId_008 */ +/* DesignId : SYSTEM_DesignId_008 */ +/* Requirements : HL_SR506 */ +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE; + config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE; + config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE; + config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE; + config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE; + config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE; + config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE; + config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE; + config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE; + config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE; + config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE; + config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE; + config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE; + config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2; + config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE; + config_reg->CONFIG_UERFLAG = SYS_UERFLAG_CONFIGVALUE; + + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1; + } + else + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2; + } + + config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE; + config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE; + config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE; + config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE; + config_reg->CONFIG_MMUGCR = SYS_MMUGCR_CONFIGVALUE; + config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE; + config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE; + config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE; + + config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2; + config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE; + config_reg->CONFIG_CLK2CNTL = SYS2_CLK2CNTL_CONFIGVALUE; + config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE; + config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE; + config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1; + config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2; + config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7; + config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8; + config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9; + config_reg->CONFIG_CSDIS = systemREG1->CSDIS; + config_reg->CONFIG_CDDIS = systemREG1->CDDIS; + config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC; + config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC; + config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC; + config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR; + config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR; + config_reg->CONFIG_MSINENA = systemREG1->MSINENA; + config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1; + config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2; + config_reg->CONFIG_UERFLAG = systemREG1->SYSPC10; + config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL; + config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST; + config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1; + config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2; + config_reg->CONFIG_GPREG1 = systemREG1->GPREG1; + config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR; + config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1; + config_reg->CONFIG_MMUGCR = systemREG1->CPURSTCR; + config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL; + config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL; + config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1; + config_reg->CONFIG_SYSECR = systemREG1->SYSECR; + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3; + config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV; + config_reg->CONFIG_CLK2CNTL = systemREG2->CLK2CNTL; + config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1; + config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP; + config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN; + } +} + +/** @fn void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SYSTEM_SourceId_009 */ +/* DesignId : SYSTEM_DesignId_009 */ +/* Requirements : HL_SR506 */ +void tcmflashGetConfigValue( tcmflash_config_reg_t * config_reg, + config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_FRDCNTL = TCMFLASH_FRDCNTL_CONFIGVALUE; + config_reg->CONFIG_FEDACCTRL1 = TCMFLASH_FEDACCTRL1_CONFIGVALUE; + config_reg->CONFIG_FEDACCTRL2 = TCMFLASH_FEDACCTRL2_CONFIGVALUE; + config_reg->CONFIG_FEDACSDIS = TCMFLASH_FEDACSDIS_CONFIGVALUE; + config_reg->CONFIG_FBPROT = TCMFLASH_FBPROT_CONFIGVALUE; + config_reg->CONFIG_FBSE = TCMFLASH_FBSE_CONFIGVALUE; + config_reg->CONFIG_FBAC = TCMFLASH_FBAC_CONFIGVALUE; + config_reg->CONFIG_FBFALLBACK = TCMFLASH_FBFALLBACK_CONFIGVALUE; + config_reg->CONFIG_FPAC1 = TCMFLASH_FPAC1_CONFIGVALUE; + config_reg->CONFIG_FPAC2 = TCMFLASH_FPAC2_CONFIGVALUE; + config_reg->CONFIG_FMAC = TCMFLASH_FMAC_CONFIGVALUE; + config_reg->CONFIG_FLOCK = TCMFLASH_FLOCK_CONFIGVALUE; + config_reg->CONFIG_FDIAGCTRL = TCMFLASH_FDIAGCTRL_CONFIGVALUE; + config_reg->CONFIG_FEDACSDIS2 = TCMFLASH_FEDACSDIS2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_FRDCNTL = flashWREG->FRDCNTL; + config_reg->CONFIG_FEDACCTRL1 = flashWREG->FEDACCTRL1; + config_reg->CONFIG_FEDACCTRL2 = flashWREG->FEDACCTRL2; + config_reg->CONFIG_FEDACSDIS = flashWREG->FEDACSDIS; + config_reg->CONFIG_FBPROT = flashWREG->FBPROT; + config_reg->CONFIG_FBSE = flashWREG->FBSE; + config_reg->CONFIG_FBAC = flashWREG->FBAC; + config_reg->CONFIG_FBFALLBACK = flashWREG->FBFALLBACK; + config_reg->CONFIG_FPAC1 = flashWREG->FPAC1; + config_reg->CONFIG_FPAC2 = flashWREG->FPAC2; + config_reg->CONFIG_FMAC = flashWREG->FMAC; + config_reg->CONFIG_FLOCK = flashWREG->FLOCK; + config_reg->CONFIG_FDIAGCTRL = flashWREG->FDIAGCTRL; + config_reg->CONFIG_FEDACSDIS2 = flashWREG->FEDACSDIS2; + } +} + +/** @fn void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : SYSTEM_SourceId_010 */ +/* DesignId : SYSTEM_DesignId_010 */ +/* Requirements : HL_SR506 */ +void sramGetConfigValue( sram_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_RAMCTRL[ 0U ] = SRAM_RAMCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTHRESHOLD[ 0U ] = SRAM_RAMTHRESHOLD_CONFIGVALUE; + config_reg->CONFIG_RAMINTCTRL[ 0U ] = SRAM_RAMINTCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTEST[ 0U ] = SRAM_RAMTEST_CONFIGVALUE; + config_reg->CONFIG_RAMADDRDECVECT[ 0U ] = SRAM_RAMADDRDECVECT_CONFIGVALUE; + + config_reg->CONFIG_RAMCTRL[ 1U ] = SRAM_RAMCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTHRESHOLD[ 1U ] = SRAM_RAMTHRESHOLD_CONFIGVALUE; + config_reg->CONFIG_RAMINTCTRL[ 1U ] = SRAM_RAMINTCTRL_CONFIGVALUE; + config_reg->CONFIG_RAMTEST[ 1U ] = SRAM_RAMTEST_CONFIGVALUE; + config_reg->CONFIG_RAMADDRDECVECT[ 1U ] = SRAM_RAMADDRDECVECT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_RAMCTRL[ 0U ] = tcram1REG->RAMCTRL; + config_reg->CONFIG_RAMTHRESHOLD[ 0U ] = tcram1REG->RAMTHRESHOLD; + config_reg->CONFIG_RAMINTCTRL[ 0U ] = tcram1REG->RAMINTCTRL; + config_reg->CONFIG_RAMTEST[ 0U ] = tcram1REG->RAMTEST; + config_reg->CONFIG_RAMADDRDECVECT[ 0U ] = tcram1REG->RAMADDRDECVECT; + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_RAMCTRL[ 1U ] = tcram2REG->RAMCTRL; + config_reg->CONFIG_RAMTHRESHOLD[ 1U ] = tcram2REG->RAMTHRESHOLD; + config_reg->CONFIG_RAMINTCTRL[ 1U ] = tcram2REG->RAMINTCTRL; + config_reg->CONFIG_RAMTEST[ 1U ] = tcram2REG->RAMTEST; + config_reg->CONFIG_RAMADDRDECVECT[ 1U ] = tcram2REG->RAMADDRDECVECT; + } +} + +/** @fn customTrimLPO(void) + * @brief custom function to initilize LPO trim values + * + * This function initializes default LPO trim values if OTP value is 0XFFFF, + * user can also write their own code to handle this case . + * + */ +void customTrimLPO( void ) +{ + /* User can write logic to handle the case where LPO trim is set to 0xFFFFu */ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + /* Load default trimLPO value */ + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 16U ); + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/CMakeLists.txt b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/CMakeLists.txt new file mode 100644 index 00000000000..c35b86b7912 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/CMakeLists.txt @@ -0,0 +1,205 @@ +cmake_minimum_required(VERSION 3.25) + +SET(CMAKE_CROSSCOMPILING "TRUE" CACHE STRING "Set Cross Compiling to true" FORCE) + +# Strip the default MacOSX flags that cause cross-compilations to fail. +SET(CMAKE_OSX_DEPLOYMENT_TARGET "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) +SET(CMAKE_OSX_SYSROOT "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) + +# Set the compiler before declaring the project for the test build +SET(CMAKE_C_COMPILER "arm-none-eabi-gcc") +SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") + +# Set the system processor and name before declaring the project +# Needs to be set here otherwise it will fail the test compilation +SET(CMAKE_SYSTEM_NAME "Generic" CACHE STRING "Target system is a generic ARM Processor") +SET(CMAKE_SYSTEM_PROCESSOR "armv7-r" CACHE STRING "Target system is an ARM7r Processor") + +# Set the ASM and C compilation flags +SET(CMAKE_ASM_FLAGS "-mcpu=cortex-r4 -mfpu=vfpv3-d16 -Og -g -ggdb -Wall -MMD -MP") +SET(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -specs=\"nosys.specs\" -specs=\"nano.specs\"") +SET(CMAKE_C_FLAGS "${CMAKE_ASM_FLAGS} -marm -mfloat-abi=hard") + +project(RM46_FreeRTOS C ASM) + +SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR} CACHE STRING "") + +# Increase the debug level of the CMAKE build +SET(CMAKE_VERBOSE_MAKEFILE ON) + +# Get the absolute path to the Demo Directory +SET(DEMO_DIR_REL "${CMAKE_CURRENT_SOURCE_DIR}") +GET_FILENAME_COMPONENT(DEMO_DIR ${DEMO_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Board Files +SET(BOARD_FILES_DIR_REL "${DEMO_DIR}/BoardFiles") +GET_FILENAME_COMPONENT(BOARD_FILES_DIR ${BOARD_FILES_DIR_REL} ABSOLUTE) + +SET(FREERTOS_CONFIG_FILE_DIRECTORY "${DEMO_DIR}/include" CACHE STRING "Config File Path") +SET(FREERTOS_PORT "GCC_ARM_CRX_MPU" CACHE STRING "FreeRTOS Port to Use") + +ADD_LIBRARY(freertos_config INTERFACE) +TARGET_INCLUDE_DIRECTORIES(freertos_config SYSTEM + INTERFACE + INCLUDE ${FREERTOS_CONFIG_FILE_DIRECTORY} +) + +# Clone the tag of the FreeRTOS-Kernel last tested with this project. +INCLUDE(FetchContent) + +FetchContent_Declare( + FreeRTOS-Kernel + GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git + # Last tested FreeRTOS-Kernel Commit + GIT_TAG e8289dfee6e00660b5ad028e9f931ffb76c95840 + SOURCE_DIR "${DEMO_DIR}/../../Source" + USES_TERMINAL_DOWNLOAD YES + USES_TERMINAL_UPDATE YES + BUILD_COMMAND "" +) + +# Uncomment the following lines to use Fetch-Content to clone Kernel. +# FetchContent_GetProperties(FreeRTOS-Kernel) +# if(NOT FreeRTOS-Kernel_POPULATED) +# FetchContent_Populate(FreeRTOS-Kernel) +# endif() + +# Get the absolute path to the FreeRTOS-Kernel Directory +SET(FREERTOS_KERNEL_DIR_REL "${DEMO_DIR}/../../Source") +GET_FILENAME_COMPONENT(FREERTOS_KERNEL_DIR ${FREERTOS_KERNEL_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Port Directory +SET(PORT_DIR_REL "${FREERTOS_KERNEL_DIR}/portable/GCC/ARM_CRx_MPU") +GET_FILENAME_COMPONENT(PORT_DIR ${PORT_DIR_REL} ABSOLUTE) + +# Debug +MESSAGE("Project: ${PROJECT_NAME}") +MESSAGE("Demo Directory: ${DEMO_DIR}") +MESSAGE("FREERTOS_KERNEL_DIR: ${FREERTOS_KERNEL_DIR}") +MESSAGE("PORT_DIR: ${PORT_DIR}") + +INCLUDE_DIRECTORIES( + ${DEMO_DIR} + ${DEMO_DIR}/include + ${BOARD_FILES_DIR}/include + ${FREERTOS_KERNEL_DIR}/include + ${PORT_DIR} +) + +# Source files used for the FreeRTOS Demos +SET(FREERTOS_DEMO_SOURCES + ${DEMO_DIR}/source/main.c + ${DEMO_DIR}/source/irq_demo.c + ${DEMO_DIR}/source/mpu_demo.c + ${DEMO_DIR}/source/notification_demo.c + ${DEMO_DIR}/source/queue_demo.c + ${DEMO_DIR}/source/reg_test.c + ${DEMO_DIR}/source/reg_test_GCC.S +) + +# Source files used for the Board Support Package +ADD_LIBRARY(TI_BOARD_SUPPORT_PACKAGE OBJECT + ${BOARD_FILES_DIR}/source/adc.c + ${BOARD_FILES_DIR}/source/can.c + ${BOARD_FILES_DIR}/source/dabort.S + ${BOARD_FILES_DIR}/source/emac.c + ${BOARD_FILES_DIR}/source/emif.c + ${BOARD_FILES_DIR}/source/errata_SSWF021_45.c + ${BOARD_FILES_DIR}/source/esm.c + ${BOARD_FILES_DIR}/source/gio.c + ${BOARD_FILES_DIR}/source/het.c + ${BOARD_FILES_DIR}/source/lin.c + ${BOARD_FILES_DIR}/source/mdio.c + ${BOARD_FILES_DIR}/source/mibspi.c + ${BOARD_FILES_DIR}/source/notification.c + ${BOARD_FILES_DIR}/source/phy_dp83640.c + ${BOARD_FILES_DIR}/source/pinmux.c + ${BOARD_FILES_DIR}/source/sci.c + ${BOARD_FILES_DIR}/source/spi.c + ${BOARD_FILES_DIR}/source/sys_core.S + ${BOARD_FILES_DIR}/source/sys_dma.c + ${BOARD_FILES_DIR}/source/sys_intvecs.S + ${BOARD_FILES_DIR}/source/sys_link.ld + ${BOARD_FILES_DIR}/source/sys_main.c + ${BOARD_FILES_DIR}/source/sys_pcr.c + ${BOARD_FILES_DIR}/source/sys_phantom.c + ${BOARD_FILES_DIR}/source/sys_pmm.c + ${BOARD_FILES_DIR}/source/sys_pmu.S + ${BOARD_FILES_DIR}/source/sys_selftest.c + ${BOARD_FILES_DIR}/source/sys_startup.c + ${BOARD_FILES_DIR}/source/system.c + ${BOARD_FILES_DIR}/source/sys_vim.c +) + +# FreeRTOS Kernel Files +ADD_LIBRARY(FREERTOS_KERNEL OBJECT + ${FREERTOS_KERNEL_DIR}/croutine.c + ${FREERTOS_KERNEL_DIR}/event_groups.c + ${FREERTOS_KERNEL_DIR}/list.c + ${FREERTOS_KERNEL_DIR}/queue.c + ${FREERTOS_KERNEL_DIR}/stream_buffer.c + ${FREERTOS_KERNEL_DIR}/tasks.c + ${FREERTOS_KERNEL_DIR}/timers.c + ${FREERTOS_KERNEL_DIR}/portable/Common/mpu_wrappers_v2.c +) + +ADD_LIBRARY(FREERTOS_PORT OBJECT + ${PORT_DIR}/mpu_wrappers_v2_asm.S + ${PORT_DIR}/portASM.S + ${PORT_DIR}/port.c +) + +# On Mac the C_LINK flags by default adds "-Wl,-search_paths_first -Wl,-headerpad_max_install_names" which +# Causes the executable that gets built to strip the symbols, so force set it to empty here. +SET(CMAKE_C_LINK_FLAGS "") +SET(CMAKE_EXE_LINKER_FLAGS "-Wl,-Map,\"RTOSDemo.map\" -Wl,-T\"${BOARD_FILES_DIR}/source/sys_link.ld\"") + +# Debug +MESSAGE("Demo Sources: ${FREERTOS_DEMO_SOURCES}") +MESSAGE("FreeRTOS Sources: ${FREERTOS_KERNEL_SOURCES}") +MESSAGE("Port Sources: ${FREERTOS_PORT_SOURCES}") + +# Create Full Demo executable +ADD_EXECUTABLE(RM46_FreeRTOS_Full.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Register Demo executable +ADD_EXECUTABLE(RM46_FreeRTOS_Register_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Queue Demo executable +ADD_EXECUTABLE(RM46_FreeRTOS_Queue_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create MPU Demo executable +ADD_EXECUTABLE(RM46_FreeRTOS_MPU_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create IRQ Demo executable +ADD_EXECUTABLE(RM46_FreeRTOS_IRQ_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Notification Demo executable +ADD_EXECUTABLE(RM46_FreeRTOS_Notification_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# These options are explained in the demo_tasks.h file +SET_TARGET_PROPERTIES(RM46_FreeRTOS_Full.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x1F") +SET_TARGET_PROPERTIES(RM46_FreeRTOS_Register_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x1") +SET_TARGET_PROPERTIES(RM46_FreeRTOS_Queue_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x2") +SET_TARGET_PROPERTIES(RM46_FreeRTOS_MPU_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x4") +SET_TARGET_PROPERTIES(RM46_FreeRTOS_IRQ_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x8") +SET_TARGET_PROPERTIES(RM46_FreeRTOS_Notification_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x10") + +TARGET_LINK_LIBRARIES(RM46_FreeRTOS_Full.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM46_FreeRTOS_Register_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM46_FreeRTOS_Queue_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM46_FreeRTOS_MPU_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM46_FreeRTOS_IRQ_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM46_FreeRTOS_Notification_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/README.md b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/README.md new file mode 100644 index 00000000000..80f7224148d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/README.md @@ -0,0 +1,66 @@ +# Intro + +This directory contains a FreeRTOS project to build either a Blinky, or MPU demo +for the [RM46L852](https://www.ti.com/product/RM46L852). + +It is set up to blink LEDs on the Texas Instruments +[LAUNCHXL2-RM46](https://www.ti.com/tool/LAUNCHXL2-RM46) +and the [TMDXRM46HDK](https://www.ti.com/tool/TMDXRM46HDK) Development Kits. + +The code related to the Main Demo Files can be found in the +[source](./source) directory. +The code related to the board setup can be found in the +[BoardFiles](./BoardFiles) directory + +## Building + +This demo can either be loaded into Texas Instrument's +[Code Composer Studio (CCS)](https://www.ti.com/tool/CCSTUDIO). +or built using [CMake](https://cmake.org/). + +### CCS Build + +If building with CCS you need to install CCS, and then install the +[ARM Compiler Tools](https://software-dl.ti.com/ccs/esd/documents/ccs_compiler-installation-selection.html#compiler-installation) +as well as the Hercules Safety MCUs +[device support targets](https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_installation.html#device-support). + +After doing this, you can then open this directory in CCS, which will load up the +project. If everything installed correctly you should then be able to build and flash +to the board. + +Please be aware there is a filter on [CMakeLists.txt](./CMakeLists.txt) and the *build* +directory in the CCS project. + +This is to keep CCS from attempting to use resources generated with a CMAKE build. +If a directory other than "build" is selected when building using CMAKE, CCS will +attempt to use the the files in that directory, leading to build issues in CCS. +At time of writing this can be fixed by right clicking the folder in CCS +and selecting "Exclude from build". + +### CMake build + +When using CMake you will need to install a compatible version of the +[Arm GNU Toolchain](https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain) +and add this to your `PATH`. + +After doing this inspect the [demo_task.h](./include/demo_tasks.h#L30) file to see +what the possible demo configurations are, and select your desired demo config. + +The `all` options builds all combinations of these. +Example Usage: + +```sh +cmake -S . -B build; +make -C build all; +``` + +The generated binaries can then be found in the `build` directory. +These binaries can then be flashed to the board by using +[Uniflash](https://www.ti.com/tool/UNIFLASH) or by using CCS. + +## UART Output + +Rudimentary UART output is available by opening a Serial Connection +to the board. The settings for the UART are a BAUD rate of 115200, 1 stopbit, +and None Parity diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/include/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/include/FreeRTOSConfig.h new file mode 100644 index 00000000000..4d1fe2a161f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/include/FreeRTOSConfig.h @@ -0,0 +1,185 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Section of the file that can't be included in ASM Pre-processor */ +#ifndef FREERTOS_ASSEMBLY + #include + #ifndef configASSERT + +/* debug ASSERT The first option calls a function that prints to UART + * The second one loops for when using a debugger. */ +extern void vAssertCalled( const char * pcFileName, uint32_t ulLine ); + #define configASSERT( x ) \ + if( ( x ) == pdFALSE ) \ + { \ + vAssertCalled( __func__, __LINE__ ); \ + } + +extern void vMainSetupTimerInterrupt( void ); + #define configCLEAR_TICK_INTERRUPT() + #define configSETUP_TICK_INTERRUPT() vMainSetupTimerInterrupt() + #endif /* configASSERT */ +#endif /* FREERTOS_ASSEMBLY */ + +#ifndef FREERTOS_CONFIG_H + #define FREERTOS_CONFIG_H + + /*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + + /** Code Composer Studio will throw errors about NULL not being defined. + * as such wrap a define for NULL to 0 to remove the errors. + */ + #ifndef NULL + #define NULL 0x0 + #endif + + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1U + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0U + #define configENABLE_ACCESS_CONTROL_LIST 1U + + #define configENABLE_MPU 1U + #define configENABLE_FPU 1U + #define configUSE_MPU_WRAPPERS_V1 0U + #define configTOTAL_MPU_REGIONS 12UL + + #define configNUMBER_OF_CORES 1U + #define configUSE_PREEMPTION 1U + #define configUSE_IDLE_HOOK 1U + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + #define configUSE_TICK_HOOK 0 + #define configMAX_PRIORITIES ( 30UL ) + #define configQUEUE_REGISTRY_SIZE 10U + #define configSUPPORT_STATIC_ALLOCATION 1U + #define configSUPPORT_DYNAMIC_ALLOCATION 0U + + #define configCPU_CLOCK_HZ ( 110000000U ) + #define configTICK_RATE_HZ ( 1000U ) + #define configMINIMAL_STACK_SIZE ( 0x80 ) + #define configSYSTEM_CALL_STACK_SIZE configMINIMAL_STACK_SIZE + #define configTOTAL_HEAP_SIZE ( ( 80 * 512 ) ) + #define configMAX_TASK_NAME_LEN ( 0x20U ) + #define configUSE_TRACE_FACILITY 0U + #define configUSE_16_BIT_TICKS 0 + #define configIDLE_SHOULD_YIELD 0 + #define configUSE_CO_ROUTINES 0 + #define configUSE_MUTEXES 1U + #define configUSE_RECURSIVE_MUTEXES 1U + #define configUSE_EVENT_GROUPS 0U + #define configCHECK_FOR_STACK_OVERFLOW 0 + #define configUSE_QUEUE_SETS 1U + #define configUSE_COUNTING_SEMAPHORES 1U + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1U + #define configUSE_POSIX_ERRNO 0 + #define configUSE_TIME_SLICING 0 + #define configUSE_C_RUNTIME_TLS_SUPPORT 0 + #define configUSE_NEWLIB_REENTRANT 0 + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 + #define configUSE_MALLOC_FAILED_HOOK 0 + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + #define configAPPLICATION_ALLOCATED_HEAP 0 + #define configUSE_SB_COMPLETED_CALLBACK 0 + #define configRUN_MULTIPLE_PRIORITIES 0 + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING 0 + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + #define configUSE_MINI_LIST_ITEM 0 + #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 0x20UL + + /* Timer related defines. */ + #define configUSE_TIMERS 1 + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 6UL ) + #define configTIMER_QUEUE_LENGTH 20 + #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + #define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 + #define INCLUDE_xTimerPendFunctionCall 1 + + #define configUSE_TASK_NOTIFICATIONS 1 + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 3 + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. */ + + #define INCLUDE_vTaskPrioritySet 1 + #define INCLUDE_uxTaskPriorityGet 1 + #define INCLUDE_vTaskDelete 1 + #define INCLUDE_vTaskCleanUpResources 0 + #define INCLUDE_vTaskSuspend 1 + #define INCLUDE_xTaskDelayUntil 1 + #define INCLUDE_vTaskDelay 1 + #define INCLUDE_uxTaskGetStackHighWaterMark 1 + #define INCLUDE_xTaskGetSchedulerState 1 + #define INCLUDE_xTaskGetIdleTaskHandle 1 + #define INCLUDE_xSemaphoreGetMutexHolder 1 + #define INCLUDE_eTaskGetState 1 + #define INCLUDE_xTaskAbortDelay 1 + #define INCLUDE_xTaskGetHandle 1 + + /** Note: These value come from the Board Support Package. They are pulled directly + * from sys_vim.h, and reg_vim.h. These values correspond to hardware registers + * and keys exclusive to the board that this demo was written for. + */ + + /** @brief Address of MCU Register used to mark the end of an IRQ */ + #define configEOI_ADDRESS 0xFFFFFE70UL + + /** @brief Address of Real Time Interrupt (RTI) used for the system clock */ + #define configRTI_ADDRESS 0xFFFFFC88UL + + /** @brief Value used to clear a RTI Interrupt */ + #define configRTI_CLEAR_VALUE 0x1 + + /** @brief Address of Register used to trigger Software Interrupts (SWI) */ + #define configSWI_ADDRESS 0xFFFFFFB0UL + + /** @brief Key value that is written to the SWI Interrupt Register */ + #define configSWI_KEY_VAL 0x7500UL + + /** @brief Address of Register used to clear SWI Interrupts */ + #define configSWI_CLEAR_ADDRESS 0xFFFFFFF4UL + + /** @brief Value to write to clear a Software Interrupt (SWI) */ + #define configSWI_CLEAR_VAL 0x0 + + /** @brief Trigger a pending context swap from inside an ISR */ + #define portYIELD_FROM_ISR( x ) \ + if( x != pdFALSE ) \ + { \ + configPEND_YIELD_REG = configPEND_YIELD_KEY_VAL; \ + ( void ) configPEND_YIELD_REG; \ + } + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/include/demo_tasks.h b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/include/demo_tasks.h new file mode 100644 index 00000000000..ddc0a0b8eb2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/include/demo_tasks.h @@ -0,0 +1,206 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEMO_TASKS_H +#define DEMO_TASKS_H + +/* ----------------------------------- Demo Option ----------------------------------- */ + +/** @brief Create Tasks that are written in assembly to test context swaps */ +#define REGISTER_DEMO 0x1 + +/** @brief Demo that uses timers, timer callbacks, and Queues */ +#define QUEUE_DEMO 0x2 + +/** @brief Demo that causes data aborts and clears them to show MPU usage */ +#define MPU_DEMO 0x4 + +/** @brief Demo that causes and unwinds a Nested IRQ */ +#define IRQ_DEMO 0x8 + +/** @brief Demo that uses the Task Notification APIs */ +#define NOTIFICATION_DEMO 0x10 + +/** @brief Build Register, Queue, MPU, IRQ, and Notification demos */ +#define FULL_DEMO ( REGISTER_DEMO | QUEUE_DEMO | MPU_DEMO | IRQ_DEMO | NOTIFICATION_DEMO ) + +/** @brief Bitfield used to select the Demo Tasks to build and run + * + * @note This project contains multiple demo and test tasks. A bitfield is used + * to select which demos and tests are built and run as part of the executable. + * More information about what these demos and tests do can be found in their + * corresponding files. + * + * Bit 1 Set: Include the Register Test Tasks + * + * Bit 2 Set: Include the Queue Send and Receive Test Tasks + * + * Bit 3 Set: Include the MPU Data Abort Test Tasks + * + * Bit 4 Set: Include the Nested IRQ Test Tasks + * + * Bit 5 Set: Include the Notification Test Tasks + * + */ +#ifndef mainDEMO_TYPE + #define mainDEMO_TYPE ( FULL_DEMO ) +#endif /* mainDEMO_TYPE */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "portmacro.h" +#include "mpu_wrappers.h" + +/* These tasks have been given pseudo random priority values for testing. + * Except for the queue send and receive task any of these tasks priorities + * should be able to be set to any valid priority without issue. */ + +/** @brief Priority at which the Privileged Register Task is created. */ +#define demoREG_PRIVILEGED_TASK_PRIORITY ( configMAX_PRIORITIES - 2UL ) + +/** @brief Priority at which the Unprivileged Register Task is created. */ +#define demoREG_UNPRIVILEGED_TASK_PRIORITY ( configMAX_PRIORITIES - 1UL ) + +/** @brief Priority at which the prvQueueSendTask is created. */ +#define demoQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL ) + +/** @brief Priority at which the prvQueueReceiveTask is created. */ +#define demoQUEUE_RECEIVE_TASK_PRIORITY ( demoQUEUE_SEND_TASK_PRIORITY + 1UL ) + +/** @brief Priority at which the MPU Read & Write Task is created. */ +#define demoMPU_READ_WRITE_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) + +/** @brief Priority at which the MPU Read Only Task is created. */ +#define demoMPU_READ_ONLY_TASK_PRIORITY ( tskIDLE_PRIORITY + 4UL ) + +/** @brief Priority at which the Nested IRQ Test Task is created. */ +#define demoIRQ_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 2UL ) + +/** @brief Priority at which the Notification Demo Task is created. */ +#define demoNOTIFICATION_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 1UL ) + +/* ------------------------------- Register Test Tasks ------------------------------- */ + +/* @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest1Implementation( void ); + +/** @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest2Implementation( void ); + +/** @brief Creates the Register Test Tasks implemented in reg_test_GCC.S + * @return pdPASS if all tasks are created, pdFAIL if they are not. + */ +BaseType_t xCreateRegisterTestTasks( void ); + +/* ----------------------------- Demo Tasks Declarations ----------------------------- */ + +/** + * @brief Create two tasks, a queue, and a timer, which are used to blink an LED. + * + * @return + * pdPASS if all objects are created. + * pdFAIL if any object cannot be created. + */ +BaseType_t xCreateQueueTasks( void ); + +/** + * @brief Create the MPU Tasks that trigger data aborts. + * + * @note The MPU demo creates 2 unprivileged tasks - One of which has Read Only + * access to a shared memory region while the other has Read Write access. The + * task with Read Only access then tries to write to the shared memory which + * results in a Memory fault. The fault handler examines that it is the fault + * generated by the task with Read Only access and if so, it recovers from the + * fault gracefully by moving the Program Counter to the next instruction to the + * one which generated the fault. If any other memory access violation occurs, + * the fault handler will get stuck in an infinite loop. + */ +BaseType_t xCreateMPUTasks( void ); + +/** @brief Create a task that waits for a response from a nested IRQ + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateIRQTestTask( void ); + +/** + * @brief Create tasks that send task notifications back and forth. + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateNotificationTestTask( void ); + +/** @brief Interrupt Handler used for Software Raised Interrupts */ +PRIVILEGED_FUNCTION void vIRQDemoHandler( void ); + +/* Registers required to configure the Real Time Interrupt (RTI). */ +#define portRTI_GCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC00UL ) ) +#define portRTI_TBCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC04UL ) ) +#define portRTI_COMPCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC0CUL ) ) +#define portRTI_CNT0_FRC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC10UL ) ) +#define portRTI_CNT0_UC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC14UL ) ) +#define portRTI_CNT0_CPUC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC18UL ) ) +#define portRTI_CNT0_COMP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC50UL ) ) +#define portRTI_CNT0_UDCP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC54UL ) ) +#define portRTI_SETINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC80UL ) ) +#define portRTI_CLEARINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC84UL ) ) +#define portRTI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFC88UL ) ) +#define portEND_OF_INTERRUPT_REG ( ( ( volatile uint32_t * ) configEOI_ADDRESS ) ) + +/* Registers used by the Vectored Interrupt Manager */ +typedef void ( *ISRFunction_t )( void ); +#define portVIM_IRQ_INDEX ( *( ( volatile uint32_t * ) 0xFFFFFE00 ) ) +#define portVIM_IRQ_VEC_REG ( *( ( volatile ISRFunction_t * ) 0xFFFFFE70 ) ) + +#define portSSI_INT_REG_BASE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) + +#define portSSI_INT_REG_ONE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) +#define portSSI_ONE_KEY 0x7500UL + +#define portSSI_INT_REG_TWO ( ( ( volatile uint32_t * ) 0xFFFFFFB4 ) ) +#define portSSI_TWO_KEY 0x8400UL + +#define portSSI_INT_REG_THREE ( ( ( volatile uint32_t * ) 0xFFFFFFB8 ) ) +#define portSSI_THREE_KEY 0x9300UL + +#define portSSI_INT_REG_FOUR ( ( ( volatile uint32_t * ) 0xFFFFFFBC ) ) +#define portSSI_FOUR_KEY 0xA200UL + +#define portSSI_VEC_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF4 ) ) +#define portSSI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF8 ) ) + +/* --------------------------- Shared Function Deceleration --------------------------- */ + +/** @brief Function to toggle LEDs on the Hercules Launchpad + * @param ulLED Which LED to flicker + */ +void vToggleLED( uint32_t ulLED ); + +/* ----------------------------------------------------------------------------------- */ + +#endif /* DEMO_TASKS_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/irq_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/irq_demo.c new file mode 100644 index 00000000000..9ca0e0f51fe --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/irq_demo.c @@ -0,0 +1,292 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if( mainDEMO_TYPE & IRQ_DEMO ) + +/** @brief TCB used by the IRQ Test Task */ +PRIVILEGED_DATA static StaticTask_t xIRQTestTaskTCB; + +/** @brief MPU Region Aligned Stack used by the IRQ Test Task */ + +PRIVILEGED_DATA static StackType_t uxIRQTestTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4UL ) ) ); + + /** @brief Parameters that are passed into the IRQ test task solely for + * the purpose of ensuring parameters are passed into tasks correctly. */ + #define irqTASK_PARAMETER ( 0xFEEDBEEFUL ) + +/** @brief Statically allocated task handle for the IRQ Test task. */ +PRIVILEGED_DATA static TaskHandle_t xIRQTaskHandle; + +PRIVILEGED_DATA volatile static uint32_t ulIntNestTestVal; +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Unprivileged IRQ Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task raises Software Interrupts (SWI) in the form of IRQs using the + * Vectored Interrupt Manager (VIM) built into the RM46 by Texas Instrument (TI). + * It does this through use of the Software Interrupt Registers (SSIRs). + * More information about these can be found in the following documents: + * SWI Info Section 6.15: https://www.ti.com/lit/ds/symlink/rm46l852.pdf?ts=1704878833799 + * VIM Info: https://www.ti.com/lit/pdf/spna218 + */ +static void prvIRQTestTask( void * pvParameters ) +{ + /* Ensure that the correct parameter was passed to the task */ + configASSERT( ( uint32_t ) pvParameters == irqTASK_PARAMETER ); + volatile uint32_t * xSoftwareInterruptRegister; + volatile TickType_t ulLoopCount; + volatile TickType_t xPreIRQTickCount; + for( ;; ) + { + /* Disable IRQs to raise a Software Based IRQ */ + // portDISABLE_INTERRUPTS(); + sci_print( "IRQ Test Task Starting IRQ Nesting Test!\r\n" ); + ulIntNestTestVal = 0xFFFFUL; + + /* Get the tick count before raising the SWI */ + xPreIRQTickCount = xTaskGetTickCount(); + + /* Trigger an IRQ by writing to the SSI Register with a data value */ + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + *xSoftwareInterruptRegister = portSSI_FOUR_KEY | 0x44UL; + + /* When using a debugger IRQs can be paused/delayed. + * This loop exists to keep the compiler from optimizing it out + * while also giving the debugger time to trigger the IRQ. */ + ulLoopCount = xPreIRQTickCount; + while( ( ulLoopCount + xPreIRQTickCount ) < ( xPreIRQTickCount + 0x20UL ) ) + { + if( 0xFFFFUL != ulIntNestTestVal ) + { + ulLoopCount++; + } + else + { + ulLoopCount = 0xFFFF0000UL; + } + } + + if( 0x4UL == ulIntNestTestVal ) + { + sci_print( "IRQ Test Task reported correct unwinding!\r\n" ); + vToggleLED( 0x1 ); + } + else + { + sci_print( "IRQ Test Task did not receive the correct nesting value!\r\n" ); + configASSERT( 0x0 ); + } + + sci_print( "IRQ Test Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 3150UL ) ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +void vIRQDemoHandler( void ) /* PRIVILEGED_FUNCTION */ +{ + sci_print( "\tSWI Based IRQ was raised!\r\n" ); + volatile uint32_t ulSSIRegisterValue; + volatile uint32_t ulSSIIntFlagValue; + volatile uint32_t * xSoftwareInterruptRegister; + /* The 4 different SWI Registers use a bitfield to mark that they where raised */ + { + /* Determine what channel raised the IRQ without clearing the interrupt */ + ulSSIIntFlagValue = portSSI_INTFLAG_REG; + if( 0x1UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x11UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #1 Raised with Data Value 0x11, clearing the " + "IRQs...\r\n" ); + /* Read to mark this IRQ as cleared */ + /* Mark the Nested Channel 1 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x1101UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 2 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x2202UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 3 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x3303UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 4 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x4404UL == ulSSIIntFlagValue ); + + /* Should be no other IRQs raised, mask out the data */ + ulSSIIntFlagValue = ( portSSI_VEC_REG ) & 0XFFUL; + configASSERT( 0x0UL == ulSSIIntFlagValue ); + } + } + + else if( 0x2UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x22UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #2 triggering nested Channel #1 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + *xSoftwareInterruptRegister = portSSI_ONE_KEY | 0x11UL; + __asm volatile( "CPSIE I" ); + } + } + + else if( 0x4UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x33UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #3 triggering nested Channel #2 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + *xSoftwareInterruptRegister = portSSI_TWO_KEY | 0x22UL; + __asm volatile( "CPSIE I" ); + } + } + + else /* if( 0x8UL & ulSSIIntFlagValue ) */ + { + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x44UL ) + { + ulIntNestTestVal = 0x1UL; + sci_print( "\t\tSWI Channel #4 triggering nested Channel #3 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + *xSoftwareInterruptRegister = portSSI_THREE_KEY | 0x33UL; + __asm volatile( "CPSIE I" ); + } + } + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateIRQTestTask( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + uint32_t ulSRAMBaseAddress = ( uint32_t ) __SRAM_segment_start__; + uint32_t ulSRAMRegionSize = ( uint32_t ) __SRAM_segment_end__ - ulSRAMBaseAddress; + uint32_t ulSRAMRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + BaseType_t xReturn = pdFAIL; + /* Create the register check tasks, as described at the top of this file. */ + TaskParameters_t xIRQTestTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvIRQTestTask, + /* The name of the task. */ + .pcName = "IRQTestTask", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE, + /* Parameter passed into the task. */ + .pvParameters = ( void * ) irqTASK_PARAMETER, + /* Priority of the task. */ + .uxPriority = ( configTIMER_TASK_PRIORITY + 0x2UL ) | portPRIVILEGE_BIT, + .puxStackBuffer = uxIRQTestTaskStack, + .pxTaskBuffer = &xIRQTestTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { ( void * ) ulSRAMBaseAddress, ulSRAMRegionSize, ulSRAMRegionAttr }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, + #endif + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, ulPeriphRegionSize, ulPeriphRegionAttr }, + } + }; + + /* Create the first register test task as a privileged task */ + xReturn = xTaskCreateRestrictedStatic( &( xIRQTestTaskParameters ), + &( xIRQTaskHandle ) ); + if( pdPASS == xReturn ) + { + sci_print( "Created the IRQ Test Task\r\n" ); + } + else + { + sci_print( "Failed to create the IRQ Test Task\r\n" ); + } + + ulIntNestTestVal = 0xFEEDBEEFUL; + return xReturn; +} +#endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/main.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/main.c new file mode 100644 index 00000000000..005500421ea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/main.c @@ -0,0 +1,480 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* ------------------------------------------------------------------------- */ +/** + * @file main.c + * @brief File implementing RM46L852 specific functions + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "portmacro.h" +#include "task.h" +#include "timers.h" + +/* Standard includes. */ +#include +#include + +/* HalCoGen includes. */ +#include "system.h" +#include "gio.h" +#include "het.h" +#include "reg_vim.h" +#include "sci.h" +#include "sys_vim.h" +#include "system.h" + +/* Demo Tasks include */ +#include "demo_tasks.h" + +/* ----------------------- Microcontroller Registers ----------------------- */ + +/** @brief Configure the hardware to start the scheduler timer. */ +PRIVILEGED_FUNCTION void vMainSetupTimerInterrupt( void ); + +/** @brief Set up necessary hardware registers */ +PRIVILEGED_FUNCTION static void prvSetupHardware( void ); + +/** @brief Landing point function for any failed configASSERT() check. + * @param pcFuncName The function that raised the assert. + * @param ulLine The line that the assert was called from. + * @note Unprivileged tasks shall pre-fetch abort if their assert fails. */ +FREERTOS_SYSTEM_CALL void vAssertCalled( const char * pcFileName, uint32_t ulLine ); + +PRIVILEGED_FUNCTION void vApplicationIRQHandler( void ); +/* --------------------- Static Task Memory Allocation --------------------- */ + +/** @brief Statically declared TCB Used by the Idle Task */ +PRIVILEGED_DATA static StaticTask_t xTimerTaskTCB; + +/** @brief Statically declared MPU aligned stack used by the timer task */ +PRIVILEGED_DATA static StackType_t uxTimerTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Statically declared TCB Used by the Idle Task */ +PRIVILEGED_DATA static StaticTask_t xIdleTaskTCB; + +/** @brief Statically declared MPU aligned stack used by the idle task */ +PRIVILEGED_DATA static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Simple variable to show how the idle tick hook can be used */ +PRIVILEGED_DATA static volatile TickType_t ulIdleTickHookCount = 0x0; + +extern PRIVILEGED_DATA volatile uint32_t ulPortYieldRequired; + +/* ------------------------------------------------------------------------- */ + +int main( void ) +{ + UBaseType_t xReturn = pdPASS; + ulIdleTickHookCount = 0x0; + prvSetupHardware(); + + sci_print( "\r\n---------------------------- Create FreeRTOS Tasks" + "----------------------------\r\n\r\n" ); + +#if( mainDEMO_TYPE & REGISTER_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Register test tasks\r\n" ); + xReturn = xCreateRegisterTestTasks(); + } + } +#endif /* ( mainDEMO_TYPE & REGISTER_DEMO ) */ + +#if( mainDEMO_TYPE & QUEUE_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Queue Demo Tasks\r\n" ); + xReturn = xCreateQueueTasks(); + } + } +#endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ + +#if( mainDEMO_TYPE & MPU_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the MPU Demo Tasks\r\n" ); + xReturn = xCreateMPUTasks(); + } + } +#endif + +#if( mainDEMO_TYPE & IRQ_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the IRQ Demo Tasks\r\n" ); + xReturn = xCreateIRQTestTask(); + } + } +#endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ + +#if( mainDEMO_TYPE & NOTIFICATION_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Notification Demo Tasks\r\n" ); + xReturn = xCreateNotificationTestTask(); + } + } +#endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ + + if( pdPASS == xReturn ) + { + sci_print( "\r\n--------------------------- Start of FreeRTOS Demos" + "---------------------------\r\n\r\n" ); + vTaskStartScheduler(); + } + else + { + sci_print( "Failed to create the Demo Tasks\r\n" ); + configASSERT( pdFAIL ); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was an error when creating the necessary FreeRTOS objects. */ + configASSERT( 0x0 ); + return 0; +} +/*---------------------------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + systemInit(); + gioInit(); + hetInit(); + sciInit(); + + /* Setup gioPORTB for when using the RM46 Launchpad */ + gioPORTB->DIR |= ( 0x01 << 1 ); /*configure GIOB[1] as output */ + gioPORTB->DIR |= ( 0x01 << 2 ); /*configure GIOB[3] as output */ + + /* Configure HET as master, pull functionality, and switch on. */ + hetREG1->GCR = 0x01000001; + hetREG1->PULDIS = 0x00000000; + + /* Configure pins connected to LEDs NHET[0,2,4,5,25,16,17,18,20,27,29,31] + * as output. */ + hetREG1->DIR = 0xAA178035; + hetREG1->DOUT = 0x0; + + /* Enable notifications for the SCI register */ + /* Use a BAUD rate of 115200, 1 stop bit, and None Parity */ + sciEnableNotification( scilinREG, SCI_RX_INT ); +} + +/*---------------------------------------------------------------------------*/ + +void vToggleLED( uint32_t ulLEDNum ) +{ + uint32_t ulLEDVal; + uint32_t ulGIOVal; + + if( 0x0 == ulLEDNum ) + { + /* RM46 TMDX Dev Kit LED1 use NHET[0], Launchpad LED2 uses GIOB[1] */ + ulLEDVal = 1UL << 0UL; + ulGIOVal = 1UL << 1UL; + } + else + { + /* RM46 TMDX Dev Kit LED2 use NHET[5], Launchpad LED3 uses GIOB[2] */ + ulLEDVal = 1UL << 5UL; + ulGIOVal = 1UL << 2UL; + } + + if( ( hetREG1->DOUT & ulLEDVal ) == 0 ) + { + hetREG1->DOUT |= ulLEDVal; + gioPORTB->DOUT |= ulGIOVal; + } + else + { + hetREG1->DOUT &= ~ulLEDVal; + gioPORTB->DOUT &= ~ulGIOVal; + } +} + +/*---------------------------------------------------------------------------*/ + +void vMainSetupTimerInterrupt( void ) +{ + /* Disable timer 0. */ + portRTI_GCTRL_REG &= 0xFFFFFFFEUL; + + /* Use the internal counter. */ + portRTI_TBCTRL_REG = 0x00000000U; + + /* COMPSEL0 will use the RTIFRC0 counter. */ + portRTI_COMPCTRL_REG = 0x00000000U; + + /* Initialise the counter and the prescale counter registers. */ + portRTI_CNT0_UC0_REG = 0x00000000U; + portRTI_CNT0_FRC0_REG = 0x00000000U; + + /* Set Prescalar for RTI clock. */ + portRTI_CNT0_CPUC0_REG = 0x00000001U; + portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + + /* Clear interrupts. */ + portRTI_INTFLAG_REG = 0x0007000FU; + portRTI_CLEARINTENA_REG = 0x00070F0FU; + + /* Enable the compare 0 interrupt. */ + portRTI_SETINTENA_REG = 0x00000001U; + portRTI_GCTRL_REG |= 0x00000001U; +} + +/*---------------------------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the + * idle task. It is essential that code added to this hook function never + * attempts to block in any way (for example, call xQueueReceive() with a + * block time specified, or call vTaskDelay()). If application tasks make + * use of the vTaskDelete() API function to delete themselves then it is + * also important that vApplicationIdleHook() is permitted to return to its + * calling function, because it is the responsibility of the idle task to + * clean up memory allocated by the kernel to any task that has since + * deleted itself. */ + ulIdleTickHookCount++; + if( ( TickType_t ) 0xF00000 == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xF0 0000 times!\r\n" ); + } + + else if( ( TickType_t ) 0xFFFFFFFF == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xFFFFFFFF times! " + "Setting it to 0x0!\r\n" ); + ulIdleTickHookCount = 0x0; + } +} + +/*---------------------------------------------------------------------------*/ + +void vAssertCalled( const char * pcFuncName, uint32_t ulLine ) /* FREERTOS_SYSTEM_CALL */ +{ + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + volatile const char * callingFunc = pcFuncName; + volatile uint32_t callingLine = ulLine; + + /* These variables can be inspected in a debugger. */ + if( callingFunc != ( char * ) callingLine ) + { + __asm volatile( "NOP" ); + } + + /* NOTE: Unprivileged tasks cannot enter critical sections on the ARM_CRx_MPU port. + * Meaning unprivileged tasks will cause a pre-fetch abort if they fail an assert. */ + taskENTER_CRITICAL(); + { + if( callingFunc != ( char * ) callingLine ) + { + __asm volatile( "NOP" ); + } + + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + } + } + taskEXIT_CRITICAL(); +} + +/*---------------------------------------------------------------------------*/ + +/** @brief Default IRQ Handler used in the ARM_Cortex_RX ports. + * @note This Handler is directly tied to the Texas Instrument's Hercules + * Vectored Interrupt Manager (VIM). For more information about what + * this is and how it operates please refer to their document: + * https://www.ti.com/lit/pdf/spna218 + */ +void vApplicationIRQHandler( void ) +{ + /* Load the IRQ Channel Number and Function PTR from the VIM */ + volatile uint32_t ulIRQChannelIndex = portVIM_IRQ_INDEX; + volatile ISRFunction_t xIRQFncPtr = portVIM_IRQ_VEC_REG; + + /* Setup Bit Mask Clear Values */ + volatile uint32_t ulPendingIRQMask; + + volatile uint32_t ulPendISRReg0 = vimREG->REQMASKCLR0; + volatile uint32_t ulPendISRReg1 = vimREG->REQMASKCLR1; + volatile uint32_t ulPendISRReg2 = vimREG->REQMASKCLR2; + volatile uint32_t ulPendISRReg3 = vimREG->REQMASKCLR3; + + if( NULL == xIRQFncPtr ) + { + sci_print( "Received a NULL Function Pointer from the IRQ VIM\r\n" ); + configASSERT( pdFALSE ); + } + else + { + if( 0U != ulIRQChannelIndex ) + { + ulIRQChannelIndex--; + } + + if( ulIRQChannelIndex <= 31U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ulIRQChannelIndex; + vimREG->REQMASKCLR0 = ulPendingIRQMask; + vimREG->REQMASKCLR1 = 0xFFFFFFFFU; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 63U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 32U ); + vimREG->REQMASKCLR1 = ulPendingIRQMask; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 95U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 64U ); + vimREG->REQMASKCLR2 = ulPendingIRQMask; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 96U ); + vimREG->REQMASKCLR3 = ulPendingIRQMask; + } + } + /* + * Channel 0 is the ESM handler, treat this as a special case. + * phantomInterrupt() + * Keep interrupts disabled, this function does not return + */ + + if( 0UL == ulIRQChannelIndex ) + { + sci_print( "Phantom interrupt?\r\n" ); + configASSERT( pdFALSE ); + ( *xIRQFncPtr )(); + } + else if( ( phantomInterrupt == xIRQFncPtr ) ) + { + sci_print( "IRQ With no registered function in sys_vim.c has been raised\r\n" ); + configASSERT( pdFALSE ); + } + else + { + /* Information about the mapping of Interrupts in the VIM to their + * causes can be found in the RM48L852 Data Sheet: + * https://www.ti.com/lit/ds/symlink/rm46l852.pdf?ts=1704878833799 */ + /* An IRQ Raised by Channel Two of the VIM is RTI Compare Interrupt 0. */ + if( 2UL == ulIRQChannelIndex ) + { + /* This is the System Tick Timer Interrupt */ + ulPortYieldRequired = xTaskIncrementTick(); + /* Acknowledge the System Tick Timer Interrupt */ + portRTI_INTFLAG_REG = 0x1UL; + } + /* An IRQ Raised by Channel 21 of the VIM is a Software Interrupt (SSI). */ + else if( 21UL == ulIRQChannelIndex ) + { +#if( mainDEMO_TYPE & IRQ_DEMO ) + /* This is an interrupt raised by Software */ + vIRQDemoHandler(); +#else + sci_print( "SWI of unknown cause was raised!\r\n" ); + configASSERT( 0x0 ); +#endif + + /* Register read is needed to mark the end of the IRQ */ + volatile uint32_t ulEndOfIntRegVal = *portEND_OF_INTERRUPT_REG; + *portEND_OF_INTERRUPT_REG = ulEndOfIntRegVal; + } + else + { + sci_print( "Unmapped IRQ Channel Number Raised\r\n" ); + } + } + + vimREG->REQMASKSET0 = ulPendISRReg0; + vimREG->REQMASKSET1 = ulPendISRReg1; + vimREG->REQMASKSET2 = ulPendISRReg2; + vimREG->REQMASKSET3 = ulPendISRReg3; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/mpu_demo.c new file mode 100644 index 00000000000..bf70680322d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/mpu_demo.c @@ -0,0 +1,508 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "mpu_wrappers.h" + +/* Board Includes */ +#include "sci.h" + +/* Demo includes */ +#include "demo_tasks.h" + +/** @brief Size of the smallest valid MPU region, 32 bytes. */ +#define SHARED_MEMORY_SIZE 0x20UL + +#if( ( ( SHARED_MEMORY_SIZE % 2UL ) != 0UL ) || ( SHARED_MEMORY_SIZE < 32UL ) ) + #error SHARED_MEMORY_SIZE Must be a power of 2 that is larger than 32 +#endif /* ( ( SHARED_MEMORY_SIZE % 2UL ) != 0UL ) || ( SHARED_MEMORY_SIZE < 32UL ) */ +/** + * @brief Memory region used to track Memory Fault intentionally caused by the + * RO Access task. + * + * @note RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal + * memory. Illegal memory access causes Memory Fault and the fault handler + * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We + * recover gracefully from an expected fault by jumping to the next instruction. + * + */ +static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 }; + +#if( mainDEMO_TYPE & MPU_DEMO ) + +/* --------------------- Static Task Memory Allocation --------------------- */ + +/** @brief static variable that will be placed in privileged data */ +static volatile uint32_t ulStaticUnprotectedData = 0xFEED; + +/** @brief Memory regions shared between the two MPU Tasks. */ +static volatile uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory1[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory2[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory3[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory4[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + + #if( configTOTAL_MPU_REGIONS == 16 ) +static volatile uint8_t ucSharedMemory5[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory6[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory7[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory8[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + #endif /* configTOTAL_MPU_REGIONS == 16 */ + +/* These tasks will use over 288 bytes as of time of writing. + * Minimal Cortex R MPU region sizes are 32, 64, 128, 256, and 512 bytes. Regions must + * aligned to their size. Due to this limitation these regions declare 512, or 0x200, + * bytes and align to that size. */ + +/** @brief Statically declared MPU aligned stack used by the Read Only task */ +static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Statically declared TCB Used by the Idle Task */ +PRIVILEGED_DATA static StaticTask_t xROAccessTaskTCB; + +/** @brief Statically declared MPU aligned stack used by the Read Write task */ +static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Statically declared TCB Used by the Read Write Task */ +PRIVILEGED_DATA static StaticTask_t xRWAccessTaskTCB; + +/* ----------------------- Task Function Declaration ----------------------- */ + +/** @brief Task function used by the task with RO access to shared memory + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvROAccessTask( void * pvParameters ); + +/** @brief Task function used by the task with RW access to shared memory + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvRWAccessTask( void * pvParameters ); + +/* --------------------- MPU Demo Function Definitions --------------------- */ + +static void prvROAccessTask( void * pvParameters ) +{ + volatile uint8_t ucVal = 0x0; + + /* Unused parameters. */ + ( void ) pvParameters; + + for( ;; ) + { + /* This task performs the following sequence for all the shared memory + * regions: + * + * 1. Perform a read access to the shared memory. Since this task has + * RO access to the shared memory, the read operation is successful. + * + * 2. Set ucROTaskFaultTracker[ 0 ] to 1 before performing a write to + * the shared memory. Since this task has Read Only access to the + * shared memory, the write operation would result in a Memory Fault. + * Setting ucROTaskFaultTracker[ 0 ] to 1 tells the Memory Fault + * Handler that this is an expected fault. The handler recovers from + * the expected fault gracefully by jumping to the next instruction. + * + * 3. Perform a write to the shared memory resulting in a memory fault. + * + * 4. Ensure that the write access did generate MemFault and the fault + * handler did clear the ucROTaskFaultTracker[ 0 ]. + */ + /* Perform the above mentioned sequence on ucSharedMemory. */ + ucVal = ucSharedMemory[ 0 ]; + ucVal = 1U; + ucROTaskFaultTracker[ 0 ] = ucVal; + ucSharedMemory[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory1. */ + ucVal = ucSharedMemory1[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory1[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory2. */ + ucVal = ucSharedMemory2[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory2[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory3. */ + ucVal = ucSharedMemory3[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory3[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory4. */ + ucVal = ucSharedMemory4[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory4[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + #if( configTOTAL_MPU_REGIONS == 16 ) + { + /* Perform the above mentioned sequence on ucSharedMemory5. */ + ucVal = ucSharedMemory5[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory5[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory6. */ + ucVal = ucSharedMemory6[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory6[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory7. */ + ucVal = ucSharedMemory7[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory7[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory8. */ + ucVal = ucSharedMemory8[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory8[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + } + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + vToggleLED( 0x0 ); + sci_print( "Read Only MPU Task sleeping before next loop!\r\n\r\n" ); + + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 4004UL ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRWAccessTask( void * pvParameters ) +{ + volatile uint32_t ulVal = ( uint32_t ) pvParameters; + + for( ;; ) + { + /* This task has RW access to ucSharedMemory */ + ucSharedMemory[ 0 ] += 2U; + ucSharedMemory1[ 0 ]++; + ucSharedMemory2[ 0 ]++; + ucSharedMemory3[ 0 ]++; + ucSharedMemory4[ 0 ]++; + #if( configTOTAL_MPU_REGIONS == 16 ) + { + ucSharedMemory5[ 0 ]++; + ucSharedMemory6[ 0 ]++; + ucSharedMemory7[ 0 ]++; + ucSharedMemory8[ 0 ]++; + } + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + /* Set ucVal to 0 */ + ulVal = ( uint32_t ) ucSharedMemory[ 0 ]; + + /* Mark that we will trigger a data abort */ + ucROTaskFaultTracker[ 1 ] = 1U; + /* Attempt to set ulVal to ulStaticUnprotectedData. + * This will trigger a data abort as this task did not grant itself + * access to this variable. The Data abort handler at the bottom of this + * file will then see the raised value in the fault tracker, mark it low, + * and cause this task to resume from the following instruction. + */ + ulVal = ulStaticUnprotectedData; + + /* The value of ucVal should not have changed */ + configASSERT( ulVal != ucSharedMemory[ 0 ] ); + + vToggleLED( 0x1 ); + sci_print( "Read & Write MPU Task sleeping before next loop!\r\n\r\n" ); + + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 4321UL ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xCreateMPUTasks( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + BaseType_t xReturn = pdPASS; + + uint32_t ulReadMemoryPermissions = portMPU_REGION_PRIV_RW_USER_RO_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + uint32_t ulWriteMemoryPermissions = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + ulStaticUnprotectedData = 0xC3; + + TaskParameters_t + xROAccessTaskParameters = { .pvTaskCode = prvROAccessTask, + .pcName = "ROAccess", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = demoMPU_READ_ONLY_TASK_PRIORITY, + .puxStackBuffer = xROAccessTaskStack, + .pxTaskBuffer = &xROAccessTaskTCB, + .xRegions = { + /* Region 0 */ + { ( void * ) ucSharedMemory, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 1 */ + { ( void * ) ucSharedMemory1, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 2 */ + { ( void * ) ucSharedMemory2, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 3 */ + { ( void * ) ucSharedMemory3, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 4 */ + { ( void * ) ucSharedMemory4, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* Region 5 */ + { ( void * ) ucSharedMemory5, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 6 */ + { ( void * ) ucSharedMemory6, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 7 */ + { ( void * ) ucSharedMemory7, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 8 */ + { ( void * ) ucSharedMemory8, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Second to last Configurable Region */ + { ( void * ) ucROTaskFaultTracker, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + TaskParameters_t + xRWAccessTaskParameters = { .pvTaskCode = prvRWAccessTask, + .pcName = "RWAccess", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = ( void * ) ( 0xFF ), + .uxPriority = demoMPU_READ_WRITE_TASK_PRIORITY, + .puxStackBuffer = xRWAccessTaskStack, + .pxTaskBuffer = &xRWAccessTaskTCB, + .xRegions = { + /* First Configurable Region 0 */ + { ( void * ) ucSharedMemory, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 1 */ + { ( void * ) ucSharedMemory1, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 2 */ + { ( void * ) ucSharedMemory2, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 3 */ + { ( void * ) ucSharedMemory3, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 4 */ + { ( void * ) ucSharedMemory4, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 5 */ + { ( void * ) ucSharedMemory5, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 6 */ + { ( void * ) ucSharedMemory6, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 7 */ + { ( void * ) ucSharedMemory7, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 8 */ + { ( void * ) ucSharedMemory8, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Second to Last MPU Region */ + { ( void * ) ucROTaskFaultTracker, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + /* Create an unprivileged task with RO access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xROAccessTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + /* Create an unprivileged task with RW access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xRWAccessTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + sci_print( "Created the MPU Tasks\r\n" ); + } + else + { + sci_print( "Failed to create the Read Write MPU Task\r\n" ); + } + } + else + { + sci_print( "Failed to create the Read Write MPU Task\r\n" ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ +#endif /* ( mainDEMO_TYPE & MPU_DEMO ) */ + +PRIVILEGED_FUNCTION portDONT_DISCARD void vHandleMemoryFault( + uint32_t * pulFaultStackAddress ) +{ + volatile uint32_t ulPC; + volatile uint32_t ulOffendingInstruction; + + /* Is this an expected fault? */ + if( ( ucROTaskFaultTracker[ 0 ] == 1U ) || ( ucROTaskFaultTracker[ 1 ] == 1U ) ) + { + /* Read program counter. */ + ulPC = pulFaultStackAddress[ 6 ]; + + /* Read the offending instruction. */ + ulOffendingInstruction = *( uint32_t * ) ulPC; + + /** From ARM docs: + * Bits [31:28] are the conditional field + * Bits [27:24] are the operation code + * If bits [31:28] are 0b1111, the instruction can only be executed + * unconditionally If bits [31:28] are not 0b1111, the op code determines what the + * instruction is doing If bits [27:24] are 0b01x0 it is a load/store word If bits + * [27:24] are 0b0111 it is a media instruction + */ + + /* Extract bits[31:25] of the offending instruction. */ + ulOffendingInstruction = ulOffendingInstruction & 0xFF000000; + ulOffendingInstruction = ( ulOffendingInstruction >> 24 ); + + /* Check if we were called by a load/store word instruction */ + if( ( ulOffendingInstruction == 0x00E4 ) || ( ulOffendingInstruction == 0x00E5 ) + || ( ulOffendingInstruction == 0x00E6 ) ) + { + /* Increment the program counter to move to the next instruction */ + ulPC += 0x4; + } + else + { + sci_print( "Unexpected Instruction caused an MPU fault\r\n" ); + configASSERT( 0 ); + } + + /* Save the new program counter on the stack. */ + pulFaultStackAddress[ 6 ] = ulPC; + + /* Mark the fault as handled. */ + if( ucROTaskFaultTracker[ 0 ] == 1U ) + { + ucROTaskFaultTracker[ 0 ] = 0U; + sci_print( "Cleared an MPU Read Only Task Fault\r\n" ); + } + else if( ucROTaskFaultTracker[ 1 ] == 1U ) + { + sci_print( "Cleared an MPU Write Only Task Fault\r\n" ); + ucROTaskFaultTracker[ 1 ] = 0U; + } + else + { + sci_print( "TaskFaultTracker value changed, Are IRQs disabled? \r\n" ); + /* Sit in a loop forever */ + configASSERT( 0 ); + } + } + else + { + sci_print( "Unexpected MPU Fault\r\n" ); + /* This is an unexpected fault - loop forever. */ + configASSERT( 0 ); + } +} + +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/notification_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/notification_demo.c new file mode 100644 index 00000000000..b4fd35c983e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/notification_demo.c @@ -0,0 +1,242 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if( mainDEMO_TYPE & NOTIFICATION_DEMO ) + + /** @brief Parameters that are passed into the notification test task solely + * for the purpose of ensuring parameters are passed into tasks correctly. */ + #define notificationTASK_PARAMETER ( 0xFEEDBEEFUL ) + + /** @brief Value sent back and forth between the tasks */ + #define notificationTEST_VALUE 0x1234UL + +/** @brief TCB used by the Notification Test Task */ +PRIVILEGED_DATA static StaticTask_t xNotificationTestTaskTCB; + +/** @brief MPU Region Aligned Stack used by the Notification Test Task */ +static StackType_t uxNotificationTestTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4UL ) ) ); + +/** @brief Statically allocated task handle for the Notification Test task. */ +static TaskHandle_t xNotificationTaskOneHandle; + +/* ----------------------------------------------------------------------------------- */ + +static void prvNotifyCheck( BaseType_t ulRetVal ) +{ + if( pdPASS == ulRetVal ) + { + sci_print( "Notification API Returned a passing value!\r\n" ); + } + else + { + sci_print( "Notification API did not return pdPASS.\r\n" ); + configASSERT( ulRetVal ); + } +} + +/** @brief Entry point for the Unprivileged Notification Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task sends itself and another task notifications using the + * cross-task notification APIs. + */ +static void prvNotificationTestTask( void * pvParameters ) +{ + BaseType_t xReturned; + UBaseType_t ulNotificationValue; + + /* Ensure that the correct parameter was passed to the task */ + configASSERT( ( uint32_t ) pvParameters == notificationTEST_VALUE ); + for( ;; ) + { + /* Clear the notification value each loop */ + ulNotificationValue = 0x0UL; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0x0UL, 0x0UL, &ulNotificationValue, 0x0UL ); + configASSERT( pdFAIL == xReturned ); + configASSERT( 0x0UL == ulNotificationValue ); + + /* Tell the task to notify itself twice */ + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + /* Perform a non-blocking notification read, should see two "gives" */ + ulNotificationValue = ulTaskNotifyTake( pdTRUE, 0x0 ); + + /* Two notifications have been sent to this task by itself */ + configASSERT( 0x2UL == ulNotificationValue ); + sci_print( "Notification Task correctly sent itself two notifications!\r\n" ); + + /* Now make the task send itself a notification with a value */ + xReturned = xTaskNotify( xTaskGetCurrentTaskHandle(), + notificationTEST_VALUE, + eSetValueWithOverwrite ); + prvNotifyCheck( xReturned ); + + /* Clear ulNotificationValue before using it */ + ulNotificationValue = 0x0UL; + + /* Receive the value sent using xTaskNotify */ + xReturned = xTaskNotifyWait( 0, + ( uint32_t ) 0xFFFFFFFFUL, + &ulNotificationValue, + ( TickType_t ) 0x50UL ); + prvNotifyCheck( xReturned ); + + if( notificationTEST_VALUE == ulNotificationValue ) + { + sci_print( "Notification Task got the expected value!\r\n" ); + } + else + { + sci_print( "Notification Task did NOT get the expected value!\r\n" ); + configASSERT( 0x0UL ); + } + + /* Reset the variable before using it */ + ulNotificationValue = 0x0UL; + + /* There should be no value to receive this time */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, ( TickType_t ) 0x0UL ); + if( ( pdPASS == xReturned ) || ( 0x0 != ulNotificationValue ) ) + { + sci_print( "Notification Task received a value when there should have been " + "none" ); + configASSERT( 0x0UL ); + } + + xTaskNotify( xTaskGetCurrentTaskHandle(), + ulNotificationValue, + eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* First time a notification was pending. */ + configASSERT( xReturned == pdTRUE ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* Second time the notification was already clear. */ + configASSERT( xReturned == pdFALSE ); + + sci_print( "Notification Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 2750UL ) ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateNotificationTestTask( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + BaseType_t xReturn = pdFAIL; + /* Create the register check tasks, as described at the top of this file. */ + TaskParameters_t xNotificationTestTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvNotificationTestTask, + /* The name of the task. */ + .pcName = "NotificationTestTask", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE, + /* Parameter passed into the task. */ + .pvParameters = ( void * ) notificationTEST_VALUE, + /* Priority of the task. */ + .uxPriority = ( demoNOTIFICATION_TASK_PRIORITY ), + .puxStackBuffer = uxNotificationTestTaskStack, + .pxTaskBuffer = &xNotificationTestTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { ( void * ) &xNotificationTaskOneHandle, + ( uint32_t ) sizeof( TaskHandle_t ), + portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | + portMPU_REGION_NORMAL_OIWTNOWA_SHARED }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, + #endif + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, ulPeriphRegionSize, ulPeriphRegionAttr }, + } + }; + + /* Create the notification test task */ + xReturn = xTaskCreateRestrictedStatic( &( xNotificationTestTaskParameters ), + &( xNotificationTaskOneHandle ) ); + if( pdPASS == xReturn ) + { + sci_print( "Created the Notification Test Task\r\n" ); + } + else + { + sci_print( "Failed to create the Notification Test Task\r\n" ); + } + + return xReturn; +} +#endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/queue_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/queue_demo.c new file mode 100644 index 00000000000..7b73606df80 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/queue_demo.c @@ -0,0 +1,448 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file queue_demo.c + * @brief Use the Queue APIs to send data from a sender task to a receiver task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" + +/* Board Support Package Includes */ +#include "sci.h" +#include "reg_system.h" + +/* Demo Specific Includes */ +#include "demo_tasks.h" + +#if( mainDEMO_TYPE & QUEUE_DEMO ) + + /* ------------------------------ Demo Task Configs ------------------------------ */ + + /** @brief The rate at which data is sent to the queue from the send task. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) + + /** @brief The rate at which data is sent to the queue from the timer. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + + /** @brief The number of items the queue can hold at once. */ + #define queueQUEUE_LENGTH ( 2 ) + + /** @brief Value sent from the send task to the receive task */ + #define queueVALUE_SENT_FROM_TASK ( 0x1234UL ) + + /** @brief Value sent from the timer to the receive task */ + #define queueVALUE_SENT_FROM_TIMER ( 0x4321UL ) + +/* --------------------- Task Function Declaration --------------------- */ + +/** @brief Function run by the task that receives data from the queue. + * @note + * The queue receive task is implemented by the prvQueueReceiveTask() + * function in this file. prvQueueReceiveTask() waits for data to arrive on + * the queue. When data is received, the task checks the value of the data, + * then outputs a message to indicate if the data came from the queue send + * task or the queue send software timer. */ +static void prvQueueReceiveTask( void * pvParameters ); + +/** @brief Function run by the task that sends data to a queue. + * @note + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It uses vTaskDelayUntil() to create a periodic task that + * sends queueVALUE_SENT_FROM_TASK to the queue every 200 milliseconds. */ +static void prvQueueSendTask( void * pvParameters ); + +/** @brief The callback function executed when the timer expires. + * @note + * The timer is an auto-reload timer with a period of two seconds. Its + * callback function sends the value queueVALUE_SENT_FROM_TIMER to the + * queue. The callback function is implemented by prvQueueSendTimerCallback(). + */ +static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); + +/*-------------------- Static Task Memory Allocation ------------------- */ + +/** @brief Statically allocated, and MPU aligned, Queue object */ +static StaticQueue_t xStaticQueue __attribute__( ( aligned( 0x80 ) ) ); + +/** @brief Statically allocated, and MPU aligned, Storage for the Queue */ +static uint8_t xQueueStorage[ 0x20 ] __attribute__( ( aligned( 0x80 ) ) ); + +/** @brief Statically allocated, and MPU aligned, QueueHandle */ +static QueueHandle_t xQueue __attribute__( ( aligned( 0x20 ) ) ); + +/* Each task needs to know the other tasks handle so they can send signals to + * each other. The handle is obtained from the task's name. */ + +/** @brief Task name for the queue send task. */ +static const char * pcSendTaskName = "SendTaskName"; + +/** @brief Task name for the queue receive task. */ +static const char * pcReceiveTaskName = "ReceiveTaskName"; + +/** @brief Static MPU aligned stack used by the Queue Send Task */ +static StackType_t xQueueSendTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/** @brief Static TCB Used by the Queue Send Task */ +PRIVILEGED_DATA static StaticTask_t xQueueSendTaskTCB; + +/** @brief Static MPU aligned stack used by the Queue Receive Task */ +static StackType_t xQueueReceiveTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/** @brief Static TCB Used by the Queue Receive Task */ +PRIVILEGED_DATA static StaticTask_t xQueueReceiveTaskTCB; + +/** @brief A software timer that is started from the tick hook. */ +static TimerHandle_t xTimer = NULL; + +/** @brief Statically allocated timer object. */ +static StaticTimer_t xStaticTimer; + +/** @brief Statically allocated task handle for the queue receive task. */ +static TaskHandle_t xReceiveTaskHandle; + +/** @brief Statically allocated task handle for the queue send task. */ +static TaskHandle_t xSendTaskHandle; + +/* ------------------------------------------------------------------------------------ */ + +BaseType_t prvCreateQueueTasks( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + BaseType_t xReturn = pdPASS; + + uint32_t ulRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + /* Start the two tasks as described in the comments at the top of this file. */ + TaskParameters_t + xQueueReceiveTaskParameters = { .pvTaskCode = prvQueueReceiveTask, + .pcName = pcReceiveTaskName, + .usStackDepth = configMINIMAL_STACK_SIZE / 2U, + .pvParameters = NULL, + .uxPriority = demoQUEUE_RECEIVE_TASK_PRIORITY, + .puxStackBuffer = xQueueReceiveTaskStack, + .pxTaskBuffer = &xQueueReceiveTaskTCB, + .xRegions = { + /* First Configurable Region 0 */ + { ( void * ) &xStaticQueue, + ( uint32_t ) sizeof( StaticQueue_t ), + ulRegionAttr }, + /* Region 1 */ + { ( void * ) &xQueueStorage, + ( uint32_t ) sizeof( xQueueStorage ), + ulRegionAttr }, + /* Region 2 */ + { ( void * ) &xQueue, + ( uint32_t ) sizeof( QueueHandle_t ), + ulRegionAttr }, + /* Region 3 */ + { 0, 0, 0 }, + /* Region 4 */ + { 0, 0, 0 }, + /* Region 5 */ + { 0, 0, 0 }, + /* Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* Region 7 */ + { 0, 0, 0 }, + /* Region 8 */ + { 0, 0, 0 }, + /* Region 9 */ + { 0, 0, 0 }, + /* Region 10 */ + { 0, 0, 0 }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + TaskParameters_t + xQueueSendTaskParameters = { .pvTaskCode = prvQueueSendTask, + .pcName = pcSendTaskName, + .usStackDepth = configMINIMAL_STACK_SIZE / 2U, + .pvParameters = NULL, + .uxPriority = demoQUEUE_SEND_TASK_PRIORITY, + .puxStackBuffer = xQueueSendTaskStack, + .pxTaskBuffer = &xQueueSendTaskTCB, + .xRegions = { + /* First Configurable Region 0 */ + { ( void * ) &xStaticQueue, + ( uint32_t ) sizeof( StaticQueue_t ), + ulRegionAttr }, + /* Region 1 */ + { ( void * ) &xQueueStorage, + ( uint32_t ) sizeof( xQueueStorage ), + ulRegionAttr }, + /* Region 2 */ + { ( void * ) &xQueue, + ( uint32_t ) sizeof( QueueHandle_t ), + ulRegionAttr }, + /* Region 3 */ + { 0, 0, 0 }, + /* Region 4 */ + { 0, 0, 5 }, + /* Region 5 */ + { 0, 0, 0 }, + /* Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* Region 7 */ + { 0, 0, 0 }, + /* Region 8 */ + { 0, 0, 0 }, + /* Region 9 */ + { 0, 0, 0 }, + /* Region 10 */ + { 0, 0, 0 }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + /* Create an unprivileged task with RO access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xQueueReceiveTaskParameters ), + &( xReceiveTaskHandle ) ); + + if( pdPASS == xReturn ) + { + sci_print( "Created the Queue Receive Task\r\n" ); + /* Create an unprivileged task with RW access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xQueueSendTaskParameters ), + &xSendTaskHandle ); + if( pdPASS == xReturn ) + { + sci_print( "Created the Queue Send Task\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + return xReturn; +} + +BaseType_t xCreateQueueTasks( void ) +{ + BaseType_t xReturn = pdPASS; + + /* The Receive Task MUST be a higher priority than the send task. */ + configASSERT( demoQUEUE_RECEIVE_TASK_PRIORITY > demoQUEUE_SEND_TASK_PRIORITY ); + + /* Create the queue used by the queue tasks . */ + xQueue = xQueueCreateStatic( queueQUEUE_LENGTH, + sizeof( uint32_t ), + xQueueStorage, + &xStaticQueue ); + + if( xQueue != NULL ) + { + sci_print( "Created the Queue for the tasks\r\n" ); + + /** @brief The debugging text name for the timer */ + const char * pcTimerName = "Timer"; + /** @brief Mark that this is an auto-reload timer. */ + const BaseType_t xAutoReload = ( BaseType_t ) pdTRUE; + /** @brief Timer ID that is not used in this demo. */ + void * const pvTimerID = NULL; + /** @brief Callback function for the timer */ + TimerCallbackFunction_t pxCallbackFunction = prvQueueSendTimerCallback; + + /* Create a statically allocated timer */ + xTimer = xTimerCreateStatic( pcTimerName, + ( const TickType_t ) queueTIMER_SEND_FREQUENCY_MS, + xAutoReload, + pvTimerID, + pxCallbackFunction, + &( xStaticTimer ) ); + } + else + { + sci_print( "Failed to create the Queue for the tasks\r\n" ); + xReturn = pdFAIL; + } + + if( NULL != xTimer ) + { + sci_print( "Created the Queue Timer\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Timer\r\n" ); + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + xReturn = prvCreateQueueTasks(); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + /* Use an Access Control List to allow the tasks to use this queue */ + vGrantAccessToQueue( xReceiveTaskHandle, xQueue ); + vGrantAccessToQueue( xSendTaskHandle, xQueue ); + + /* The scheduler has not started so use a block time of 0. */ + xReturn = xTimerStart( xTimer, 0 ); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + sci_print( "Started the Timer\r\n" ); + } + else + { + sci_print( "Failed to start the Queue Timer\r\n" ); + } + + return xReturn; +} + +/*-----------------------------------------------------------------------*/ + +static void prvQueueSendTask( void * pvParameters ) +{ + TickType_t xNextWakeTime; + const TickType_t xBlockTime = queueTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TASK; + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Move this task to the blocked state for xBlockTime milliseconds. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in + * ticks. While in the Blocked state this task will not consume any + * CPU time. */ + xTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock + * and write to the console. 0 is used as the block time so the send + * operation will not block. It shouldn't need to block as the queue + * should always have at least one space at this point in the code. + */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} + +/*-----------------------------------------------------------------------*/ + +static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) +{ + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TIMER; + + /* This is the software timer callback function. The software timer has + * a period of two seconds. This callback function will execute if the + * timer expires, which will happen every two seconds. */ + + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; + + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon + * task, so must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); +} + +/*-----------------------------------------------------------------------*/ + +static void prvQueueReceiveTask( void * pvParameters ) +{ + uint32_t ulReceivedValue = 0; + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, + * but is it an expected value? */ + if( ulReceivedValue == queueVALUE_SENT_FROM_TASK ) + { + vToggleLED( 0x0 ); + } + else if( ulReceivedValue == queueVALUE_SENT_FROM_TIMER ) + { + vToggleLED( 0x1 ); + } + else + { + /* Invalid value received. Force an assert. */ + configASSERT( ulReceivedValue == !ulReceivedValue ); + } + } +} +/* --------------------------------------------------------------------- */ + +#endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/reg_test.c b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/reg_test.c new file mode 100644 index 00000000000..e662b54ff7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/reg_test.c @@ -0,0 +1,246 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +/* ----------------------------------------------------------------------------------- */ + +/** @brief TCB used by Register Test Task One */ +PRIVILEGED_DATA static StaticTask_t xRegTestOneTaskTCB; + +/** @brief Small MPU Region Aligned Stack used by Register Test Task One */ +PRIVILEGED_DATA static StackType_t uxRegTestOneTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/** @brief TCB used by Register Test Two Task */ +PRIVILEGED_DATA static StaticTask_t xRegTestTwoTaskTCB; + +/** @brief Small MPU Region Aligned Stack used by Register Test Task Two */ +static StackType_t uxRegTestTwoTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/* Parameters that are passed into the register check tasks solely for the + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Array to track the number of loops the register test tasks have run. + * + * @note Smallest valid MPU region size for Armv7-R is 32 bytes. + * Register Test One will use loopCount[0]; + * Register Test Two Will use loopCount[1]; + */ +uint32_t loopCounter[ 0x8 ] __attribute__( ( aligned( 0x20 ) ) ); + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Privileged Register Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry1( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + else + { + /** The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Unprivileged Register Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry2( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + else + { + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateRegisterTestTasks( void ) +{ + BaseType_t xReturn = pdFAIL; + /* Create the register check tasks, as described at the top of this file. */ + TaskParameters_t xRegTestOneTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvRegTestTaskEntry1, + /* The name of the task. */ + .pcName = "RegTestOne", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE / 0x2, + /* Parameter passed into the task. */ + .pvParameters = mainREG_TEST_TASK_1_PARAMETER, + /* Priority of the task. */ + .uxPriority = demoREG_PRIVILEGED_TASK_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = uxRegTestOneTaskStack, + .pxTaskBuffer = &xRegTestOneTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { loopCounter, + 0x20, + portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_NORMAL_OIWTNOWA_SHARED, + }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, +#if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, +#endif + /* Final MPU Region */ + { 0, 0, 0 }, + } + }; + + TaskParameters_t xRegTestTwoTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvRegTestTaskEntry2, + /* The name of the task. */ + .pcName = "RegTestTwo", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE / 0x2, + /* Parameter passed into the task. */ + .pvParameters = mainREG_TEST_TASK_2_PARAMETER, + /* Priority of the task. */ + .uxPriority = demoREG_UNPRIVILEGED_TASK_PRIORITY, + .puxStackBuffer = uxRegTestTwoTaskStack, + .pxTaskBuffer = &xRegTestTwoTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { loopCounter, + 0x20, + portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_NORMAL_OIWTNOWA_SHARED, + }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, +#if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, +#endif + /* Final MPU Region */ + { 0, 0, 0 }, + } + }; + + /* Create the first register test task as a privileged task */ + xReturn = xTaskCreateRestrictedStatic( &( xRegTestOneTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + /* Create the second register test task as an unprivileged task */ + xReturn = xTaskCreateRestrictedStatic( &( xRegTestTwoTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + sci_print( "Created the Unprivileged Regsiter Test Task\r\n" ); + } + else + { + sci_print( "Failed to create the Unprivileged Regsiter Test Task\r\n" ); + } + } + else + { + sci_print( "Failed to create the Privileged Regsiter Test Task\r\n" ); + } + + return xReturn; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/reg_test_GCC.S new file mode 100644 index 00000000000..43b8fc7d050 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/source/reg_test_GCC.S @@ -0,0 +1,448 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#define FREERTOS_ASSEMBLY + #include "portmacro_asm.h" + #include "FreeRTOSConfig.h" +#undef FREERTOS_ASSEMBLY + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern vPortYield + .extern MPU_vTaskDelay + .extern + .extern loopCounter + .text + .arm + +/*-----------------------------------------------------------*/ + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + MOV R0, #0xFF + MOV R1, #0x11 + MOV R2, #0x22 + MOV R3, #0x33 + MOV R4, #0x44 + MOV R5, #0x55 + MOV R6, #0x66 + MOV R7, #0x77 + MOV R8, #0x88 + MOV R9, #0x99 + MOV R10, #0xAA + MOV R11, #0xBB + MOV R12, #0xCC + MOV R14, #0xEE + + /* Fill each FPU register with a known value. */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg1_loop: + /* Perform a yield to increase test coverage */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B reg1_error_loopf + B 0xDEACFC + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + CMP R0, #0xFF + BLNE reg1_error_loop + CMP R1, #0x11 + BLNE reg1_error_loop + CMP R2, #0x22 + BLNE reg1_error_loop + CMP R3, #0x33 + BLNE reg1_error_loop + CMP R4, #0x44 + BLNE reg1_error_loop + CMP R5, #0x55 + BLNE reg1_error_loop + CMP R6, #0x66 + BLNE reg1_error_loop + CMP R7, #0x77 + BLNE reg1_error_loop + CMP R8, #0x88 + BLNE reg1_error_loop + CMP R9, #0x99 + BLNE reg1_error_loop + CMP R10, #0xAA + BLNE reg1_error_loop + CMP R11, #0xBB + BLNE reg1_error_loop + CMP R12, #0xCC + BLNE reg1_error_loop + CMP R14, #0xEE + BLNE reg1_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0] + ADD R1, R1, #1 + STR R1, [R0] + POP { R0-R1 } + + /* Delay for 0x100 ticks before running again */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x100 + /* As this is a privileged task, it can directly call vTaskDelay */ + LDR R1, =vTaskDelay + BLX R1 + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B 0xDEACFD + NOP + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + MOV R0, #0xFF000000 + MOV R1, #0x11000000 + MOV R2, #0x22000000 + MOV R3, #0x33000000 + MOV R4, #0x44000000 + MOV R5, #0x55000000 + MOV R6, #0x66000000 + MOV R7, #0x77000000 + MOV R8, #0x88000000 + MOV R9, #0x99000000 + MOV R10, #0xAA000000 + MOV R11, #0xBB000000 + MOV R12, #0xCC000000 + MOV R14, #0xEE000000 + + /* Likewise the floating point registers */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg2_loop: + + /* Yield to increase test coverage */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B 0xDEACFE + +reg2_loopf_pass: + + CMP R0, #0xFF000000 + BLNE reg2_error_loop + CMP R1, #0x11000000 + BLNE reg2_error_loop + CMP R2, #0x22000000 + BLNE reg2_error_loop + CMP R3, #0x33000000 + BLNE reg2_error_loop + CMP R4, #0x44000000 + BLNE reg2_error_loop + CMP R5, #0x55000000 + BLNE reg2_error_loop + CMP R6, #0x66000000 + BLNE reg2_error_loop + CMP R7, #0x77000000 + BLNE reg2_error_loop + CMP R8, #0x88000000 + BLNE reg2_error_loop + CMP R9, #0x99000000 + BLNE reg2_error_loop + CMP R10, #0xAA000000 + BLNE reg2_error_loop + CMP R11, #0xBB000000 + BLNE reg2_error_loop + CMP R12, #0xCC000000 + BLNE reg2_error_loop + CMP R14, #0xEE000000 + BLNE reg2_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0, #+0x4] + ADD R1, R1, #1 + STR R1, [R0, #+0x4] + POP { R0-R1 } + + /* Delay for 0x200 ticks before running again */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x200 + /* Unprivileged tasks need to use the MPU wrapped functions. + * Change this to be BLX vTaskDelay to trigger a pre-fetch abort. */ + BLX MPU_vTaskDelay + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B 0xDEACFF + NOP + +/* End of file */ +.end + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/targetConfigs/RM46L852.ccxml b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/targetConfigs/RM46L852.ccxml new file mode 100644 index 00000000000..c3732502fef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/targetConfigs/RM46L852.ccxml @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/targetConfigs/readme.txt b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/targetConfigs/readme.txt new file mode 100644 index 00000000000..d783fef4d6a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.ccsproject b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.ccsproject new file mode 100644 index 00000000000..7fdda62015b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.ccsproject @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.clang-format b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.clang-format new file mode 100644 index 00000000000..c745d9c66fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.clang-format @@ -0,0 +1,104 @@ +--- +Language: Cpp +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: None +AlignConsecutiveBitFields: AcrossEmptyLinesAndComments +AlignConsecutiveDeclarations: None +AlignConsecutiveMacros: AcrossEmptyLinesAndComments +AlignEscapedNewlines: Left +AlignOperands: AlignAfterOperator +AlignTrailingComments: true +AllowAllArgumentsOnNextLine: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: Never +AllowShortCaseLabelsOnASingleLine: false +AllowShortEnumsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: false +AllowShortLambdasOnASingleLine: All +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: Yes +BinPackArguments: false +BinPackParameters: false +BitFieldColonSpacing: Both +BraceWrapping: + AfterCaseLabel: true + AfterClass: true + AfterControlStatement: Always + AfterEnum: true + AfterExternBlock: false + AfterFunction: true + AfterNamespace: true + AfterStruct: true + AfterUnion: true + BeforeCatch: true + BeforeElse: true + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBinaryOperators: NonAssignment +BreakBeforeBraces: Custom +BreakBeforeConceptDeclarations: true +BreakBeforeTernaryOperators: true +BreakConstructorInitializers: BeforeColon +BreakInheritanceList: BeforeColon +BreakStringLiterals: true +ColumnLimit: 90 +CompactNamespaces: false +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +EmptyLineBeforeAccessModifier: Always +FixNamespaceComments: true +IncludeBlocks: Preserve +IndentCaseBlocks: false +IndentCaseLabels: true +IndentExternBlock: NoIndent +IndentGotoLabels: true +IndentPPDirectives: BeforeHash +IndentWidth: 4 +IndentWrappedFunctionNames: true +KeepEmptyLinesAtTheStartOfBlocks: false +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +PenaltyBreakAssignment: 1000 +PenaltyBreakBeforeFirstCallParameter: 200 +PenaltyBreakComment: 50 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 100 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 100 +PenaltyIndentedWhitespace: 0 +PenaltyReturnTypeOnItsOwnLine: 10000 +PointerAlignment: Middle +ReflowComments: true +SortIncludes: false +SortUsingDeclarations: true +SpaceAfterCStyleCast: true +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: false +SpaceBeforeCpp11BracedList: true +SpaceBeforeCtorInitializerColon: false +SpaceBeforeInheritanceColon: false +SpaceBeforeParens: Never +SpaceBeforeRangeBasedForLoopColon: false +SpaceBeforeSquareBrackets: false +SpaceInEmptyBlock: false +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInConditionalStatement: true +SpacesInContainerLiterals: true +SpacesInCStyleCastParentheses: true +SpacesInParentheses: true +SpacesInSquareBrackets: true +TabWidth: 4 +UseCRLF: false +UseTab: Never +... + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.cproject b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.cproject new file mode 100644 index 00000000000..29e8979ae89 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.cproject @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.gitignore new file mode 100644 index 00000000000..ba04ae8d56e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.gitignore @@ -0,0 +1,4 @@ +[Bb]uild +[Dd]ebug +.settings/ +.launches/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.project new file mode 100644 index 00000000000..8ea7e150fa2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.project @@ -0,0 +1,130 @@ + + + RM57_DEMO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + FreeRTOS-Kernel + 2 + FREERTOS_KERNEL_DIR + + + + + 1703728734708 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-CMakeLists.txt + + + + 1703728734721 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-build + + + + 1703284519364 + FreeRTOS-Kernel + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.c + + + + 1703284519366 + FreeRTOS-Kernel + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-examples + + + + 1703728684338 + FreeRTOS-Kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Common + + + + 1703728684340 + FreeRTOS-Kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1703263792368 + FreeRTOS-Kernel/portable/Common + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-mpu_wrappers.c + + + + 1703728698924 + FreeRTOS-Kernel/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CRx_MPU + + + + + + BOARD_FILES_DIR + $%7BPROJECT_LOC%7D/BoardFiles + + + DEMO_TASKS_DIR + $%7BPARENT-1-PROJECT_LOC%7D/DemoTasks + + + FREERTOS_KERNEL_DIR + $%7BPARENT-2-PROJECT_LOC%7D/Source + + + FREERTOS_PORT_DIR + $%7BFREERTOS_KERNEL_DIR%7D/portable/GCC/ARM_CRx_MPU + + + REPOSITORY_ROOT + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC.code-workspace b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC.code-workspace new file mode 100644 index 00000000000..87f157a2203 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC.code-workspace @@ -0,0 +1,50 @@ +{ + "folders": [ + { + "path": ".." + }, + { + "path": "../../../Source", + "name": "FreeRTOS-Kernel" + }, + { + "path": "../../../Source/portable/GCC/ARM_CRx_MPU", + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_MPU", + "../../Source/include", + "../../Source", + ], + } + ], + "settings": { + "files.associations": { + "*.h": "c", + "variant": "c" + }, + + "files.exclude": { + "**/.launches/**": true, + "**/.settings/**": true, + "**/.ccsproject/**": true, + "**/examples**": true, + "**/.github**": true, + "**/.git[a-hj-z-]**": true, + "**/portable/**": true + + }, + + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_MPU", + "../../Source/include", + "../../Source", + ], + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil new file mode 100644 index 00000000000..49910de8bf4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil @@ -0,0 +1,11975 @@ +# RM57L843ZWT 02/13/23 13:55:32 +# +ARCH=RM57L843ZWT +# +DRIVER.TOOLS.VAR.GCC.VALUE=1 +DRIVER.TOOLS.VAR.ARM.VALUE=0 +DRIVER.TOOLS.VAR.IAR.VALUE=0 +DRIVER.TOOLS.VAR.GHS.VALUE=0 +DRIVER.TOOLS.VAR.TI.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OIWTNOWA_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_0.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_1_WAIT_STATE_FREQ.VALUE=32.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=mibspi4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2 +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_1.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=180.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.LIN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0002 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=epcFullInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=sci4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=ecap5Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=150.000 +DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=300.00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=dmaBTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x6FFFFFFF +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=etpwm5TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_isrStub +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OIWBWA_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x00007fff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=90.0 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08000500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=etpwm1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SIZE.VALUE=512_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_STACK.VALUE=12 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=FreeRTOS_Tick_Handler +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=can4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=ecap6Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x00080000 +DRIVER.SYSTEM.VAR.CORE_MPU_TOTAL_REGION.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=256_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=dmaFTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_8_WAIT_STATE_FREQ.VALUE=144.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt +DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=40 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=300.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48 +DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=8 +DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001 +DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=etpwm1TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0xF8000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x1B +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_NUM.VALUE=3 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=lin2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=dmaLFSAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_6_WAIT_STATE_FREQ.VALUE=112.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SIZE_VALUE.VALUE=0x12 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE +DRIVER.SYSTEM.VAR.CRC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_WAIT_STATES.VALUE=9 +DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08000600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_HCLK_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=sci4LowLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_4_WAIT_STATE_FREQ.VALUE=80.0 +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=120.0 +DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=lin1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=eqep1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=etpwm7Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=0 +DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_ECC_AVAILABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x000C +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_CACHE_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=9.375 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=etpwm2TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_10_WAIT_STATE_FREQ.VALUE=176.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_NA_EXEC +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0x003fffff +DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=VCLKA4_DIVR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_2_WAIT_STATE_FREQ.VALUE=48.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=18.750 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.MIBSPI2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=150 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_LAST.VALUE=15 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_FIRST.VALUE=13 +DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=eqep2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0007F800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=150 +DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=0.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=etpwm3Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00008020 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00200000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_0_WAIT_STATE_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=135.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5 +DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=128 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.LIN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=ecap1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68 +DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_9_WAIT_STATE_FREQ.VALUE=160.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00400000 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=etpwm3TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=EMACRxIntISR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=45.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=75.000 +DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_MAX_WAIT_STATES.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x000B +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=mibspi4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt +DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESERVED_ENTRY.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=crc2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=can4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=ecap2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.I2C1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_7_WAIT_STATE_FREQ.VALUE=128.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=vPortYieldWithinAPI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=lin1HighLevelInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08000700 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=etpwm4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0807ffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x0E +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=75.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL_VAL.VALUE=9500 +DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=dmaHBCAInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13 +DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=8 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_5_WAIT_STATE_FREQ.VALUE=96.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=i2c2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=ecap3nterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=32_KB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=mibspi2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt +DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SCI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=vPortSWI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1 +DRIVER.SYSTEM.VAR.CRC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0002 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=etpwm4TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3 +DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=75.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_M3.VALUE=0 +DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OIWTNOWA_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x001F7FE0 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00200000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_11_WAIT_STATE_FREQ.VALUE=192.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sci3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_3_WAIT_STATE_FREQ.VALUE=64.0 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08000400 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000020000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=lin2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=ecap4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=0 +DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE +DRIVER.SYSTEM.VAR.CLKT_RESERVED_SOURCE_ENABLE.VALUE=0x00000004 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=512_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=0 +DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=9500 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=300.00 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_BASE_ADDRESS.VALUE=0xFFF80000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=etpwm5Interrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2 +DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.AJSM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SPL_SOURCE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9 +DRIVER.SYSTEM.VAR.VIM_ECC_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SCI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_MAPPING.VALUE=111 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_MAPPING.VALUE=103 +DRIVER.SYSTEM.VAR.VIM_PHANTOM_NAME.VALUE=phantomInterrupt +DRIVER.OS.VAR.OS_USERECERSIVEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_USETIMERS.VALUE=0 +DRIVER.OS.VAR.OS_USECNTSEMAPHORE.VALUE=0 +DRIVER.OS.VAR.OS_GENERATERUNTIMESTATS.VALUE=0 +DRIVER.OS.VAR.OS_USEMPU.VALUE=0 +DRIVER.OS.VAR.OS_TOTALHEAPSIZE.VALUE=8192 +DRIVER.OS.VAR.OS_USEVERBOSESTACK.VALUE=2 +DRIVER.OS.VAR.OS_TIMERPRIORITY.VALUE=0 +DRIVER.OS.VAR.OS_SVCENABLE.VALUE=0 +DRIVER.OS.VAR.OS_MAXTASKNAMELEN.VALUE=16 +DRIVER.OS.VAR.OS_MAXPRIORITIES.VALUE=5 +DRIVER.OS.VAR.OS_TIMERTASKSTACKDEPTH.VALUE=0 +DRIVER.OS.VAR.OS_COROUTINEPRIORITIES.VALUE=2 +DRIVER.OS.VAR.OS_USECOROUTINES.VALUE=0 +DRIVER.OS.VAR.OS_USEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_CPUCLOCKHZ.VALUE=75000000 +DRIVER.OS.VAR.OS_USEMALLOCFAILEDHOOK.VALUE=0 +DRIVER.OS.VAR.OS_MINSTACKSIZE.VALUE=128 +DRIVER.OS.VAR.OS_SYSTEM_MODE.VALUE=0x1F +DRIVER.OS.VAR.OS_USEPREEMPTION.VALUE=1 +DRIVER.OS.VAR.OS_IDLESHOULDYIELD.VALUE=1 +DRIVER.OS.VAR.OS_USEIDLEHOOK.VALUE=0 +DRIVER.OS.VAR.OS_TICKRATEHZ.VALUE=1000 +DRIVER.OS.VAR.OS_TIMERPQUEUELENGTH.VALUE=0 +DRIVER.OS.VAR.OS_USETRACE.VALUE=0 +DRIVER.OS.VAR.OS_USESTACK.VALUE=0 +DRIVER.OS.VAR.OS_USETICKHOOK.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL93_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL85_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL77_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL69_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL94_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL86_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL78_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL88_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL81_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL73_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL65_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL70_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL94_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL86_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL78_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL91_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL83_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL75_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL67_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL82_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL74_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL66_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=218.453 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL31_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL23_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL15_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL95_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL87_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL79_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL88_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL82_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL74_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL66_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL82_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL74_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL66_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL60_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL52_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL44_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL36_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL28_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL80_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL72_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL64_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=75 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL93_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL85_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL77_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL69_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL95_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL87_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL79_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL95_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL87_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL79_ENABLE.VALUE=0 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+DRIVER.SCI.VAR.SCI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI2_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI1_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.SCI.VAR.SCI4_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI3_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI4_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI4_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI1_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI4_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI3_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI4_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_BASE_PORT.VALUE=0xFFF7E740 +DRIVER.SCI.VAR.SCI4_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI2_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI4_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI3_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI1_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_BASE_PORT.VALUE=0xFFF7E640 +DRIVER.SCI.VAR.SCI3_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI3_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI2_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI4_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI1_BASE.VALUE=0xFFF7E400 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI1_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_BASE.VALUE=0xFFF7E600 +DRIVER.SCI.VAR.SCI2_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI3_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI3_BASE.VALUE=0xFFF7E500 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI2_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_BASE_PORT.VALUE=0xFFF7E540 +DRIVER.SCI.VAR.SCI4_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI2_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI2_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_BASE_RAM.VALUE=0xFF080000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.MIBSPI.VAR.MIBSPI4_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI4_BASE_RAM.VALUE=0xFF060000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_BASE.VALUE=0xFFF7F600 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF060000 +DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400 +DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF080000 +DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00 +DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_BASE.VALUE=0xFFF7E200 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_4_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_4_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_RAMBASE.VALUE=0xFF180000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=106.67 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000 +DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=106.67 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000 +DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=7 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=7 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN1_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN1_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.LIN.VAR.LIN2_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN2_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN2_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_MAXPRESCALE.VALUE=3370 +DRIVER.LIN.VAR.LIN2_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN1_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN1_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN2_RXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_FEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN2_IDINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN2_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN2_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BASE.VALUE=0xFFF7E400 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN2_TOINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN2_BEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_ACTUALBAUDRATE.VALUE=20.032 +DRIVER.LIN.VAR.LIN1_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN2_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN2_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN2_RXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PRESCALE.VALUE=233 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN2_BASE.VALUE=0xFFF7E600 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN2_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN2_BASE_PORT.VALUE=0xFFF7E640 +DRIVER.LIN.VAR.LIN1_BAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN2_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN2_MAXBAUDRATE.VALUE=22.255 +DRIVER.LIN.VAR.LIN1_RXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_FEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN2_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_ISFEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_ACTUALBAUDRATE.VALUE=20.032 +DRIVER.LIN.VAR.LIN1_IDINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN1_BEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_RXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN1_PRESCALE.VALUE=233 +DRIVER.LIN.VAR.LIN1_ISFEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN2_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN2_MAXPRESCALE.VALUE=3370 +DRIVER.LIN.VAR.LIN2_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_MAXBAUDRATE.VALUE=22.255 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN2_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN2_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=149888 +DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0 +DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000008 +DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50 +DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000 +DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10 +DRIVER.HET.VAR.HET2_BIT20_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.053 +DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3 +DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0 +DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000 +DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00002000 +DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.106 +DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9 +DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT26_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0 +DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16 +DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.053 +DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000 +DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0 +DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT31_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT23_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT15_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE2_EVENT.VALUE=1 +DRIVER.HET.VAR.HET2_BIT11_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PIN_ENABLE.VALUE=0 +DRIVER.HET.VAR.HET1_CAP3_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET1_BIT24_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT16_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT5_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT27_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT19_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_EDGE6_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT24_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_BIT16_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_BIT2_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM6_DUTY_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE3_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE5_PIN_SELECT.VALUE=21 +DRIVER.HET.VAR.HET2_BIT21_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT13_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM7_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET1_BIT27_DOUT.VALUE=0 +DRIVER.HET.VAR.HET1_BIT19_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_CAP5_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET2_PWM4_ENA.VALUE=0 +DRIVER.HET.VAR.HET2_BIT8_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM1_POLARITY.VALUE=3 +DRIVER.HET.VAR.HET2_CAP2_PIN_SELECT.VALUE=4 +DRIVER.HET.VAR.HET2_BIT4_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM0_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=149888 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+DRIVER.I2C.VAR.I2C1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_FUN.VALUE=0 +DRIVER.I2C.VAR.I2C1_NACKINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_NACKINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_BAUDRATE.VALUE=100 +DRIVER.I2C.VAR.I2C1_AAS.VALUE=0 +DRIVER.I2C.VAR.I2C1_BCM.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_MSMODE.VALUE=1 +DRIVER.I2C.VAR.I2C2_STOPBITS.VALUE=2 +DRIVER.I2C.VAR.I2C1_BC.VALUE=8_BIT +DRIVER.I2C.VAR.I2C1_PORT_BIT1_FUN.VALUE=0 +DRIVER.I2C.VAR.I2C2_EVENPARITY.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICRRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C2_BASE.VALUE=0xFFF7D500 +DRIVER.I2C.VAR.I2C2_AASLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_AAS.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICCH.VALUE=37 +DRIVER.I2C.VAR.I2C2_BCM.VALUE=0 +DRIVER.I2C.VAR.I2C2_BC.VALUE=2_BIT +DRIVER.I2C.VAR.I2C1_MODCLK.VALUE=8 +DRIVER.I2C.VAR.I2C1_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICCL.VALUE=37 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_ADDRMODE.VALUE=7BIT_AMODE +DRIVER.I2C.VAR.I2C2_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C1_RXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C2_BC_VALUE.VALUE=0x0003 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C1_ICXRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICCH.VALUE=37 +DRIVER.I2C.VAR.I2C1_NACKINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICCL.VALUE=37 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C1_TXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C2_LENGTH.VALUE=8 +DRIVER.I2C.VAR.I2C1_EVENPARITY.VALUE=0 +DRIVER.I2C.VAR.I2C1_RM_ENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICRRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ALINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_PRESCALE.VALUE=8 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C1_SCDLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C2_TXRX_VALUE.VALUE=0 +DRIVER.I2C.VAR.I2C1_STPCND.VALUE=1 +DRIVER.I2C.VAR.I2C2_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C1_BAUDRATE.VALUE=100 +DRIVER.I2C.VAR.I2C2_STACND.VALUE=1 +DRIVER.I2C.VAR.I2C2_RXDMA.VALUE=0 +DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10 +DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00 +DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40 +DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0 +DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792 +DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00 +DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=300.0 +DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400 +DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0xA +DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1 +DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0 +DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=742500 +DRIVER.PINMUX.VAR.EQEP2A_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC4A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP5_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.EMIF_OUTPUT_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT" +DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_ETMDATA_08 | PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_E7_ETMDATA_10" +DRIVER.PINMUX.VAR.PINMUX20.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6" +DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_E6_ETMDATA_11 | PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_E12_ETMDATA_13 | PINMUX_BALL_E11_ETMDATA_14" +DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MIBSPI1NCS_0 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_MIBSPI1NCS_2" +DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_M15_ETMDATA_18" +DRIVER.PINMUX.VAR.ECAP3_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX30.VALUE="PINMUX_BALL_E18_N2HET1_08 | PINMUX_BALL_V7_N2HET1_09 | PINMUX_BALL_D19_N2HET1_10 | PINMUX_BALL_E3_N2HET1_11" +DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0" +DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21 | PINMUX_BALL_G5_ETMDATA_22" +DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX31.VALUE="PINMUX_BALL_B4_N2HET1_12 | PINMUX_BALL_N2_N2HET1_13 | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16" +DRIVER.PINMUX.VAR.PINMUX23.VALUE="PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_B2_MIBSPI3NCS_2 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA" +DRIVER.PINMUX.VAR.PINMUX15.VALUE="PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_L5_ETMDATA_24 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_N5_ETMDATA_26" +DRIVER.PINMUX.VAR.PINMUX32.VALUE="PINMUX_BALL_A13_N2HET1_17 | PINMUX_BALL_J1_N2HET1_18 | PINMUX_BALL_B13_N2HET1_19 | PINMUX_BALL_P2_N2HET1_20" +DRIVER.PINMUX.VAR.PINMUX24.VALUE="PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_E19_MIBSPI5NCS_0" +DRIVER.PINMUX.VAR.PINMUX16.VALUE="PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_R5_ETMDATA_28 | PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_R7_ETMDATA_30" +DRIVER.PINMUX.VAR.SIGNAL56_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL48_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX131_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_N2HET1_24" +DRIVER.PINMUX.VAR.PINMUX25.VALUE="PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MIBSPI5NENA" +DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_R8_ETMDATA_31 | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_R10_ETMTRACECLKOUT | PINMUX_BALL_R11_ETMTRACECTL" +DRIVER.PINMUX.VAR.SIGNAL56_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL48_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX131_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB6_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.EQEP2B_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_BALL_A14_N2HET1_26 | PINMUX_BALL_K19_N2HET1_28 | PINMUX_BALL_B11_N2HET1_30 | PINMUX_BALL_D8_N2HET2_01" +DRIVER.PINMUX.VAR.PINMUX26.VALUE="PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2 | PINMUX_BALL_G17_MIBSPI5SIMO_3" +DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2" +DRIVER.PINMUX.VAR.MUX131_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX35.VALUE="PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_N2HET2_12 | PINMUX_BALL_D2_N2HET2_13 | PINMUX_BALL_D1_N2HET2_14" +DRIVER.PINMUX.VAR.PINMUX27.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3" +DRIVER.PINMUX.VAR.PINMUX19.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6" +DRIVER.PINMUX.VAR.MUX131_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX36.VALUE="PINMUX_BALL_P4_N2HET2_19 | PINMUX_BALL_T5_N2HET2_20 | PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK" +DRIVER.PINMUX.VAR.PINMUX28.VALUE="PINMUX_BALL_K18_N2HET1_00 | PINMUX_BALL_V2_N2HET1_01 | PINMUX_BALL_W5_N2HET1_02 | PINMUX_BALL_U1_N2HET1_03" +DRIVER.PINMUX.VAR.MUX131_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX37.VALUE="PINMUX_BALL_E2_N2HET2_03 | PINMUX_BALL_N3_N2HET2_07" +DRIVER.PINMUX.VAR.PINMUX29.VALUE="PINMUX_BALL_B12_N2HET1_04 | PINMUX_BALL_V6_N2HET1_05 | PINMUX_BALL_W3_N2HET1_06 | PINMUX_BALL_T1_N2HET1_07" +DRIVER.PINMUX.VAR.MUX131_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX80.VALUE=SIGNAL_AD2EVT_T10 +DRIVER.PINMUX.VAR.SIGNAL41_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL33_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL25_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL17_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.TEMP2_ENABLE.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX81.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL41_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL33_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL25_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL17_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX90.VALUE="SIGNAL_MII_RX_DV_U6 | SIGNAL_MII_RX_ER_U5 | SIGNAL_MII_RXCLK_T4 | SIGNAL_MII_RXD_0_U4" +DRIVER.PINMUX.VAR.PINMUX82.VALUE=0 +DRIVER.PINMUX.VAR.MUX127_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX119_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_133_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_125_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_117_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_109_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX91.VALUE="SIGNAL_MII_RXD_1_T3 | SIGNAL_MII_RXD_2_U3 | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_U7" +DRIVER.PINMUX.VAR.PINMUX83.VALUE=SIGNAL_GIOA_0_A5 +DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX92.VALUE="SIGNAL_N2HET1_17_A13 | SIGNAL_N2HET1_19_B13 | SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4" +DRIVER.PINMUX.VAR.PINMUX84.VALUE="SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 | SIGNAL_GIOA_4_A6" +DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX93.VALUE="SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17" +DRIVER.PINMUX.VAR.PINMUX85.VALUE="SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 | SIGNAL_GIOB_0_M2" +DRIVER.PINMUX.VAR.MUX100_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB0_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA2_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX94.VALUE="SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 | SIGNAL_N2HET2_02_D7 | SIGNAL_N2HET2_03_E2" +DRIVER.PINMUX.VAR.PINMUX86.VALUE="SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_F2 | SIGNAL_GIOB_3_W10 | SIGNAL_GIOB_4_G1" +DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_110_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX95.VALUE="SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 | SIGNAL_N2HET2_06_D11 | SIGNAL_N2HET2_07_N3" +DRIVER.PINMUX.VAR.PINMUX87.VALUE="SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 | SIGNAL_MDIO_F4" +DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX96.VALUE="SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16" +DRIVER.PINMUX.VAR.PINMUX88.VALUE="SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9" +DRIVER.PINMUX.VAR.SIGNAL10_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX97.VALUE="SIGNAL_N2HET2_12_D3 | SIGNAL_N2HET2_13_D2 | SIGNAL_N2HET2_14_D1 | SIGNAL_N2HET2_15_K4" +DRIVER.PINMUX.VAR.PINMUX89.VALUE="SIGNAL_MII_COL_W4 | SIGNAL_MII_CRS_V4" +DRIVER.PINMUX.VAR.SIGNAL10_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX98.VALUE="SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 | SIGNAL_N2HET2_20_T5 | SIGNAL_N2HET2_22_T7" +DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX99.VALUE="SIGNAL_nTZ1_1_N19 | SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3" +DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1A_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1I_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_SOC3A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.TEMP3_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX120_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX112_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM3_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA_DISABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL4_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL4_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL61_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL53_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL45_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL37_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL29_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP3_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.MUX129_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TBCLK_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX129_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL30_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL22_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL14_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.I2C1.VALUE=0 +DRIVER.PINMUX.VAR.I2C2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL47_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL39_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX130_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL47_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL39_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL8_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1A_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL1_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GIOA0_DMA.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL32_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL24_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL16_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL32_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL24_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL16_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.GIOB5_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA7_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PIN_MUX_131_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_123_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_115_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION5.VALUE=0 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+DRIVER.PINMUX.VAR.PIN_MUX_93_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_85_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_77_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_69_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_2_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX40_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL7_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX40_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL7_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX40_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX32_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX24_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX16_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL59_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_70_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_62_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_54_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_46_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_38_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MII.VALUE=0 +DRIVER.PINMUX.VAR.SCI2.VALUE=0 +DRIVER.PINMUX.VAR.GIOA_DISABLE.VALUE=0 +DRIVER.PINMUX.VAR.SCI3.VALUE=0 +DRIVER.PINMUX.VAR.GATE_EMIF_CLK_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SCI4.VALUE=0 +DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL60_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL52_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL44_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL36_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL28_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP2_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SYNC_ENABLE.VALUE=0 +DRIVER.PINMUX.VAR.GIOB2_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA4_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX93_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL21_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL13_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_EPWM1SYNCI.VALUE=ASYNC +DRIVER.PINMUX.VAR.ETPWM6_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.SIGNAL58_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX133_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL58_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC1A.VALUE=1 +DRIVER.PINMUX.VAR.SCI.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC2A.VALUE=1 +DRIVER.PINMUX.VAR.MUX133_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL7_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC3A.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL51_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL43_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL35_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL27_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL19_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX110_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC4A.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL51_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL43_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL35_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL27_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL19_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX128_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_129_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC5A.VALUE=1 +DRIVER.PINMUX.VAR.ETPWM.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1S_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC6A.VALUE=1 +DRIVER.PINMUX.VAR.MUX110_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_130_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_122_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_114_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC7A.VALUE=1 +DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL20_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL12_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL20_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL12_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ECAP1_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_TZ3_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1B_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_SOC5A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.ETPWM6_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX121_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX113_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX105_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL6_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GIOB7_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ECAP6_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SIGNAL50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SPI2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL49_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX132_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL49_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.TEMP1_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SPI4.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.RMII.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_D4_EMIF_ADDR_00 | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06" +DRIVER.PINMUX.VAR.MUX132_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10" +DRIVER.PINMUX.VAR.MUX132_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB1_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA3_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14" +DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18" +DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C17_EMIF_ADDR_21" +DRIVER.PINMUX.VAR.SIGNAL50_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL42_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL34_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL26_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL18_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX5.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL50_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL42_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL34_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL26_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL18_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX6.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_127_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_119_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_A.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX7.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX8.VALUE=PINMUX_BALL_D16_EMIF_BA_1 +DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_L17_EMIF_nCS_2" +DRIVER.PINMUX.VAR.MUX101_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_120_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_112_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TZ1_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX132_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM +DRIVER.CRC.VAR.CRC2_CH2_WDTO.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_BASE.VALUE=0xFE000000 +DRIVER.CRC.VAR.CRC1_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400 +DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_BASE.VALUE=0xFB000000 +DRIVER.CRC.VAR.CRC1_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_BCTO.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0 +DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_BCTO.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC2_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_CVH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_RES_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_CVL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC1_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC1_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_CVH.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC2_CH2_CVL.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_PCP.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_SCP.VALUE=0 +DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC2_CH2_PCP.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC2_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC2_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC2_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH2_SCP.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC2_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC2_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT +DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH2_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC1_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.CRC1_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT +DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_WDTO.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC2_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.EMAC.VAR.EMAC_PHY_CUSTOM.VALUE=0 +DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF +DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800 +DRIVER.EMAC.VAR.EMAC_PHY_DP83640.VALUE=1 +DRIVER.EMAC.VAR.EMAC_LOOPBACK_ENA.VALUE=0 +DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900 +DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000 +DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF +DRIVER.EMAC.VAR.EMAC_TRANSMIT_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHY_TLK111.VALUE=0 +DRIVER.EMAC.VAR.EMAC_CHANNELNUMBER.VALUE=0 +DRIVER.EMAC.VAR.EMAC_RX_PBUF_ALLOC.VALUE=10 +DRIVER.EMAC.VAR.EMAC_UNICAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_FULL_DUPLEX_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=1 +DRIVER.EMAC.VAR.EMAC_MII_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000 +DRIVER.EMAC.VAR.EMAC_BROADCAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_RECEIVE_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0 +DRIVER.EMIF.VAR.EMIF_AVAILABLE.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=213 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=213 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=427 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_INIT_TIME.VALUE=200 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=1605 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_CLK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001 +DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=427 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0 +DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0 +DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0 +DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1 +DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1 +DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM +DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0 +DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000 +DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200 +DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM3_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM6_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP5_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP5_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP2_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP6_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_BASE.VALUE=0xFCF79300 +DRIVER.ECAP.VAR.ECAP4_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP5_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP4_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_BASE.VALUE=0xFCF79400 +DRIVER.ECAP.VAR.ECAP2_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP6_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP3_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP3_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP3_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_BASE.VALUE=0xFCF79500 +DRIVER.ECAP.VAR.ECAP5_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP4_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_BASE.VALUE=0xFCF79600 +DRIVER.ECAP.VAR.ECAP6_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP4_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_BASE.VALUE=0xFCF79700 +DRIVER.ECAP.VAR.ECAP3_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_BASE.VALUE=0xFCF79800 +DRIVER.ECAP.VAR.ECAP6_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT4.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP2_QUPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_BASE.VALUE=0xFCF79900 +DRIVER.EQEP.VAR.EQEP1_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_BASE.VALUE=0xFCF79A00 +DRIVER.EQEP.VAR.EQEP1_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP2_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP1_PCSPW.VALUE=0x000 +DRIVER.EQEP.VAR.EQEP1_POSCMP.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP1_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP2_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP2_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP2_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCSPW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.EQEP.VAR.EQEP2_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP1_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP1_WDPRD.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP1_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSCMP.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QUPRD.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP2_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_NUMBER.VALUE=11 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_END.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_START_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_START.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_START.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_START.VALUE=8 +DRIVER.FEE.VAR.FEE_VS29_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VS30_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS22_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS14_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_END.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VS7_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_READ_CYCLE_COUNT.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_NUMBER_OF_VIRTUAL_SECTORS.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX15_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_CRC_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_START.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_START.VALUE=17 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_NUMBER.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_END.VALUE=19 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_END.VALUE=11 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_NUMBER.VALUE=3 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_NUMBER.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_NUMBER.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_NUMBER.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_SECTORS_EEP1.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_END.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_END.VALUE=12 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_START.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VS27_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS19_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS20_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS12_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_DRIVER_INDEX.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_END.VALUE=29 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_END.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_END.VALUE=13 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX9_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX13_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX2_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_START.VALUE=29 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_START.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_START.VALUE=13 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_NUMBER.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_NUMBER_OF_EEPS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_NUMBER.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_END.VALUE=30 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_NUMBER.VALUE=29 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_END.VALUE=22 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_END.VALUE=14 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_NUMBER.VALUE=30 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_NUMBER.VALUE=22 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_NUMBER.VALUE=14 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_DEVICE_INDEX.VALUE=0 +DRIVER.FEE.VAR.FEE_PAGE_OVERHEAD.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_NUMBER.VALUE=3 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MAJOR_VERSION.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_START.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_START.VALUE=18 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_END.VALUE=31 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_END.VALUE=23 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_END.VALUE=15 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_END.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_START.VALUE=0 +DRIVER.FEE.VAR.FEE_VS33_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS25_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS17_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_SECTOR_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VS10_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUALPAGE_SIZE.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS3_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX7_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_END.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_END.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_END.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_END.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX11_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_WRITECOUNTER_SAVE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VS_INDEX.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_NUMBER.VALUE=15 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_PATCH_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_START.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_START.VALUE=5 +DRIVER.FEE.VAR.FEE_JOBERROR_NOTIFICATION.VALUE=JobErrorNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_NUMBER.VALUE=6 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_NUMBER.VALUE=27 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_NUMBER.VALUE=19 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_END.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_NUMBER.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_END.VALUE=17 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_NUMBER.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_NUMBER.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_END.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_SIZE.VALUE=0x10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_TOTAL_BLOCKS_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_START.VALUE=30 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_START.VALUE=22 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_START.VALUE=14 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_SIZE.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX.VALUE=1 +DRIVER.FEE.VAR.FEE_VS31_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS23_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS15_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_END.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_END.VALUE=18 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_END.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VS8_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_MAXIMUM_BLOCKING_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_NO_OF_UNCONFIGURED_BLOCKS_TO_COPY.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_BANK_NUM.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_START.VALUE=27 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_END.VALUE=27 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_END.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_START.VALUE=1 +DRIVER.FEE.VAR.FEE_SECTOR_OVERHEAD.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_NUMBER.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_NUMBER.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_NUMBER.VALUE=17 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MINOR_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_NUMBER.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_NUMBER.VALUE=6 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_END.VALUE=28 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_END.VALUE=5 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_START.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_START.VALUE=6 +DRIVER.FEE.VAR.FEE_VS28_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VERSIONINFO_API.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DATASETS.VALUE=1 +DRIVER.FEE.VAR.MAX_BLOCK_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS21_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS13_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_WRITE_CYCLES.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_OFFSET.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_END.VALUE=6 +DRIVER.FEE.VAR.FEE_NUMBER_OF_BLOCKS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_BANK.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX14_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX3_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_NUMBER_OF_EIGHTBYTEWRITES.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_START.VALUE=31 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_START.VALUE=23 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_START.VALUE=15 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_NUMBER.VALUE=11 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_NUMBER.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_END.VALUE=7 +DRIVER.FEE.VAR.FEE_END_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_NUMBER.VALUE=31 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_NUMBER.VALUE=23 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_NUMBER.VALUE=15 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_HANDLING.VALUE=TI_Fee_None +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_DEVERROR_DETECT.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_START.VALUE=28 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_END.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_START.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VS26_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS18_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS11_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX8_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_MAX_NUMBER_OF_LINKS.VALUE=256 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX12_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_DATASELECT_BITS.VALUE=0 +DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=150.000 +DRIVER.FEE.VAR.FEE_TOTAL_SECTORS.VALUE=32 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_NUMBER.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_START.VALUE=19 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_START.VALUE=11 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_START.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_NUMBER.VALUE=28 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_NUMBER.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_NUMBER.VALUE=9 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_START.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_START.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_START.VALUE=16 +DRIVER.FEE.VAR.FEE_JOBEND_NOTIFICATION.VALUE=JobEndNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VS32_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS24_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_ENABLE_ECC.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_OVERHEAD.VALUE=24 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VS9_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS2_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX10_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_NUMBER.VALUE=14 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_START.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_CHECK_BANK7_ACCESS.VALUE=STD_OFF +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_POLLING_MODE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_NUMBER.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_NUMBER.VALUE=18 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_SIZE.VALUE=0 +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_1.VALUE=0xFFFFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_0.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_0.VALUE=0xFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_1.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_1.VALUE=0xD2 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_2.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_3.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_0.VALUE=0xFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_1.VALUE=0xD2 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_1.VALUE=0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg new file mode 100644 index 00000000000..b26c9d9f031 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg @@ -0,0 +1,1041 @@ + + + + RM57Lx + RM57L843ZWT_FREERTOS + FreeRTOS.dil + gcc + + + 04.07.01 + + + + + + + + + + + + + + + + + + + + + + + + + hal_stdtypes.h + include\hal_stdtypes.h + + + sys_common.h + include\sys_common.h + + + reg_system.h + include\reg_system.h + + + reg_flash.h + include\reg_flash.h + + + reg_l2ramw.h + include\reg_l2ramw.h + + + reg_vim.h + include\reg_vim.h + + + reg_pbist.h + include\reg_pbist.h + + + reg_stc.h + include\reg_stc.h + + + reg_efc.h + include\reg_efc.h + + + reg_pcr.h + include\reg_pcr.h + + + reg_pmm.h + include\reg_pmm.h + + + reg_dma.h + include\reg_dma.h + + + reg_ccmr5.h + include\reg_ccmr5.h + + + sys_core.h + include\sys_core.h + + + system.h + include\system.h + + + sys_vim.h + include\sys_vim.h + + + sys_mpu.h + include\sys_mpu.h + + + sys_pmu.h + include\sys_pmu.h + + + sys_pcr.h + include\sys_pcr.h + + + sys_pmm.h + include\sys_pmm.h + + + sys_dma.h + include\sys_dma.h + + + sys_core.s + source\sys_core.s + + + sys_intvecs.s + source\sys_intvecs.s + + + sys_mpu.s + source\sys_mpu.s + + + sys_pmu.s + source\sys_pmu.s + + + sys_pcr.c + source\sys_pcr.c + + + sys_pmm.c + source\sys_pmm.c + + + sys_dma.c + source\sys_dma.c + + + system.c + source\system.c + + + sys_phantom.c + source\sys_phantom.c + + + sys_startup.c + source\sys_startup.c + + + sys_vim.c + source\sys_vim.c + + + sys_main.c + source\sys_main.c + + + notification.c + source\notification.c + + + sys_link.ld + source\sys_link.ld + + + reg_epc.h + include\reg_epc.h + + + reg_nmpu.h + include\reg_nmpu.h + + + reg_scm.h + include\reg_scm.h + + + reg_sdcmmr.h + include\reg_sdcmmr.h + + + epc.h + include\epc.h + + + epc.c + source\epc.c + + + nmpu.h + include\nmpu.h + + + nmpu.c + source\nmpu.c + + + errata.h + include\errata.h + + + errata.c + source\errata.c + + + Test.h + + + errata_SSWF021_45.h + include\errata_SSWF021_45.h + + + errata_SSWF021_45_defs.h + include\errata_SSWF021_45_defs.h + + + errata_SSWF021_45.c + source\errata_SSWF021_45.c + + + os_projdefs.h + + + FreeRTOSConfig.h + + + os_portmacro.h + + + os_mpu_wrappers.h + + + os_portable.h + + + FreeRTOS.h + + + os_list.h + + + os_queue.h + + + os_semphr.h + + + os_croutine.h + + + os_StackMacros.h + + + os_task.h + + + os_timer.h + + + os_port.c + + + os_portasm.s + + + os_tasks.c + + + os_queue.c + + + os_list.c + + + os_croutine.c + + + os_timer.c + + + os_mpu_wrappers.c + + + os_heap.c + + + os_event_groups.c + + + os_event_groups.h + + + reg_pinmux.h + + + pinmux.h + + + pinmux.c + + + reg_gio.h + + + gio.h + + + gio.c + + + reg_esm.h + + + esm.h + + + esm.c + + + reg_sci.h + + + sci.h + + + sci.c + + + reg_lin.h + + + lin.h + + + lin.c + + + reg_mibspi.h + + + mibspi.h + + + mibspi.c + + + reg_spi.h + + + spi.h + + + + reg_can.h + + + can.h + + + can.c + + + reg_adc.h + + + adc.h + + + adc.c + + + + + + + + + std_nhet.h + + + reg_het.h + + + het.h + + + het.c + + + reg_htu.h + + + htu.h + + + + + + + + + reg_i2c.h + + + i2c.h + + + i2c.c + + + emac.h + + + hw_emac.h + + + hw_emac_ctrl.h + + + hw_mdio.h + + + hw_reg_access.h + + + mdio.h + + + emac.c + + + mdio.c + + + phy_dp83640.c + + + phy_dp83640.h + + + phy_tlk111.c + + + phy_tlk111.h + + + emac_phyConfig.h + + + reg_dcc.h + + + dcc.h + + + dcc.c + + + reg_rtp.h + + + rtp.h + + + + reg_dmm.h + + + dmm.h + + + + reg_emif.h + + + emif.h + + + emif.c + + + reg_pom.h + + + pom.h + + + pom.c + + + reg_crc.h + + + crc.h + + + crc.c + + + reg_etpwm.h + + + etpwm.h + + + etpwm.c + + + reg_ecap.h + + + ecap.h + + + ecap.c + + + reg_eqep.h + + + eqep.h + + + eqep.c + + + Device_RM57.h + + + Device_header.h + + + Device_types.h + + + ti_fee_cfg.h + + + MemMap.h + + + ti_fee_types.h + + + ti_fee.h + + + fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + include\os_projdefs.h + + + include\FreeRTOSConfig.h + + + include\os_portmacro.h + + + include\os_mpu_wrappers.h + + + include\os_portable.h + + + include\FreeRTOS.h + + + include\os_list.h + + + include\os_queue.h + + + include\os_semphr.h + + + include\os_croutine.h + + + include\os_StackMacros.h + + + include\os_task.h + + + include\os_timer.h + + + source\os_port.c + + + source\os_portasm.s + + + source\os_tasks.c + + + source\os_queue.c + + + source\os_list.c + + + source\os_croutine.c + + + source\os_timer.c + + + source\os_mpu_wrappers.c + + + source\os_heap.c + + + source\os_event_groups.c + + + include\os_event_groups.h + + + + + + + include\reg_pinmux.h + + + include\pinmux.h + + + source\pinmux.c + + + + + + + include\reg_gio.h + + + include\gio.h + + + source\gio.c + + + + + + + include\reg_esm.h + + + include\esm.h + + + source\esm.c + + + + + + + include\reg_sci.h + + + include\sci.h + + + source\sci.c + + + + + + + include\reg_lin.h + + + include\lin.h + + + source\lin.c + + + + + + + include\reg_mibspi.h + + + include\mibspi.h + + + source\mibspi.c + + + + + + + include\reg_spi.h + + + include\spi.h + + + + + + + + + + include\reg_can.h + + + include\can.h + + + source\can.c + + + + + + + include\reg_adc.h + + + include\adc.h + + + source\adc.c + + + + + + + include\std_nhet.h + + + include\reg_het.h + + + include\het.h + + + source\het.c + + + include\reg_htu.h + + + include\htu.h + + + + + + + include\reg_i2c.h + + + include\i2c.h + + + source\i2c.c + + + + + + + include\emac.h + + + include\hw_emac.h + + + include\hw_emac_ctrl.h + + + include\hw_mdio.h + + + include\hw_reg_access.h + + + include\mdio.h + + + source\emac.c + + + source\mdio.c + + + source\phy_dp83640.c + + + include\phy_dp83640.h + + + source\phy_tlk111.c + + + include\phy_tlk111.h + + + include\emac_phyConfig.h + + + + + + + include\reg_dcc.h + + + include\dcc.h + + + source\dcc.c + + + + + + + include\reg_rtp.h + + + include\rtp.h + + + + + + + + + + include\reg_dmm.h + + + include\dmm.h + + + + + + + + + + include\reg_emif.h + + + include\emif.h + + + source\emif.c + + + + + + + include\reg_pom.h + + + include\pom.h + + + source\pom.c + + + + + + + include\reg_crc.h + + + include\crc.h + + + source\crc.c + + + + + + + include\reg_etpwm.h + + + include\etpwm.h + + + source\etpwm.c + + + + + + + include\reg_ecap.h + + + include\ecap.h + + + source\ecap.c + + + + + + + include\reg_eqep.h + + + include\eqep.h + + + source\eqep.c + + + + + + + include\Device_RM57.h + + + include\Device_header.h + + + include\Device_types.h + + + include\ti_fee_cfg.h + + + include\MemMap.h + + + include\ti_fee_types.h + + + include\ti_fee.h + + + include\fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml new file mode 100644 index 00000000000..b8ddc17d97a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h new file mode 100644 index 00000000000..b8d0e928377 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h @@ -0,0 +1,114 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_RM57.c + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the number of sectors. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_RM57_H + #define DEVICE_RM57_H + + /** @def DEVICE_CONFIGURATION_VERSION + * @brief Device Configuration Version + * + * @note Indicates the current version of the device files + */ + #define DEVICE_CONFIGURATION_VERSION \ + 0U /* Indicates the current version of the device files */ + + /** @def DEVICE_NUMBER_OF_FLASH_BANKS + * @brief Number of Flash Banks + * + * @note Defines the number of Flash Banks on the device + */ + #define DEVICE_NUMBER_OF_FLASH_BANKS \ + 1U /* Defines the number of Flash Banks on the device */ + + /** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS + * @brief Maximum number of Sectors + * + * @note Defines the maxium number of sectors in all banks + */ + #define DEVICE_BANK_MAX_NUMBER_OF_SECTORS \ + 32U /* Defines the maxium number of sectors in all banks */ + + /** @def DEVICE_BANK1_NUMBER_OF_SECTORS + * @brief Number of Sectors + * + * @note Defines the number of sectors in bank1 + */ + #define DEVICE_BANK1_NUMBER_OF_SECTORS \ + 32U /* Defines the number of sectors in bank1 */ + + /** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS + * @brief Number of Sectors + * + * @note Defines the number of Read Cycle Thresholds + */ + #define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS \ + 4U /* Defines the number of Read Cycle Thresholds */ + + /* Include Files */ + #ifndef _PLATFORM_TYPES_H_ + #define _PLATFORM_TYPES_H_ + #endif + #ifndef _L2FMC + #define _L2FMC + #endif + #include "F021.h" + #include "hal_stdtypes.h" + #include "Device_types.h" + +#endif /* DEVICE_RM57_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h new file mode 100644 index 00000000000..99b1e37ae0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h @@ -0,0 +1,65 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_header.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file includes the header file. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef TI_FEE_DEVICEHEADER_H +#define TI_FEE_DEVICEHEADER_H + +/* Uncomment the appropriate include file depending on the device you are using */ +#include "Device_RM57.h" + +/* End of file */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h new file mode 100644 index 00000000000..96add2784e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h @@ -0,0 +1,133 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the structures. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_TYPES_H + #define DEVICE_TYPES_H + + #include "hal_stdtypes.h" + +/* Enum to describe the type of error handling on the device */ +typedef enum +{ + Device_ErrorHandlingNone, /* Device has no error handling */ + Device_ErrorHandlingParity, /* Device has parity error handling */ + Device_ErrorHandlingEcc /* Device has ECC error handling */ +} Device_FlashErrorCorrectionProcessType; + +/* Enum to describe the ARM core on the device*/ +typedef enum +{ + Device_CoreNone, /* To indicate that the device has a single core */ + Device_Arm7, /* To indicate that the device has a ARM7 core */ + Device_CortexR4, /* To indicate that the device has a CortexR4 core */ + Device_CortexM3 /* To indicate that the device has a CortexM3 core */ +} Device_ArmCoreType; + +/* Structure defines an individual sector within a bank */ +typedef struct +{ + Fapi_FlashSectorType Device_Sector; /* Sector number */ + uint32 Device_SectorStartAddress; /* Starting address of the sector */ + uint32 Device_SectorLength; /* Length of the sector */ + uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */ + uint32 Device_EccAddress; + uint32 Device_EccLength; +} Device_SectorType; + +/* Structure defines an individual bank */ +typedef struct +{ + Fapi_FmcRegistersType * Device_ControlRegister; + Fapi_FlashBankType Device_Core; /* Core number for this bank */ + Device_SectorType Device_SectorInfo[ DEVICE_BANK_MAX_NUMBER_OF_SECTORS ]; /* Array of + the + Sectors + within a + bank */ +} Device_BankType; + +/* Structure defines the Flash structure of the device */ +typedef struct +{ + uint8 Device_DeviceName[ 12 ]; /* Device name */ + uint32 Device_EngineeringId; /* Device Engineering ID */ + Device_FlashErrorCorrectionProcessType + Device_FlashErrorHandlingProcessInfo; /* Indicates + which + type + of bit + Error + handling + is on + the + device + */ + Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device + */ + boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash + interrupts for processing Flash */ + uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS + */ + uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS + */ + Device_BankType Device_BankInfo[ DEVICE_NUMBER_OF_FLASH_BANKS ]; /* Array of Banks on + the device */ +} Device_FlashType; + +#endif /* DEVICE_TYPES_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h new file mode 100644 index 00000000000..8781cbf7be2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h @@ -0,0 +1,39 @@ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MEM_MAP_H__ +#define __MEM_MAP_H__ + +#endif /* __MEM_MAP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h new file mode 100644 index 00000000000..b9d8118372d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h @@ -0,0 +1,344 @@ +/** @file adc.h + * @brief ADC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +#include "reg_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ADC General Definitions */ + +/** @def adcGROUP0 + * @brief Alias name for ADC event group + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP0 0U + +/** @def adcGROUP1 + * @brief Alias name for ADC group 1 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP1 1U + +/** @def adcGROUP2 + * @brief Alias name for ADC group 2 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP2 2U + +/** @def ADC_12_BIT_MODE + * @brief Alias name for ADC 12-bit mode of operation + */ +#define ADC_12_BIT_MODE 0x80000000U + +/** @enum adcResolution + * @brief Alias names for data resolution + * This enumeration is used to provide alias names for the data resolution: + * - 12 bit resolution + * - 10 bit resolution + * - 8 bit resolution + */ + +enum adcResolution +{ + ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */ + ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */ + ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */ +}; + +/** @enum adcFiFoStatus + * @brief Alias names for FiFo status + * This enumeration is used to provide alias names for the current FiFo states: + * - FiFo is not full + * - FiFo is full + * - FiFo overflow occurred + */ + +enum adcFiFoStatus +{ + ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */ + ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */ + ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */ +}; + +/** @enum adcConversionStatus + * @brief Alias names for conversion status + * This enumeration is used to provide alias names for the current conversion states: + * - Conversion is not finished + * - Conversion is finished + */ + +enum adcConversionStatus +{ + ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished + */ + ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */ +}; + +/** @enum adc1HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc1HwTriggerSource +{ + ADC1_EVENT = 0U, /**< Alias for event pin */ + ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + + ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/** @enum adc2HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc2HwTriggerSource +{ + ADC2_EVENT = 0U, /**< Alias for event pin */ + ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct adcData + * @brief ADC Conversion data structure + * + * This type is used to pass adc conversion data. + */ +/** @typedef adcData_t + * @brief ADC Data Type Definition + */ +typedef struct adcData +{ + uint32 id; /**< Channel/Pin Id */ + uint16 value; /**< Conversion data value */ +} adcData_t; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +typedef struct adc_config_reg +{ + uint32 CONFIG_OPMODECR; + uint32 CONFIG_CLOCKCR; + uint32 CONFIG_GxMODECR[ 3U ]; + uint32 CONFIG_G0SRC; + uint32 CONFIG_G1SRC; + uint32 CONFIG_G2SRC; + uint32 CONFIG_BNDCR; + uint32 CONFIG_BNDEND; + uint32 CONFIG_G0SAMP; + uint32 CONFIG_G1SAMP; + uint32 CONFIG_G2SAMP; + uint32 CONFIG_G0SAMPDISEN; + uint32 CONFIG_G1SAMPDISEN; + uint32 CONFIG_G2SAMPDISEN; + uint32 CONFIG_PARCR; +} adc_config_reg_t; + +#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC1_CLOCKCR_CONFIGVALUE ( 7U ) + +#define ADC1_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC1_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC1_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC1_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) + +#define ADC1_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC1_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC1_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC1_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC1_PARCR_CONFIGVALUE ( 0x00000005U ) + +#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC2_CLOCKCR_CONFIGVALUE ( 7U ) + +#define ADC2_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC2_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC2_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC2_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) + +#define ADC2_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC2_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC2_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC2_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC2_PARCR_CONFIGVALUE ( 0x00000005U ) + +/** + * @defgroup ADC ADC + * @brief Analog To Digital Converter Module. + * + * The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit + *resolution + * + * Related Files + * - reg_adc.h + * - adc.h + * - adc.c + * @addtogroup ADC + * @{ + */ + +/* ADC Interface Functions */ + +void adcInit( void ); +void adcStartConversion( adcBASE_t * adc, uint32 group ); +void adcStopConversion( adcBASE_t * adc, uint32 group ); +void adcResetFiFo( adcBASE_t * adc, uint32 group ); +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ); +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ); +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ); +void adcEnableNotification( adcBASE_t * adc, uint32 group ); +void adcDisableNotification( adcBASE_t * adc, uint32 group ); +void adcCalibration( adcBASE_t * adc ); +uint32 adcMidPointCalibration( adcBASE_t * adc ); +void adcSetEVTPin( adcBASE_t * adc, uint32 value ); +uint32 adcGetEVTPin( adcBASE_t * adc ); + +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void adcNotification(adcBASE_t *adc, uint32 group) + * @brief Group notification + * @param[in] adc Pointer to ADC node: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group number of ADC node: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * @note This function has to be provide by the user. + */ +void adcNotification( adcBASE_t * adc, uint32 group ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h new file mode 100644 index 00000000000..d1c122e6712 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h @@ -0,0 +1,926 @@ +/** @file can.h + * @brief CAN Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CAN_H__ +#define __CAN_H__ + +#include "reg_can.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CAN General Definitions */ + +/** @def canLEVEL_ACTIVE + * @brief Alias name for CAN error operation level active (Error counter 0-95) + */ +#define canLEVEL_ACTIVE 0x00U + +/** @def canLEVEL_WARNING + * @brief Alias name for CAN error operation level warning (Error counter 96-127) + */ +#define canLEVEL_WARNING 0x40U + +/** @def canLEVEL_PASSIVE + * @brief Alias name for CAN error operation level passive (Error counter 128-255) + */ +#define canLEVEL_PASSIVE 0x20U + +/** @def canLEVEL_BUS_OFF + * @brief Alias name for CAN error operation level bus off (Error counter 256) + */ +#define canLEVEL_BUS_OFF 0x80U + +/** @def canLEVEL_PARITY_ERR + * @brief Alias name for CAN Parity error (Error counter 256-511) + */ +#define canLEVEL_PARITY_ERR 0x100U + +/** @def canLEVEL_TxOK + * @brief Alias name for CAN Sucessful Transmission + */ +#define canLEVEL_TxOK 0x08U + +/** @def canLEVEL_RxOK + * @brief Alias name for CAN Sucessful Reception + */ +#define canLEVEL_RxOK 0x10U + +/** @def canLEVEL_WakeUpPnd + * @brief Alias name for CAN Initiated a WakeUp to system + */ +#define canLEVEL_WakeUpPnd 0x200U + +/** @def canLEVEL_PDA + * @brief Alias name for CAN entered low power mode successfully. + */ +#define canLEVEL_PDA 0x400U + +/** @def canERROR_NO + * @brief Alias name for no CAN error occurred + */ +#define canERROR_OK 0U + +/** @def canERROR_STUFF + * @brief Alias name for CAN stuff error an RX message + */ +#define canERROR_STUFF 1U + +/** @def canERROR_FORMAT + * @brief Alias name for CAN form/format error an RX message + */ +#define canERROR_FORMAT 2U + +/** @def canERROR_ACKNOWLEDGE + * @brief Alias name for CAN TX message wasn't acknowledged + */ +#define canERROR_ACKNOWLEDGE 3U + +/** @def canERROR_BIT1 + * @brief Alias name for CAN TX message sending recessive level but monitoring dominant + */ +#define canERROR_BIT1 4U + +/** @def canERROR_BIT0 + * @brief Alias name for CAN TX message sending dominant level but monitoring recessive + */ +#define canERROR_BIT0 5U + +/** @def canERROR_CRC + * @brief Alias name for CAN RX message received wrong CRC + */ +#define canERROR_CRC 6U + +/** @def canERROR_NO + * @brief Alias name for CAN no message has send or received since last call of + * CANGetLastError + */ +#define canERROR_NO 7U + +/** @def canMESSAGE_BOX1 + * @brief Alias name for CAN message box 1 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX1 1U + +/** @def canMESSAGE_BOX2 + * @brief Alias name for CAN message box 2 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX2 2U + +/** @def canMESSAGE_BOX3 + * @brief Alias name for CAN message box 3 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX3 3U + +/** @def canMESSAGE_BOX4 + * @brief Alias name for CAN message box 4 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX4 4U + +/** @def canMESSAGE_BOX5 + * @brief Alias name for CAN message box 5 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX5 5U + +/** @def canMESSAGE_BOX6 + * @brief Alias name for CAN message box 6 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX6 6U + +/** @def canMESSAGE_BOX7 + * @brief Alias name for CAN message box 7 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX7 7U + +/** @def canMESSAGE_BOX8 + * @brief Alias name for CAN message box 8 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX8 8U + +/** @def canMESSAGE_BOX9 + * @brief Alias name for CAN message box 9 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX9 9U + +/** @def canMESSAGE_BOX10 + * @brief Alias name for CAN message box 10 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX10 10U + +/** @def canMESSAGE_BOX11 + * @brief Alias name for CAN message box 11 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX11 11U + +/** @def canMESSAGE_BOX12 + * @brief Alias name for CAN message box 12 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX12 12U + +/** @def canMESSAGE_BOX13 + * @brief Alias name for CAN message box 13 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX13 13U + +/** @def canMESSAGE_BOX14 + * @brief Alias name for CAN message box 14 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX14 14U + +/** @def canMESSAGE_BOX15 + * @brief Alias name for CAN message box 15 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX15 15U + +/** @def canMESSAGE_BOX16 + * @brief Alias name for CAN message box 16 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX16 16U + +/** @def canMESSAGE_BOX17 + * @brief Alias name for CAN message box 17 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX17 17U + +/** @def canMESSAGE_BOX18 + * @brief Alias name for CAN message box 18 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX18 18U + +/** @def canMESSAGE_BOX19 + * @brief Alias name for CAN message box 19 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX19 19U + +/** @def canMESSAGE_BOX20 + * @brief Alias name for CAN message box 20 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX20 20U + +/** @def canMESSAGE_BOX21 + * @brief Alias name for CAN message box 21 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX21 21U + +/** @def canMESSAGE_BOX22 + * @brief Alias name for CAN message box 22 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX22 22U + +/** @def canMESSAGE_BOX23 + * @brief Alias name for CAN message box 23 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX23 23U + +/** @def canMESSAGE_BOX24 + * @brief Alias name for CAN message box 24 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX24 24U + +/** @def canMESSAGE_BOX25 + * @brief Alias name for CAN message box 25 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX25 25U + +/** @def canMESSAGE_BOX26 + * @brief Alias name for CAN message box 26 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX26 26U + +/** @def canMESSAGE_BOX27 + * @brief Alias name for CAN message box 27 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX27 27U + +/** @def canMESSAGE_BOX28 + * @brief Alias name for CAN message box 28 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX28 28U + +/** @def canMESSAGE_BOX29 + * @brief Alias name for CAN message box 29 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX29 29U + +/** @def canMESSAGE_BOX30 + * @brief Alias name for CAN message box 30 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX30 30U + +/** @def canMESSAGE_BOX31 + * @brief Alias name for CAN message box 31 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX31 31U + +/** @def canMESSAGE_BOX32 + * @brief Alias name for CAN message box 32 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX32 32U + +/** @def canMESSAGE_BOX33 + * @brief Alias name for CAN message box 33 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX33 33U + +/** @def canMESSAGE_BOX34 + * @brief Alias name for CAN message box 34 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX34 34U + +/** @def canMESSAGE_BOX35 + * @brief Alias name for CAN message box 35 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX35 35U + +/** @def canMESSAGE_BOX36 + * @brief Alias name for CAN message box 36 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX36 36U + +/** @def canMESSAGE_BOX37 + * @brief Alias name for CAN message box 37 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX37 37U + +/** @def canMESSAGE_BOX38 + * @brief Alias name for CAN message box 38 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX38 38U + +/** @def canMESSAGE_BOX39 + * @brief Alias name for CAN message box 39 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX39 39U + +/** @def canMESSAGE_BOX40 + * @brief Alias name for CAN message box 40 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX40 40U + +/** @def canMESSAGE_BOX41 + * @brief Alias name for CAN message box 41 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX41 41U + +/** @def canMESSAGE_BOX42 + * @brief Alias name for CAN message box 42 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX42 42U + +/** @def canMESSAGE_BOX43 + * @brief Alias name for CAN message box 43 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX43 43U + +/** @def canMESSAGE_BOX44 + * @brief Alias name for CAN message box 44 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX44 44U + +/** @def canMESSAGE_BOX45 + * @brief Alias name for CAN message box 45 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX45 45U + +/** @def canMESSAGE_BOX46 + * @brief Alias name for CAN message box 46 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX46 46U + +/** @def canMESSAGE_BOX47 + * @brief Alias name for CAN message box 47 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX47 47U + +/** @def canMESSAGE_BOX48 + * @brief Alias name for CAN message box 48 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX48 48U + +/** @def canMESSAGE_BOX49 + * @brief Alias name for CAN message box 49 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX49 49U + +/** @def canMESSAGE_BOX50 + * @brief Alias name for CAN message box 50 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX50 50U + +/** @def canMESSAGE_BOX51 + * @brief Alias name for CAN message box 51 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX51 51U + +/** @def canMESSAGE_BOX52 + * @brief Alias name for CAN message box 52 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX52 52U + +/** @def canMESSAGE_BOX53 + * @brief Alias name for CAN message box 53 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX53 53U + +/** @def canMESSAGE_BOX54 + * @brief Alias name for CAN message box 54 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX54 54U + +/** @def canMESSAGE_BOX55 + * @brief Alias name for CAN message box 55 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX55 55U + +/** @def canMESSAGE_BOX56 + * @brief Alias name for CAN message box 56 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX56 56U + +/** @def canMESSAGE_BOX57 + * @brief Alias name for CAN message box 57 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX57 57U + +/** @def canMESSAGE_BOX58 + * @brief Alias name for CAN message box 58 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX58 58U + +/** @def canMESSAGE_BOX59 + * @brief Alias name for CAN message box 59 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX59 59U + +/** @def canMESSAGE_BOX60 + * @brief Alias name for CAN message box 60 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX60 60U + +/** @def canMESSAGE_BOX61 + * @brief Alias name for CAN message box 61 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX61 61U + +/** @def canMESSAGE_BOX62 + * @brief Alias name for CAN message box 62 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX62 62U + +/** @def canMESSAGE_BOX63 + * @brief Alias name for CAN message box 63 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX63 63U + +/** @def canMESSAGE_BOX64 + * @brief Alias name for CAN message box 64 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX64 64U + +/** @enum canloopBackType + * @brief canLoopback type definition + */ +/** @typedef canloopBackType_t + * @brief canLoopback type Type Definition + * + * This type is used to select the can module Loopback type Digital or Analog loopback. + */ +typedef enum canloopBackType +{ + Internal_Lbk = 0x00000010U, + External_Lbk = 0x00000100U, + Internal_Silent_Lbk = 0x00000018U +} canloopBackType_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct can_config_reg +{ + uint32 CONFIG_CTL; + uint32 CONFIG_ES; + uint32 CONFIG_BTR; + uint32 CONFIG_TEST; + uint32 CONFIG_ABOTR; + uint32 CONFIG_INTMUX0; + uint32 CONFIG_INTMUX1; + uint32 CONFIG_INTMUX2; + uint32 CONFIG_INTMUX3; + uint32 CONFIG_TIOC; + uint32 CONFIG_RIOC; +} can_config_reg_t; + +/* Configuration registers initial value for CAN1*/ +#define CAN1_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN1_ES_CONFIGVALUE 0x00000007U +#define CAN1_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN1_TEST_CONFIGVALUE 0x00000080U +#define CAN1_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN1_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN1_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN1_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN1_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN2*/ +#define CAN2_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN2_ES_CONFIGVALUE 0x00000007U +#define CAN2_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN2_TEST_CONFIGVALUE 0x00000080U +#define CAN2_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN2_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN2_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN2_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN3*/ +#define CAN3_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN3_ES_CONFIGVALUE 0x00000007U +#define CAN3_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN3_TEST_CONFIGVALUE 0x00000080U +#define CAN3_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN3_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN3_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN3_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN4*/ +#define CAN4_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN4_ES_CONFIGVALUE 0x00000007U +#define CAN4_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN4_TEST_CONFIGVALUE 0x00000080U +#define CAN4_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN4_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN4_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN4_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN4_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN4_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN4_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/** + * @defgroup CAN CAN + * @brief Controller Area Network Module. + * + * The Controller Area Network is a high-integrity, serial, multi-master communication + * protocol for distributed real-time applications. This CAN module is implemented + * according to ISO 11898-1 and is suitable for industrial, automotive and general + * embedded communications + * + * Related Files + * - reg_can.h + * - can.h + * - can.c + * @addtogroup CAN + * @{ + */ + +/* CAN Interface Functions */ + +void canInit( void ); +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ); +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ); +uint32 canGetID( canBASE_t * node, uint32 messageBox ); +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ); +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ); +uint32 canFillMessageObjectData( canBASE_t * node, + uint32 messageBox, + const uint8 * data ); +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ); +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ); +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ); +uint32 canGetLastError( canBASE_t * node ); +uint32 canGetErrorLevel( canBASE_t * node ); +void canEnableErrorNotification( canBASE_t * node ); +void canDisableErrorNotification( canBASE_t * node ); +void canEnableStatusChangeNotification( canBASE_t * node ); +void canDisableStatusChangeNotification( canBASE_t * node ); +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ); +void canDisableloopback( canBASE_t * node ); +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ); +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ); +uint32 canIoTxGetBit( canBASE_t * node ); +uint32 canIoRxGetBit( canBASE_t * node ); +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +/** @fn void canErrorNotification(canBASE_t *node, uint32 notification) + * @brief Error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Error notification code: + * - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 + * and 63 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256 + * + * @note This function has to be provide by the user. + */ +void canErrorNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification) + * @brief Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Status change notification code: + * - canLEVEL_TxOK (0x08) : When sucessful transmission + * - canLEVEL_RxOK (0x10) : When sucessful reception + * - canLEVEL_WakeUpPnd (0x200): When sucessful WakeUp to system initiated + * - canLEVEL_PDA (0x400): When sucessful low power mode entrance + * + * @note This function has to be provide by the user. + */ +void canStatusChangeNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox) + * @brief Message notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * + * @note This function has to be provide by the user. + */ +void canMessageNotification( canBASE_t * node, uint32 messageBox ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h new file mode 100644 index 00000000000..28291143d45 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h @@ -0,0 +1,344 @@ +/** @file crc.h + * @brief CRC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + +#include "reg_crc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CRC General Definitions */ + +/** @def CRCLEVEL_ACTIVE + * @brief Alias name for CRC error operation level active + */ +#define CRCLEVEL_ACTIVE 0x00U + +/** @def CRC_AUTO + * @brief Alias name for CRC auto mode + */ +#define CRC_AUTO 0x00000001U + +/** @def CRC_SEMI_CPU + * @brief Alias name for semi cpu mode setting + */ +#define CRC_SEMI_CPU 0x00000002U + +/** @def CRC_FULL_CPU + * @brief Alias name for CRC cpu full mode + */ +#define CRC_FULL_CPU 0x00000003U + +/** @def CRC_CH4_TO + * @brief Alias name for channel4 time out interrupt flag + */ +#define CRC_CH4_TO 0x10000000U + +/** @def CRC_CH4_UR + * @brief Alias name for channel4 underrun interrupt flag + */ +#define CRC_CH4_UR 0x08000000U + +/** @def CRC_CH4_OR + * @brief Alias name for channel4 overrun interrupt flag + */ +#define CRC_CH4_OR 0x04000000U + +/** @def CRC_CH4_FAIL + * @brief Alias name for channel4 crc fail interrupt flag + */ +#define CRC_CH4_FAIL 0x02000000U + +/** @def CRC_CH4_CC + * @brief Alias name for channel4 compression complete interrupt flag + */ +#define CRC_CH4_CC 0x01000000U + +/** @def CRC_CH3_TO + * @brief Alias name for channel3 time out interrupt flag + */ +#define CRC_CH3_TO 0x00100000U + +/** @def CRC_CH3_UR + * @brief Alias name for channel3 underrun interrupt flag + */ +#define CRC_CH3_UR 0x00080000U + +/** @def CRC_CH3_OR + * @brief Alias name for channel3 overrun interrupt flag + */ +#define CRC_CH3_OR 0x00040000U + +/** @def CRC_CH3_FAIL + * @brief Alias name for channel3 crc fail interrupt flag + */ +#define CRC_CH3_FAIL 0x00020000U + +/** @def CRC_CH3_CC + * @brief Alias name for channel3 compression complete interrupt flag + */ +#define CRC_CH3_CC 0x00010000U + +/** @def CRC_CH2_TO + * @brief Alias name for channel2 time out interrupt flag + */ +#define CRC_CH2_TO 0x00001000U + +/** @def CRC_CH2_UR + * @brief Alias name for channel2 underrun interrupt flag + */ +#define CRC_CH2_UR 0x00000800U + +/** @def CRC_CH2_OR + * @brief Alias name for channel2 overrun interrupt flag + */ +#define CRC_CH2_OR 0x00000400U + +/** @def CRC_CH2_FAIL + * @brief Alias name for channel2 crc fail interrupt flag + */ +#define CRC_CH2_FAIL 0x00000200U + +/** @def CRC_CH2_CC + * @brief Alias name for channel2 compression complete interrupt flag + */ +#define CRC_CH2_CC 0x00000100U + +/** @def CRC_CH1_TO + * @brief Alias name for channel1 time out interrupt flag + */ +#define CRC_CH1_TO 0x00000010U + +/** @def CRC_CH1_UR + * @brief Alias name for channel1 underrun interrupt flag + */ +#define CRC_CH1_UR 0x00000008U + +/** @def CRC_CH1_OR + * @brief Alias name for channel1 overrun interrupt flag + */ +#define CRC_CH1_OR 0x00000004U + +/** @def CRC_CH1_FAIL + * @brief Alias name for channel1 crc fail interrupt flag + */ +#define CRC_CH1_FAIL 0x00000002U + +/** @def CRC_CH1_CC + * @brief Alias name for channel1 compression complete interrupt flag + */ +#define CRC_CH1_CC 0x00000001U + +/** @def CRC_CH1 + * @brief Alias name for channel1 + */ +#define CRC_CH1 0x00000000U + +/** @def CRC_CH1 + * @brief Alias name for channel2 + */ +#define CRC_CH2 0x00000001U + +/** @def CRC_CH3 + * @brief Alias name for channel3 + */ +#define CRC_CH3 0x00000002U + +/** @def CRC_CH4 + * @brief Alias name for channel4 + */ +#define CRC_CH4 0x00000003U + +/** @struct crcModConfig + * @brief CRC mode specific parameters + * + * This type is used to pass crc mode specific parameters + */ +/** @typedef crcModConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcModConfig +{ + uint32 mode; /**< Mode of operation */ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint64 * src_data_pat; /**< Pattern data */ + uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/ +} crcModConfig_t; + +/** @struct crcConfig + * @brief CRC configuration for different modes + * + * This type is used to pass crc configuration + */ +/** @typedef crcConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcConfig +{ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint32 mode; /**< Mode of operation */ + uint32 pcount; /**< Pattern count*/ + uint32 scount; /**< Sector count */ + uint32 wdg_preload; /**< Watchdog period */ + uint32 block_preload; /**< Block period*/ + +} crcConfig_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +typedef struct crc_config_reg +{ + uint32 CONFIG_CTRL0; + uint32 CONFIG_CTRL1; + uint32 CONFIG_CTRL2; + uint32 CONFIG_INTS; + uint32 CONFIG_PCOUNT_REG1; + uint32 CONFIG_SCOUNT_REG1; + uint32 CONFIG_WDTOPLD1; + uint32 CONFIG_BCTOPLD1; + uint32 CONFIG_PCOUNT_REG2; + uint32 CONFIG_SCOUNT_REG2; + uint32 CONFIG_WDTOPLD2; + uint32 CONFIG_BCTOPLD2; +} crc_config_reg_t; + +#define CRC1_CTRL0_CONFIGVALUE 0x00000000U +#define CRC1_CTRL1_CONFIGVALUE 0x00000000U +#define CRC1_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC1_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC1_PCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_SCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_WDTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_BCTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_PCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_SCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_WDTOPLD2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_BCTOPLD2_CONFIGVALUE ( 0x00000000U ) + +#define CRC2_CTRL0_CONFIGVALUE 0x00000000U +#define CRC2_CTRL1_CONFIGVALUE 0x00000000U +#define CRC2_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC2_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC2_PCOUNT_REG1_CONFIGVALUE ( 0U ) +#define CRC2_SCOUNT_REG1_CONFIGVALUE ( 0U ) +#define CRC2_WDTOPLD1_CONFIGVALUE ( 0U ) +#define CRC2_BCTOPLD1_CONFIGVALUE ( 0U ) +#define CRC2_PCOUNT_REG2_CONFIGVALUE ( 0U ) +#define CRC2_SCOUNT_REG2_CONFIGVALUE ( 0U ) +#define CRC2_WDTOPLD2_CONFIGVALUE ( 0U ) +#define CRC2_BCTOPLD2_CONFIGVALUE ( 0U ) + +/** + * @defgroup CRC CRC + * @brief Cyclic Redundancy Check Controller Module. + * + * The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) + * to verify the integrity of memory system. A signature representing the contents of the + * memory is obtained when the contents of the memory are read into CRC controller. The + * responsibility of CRC controller is to calculate the signature for a set of data and + * then compare the calculated signature value against a pre-determined good signature + * value. CRC controller supports two channels to perform CRC calculation on multiple + * memories in parallel and can be used on any memory system. + * + * Related Files + * - reg_crc.h + * - crc.h + * - crc.c + * @addtogroup CRC + * @{ + */ + +/* CRC Interface Functions */ +void crcInit( void ); +void crcSendPowerDown( crcBASE_t * crc ); +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ); +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ); +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ); +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ); +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ); +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ); +void crcChannelReset( crcBASE_t * crc, uint32 channel ); +void crcEnableNotification( crcBASE_t * crc, uint32 flags ); +void crcDisableNotification( crcBASE_t * crc, uint32 flags ); +void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); +void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void crcNotification(crcBASE_t *crc, uint32 flags) + * @brief Interrupt callback + * @param[in] crc - crc module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void crcNotification( crcBASE_t * crc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h new file mode 100644 index 00000000000..d53db2648be --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h @@ -0,0 +1,353 @@ +/** @file dcc.h + * @brief DCC Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DCC_H__ +#define __DCC_H__ + +#include "reg_dcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DCC General Definitions */ + +/** @def dcc1CNT0_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 0 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U + +/** @def dcc1CNT0_CLKSRC_TCK + * @brief Alias name for DCC1 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc1CNT1_CLKSRC_PLL1 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL1 + * + * This is an alias name for the Clock Source PLL for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U + +/** @def dcc1CNT1_CLKSRC_PLL2 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL2 + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U + +/** @def dcc1CNT1_CLKSRC_LFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source LFLPO + * + * This is an alias name for the Clock Source LFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U + +/** @def dcc1CNT1_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN1 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1 + * + * This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN2 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2 + * + * This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U + +/** @def dcc1CNT1_CLKSRC_VCLK + * @brief Alias name for DCC1 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc1CNT1_CLKSRC_N2HET1_31 + * @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31 + * + * This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU + +/** @def dcc2CNT0_CLKSRC_TCK + * @brief Alias name for DCC2 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc2CNT1_CLKSRC_VCLK + * @brief Alias name for DCC2 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc2CNT1_CLKSRC_ODCLK8 + * @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/8 + * + * This is an alias name for the Clock Source PLL2_post_ODCLK/8 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_ODCLK8 0x0000A001U + +/** @def dcc2CNT1_CLKSRC_ODCLK16 + * @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/16 + * + * This is an alias name for the Clock Source PLL2_post_ODCLK/16 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_ODCLK16 0x0000A002U + +/** @def dcc2CNT1_CLKSRC_N2HET1_0 + * @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0 + * + * This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU + +/** @def dccNOTIFICATION_DONE + * @brief Alias name for DCC Done notification + * + * This is an alias name for the DCC Done notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_DONE 0x0000A000U + +/** @def dccNOTIFICATION_ERROR + * @brief Alias name for DCC Error notification + * + * This is an alias name for the DCC Error notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_ERROR 0x000000A0U + +/** @enum dcc1clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc1clocksource +{ + DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/ + DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/ + DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/ + DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/ + DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/ + DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/** @enum dcc2clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc2clocksource +{ + DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC2_CNT1_ODCLK8 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC2_CNT1_ODCLK16 = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/* Configuration registers */ +typedef struct dcc_config_reg +{ + uint32 CONFIG_GCTRL; + uint32 CONFIG_CNT0SEED; + uint32 CONFIG_VALID0SEED; + uint32 CONFIG_CNT1SEED; + uint32 CONFIG_CNT1CLKSRC; + uint32 CONFIG_CNT0CLKSRC; +} dcc_config_reg_t; + +/* Configuration registers initial value */ +#define DCC1_GCTRL_CONFIGVALUE \ + ( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) ) +#define DCC1_CNT0SEED_CONFIGVALUE 39204U +#define DCC1_VALID0SEED_CONFIGVALUE 792U +#define DCC1_CNT1SEED_CONFIGVALUE 742500U +#define DCC1_CNT1CLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 10U << 12U ) | ( uint32 ) DCC1_CNT1_PLL1 ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define DCC1_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC1_CNT0_OSCIN ) + +#define DCC2_GCTRL_CONFIGVALUE \ + ( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) ) +#define DCC2_CNT0SEED_CONFIGVALUE 0U +#define DCC2_VALID0SEED_CONFIGVALUE 0U +#define DCC2_CNT1SEED_CONFIGVALUE 0U +#define DCC2_CNT1CLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | ( uint32 ) DCC2_CNT1_VCLK ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define DCC2_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC2_CNT0_OSCIN ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** + * @defgroup DCC DCC + * @brief Dual-Clock Comparator Module + * + * The primary purpose of a DCC module is to measure the frequency of a clock signal + * using a second known clock signal as a reference. This capability can be used to ensure + * the correct frequency range for several different device clock sources, thereby + * enhancing the system safety metrics. + * + * Related Files + * - reg_dcc.h + * - dcc.h + * - dcc .c + * @addtogroup DCC + * @{ + */ + +/* DCC Interface Functions */ +void dccInit( void ); +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ); +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ); +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ); +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ); +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ); +void dccEnable( dccBASE_t * dcc ); +void dccDisable( dccBASE_t * dcc ); +uint32 dccGetErrStatus( dccBASE_t * dcc ); + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ); +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ); +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags) + * @brief Interrupt callback + * @param[in] dcc - dcc module base address + * @param[in] flags - status flags + * + * This is a callback function provided by the application. It is call when + * a dcc is complete or detected error. + */ +void dccNotification( dccBASE_t * dcc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h new file mode 100644 index 00000000000..306c304460f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h @@ -0,0 +1,164 @@ +/** @file dmm.h + * @brief DMM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DMM_H__ +#define __DMM_H__ + +#include "reg_dmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct dmm_config_reg +{ + uint32 CONFIG_PC0; + uint32 CONFIG_PC1; + uint32 CONFIG_PC3; + uint32 CONFIG_PC6; + uint32 CONFIG_PC7; + uint32 CONFIG_PC8; +} dmm_config_reg_t; + +#define DMM_PC3_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC1_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +#define DMM_PC6_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC8_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +#define DMM_PC7_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC0_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +/** + * @defgroup DMM DMM + * @brief Data Modification Module. + * + * The DMM module provides the capability to modify data in the entire 4 GB address space + *of the device from an external peripheral, with minimal interruption of the application. + * + * Related Files + * - reg_dmm.h + * - dmm.h + * - dmm.c + * @addtogroup DMM + * @{ + */ +/* DMM Interface Functions */ + +void dmmInit( void ); +void dmmGetConfigValue( dmm_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h new file mode 100644 index 00000000000..8400703d3e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h @@ -0,0 +1,347 @@ +/** @file ecap.h + * @brief ECAP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#include "reg_ecap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @brief Enumeration to define the capture (CAP) interrupts + */ +typedef enum +{ + ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */ + ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */ + ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */ + ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */ + ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */ + ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */ + ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */ + ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */ + ecapInt_All = 0x00FFU /*< Denotes All interrupts */ +} ecapInterrupt_t; + +/** @brief Enumeration to define the capture (CAP) prescaler values + */ +typedef enum +{ + ecapPrescale_By_1 = ( ( uint16 ) 0U << 9U ), /*< Divide by 1 */ + ecapPrescale_By_2 = ( ( uint16 ) 1U << 9U ), /*< Divide by 2 */ + ecapPrescale_By_4 = ( ( uint16 ) 2U << 9U ), /*< Divide by 4 */ + ecapPrescale_By_6 = ( ( uint16 ) 3U << 9U ), /*< Divide by 6 */ + ecapPrescale_By_8 = ( ( uint16 ) 4U << 9U ), /*< Divide by 8 */ + ecapPrescale_By_10 = ( ( uint16 ) 5U << 9U ), /*< Divide by 10 */ + ecapPrescale_By_12 = ( ( uint16 ) 6U << 9U ), /*< Divide by 12 */ + ecapPrescale_By_14 = ( ( uint16 ) 7U << 9U ), /*< Divide by 14 */ + ecapPrescale_By_16 = ( ( uint16 ) 8U << 9U ), /*< Divide by 16 */ + ecapPrescale_By_18 = ( ( uint16 ) 9U << 9U ), /*< Divide by 18 */ + ecapPrescale_By_20 = ( ( uint16 ) 10U << 9U ), /*< Divide by 20 */ + ecapPrescale_By_22 = ( ( uint16 ) 11U << 9U ), /*< Divide by 22 */ + ecapPrescale_By_24 = ( ( uint16 ) 12U << 9U ), /*< Divide by 24 */ + ecapPrescale_By_26 = ( ( uint16 ) 13U << 9U ), /*< Divide by 26 */ + ecapPrescale_By_28 = ( ( uint16 ) 14U << 9U ), /*< Divide by 28 */ + ecapPrescale_By_30 = ( ( uint16 ) 15U << 9U ), /*< Divide by 30 */ + ecapPrescale_By_32 = ( ( uint16 ) 16U << 9U ), /*< Divide by 32 */ + ecapPrescale_By_34 = ( ( uint16 ) 17U << 9U ), /*< Divide by 34 */ + ecapPrescale_By_36 = ( ( uint16 ) 18U << 9U ), /*< Divide by 36 */ + ecapPrescale_By_38 = ( ( uint16 ) 19U << 9U ), /*< Divide by 38 */ + ecapPrescale_By_40 = ( ( uint16 ) 20U << 9U ), /*< Divide by 40 */ + ecapPrescale_By_42 = ( ( uint16 ) 21U << 9U ), /*< Divide by 42 */ + ecapPrescale_By_44 = ( ( uint16 ) 22U << 9U ), /*< Divide by 44 */ + ecapPrescale_By_46 = ( ( uint16 ) 23U << 9U ), /*< Divide by 46 */ + ecapPrescale_By_48 = ( ( uint16 ) 24U << 9U ), /*< Divide by 48 */ + ecapPrescale_By_50 = ( ( uint16 ) 25U << 9U ), /*< Divide by 50 */ + ecapPrescale_By_52 = ( ( uint16 ) 26U << 9U ), /*< Divide by 52 */ + ecapPrescale_By_54 = ( ( uint16 ) 27U << 9U ), /*< Divide by 54 */ + ecapPrescale_By_56 = ( ( uint16 ) 28U << 9U ), /*< Divide by 56 */ + ecapPrescale_By_58 = ( ( uint16 ) 29U << 9U ), /*< Divide by 58 */ + ecapPrescale_By_60 = ( ( uint16 ) 30U << 9U ), /*< Divide by 60 */ + ecapPrescale_By_62 = ( ( uint16 ) 31U << 9U ) /*< Divide by 62 */ +} ecapPrescale_t; + +/** @brief Enumeration to define the Sync Out options + */ +typedef enum +{ + SyncOut_SyncIn = ( ( uint16 ) 0U << 6U ), /*< Sync In used for Sync Out */ + SyncOut_CTRPRD = ( ( uint16 ) 1U << 6U ), /*< CTR = PRD used for Sync Out */ + SyncOut_None = ( ( uint16 ) 2U << 6U ) /*< Disables Sync Out */ +} ecapSyncOut_t; + +/** @brief Enumeration to define the Polarity + */ +typedef enum +{ + RISING_EDGE = 0U, + FALLING_EDGE = 1U +} ecapEdgePolarity_t; + +typedef enum +{ + ACTIVE_HIGH = 0U, + ACTIVE_LOW = 1U +} ecapAPWMPolarity_t; + +/** @brief Enumeration to define the Mode of operation + */ +typedef enum +{ + CONTINUOUS = 0U, + ONE_SHOT = 1U +} ecapMode_t; + +/** @brief Enumeration to define the capture events + */ +typedef enum +{ + CAPTURE_EVENT1 = 0U, + CAPTURE_EVENT2 = 1U, + CAPTURE_EVENT3 = 2U, + CAPTURE_EVENT4 = 3U +} ecapEvent_t; + +typedef enum +{ + RESET_ENABLE = 1U, + RESET_DISABLE = 0U +} ecapReset_t; + +typedef struct ecap_config_reg +{ + uint32 CONFIG_CTRPHS; + uint16 CONFIG_ECCTL1; + uint16 CONFIG_ECCTL2; + uint16 CONFIG_ECEINT; +} ecap_config_reg_t; + +#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP1_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP1_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP1_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP2_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP2_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP2_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP3_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP3_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP3_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP4_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP4_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP4_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP5_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP5_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP5_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP6_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP6_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP6_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) +/** + * @defgroup eCAP eCAP + * @brief Enhanced Capture Module. + * + * The enhanced Capture (eCAP) module is essential in systems where accurate timing of + *external events is important. This microcontroller implements 6 instances of the eCAP + *module. + * + * Related Files + * - reg_ecap.h + * - ecap.h + * - ecap.c + * @addtogroup eCAP + * @{ + */ +void ecapInit( void ); +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ); +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ); +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ); +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ); +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ); +void ecapEnableCapture( ecapBASE_t * ecap ); +void ecapDisableCapture( ecapBASE_t * ecap ); +void ecapStartCounter( ecapBASE_t * ecap ); +void ecapStopCounter( ecapBASE_t * ecap ); +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ); +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ); +void ecapDisableAPWMMode( ecapBASE_t * ecap ); +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ); +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ); +uint32 ecapGetCAP1( ecapBASE_t * ecap ); +uint32 ecapGetCAP2( ecapBASE_t * ecap ); +uint32 ecapGetCAP3( ecapBASE_t * ecap ); +uint32 ecapGetCAP4( ecapBASE_t * ecap ); +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); + +/** @brief Interrupt callback + * @param[in] ecap Handle to CAP object + * @param[in] flags Copy of interrupt flags + */ +void ecapNotification( ecapBASE_t * ecap, uint16 flags ); + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /*end of _CAP_H_ definition */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h new file mode 100644 index 00000000000..11b377794cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h @@ -0,0 +1,438 @@ +/** + * \file emac.h + * + * \brief EMAC APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __EMAC_H__ +#define __EMAC_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "hw_reg_access.h" +#include "hw_emac.h" +#include "hw_emac_ctrl.h" +#include "mdio.h" +#include "emac_phyConfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/*****************************************************************************/ +/* +** Macros which can be used as speed parameter to the API EMACRMIISpeedSet +*/ +#define EMAC_RMIISPEED_10MBPS ( 0x00000000U ) +#define EMAC_RMIISPEED_100MBPS ( 0x00008000U ) + +/* Macros for enabling taken as inputs from HALCoGen GUI. */ +#define EMAC_TX_ENABLE ( 1U ) +#define EMAC_RX_ENABLE ( 1U ) +#define EMAC_MII_ENABLE ( 1U ) +#define EMAC_FULL_DUPLEX_ENABLE ( 1U ) +#define EMAC_LOOPBACK_ENABLE ( 0U ) +#define EMAC_BROADCAST_ENABLE ( 1U ) +#define EMAC_UNICAST_ENABLE ( 1U ) +#define EMAC_CHANNELNUMBER ( 0U ) +#define EMAC_PHYADDRESS ( 1U ) + +/* + * Macros to indicate EMAC Channel Numbers + */ +#define EMAC_CHANNEL_0 ( 0x00000000U ) +#define EMAC_CHANNEL_1 ( 0x00000001U ) +#define EMAC_CHANNEL_2 ( 0x00000002U ) +#define EMAC_CHANNEL_3 ( 0x00000003U ) +#define EMAC_CHANNEL_4 ( 0x00000004U ) +#define EMAC_CHANNEL_5 ( 0x00000005U ) +#define EMAC_CHANNEL_6 ( 0x00000006U ) +#define EMAC_CHANNEL_7 ( 0x00000007U ) +/* Macros which can be used as duplexMode parameter to the API +** EMACDuplexSet +*/ +#define EMAC_DUPLEX_FULL ( 0x00000001U ) +#define EMAC_DUPLEX_HALF ( 0x00000000U ) + +/* +** Macros which can be used as matchFilt parameters to the API +** EMACMACAddrSet +*/ +/* Address not used to match/filter incoming packets */ +#define EMAC_MACADDR_NO_MATCH_NO_FILTER ( 0x00000000U ) + +/* Address will be used to filter incoming packets */ +#define EMAC_MACADDR_FILTER ( 0x00100000U ) + +/* Address will be used to match incoming packets */ +#define EMAC_MACADDR_MATCH ( 0x00180000U ) + +/* +** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API +*/ +#define EMAC_INT_CORE0_RX ( 0x1U ) +#define EMAC_INT_CORE1_RX ( 0x5U ) +#define EMAC_INT_CORE2_RX ( 0x9U ) + +/* +** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API +*/ +#define EMAC_INT_CORE0_TX ( 0x2U ) +#define EMAC_INT_CORE1_TX ( 0x6U ) +#define EMAC_INT_CORE2_TX ( 0xAU ) +/* Base Addresses */ +#define EMAC_CTRL_RAM_0_BASE 0xFC520000U +#define EMAC_0_BASE 0xFCF78000U +#define EMAC_CTRL_0_BASE 0xFCF78800U +#define MDIO_0_BASE 0xFCF78900U + +/*MAC address length*/ +#define EMAC_HWADDR_LEN 6U +#define MAX_EMAC_INSTANCE 1U +#define SIZE_EMAC_CTRL_RAM 0x2000U +#define MAX_TRANSFER_UNIT 1514U +#define MAX_RX_PBUF_ALLOC ( 10U ) +#define MIN_PKT_LEN 60U +#define MIN_PACKET_SIZE ( 46U ) + +#define EMAC_BUF_DESC_OWNER 0x20000000U +#define EMAC_BUF_DESC_SOP 0x80000000U +#define EMAC_BUF_DESC_EOP 0x40000000U +#define EMAC_BUF_DESC_EOQ 0x10000000U + +#define EMAC_NETSTATREGS( n ) ( ( uint32 ) 0x200U + ( uint32 ) ( ( n ) * 4U ) ) + +/* Error Signalling Macros */ +#define EMAC_ERR_CONNECT 0x2U /* Not connected. */ +#define EMAC_ERR_OK 0x1U /* No error, everything OK. */ + +/* Macros for Configuration Value Registers */ +#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_MACSRCADDRHI_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 24U ) | ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MACSRCADDRLO_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU +#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U +#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U + +/* Structure to store pending status from the Tx Interrupt Status Registers. */ +typedef struct emac_tx_int_status +{ + volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit + Interrupt Status (Masked) Register (TXINTSTATMASKED) + */ + volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit + Interrupt Status (Unmasked) Register (TXINTSTATRAW) */ +} emac_tx_int_status_t; + +/* Structure to store pending status from the Rx Interrupt Status Registers. */ +typedef struct emac_rx_int_status +{ + volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the + Receive Interrupt Status (Unmasked) + Register (RXINTSTATRAW) */ + + volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive + Interrupt Status (Unmasked) Register + (RXINTSTATRAW) */ + +} emac_rx_int_status_t; + +/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure.*/ +typedef struct emac_tx_bd +{ + volatile struct emac_tx_bd * next; + volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be + transmitted. */ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_tx_bd_t; + +/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure. */ +typedef struct emac_rx_bd +{ + volatile struct emac_rx_bd * next; /*Used as a pointer for next element in the linked + list of descriptors.*/ + volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received + data.*/ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_rx_bd_t; + +/** + * Helper struct to hold the data used to operate on a particular + * receive channel + */ +typedef struct rxch_struct +{ + volatile emac_rx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can receive new data.*/ + volatile emac_rx_bd_t * active_head; /*Used to point to the active descriptor in the + chain which is receiving.*/ + volatile emac_rx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ +} rxch_t; + +/** + * Helper struct to hold the data used to operate on a particular + * transmit channel + */ +typedef struct txch_struct +{ + volatile emac_tx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can transmit new data.*/ + volatile emac_tx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ + volatile emac_tx_bd_t * next_bd_to_process; /*Used to point to the next descriptor in + the chain to be processed.*/ +} txch_t; +/** + * Helper struct to hold private data used to operate the ethernet interface. + */ +typedef struct hdkif_struct +{ + /* MAC Address of the Module. */ + uint8_t mac_addr[ 6 ]; + + /* emac base address */ + uint32 emac_base; + + /* emac controller base address */ + volatile uint32 emac_ctrl_base; + volatile uint32 emac_ctrl_ram; + + /* mdio base address */ + volatile uint32 mdio_base; + + /* phy parameters for this instance - for future use */ + uint32 phy_addr; + boolean ( *phy_autoneg )( uint32 param1, uint32 param2, uint16 param3 ); + boolean ( *phy_partnerability )( uint32 param4, uint32 param5, uint16 * param6 ); + + /* The tx/rx channels for the interface */ + txch_t txchptr; + rxch_t rxchptr; +} hdkif_t; + +/*Ethernet Frame Structure */ +typedef struct ethernet_frame +{ + uint8 dest_addr[ 6 ]; /* Destination MAC Address */ + uint8 src_addr[ 6 ]; /*Source MAC Address. */ + uint16 frame_length; /* Data Frame Length */ + uint8 data[ 1500 ]; /* Data */ +} ethernet_frame_t; + +/* Struct used to take packet data input from the user for transmit APIs. */ +typedef struct pbuf_struct +{ + /** next pbuf in singly linked pbuf chain */ + struct pbuf_struct * next; + + /** + * Pointer to the actual ethernet packet/packet fragment to be transmitted. + * The packet needs to be in the following format: + * |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2 + *bytes)| Data (46- 1500 bytes) The data can be split up over multiple pbufs which are + *linked as a linked list. + **/ + uint8 * payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + uint16 tot_len; + + /** length of this buffer */ + uint16 len; + +} pbuf_t; + +/* Structure to hold the values of the EMAC Configuration Registers. */ +typedef struct emac_config_reg_struct +{ + /* EMAC Module Register Values */ + uint32 TXCONTROL; /* Transmit Control Register. */ + uint32 RXCONTROL; /* Receive Control Register */ + uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */ + uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */ + uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */ + uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/ + uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/ + uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/ + + /*MDIO Module Registers */ + uint32 MDIOCONTROL; /*MDIO Control Register. */ + + /* EMAC Control Module Registers */ + uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ +} emac_config_reg_t; +/*****************************************************************************/ +/** + * @defgroup EMACMDIO EMAC/MDIO + * @brief Ethernet Media Access Controller/Management Data Input/Output. + * + * The EMAC controls the flow of packet data from the system to the PHY. The MDIO module + *controls PHY configuration and status monitoring. + * + * Both the EMAC and the MDIO modules interface to the system core through a custom + *interface that allows efficient data transmission and reception. This custom interface + *is referred to as the EMAC control module and is considered integral to the EMAC/MDIO + *peripheral + * + * Related Files + * - emac.h + * - emac.c + * - hw_emac.h + * - hw_emac_ctrl.h + * - hw_mdio.h + * - hw_reg_access.h + * - mdio.h + * - mdio.c + * @addtogroup EMACMDIO + * @{ + */ +/* +** Prototypes for the APIs +*/ +extern uint32 EMACLinkSetup( hdkif_t * hdkif ); +extern void EMACInstConfig( hdkif_t * hdkif ); +extern void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ); +extern void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ); +extern void EMACTxEnable( uint32 emacBase ); +extern void EMACTxDisable( uint32 emacBase ); +extern void EMACRxEnable( uint32 emacBase ); +extern void EMACRxDisable( uint32 emacBase ); +uint32 EMACSwizzleData( uint32 word ); +extern void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACInit( uint32 emacCtrlBase, uint32 emacBase ); +extern void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ); +extern void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ); +extern void EMACMIIEnable( uint32 emacBase ); +extern void EMACMIIDisable( uint32 emacBase ); +extern void EMACRxUnicastSet( uint32 emacBase, uint32 channel ); +extern void EMACRxUnicastClear( uint32 emacBase, uint32 channel ); +extern void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ); +extern void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ); +extern uint32 EMACIntVectorGet( uint32 emacBase ); +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ); +void EMACTxTeardown( uint32 emacBase, uint32 channel ); +void EMACRxTeardown( uint32 emacBase, uint32 channel ); +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ); +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ); +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ); +void EMACEnableIdleState( uint32 emacBase ); +void EMACDisableIdleState( uint32 emacBase ); +void EMACEnableLoopback( uint32 emacBase ); +void EMACDisableLoopback( uint32 emacBase ); +void EMACTxFlowControlEnable( uint32 emacBase ); +void EMACTxFlowControlDisable( uint32 emacBase ); +void EMACRxFlowControlEnable( uint32 emacBase ); +void EMACRxFlowControlDisable( uint32 emacBase ); +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ); +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ); +void EMACDMAInit( hdkif_t * hdkif ); +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ); +void EMACTxIntHandler( hdkif_t * hdkif ); +void EMACReceive( hdkif_t * hdkif ); +/* Notification Function to which received packets are passed after processing */ +void emacTxNotification( hdkif_t * hdkif ); +void emacRxNotification( hdkif_t * hdkif ); +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ); +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ); +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __EMAC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h new file mode 100644 index 00000000000..035722af057 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h @@ -0,0 +1,45 @@ +/** + * \file emac_phyConfig.h + * + * \brief PHY Configuration file for selecting and configuring the required PHY. + * + * This file contains the mappings of the PHY APIs so that the right one is chosen based + * on the user's preference. + */ + +/* (c) Texas Instruments 2009-2014, All rights reserved. */ + +#ifndef _EMAC_PHYCONFIG_H_ +#define _EMAC_PHYCONFIG_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define PhyIDGet Dp83640IDGet +#define PhyLinkStatusGet Dp83640LinkStatusGet +#define PhyAutoNegotiate Dp83640AutoNegotiate +#define PhyPartnerAbilityGet Dp83640PartnerAbilityGet +#define PhyReset Dp83640Reset +#define PhyEnableLoopback Dp83640EnableLoopback +#define PhyDisableLoopback Dp83640DisableLoopback +#define PhyGetTimeStamp Dp83640GetTimeStamp +#define PhyPartnerSpdGet Dp83640PartnerSpdGet + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* _EMAC_PHYCONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h new file mode 100644 index 00000000000..8e65dcacc63 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h @@ -0,0 +1,216 @@ +/** @file emif.h + * @brief emif Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ + +#include "reg_emif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum emif_pins + * @brief Alias for emif pins + * + */ +enum emif_pins +{ + emif_wait_pin0 = 0U, + emif_wait_pin1 = 1U +}; + +/** @enum emif_size + * @brief Alias for emif page size + * + */ +enum emif_size +{ + elements_256 = 0U, + elements_512 = 1U, + elements_1024 = 2U, + elements_2048 = 3U +}; + +/** @enum emif_port + * @brief Alias for emif port + * + */ +enum emif_port +{ + emif_8_bit_port = 0U, + emif_16_bit_port = 1U +}; + +/** @enum emif_pagesize + * @brief Alias for emif pagesize + * + */ +enum emif_pagesize +{ + emif_4_words = 0U, + emif_8_words = 1U +}; + +/** @enum emif_wait_polarity + * @brief Alias for emif wait polarity + * + */ +enum emif_wait_polarity +{ + emif_pin_low = 0U, + emif_pin_high = 1U +}; + +#define PTR ( ( volatile uint32 * ) ( 0x80000000U ) ) + +/* Configuration registers */ +typedef struct emif_config_reg +{ + uint32 CONFIG_AWCC; + uint32 CONFIG_SDCR; + uint32 CONFIG_SDRCR; + uint32 CONFIG_CE2CFG; + uint32 CONFIG_CE3CFG; + uint32 CONFIG_CE4CFG; + uint32 CONFIG_CE5CFG; + uint32 CONFIG_SDTIMR; + uint32 CONFIG_SDSRETR; + uint32 CONFIG_INTMSK; + uint32 CONFIG_PMCR; +} emif_config_reg_t; + +/* Configuration registers initial value for EMIF*/ +#define EMIF_AWCC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) \ + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) 0xC0000000U ) + +#define EMIF_SDCR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 31U ) | ( uint32 ) ( ( uint32 ) 1U << 14U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) elements_256 ) ) + +#define EMIF_SDRCR_CONFIGVALUE 0U + +#define EMIF_CE2CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE3CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE4CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE5CFG_CONFIGVALUE 0x3FFFFFFDU + +#define EMIF_SDTIMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | 0x00000000U ) + +#define EMIF_SDSRETR_CONFIGVALUE 0U +#define EMIF_INTMSK_CONFIGVALUE 0x00000000U +#define EMIF_PMCR_CONFIGVALUE \ + ( 0xFC000000U | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +/** + * @defgroup EMIF EMIF + * @brief External Memory Interface. + * + * This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories + *utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU + *to connect to a variety of external devices including: + * - Single data rate (SDR) SDRAM + * - Asynchronous devices including NOR Flash and SRAM + * The most common use for the EMIF is to interface with both a flash device and an SDRAM + *device simultaneously. contains an example of operating the EMIF in this configuration. + * + * Related Files + * - reg_emif.h + * - emif.h + * - emif.c + * @addtogroup EMIF + * @{ + */ +/* EMIF Interface Functions */ + +void emif_SDRAMInit( void ); +void emif_SDRAM_StartupInit( void ); +void emif_ASYNC1Init( void ); +void emif_ASYNC2Init( void ); +void emif_ASYNC3Init( void ); +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /*EMIF_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h new file mode 100644 index 00000000000..920b963568f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h @@ -0,0 +1,134 @@ +/** @file epc.h + * @brief EPC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EPC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYS_EPC_H_ +#define SYS_EPC_H_ + +#include "reg_epc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +enum CAMIndex +{ + CAMIndex_0 = 0U, + CAMIndex_1 = 1U, + CAMIndex_2 = 2U, + CAMIndex_3 = 3U, + CAMIndex_4 = 4U, + CAMIndex_5 = 5U, + CAMIndex_6 = 6U, + CAMIndex_7 = 7U, + CAMIndex_8 = 8U, + CAMIndex_9 = 9U, + CAMIndex_10 = 10U, + CAMIndex_11 = 11U, + CAMIndex_12 = 12U, + CAMIndex_13 = 13U, + CAMIndex_14 = 14U, + CAMIndex_15 = 15U, + CAMIndex_16 = 16U, + CAMIndex_17 = 17U, + CAMIndex_18 = 18U, + CAMIndex_19 = 19U, + CAMIndex_20 = 20U, + CAMIndex_21 = 21U, + CAMIndex_22 = 22U, + CAMIndex_23 = 23U, + CAMIndex_24 = 24U, + CAMIndex_25 = 25U, + CAMIndex_26 = 26U, + CAMIndex_27 = 27U, + CAMIndex_28 = 28U, + CAMIndex_29 = 29U, + CAMIndex_30 = 30U, + CAMIndex_31 = 31U +}; + +/** + * @defgroup EPC EPC + * @brief Error Profiling Controller + * + * Related files: + * - reg_epc.h + * - sys_epc.h + * - sys_epc.c + * + * @addtogroup EPC + * @{ + */ + +void epcEnableIP1ErrorGen( void ); +void epcDisableIP1ErrorGen( void ); +void epcEnableIP2ErrorGen( void ); +void epcDisableIP2ErrorGen( void ); +void epcEnableSERREvent( void ); +void epcDisableSERREvent( void ); +void epcEnableInterrupt( void ); +void epcDisableInterrupt( void ); +void epcCAMInit( void ); +boolean epcDiagnosticTest( void ); +boolean epcAddCAMEEntry( uint32 address ); +boolean epcCheckCAMEntry( uint32 index ); + +void epcCAMFullNotification( void ); +void epcFIFOFullNotification( uint32 epcFIFOStatus ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* SYS_EPC_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h new file mode 100644 index 00000000000..274a69ca691 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h @@ -0,0 +1,863 @@ +/** @file eqep.h + * @brief EQEP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __eQEP_H__ +#define __eQEP_H__ + +#include "reg_eqep.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define QEP_BASE_ADDR ( 0x00006B00U ) /* "Reason - TI_Fee_Fix is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_Fee_None is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None + #endif + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_MAXIMUM_BLOCKING_TIME is a + * symbolic constant"*/ + #define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_OPERATING_FREQUENCY is a + * symbolic constant."*/ + #define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE + * is a symbolic constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_CHECKSUM_ENABLE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - NVM_DATASET_SELECTION_BITS is a + * symbolic constant."*/ + #define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EEPS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_INDEX is a symbolic + * constant."*/ + #define TI_FEE_INDEX FEE_INDEX + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PAGE_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_BLOCK_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_PAGE_SIZE is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/ + #define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY \ + FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a + * symbolic constant."*/ + #define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_END_NOTIFICATION is a + * symbolic constant."*/ + #define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is + * a symbolic constant."*/ + #define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_POLLING_MODE is a symbolic + * constant."*/ + #define TI_FEE_POLLING_MODE FEE_POLLING_MODE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #ifndef FEE_CHECK_BANK7_ACCESS + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #endif + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_TOTAL_BLOCKS_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUALSECTOR_SIZE is a + * symbolic constant."*/ + #define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PHYSICALSECTOR_SIZE is a + * symbolic constant."*/ + #define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/ + #define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC \ + FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_USEPARTIALERASEDSECTOR is a + * symbolic constant."*/ + #define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR + + /*----------------------------------------------------------------------------*/ + /* Virtual Sector Configuration */ + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a + * symbolic constant."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + * is a symbolic constant."*/ + /*SAFETYMCUSW 384 S MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + + /*----------------------------------------------------------------------------*/ + /* Block Configuration */ + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_FEE_VARIABLE_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_VARIABLE_DATASETS STD_ON + + #endif /* TI_FEE_DRIVER */ + +#endif /* FEE_INTERFACE_H */ +/********************************************************************************************************************** + * END OF FILE: fee_interface.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h new file mode 100644 index 00000000000..ea64d9e5806 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h @@ -0,0 +1,182 @@ +/** @file gio.h + * @brief GIO Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GIO_H__ +#define __GIO_H__ + +#include "reg_gio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef struct gio_config_reg +{ + uint32 CONFIG_INTDET; + uint32 CONFIG_POL; + uint32 CONFIG_INTENASET; + uint32 CONFIG_LVLSET; + + uint32 CONFIG_PORTADIR; + uint32 CONFIG_PORTAPDR; + uint32 CONFIG_PORTAPSL; + uint32 CONFIG_PORTAPULDIS; + + uint32 CONFIG_PORTBDIR; + uint32 CONFIG_PORTBPDR; + uint32 CONFIG_PORTBPSL; + uint32 CONFIG_PORTBPULDIS; +} gio_config_reg_t; + +#define GIO_INTDET_CONFIGVALUE 0U +#define GIO_POL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_INTENASET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_LVLSET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_PORTADIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +#define GIO_PORTBDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +/** + * @defgroup GIO GIO + * @brief General-Purpose Input/Output Module. + * + * The GIO module provides the family of devices with input/output (I/O) capability. + * The I/O pins are bidirectional and bit-programmable. + * The GIO module also supports external interrupt capability. + * + * Related Files + * - reg_gio.h + * - gio.h + * - gio.c + * @addtogroup GIO + * @{ + */ + +/* GIO Interface Functions */ +void gioInit( void ); +void gioSetDirection( gioPORT_t * port, uint32 dir ); +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ); +void gioSetPort( gioPORT_t * port, uint32 value ); +uint32 gioGetBit( gioPORT_t * port, uint32 bit ); +uint32 gioGetPort( gioPORT_t * port ); +void gioToggleBit( gioPORT_t * port, uint32 bit ); +void gioEnableNotification( gioPORT_t * port, uint32 bit ); +void gioDisableNotification( gioPORT_t * port, uint32 bit ); +void gioNotification( gioPORT_t * port, uint32 bit ); +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h new file mode 100644 index 00000000000..1def1eafe6e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h @@ -0,0 +1,185 @@ +/** @file hal_stdtypes.h + * @brief HALCoGen standard types header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Type and Global definitions which are relevant for all drivers. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HAL_STDTYPES_H__ +#define __HAL_STDTYPES_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include +#include + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +/************************************************************/ +/* Type Definitions */ +/************************************************************/ +#ifndef _UINT64_DECLARED +typedef uint64_t uint64; + #define _UINT64_DECLARED +#endif + +#ifndef _UINT32_DECLARED +typedef uint32_t uint32; + #define _UINT32_DECLARED +#endif + +#ifndef _UINT16_DECLARED +typedef uint16_t uint16; + #define _UINT16_DECLARED +#endif + +#ifndef _UINT8_DECLARED +typedef uint8_t uint8; + #define _UINT8_DECLARED +#endif + +#ifndef _BOOLEAN_DECLARED + #ifdef __cplusplus +typedef bool boolean; + #else +typedef _Bool boolean; + #endif + #define _BOOLEAN_DECLARED +#endif + +#ifndef _SINT64_DECLARED +typedef int64_t sint64; + #define _SINT64_DECLARED +#endif + +#ifndef _SINT32_DECLARED +typedef int32_t sint32; + #define _SINT32_DECLARED +#endif + +#ifndef _SINT16_DECLARED +typedef int16_t sint16; + #define _SINT16_DECLARED +#endif + +#ifndef _SINT8_DECLARED +typedef int8_t sint8; + #define _SINT8_DECLARED +#endif + +#ifndef _FLOAT32_DECLARED +typedef float float32; + #define _FLOAT32_DECLARED +#endif + +#ifndef _FLOAT64_DECLARED +typedef double float64; + #define _FLOAT64_DECLARED +#endif + +typedef uint8 Std_ReturnType; + +typedef struct +{ + uint16 vendorID; + uint16 moduleID; + uint8 instanceID; + uint8 sw_major_version; + uint8 sw_minor_version; + uint8 sw_patch_version; +} Std_VersionInfoType; + +/*****************************************************************************/ +/* SYMBOL DEFINITIONS */ +/*****************************************************************************/ +#ifndef STATUSTYPEDEFINED + #define STATUSTYPEDEFINED + #define E_OK 0x00U + +typedef unsigned char StatusType; +#endif + +#ifndef E_NOT_OK + #define E_NOT_OK 0x01U +#endif + +#ifndef STD_ON + #define STD_ON 0x01U +#endif + +#ifndef STD_OFF + #define STD_OFF 0x00U +#endif + +/************************************************************/ +/* Global Definitions */ +/************************************************************/ +/** @def NULL + * @brief NULL definition + */ +#ifndef NULL + #define NULL ( ( void * ) 0U ) +#endif + +/** @def TRUE + * @brief definition for TRUE + */ +#ifndef TRUE + #define TRUE true +#endif + +/** @def FALSE + * @brief BOOLEAN definition for FALSE + */ +#ifndef FALSE + #define FALSE false +#endif + +/*****************************************************************************/ +/* Define: NULL_PTR */ +/* Description: Void pointer to 0 */ +/*****************************************************************************/ +#ifndef NULL_PTR + #define NULL_PTR ( ( void * ) 0x0U ) +#endif +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* __HAL_STDTYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h new file mode 100644 index 00000000000..ba0e72753eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h @@ -0,0 +1,633 @@ +/** @file het.h + * @brief HET Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HET_H__ +#define __HET_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "reg_het.h" +#include + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @def pwm0 + * @brief Pwm signal 0 + * + * Alias for pwm signal 0 + */ +#define pwm0 0U + +/** @def pwm1 + * @brief Pwm signal 1 + * + * Alias for pwm signal 1 + */ +#define pwm1 1U + +/** @def pwm2 + * @brief Pwm signal 2 + * + * Alias for pwm signal 2 + */ +#define pwm2 2U + +/** @def pwm3 + * @brief Pwm signal 3 + * + * Alias for pwm signal 3 + */ +#define pwm3 3U + +/** @def pwm4 + * @brief Pwm signal 4 + * + * Alias for pwm signal 4 + */ +#define pwm4 4U + +/** @def pwm5 + * @brief Pwm signal 5 + * + * Alias for pwm signal 5 + */ +#define pwm5 5U + +/** @def pwm6 + * @brief Pwm signal 6 + * + * Alias for pwm signal 6 + */ +#define pwm6 6U + +/** @def pwm7 + * @brief Pwm signal 7 + * + * Alias for pwm signal 7 + */ +#define pwm7 7U + +/** @def edge0 + * @brief Edge signal 0 + * + * Alias for edge signal 0 + */ +#define edge0 0U + +/** @def edge1 + * @brief Edge signal 1 + * + * Alias for edge signal 1 + */ +#define edge1 1U + +/** @def edge2 + * @brief Edge signal 2 + * + * Alias for edge signal 2 + */ +#define edge2 2U + +/** @def edge3 + * @brief Edge signal 3 + * + * Alias for edge signal 3 + */ +#define edge3 3U + +/** @def edge4 + * @brief Edge signal 4 + * + * Alias for edge signal 4 + */ +#define edge4 4U + +/** @def edge5 + * @brief Edge signal 5 + * + * Alias for edge signal 5 + */ +#define edge5 5U + +/** @def edge6 + * @brief Edge signal 6 + * + * Alias for edge signal 6 + */ +#define edge6 6U + +/** @def edge7 + * @brief Edge signal 7 + * + * Alias for edge signal 7 + */ +#define edge7 7U + +/** @def cap0 + * @brief Capture signal 0 + * + * Alias for capture signal 0 + */ +#define cap0 0U + +/** @def cap1 + * @brief Capture signal 1 + * + * Alias for capture signal 1 + */ +#define cap1 1U + +/** @def cap2 + * @brief Capture signal 2 + * + * Alias for capture signal 2 + */ +#define cap2 2U + +/** @def cap3 + * @brief Capture signal 3 + * + * Alias for capture signal 3 + */ +#define cap3 3U + +/** @def cap4 + * @brief Capture signal 4 + * + * Alias for capture signal 4 + */ +#define cap4 4U + +/** @def cap5 + * @brief Capture signal 5 + * + * Alias for capture signal 5 + */ +#define cap5 5U + +/** @def cap6 + * @brief Capture signal 6 + * + * Alias for capture signal 6 + */ +#define cap6 6U + +/** @def cap7 + * @brief Capture signal 7 + * + * Alias for capture signal 7 + */ +#define cap7 7U + +/** @def pwmEND_OF_DUTY + * @brief Pwm end of duty + * + * Alias for pwm end of duty notification + */ +#define pwmEND_OF_DUTY 2U + +/** @def pwmEND_OF_PERIOD + * @brief Pwm end of period + * + * Alias for pwm end of period notification + */ +#define pwmEND_OF_PERIOD 4U + +/** @def pwmEND_OF_BOTH + * @brief Pwm end of duty and period + * + * Alias for pwm end of duty and period notification + */ +#define pwmEND_OF_BOTH 6U + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/** @struct hetBase + * @brief HET Register Definition + * + * This structure is used to access the HET module registers. + */ +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +enum hetPinSelect +{ + PIN_HET_0 = 0U, + PIN_HET_1 = 1U, + PIN_HET_2 = 2U, + PIN_HET_3 = 3U, + PIN_HET_4 = 4U, + PIN_HET_5 = 5U, + PIN_HET_6 = 6U, + PIN_HET_7 = 7U, + PIN_HET_8 = 8U, + PIN_HET_9 = 9U, + PIN_HET_10 = 10U, + PIN_HET_11 = 11U, + PIN_HET_12 = 12U, + PIN_HET_13 = 13U, + PIN_HET_14 = 14U, + PIN_HET_15 = 15U, + PIN_HET_16 = 16U, + PIN_HET_17 = 17U, + PIN_HET_18 = 18U, + PIN_HET_19 = 19U, + PIN_HET_20 = 20U, + PIN_HET_21 = 21U, + PIN_HET_22 = 22U, + PIN_HET_23 = 23U, + PIN_HET_24 = 24U, + PIN_HET_25 = 25U, + PIN_HET_26 = 26U, + PIN_HET_27 = 27U, + PIN_HET_28 = 28U, + PIN_HET_29 = 29U, + PIN_HET_30 = 30U, + PIN_HET_31 = 31U +}; + +/** @struct hetSignal + * @brief HET Signal Definition + * + * This structure is used to define a pwm signal. + */ +/** @typedef hetSIGNAL_t + * @brief HET Signal Type Definition + * + * This type is used to access HET Signal Information. + */ +typedef struct hetSignal +{ + uint32 duty; /**< Duty cycle in % of the period */ + float64 period; /**< Period in us */ +} hetSIGNAL_t; + +/* Configuration registers */ +typedef struct het_config_reg +{ + uint32 CONFIG_GCR; + uint32 CONFIG_PFR; + uint32 CONFIG_INTENAS; + uint32 CONFIG_INTENAC; + uint32 CONFIG_PRY; + uint32 CONFIG_AND; + uint32 CONFIG_HRSH; + uint32 CONFIG_XOR; + uint32 CONFIG_DIR; + uint32 CONFIG_PDR; + uint32 CONFIG_PULDIS; + uint32 CONFIG_PSL; + uint32 CONFIG_PCR; +} het_config_reg_t; + +/* Configuration registers initial value for HET1*/ +#define HET1_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET1_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U ) + +#define HET1_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET1_GCR_CONFIGVALUE \ + ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ) + +/* Configuration registers initial value for HET2*/ +#define HET2_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET2_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U ) + +#define HET2_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET2_GCR_CONFIGVALUE \ + ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ) + +/** + * @defgroup HET HET + * @brief HighEnd Timer Module. + * + * The HET is a software-controlled timer with a dedicated specialized timer micromachine + *and a set of 30 instructions. The HET micromachine is connected to a port of up to 32 + *input/output (I/O) pins. + * + * Related Files + * - reg_het.h + * - het.h + * - het.c + * - reg_htu.h + * - htu.h + * - std_nhet.h + * @addtogroup HET + * @{ + */ + +/* HET Interface Functions */ +void hetInit( void ); + +/* PWM Interface Functions */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ); +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ); +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ); +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); + +/* Edge Interface Functions */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeNotification( hetBASE_t * hetREG, uint32 edge ); + +/* Captured Signal Interface Functions */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ); + +/* Timestamp Interface Functions */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ); +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ); +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void hetNotification(hetBASE_t *het, uint32 offset) + * @brief het interrupt callback + * @param[in] het - Het module base address + * - hetREG1: HET1 module base address pointer + * - hetREG2: HET2 module base address pointer + * @param[in] offset - het interrupt offset / Source number + * + * @note This function has to be provide by the user. + * + * This is a interrupt callback that is provided by the application and is call upon + * an het interrupt. The parameter passed to the callback is a copy of the interrupt + * offset register which is used to decode the interrupt source. + */ +void hetNotification( hetBASE_t * het, uint32 offset ); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h new file mode 100644 index 00000000000..414c09fc037 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h @@ -0,0 +1,70 @@ +/** @file htu.h + * @brief HTU Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HTU_H__ +#define __HTU_H__ + +#include "reg_htu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* HTU General Definitions */ + +#define HTU1PARLOC ( *( volatile uint32 * ) 0xFF4E0200U ) +#define HTU2PARLOC ( *( volatile uint32 * ) 0xFF4C0200U ) + +#define HTU1RAMLOC ( *( volatile uint32 * ) 0xFF4E0000U ) +#define HTU2RAMLOC ( *( volatile uint32 * ) 0xFF4C0000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h new file mode 100644 index 00000000000..7ca60027f51 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h @@ -0,0 +1,1304 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_H_ +#define _HW_EMAC_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_BASE ( 0xFCF78000U ) +#define EMAC_CTRL_BASE ( 0xFCF78800U ) +#define EMAC_CTRL_RAM_BASE ( 0xFC520000U ) + +#define EMAC_TXREVID ( 0x0U ) +#define EMAC_TXCONTROL ( 0x4U ) +#define EMAC_TXTEARDOWN ( 0x8U ) +#define EMAC_RXREVID ( 0x10U ) +#define EMAC_RXCONTROL ( 0x14U ) +#define EMAC_RXTEARDOWN ( 0x18U ) +#define EMAC_TXINTSTATRAW ( 0x80U ) +#define EMAC_TXINTSTATMASKED ( 0x84U ) +#define EMAC_TXINTMASKSET ( 0x88U ) +#define EMAC_TXINTMASKCLEAR ( 0x8CU ) +#define EMAC_MACINVECTOR ( 0x90U ) +#define EMAC_MACEOIVECTOR ( 0x94U ) +#define EMAC_RXINTSTATRAW ( 0xA0U ) +#define EMAC_RXINTSTATMASKED ( 0xA4U ) +#define EMAC_RXINTMASKSET ( 0xA8U ) +#define EMAC_RXINTMASKCLEAR ( 0xACU ) +#define EMAC_MACINTSTATRAW ( 0xB0U ) +#define EMAC_MACINTSTATMASKED ( 0xB4U ) +#define EMAC_MACINTMASKSET ( 0xB8U ) +#define EMAC_MACINTMASKCLEAR ( 0xBCU ) +#define EMAC_RXMBPENABLE ( 0x100U ) +#define EMAC_RXUNICASTSET ( 0x104U ) +#define EMAC_RXUNICASTCLEAR ( 0x108U ) +#define EMAC_RXMAXLEN ( 0x10CU ) +#define EMAC_RXBUFFEROFFSET ( 0x110U ) +#define EMAC_RXFILTERLOWTHRESH ( 0x114U ) +#define EMAC_RXFLOWTHRESH( n ) ( ( uint32 ) 0x120U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXFREEBUFFER( n ) ( ( uint32 ) 0x140U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_MACCONTROL ( 0x160U ) +#define EMAC_MACSTATUS ( 0x164U ) +#define EMAC_EMCONTROL ( 0x168U ) +#define EMAC_FIFOCONTROL ( 0x16CU ) +#define EMAC_MACCONFIG ( 0x170U ) +#define EMAC_SOFTRESET ( 0x174U ) +#define EMAC_MACSRCADDRLO ( 0x1D0U ) +#define EMAC_MACSRCADDRHI ( 0x1D4U ) +#define EMAC_MACHASH1 ( 0x1D8U ) +#define EMAC_MACHASH2 ( 0x1DCU ) +#define EMAC_BOFFTEST ( 0x1E0U ) +#define EMAC_TPACETEST ( 0x1E4U ) +#define EMAC_RXPAUSE ( 0x1E8U ) +#define EMAC_TXPAUSE ( 0x1ECU ) +#define EMAC_RXGOODFRAMES ( 0x200U ) +#define EMAC_RXBCASTFRAMES ( 0x204U ) +#define EMAC_RXMCASTFRAMES ( 0x208U ) +#define EMAC_RXPAUSEFRAMES ( 0x20CU ) +#define EMAC_RXCRCERRORS ( 0x210U ) +#define EMAC_RXALIGNCODEERRORS ( 0x214U ) +#define EMAC_RXOVERSIZED ( 0x218U ) +#define EMAC_RXJABBER ( 0x21CU ) +#define EMAC_RXUNDERSIZED ( 0x220U ) +#define EMAC_RXFRAGMENTS ( 0x224U ) +#define EMAC_RXFILTERED ( 0x228U ) +#define EMAC_RXQOSFILTERED ( 0x22CU ) +#define EMAC_RXOCTETS ( 0x230U ) +#define EMAC_TXGOODFRAMES ( 0x234U ) +#define EMAC_TXBCASTFRAMES ( 0x238U ) +#define EMAC_TXMCASTFRAMES ( 0x23CU ) +#define EMAC_TXPAUSEFRAMES ( 0x240U ) +#define EMAC_TXDEFERRED ( 0x244U ) +#define EMAC_TXCOLLISION ( 0x248U ) +#define EMAC_TXSINGLECOLL ( 0x24CU ) +#define EMAC_TXMULTICOLL ( 0x250U ) +#define EMAC_TXEXCESSIVECOLL ( 0x254U ) +#define EMAC_TXLATECOLL ( 0x258U ) +#define EMAC_TXUNDERRUN ( 0x25CU ) +#define EMAC_TXCARRIERSENSE ( 0x260U ) +#define EMAC_TXOCTETS ( 0x264U ) +#define EMAC_FRAME64 ( 0x268U ) +#define EMAC_FRAME65T127 ( 0x26CU ) +#define EMAC_FRAME128T255 ( 0x270U ) +#define EMAC_FRAME256T511 ( 0x274U ) +#define EMAC_FRAME512T1023 ( 0x278U ) +#define EMAC_FRAME1024TUP ( 0x27CU ) +#define EMAC_NETOCTETS ( 0x208U ) +#define EMAC_RXSOFOVERRUNS ( 0x284U ) +#define EMAC_RXMOFOVERRUNS ( 0x288U ) +#define EMAC_RXDMAOVERRUNS ( 0x28CU ) +#define EMAC_MACADDRLO ( 0x500U ) +#define EMAC_MACADDRHI ( 0x504U ) +#define EMAC_MACINDEX ( 0x508U ) +#define EMAC_TXHDP( n ) ( ( uint32 ) 0x600U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXHDP( n ) ( ( uint32 ) 0x620U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_TXCP( n ) ( ( uint32 ) 0x640U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXCP( n ) ( ( uint32 ) 0x660U + ( uint32 ) ( ( n ) * 4U ) ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* TXREVID */ + +#define EMAC_TXREVID_TXREV ( 0xFFFFFFFFU ) +#define EMAC_TXREVID_TXREV_SHIFT ( 0x00000000U ) + +/* TXCONTROL */ + +#define EMAC_TXCONTROL_TXEN ( 0x00000001U ) +#define EMAC_TXCONTROL_TXEN_SHIFT ( 0x00000000U ) +#define EMAC_TXCONTROL_TXDIS ( 0x00000000U ) + +/* TXTEARDOWN */ + +#define EMAC_TXTEARDOWN_TXTDNCH ( 0x00000007U ) +#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 ( 0x00000007U ) + +/* RXREVID */ + +#define EMAC_RXREVID_RXREV ( 0xFFFFFFFFU ) +#define EMAC_RXREVID_RXREV_SHIFT ( 0x00000000U ) + +/* RXCONTROL */ + +#define EMAC_RXCONTROL_RXEN ( 0x00000001U ) +#define EMAC_RXCONTROL_RXEN_SHIFT ( 0x00000000U ) +#define EMAC_RXCONTROL_RXDIS ( 0x00000000U ) + +/* RXTEARDOWN */ + +#define EMAC_RXTEARDOWN_RXTDNCH ( 0x00000007U ) +#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 ( 0x00000007U ) + +/* TXINTSTATRAW */ + +#define EMAC_TXINTSTATRAW_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATRAW_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATRAW_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATRAW_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATRAW_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATRAW_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATRAW_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATRAW_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTSTATMASKED */ + +#define EMAC_TXINTSTATMASKED_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATMASKED_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATMASKED_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATMASKED_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATMASKED_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATMASKED_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATMASKED_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATMASKED_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTMASKSET */ + +#define EMAC_TXINTMASKSET_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKSET_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKSET_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKSET_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKSET_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKSET_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKSET_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKSET_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKSET_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKSET_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKSET_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKSET_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKSET_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKSET_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKSET_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKSET_TX0MASK_SHIFT ( 0x00000000U ) + +/* TXINTMASKCLEAR */ + +#define EMAC_TXINTMASKCLEAR_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKCLEAR_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKCLEAR_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKCLEAR_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKCLEAR_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKCLEAR_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKCLEAR_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKCLEAR_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT ( 0x00000000U ) + +/* MACINVECTOR */ + +#define EMAC_MACINVECTOR_STATPEND ( 0x08000000U ) +#define EMAC_MACINVECTOR_STATPEND_SHIFT ( 0x0000001BU ) + +#define EMAC_MACINVECTOR_HOSTPEND ( 0x04000000U ) +#define EMAC_MACINVECTOR_HOSTPEND_SHIFT ( 0x0000001AU ) + +#define EMAC_MACINVECTOR_LINKINT0 ( 0x02000000U ) +#define EMAC_MACINVECTOR_LINKINT0_SHIFT ( 0x00000019U ) + +#define EMAC_MACINVECTOR_USERINT0 ( 0x01000000U ) +#define EMAC_MACINVECTOR_USERINT0_SHIFT ( 0x00000018U ) + +#define EMAC_MACINVECTOR_TXPEND ( 0x00FF0000U ) +#define EMAC_MACINVECTOR_TXPEND_SHIFT ( 0x00000010U ) + +#define EMAC_MACINVECTOR_RXTHRESHPEND ( 0x0000FF00U ) +#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_MACINVECTOR_RXPEND ( 0x000000FFU ) +#define EMAC_MACINVECTOR_RXPEND_SHIFT ( 0x00000000U ) + +/* MACEOIVECTOR */ + +#define EMAC_MACEOIVECTOR_INTVECT ( 0x0000001FU ) +#define EMAC_MACEOIVECTOR_INTVECT_SHIFT ( 0x00000000U ) +/*----INTVECT Tokens----*/ +#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH ( 0x00000000U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0RX ( 0x00000001U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0TX ( 0x00000002U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0MISC ( 0x00000003U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH ( 0x00000004U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RX ( 0x00000005U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1TX ( 0x00000006U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1MISC ( 0x00000007U ) + +/* RXINTSTATRAW */ + +#define EMAC_RXINTSTATRAW_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATRAW_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATRAW_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATRAW_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATRAW_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATRAW_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATRAW_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATRAW_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATRAW_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATRAW_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATRAW_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATRAW_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATRAW_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATRAW_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATRAW_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATRAW_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTSTATMASKED */ + +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATMASKED_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATMASKED_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATMASKED_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATMASKED_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATMASKED_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATMASKED_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATMASKED_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATMASKED_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTMASKSET */ + +#define EMAC_RXINTMASKSET_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKSET_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKSET_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKSET_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKSET_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKSET_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKSET_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKSET_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKSET_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKSET_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKSET_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKSET_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKSET_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKSET_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKSET_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKSET_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKSET_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKSET_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKSET_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKSET_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKSET_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKSET_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKSET_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKSET_RX0MASK_SHIFT ( 0x00000000U ) + +/* RXINTMASKCLEAR */ + +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKCLEAR_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKCLEAR_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKCLEAR_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKCLEAR_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKCLEAR_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKCLEAR_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKCLEAR_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKCLEAR_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT ( 0x00000000U ) + +/* MACINTSTATRAW */ + +#define EMAC_MACINTSTATRAW_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATRAW_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATRAW_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTSTATMASKED */ + +#define EMAC_MACINTSTATMASKED_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATMASKED_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTMASKSET */ + +#define EMAC_MACINTMASKSET_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKSET_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKSET_STATMASK_SHIFT ( 0x00000000U ) + +/* MACINTMASKCLEAR */ + +#define EMAC_MACINTMASKCLEAR_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKCLEAR_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT ( 0x00000000U ) + +/* RXMBPENABLE */ + +#define EMAC_RXMBPENABLE_RXPASSCRC ( 0x40000000U ) +#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT ( 0x0000001EU ) +#define EMAC_RXMBPENABLE_RXQOSEN ( 0x20000000U ) +#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT ( 0x0000001DU ) +#define EMAC_RXMBPENABLE_RXNOCHAIN ( 0x10000000U ) +#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT ( 0x0000001CU ) +#define EMAC_RXMBPENABLE_RXCMFEN ( 0x01000000U ) +#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT ( 0x00000018U ) +#define EMAC_RXMBPENABLE_RXCSFEN ( 0x00800000U ) +#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT ( 0x00000017U ) +#define EMAC_RXMBPENABLE_RXCEFEN ( 0x00400000U ) +#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT ( 0x00000016U ) +#define EMAC_RXMBPENABLE_RXCAFEN ( 0x00200000U ) +#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT ( 0x00000015U ) +/*----RXCAFEN Tokens----*/ +#define EMAC_RXMBPENABLE_RXPROMCH ( 0x00070000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT ( 0x00000010U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXBROADEN ( 0x00002000U ) +#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT ( 0x0000000DU ) +#define EMAC_RXMBPENABLE_RXBROADCH ( 0x00000700U ) +#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT ( 0x00000008U ) +/*----RXBROADCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXMULTEN ( 0x00000020U ) +#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH ( 0x00000007U ) +#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT ( 0x00000000U ) +/*----RXMULTCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 ( 0x00000007U ) + +/* RXUNICASTSET */ + +#define EMAC_RXUNICASTSET_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTSET_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTSET_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTSET_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTSET_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXUNICASTCLEAR */ + +#define EMAC_RXUNICASTCLEAR_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXMAXLEN */ + +#define EMAC_RXMAXLEN_RXMAXLEN ( 0x0000FFFFU ) +#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT ( 0x00000000U ) + +/* RXBUFFEROFFSET */ + +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET ( 0x0000FFFFU ) +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT ( 0x00000000U ) + +/* RXFILTERLOWTHRESH */ + +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH ( 0x000000FFU ) +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FLOWTHRESH */ + +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX1FLOWTHRESH */ + +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX2FLOWTHRESH */ + +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX3FLOWTHRESH */ + +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX4FLOWTHRESH */ + +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX5FLOWTHRESH */ + +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX6FLOWTHRESH */ + +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX7FLOWTHRESH */ + +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FREEBUFFER */ + +#define EMAC_RX0FREEBUFFER_RX0FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT ( 0x00000000U ) + +/* RX1FREEBUFFER */ + +#define EMAC_RX1FREEBUFFER_RX1FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT ( 0x00000000U ) + +/* RX2FREEBUFFER */ + +#define EMAC_RX2FREEBUFFER_RX2FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT ( 0x00000000U ) + +/* RX3FREEBUFFER */ + +#define EMAC_RX3FREEBUFFER_RX3FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT ( 0x00000000U ) + +/* RX4FREEBUFFER */ + +#define EMAC_RX4FREEBUFFER_RX4FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT ( 0x00000000U ) + +/* RX5FREEBUFFER */ + +#define EMAC_RX5FREEBUFFER_RX5FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT ( 0x00000000U ) + +/* RX6FREEBUFFER */ + +#define EMAC_RX6FREEBUFFER_RX6FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT ( 0x00000000U ) + +/* RX7FREEBUFFER */ + +#define EMAC_RX7FREEBUFFER_RX7FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT ( 0x00000000U ) + +/* MACCONTROL */ + +#define EMAC_MACCONTROL_RMIISPEED ( 0x00008000U ) +#define EMAC_MACCONTROL_RMIISPEED_SHIFT ( 0x0000000FU ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK ( 0x00004000U ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT ( 0x0000000EU ) +#define EMAC_MACCONTROL_RXOWNERSHIP ( 0x00002000U ) +#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT ( 0x0000000DU ) +#define EMAC_MACCONTROL_CMDIDLE ( 0x00000800U ) +#define EMAC_MACCONTROL_CMDIDLE_SHIFT ( 0x0000000BU ) +#define EMAC_MACCONTROL_TXSHORTGAPEN ( 0x00000400U ) +#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT ( 0x0000000AU ) +#define EMAC_MACCONTROL_TXPTYPE ( 0x00000200U ) +#define EMAC_MACCONTROL_TXPTYPE_SHIFT ( 0x00000009U ) +#define EMAC_MACCONTROL_TXPACE ( 0x00000040U ) +#define EMAC_MACCONTROL_TXPACE_SHIFT ( 0x00000006U ) +#define EMAC_MACCONTROL_GMIIEN ( 0x00000020U ) +#define EMAC_MACCONTROL_GMIIEN_SHIFT ( 0x00000005U ) +#define EMAC_MACCONTROL_TXFLOWEN ( 0x00000010U ) +#define EMAC_MACCONTROL_TXFLOWEN_SHIFT ( 0x00000004U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN ( 0x00000008U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT ( 0x00000003U ) +#define EMAC_MACCONTROL_LOOPBACK ( 0x00000002U ) +#define EMAC_MACCONTROL_LOOPBACK_SHIFT ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT ( 0x00000000U ) + +/* MACSTATUS */ + +#define EMAC_MACSTATUS_IDLE ( 0x80000000U ) +#define EMAC_MACSTATUS_IDLE_SHIFT ( 0x0000001FU ) +#define EMAC_MACSTATUS_TXERRCODE ( 0x00F00000U ) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT ( 0x00000014U ) +/*----TXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_TXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCODE_SOPERROR ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCODE_NOEOP ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLPTR ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLEN ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCODE_LENERROR ( 0x00000006U ) + +#define EMAC_MACSTATUS_TXERRCH ( 0x00070000U ) +#define EMAC_MACSTATUS_TXERRCH_SHIFT ( 0x00000010U ) +/*----TXERRCH Tokens----*/ +#define EMAC_MACSTATUS_TXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_TXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXERRCODE ( 0x0000F000U ) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT ( 0x0000000CU ) +/*----RXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_RXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCODE_NULLPTR ( 0x00000004U ) + +#define EMAC_MACSTATUS_RXERRCH ( 0x00000700U ) +#define EMAC_MACSTATUS_RXERRCH_SHIFT ( 0x00000008U ) +/*----RXERRCH Tokens----*/ +#define EMAC_MACSTATUS_RXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_RXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_RXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_RXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_RXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_RXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXQOSACT ( 0x00000004U ) +#define EMAC_MACSTATUS_RXQOSACT_SHIFT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT_SHIFT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT_SHIFT ( 0x00000000U ) + +/* EMCONTROL */ + +#define EMAC_EMCONTROL_SOFT ( 0x00000002U ) +#define EMAC_EMCONTROL_SOFT_SHIFT ( 0x00000001U ) + +#define EMAC_EMCONTROL_FREE ( 0x00000001U ) +#define EMAC_EMCONTROL_FREE_SHIFT ( 0x00000000U ) + +/* FIFOCONTROL */ + +#define EMAC_FIFOCONTROL_TXCELLTHRESH ( 0x00000003U ) +#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT ( 0x00000000U ) + +/* MACCONFIG */ + +#define EMAC_MACCONFIG_TXCELLDEPTH ( 0xFF000000U ) +#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT ( 0x00000018U ) + +#define EMAC_MACCONFIG_RXCELLDEPTH ( 0x00FF0000U ) +#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT ( 0x00000010U ) + +#define EMAC_MACCONFIG_ADDRESSTYPE ( 0x0000FF00U ) +#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT ( 0x00000008U ) + +#define EMAC_MACCONFIG_MACCFIG ( 0x000000FFU ) +#define EMAC_MACCONFIG_MACCFIG_SHIFT ( 0x00000000U ) + +/* SOFTRESET */ + +#define EMAC_SOFTRESET_SOFTRESET ( 0x00000001U ) +#define EMAC_SOFTRESET_SOFTRESET_SHIFT ( 0x00000000U ) + +/* MACSRCADDRLO */ + +#define EMAC_MACSRCADDRLO_MACSRCADDR0 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1 ( 0x000000FFU ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT ( 0x00000000U ) + +/* MACSRCADDRHI */ + +#define EMAC_MACSRCADDRHI_MACSRCADDR2 ( 0xFF000000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR3 ( 0x00FF0000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR4 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR5 ( 0x000000FFU ) +#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT ( 0x00000000U ) + +/* MACHASH1 */ + +#define EMAC_MACHASH1_MACHASH1 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH1_MACHASH1_SHIFT ( 0x00000000U ) + +/* MACHASH2 */ + +#define EMAC_MACHASH2_MACHASH2 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH2_MACHASH2_SHIFT ( 0x00000000U ) + +/* BOFFTEST */ + +#define EMAC_BOFFTEST_RNDNUM ( 0x03FF0000U ) +#define EMAC_BOFFTEST_RNDNUM_SHIFT ( 0x00000010U ) + +#define EMAC_BOFFTEST_COLLCOUNT ( 0x0000F000U ) +#define EMAC_BOFFTEST_COLLCOUNT_SHIFT ( 0x0000000CU ) + +#define EMAC_BOFFTEST_TXBACKOFF ( 0x000003FFU ) +#define EMAC_BOFFTEST_TXBACKOFF_SHIFT ( 0x00000000U ) + +/* TPACETEST */ + +#define EMAC_TPACETEST_PACEVAL ( 0x0000001FU ) +#define EMAC_TPACETEST_PACEVAL_SHIFT ( 0x00000000U ) + +/* RXPAUSE */ + +#define EMAC_RXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_RXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* TXPAUSE */ + +#define EMAC_TXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_TXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* RXGOODFRAMES */ + +#define EMAC_RXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXBCASTFRAMES */ + +#define EMAC_RXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXMCASTFRAMES */ + +#define EMAC_RXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXPAUSEFRAMES */ + +#define EMAC_RXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXCRCERRORS */ + +#define EMAC_RXCRCERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXCRCERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXALIGNCODEERRORS */ + +#define EMAC_RXALIGNCODEERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXOVERSIZED */ + +#define EMAC_RXOVERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOVERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXJABBER */ + +#define EMAC_RXJABBER_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXJABBER_COUNT_SHIFT ( 0x00000000U ) + +/* RXUNDERSIZED */ + +#define EMAC_RXUNDERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXUNDERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXFRAGMENTS */ + +#define EMAC_RXFRAGMENTS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFRAGMENTS_COUNT_SHIFT ( 0x00000000U ) + +/* RXFILTERED */ + +#define EMAC_RXFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXQOSFILTERED */ + +#define EMAC_RXQOSFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXQOSFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXOCTETS */ + +#define EMAC_RXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* TXGOODFRAMES */ + +#define EMAC_TXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXBCASTFRAMES */ + +#define EMAC_TXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXMCASTFRAMES */ + +#define EMAC_TXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXPAUSEFRAMES */ + +#define EMAC_TXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXDEFERRED */ + +#define EMAC_TXDEFERRED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXDEFERRED_COUNT_SHIFT ( 0x00000000U ) + +/* TXCOLLISION */ + +#define EMAC_TXCOLLISION_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCOLLISION_COUNT_SHIFT ( 0x00000000U ) + +/* TXSINGLECOLL */ + +#define EMAC_TXSINGLECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXSINGLECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXMULTICOLL */ + +#define EMAC_TXMULTICOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMULTICOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXEXCESSIVECOLL */ + +#define EMAC_TXEXCESSIVECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXLATECOLL */ + +#define EMAC_TXLATECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXLATECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXUNDERRUN */ + +#define EMAC_TXUNDERRUN_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXUNDERRUN_COUNT_SHIFT ( 0x00000000U ) + +/* TXCARRIERSENSE */ + +#define EMAC_TXCARRIERSENSE_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCARRIERSENSE_COUNT_SHIFT ( 0x00000000U ) + +/* TXOCTETS */ + +#define EMAC_TXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME64 */ + +#define EMAC_FRAME64_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME64_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME65T127 */ + +#define EMAC_FRAME65T127_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME65T127_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME128T255 */ + +#define EMAC_FRAME128T255_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME128T255_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME256T511 */ + +#define EMAC_FRAME256T511_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME256T511_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME512T1023 */ + +#define EMAC_FRAME512T1023_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME512T1023_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME1024TUP */ + +#define EMAC_FRAME1024TUP_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME1024TUP_COUNT_SHIFT ( 0x00000000U ) + +/* NETOCTETS */ + +#define EMAC_NETOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_NETOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* RXSOFOVERRUNS */ + +#define EMAC_RXSOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXMOFOVERRUNS */ + +#define EMAC_RXMOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXDMAOVERRUNS */ + +#define EMAC_RXDMAOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* MACADDRLO */ + +#define EMAC_MACADDRLO_VALID ( 0x00100000U ) +#define EMAC_MACADDRLO_VALID_SHIFT ( 0x00000014U ) +#define EMAC_MACADDRLO_MATCHFILT ( 0x00080000U ) +#define EMAC_MACADDRLO_MATCHFILT_SHIFT ( 0x00000013U ) +#define EMAC_MACADDRLO_CHANNEL ( 0x00070000U ) +#define EMAC_MACADDRLO_CHANNEL_SHIFT ( 0x00000010U ) +#define EMAC_MACADDRLO_MACADDR0 ( 0x0000FF00U ) +#define EMAC_MACADDRLO_MACADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACADDRLO_MACADDR1 ( 0x000000FFU ) +#define EMAC_MACADDRLO_MACADDR1_SHIFT ( 0x00000000U ) + +/* MACADDRHI */ + +#define EMAC_MACADDRHI_MACADDR2 ( 0xFF000000U ) +#define EMAC_MACADDRHI_MACADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACADDRHI_MACADDR3 ( 0x00FF0000U ) +#define EMAC_MACADDRHI_MACADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACADDRHI_MACADDR4 ( 0x0000FF00U ) +#define EMAC_MACADDRHI_MACADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACADDRHI_MACADDR5 ( 0x000000FFU ) +#define EMAC_MACADDRHI_MACADDR5_SHIFT ( 0x00000000U ) + +/* MACINDEX */ + +#define EMAC_MACINDEX_MACINDEX ( 0x0000001FU ) +#define EMAC_MACINDEX_MACINDEX_SHIFT ( 0x00000000U ) + +/* TX0HDP */ + +#define EMAC_TX0HDP_TX0HDP ( 0xFFFFFFFFU ) +#define EMAC_TX0HDP_TX0HDP_SHIFT ( 0x00000000U ) + +/* TX1HDP */ + +#define EMAC_TX1HDP_TX1HDP ( 0xFFFFFFFFU ) +#define EMAC_TX1HDP_TX1HDP_SHIFT ( 0x00000000U ) + +/* TX2HDP */ + +#define EMAC_TX2HDP_TX2HDP ( 0xFFFFFFFFU ) +#define EMAC_TX2HDP_TX2HDP_SHIFT ( 0x00000000U ) + +/* TX3HDP */ + +#define EMAC_TX3HDP_TX3HDP ( 0xFFFFFFFFU ) +#define EMAC_TX3HDP_TX3HDP_SHIFT ( 0x00000000U ) + +/* TX4HDP */ + +#define EMAC_TX4HDP_TX4HDP ( 0xFFFFFFFFU ) +#define EMAC_TX4HDP_TX4HDP_SHIFT ( 0x00000000U ) + +/* TX5HDP */ + +#define EMAC_TX5HDP_TX5HDP ( 0xFFFFFFFFU ) +#define EMAC_TX5HDP_TX5HDP_SHIFT ( 0x00000000U ) + +/* TX6HDP */ + +#define EMAC_TX6HDP_TX6HDP ( 0xFFFFFFFFU ) +#define EMAC_TX6HDP_TX6HDP_SHIFT ( 0x00000000U ) + +/* TX7HDP */ + +#define EMAC_TX7HDP_TX7HDP ( 0xFFFFFFFFU ) +#define EMAC_TX7HDP_TX7HDP_SHIFT ( 0x00000000U ) + +/* RX0HDP */ + +#define EMAC_RX0HDP_RX0HDP ( 0xFFFFFFFFU ) +#define EMAC_RX0HDP_RX0HDP_SHIFT ( 0x00000000U ) + +/* RX1HDP */ + +#define EMAC_RX1HDP_RX1HDP ( 0xFFFFFFFFU ) +#define EMAC_RX1HDP_RX1HDP_SHIFT ( 0x00000000U ) + +/* RX2HDP */ + +#define EMAC_RX2HDP_RX2HDP ( 0xFFFFFFFFU ) +#define EMAC_RX2HDP_RX2HDP_SHIFT ( 0x00000000U ) + +/* RX3HDP */ + +#define EMAC_RX3HDP_RX3HDP ( 0xFFFFFFFFU ) +#define EMAC_RX3HDP_RX3HDP_SHIFT ( 0x00000000U ) + +/* RX4HDP */ + +#define EMAC_RX4HDP_RX4HDP ( 0xFFFFFFFFU ) +#define EMAC_RX4HDP_RX4HDP_SHIFT ( 0x00000000U ) + +/* RX5HDP */ + +#define EMAC_RX5HDP_RX5HDP ( 0xFFFFFFFFU ) +#define EMAC_RX5HDP_RX5HDP_SHIFT ( 0x00000000U ) + +/* RX6HDP */ + +#define EMAC_RX6HDP_RX6HDP ( 0xFFFFFFFFU ) +#define EMAC_RX6HDP_RX6HDP_SHIFT ( 0x00000000U ) + +/* RX7HDP */ + +#define EMAC_RX7HDP_RX7HDP ( 0xFFFFFFFFU ) +#define EMAC_RX7HDP_RX7HDP_SHIFT ( 0x00000000U ) + +/* TX0CP */ + +#define EMAC_TX0CP_TX0CP ( 0xFFFFFFFFU ) +#define EMAC_TX0CP_TX0CP_SHIFT ( 0x00000000U ) + +/* TX1CP */ + +#define EMAC_TX1CP_TX1CP ( 0xFFFFFFFFU ) +#define EMAC_TX1CP_TX1CP_SHIFT ( 0x00000000U ) + +/* TX2CP */ + +#define EMAC_TX2CP_TX2CP ( 0xFFFFFFFFU ) +#define EMAC_TX2CP_TX2CP_SHIFT ( 0x00000000U ) + +/* TX3CP */ + +#define EMAC_TX3CP_TX3CP ( 0xFFFFFFFFU ) +#define EMAC_TX3CP_TX3CP_SHIFT ( 0x00000000U ) + +/* TX4CP */ + +#define EMAC_TX4CP_TX4CP ( 0xFFFFFFFFU ) +#define EMAC_TX4CP_TX4CP_SHIFT ( 0x00000000U ) + +/* TX5CP */ + +#define EMAC_TX5CP_TX5CP ( 0xFFFFFFFFU ) +#define EMAC_TX5CP_TX5CP_SHIFT ( 0x00000000U ) + +/* TX6CP */ + +#define EMAC_TX6CP_TX6CP ( 0xFFFFFFFFU ) +#define EMAC_TX6CP_TX6CP_SHIFT ( 0x00000000U ) + +/* TX7CP */ + +#define EMAC_TX7CP_TX7CP ( 0xFFFFFFFFU ) +#define EMAC_TX7CP_TX7CP_SHIFT ( 0x00000000U ) + +/* RX0CP */ + +#define EMAC_RX0CP_RX0CP ( 0xFFFFFFFFU ) +#define EMAC_RX0CP_RX0CP_SHIFT ( 0x00000000U ) + +/* RX1CP */ + +#define EMAC_RX1CP_RX1CP ( 0xFFFFFFFFU ) +#define EMAC_RX1CP_RX1CP_SHIFT ( 0x00000000U ) + +/* RX2CP */ + +#define EMAC_RX2CP_RX2CP ( 0xFFFFFFFFU ) +#define EMAC_RX2CP_RX2CP_SHIFT ( 0x00000000U ) + +/* RX3CP */ + +#define EMAC_RX3CP_RX3CP ( 0xFFFFFFFFU ) +#define EMAC_RX3CP_RX3CP_SHIFT ( 0x00000000U ) + +/* RX4CP */ + +#define EMAC_RX4CP_RX4CP ( 0xFFFFFFFFU ) +#define EMAC_RX4CP_RX4CP_SHIFT ( 0x00000000U ) + +/* RX5CP */ + +#define EMAC_RX5CP_RX5CP ( 0xFFFFFFFFU ) +#define EMAC_RX5CP_RX5CP_SHIFT ( 0x00000000U ) + +/* RX6CP */ + +#define EMAC_RX6CP_RX6CP ( 0xFFFFFFFFU ) +#define EMAC_RX6CP_RX6CP_SHIFT ( 0x00000000U ) + +/* RX7CP */ + +#define EMAC_RX7CP_RX7CP ( 0xFFFFFFFFU ) +#define EMAC_RX7CP_RX7CP_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h new file mode 100644 index 00000000000..764e8f748f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h @@ -0,0 +1,92 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_CTRL_H_ +#define _HW_EMAC_CTRL_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_CTRL_REVID ( 0x0U ) +#define EMAC_CTRL_SOFTRESET ( 0x4U ) +#define EMAC_CTRL_INTCONTROL ( 0xCU ) +#define EMAC_CTRL_C0RXTHRESHEN ( 0x10U ) +#define EMAC_CTRL_CnRXEN( n ) ( ( uint32 ) 0x14u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnTXEN( n ) ( ( uint32 ) 0x18u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnMISCEN( n ) \ + ( ( uint32 ) 0x1Cu + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnRXTHRESHEN( n ) \ + ( ( uint32 ) 0x20u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_C0RXTHRESHSTAT ( 0x40U ) +#define EMAC_CTRL_C0RXSTAT ( 0x44U ) +#define EMAC_CTRL_C0TXSTAT ( 0x48U ) +#define EMAC_CTRL_C0MISCSTAT ( 0x4CU ) +#define EMAC_CTRL_C1RXTHRESHSTAT ( 0x50U ) +#define EMAC_CTRL_C1RXSTAT ( 0x54U ) +#define EMAC_CTRL_C1TXSTAT ( 0x58U ) +#define EMAC_CTRL_C1MISCSTAT ( 0x5CU ) +#define EMAC_CTRL_C2RXTHRESHSTAT ( 0x60U ) +#define EMAC_CTRL_C2RXSTAT ( 0x64U ) +#define EMAC_CTRL_C2TXSTAT ( 0x68U ) +#define EMAC_CTRL_C2MISCSTAT ( 0x6CU ) +#define EMAC_CTRL_C0RXIMAX ( 0x70U ) +#define EMAC_CTRL_C0TXIMAX ( 0x74U ) +#define EMAC_CTRL_C1RXIMAX ( 0x78U ) +#define EMAC_CTRL_C1TXIMAX ( 0x7CU ) +#define EMAC_CTRL_C2RXIMAX ( 0x80U ) +#define EMAC_CTRL_C2TXIMAX ( 0x84U ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h new file mode 100644 index 00000000000..d12203353d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h @@ -0,0 +1,235 @@ +/* + * hw_mdio.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_MDIO_H_ +#define _HW_MDIO_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define MDIO_BASE ( 0xFCF78900U ) + +#define MDIO_REVID ( 0x0U ) +#define MDIO_CONTROL ( 0x4U ) +#define MDIO_ALIVE ( 0x8U ) +#define MDIO_LINK ( 0xCU ) +#define MDIO_LINKINTRAW ( 0x10U ) +#define MDIO_LINKINTMASKED ( 0x14U ) +#define MDIO_USERINTRAW ( 0x20U ) +#define MDIO_USERINTMASKED ( 0x24U ) +#define MDIO_USERINTMASKSET ( 0x28U ) +#define MDIO_USERINTMASKCLEAR ( 0x2CU ) +#define MDIO_USERACCESS0 ( 0x80U ) +#define MDIO_USERPHYSEL0 ( 0x84U ) +#define MDIO_USERACCESS1 ( 0x88U ) +#define MDIO_USERPHYSEL1 ( 0x8CU ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REVID */ + +#define MDIO_REVID_REV ( 0xFFFFFFFFU ) +#define MDIO_REVID_REV_SHIFT ( 0x00000000U ) + +/* CONTROL */ + +#define MDIO_CONTROL_IDLE ( 0x80000000U ) +#define MDIO_CONTROL_IDLE_SHIFT ( 0x0000001FU ) +/*----IDLE Tokens----*/ +#define MDIO_CONTROL_IDLE_NO ( 0x00000000U ) +#define MDIO_CONTROL_IDLE_YES ( 0x00000001U ) + +#define MDIO_CONTROL_ENABLE ( 0x40000000U ) +#define MDIO_CONTROL_ENABLE_SHIFT ( 0x0000001EU ) + +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL ( 0x1F000000U ) +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT ( 0x00000018U ) + +#define MDIO_CONTROL_PREAMBLE ( 0x00100000U ) +#define MDIO_CONTROL_PREAMBLE_SHIFT ( 0x00000014U ) +/*----PREAMBLE Tokens----*/ + +#define MDIO_CONTROL_FAULT ( 0x00080000U ) +#define MDIO_CONTROL_FAULT_SHIFT ( 0x00000013U ) + +#define MDIO_CONTROL_FAULTENB ( 0x00040000U ) +#define MDIO_CONTROL_FAULTENB_SHIFT ( 0x00000012U ) +/*----FAULTENB Tokens----*/ + +#define MDIO_CONTROL_CLKDIV ( 0x0000FFFFU ) +#define MDIO_CONTROL_CLKDIV_SHIFT ( 0x00000000U ) +/*----CLKDIV Tokens----*/ + +/* ALIVE */ + +#define MDIO_ALIVE_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_ALIVE_REGVAL_SHIFT ( 0x00000000U ) + +/* LINK */ + +#define MDIO_LINK_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_LINK_REGVAL_SHIFT ( 0x00000000U ) + +/* LINKINTRAW */ + +#define MDIO_LINKINTRAW_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTRAW_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTRAW_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTRAW_USERPHY0_SHIFT ( 0x00000000U ) + +/* LINKINTMASKED */ + +#define MDIO_LINKINTMASKED_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTMASKED_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTMASKED_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTMASKED_USERPHY0_SHIFT ( 0x00000000U ) + +/* USERINTRAW */ + +#define MDIO_USERINTRAW_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTRAW_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTRAW_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTRAW_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKED */ + +#define MDIO_USERINTMASKED_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKED_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKED_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKED_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKSET */ + +#define MDIO_USERINTMASKSET_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKSET_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKCLEAR */ + +#define MDIO_USERINTMASKCLEAR_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKCLEAR_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERACCESS0 */ + +#define MDIO_USERACCESS0_GO ( 0x80000000U ) +#define MDIO_USERACCESS0_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS0_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS0_READ ( 0x00000000U ) +#define MDIO_USERACCESS0_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS0_ACK ( 0x20000000U ) +#define MDIO_USERACCESS0_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS0_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS0_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS0_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS0_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS0_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS0_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL0 */ + +#define MDIO_USERPHYSEL0_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL0_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL0_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL0_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USERACCESS1 */ + +#define MDIO_USERACCESS1_GO ( 0x80000000U ) +#define MDIO_USERACCESS1_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS1_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS1_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS1_ACK ( 0x20000000U ) +#define MDIO_USERACCESS1_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS1_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS1_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS1_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS1_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS1_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS1_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL1 */ + +#define MDIO_USERPHYSEL1_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL1_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL1_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL1_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h new file mode 100644 index 00000000000..f1417768169 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h @@ -0,0 +1,80 @@ +/* + * hw_reg_access.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_REG_ACCESS_H_ +#define _HW_REG_ACCESS_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * + * Macros for hardware access, both direct and via the bit-band region. + * + *****************************************************************************/ +#define HWREG( x ) ( *( ( volatile uint32 * ) ( x ) ) ) +#define HWREGH( x ) ( *( ( volatile uint16 * ) ( x ) ) ) +#define HWREGB( x ) ( *( ( volatile uint8 * ) ( x ) ) ) +#define HWREGBITW( x, b ) \ + ( HWREG( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITH( x, b ) \ + ( HWREGH( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITB( x, b ) \ + ( HWREGB( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HW_TYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h new file mode 100644 index 00000000000..5cb77563052 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h @@ -0,0 +1,290 @@ +/** @file I2C.h + * @brief I2C Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +#include "reg_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum i2cMode + * @brief Alias names for i2c modes + * This enumeration is used to provide alias names for I2C modes: + */ +enum i2cMode +{ + I2C_FD_FORMAT = 0x0008U, /* Free Data Format */ + I2C_START_BYTE = 0x0010U, + I2C_RESET_OUT = 0x0020U, + I2C_RESET_IN = 0x0000U, + I2C_DLOOPBACK = 0x0040U, + I2C_REPEATMODE = 0x0080U, /* In Master Mode only */ + I2C_10BIT_AMODE = 0x0100U, + I2C_7BIT_AMODE = 0x0000U, + I2C_TRANSMITTER = 0x0200U, + I2C_RECEIVER = 0x0000U, + I2C_MASTER = 0x0400U, + I2C_SLAVE = 0x0000U, + I2C_STOP_COND = 0x0800U, /* In Master Mode only */ + I2C_START_COND = 0x2000U, /* In Master Mode only */ + I2C_FREE_RUN = 0x4000U, + I2C_NACK_MODE = 0x8000U +}; + +/** @enum i2cBitCount + * @brief Alias names for i2c bit count + * This enumeration is used to provide alias names for I2C bit count: + */ +enum i2cBitCount +{ + I2C_2_BIT = 0x2U, + I2C_3_BIT = 0x3U, + I2C_4_BIT = 0x4U, + I2C_5_BIT = 0x5U, + I2C_6_BIT = 0x6U, + I2C_7_BIT = 0x7U, + I2C_8_BIT = 0x0U +}; + +/** @enum i2cIntFlags + * @brief Interrupt Flag Definitions + * + * Used with I2CEnableNotification, I2CDisableNotification + */ +enum i2cIntFlags +{ + I2C_AL_INT = 0x0001U, /* arbitration lost */ + I2C_NACK_INT = 0x0002U, /* no acknowledgment */ + I2C_ARDY_INT = 0x0004U, /* access ready */ + I2C_RX_INT = 0x0008U, /* receive data ready */ + I2C_TX_INT = 0x0010U, /* transmit data ready */ + I2C_SCD_INT = 0x0020U, /* stop condition detect */ + I2C_AAS_INT = 0x0040U /* address as slave */ +}; + +/** @enum i2cStatFlags + * @brief Interrupt Status Definitions + * + */ +enum i2cStatFlags +{ + I2C_AL = 0x0001U, /* arbitration lost */ + I2C_NACK = 0x0002U, /* no acknowledgement */ + I2C_ARDY = 0x0004U, /* access ready */ + I2C_RX = 0x0008U, /* receive data ready */ + I2C_TX = 0x0010U, /* transmit data ready */ + I2C_SCD = 0x0020U, /* stop condition detect */ + I2C_AD0 = 0x0100U, /* address Zero Status */ + I2C_AAS = 0x0200U, /* address as slave */ + I2C_XSMT = 0x0400U, /* Transmit shift empty not */ + I2C_RXFULL = 0x0800U, /* receive full */ + I2C_BUSBUSY = 0x1000U, /* bus busy */ + I2C_NACKSNT = 0x2000U, /* No Ack Sent */ + I2C_SDIR = 0x4000U /* Slave Direction */ +}; + +/** @enum i2cDMA + * @brief I2C DMA definitions + * + * Used before i2c transfer + */ +enum i2cDMA +{ + I2C_TXDMA = 0x20U, + I2C_RXDMA = 0x10U +}; + +/* Configuration registers */ +typedef struct i2c_config_reg +{ + uint32 CONFIG_OAR; + uint32 CONFIG_IMR; + uint32 CONFIG_CLKL; + uint32 CONFIG_CLKH; + uint32 CONFIG_CNT; + uint32 CONFIG_SAR; + uint32 CONFIG_MDR; + uint32 CONFIG_EMDR; + uint32 CONFIG_PSC; + uint32 CONFIG_DMAC; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; +} i2c_config_reg_t; + +/* Configuration registers initial value for I2C*/ +#define I2C1_OAR_CONFIGVALUE 0x00000000U +#define I2C1_IMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( ( uint32 ) 0U ) ) + +#define I2C1_CLKL_CONFIGVALUE 37U +#define I2C1_CLKH_CONFIGVALUE 37U +#define I2C1_CNT_CONFIGVALUE 8U +#define I2C1_SAR_CONFIGVALUE 0x000003FFU +#define I2C1_MDR_CONFIGVALUE \ + ( 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( ( uint32 ) I2C_TRANSMITTER ) \ + | ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \ + | ( ( uint32 ) 0U ) | ( ( uint32 ) I2C_8_BIT ) | ( uint32 ) I2C_RESET_OUT ) + +#define I2C1_EMDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PSC_CONFIGVALUE 8U +#define I2C1_DMAC_CONFIGVALUE 0x00000000U +#define I2C1_FUN_CONFIGVALUE 0U +#define I2C1_DIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_ODR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PD_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) ) + +/* Configuration registers initial value for I2C*/ +#define I2C2_OAR_CONFIGVALUE 0x00000000U +#define I2C2_IMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( ( uint32 ) 0U ) ) + +#define I2C2_CLKL_CONFIGVALUE 37U +#define I2C2_CLKH_CONFIGVALUE 37U +#define I2C2_CNT_CONFIGVALUE 8U +#define I2C2_SAR_CONFIGVALUE 0x000003FFU +#define I2C2_MDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) \ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) | ( uint32 ) ( ( uint32 ) I2C_2_BIT ) \ + | ( uint32 ) I2C_RESET_OUT ) + +#define I2C2_EMDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PSC_CONFIGVALUE 8U +#define I2C2_DMAC_CONFIGVALUE 0x00000000U +#define I2C2_FUN_CONFIGVALUE 0U +#define I2C2_DIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_ODR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PD_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) ) + +/** + * @defgroup I2C I2C + * @brief Inter-Integrated Circuit Module. + * + * The I2C is a multi-master communication module providing an interface between the + * Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor + * I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support + * any slave or master I2C compatible device. + * + * Related Files + * - reg_i2c.h + * - i2c.h + * - i2c.c + * @addtogroup I2C + * @{ + */ + +/* I2C Interface Functions */ +void i2cInit( void ); +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ); +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ); +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ); +uint32 i2cIsTxReady( i2cBASE_t * i2c ); +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ); +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ); +uint32 i2cIsRxReady( i2cBASE_t * i2c ); +uint32 i2cIsStopDetected( i2cBASE_t * i2c ); +void i2cClearSCD( i2cBASE_t * i2c ); +uint32 i2cRxError( i2cBASE_t * i2c ); +uint8 i2cReceiveByte( i2cBASE_t * i2c ); +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ); +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cSetStart( i2cBASE_t * i2c ); +void i2cSetStop( i2cBASE_t * i2c ); +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ); +void i2cEnableLoopback( i2cBASE_t * i2c ); +void i2cDisableLoopback( i2cBASE_t * i2c ); +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ); +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ); +bool i2cIsMasterReady( i2cBASE_t * i2c ); +bool i2cIsBusBusy( i2cBASE_t * i2c ); +void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); +void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Interrupt callback + * @param[in] i2c - I2C module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h new file mode 100644 index 00000000000..36d037b8fe3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h @@ -0,0 +1,317 @@ +/** @file lin.h + * @brief LIN Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __LIN_H__ +#define __LIN_H__ + +#include "reg_lin.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def LIN_BREAK_INT + * @brief Alias for break detect interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BREAK_INT 0x00000001U + +/** @def LIN_WAKEUP_INT + * @brief Alias for wakeup interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_WAKEUP_INT 0x00000002U + +/** @def LIN_TO_INT + * @brief Alias for time out interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TO_INT 0x00000010U + +/** @def LIN_TOAWUS_INT + * @brief Alias for time out after wakeup signal interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOAWUS_INT 0x00000040U + +/** @def LIN_TOA3WUS_INT + * @brief Alias for time out after 3 wakeup signals interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOA3WUS_INT 0x00000080U + +/** @def LIN_TX_READY + * @brief Alias for transmit buffer ready flag + * + * Used with linIsTxReady. + */ +#define LIN_TX_READY 0x00000100U + +/** @def LIN_RX_INT + * @brief Alias for receive buffer ready interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_RX_INT 0x00000200U + +/** @def LIN_ID_INT + * @brief Alias for received matching identifier interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ID_INT 0x00002000U + +/** @def LIN_PE_INT + * @brief Alias for parity error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PE_INT 0x01000000U + +/** @def LIN_OE_INT + * @brief Alias for overrun error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_OE_INT 0x02000000U + +/** @def LIN_FE_INT + * @brief Alias for framing error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_FE_INT 0x04000000U + +/** @def LIN_NRE_INT + * @brief Alias for no response error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_NRE_INT 0x08000000U + +/** @def LIN_ISFE_INT + * @brief Alias for inconsistent sync field error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ISFE_INT 0x10000000U + +/** @def LIN_CE_INT + * @brief Alias for checksum error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_CE_INT 0x20000000U + +/** @def LIN_PBE_INT + * @brief Alias for physical bus error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PBE_INT 0x40000000U + +/** @def LIN_BE_INT + * @brief Alias for bit error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BE_INT 0x80000000U + +/** @struct linBase + * @brief LIN Register Definition + * + * This structure is used to access the LIN module registers. + */ +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +enum linPinSelect +{ + PIN_LIN_TX = 4U, + PIN_LIN_RX = 2U +}; + +/* Configuration registers */ +typedef struct lin_config_reg +{ + uint32 CONFIG_GCR0; + uint32 CONFIG_GCR1; + uint32 CONFIG_GCR2; + uint32 CONFIG_SETINT; + uint32 CONFIG_SETINTLVL; + uint32 CONFIG_FORMAT; + uint32 CONFIG_BRSR; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; + uint32 CONFIG_COMP; + uint32 CONFIG_MASK; + uint32 CONFIG_MBRSR; +} lin_config_reg_t; + +/* Configuration registers initial value for LIN*/ +#define LIN1_GCR0_CONFIGVALUE 0x00000001U +#define LIN1_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN1_GCR2_CONFIGVALUE 0x00000000U +#define LIN1_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN1_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN1_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN1_BRSR_CONFIGVALUE ( 233U ) +#define LIN1_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN1_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN1_MBRSR_CONFIGVALUE ( 3370U ) +#define LIN1_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN1_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/* Configuration registers initial value for LIN*/ +#define LIN2_GCR0_CONFIGVALUE 0x00000001U +#define LIN2_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN2_GCR2_CONFIGVALUE 0x00000000U +#define LIN2_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN2_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN2_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN2_BRSR_CONFIGVALUE ( 233U ) +#define LIN2_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN2_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN2_MBRSR_CONFIGVALUE ( 3370U ) +#define LIN2_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN2_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/** + * @defgroup LIN LIN + * @brief Local Interconnect Network Module. + * + * The LIN standard is based on the SCI (UART) serial data link format. The communication + *concept is single-master/multiple-slave with a message identification for multi-cast + *transmission between any network nodes. + * + * Related Files + * - reg_lin.h + * - lin.h + * - lin.c + * @addtogroup LIN + * @{ + */ + +/* LIN Interface Functions */ +void linInit( void ); +void linSetFunctional( linBASE_t * lin, uint32 port ); +void linSendHeader( linBASE_t * lin, uint8 identifier ); +void linSendWakupSignal( linBASE_t * lin ); +void linEnterSleep( linBASE_t * lin ); +void linSoftwareReset( linBASE_t * lin ); +uint32 linIsTxReady( linBASE_t * lin ); +void linSetLength( linBASE_t * lin, uint32 length ); +void linSend( linBASE_t * lin, uint8 * data ); +uint32 linIsRxReady( linBASE_t * lin ); +uint32 linTxRxError( linBASE_t * lin ); +uint32 linGetIdentifier( linBASE_t * lin ); +void linGetData( linBASE_t * lin, uint8 * const data ); +void linEnableNotification( linBASE_t * lin, uint32 flags ); +void linDisableNotification( linBASE_t * lin, uint32 flags ); +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ); +void linDisableLoopback( linBASE_t * lin ); +void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +uint32 linGetStatusFlag( linBASE_t * lin ); +void linClearStatusFlag( linBASE_t * lin, uint32 flags ); + +/** @fn void linNotification(linBASE_t *lin, uint32 flags) + * @brief Interrupt callback + * @param[in] lin - lin module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void linNotification( linBASE_t * lin, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h new file mode 100644 index 00000000000..f936f915c91 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h @@ -0,0 +1,94 @@ +/** + * \file mdio.h + * + * \brief MDIO APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MDIO_H__ +#define __MDIO_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "system.h" +#include "hw_mdio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* MDIO input and output frequencies in Hz */ +#define MDIO_FREQ_INPUT ( ( uint32 ) ( VCLK3_FREQ * 1000000.00F ) ) +#define MDIO_FREQ_OUTPUT 1000000U +/*****************************************************************************/ + +/** + * @addtogroup EMACMDIO + * @{ + */ +/* +** Prototypes for the APIs +*/ +extern uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ); +extern uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ); +extern void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ); +extern boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ); +extern void MDIOPhyRegWrite( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + uint16 RegVal ); +extern void MDIOEnable( uint32 baseAddr ); +extern void MDIODisable( uint32 baseAddr ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __MDIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h new file mode 100644 index 00000000000..71d7b98f224 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h @@ -0,0 +1,885 @@ +/** @file mibspi.h + * @brief MIBSPI Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MIBSPI_H__ +#define __MIBSPI_H__ + +#include "reg_mibspi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum triggerEvent + * @brief Transfer Group Trigger Event + */ +enum triggerEvent +{ + TRG_NEVER = 0U, + TRG_RISING = 1U, + TRG_FALLING = 2U, + TRG_BOTH = 3U, + TRG_HIGH = 5U, + TRG_LOW = 6U, + TRG_ALWAYS = 7U +}; + +/** @enum triggerSource + * @brief Transfer Group Trigger Source + */ +enum triggerSource +{ + TRG_DISABLED, + TRG_GIOA0, + TRG_GIOA1, + TRG_GIOA2, + TRG_GIOA3, + TRG_GIOA4, + TRG_GIOA5, + TRG_GIOA6, + TRG_GIOA7, + TRG_HET1_8, + TRG_HET1_10, + TRG_HET1_12, + TRG_HET1_14, + TRG_HET1_16, + TRG_HET1_18, + TRG_TICK +}; + +/** @enum mibspiPinSelect + * @brief mibspi Pin Select + */ +enum mibspiPinSelect +{ + PIN_CS0 = 0U, + PIN_CS1 = 1U, + PIN_CS2 = 2U, + PIN_CS3 = 3U, + PIN_CS4 = 4U, + PIN_CS5 = 5U, + PIN_CS6 = 6U, + PIN_CS7 = 7U, + PIN_ENA = 8U, + PIN_CLK = 9U, + PIN_SIMO = 10U, + PIN_SOMI = 11U, + PIN_SIMO_1 = 17U, + PIN_SIMO_2 = 18U, + PIN_SIMO_3 = 19U, + PIN_SIMO_4 = 20U, + PIN_SIMO_5 = 21U, + PIN_SIMO_6 = 22U, + PIN_SIMO_7 = 23U, + PIN_SOMI_1 = 25U, + PIN_SOMI_2 = 26U, + PIN_SOMI_3 = 27U, + PIN_SOMI_4 = 28U, + PIN_SOMI_5 = 29U, + PIN_SOMI_6 = 30U, + PIN_SOMI_7 = 31U +}; + +/** @enum chipSelect + * @brief Transfer Group Chip Select + */ +enum chipSelect +{ + CS_NONE = 0xFFU, + CS_0 = 0xFEU, + CS_1 = 0xFDU, + CS_2 = 0xFBU, + CS_3 = 0xF7U, + CS_4 = 0xEFU, + CS_5 = 0xDFU, + CS_6 = 0xBFU, + CS_7 = 0x7FU +}; + +/** @typedef mibspiPmode_t + * @brief Mibspi Parellel mode Type Definition + * + * This type is used to represent Mibspi Parellel mode. + */ +typedef enum mibspiPmode +{ + PMODE_NORMAL = 0x0U, + PMODE_2_DATALINE = 0x1U, + PMODE_4_DATALINE = 0x2U, + PMODE_8_DATALINE = 0x3U +} mibspiPmode_t; + +/** @typedef mibspiDFMT_t + * @brief Mibspi Data format selection Type Definition + * + * This type is used to represent Mibspi Data format selection. + */ +typedef enum mibspiDFMT +{ + DATA_FORMAT0 = 0x0U, + DATA_FORMAT1 = 0x1U, + DATA_FORMAT2 = 0x2U, + DATA_FORMAT3 = 0x3U +} mibspiDFMT_t; + +typedef struct mibspi_config_reg +{ + uint32 CONFIG_GCR1; + uint32 CONFIG_INT0; + uint32 CONFIG_LVL; + uint32 CONFIG_PCFUN; + uint32 CONFIG_PCDIR; + uint32 CONFIG_PCPDR; + uint32 CONFIG_PCDIS; + uint32 CONFIG_PCPSL; + uint32 CONFIG_DELAY; + uint32 CONFIG_FMT0; + uint32 CONFIG_FMT1; + uint32 CONFIG_FMT2; + uint32 CONFIG_FMT3; + uint32 CONFIG_MIBSPIE; + uint32 CONFIG_LTGPEND; + uint32 CONFIG_TGCTRL[ 8U ]; + uint32 CONFIG_PAR_ECC_CTRL; +} mibspi_config_reg_t; + +#define MIBSPI1_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI1_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI1_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) +#define MIBSPI1_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) + +#define MIBSPI1_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI1_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI1_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI1_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI1_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI1_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI2_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI2_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) +#define MIBSPI2_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define MIBSPI2_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI2_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI2_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI2_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI2_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI2_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI2_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI2_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI2_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI3_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI3_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI3_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI3_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI3_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI3_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI3_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI3_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI3_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI3_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI4_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI4_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) +#define MIBSPI4_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define MIBSPI4_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI4_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI4_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI4_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI4_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI4_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI4_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI4_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI4_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI5_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI5_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI5_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) +#define MIBSPI5_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) + +#define MIBSPI5_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI5_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI5_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI5_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI5_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI5_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +/** + * @defgroup MIBSPI MIBSPI + * @brief Multi-Buffered Serial Peripheral Interface Module. + * + * The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a + *serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the + *device at a programmed bit-transfer rate. The MibSPI has a programmable buffer memory + *that enables programmed transmission to be completed without CPU intervention + * + * Related Files + * - reg_mibspi.h + * - mibspi.h + * - mibspi.c + * @addtogroup MIBSPI + * @{ + */ + +/* MIBSPI Interface Functions */ +void mibspiInit( void ); +boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi ); +void mibspiOutofReset( mibspiBASE_t * mibspi ); +void mibspiReset( mibspiBASE_t * mibspi ); +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ); +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ); +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ); +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ); +void mibspiDisableLoopback( mibspiBASE_t * mibspi ); +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ); +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) + * @brief Error interrupt callback + * @param[in] mibspi - mibSpi module base address + * @param[in] flags - Copy of error interrupt flags + * + * This is a error callback that is provided by the application and is call upon + * an error interrupt. The paramer passed to the callback is a copy of the error + * interrupt flag register. + */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ); + +/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Transfer complete notification callback + * @param[in] mibspi - mibSpi module base address + * @param[in] group - Transfer group + * + * This is a callback function provided by the application. It is call when + * a transfer is complete. The parameter is the transfer group that triggered + * the interrupt. + */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h new file mode 100644 index 00000000000..47bd39fa1b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h @@ -0,0 +1,165 @@ +/** @file nmpu.h + * @brief NMPU Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NMPU_H_ +#define NMPU_H_ + +#include "reg_nmpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef enum nmpuRegion +{ + NMPU_REGION0 = 0U, + NMPU_REGION1 = 1U, + NMPU_REGION2 = 2U, + NMPU_REGION3 = 3U, + NMPU_REGION4 = 4U, + NMPU_REGION5 = 5U, + NMPU_REGION6 = 6U, + NMPU_REGION7 = 7U +} nmpuReg_t; + +typedef enum nmpuAccessPermission +{ + NMPU_PRIV_NA_USER_NA = 0U, + NMPU_PRIV_RW_USER_NA = 1U, + NMPU_PRIV_RW_USER_RO = 2U, + NMPU_PRIV_RW_USER_RW = 3U, + NMPU_PRIV_RO_USER_NA = 5U, + NMPU_PRIV_RO_USER_RO = 6U +} nmpuAP_t; + +typedef enum nmpuRegionSize +{ + NMPU_SIZE_32_BYTES = 0x4U, + NMPU_SIZE_64_BYTES = 0x5U, + NMPU_SIZE_128_BYTES = 0x6U, + NMPU_SIZE_256_BYTES = 0x7U, + NMPU_SIZE_512_BYTES = 0x8U, + NMPU_SIZE_1_KB = 0x9U, + NMPU_SIZE_2_KB = 0xAU, + NMPU_SIZE_4_KB = 0xBU, + NMPU_SIZE_8_KB = 0xCU, + NMPU_SIZE_16_KB = 0xDU, + NMPU_SIZE_32_KB = 0xEU, + NMPU_SIZE_64_KB = 0xFU, + NMPU_SIZE_128_KB = 0x10U, + NMPU_SIZE_256_KB = 0x11U, + NMPU_SIZE_512_KB = 0x12U, + NMPU_SIZE_1_MB = 0x13U, + NMPU_SIZE_2_MB = 0x14U, + NMPU_SIZE_4_MB = 0x15U, + NMPU_SIZE_8_MB = 0x16U, + NMPU_SIZE_16_MB = 0x17U, + NMPU_SIZE_32_MB = 0x18U, + NMPU_SIZE_64_MB = 0x19U, + NMPU_SIZE_128_MB = 0x1AU, + NMPU_SIZE_256_MB = 0x1BU, + NMPU_SIZE_512_MB = 0x1CU, + NMPU_SIZE_1_GB = 0x1DU, + NMPU_SIZE_2_GB = 0x1EU, + NMPU_SIZE_4_GB = 0x1FU +} nmpuRegionSize_t; + +typedef enum nmpuError +{ + NMPU_ERROR_NONE, + NMPU_ERROR_AP_READ, + NMPU_ERROR_AP_WRITE, + NMPU_ERROR_BG_READ, + NMPU_ERROR_BG_WRITE +} nmpuErr_t; + +typedef struct nmpuRegionAttributes +{ + uint32 baseaddr; + nmpuReg_t regionsize; + nmpuAP_t accesspermission; +} nmpuRegionAttributes_t; + +/** + * @defgroup NMPU NMPU + * @brief System Memory Protection Unit + * + * Related files: + * - reg_nmpu.h + * - sys_nmpu.h + * - sys_nmpu.c + * + * @addtogroup NMPU + * @{ + */ + +void nmpuEnable( nmpuBASE_t * nmpu ); +void nmpuDisable( nmpuBASE_t * nmpu ); +void nmpuEnableErrorGen( nmpuBASE_t * nmpu ); +void nmpuDisableErrorGen( nmpuBASE_t * nmpu ); +boolean nmpuEnableRegion( nmpuBASE_t * nmpu, + nmpuReg_t region, + nmpuRegionAttributes_t config ); +boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region ); +nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu ); +nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu ); +uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu ); +void nmpuClearErrorStatus( nmpuBASE_t * nmpu ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* NMPU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h new file mode 100644 index 00000000000..98d1837da4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h @@ -0,0 +1,139 @@ +/* + * DP83640.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _PHY_DP83640_H_ +#define _PHY_DP83640_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Dp83640GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define DP83640_PHY_ID ( 0x0007C0F0u ) +#define DP83640_PHY_ID_REV_MASK ( 0x0000000Fu ) + +/* Pause operations */ +#define DP83640_PAUSE_NIL ( 0x0000u ) +#define DP83640_PAUSE_SYM ( 0x0400u ) +#define DP83640_PAUSE_ASYM ( 0x0800u ) +#define DP83640_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define DP83640_100BTX_HD ( 0x0000u ) +#define DP83640_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define DP83640_NO_100BTX ( 0x0000u ) +#define DP83640_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define DP83640_10BT_HD ( 0x0000u ) +#define DP83640_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define DP83640_NO_10BT ( 0x0000u ) +#define DP83640_10BT ( 0x0020u ) + +/************************************************************************** + API function Prototypes +***************************************************************************/ +extern uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h new file mode 100644 index 00000000000..610217ea173 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h @@ -0,0 +1,156 @@ +/* + * Tlk111.h + */ + +/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com + * ALL RIGHTS RESERVED + */ + +#ifndef _PHY_TLK111_H_ +#define _PHY_TLK111_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Tlk111GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_SWSCR1 ( 9u ) +#define PHY_SWSCR2 ( 10u ) +#define PHY_SWSCR3 ( 11u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define Tlk111_PHY_ID ( 0x2000A212 ) +#define Tlk111_PHY_ID_REV_MASK ( 0x0000000Fu ) +#define Tlk111_PHY_ID_OUI ( 0x2000A000 ) +#define Tlk111_PHY_ID_OUI_MASK ( 0xFFFFFC00 ) + +/* Pause operations */ +#define Tlk111_PAUSE_NIL ( 0x0000u ) +#define Tlk111_PAUSE_SYM ( 0x0400u ) +#define Tlk111_PAUSE_ASYM ( 0x0800u ) +#define Tlk111_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define Tlk111_100BTX_HD ( 0x0000u ) +#define Tlk111_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define Tlk111_NO_100BTX ( 0x0000u ) +#define Tlk111_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define Tlk111_10BT_HD ( 0x0000u ) +#define Tlk111_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define Tlk111_NO_10BT ( 0x0000u ) +#define Tlk111_10BT ( 0x0020u ) + +/* Software Strap Register 1 */ +#define Tlk111_SWStrapDone ( 1u << 15 ) +#define Tlk111_Auto_MDIX_Ena ( 1u << 14 ) +#define Tlk111_Auto_Neg_Ena ( 1u << 13 ) +#define Tlk111_Auto_AnMode_10BT_HD ( 0u << 11 ) +#define Tlk111_Auto_AnMode_10BT_FD ( 1u << 11 ) +#define Tlk111_Auto_AnMode_100BT_HD ( 2u << 11 ) +#define Tlk111_Auto_AnMode_100BT_FD ( 3u << 11 ) +#define Tlk111_Force_LEDMode1 ( 1u << 10 ) +#define Tlk111_RMII_Enhanced ( 1u << 9 ) +#define Tlk111_TDR_AutoRun ( 1u << 8 ) +#define Tlk111_LinkLoss_Recovery ( 1u << 8 ) +#define Tlk111_FastAutoMdix ( 1u << 6 ) +#define Tlk111_RobustAutoMdix ( 1u << 5 ) +#define Tlk111_FastAnEn ( 1u << 4 ) +#define Tlk111_FastAnSel0 ( 0u << 2 ) +#define Tlk111_FastAnSel1 ( 1u << 2 ) +#define Tlk111_FastAnSel2 ( 2u << 2 ) +#define Tlk111_FastRxDvDetect ( 1u << 1 ) +#define Tlk111_IntPdn_InterruptOut ( 1u << 0 ) + +/* Software Strap Register 2 */ +#define Tlk111_100BT_Force_FE_LinkDrop ( 1u << 15 ) +#define Tlk111_Rsv1 ( 2u << 7 ) +#define Tlk111_FastLinkUpParallel ( 1u << 6 ) +#define Tlk111_ExtendedFDAbility ( 1u << 5 ) +#define Tlk111_ExtendedLEDLink ( 1u << 4 ) +#define Tlk111_IsolateMII_100BT_HD ( 1u << 3 ) +#define Tlk111_RXERR_DuringIdle ( 1u << 2 ) +#define Tlk111_OddNibbleDetectDisable ( 1u << 1 ) +#define Tlk111_RMII_Use_RXCLK ( 1u << 0 ) +#define Tlk111_RMII_Use_XI ( 0u << 0 ) + +/* Software Strap Register 2 */ +#define Tlk111_FastLinkDown ( 1u << 10 ) +#define Tlk111_PolaritySwap ( 1u << 6 ) +#define Tlk111_MDIXSwap ( 1u << 5 ) +#define Tlk111_Bypass4B5B ( 1u << 4 ) +#define Tlk111_FastLinkDownRxErrCnt ( 1u << 3 ) +#define Tlk111_FastLinkDownMLT3ErrCnt ( 1u << 2 ) +#define Tlk111_FastLinkDownLowSnr ( 1u << 1 ) +#define Tlk111_FastLinkDownSigLoss ( 1u << 0 ) + +/* The Values for SWSCR Registers */ +#define Tlk111_SWSCR1_Val \ + ( Tlk111_Auto_MDIX_Ena | Tlk111_Auto_Neg_Ena | Tlk111_Auto_AnMode_100BT_FD \ + | Tlk111_Force_LEDMode1 | Tlk111_IntPdn_InterruptOut ) +#define Tlk111_SWSCR2_Val ( Tlk111_Rsv1 | Tlk111_RXERR_DuringIdle ) +#define Tlk111_SWSCR3_Val ( 0u ) + +/************************************************************************** + API function Prototypes +***************************************************************************/ +extern uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h new file mode 100644 index 00000000000..2ec2e899db4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h @@ -0,0 +1,1762 @@ +/** @file pinmux.h + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __PINMUX_H__ +#define __PINMUX_H__ + +#include "reg_pinmux.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define PINMUX_BALL_N19_SHIFT 0U +#define PINMUX_BALL_D4_SHIFT 8U +#define PINMUX_BALL_D5_SHIFT 16U +#define PINMUX_BALL_C4_SHIFT 24U +#define PINMUX_BALL_C5_SHIFT 0U +#define PINMUX_BALL_C6_SHIFT 8U +#define PINMUX_BALL_C7_SHIFT 16U +#define PINMUX_BALL_C8_SHIFT 24U +#define PINMUX_BALL_C9_SHIFT 0U +#define PINMUX_BALL_C10_SHIFT 8U +#define PINMUX_BALL_C11_SHIFT 16U +#define PINMUX_BALL_C12_SHIFT 24U +#define PINMUX_BALL_C13_SHIFT 0U +#define PINMUX_BALL_D14_SHIFT 8U +#define PINMUX_BALL_C14_SHIFT 16U +#define PINMUX_BALL_D15_SHIFT 24U +#define PINMUX_BALL_C15_SHIFT 0U +#define PINMUX_BALL_C16_SHIFT 8U +#define PINMUX_BALL_C17_SHIFT 16U +#define PINMUX_BALL_D16_SHIFT 24U +#define PINMUX_BALL_K3_SHIFT 0U +#define PINMUX_BALL_R4_SHIFT 8U +#define PINMUX_BALL_N17_SHIFT 16U +#define PINMUX_BALL_L17_SHIFT 24U +#define PINMUX_BALL_K17_SHIFT 0U +#define PINMUX_BALL_M17_SHIFT 8U +#define PINMUX_BALL_R3_SHIFT 16U +#define PINMUX_BALL_P3_SHIFT 24U +#define PINMUX_BALL_D17_SHIFT 0U +#define PINMUX_BALL_E9_SHIFT 8U +#define PINMUX_BALL_E8_SHIFT 16U +#define PINMUX_BALL_E7_SHIFT 24U +#define PINMUX_BALL_E6_SHIFT 0U +#define PINMUX_BALL_E13_SHIFT 8U +#define PINMUX_BALL_E12_SHIFT 16U +#define PINMUX_BALL_E11_SHIFT 24U +#define PINMUX_BALL_E10_SHIFT 0U +#define PINMUX_BALL_K15_SHIFT 8U +#define PINMUX_BALL_L15_SHIFT 16U +#define PINMUX_BALL_M15_SHIFT 24U +#define PINMUX_BALL_N15_SHIFT 0U +#define PINMUX_BALL_E5_SHIFT 8U +#define PINMUX_BALL_F5_SHIFT 16U +#define PINMUX_BALL_G5_SHIFT 24U +#define PINMUX_BALL_K5_SHIFT 0U +#define PINMUX_BALL_L5_SHIFT 8U +#define PINMUX_BALL_M5_SHIFT 16U +#define PINMUX_BALL_N5_SHIFT 24U +#define PINMUX_BALL_P5_SHIFT 0U +#define PINMUX_BALL_R5_SHIFT 8U +#define PINMUX_BALL_R6_SHIFT 16U +#define PINMUX_BALL_R7_SHIFT 24U +#define PINMUX_BALL_R8_SHIFT 0U +#define PINMUX_BALL_R9_SHIFT 8U +#define PINMUX_BALL_R10_SHIFT 16U +#define PINMUX_BALL_R11_SHIFT 24U +#define PINMUX_BALL_B15_SHIFT 0U +#define PINMUX_BALL_B8_SHIFT 8U +#define PINMUX_BALL_B16_SHIFT 16U +#define PINMUX_BALL_B9_SHIFT 24U +#define PINMUX_BALL_C1_SHIFT 0U +#define PINMUX_BALL_E1_SHIFT 8U +#define PINMUX_BALL_B5_SHIFT 16U +#define PINMUX_BALL_H3_SHIFT 24U +#define PINMUX_BALL_M1_SHIFT 0U +#define PINMUX_BALL_F2_SHIFT 8U +#define PINMUX_BALL_W10_SHIFT 16U +#define PINMUX_BALL_J2_SHIFT 24U +#define PINMUX_BALL_F1_SHIFT 0U +#define PINMUX_BALL_R2_SHIFT 8U +#define PINMUX_BALL_F3_SHIFT 16U +#define PINMUX_BALL_G3_SHIFT 24U +#define PINMUX_BALL_J3_SHIFT 0U +#define PINMUX_BALL_G19_SHIFT 8U +#define PINMUX_BALL_V9_SHIFT 16U +#define PINMUX_BALL_V10_SHIFT 24U +#define PINMUX_BALL_V5_SHIFT 0U +#define PINMUX_BALL_B2_SHIFT 8U +#define PINMUX_BALL_C3_SHIFT 16U +#define PINMUX_BALL_W9_SHIFT 24U +#define PINMUX_BALL_W8_SHIFT 0U +#define PINMUX_BALL_V8_SHIFT 8U +#define PINMUX_BALL_H19_SHIFT 16U +#define PINMUX_BALL_E19_SHIFT 24U +#define PINMUX_BALL_B6_SHIFT 0U +#define PINMUX_BALL_W6_SHIFT 8U +#define PINMUX_BALL_T12_SHIFT 16U +#define PINMUX_BALL_H18_SHIFT 24U +#define PINMUX_BALL_J19_SHIFT 0U +#define PINMUX_BALL_E16_SHIFT 8U +#define PINMUX_BALL_H17_SHIFT 16U +#define PINMUX_BALL_G17_SHIFT 24U +#define PINMUX_BALL_J18_SHIFT 0U +#define PINMUX_BALL_E17_SHIFT 8U +#define PINMUX_BALL_H16_SHIFT 16U +#define PINMUX_BALL_G16_SHIFT 24U +#define PINMUX_BALL_K18_SHIFT 0U +#define PINMUX_BALL_V2_SHIFT 8U +#define PINMUX_BALL_W5_SHIFT 16U +#define PINMUX_BALL_U1_SHIFT 24U +#define PINMUX_BALL_B12_SHIFT 0U +#define PINMUX_BALL_V6_SHIFT 8U +#define PINMUX_BALL_W3_SHIFT 16U +#define PINMUX_BALL_T1_SHIFT 24U +#define PINMUX_BALL_E18_SHIFT 0U +#define PINMUX_BALL_V7_SHIFT 8U +#define PINMUX_BALL_D19_SHIFT 16U +#define PINMUX_BALL_E3_SHIFT 24U +#define PINMUX_BALL_B4_SHIFT 0U +#define PINMUX_BALL_N2_SHIFT 8U +#define PINMUX_BALL_N1_SHIFT 16U +#define PINMUX_BALL_A4_SHIFT 24U +#define PINMUX_BALL_A13_SHIFT 0U +#define PINMUX_BALL_J1_SHIFT 8U +#define PINMUX_BALL_B13_SHIFT 16U +#define PINMUX_BALL_P2_SHIFT 24U +#define PINMUX_BALL_H4_SHIFT 0U +#define PINMUX_BALL_B3_SHIFT 8U +#define PINMUX_BALL_J4_SHIFT 16U +#define PINMUX_BALL_P1_SHIFT 24U +#define PINMUX_BALL_A14_SHIFT 0U +#define PINMUX_BALL_K19_SHIFT 8U +#define PINMUX_BALL_B11_SHIFT 16U +#define PINMUX_BALL_D8_SHIFT 24U +#define PINMUX_BALL_D7_SHIFT 0U +#define PINMUX_BALL_D3_SHIFT 8U +#define PINMUX_BALL_D2_SHIFT 16U +#define PINMUX_BALL_D1_SHIFT 24U +#define PINMUX_BALL_P4_SHIFT 0U +#define PINMUX_BALL_T5_SHIFT 8U +#define PINMUX_BALL_T4_SHIFT 16U +#define PINMUX_BALL_U7_SHIFT 24U +#define PINMUX_BALL_E2_SHIFT 0U +#define PINMUX_BALL_N3_SHIFT 8U + +#define PINMUX_GATE_EMIF_CLK_SHIFT 0U +#define PINMUX_EMIF_OUTPUT_ENABLE_SHIFT 8U +#define PINMUX_GIOA_DISABLE_HET1_SHIFT 8U +#define PINMUX_GIOB_DISABLE_HET2_SHIFT 0U +#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0U +#define PINMUX_ETHERNET_SHIFT 24U +#define PINMUX_ETPWM1_SHIFT 0U +#define PINMUX_ETPWM2_SHIFT 8U +#define PINMUX_ETPWM3_SHIFT 16U +#define PINMUX_ETPWM4_SHIFT 24U +#define PINMUX_ETPWM5_SHIFT 0U +#define PINMUX_ETPWM6_SHIFT 8U +#define PINMUX_ETPWM7_SHIFT 16U +#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT 24U +#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT 0U +#define PINMUX_TZ1_SHIFT 16U +#define PINMUX_TZ2_SHIFT 24U +#define PINMUX_TZ3_SHIFT 0U +#define PINMUX_EPWM1SYNCI_SHIFT 8U +#define PINMUX_ETPWM_SOC1A_SHIFT 0U +#define PINMUX_ETPWM_SOC2A_SHIFT 8U +#define PINMUX_ETPWM_SOC3A_SHIFT 16U +#define PINMUX_ETPWM_SOC4A_SHIFT 24U +#define PINMUX_ETPWM_SOC5A_SHIFT 0U +#define PINMUX_ETPWM_SOC6A_SHIFT 8U +#define PINMUX_ETPWM_SOC7A_SHIFT 16U +#define PINMUX_EQEP1A_FILTER_SHIFT 16U +#define PINMUX_EQEP1B_FILTER_SHIFT 24U +#define PINMUX_EQEP1I_FILTER_SHIFT 0U +#define PINMUX_EQEP1S_FILTER_SHIFT 8U +#define PINMUX_EQEP2A_FILTER_SHIFT 16U +#define PINMUX_EQEP2B_FILTER_SHIFT 24U +#define PINMUX_EQEP2I_FILTER_SHIFT 0U +#define PINMUX_EQEP2S_FILTER_SHIFT 8U +#define PINMUX_ECAP1_FILTER_SHIFT 0U +#define PINMUX_ECAP2_FILTER_SHIFT 8U +#define PINMUX_ECAP3_FILTER_SHIFT 16U +#define PINMUX_ECAP4_FILTER_SHIFT 24U +#define PINMUX_ECAP5_FILTER_SHIFT 0U +#define PINMUX_ECAP6_FILTER_SHIFT 8U +#define PINMUX_GIOA0_DMA_SHIFT 0U +#define PINMUX_GIOA1_DMA_SHIFT 8U +#define PINMUX_GIOA2_DMA_SHIFT 16U +#define PINMUX_GIOA3_DMA_SHIFT 24U +#define PINMUX_GIOA4_DMA_SHIFT 0U +#define PINMUX_GIOA5_DMA_SHIFT 8U +#define PINMUX_GIOA6_DMA_SHIFT 16U +#define PINMUX_GIOA7_DMA_SHIFT 24U +#define PINMUX_GIOB0_DMA_SHIFT 0U +#define PINMUX_GIOB1_DMA_SHIFT 8U +#define PINMUX_GIOB2_DMA_SHIFT 16U +#define PINMUX_GIOB3_DMA_SHIFT 24U +#define PINMUX_GIOB4_DMA_SHIFT 0U +#define PINMUX_GIOB5_DMA_SHIFT 8U +#define PINMUX_GIOB6_DMA_SHIFT 16U +#define PINMUX_GIOB7_DMA_SHIFT 24U +#define PINMUX_TEMP1_ENABLE_SHIFT 16U +#define PINMUX_TEMP2_ENABLE_SHIFT 24U +#define PINMUX_TEMP3_ENABLE_SHIFT 0U + +#define PINMUX_BALL_N19_MASK \ + ( ~( uint32 ) ( ( uint32 ) uint32 )( ( uint32 ) 0xFFU << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_D4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_C4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C7_SHIFT ) ) +#define PINMUX_BALL_C8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C8_SHIFT ) ) +#define PINMUX_BALL_C9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C9_SHIFT ) ) +#define PINMUX_BALL_C10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C10_SHIFT ) ) +#define PINMUX_BALL_C11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C11_SHIFT ) ) +#define PINMUX_BALL_C12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C12_SHIFT ) ) +#define PINMUX_BALL_C13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C13_SHIFT ) ) +#define PINMUX_BALL_D14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D14_SHIFT ) ) +#define PINMUX_BALL_C14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C14_SHIFT ) ) +#define PINMUX_BALL_D15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D15_SHIFT ) ) +#define PINMUX_BALL_C15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C15_SHIFT ) ) +#define PINMUX_BALL_C16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C16_SHIFT ) ) +#define PINMUX_BALL_C17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C17_SHIFT ) ) +#define PINMUX_BALL_D16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_K3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_R4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R4_SHIFT ) ) +#define PINMUX_BALL_N17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_L17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L17_SHIFT ) ) +#define PINMUX_BALL_K17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_M17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_R3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R3_SHIFT ) ) +#define PINMUX_BALL_P3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P3_SHIFT ) ) +#define PINMUX_BALL_D17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_E9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E9_SHIFT ) ) +#define PINMUX_BALL_E8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E8_SHIFT ) ) +#define PINMUX_BALL_E7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E7_SHIFT ) ) +#define PINMUX_BALL_E6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E6_SHIFT ) ) +#define PINMUX_BALL_E13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E13_SHIFT ) ) +#define PINMUX_BALL_E12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E12_SHIFT ) ) +#define PINMUX_BALL_E11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E11_SHIFT ) ) +#define PINMUX_BALL_E10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E10_SHIFT ) ) +#define PINMUX_BALL_K15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K15_SHIFT ) ) +#define PINMUX_BALL_L15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L15_SHIFT ) ) +#define PINMUX_BALL_M15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M15_SHIFT ) ) +#define PINMUX_BALL_N15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N15_SHIFT ) ) +#define PINMUX_BALL_E5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E5_SHIFT ) ) +#define PINMUX_BALL_F5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F5_SHIFT ) ) +#define PINMUX_BALL_G5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G5_SHIFT ) ) +#define PINMUX_BALL_K5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K5_SHIFT ) ) +#define PINMUX_BALL_L5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_M5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_N5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_P5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_R5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R10_SHIFT ) ) +#define PINMUX_BALL_R11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R11_SHIFT ) ) +#define PINMUX_BALL_B15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B15_SHIFT ) ) +#define PINMUX_BALL_B8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B8_SHIFT ) ) +#define PINMUX_BALL_B16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B16_SHIFT ) ) +#define PINMUX_BALL_B9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B9_SHIFT ) ) +#define PINMUX_BALL_C1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_E1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_B5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_H3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_M1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_F2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F2_SHIFT ) ) +#define PINMUX_BALL_W10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_J2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J2_SHIFT ) ) +#define PINMUX_BALL_F1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_R2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_F3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_G3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_J3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_G19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_V9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_B2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_C3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_W9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_V8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_H19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_E19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_B6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B6_SHIFT ) ) +#define PINMUX_BALL_W6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W6_SHIFT ) ) +#define PINMUX_BALL_T12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_H18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_J19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_E16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_H17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_G17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_J18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_E17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_H16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_G16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_K18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_V2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_W5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_U1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_B12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_V6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_W3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_T1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_E18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_V7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_D19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_E3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_B4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_N2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_A4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_J1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_B13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_P2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_H4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H4_SHIFT ) ) +#define PINMUX_BALL_B3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_J4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J4_SHIFT ) ) +#define PINMUX_BALL_P1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_A14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_K19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_B11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_D8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D8_SHIFT ) ) +#define PINMUX_BALL_D7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D7_SHIFT ) ) +#define PINMUX_BALL_D3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D2_SHIFT ) ) +#define PINMUX_BALL_D1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D1_SHIFT ) ) +#define PINMUX_BALL_P4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P4_SHIFT ) ) +#define PINMUX_BALL_T5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T5_SHIFT ) ) +#define PINMUX_BALL_T4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T4_SHIFT ) ) +#define PINMUX_BALL_U7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U7_SHIFT ) ) +#define PINMUX_BALL_E2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E2_SHIFT ) ) +#define PINMUX_BALL_N3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N3_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2S_FILTER_SHIFT ) ) +#define PINMUX_ECAP1_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP6_FILTER_SHIFT ) ) + +#define PINMUX_GIOA0_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP3_ENABLE_SHIFT ) ) + +#define PINMUX_BALL_N19_AD1EVT ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_MII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_RMII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_nTZ1_1 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N19_SHIFT ) ) + +#define PINMUX_BALL_D4_EMIF_ADDR_00 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D4_N2HET2_01 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D4_SHIFT ) ) + +#define PINMUX_BALL_D5_EMIF_ADDR_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_D5_N2HET2_03 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D5_SHIFT ) ) + +#define PINMUX_BALL_C4_EMIF_ADDR_06 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_RTP_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_N2HET2_11 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C4_SHIFT ) ) + +#define PINMUX_BALL_C5_EMIF_ADDR_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_RTP_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_N2HET2_13 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C5_SHIFT ) ) + +#define PINMUX_BALL_C6_EMIF_ADDR_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_RTP_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_N2HET2_15 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C6_SHIFT ) ) + +#define PINMUX_BALL_C7_EMIF_ADDR_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C7_SHIFT ) ) +#define PINMUX_BALL_C7_RTP_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C7_SHIFT ) ) + +#define PINMUX_BALL_C8_EMIF_ADDR_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C8_SHIFT ) ) +#define PINMUX_BALL_C8_RTP_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C8_SHIFT ) ) + +#define PINMUX_BALL_C9_EMIF_ADDR_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C9_SHIFT ) ) +#define PINMUX_BALL_C9_RTP_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C9_SHIFT ) ) + +#define PINMUX_BALL_C10_EMIF_ADDR_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C10_SHIFT ) ) +#define PINMUX_BALL_C10_RTP_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C10_SHIFT ) ) + +#define PINMUX_BALL_C11_EMIF_ADDR_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C11_SHIFT ) ) +#define PINMUX_BALL_C11_RTP_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C11_SHIFT ) ) + +#define PINMUX_BALL_C12_EMIF_ADDR_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C12_SHIFT ) ) +#define PINMUX_BALL_C12_RTP_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C12_SHIFT ) ) + +#define PINMUX_BALL_C13_EMIF_ADDR_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C13_SHIFT ) ) +#define PINMUX_BALL_C13_RTP_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C13_SHIFT ) ) + +#define PINMUX_BALL_D14_EMIF_ADDR_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D14_SHIFT ) ) +#define PINMUX_BALL_D14_RTP_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D14_SHIFT ) ) + +#define PINMUX_BALL_C14_EMIF_ADDR_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C14_SHIFT ) ) +#define PINMUX_BALL_C14_RTP_DATA_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C14_SHIFT ) ) + +#define PINMUX_BALL_D15_EMIF_ADDR_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D15_SHIFT ) ) +#define PINMUX_BALL_D15_RTP_DATA_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D15_SHIFT ) ) + +#define PINMUX_BALL_C15_EMIF_ADDR_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C15_SHIFT ) ) +#define PINMUX_BALL_C15_RTP_nENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C15_SHIFT ) ) + +#define PINMUX_BALL_C16_EMIF_ADDR_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C16_SHIFT ) ) +#define PINMUX_BALL_C16_RTP_nSYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C16_SHIFT ) ) + +#define PINMUX_BALL_C17_EMIF_ADDR_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C17_SHIFT ) ) +#define PINMUX_BALL_C17_RTP_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C17_SHIFT ) ) + +#define PINMUX_BALL_D16_EMIF_BA_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_8_25 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_N2HET2_05 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D16_SHIFT ) ) + +#define PINMUX_BALL_K3_RESERVED ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_K3_EMIF_CLK ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_K3_ECLK2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K3_SHIFT ) ) + +#define PINMUX_BALL_R4_EMIF_nCAS \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R4_SHIFT ) ) +#define PINMUX_BALL_R4_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R4_SHIFT ) ) + +#define PINMUX_BALL_N17_EMIF_nCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_RTP_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_N2HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N17_SHIFT ) ) + +#define PINMUX_BALL_L17_EMIF_nCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L17_SHIFT ) ) +#define PINMUX_BALL_L17_GIOB_4 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_L17_SHIFT ) ) + +#define PINMUX_BALL_K17_EMIF_nCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_RTP_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_N2HET2_09 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K17_SHIFT ) ) + +#define PINMUX_BALL_M17_EMIF_nCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_M17_RTP_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_M17_GIOB_5 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M17_SHIFT ) ) + +#define PINMUX_BALL_R3_EMIF_nRAS \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R3_SHIFT ) ) +#define PINMUX_BALL_R3_GIOB_6 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R3_SHIFT ) ) + +#define PINMUX_BALL_P3_EMIF_nWAIT \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P3_SHIFT ) ) +#define PINMUX_BALL_P3_GIOB_7 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P3_SHIFT ) ) + +#define PINMUX_BALL_D17_EMIF_nWE \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_D17_EMIF_RNW \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D17_SHIFT ) ) + +#define PINMUX_BALL_E9_ETMDATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E9_SHIFT ) ) +#define PINMUX_BALL_E9_EMIF_ADDR_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E9_SHIFT ) ) + +#define PINMUX_BALL_E8_ETMDATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E8_SHIFT ) ) +#define PINMUX_BALL_E8_EMIF_ADDR_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E8_SHIFT ) ) + +#define PINMUX_BALL_E7_ETMDATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E7_SHIFT ) ) +#define PINMUX_BALL_E7_EMIF_ADDR_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E7_SHIFT ) ) + +#define PINMUX_BALL_E6_ETMDATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E6_SHIFT ) ) +#define PINMUX_BALL_E6_EMIF_ADDR_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E6_SHIFT ) ) + +#define PINMUX_BALL_E13_ETMDATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E13_SHIFT ) ) +#define PINMUX_BALL_E13_EMIF_BA_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E13_SHIFT ) ) + +#define PINMUX_BALL_E12_ETMDATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E12_SHIFT ) ) +#define PINMUX_BALL_E12_EMIF_nOE \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E12_SHIFT ) ) + +#define PINMUX_BALL_E11_ETMDATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E11_SHIFT ) ) +#define PINMUX_BALL_E11_EMIF_nDQM_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E11_SHIFT ) ) + +#define PINMUX_BALL_E10_ETMDATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E10_SHIFT ) ) +#define PINMUX_BALL_E10_EMIF_nDQM_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E10_SHIFT ) ) + +#define PINMUX_BALL_K15_ETMDATA_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K15_SHIFT ) ) +#define PINMUX_BALL_K15_EMIF_DATA_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K15_SHIFT ) ) + +#define PINMUX_BALL_L15_ETMDATA_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L15_SHIFT ) ) +#define PINMUX_BALL_L15_EMIF_DATA_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_L15_SHIFT ) ) + +#define PINMUX_BALL_M15_ETMDATA_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M15_SHIFT ) ) +#define PINMUX_BALL_M15_EMIF_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M15_SHIFT ) ) + +#define PINMUX_BALL_N15_ETMDATA_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N15_SHIFT ) ) +#define PINMUX_BALL_N15_EMIF_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N15_SHIFT ) ) + +#define PINMUX_BALL_E5_ETMDATA_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E5_SHIFT ) ) +#define PINMUX_BALL_E5_EMIF_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E5_SHIFT ) ) + +#define PINMUX_BALL_F5_ETMDATA_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F5_SHIFT ) ) +#define PINMUX_BALL_F5_EMIF_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F5_SHIFT ) ) + +#define PINMUX_BALL_G5_ETMDATA_22 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G5_SHIFT ) ) +#define PINMUX_BALL_G5_EMIF_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G5_SHIFT ) ) + +#define PINMUX_BALL_K5_ETMDATA_23 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K5_SHIFT ) ) +#define PINMUX_BALL_K5_EMIF_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K5_SHIFT ) ) + +#define PINMUX_BALL_L5_ETMDATA_24 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_EMIF_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_N2HET2_24 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_MIBSPI5NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_L5_SHIFT ) ) + +#define PINMUX_BALL_M5_ETMDATA_25 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_EMIF_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_N2HET2_25 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_MIBSPI5NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_M5_SHIFT ) ) + +#define PINMUX_BALL_N5_ETMDATA_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_N5_EMIF_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_N5_N2HET2_26 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N5_SHIFT ) ) + +#define PINMUX_BALL_P5_ETMDATA_27 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_P5_EMIF_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_P5_N2HET2_27 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P5_SHIFT ) ) + +#define PINMUX_BALL_R5_ETMDATA_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_EMIF_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_N2HET2_28 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_GIOA_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R5_SHIFT ) ) + +#define PINMUX_BALL_R6_ETMDATA_29 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_EMIF_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_N2HET2_29 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_GIOA_1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R6_SHIFT ) ) + +#define PINMUX_BALL_R7_ETMDATA_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_EMIF_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_N2HET2_30 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R7_SHIFT ) ) + +#define PINMUX_BALL_R8_ETMDATA_31 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_EMIF_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_N2HET2_31 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_GIOA_4 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R8_SHIFT ) ) + +#define PINMUX_BALL_R9_ETMTRACECLKIN \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R9_EXTCLKIN2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R9_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R9_SHIFT ) ) + +#define PINMUX_BALL_R10_ETMTRACECLKOUT \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R10_SHIFT ) ) +#define PINMUX_BALL_R10_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R10_SHIFT ) ) + +#define PINMUX_BALL_R11_ETMTRACECTL \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R11_SHIFT ) ) +#define PINMUX_BALL_R11_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R11_SHIFT ) ) + +#define PINMUX_BALL_B15_FRAYTX1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B15_SHIFT ) ) +#define PINMUX_BALL_B15_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B15_SHIFT ) ) + +#define PINMUX_BALL_B8_FRAYTX2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B8_SHIFT ) ) +#define PINMUX_BALL_B8_GIOB_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B8_SHIFT ) ) + +#define PINMUX_BALL_B16_FRAYTXEN1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B16_SHIFT ) ) +#define PINMUX_BALL_B16_GIOB_1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B16_SHIFT ) ) + +#define PINMUX_BALL_B9_FRAYTXEN2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B9_SHIFT ) ) +#define PINMUX_BALL_B9_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B9_SHIFT ) ) + +#define PINMUX_BALL_C1_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_N2HET2_00 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_eQEP2I ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_C1_SHIFT ) ) + +#define PINMUX_BALL_E1_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_E1_N2HET2_02 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E1_SHIFT ) ) + +#define PINMUX_BALL_B5_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_EXTCLKIN ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_eTPWM1A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B5_SHIFT ) ) + +#define PINMUX_BALL_H3_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_N2HET2_04 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_eTPWM1B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H3_SHIFT ) ) + +#define PINMUX_BALL_M1_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_N2HET2_06 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_eTPWM2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_M1_SHIFT ) ) + +#define PINMUX_BALL_F2_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F2_SHIFT ) ) +#define PINMUX_BALL_F2_DCAN4TX ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F2_SHIFT ) ) + +#define PINMUX_BALL_W10_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_W10_DCAN4RX \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W10_SHIFT ) ) + +#define PINMUX_BALL_J2_GIOB_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J2_SHIFT ) ) +#define PINMUX_BALL_J2_nERROR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J2_SHIFT ) ) + +#define PINMUX_BALL_F1_GIOB_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_F1_nERROR2 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_F1_nTZ1_2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_F1_SHIFT ) ) + +#define PINMUX_BALL_R2_MIBSPI1NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MIBSPI1SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MII_TXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_ECAP6 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_R2_SHIFT ) ) + +#define PINMUX_BALL_F3_MIBSPI1NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_MII_COL ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_N2HET1_17 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_eQEP1S ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_F3_SHIFT ) ) + +#define PINMUX_BALL_G3_MIBSPI1NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_MDIO ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_N2HET1_19 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G3_SHIFT ) ) + +#define PINMUX_BALL_J3_MIBSPI1NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_N2HET1_21 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_nTZ1_3 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_J3_SHIFT ) ) + +#define PINMUX_BALL_G19_MIBSPI1NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_MII_RXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_N2HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_ECAP4 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_G19_SHIFT ) ) + +#define PINMUX_BALL_V9_MIBSPI3CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_EXT_SEL_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_eQEP1A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V9_SHIFT ) ) + +#define PINMUX_BALL_V10_MIBSPI3NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_AD2EVT ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_eQEP1I \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V10_SHIFT ) ) + +#define PINMUX_BALL_V5_MIBSPI3NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_MDCLK ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_N2HET1_25 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V5_SHIFT ) ) + +#define PINMUX_BALL_B2_MIBSPI3NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_I2C1_SDA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_N2HET1_27 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_nTZ1_2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B2_SHIFT ) ) + +#define PINMUX_BALL_C3_MIBSPI3NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_I2C1_SCL ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_N2HET1_29 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_nTZ1_1 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_C3_SHIFT ) ) + +#define PINMUX_BALL_W9_MIBSPI3NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_MIBSPI3NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_N2HET1_31 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_eQEP1B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W9_SHIFT ) ) + +#define PINMUX_BALL_W8_MIBSPI3SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_EXT_SEL_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_ECAP3 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W8_SHIFT ) ) + +#define PINMUX_BALL_V8_MIBSPI3SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_EXT_ENA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_ECAP2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V8_SHIFT ) ) + +#define PINMUX_BALL_H19_MIBSPI5CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_DMM_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_MII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_RMII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_H19_SHIFT ) ) + +#define PINMUX_BALL_E19_MIBSPI5NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_DMM_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_eTPWM4A \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E19_SHIFT ) ) + +#define PINMUX_BALL_B6_MIBSPI5NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B6_SHIFT ) ) +#define PINMUX_BALL_B6_DMM_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B6_SHIFT ) ) + +#define PINMUX_BALL_W6_MIBSPI5NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W6_SHIFT ) ) +#define PINMUX_BALL_W6_DMM_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W6_SHIFT ) ) + +#define PINMUX_BALL_T12_MIBSPI5NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_T12_DMM_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T12_SHIFT ) ) + +#define PINMUX_BALL_H18_MIBSPI5NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_DMM_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_MII_RXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_ECAP5 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H18_SHIFT ) ) + +#define PINMUX_BALL_J19_MIBSPI5SIMO_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_DMM_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_MII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_RMII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J19_SHIFT ) ) + +#define PINMUX_BALL_E16_MIBSPI5SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_E16_DMM_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_E16_EXT_SEL_00 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E16_SHIFT ) ) + +#define PINMUX_BALL_H17_MIBSPI5SIMO_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_H17_DMM_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_H17_EXT_SEL_01 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H17_SHIFT ) ) + +#define PINMUX_BALL_G17_MIBSPI5SIMO_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_DMM_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_I2C2_SDA \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_EXT_SEL_02 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G17_SHIFT ) ) + +#define PINMUX_BALL_J18_MIBSPI5SOMI_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_DMM_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_MII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_RMII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J18_SHIFT ) ) + +#define PINMUX_BALL_E17_MIBSPI5SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_E17_DMM_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_E17_EXT_SEL_03 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E17_SHIFT ) ) + +#define PINMUX_BALL_H16_MIBSPI5SOMI_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_H16_DMM_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_H16_EXT_SEL_04 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H16_SHIFT ) ) + +#define PINMUX_BALL_G16_MIBSPI5SOMI_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_DMM_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_I2C2_SCL \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_EXT_ENA \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G16_SHIFT ) ) + +#define PINMUX_BALL_K18_N2HET1_00 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_MIBSPI4CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_eTPWM2B \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_K18_SHIFT ) ) + +#define PINMUX_BALL_V2_N2HET1_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_MIBSPI4NENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_N2HET2_08 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_eQEP2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V2_SHIFT ) ) + +#define PINMUX_BALL_W5_N2HET1_02 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_MIBSPI4SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_eTPWM3A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W5_SHIFT ) ) + +#define PINMUX_BALL_U1_N2HET1_03 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_MIBSPI4NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_N2HET2_10 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_eQEP2B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_U1_SHIFT ) ) + +#define PINMUX_BALL_B12_N2HET1_04 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_MIBSPI4NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_eTPWM4B \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B12_SHIFT ) ) + +#define PINMUX_BALL_V6_N2HET1_05 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_MIBSPI4SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_N2HET2_12 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_eTPWM3B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V6_SHIFT ) ) + +#define PINMUX_BALL_W3_N2HET1_06 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_SCI3RX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_eTPWM5A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W3_SHIFT ) ) + +#define PINMUX_BALL_T1_N2HET1_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_MIBSPI4NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_N2HET2_14 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_eTPWM7B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_T1_SHIFT ) ) + +#define PINMUX_BALL_E18_N2HET1_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MIBSPI1SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MII_TXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E18_SHIFT ) ) + +#define PINMUX_BALL_V7_N2HET1_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_MIBSPI4NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_N2HET2_16 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_eTPWM7A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V7_SHIFT ) ) + +#define PINMUX_BALL_D19_N2HET1_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MIBSPI4NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_nTZ1_3 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_D19_SHIFT ) ) + +#define PINMUX_BALL_E3_N2HET1_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_MIBSPI3NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_N2HET2_18 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E3_SHIFT ) ) + +#define PINMUX_BALL_B4_N2HET1_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MIBSPI4NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MII_CRS ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_RMII_CRS_DV \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B4_SHIFT ) ) + +#define PINMUX_BALL_N2_N2HET1_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_SCI3TX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_N2HET2_20 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_eTPWM5B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N2_SHIFT ) ) + +#define PINMUX_BALL_N1_N2HET1_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_MIBSPI1NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_N2HET2_22 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_ECAP1 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N1_SHIFT ) ) + +#define PINMUX_BALL_A4_N2HET1_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCI \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_A4_SHIFT ) ) + +#define PINMUX_BALL_A13_N2HET1_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_A13_EMIF_nOE \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_A13_SCI4RX ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A13_SHIFT ) ) + +#define PINMUX_BALL_J1_N2HET1_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_EMIF_RNW ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_eTPWM6A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_J1_SHIFT ) ) + +#define PINMUX_BALL_B13_N2HET1_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_B13_EMIF_nDQM_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_B13_SCI4TX ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B13_SHIFT ) ) + +#define PINMUX_BALL_P2_N2HET1_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_EMIF_nDQM_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_eTPWM6B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_P2_SHIFT ) ) + +#define PINMUX_BALL_H4_N2HET1_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H4_SHIFT ) ) +#define PINMUX_BALL_H4_EMIF_nDQM_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H4_SHIFT ) ) + +#define PINMUX_BALL_B3_N2HET1_22 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_B3_EMIF_nDQM_3 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B3_SHIFT ) ) + +#define PINMUX_BALL_J4_N2HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J4_SHIFT ) ) +#define PINMUX_BALL_J4_EMIF_BA_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J4_SHIFT ) ) + +#define PINMUX_BALL_P1_N2HET1_24 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MIBSPI1NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_RMII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_P1_SHIFT ) ) + +#define PINMUX_BALL_A14_N2HET1_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_MII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_RMII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_A14_SHIFT ) ) + +#define PINMUX_BALL_K19_N2HET1_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_RMII_REFCLK \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_K19_SHIFT ) ) + +#define PINMUX_BALL_B11_N2HET1_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_MII_RX_DV \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_eQEP2S \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B11_SHIFT ) ) + +#define PINMUX_BALL_D8_N2HET2_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D8_SHIFT ) ) +#define PINMUX_BALL_D8_N2HET1_NDIS \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D8_SHIFT ) ) + +#define PINMUX_BALL_D7_N2HET2_02 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D7_SHIFT ) ) +#define PINMUX_BALL_D7_N2HET2_NDIS \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D7_SHIFT ) ) + +#define PINMUX_BALL_D3_N2HET2_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_MIBSPI2NENA \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_MIBSPI2NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_D3_SHIFT ) ) + +#define PINMUX_BALL_D2_N2HET2_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D2_SHIFT ) ) +#define PINMUX_BALL_D2_MIBSPI2SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D2_SHIFT ) ) + +#define PINMUX_BALL_D1_N2HET2_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D1_SHIFT ) ) +#define PINMUX_BALL_D1_MIBSPI2SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D1_SHIFT ) ) + +#define PINMUX_BALL_P4_N2HET2_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P4_SHIFT ) ) +#define PINMUX_BALL_P4_LIN2RX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P4_SHIFT ) ) + +#define PINMUX_BALL_T5_N2HET2_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T5_SHIFT ) ) +#define PINMUX_BALL_T5_LIN2TX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T5_SHIFT ) ) + +#define PINMUX_BALL_T4_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T4_SHIFT ) ) +#define PINMUX_BALL_T4_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_T4_SHIFT ) ) + +#define PINMUX_BALL_U7_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U7_SHIFT ) ) +#define PINMUX_BALL_U7_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_U7_SHIFT ) ) + +#define PINMUX_BALL_E2_N2HET2_03 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E2_SHIFT ) ) +#define PINMUX_BALL_E2_MIBSPI2CLK \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E2_SHIFT ) ) + +#define PINMUX_BALL_N3_N2HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N3_SHIFT ) ) +#define PINMUX_BALL_N3_MIBSPI2NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_N3_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_GATE_EMIF_CLK_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MII ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETHERNET_SHIFT ) ) +#define PINMUX_ETHERNET_RMII ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_ASYNC \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_SYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_FILTERED \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2S_FILTER_SHIFT ) ) + +#define PINMUX_ECAP1_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP1_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP6_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP6_FILTER_SHIFT ) ) + +#define PINMUX_GIOA0_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA0_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP3_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP3_ENABLE_SHIFT ) ) + +#define SIGNAL_AD2EVT_SHIFT 0U +#define SIGNAL_GIOA_0_SHIFT 24U +#define SIGNAL_GIOA_1_SHIFT 0U +#define SIGNAL_GIOA_2_SHIFT 8U +#define SIGNAL_GIOA_3_SHIFT 16U +#define SIGNAL_GIOA_4_SHIFT 24U +#define SIGNAL_GIOA_5_SHIFT 0U +#define SIGNAL_GIOA_6_SHIFT 8U +#define SIGNAL_GIOA_7_SHIFT 16U +#define SIGNAL_GIOB_0_SHIFT 24U +#define SIGNAL_GIOB_1_SHIFT 0U +#define SIGNAL_GIOB_2_SHIFT 8U +#define SIGNAL_GIOB_3_SHIFT 16U +#define SIGNAL_GIOB_4_SHIFT 24U +#define SIGNAL_GIOB_5_SHIFT 0U +#define SIGNAL_GIOB_6_SHIFT 8U +#define SIGNAL_GIOB_7_SHIFT 16U +#define SIGNAL_MDIO_SHIFT 24U +#define SIGNAL_MIBSPI1NCS_4_SHIFT 0U +#define SIGNAL_MIBSPI1NCS_5_SHIFT 8U +#define SIGNAL_MII_COL_SHIFT 16U +#define SIGNAL_MII_CRS_SHIFT 24U +#define SIGNAL_MII_RX_DV_SHIFT 0U +#define SIGNAL_MII_RX_ER_SHIFT 8U +#define SIGNAL_MII_RXCLK_SHIFT 16U +#define SIGNAL_MII_RXD_0_SHIFT 24U +#define SIGNAL_MII_RXD_1_SHIFT 0U +#define SIGNAL_MII_RXD_2_SHIFT 8U +#define SIGNAL_MII_RXD_3_SHIFT 16U +#define SIGNAL_MII_TX_CLK_SHIFT 24U +#define SIGNAL_N2HET1_17_SHIFT 0U +#define SIGNAL_N2HET1_19_SHIFT 8U +#define SIGNAL_N2HET1_21_SHIFT 16U +#define SIGNAL_N2HET1_23_SHIFT 24U +#define SIGNAL_N2HET1_25_SHIFT 0U +#define SIGNAL_N2HET1_27_SHIFT 8U +#define SIGNAL_N2HET1_29_SHIFT 16U +#define SIGNAL_N2HET1_31_SHIFT 24U +#define SIGNAL_N2HET2_00_SHIFT 0U +#define SIGNAL_N2HET2_01_SHIFT 8U +#define SIGNAL_N2HET2_02_SHIFT 16U +#define SIGNAL_N2HET2_03_SHIFT 24U +#define SIGNAL_N2HET2_04_SHIFT 0U +#define SIGNAL_N2HET2_05_SHIFT 8U +#define SIGNAL_N2HET2_06_SHIFT 16U +#define SIGNAL_N2HET2_07_SHIFT 24U +#define SIGNAL_N2HET2_08_SHIFT 0U +#define SIGNAL_N2HET2_09_SHIFT 8U +#define SIGNAL_N2HET2_10_SHIFT 16U +#define SIGNAL_N2HET2_11_SHIFT 24U +#define SIGNAL_N2HET2_12_SHIFT 0U +#define SIGNAL_N2HET2_13_SHIFT 8U +#define SIGNAL_N2HET2_14_SHIFT 16U +#define SIGNAL_N2HET2_15_SHIFT 24U +#define SIGNAL_N2HET2_16_SHIFT 0U +#define SIGNAL_N2HET2_18_SHIFT 8U +#define SIGNAL_N2HET2_20_SHIFT 16U +#define SIGNAL_N2HET2_22_SHIFT 24U +#define SIGNAL_nTZ1_1_SHIFT 0U +#define SIGNAL_nTZ1_2_SHIFT 8U +#define SIGNAL_nTZ1_3_SHIFT 16U + +#define SIGNAL_AD2EVT_T10 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_AD2EVT_SHIFT ) ) +#define SIGNAL_AD2EVT_V10 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_AD2EVT_SHIFT ) ) + +#define SIGNAL_GIOA_0_A5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_0_SHIFT ) ) +#define SIGNAL_GIOA_0_R5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_0_SHIFT ) ) + +#define SIGNAL_GIOA_1_C2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_1_SHIFT ) ) +#define SIGNAL_GIOA_1_R6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_1_SHIFT ) ) + +#define SIGNAL_GIOA_2_C1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_2_SHIFT ) ) +#define SIGNAL_GIOA_2_B15 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_2_SHIFT ) ) + +#define SIGNAL_GIOA_3_E1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_3_SHIFT ) ) +#define SIGNAL_GIOA_3_R7 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_3_SHIFT ) ) + +#define SIGNAL_GIOA_4_A6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_4_SHIFT ) ) +#define SIGNAL_GIOA_4_R8 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_4_SHIFT ) ) + +#define SIGNAL_GIOA_5_B5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_5_SHIFT ) ) +#define SIGNAL_GIOA_5_R9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_5_SHIFT ) ) + +#define SIGNAL_GIOA_6_H3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_6_SHIFT ) ) +#define SIGNAL_GIOA_6_R10 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_6_SHIFT ) ) + +#define SIGNAL_GIOA_7_M1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_7_SHIFT ) ) +#define SIGNAL_GIOA_7_R11 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_7_SHIFT ) ) + +#define SIGNAL_GIOB_0_M2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_0_SHIFT ) ) +#define SIGNAL_GIOB_0_B8 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_0_SHIFT ) ) + +#define SIGNAL_GIOB_1_K2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_1_SHIFT ) ) +#define SIGNAL_GIOB_1_B16 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_1_SHIFT ) ) + +#define SIGNAL_GIOB_2_F2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_2_SHIFT ) ) +#define SIGNAL_GIOB_2_B9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_2_SHIFT ) ) + +#define SIGNAL_GIOB_3_W10 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_3_SHIFT ) ) +#define SIGNAL_GIOB_3_R4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_3_SHIFT ) ) + +#define SIGNAL_GIOB_4_G1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_4_SHIFT ) ) +#define SIGNAL_GIOB_4_L17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_4_SHIFT ) ) + +#define SIGNAL_GIOB_5_G2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_5_SHIFT ) ) +#define SIGNAL_GIOB_5_M17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_5_SHIFT ) ) + +#define SIGNAL_GIOB_6_J2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_6_SHIFT ) ) +#define SIGNAL_GIOB_6_R3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_6_SHIFT ) ) + +#define SIGNAL_GIOB_7_F1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_7_SHIFT ) ) +#define SIGNAL_GIOB_7_P3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_7_SHIFT ) ) + +#define SIGNAL_MDIO_F4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MDIO_SHIFT ) ) +#define SIGNAL_MDIO_G3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MDIO_SHIFT ) ) + +#define SIGNAL_MIBSPI1NCS_4_U10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MIBSPI1NCS_4_SHIFT ) ) +#define SIGNAL_MIBSPI1NCS_4_N1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MIBSPI1NCS_4_SHIFT ) ) + +#define SIGNAL_MIBSPI1NCS_5_U9 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MIBSPI1NCS_5_SHIFT ) ) +#define SIGNAL_MIBSPI1NCS_5_P1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MIBSPI1NCS_5_SHIFT ) ) + +#define SIGNAL_MII_COL_W4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_COL_SHIFT ) ) +#define SIGNAL_MII_COL_F3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_COL_SHIFT ) ) + +#define SIGNAL_MII_CRS_V4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_CRS_SHIFT ) ) +#define SIGNAL_MII_CRS_B4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_CRS_SHIFT ) ) + +#define SIGNAL_MII_RX_DV_U6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RX_DV_SHIFT ) ) +#define SIGNAL_MII_RX_DV_B11 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RX_DV_SHIFT ) ) + +#define SIGNAL_MII_RX_ER_U5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RX_ER_SHIFT ) ) +#define SIGNAL_MII_RX_ER_N19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RX_ER_SHIFT ) ) + +#define SIGNAL_MII_RXCLK_T4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXCLK_SHIFT ) ) +#define SIGNAL_MII_RXCLK_K19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXCLK_SHIFT ) ) + +#define SIGNAL_MII_RXD_0_U4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_0_SHIFT ) ) +#define SIGNAL_MII_RXD_0_P1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_0_SHIFT ) ) + +#define SIGNAL_MII_RXD_1_T3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_1_SHIFT ) ) +#define SIGNAL_MII_RXD_1_A14 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_1_SHIFT ) ) + +#define SIGNAL_MII_RXD_2_U3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_2_SHIFT ) ) +#define SIGNAL_MII_RXD_2_G19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_2_SHIFT ) ) + +#define SIGNAL_MII_RXD_3_V3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_3_SHIFT ) ) +#define SIGNAL_MII_RXD_3_H18 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_3_SHIFT ) ) + +#define SIGNAL_MII_TX_CLK_U7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_TX_CLK_SHIFT ) ) +#define SIGNAL_MII_TX_CLK_D19 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_TX_CLK_SHIFT ) ) + +#define SIGNAL_N2HET1_17_A13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_17_SHIFT ) ) +#define SIGNAL_N2HET1_17_F3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_17_SHIFT ) ) + +#define SIGNAL_N2HET1_19_B13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_19_SHIFT ) ) +#define SIGNAL_N2HET1_19_G3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_19_SHIFT ) ) + +#define SIGNAL_N2HET1_21_H4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_21_SHIFT ) ) +#define SIGNAL_N2HET1_21_J3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_21_SHIFT ) ) + +#define SIGNAL_N2HET1_23_J4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_23_SHIFT ) ) +#define SIGNAL_N2HET1_23_G19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_23_SHIFT ) ) + +#define SIGNAL_N2HET1_25_M3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_25_SHIFT ) ) +#define SIGNAL_N2HET1_25_V5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_25_SHIFT ) ) + +#define SIGNAL_N2HET1_27_A9 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_27_SHIFT ) ) +#define SIGNAL_N2HET1_27_B2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_27_SHIFT ) ) + +#define SIGNAL_N2HET1_29_A3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_29_SHIFT ) ) +#define SIGNAL_N2HET1_29_C3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_29_SHIFT ) ) + +#define SIGNAL_N2HET1_31_J17 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_31_SHIFT ) ) +#define SIGNAL_N2HET1_31_W9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_31_SHIFT ) ) + +#define SIGNAL_N2HET2_00_D6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_00_SHIFT ) ) +#define SIGNAL_N2HET2_00_C1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_00_SHIFT ) ) + +#define SIGNAL_N2HET2_01_D8 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_01_SHIFT ) ) +#define SIGNAL_N2HET2_01_D4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_01_SHIFT ) ) + +#define SIGNAL_N2HET2_02_D7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_02_SHIFT ) ) +#define SIGNAL_N2HET2_02_E1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_02_SHIFT ) ) + +#define SIGNAL_N2HET2_03_E2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_03_SHIFT ) ) +#define SIGNAL_N2HET2_03_D5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_03_SHIFT ) ) + +#define SIGNAL_N2HET2_04_D13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_04_SHIFT ) ) +#define SIGNAL_N2HET2_04_H3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_04_SHIFT ) ) + +#define SIGNAL_N2HET2_05_D12 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_05_SHIFT ) ) +#define SIGNAL_N2HET2_05_D16 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_05_SHIFT ) ) + +#define SIGNAL_N2HET2_06_D11 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_06_SHIFT ) ) +#define SIGNAL_N2HET2_06_M1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_06_SHIFT ) ) + +#define SIGNAL_N2HET2_07_N3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_07_SHIFT ) ) +#define SIGNAL_N2HET2_07_N17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_07_SHIFT ) ) + +#define SIGNAL_N2HET2_08_K16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_08_SHIFT ) ) +#define SIGNAL_N2HET2_08_V2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_08_SHIFT ) ) + +#define SIGNAL_N2HET2_09_L16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_09_SHIFT ) ) +#define SIGNAL_N2HET2_09_K17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_09_SHIFT ) ) + +#define SIGNAL_N2HET2_10_M16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_10_SHIFT ) ) +#define SIGNAL_N2HET2_10_U1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_10_SHIFT ) ) + +#define SIGNAL_N2HET2_11_N16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_11_SHIFT ) ) +#define SIGNAL_N2HET2_11_C4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_11_SHIFT ) ) + +#define SIGNAL_N2HET2_12_D3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_12_SHIFT ) ) +#define SIGNAL_N2HET2_12_V6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_12_SHIFT ) ) + +#define SIGNAL_N2HET2_13_D2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_13_SHIFT ) ) +#define SIGNAL_N2HET2_13_C5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_13_SHIFT ) ) + +#define SIGNAL_N2HET2_14_D1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_14_SHIFT ) ) +#define SIGNAL_N2HET2_14_T1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_14_SHIFT ) ) + +#define SIGNAL_N2HET2_15_K4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_15_SHIFT ) ) +#define SIGNAL_N2HET2_15_C6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_15_SHIFT ) ) + +#define SIGNAL_N2HET2_16_L4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_16_SHIFT ) ) +#define SIGNAL_N2HET2_16_V7 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_16_SHIFT ) ) + +#define SIGNAL_N2HET2_18_N4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_18_SHIFT ) ) +#define SIGNAL_N2HET2_18_E3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_18_SHIFT ) ) + +#define SIGNAL_N2HET2_20_T5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_20_SHIFT ) ) +#define SIGNAL_N2HET2_20_N2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_20_SHIFT ) ) + +#define SIGNAL_N2HET2_22_T7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_22_SHIFT ) ) +#define SIGNAL_N2HET2_22_N1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_22_SHIFT ) ) + +#define SIGNAL_nTZ1_1_N19 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_1_SHIFT ) ) +#define SIGNAL_nTZ1_1_C3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_1_SHIFT ) ) + +#define SIGNAL_nTZ1_2_F1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_2_SHIFT ) ) +#define SIGNAL_nTZ1_2_B2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_2_SHIFT ) ) + +#define SIGNAL_nTZ1_3_J3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_3_SHIFT ) ) +#define SIGNAL_nTZ1_3_D19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_3_SHIFT ) ) + +/** @fn void muxInit(void) + * @brief Initializes the PINMUX Driver + * + * This function initializes the PINMUX module and configures the selected + * pinmux settings as per the user selection in the GUI + */ +void muxInit( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h new file mode 100644 index 00000000000..bedac83e298 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h @@ -0,0 +1,339 @@ +/** @file pom.h + * @brief POM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __POM_H__ +#define __POM_H__ + +#include "reg_pom.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pom_region_size + * @brief Alias names for pom region size + * This enumeration is used to provide alias names for POM region size: + */ +enum pom_region_size +{ + SIZE_32BYTES = 0U, + SIZE_64BYTES = 1U, + SIZE_128BYTES = 2U, + SIZE_256BYTES = 3U, + SIZE_512BYTES = 4U, + SIZE_1KB = 5U, + SIZE_2KB = 6U, + SIZE_4KB = 7U, + SIZE_8KB = 8U, + SIZE_16KB = 9U, + SIZE_32KB = 10U, + SIZE_64KB = 11U, + SIZE_128KB = 12U, + SIZE_256KB = 13U +}; + +/** @def INTERNAL_RAM + * @brief Alias name for Internal RAM + */ +#define INTERNAL_RAM 0x08000000U + +/** @def SDRAM + * @brief Alias name for SD RAM + */ +#define SDRAM 0x80000000U + +/** @def ASYNC_MEMORY + * @brief Alias name for Async RAM + */ +#define ASYNC_MEMORY 0x60000000U + +typedef uint32 REGION_t; + +/** @struct REGION_CONFIG_ST + * @brief POM region configuration + */ +typedef struct +{ + uint32 Prog_Reg_Sta_Addr; + uint32 Ovly_Reg_Sta_Addr; + uint32 Reg_Size; +} REGION_CONFIG_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct pom_config_reg +{ + uint32 CONFIG_POMGLBCTRL; + uint32 CONFIG_POMPROGSTART0; + uint32 CONFIG_POMOVLSTART0; + uint32 CONFIG_POMREGSIZE0; + uint32 CONFIG_POMPROGSTART1; + uint32 CONFIG_POMOVLSTART1; + uint32 CONFIG_POMREGSIZE1; + uint32 CONFIG_POMPROGSTART2; + uint32 CONFIG_POMOVLSTART2; + uint32 CONFIG_POMREGSIZE2; + uint32 CONFIG_POMPROGSTART3; + uint32 CONFIG_POMOVLSTART3; + uint32 CONFIG_POMREGSIZE3; + uint32 CONFIG_POMPROGSTART4; + uint32 CONFIG_POMOVLSTART4; + uint32 CONFIG_POMREGSIZE4; + uint32 CONFIG_POMPROGSTART5; + uint32 CONFIG_POMOVLSTART5; + uint32 CONFIG_POMREGSIZE5; + uint32 CONFIG_POMPROGSTART6; + uint32 CONFIG_POMOVLSTART6; + uint32 CONFIG_POMREGSIZE6; + uint32 CONFIG_POMPROGSTART7; + uint32 CONFIG_POMOVLSTART7; + uint32 CONFIG_POMREGSIZE7; + uint32 CONFIG_POMPROGSTART8; + uint32 CONFIG_POMOVLSTART8; + uint32 CONFIG_POMREGSIZE8; + uint32 CONFIG_POMPROGSTART9; + uint32 CONFIG_POMOVLSTART9; + uint32 CONFIG_POMREGSIZE9; + uint32 CONFIG_POMPROGSTART10; + uint32 CONFIG_POMOVLSTART10; + uint32 CONFIG_POMREGSIZE10; + uint32 CONFIG_POMPROGSTART11; + uint32 CONFIG_POMOVLSTART11; + uint32 CONFIG_POMREGSIZE11; + uint32 CONFIG_POMPROGSTART12; + uint32 CONFIG_POMOVLSTART12; + uint32 CONFIG_POMREGSIZE12; + uint32 CONFIG_POMPROGSTART13; + uint32 CONFIG_POMOVLSTART13; + uint32 CONFIG_POMREGSIZE13; + uint32 CONFIG_POMPROGSTART14; + uint32 CONFIG_POMOVLSTART14; + uint32 CONFIG_POMREGSIZE14; + uint32 CONFIG_POMPROGSTART15; + uint32 CONFIG_POMOVLSTART15; + uint32 CONFIG_POMREGSIZE15; + uint32 CONFIG_POMPROGSTART16; + uint32 CONFIG_POMOVLSTART16; + uint32 CONFIG_POMREGSIZE16; + uint32 CONFIG_POMPROGSTART17; + uint32 CONFIG_POMOVLSTART17; + uint32 CONFIG_POMREGSIZE17; + uint32 CONFIG_POMPROGSTART18; + uint32 CONFIG_POMOVLSTART18; + uint32 CONFIG_POMREGSIZE18; + uint32 CONFIG_POMPROGSTART19; + uint32 CONFIG_POMOVLSTART19; + uint32 CONFIG_POMREGSIZE19; + uint32 CONFIG_POMPROGSTART20; + uint32 CONFIG_POMOVLSTART20; + uint32 CONFIG_POMREGSIZE20; + uint32 CONFIG_POMPROGSTART21; + uint32 CONFIG_POMOVLSTART21; + uint32 CONFIG_POMREGSIZE21; + uint32 CONFIG_POMPROGSTART22; + uint32 CONFIG_POMOVLSTART22; + uint32 CONFIG_POMREGSIZE22; + uint32 CONFIG_POMPROGSTART23; + uint32 CONFIG_POMOVLSTART23; + uint32 CONFIG_POMREGSIZE23; + uint32 CONFIG_POMPROGSTART24; + uint32 CONFIG_POMOVLSTART24; + uint32 CONFIG_POMREGSIZE24; + uint32 CONFIG_POMPROGSTART25; + uint32 CONFIG_POMOVLSTART25; + uint32 CONFIG_POMREGSIZE25; + uint32 CONFIG_POMPROGSTART26; + uint32 CONFIG_POMOVLSTART26; + uint32 CONFIG_POMREGSIZE26; + uint32 CONFIG_POMPROGSTART27; + uint32 CONFIG_POMOVLSTART27; + uint32 CONFIG_POMREGSIZE27; + uint32 CONFIG_POMPROGSTART28; + uint32 CONFIG_POMOVLSTART28; + uint32 CONFIG_POMREGSIZE28; + uint32 CONFIG_POMPROGSTART29; + uint32 CONFIG_POMOVLSTART29; + uint32 CONFIG_POMREGSIZE29; + uint32 CONFIG_POMPROGSTART30; + uint32 CONFIG_POMOVLSTART30; + uint32 CONFIG_POMREGSIZE30; + uint32 CONFIG_POMPROGSTART31; + uint32 CONFIG_POMOVLSTART31; + uint32 CONFIG_POMREGSIZE31; +} pom_config_reg_t; + +/* Configuration registers initial value for POM*/ +#define POM_POMGLBCTRL_CONFIGVALUE ( ( uint32 ) INTERNAL_RAM | 0x00000005U ) +#define POM_POMPROGSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU ) +#define POM_POMOVLSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define POM_POMREGSIZE0_CONFIGVALUE ( ( uint32 ) SIZE_64BYTES ) +#define POM_POMPROGSTART1_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART1_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE1_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART2_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART2_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE2_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART3_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART3_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE3_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART4_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART4_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE4_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART5_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART5_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE5_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART6_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART6_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE6_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART7_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART7_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE7_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART8_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART8_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE8_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART9_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART9_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE9_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART10_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART10_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE10_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART11_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART11_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE11_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART12_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART12_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE12_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART13_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART13_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE13_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART14_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART14_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE14_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART15_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART15_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE15_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART16_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART16_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE16_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART17_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART17_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE17_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART18_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART18_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE18_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART19_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART19_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE19_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART20_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART20_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE20_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART21_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART21_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE21_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART22_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART22_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE22_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART23_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART23_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE23_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART24_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART24_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE24_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART25_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART25_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE25_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART26_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART26_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE26_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART27_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART27_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE27_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART28_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART28_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE28_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART29_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART29_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE29_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART30_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART30_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE30_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART31_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART31_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE31_CONFIGVALUE 0x00000000U + +/** + * @defgroup POM POM + * @brief Parameter Overlay Module. + * + * The POM provides a mechanism to redirect accesses to non-volatile memory into a + * volatile memory internal or external to the device. The data requested by the CPU will + * be fetched from the overlay memory instead of the main non-volatile memory. + * + * Related Files + * - reg_pom.h + * - pom.h + * - pom.c + * @addtogroup POM + * @{ + */ + +/* POM Interface Functions */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ); +void POM_Reset( void ); +void POM_Init( void ); +void POM_Enable( void ); +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* __POM_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h new file mode 100644 index 00000000000..1e8f755d94b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h @@ -0,0 +1,252 @@ +/** @file reg_adc.h + * @brief ADC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ADC_H__ +#define __REG_ADC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Adc Register Frame Definition */ +/** @struct adcBase + * @brief ADC Register Frame Definition + * + * This type is used to access the ADC Registers. + */ +/** @typedef adcBASE_t + * @brief ADC Register Frame Type Definition + * + * This type is used to access the ADC Registers. + */ +typedef volatile struct adcBase +{ + uint32 RSTCR; /**< 0x0000: Reset control register */ + uint32 OPMODECR; /**< 0x0004: Operating mode control register */ + uint32 CLOCKCR; /**< 0x0008: Clock control register */ + uint32 CALCR; /**< 0x000C: Calibration control register */ + uint32 GxMODECR[ 3U ]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */ + uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */ + uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */ + uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */ + uint32 GxINTENA[ 3U ]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register + */ + uint32 GxINTFLG[ 3U ]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */ + uint32 GxINTCR[ 3U ]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */ + uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */ + uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */ + uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */ + uint32 BNDCR; /**< 0x0058: Buffer boundary control register */ + uint32 BNDEND; /**< 0x005C: Buffer boundary end register */ + uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */ + uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */ + uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */ + uint32 EVSR; /**< 0x006C: Group 0 status register */ + uint32 G1SR; /**< 0x0070: Group 1 status register */ + uint32 G2SR; /**< 0x0074: Group 2 status register */ + uint32 GxSEL[ 3U ]; /**< 0x0078-0x007C: Group 0-2 channel select register */ + uint32 CALR; /**< 0x0084: Calibration register */ + uint32 SMSTATE; /**< 0x0088: State machine state register */ + uint32 LASTCONV; /**< 0x008C: Last conversion register */ + struct + { + uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */ + uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */ + uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */ + uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */ + uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */ + uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */ + uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */ + uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */ + } GxBUF[ 3U ]; + uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */ + uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */ + uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */ + uint32 EVTDIR; /**< 0x00FC: Event pin direction register */ + uint32 EVTOUT; /**< 0x0100: Event pin digital output register */ + uint32 EVTIN; /**< 0x0104: Event pin digital input register */ + uint32 EVTSET; /**< 0x0108: Event pin set register */ + uint32 EVTCLR; /**< 0x010C: Event pin clear register */ + uint32 EVTPDR; /**< 0x0110: Event pin open drain register */ + uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */ + uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */ + uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */ + uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */ + uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */ + uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */ + uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */ + uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */ + uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */ + uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */ + uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */ + uint32 rsvd1; /**< 0x0140: Reserved */ + uint32 rsvd2; /**< 0x0144: Reserved */ + uint32 rsvd3; /**< 0x0148: Reserved */ + uint32 rsvd4; /**< 0x014C: Reserved */ + uint32 rsvd5; /**< 0x0150: Reserved */ + uint32 rsvd6; /**< 0x0154: Reserved */ + uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */ + uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */ + uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */ + uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */ + uint32 GxFIFORESETCR[ 3U ]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register + */ + uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */ + uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */ + uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */ + uint32 PARCR; /**< 0x0180: Parity control register */ + uint32 PARADDR; /**< 0x0184: Parity error address register */ + uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */ + uint32 rsvd7; /**< 0x018C: Reserved */ + uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control + Register */ + uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register + */ + uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register + */ + uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */ + uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */ + uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */ + uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */ + uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */ + uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */ +} adcBASE_t; + +/** @struct adcLUTEntry + * @brief ADC Look-Up Table Entry + * + * This type is used to access ADC Look-Up Table Entry + */ +/** @typedef adcLUTEntry_t + * @brief ADC Look-Up Table Entry + * + * This type is used to access the Look-Up Table Entry. + */ +typedef struct adcLUTEntry +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 EV_INT_CHN_MUX_SEL; + uint8 EV_EXT_CHN_MUX_SEL; + uint16 rsvd; +#else + uint16 rsvd; + uint8 EV_EXT_CHN_MUX_SEL; + uint8 EV_INT_CHN_MUX_SEL; +#endif +} adcLUTEntry_t; + +/** @struct adcLUT + * @brief ADC Look-Up Table + * + * This type is used to access ADC Look-Up Table + */ +/** @typedef adcLUT_t + * @brief ADC Look-Up Table + * + * This type is used to access the ADC Look-Up Table. + */ +typedef volatile struct adcLUT +{ + adcLUTEntry_t eventGroup[ 32 ]; + adcLUTEntry_t Group1[ 32 ]; + adcLUTEntry_t Group2[ 32 ]; +} adcLUT_t; + +/** @def adcREG1 + * @brief ADC1 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC1 registers. + */ +#define adcREG1 ( ( adcBASE_t * ) 0xFFF7C000U ) + +/** @def adcREG2 + * @brief ADC2 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC2 registers. + */ +#define adcREG2 ( ( adcBASE_t * ) 0xFFF7C200U ) + +/** @def adcRAM1 + * @brief ADC1 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 RAM. + */ +#define adcRAM1 ( *( volatile uint32 * ) 0xFF3E0000U ) + +/** @def adcRAM2 + * @brief ADC2 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 RAM. + */ +#define adcRAM2 ( *( volatile uint32 * ) 0xFF3A0000U ) + +/** @def adcPARRAM1 + * @brief ADC1 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 Parity RAM. + */ +#define adcPARRAM1 ( *( volatile uint32 * ) ( 0xFF3E0000U + 0x1000U ) ) + +/** @def adcPARRAM2 + * @brief ADC2 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 Parity RAM. + */ +#define adcPARRAM2 ( *( volatile uint32 * ) ( 0xFF3A0000U + 0x1000U ) ) + +/** @def adcLUT1 + * @brief ADC1 Look-Up Table + * + * This pointer is used by the ADC driver to access the ADC1 Look-Up Table. + */ +#define adcLUT1 ( ( adcLUT_t * ) ( 0xFF3E0000U + 0x2000U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h new file mode 100644 index 00000000000..2bb705c66cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h @@ -0,0 +1,230 @@ +/** @file reg_can.h + * @brief CAN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CAN_H__ +#define __REG_CAN_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Can Register Frame Definition */ +/** @struct canBase + * @brief CAN Register Frame Definition + * + * This type is used to access the CAN Registers. + */ +/** @typedef canBASE_t + * @brief CAN Register Frame Type Definition + * + * This type is used to access the CAN Registers. + */ +typedef volatile struct canBase +{ + uint32 CTL; /**< 0x0000: Control Register */ + uint32 ES; /**< 0x0004: Error and Status Register */ + uint32 EERC; /**< 0x0008: Error Counter Register */ + uint32 BTR; /**< 0x000C: Bit Timing Register */ + uint32 INT; /**< 0x0010: Interrupt Register */ + uint32 TEST; /**< 0x0014: Test Register */ + uint32 rsvd1; /**< 0x0018: Reserved */ + uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */ + uint32 rsvd11; /**< 0x0020: Reserved */ + uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */ + uint32 ECCDIAG_STAT; /**< 0x0028: ECC Diagnostic Status Register */ + uint32 ECC_CS; /**< 0x002C: ECC Control and Status Register */ + uint32 ECC_SERR; /**< 0x0030: ECC Single Bit Error code register */ + uint32 rsvd2[ 19 ]; /**< 0x002C - 0x7C: Reserved */ + uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */ + uint32 TXRQX; /**< 0x0084: Transmission Request X Register */ + uint32 TXRQx[ 4U ]; /**< 0x0088-0x0094: Transmission Request Registers */ + uint32 NWDATX; /**< 0x0098: New Data X Register */ + uint32 NWDATx[ 4U ]; /**< 0x009C-0x00A8: New Data Registers */ + uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */ + uint32 INTPNDx[ 4U ]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */ + uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */ + uint32 MSGVALx[ 4U ]; /**< 0x00C4-0x00D0: Message Valid Registers */ + uint32 rsvd3; /**< 0x00D4: Reserved */ + uint32 INTMUXx[ 4U ]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */ + uint32 rsvd4[ 6 ]; /**< 0x00E8: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ +#else + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ +#endif + uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */ + uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */ + uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */ + uint8 IF1DATx[ 8U ]; /**< 0x0110-0x0114: IF1 Data A and B Registers */ + uint32 rsvd5[ 2 ]; /**< 0x0118: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ +#else + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */ +#endif + uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */ + uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */ + uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */ + uint8 IF2DATx[ 8U ]; /**< 0x0130-0x0134: IF2 Data A and B Registers */ + uint32 rsvd6[ 2 ]; /**< 0x0138: Reserved */ + uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */ + uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */ + uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */ + uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */ + uint8 IF3DATx[ 8U ]; /**< 0x0150-0x0154: IF3 Data A and B Registers */ + uint32 rsvd7[ 2 ]; /**< 0x0158: Reserved */ + uint32 IF3UEy[ 4U ]; /**< 0x0160-0x016C: IF3 Update Enable Registers */ + uint32 rsvd8[ 28 ]; /**< 0x0170: Reserved */ + uint32 TIOC; /**< 0x01E0: TX IO Control Register */ + uint32 RIOC; /**< 0x01E4: RX IO Control Register */ +} canBASE_t; + +/** @def canREG1 + * @brief CAN1 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN1 registers. + */ +#define canREG1 ( ( canBASE_t * ) 0xFFF7DC00U ) + +/** @def canREG2 + * @brief CAN2 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN2 registers. + */ +#define canREG2 ( ( canBASE_t * ) 0xFFF7DE00U ) + +/** @def canREG3 + * @brief CAN3 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN3 registers. + */ +#define canREG3 ( ( canBASE_t * ) 0xFFF7E000U ) + +/** @def canREG4 + * @brief CAN4 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN4 registers. + */ +#define canREG4 ( ( canBASE_t * ) 0xFFF7E200U ) + +/** @def canRAM1 + * @brief CAN1 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 RAM. + */ +#define canRAM1 ( *( volatile uint32 * ) 0xFF1E0000U ) + +/** @def canRAM2 + * @brief CAN2 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 RAM. + */ +#define canRAM2 ( *( volatile uint32 * ) 0xFF1C0000U ) + +/** @def canRAM3 + * @brief CAN3 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 RAM. + */ +#define canRAM3 ( *( volatile uint32 * ) 0xFF1A0000U ) + +/** @def canRAM4 + * @brief CAN4 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN4 RAM. + */ +#define canRAM4 ( *( volatile uint32 * ) 0xFF180000U ) + +/** @def canPARRAM1 + * @brief CAN1 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM1 ( *( volatile uint32 * ) ( 0xFF1E0000U + 0x10U ) ) + +/** @def canPARRAM2 + * @brief CAN2 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM2 ( *( volatile uint32 * ) ( 0xFF1C0000U + 0x10U ) ) + +/** @def canPARRAM3 + * @brief CAN3 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM3 ( *( volatile uint32 * ) ( 0xFF1A0000U + 0x10U ) ) + +/** @def canPARRAM4 + * @brief CAN4 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN4 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM4 ( *( volatile uint32 * ) ( 0xFF180000U + 0x10U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h new file mode 100644 index 00000000000..6a7b66a4ab5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h @@ -0,0 +1,84 @@ +/** @file reg_ccmr5.h + * @brief CCMR5 Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CCMR5_H__ +#define __REG_CCMR5_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ +/** @struct ccmr5Base + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ +/** @typedef ccmr5BASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct ccmr5Base +{ + uint32 CCMSR1; /* 0x00 Status Register 1 */ + uint32 CCMKEYR1; /* 0x04 Key Register 1 */ + uint32 CCMSR2; /* 0x08 Status Register 2 */ + uint32 CCMKEYR2; /* 0x0C Key Register 2 */ + uint32 CCMSR3; /* 0x10 Status Register 3 */ + uint32 CCMKEYR3; /* 0x14 Key Register 3 */ + uint32 CCMPOLCNTRL; /* 0x18 Polarity Control Register */ + uint32 CCMSR4; /* 0x1C Status Register 4 */ + uint32 CCMKEYR4; /* 0x20 Key Register 4 */ + uint32 CCMPDSTAT0; /* 0x24 Power Domain Status Register 0 */ +} ccmr5BASE_t; + +#define ccmr5REG ( ( ccmr5BASE_t * ) 0xFFFFF600U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h new file mode 100644 index 00000000000..fe70e50d066 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h @@ -0,0 +1,132 @@ +/** @file reg_crc.h + * @brief CRC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CRC_H__ +#define __REG_CRC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Crc Register Frame Definition */ +/** @struct crcBase + * @brief CRC Register Frame Definition + * + * This type is used to access the CRC Registers. + */ +/** @typedef crcBASE_t + * @brief CRC Register Frame Type Definition + * + * This type is used to access the CRC Registers. + */ +typedef volatile struct crcBase +{ + uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/ + uint32 rvd1; /**< 0x0004: reserved >**/ + uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/ + uint32 rvd2; /**< 0x000C: reserved >**/ + uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/ + uint32 rvd3; /**< 0x0014: reserved >**/ + uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/ + uint32 rvd4; /**< 0x001C: reserved >**/ + uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/ + uint32 rvd5; /**< 0x0024: reserved >**/ + uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/ + uint32 rvd6; /**< 0x002C: reserved >**/ + uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/ + uint32 rvd7; /**< 0x0034: reserved >**/ + uint32 BUSY; /**< 0x0038: CRC Busy Register >**/ + uint32 rvd8; /**< 0x003C: reserved >**/ + uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/ + uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/ + uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/ + uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/ + uint32 rvd9[ 3 ]; /**< 0x0054: reserved >**/ + uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/ + uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/ + uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/ + uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/ + uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/ + uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/ + uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/ + uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/ + uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/ + uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/ + uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/ + uint32 rvd10[ 3 ]; /**< 0x0094: reserved >**/ + uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/ + uint32 PSA_SIGREGH2; /**< 0x00A4: Channel 2 PSA signature high register >**/ + uint32 REGL2; /**< 0x00A8: Channel 2 CRC value low register >**/ + uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/ + uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/ + uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/ + uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/ +} crcBASE_t; + +/** @def crcREG1 + * @brief CRC1 Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC1 registers. + */ +#define crcREG1 ( ( crcBASE_t * ) 0xFE000000U ) + +/** @def crcREG2 + * @brief CRC2 Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC2 registers. + */ +#define crcREG2 ( ( crcBASE_t * ) 0xFB000000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h new file mode 100644 index 00000000000..f60eefcd29b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h @@ -0,0 +1,99 @@ +/** @file reg_dcc.h + * @brief DCC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DCC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DCC_H__ +#define __REG_DCC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dcc Register Frame Definition */ +/** @struct dccBase + * @brief DCC Base Register Definition + * + * This structure is used to access the DCC module registers. + */ +/** @typedef dccBASE_t + * @brief DCC Register Frame Type Definition + * + * This type is used to access the DCC Registers. + */ +typedef volatile struct dccBase +{ + uint32 GCTRL; /**< 0x0000: DCC Control Register */ + uint32 REV; /**< 0x0004: DCC Revision Id Register */ + uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */ + uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */ + uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */ + uint32 STAT; /**< 0x0014: DCC Status Register */ + uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */ + uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */ + uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */ + uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */ + uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */ +} dccBASE_t; + +/** @def dccREG1 + * @brief DCC1 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U ) + +/** @def dccREG2 + * @brief DCC2 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG2 ( ( dccBASE_t * ) 0xFFFFF400U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h new file mode 100644 index 00000000000..f0aa785319e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h @@ -0,0 +1,242 @@ +/** @file reg_dma.h + * @brief DMA Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMA_H__ +#define __REG_DMA_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DMA Register Frame Definition */ +/** @struct dmaBase + * @brief DMA Register Frame Definition + * + * This type is used to access the DMA Registers. + */ +/** @struct dmaBASE_t + * @brief DMA Register Definition + * + * This structure is used to access the DMA module egisters. + */ +typedef volatile struct dmaBase +{ + uint32 GCTRL; /**< 0x0000: Global Control Register */ + uint32 PEND; /**< 0x0004: Channel Pending Register */ + uint32 FBREG; /**< 0x0008: Fall Back Register */ + uint32 DMASTAT; /**< 0x000C: Status Register */ + uint32 rsvd1; /**< 0x0010: Reserved */ + uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */ + uint32 rsvd2; /**< 0x0018: Reserved */ + uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */ + uint32 rsvd3; /**< 0x0020: Reserved */ + uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */ + uint32 rsvd4; /**< 0x0028: Reserved */ + uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */ + uint32 rsvd5; /**< 0x0030: Reserved */ + uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */ + uint32 rsvd6; /**< 0x0038: Reserved */ + uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */ + uint32 rsvd7; /**< 0x0040: Reserved */ + uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */ + uint32 rsvd8; /**< 0x0048: Reserved */ + uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Reset */ + uint32 rsvd9; /**< 0x0050: Reserved */ + uint32 DREQASI[ 8U ]; /**< 0x0054 - 0x70: DMA Request Assignment Register */ + uint32 rsvd10[ 8U ]; /**< 0x0074 - 0x90: Reserved */ + uint32 PAR[ 4U ]; /**< 0x0094 - 0xA0: Port Assignment Register */ + uint32 rsvd11[ 4U ]; /**< 0x00A4 - 0xB0: Reserved */ + uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */ + uint32 rsvd12; /**< 0x00B8: Reserved */ + uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */ + uint32 rsvd13; /**< 0x00C0: Reserved */ + uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */ + uint32 rsvd14; /**< 0x00C8: Reserved */ + uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */ + uint32 rsvd15; /**< 0x00D0: Reserved */ + uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */ + uint32 rsvd16; /**< 0x00D8: Reserved */ + uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */ + uint32 rsvd17; /**< 0x00E0: Reserved */ + uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */ + uint32 rsvd18; /**< 0x00E8: Reserved */ + uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */ + uint32 rsvd19; /**< 0x00F0: Reserved */ + uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */ + uint32 rsvd20; /**< 0x00F8: Reserved */ + uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */ + uint32 rsvd21; /**< 0x0100: Reserved */ + uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */ + uint32 rsvd22; /**< 0x0108: Reserved */ + uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */ + uint32 rsvd23; /**< 0x0110: Reserved */ + uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */ + uint32 rsvd24; /**< 0x0118: Reserved */ + uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */ + uint32 rsvd25; /**< 0x0120: Reserved */ + uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */ + uint32 rsvd26; /**< 0x0128: Reserved */ + uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */ + uint32 rsvd27; /**< 0x0130: Reserved */ + uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */ + uint32 rsvd28; /**< 0x0138: Reserved */ + uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */ + uint32 rsvd29; /**< 0x0140: Reserved */ + uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */ + uint32 rsvd30; /**< 0x0148: Reserved */ + uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */ + uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */ + uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */ + uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */ + uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */ + uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */ + uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */ + uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */ + uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */ + uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */ + uint32 rsvd31; /**< 0x0174: Reserved */ + uint32 PTCRL; /**< 0x0178: Port Control Register */ + uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */ + uint32 DCTRL; /**< 0x0180: Debug Control */ + uint32 WPR; /**< 0x0184: Watch Point Register */ + uint32 WMR; /**< 0x0188: Watch Mask Register */ + uint32 FAACSADDR; /**< 0x018C: */ + uint32 FAACDADDR; /**< 0x0190: */ + uint32 FAACTC; /**< 0x0194: */ + uint32 FBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */ + uint32 FBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */ + uint32 FBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */ + uint32 rsvd32; /**< 0x01A4: Reserved */ + uint32 DMAPCR; /**< 0x01A8: Parity Control Register */ + uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */ + uint32 DMAMPCTRL1; /**< 0x01B0: DMA Memory Protection Control Register */ + uint32 DMAMPST1; /**< 0x01B4: DMA Memory Protection Status Register */ + + struct + { + uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + } DMAMPR_L[ 4U ]; + + uint32 DMAMPCTRL2; /**< 0x01D8: Memory Protection Control Register */ + uint32 DMAPST2; /**< 0x01DC: Memory Protection Status Register */ + + struct + { + uint32 STARTADD; /**< 0x01E0, 0x01E8, 0x01F0, 0x01F8: DMA Memory Protection + Region Start Address Register */ + uint32 ENDADD; /**< 0x01E4, 0x01EC, 0x01F4, 0x01FC: DMA Memory Protection Region + Start Address Register */ + } DMAMPR_H[ 4U ]; + + uint32 rsvd33[ 10U ]; /**< 0x0200 - 0x224: Reserved */ + uint32 DMASECCCTRL; /**< 0x0228: DMA Single bit ECC Control RegisteR */ + uint32 rsvd34; /**< 0x022C: Reserved */ + uint32 DMAECCSBE; /**< 0x0230: DMA ECC Single bit Error Address Register */ + uint32 rsvd35[ 3U ]; /**< 0x0234 - 0x023C: Reserved */ + uint32 FIFOASTATREG; /**< 0x0240: FIFO A Status Register */ + uint32 FIFOBSTATREG; /**< 0x0244: FIFO B Status Register */ + uint32 rsvd37[ 58U ]; /**< 0x0248 - 0x032C: Reserved */ + uint32 DMAREQPS1; /**< 0x0330: DMA Request Polarity Select Register 1 */ + uint32 DMAREQPS0; /**< 0x0334: DMA Request Polarity Select Register 0 */ + uint32 rsvd38[ 32 ]; /**< 0x0338 - 0x033C: Reserved */ + uint32 TERECTRL; /**< 0x0340: TER Event Control Register */ + uint32 TERFLAG; /**< 0x0344: TER Event Flag Register */ + uint32 TERROFFSET; /**< 0x0348: TER Event Channel Offset Register */ +} dmaBASE_t; + +typedef volatile struct +{ + struct /* 0x000-0x400 */ + { + uint32 ISADDR; + uint32 IDADDR; + uint32 ITCOUNT; + uint32 rsvd1; + uint32 CHCTRL; + uint32 EIOFF; + uint32 FIOFF; + uint32 rsvd2; + } PCP[ 32U ]; + + struct /* 0x400-0x800 */ + { + uint32 res[ 256U ]; + } RESERVED; + + struct /* 0x800-0xA00 */ + { + uint32 CSADDR; + uint32 CDADDR; + uint32 CTCOUNT; + uint32 rsvd3; + } WCP[ 32U ]; + +} dmaRAMBASE_t; + +#define dmaRAMREG ( ( dmaRAMBASE_t * ) 0xFFF80000U ) + +/** @def dmaREG + * @brief DMA1 Register Frame Pointer + * + * This pointer is used by the DMA driver to access the DMA module registers. + */ +#define dmaREG ( ( dmaBASE_t * ) 0xFFFFF000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* REG_DMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h new file mode 100644 index 00000000000..b53fab6355d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h @@ -0,0 +1,127 @@ +/** @file reg_dmm.h + * @brief DMM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DMM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMM_H__ +#define __REG_DMM_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dmm Register Frame Definition */ +/** @struct dmmBase + * @brief DMM Base Register Definition + * + * This structure is used to access the DMM module registers. + */ +/** @typedef dmmBASE_t + * @brief DMM Register Frame Type Definition + * + * This type is used to access the DMM Registers. + */ + +typedef volatile struct dmmBase +{ + uint32 GLBCTRL; /**< 0x0000: Global control register 0 */ + uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */ + uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */ + uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */ + uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */ + uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */ + uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */ + uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */ + uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */ + uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */ + uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */ + uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */ + uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */ + uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */ + uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */ + uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */ + uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */ + uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */ + uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */ + uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */ + uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */ + uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */ + uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */ + uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */ + uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */ + uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */ + uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */ + uint32 PC0; /**< 0x006C: DMM Pin Control 0 */ + uint32 PC1; /**< 0x0070: DMM Pin Control 1 */ + uint32 PC2; /**< 0x0074: DMM Pin Control 2 */ + uint32 PC3; /**< 0x0078: DMM Pin Control 3 */ + uint32 PC4; /**< 0x007C: DMM Pin Control 4 */ + uint32 PC5; /**< 0x0080: DMM Pin Control 5 */ + uint32 PC6; /**< 0x0084: DMM Pin Control 6 */ + uint32 PC7; /**< 0x0088: DMM Pin Control 7 */ + uint32 PC8; /**< 0x008C: DMM Pin Control 8 */ +} dmmBASE_t; + +/** @def dmmREG + * @brief DMM Register Frame Pointer + * + * This pointer is used by the DMM driver to access the DMM module registers. + */ +#define dmmREG ( ( dmmBASE_t * ) 0xFFFFF700U ) + +/** @def dmmPORT + * @brief DMM Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of DMM + * (use the GIO drivers to access the port pins). + */ +#define dmmPORT ( ( gioPORT_t * ) 0xFFFFF770U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h new file mode 100644 index 00000000000..962bc197e55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h @@ -0,0 +1,155 @@ +/** @file reg_ecap.h + * @brief ECAP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ECAP_H__ +#define __REG_ECAP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Ecap Register Frame Definition */ +/** @struct ecapBASE + * @brief ECAP Register Frame Definition + * + * This type is used to access the ECAP Registers. + */ +/** @typedef ecapBASE_t + * @brief ECAP Register Frame Type Definition + * + * This type is used to access the ECAP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ + +} ecapBASE_t; + +#else + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ + +} ecapBASE_t; + +#endif +/** @def ecapREG1 + * @brief ECAP1 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP1 registers. + */ +#define ecapREG1 ( ( ecapBASE_t * ) 0xFCF79300U ) + +/** @def ecapREG2 + * @brief ECAP2 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP2 registers. + */ +#define ecapREG2 ( ( ecapBASE_t * ) 0xFCF79400U ) + +/** @def ecapREG3 + * @brief ECAP3 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP3 registers. + */ +#define ecapREG3 ( ( ecapBASE_t * ) 0xFCF79500U ) + +/** @def ecapREG4 + * @brief ECAP4 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP4 registers. + */ +#define ecapREG4 ( ( ecapBASE_t * ) 0xFCF79600U ) + +/** @def ecapREG5 + * @brief ECAP5 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP5 registers. + */ +#define ecapREG5 ( ( ecapBASE_t * ) 0xFCF79700U ) + +/** @def ecapREG6 + * @brief ECAP6 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP6 registers. + */ +#define ecapREG6 ( ( ecapBASE_t * ) 0xFCF79800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h new file mode 100644 index 00000000000..f00eb93b75c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h @@ -0,0 +1,94 @@ +/** @file reg_efc.h + * @brief EFC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EFC_H__ +#define __REG_EFC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ +/** @struct efcBase + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ +/** @typedef efcBASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct efcBase +{ + uint32 rsvd1; /* 0x00 RESERVED */ + uint32 rsvd2; /* 0x04 RESERVED */ + uint32 rsvd3; /* 0x08 RESERVED */ + uint32 rsvd4; /* 0x0C RESERVED */ + uint32 rsvd5; /* 0x10 RESERVED */ + uint32 rsvd6; /* 0x14 RESERVED */ + uint32 rsvd7; /* 0x18 RESERVED */ + uint32 BOUND; /* 0x1C RESERVED */ + uint32 rsvd8; /* 0x20 RESERVED */ + uint32 rsvd9; /* 0x24 RESERVED */ + uint32 rsvd10; /* 0x28 RESERVED */ + uint32 PINS; /* 0x2C RESERVED */ + uint32 rsvd11; /* 0x30 RESERVED */ + uint32 rsvd12; /* 0x34 RESERVED */ + uint32 rsvd13; /* 0x38 RESERVED */ + uint32 ERR_STAT; /* 0x3C RESERVED */ + uint32 rsvd14; /* 0x40 RESERVED */ + uint32 rsvd15; /* 0x44 RESERVED */ + uint32 ST_CY; /* 0x48 RESERVED */ + uint32 ST_SIG; /* 0x4C RESERVED */ +} efcBASE_t; + +#define efcREG ( ( efcBASE_t * ) 0xFFF8C000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h new file mode 100644 index 00000000000..513ff89e67b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h @@ -0,0 +1,97 @@ +/** @file reg_emif.h + * @brief EMIF Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EMIF driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EMIF_H__ +#define __REG_EMIF_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Emif Register Frame Definition */ +/** @struct emifBASE_t + * @brief emifBASE Register Definition + * + * This structure is used to access the EMIF module registers. + */ +typedef volatile struct emifBase +{ + uint32 MIDR; /**< 0x0000 Module ID Register */ + uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/ + uint32 SDCR; /**< 0x0008 SDRAM configuration register */ + uint32 SDRCR; /**< 0x000C Set Interrupt Enable Register */ + uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */ + uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */ + uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */ + uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */ + uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */ + uint32 dummy1[ 6 ]; /** reserved **/ + uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */ + uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/ + uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */ + uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */ + uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */ + uint32 dummy2[ 6 ]; /** reserved **/ + uint32 PMCR; /**< 0x0068 Page Mode Control Register*/ + +} emifBASE_t; + +#define emifREG ( ( emifBASE_t * ) 0xFCFFE800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h new file mode 100644 index 00000000000..6c2612b51a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h @@ -0,0 +1,97 @@ +/** @file reg_epc.h + * @brief EPC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the EPC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EPC_H__ +#define __REG_EPC_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* EPC Register Frame Definition */ +/** @struct epcBase + * @brief EPC Base Register Definition + * + * This structure is used to access the EPC module registers. + */ +/** @typedef epcBASE_t + * @brief EPC Register Frame Type Definition + * + * This type is used to access the EPC Registers. + */ +typedef volatile struct epcBase +{ + uint32 EPCREVID; /**< 0x0000: EPC REVID Register */ + uint32 EPCCNTRL; /**< 0x0004: EPC Control Register */ + uint32 UERRSTAT; /**< 0x0008: Uncorrectable Error Status Register */ + uint32 EPCERRSTAT; /**< 0x000C: EPC Error Status Register */ + uint32 FIFOFULLSTAT; /**< 0x0010: FIFO Full Status Register */ + uint32 OVRFLWSTAT; /**< 0x0014: IP Interface FIFO Overflow Status Register */ + uint32 CAMAVAILSTAT; /**< 0x0018: CAM Index Available Status Register */ + uint32 rsvd1; /**< 0x001C: Reserved */ + uint32 UERRADDR[ 2 ]; /**< 0x0020 - 0x0024: Uncorrectable Error Address Registers */ + uint32 rsvd2[ 30 ]; /**< 0x0028 - 0x009C: Reserved */ + uint32 CAM_CONTENT[ 32 ]; /**< 0x00A0 - 0x011C: CAM Content Update Registers */ + uint32 rsvd3[ 56 ]; /**< 0x0120 - 0x01FC: Reserved */ + uint32 CAM_INDEX[ 8 ]; /**< 0x0200 - 0x021C: CAM Index Register 0 to 7 */ +} epcBASE_t; + +#define epcREG1 ( ( epcBASE_t * ) 0xFFFF0C00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h new file mode 100644 index 00000000000..26c50fe56f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h @@ -0,0 +1,148 @@ +/** @file reg_eqep.h + * @brief EQEP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EQEP_H__ +#define __REG_EQEP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Eqep Register Frame Definition */ +/** @struct eqepBASE + * @brief EQEP Register Frame Definition + * + * This type is used to access the EQEP Registers. + */ +/** @typedef eqepBASE_t + * @brief EQEP Register Frame Type Definition + * + * This type is used to access the EQEP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ +} eqepBASE_t; + +#else + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ +} eqepBASE_t; + +#endif + +/** @def eqepREG1 + * @brief eQEP1 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP1 registers. + */ +#define eqepREG1 ( ( eqepBASE_t * ) 0xFCF79900U ) + +/** @def eqepREG2 + * @brief eQEP2 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP2 registers. + */ +#define eqepREG2 ( ( eqepBASE_t * ) 0xFCF79A00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h new file mode 100644 index 00000000000..d5bef12ecd2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h @@ -0,0 +1,110 @@ +/** @file reg_esm.h + * @brief ESM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ESM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ESM_H__ +#define __REG_ESM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Esm Register Frame Definition */ +/** @struct esmBase + * @brief Esm Register Frame Definition + * + * This type is used to access the Esm Registers. + */ +/** @typedef esmBASE_t + * @brief Esm Register Frame Type Definition + * + * This type is used to access the Esm Registers. + */ +typedef volatile struct esmBase +{ + uint32 EEPAPR1; /* 0x0000 */ + uint32 DEPAPR1; /* 0x0004 */ + uint32 IESR1; /* 0x0008 */ + uint32 IECR1; /* 0x000C */ + uint32 ILSR1; /* 0x0010 */ + uint32 ILCR1; /* 0x0014 */ + uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */ + uint32 EPSR; /* 0x0024 */ + uint32 IOFFHR; /* 0x0028 */ + uint32 IOFFLR; /* 0x002C */ + uint32 LTCR; /* 0x0030 */ + uint32 LTCPR; /* 0x0034 */ + uint32 EKR; /* 0x0038 */ + uint32 SSR2; /* 0x003C */ + uint32 IEPSR4; /* 0x0040 */ + uint32 IEPCR4; /* 0x0044 */ + uint32 IESR4; /* 0x0048 */ + uint32 IECR4; /* 0x004C */ + uint32 ILSR4; /* 0x0050 */ + uint32 ILCR4; /* 0x0054 */ + uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */ + uint32 rsvd1[ 7U ]; /* 0x0064 - 0x007C */ + uint32 IEPSR7; /* 0x0080 */ + uint32 IEPCR7; /* 0x0084 */ + uint32 IESR7; /* 0x0088 */ + uint32 IECR7; /* 0x008C */ + uint32 ILSR7; /* 0x0090 */ + uint32 ILCR7; /* 0x0094 */ + uint32 SR7[ 3U ]; /* 0x0098, 0x009C, 0x00A0 */ +} esmBASE_t; + +/** @def esmREG + * @brief Esm Register Frame Pointer + * + * This pointer is used by the Esm driver to access the Esm registers. + */ +#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h new file mode 100644 index 00000000000..07d6382ab29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h @@ -0,0 +1,219 @@ +/** @file reg_etpwm.h + * @brief ETPWM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ETPWM_H__ +#define __REG_ETPWM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ETPWM Register Frame Definition */ +/** @struct etpwmBASE + * @brief ETPWM Register Frame Definition + * + * This type is used to access the ETPWM Registers. + */ +/** @typedef etpwmBASE_t + * @brief ETPWM Register Frame Type Definition + * + * This type is used to access the ETPWM Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct etpwmBASE +{ + uint16 TBCTL; /**< 0x0000 Time-Base Control Register*/ + uint16 TBSTS; /**< 0x0002 Time-Base Status Register*/ + uint16 rsvd1; /**< 0x0004 Reserved*/ + uint16 TBPHS; /**< 0x0006 Time-Base Phase Register*/ + uint16 TBCTR; /**< 0x0008 Time-Base Counter Register*/ + uint16 TBPRD; /**< 0x000A Time-Base Period Register*/ + uint16 rsvd2; /**< 0x000C Reserved*/ + uint16 CMPCTL; /**< 0x000E Counter-Compare Control Register*/ + uint16 rsvd3; /**< 0x0010 Reserved*/ + uint16 CMPA; /**< 0x0012 Counter-Compare A Register*/ + uint16 CMPB; /**< 0x0014 Counter-Compare B Register*/ + uint16 AQCTLA; /**< 0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 AQCTLB; /**< 0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 AQSFRC; /**< 0x001A Action-Qualifier Software Force Register*/ + uint16 AQCSFRC; /**< 0x001C Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBCTL; /**< 0x001E Dead-Band Generator Control Register*/ + uint16 DBRED; /**< 0x0020 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 DBFED; /**< 0x0022 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 TZSEL; /**< 0x0024 Trip-Zone Select Register*/ + uint16 TZDCSEL; /**< 0x0026 Trip Zone Digital Compare Select Register*/ + uint16 TZCTL; /**< 0x0028 Trip-Zone Control Register*/ + uint16 TZEINT; /**< 0x002A Trip-Zone Enable Interrupt Register*/ + uint16 TZFLG; /**< 0x002C Trip-Zone Flag Register*/ + uint16 TZCLR; /**< 0x002E Trip-Zone Clear Register*/ + uint16 TZFRC; /**< 0x0030 Trip-Zone Force Register*/ + uint16 ETSEL; /**< 0x0032 Event-Trigger Selection Register*/ + uint16 ETPS; /**< 0x0034 Event-Trigger Pre-Scale Register*/ + uint16 ETFLG; /**< 0x0036 Event-Trigger Flag Register*/ + uint16 ETCLR; /**< 0x0038 Event-Trigger Clear Register*/ + uint16 ETFRC; /**< 0x003A Event-Trigger Force Register*/ + uint16 PCCTL; /**< 0x003C PWM-Chopper Control Register*/ + uint16 rsvd4; /**< 0x003E Reserved*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCTRIPSEL; /**< 0x0060 Digital Compare Trip Select Register*/ + uint16 DCACTL; /**< 0x0062 Digital Compare A Control Register*/ + uint16 DCBCTL; /**< 0x0064 Digital Compare B Control Register*/ + uint16 DCFCTL; /**< 0x0066 Digital Compare Filter Control Register*/ + uint16 DCCAPCTL; /**< 0x0068 Digital Compare Capture Control Register*/ + uint16 DCFOFFSET; /**< 0x006A Digital Compare Filter Offset Register*/ + uint16 DCFOFFSETCNT; /**< 0x006C Digital Compare Filter Offset Counter Register*/ + uint16 DCFWINDOW; /**< 0x006E Digital Compare Filter Window Register*/ + uint16 DCFWINDOWCNT; /**< 0x0070 Digital Compare Filter Window Counter Register*/ + uint16 DCCAP; /**< 0x0072 Digital Compare Counter Capture Register*/ +} etpwmBASE_t; + +#else + +typedef volatile struct etpwmBASE +{ + uint16 TBSTS; /**< 0x0000 Time-Base Status Register*/ + uint16 TBCTL; /**< 0x0002 Time-Base Control Register*/ + uint16 TBPHS; /**< 0x0004 Time-Base Phase Register*/ + uint16 rsvd1; /**< 0x0006 Reserved*/ + uint16 TBPRD; /**< 0x0008 Time-Base Period Register*/ + uint16 TBCTR; /**< 0x000A Time-Base Counter Register*/ + uint16 CMPCTL; /**< 0x000C Counter-Compare Control Register*/ + uint16 rsvd2; /**< 0x000E Reserved*/ + uint16 CMPA; /**< 0x0010 Counter-Compare A Register*/ + uint16 rsvd3; /**< 0x0012 Reserved*/ + uint16 AQCTLA; /**< 0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 CMPB; /**< 0x0016 Counter-Compare B Register*/ + uint16 AQSFRC; /**< 0x0018 Action-Qualifier Software Force Register*/ + uint16 AQCTLB; /**< 0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 DBCTL; /**< 0x001C Dead-Band Generator Control Register*/ + uint16 AQCSFRC; /**< 0x001E Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBFED; /**< 0x0020 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 DBRED; /**< 0x0022 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 TZDCSEL; /**< 0x0024 Trip Zone Digital Compare Select Register*/ + uint16 TZSEL; /**< 0x0026 Trip-Zone Select Register*/ + uint16 TZEINT; /**< 0x0028 Trip-Zone Enable Interrupt Register*/ + uint16 TZCTL; /**< 0x002A Trip-Zone Control Register*/ + uint16 TZCLR; /**< 0x002C Trip-Zone Clear Register*/ + uint16 TZFLG; /**< 0x002E Trip-Zone Flag Register*/ + uint16 ETSEL; /**< 0x0030 Event-Trigger Selection Register*/ + uint16 TZFRC; /**< 0x0032 Trip-Zone Force Register*/ + uint16 ETFLG; /**< 0x0034 Event-Trigger Flag Register*/ + uint16 ETPS; /**< 0x0036 Event-Trigger Pre-Scale Register*/ + uint16 ETFRC; /**< 0x0038 Event-Trigger Force Register*/ + uint16 ETCLR; /**< 0x003A Event-Trigger Clear Register*/ + uint16 rsvd4; /**< 0x003C Reserved*/ + uint16 PCCTL; /**< 0x003E PWM-Chopper Control Register*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCACTL; /**< 0x0060 Digital Compare A Control Register*/ + uint16 DCTRIPSEL; /**< 0x0062 Digital Compare Trip Select Register*/ + uint16 DCFCTL; /**< 0x0064 Digital Compare Filter Control Register*/ + uint16 DCBCTL; /**< 0x0066 Digital Compare B Control Register*/ + uint16 DCFOFFSET; /**< 0x0068 Digital Compare Filter Offset Register*/ + uint16 DCCAPCTL; /**< 0x006A Digital Compare Capture Control Register*/ + uint16 DCFWINDOW; /**< 0x006C Digital Compare Filter Window Register*/ + uint16 DCFOFFSETCNT; /**< 0x006E Digital Compare Filter Offset Counter Register*/ + uint16 DCCAP; /**< 0x0070 Digital Compare Counter Capture Register*/ + uint16 DCFWINDOWCNT; /**< 0x0072 Digital Compare Filter Window Counter Register*/ +} etpwmBASE_t; + +#endif + +/** @def etpwmREG1 + * @brief ETPWM1 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM1 registers. + */ +#define etpwmREG1 ( ( etpwmBASE_t * ) 0xFCF78C00U ) + +/** @def etpwmREG2 + * @brief ETPWM2 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM2 registers. + */ +#define etpwmREG2 ( ( etpwmBASE_t * ) 0xFCF78D00U ) + +/** @def etpwmREG3 + * @brief ETPWM3 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM3 registers. + */ +#define etpwmREG3 ( ( etpwmBASE_t * ) 0xFCF78E00U ) + +/** @def etpwmREG4 + * @brief ETPWM4 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM4 registers. + */ +#define etpwmREG4 ( ( etpwmBASE_t * ) 0xFCF78F00U ) + +/** @def etpwmREG5 + * @brief ETPWM5 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM5 registers. + */ +#define etpwmREG5 ( ( etpwmBASE_t * ) 0xFCF79000U ) + +/** @def etpwmREG6 + * @brief ETPWM6 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM6 registers. + */ +#define etpwmREG6 ( ( etpwmBASE_t * ) 0xFCF79100U ) + +/** @def etpwmREG7 + * @brief ETPWM7 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM7 registers. + */ +#define etpwmREG7 ( ( etpwmBASE_t * ) 0xFCF79200U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h new file mode 100644 index 00000000000..262d45c66d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h @@ -0,0 +1,135 @@ +/** @file reg_flash.h + * @brief Flash Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_FLASH_H__ +#define __REG_FLASH_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Flash Register Frame Definition */ +/** @struct flashWBase + * @brief Flash Wrapper Register Frame Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +/** @typedef flashWBASE_t + * @brief Flash Wrapper Register Frame Type Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +typedef volatile struct flashWBase +{ + uint32 FRDCNTL; /* 0x0000 */ + uint32 rsvd1; /* 0x0004 */ + uint32 EE_FEDACCTRL1; /* 0x0008 */ + uint32 rsvd2; /* 0x000C */ + uint32 rsvd3; /* 0x0010 */ + uint32 FEDAC_PASTATUS; /* 0x0014 */ + uint32 FEDAC_PBSTATUS; /* 0x0018 */ + uint32 FEDAC_GBLSTATUS; /* 0x001C */ + uint32 rsvd4; /* 0x0020 */ + uint32 FEDACSDIS; /* 0x0024 */ + uint32 FPRIM_ADD_TAG; /* 0x0028 */ + uint32 FDUP_ADD_TAG; /* 0x002C */ + uint32 FBPROT; /* 0x0030 */ + uint32 FBSE; /* 0x0034 */ + uint32 FBBUSY; /* 0x0038 */ + uint32 FBAC; /* 0x003C */ + uint32 FBPWRMODE; /* 0x0040 */ + uint32 FBPRDY; /* 0x0044 */ + uint32 FPAC1; /* 0x0048 */ + uint32 rsvd5; /* 0x004C */ + uint32 FMAC; /* 0x0050 */ + uint32 FMSTAT; /* 0x0054 */ + uint32 FEMU_DMSW; /* 0x0058 */ + uint32 FEMU_DLSW; /* 0x005C */ + uint32 FEMU_ECC; /* 0x0060 */ + uint32 FLOCK; /* 0x0064 */ + uint32 rsvd6; /* 0x0068 */ + uint32 FDIAGCTRL; /* 0x006C */ + uint32 rsvd7; /* 0x0070 */ + uint32 FRAW_ADDR; /* 0x0074 */ + uint32 rsvd8; /* 0x0078 */ + uint32 FPAR_OVR; /* 0x007C */ + uint32 rsvd9[ 13U ]; /* 0x0080 - 0x00B0 */ + uint32 RCR_VALID; /* 0x00B4 */ + uint32 ACC_THRESHOLD; /* 0x00B8 */ + uint32 rsvd10; /* 0x00BC */ + uint32 FEDACSDIS2; /* 0x00C0 */ + uint32 rsvd11; /* 0x00C4 */ + uint32 rsvd12; /* 0x00C8 */ + uint32 rsvd13; /* 0x00CC */ + uint32 RCR_VALUE0; /* 0x00D0 */ + uint32 RCR_VALUE1; /* 0x00D4 */ + uint32 rsvd14[ 108U ]; /* 0x00D8 - 0x00284 */ + uint32 FSM_WR_ENA; /* 0x0288 */ + uint32 rsvd15[ 11U ]; /* 0x028C - 0x002B4 */ + uint32 EEPROM_CONFIG; /* 0x02B8 */ + uint32 rsvd16; /* 0x02BC */ + uint32 FSM_SECTOR1; /* 0x02C0 */ + uint32 FSM_SECTOR2; /* 0x02C4 */ + uint32 rsvd17[ 78U ]; /* 0x02A8 */ + uint32 FCFG_BANK; /* 0x02B8 */ + +} flashWBASE_t; + +/** @def flashWREG + * @brief Flash Wrapper Register Frame Pointer + * + * This pointer is used by the system driver to access the flash wrapper registers. + */ +#define flashWREG ( ( flashWBASE_t * ) ( 0xFFF87000U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h new file mode 100644 index 00000000000..694b0f4665a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h @@ -0,0 +1,128 @@ +/** @file reg_gio.h + * @brief GIO Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the GIO driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_GIO_H__ +#define __REG_GIO_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Gio Register Frame Definition */ +/** @struct gioBase + * @brief GIO Base Register Definition + * + * This structure is used to access the GIO module registers. + */ +/** @typedef gioBASE_t + * @brief GIO Register Frame Type Definition + * + * This type is used to access the GIO Registers. + */ +typedef volatile struct gioBase +{ + uint32 GCR0; /**< 0x0000: Global Control Register */ + uint32 rsvd; /**< 0x0004: Reserved*/ + uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/ + uint32 POL; /**< 0x000C: Interrupt Polarity Register */ + uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */ + uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */ + uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */ + uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */ + uint32 FLG; /**< 0x0020: Interrupt Flag Register */ + uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */ + uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */ + uint32 EMU1; /**< 0x002C: Emulation 1 Register */ + uint32 EMU2; /**< 0x0030: Emulation 2 Register */ +} gioBASE_t; + +/** @struct gioPort + * @brief GIO Port Register Definition + */ +/** @typedef gioPORT_t + * @brief GIO Port Register Type Definition + * + * This type is used to access the GIO Port Registers. + */ +typedef volatile struct gioPort +{ + uint32 DIR; /**< 0x0000: Data Direction Register */ + uint32 DIN; /**< 0x0004: Data Input Register */ + uint32 DOUT; /**< 0x0008: Data Output Register */ + uint32 DSET; /**< 0x000C: Data Output Set Register */ + uint32 DCLR; /**< 0x0010: Data Output Clear Register */ + uint32 PDR; /**< 0x0014: Open Drain Register */ + uint32 PULDIS; /**< 0x0018: Pullup Disable Register */ + uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */ +} gioPORT_t; + +/** @def gioREG + * @brief GIO Register Frame Pointer + * + * This pointer is used by the GIO driver to access the gio module registers. + */ +#define gioREG ( ( gioBASE_t * ) 0xFFF7BC00U ) + +/** @def gioPORTA + * @brief GIO Port (A) Register Pointer + * + * Pointer used by the GIO driver to access PORTA + */ +#define gioPORTA ( ( gioPORT_t * ) 0xFFF7BC34U ) + +/** @def gioPORTB + * @brief GIO Port (B) Register Pointer + * + * Pointer used by the GIO driver to access PORTB + */ +#define gioPORTB ( ( gioPORT_t * ) 0xFFF7BC54U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h new file mode 100644 index 00000000000..c5de03309e5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h @@ -0,0 +1,187 @@ +/** @file reg_het.h + * @brief HET Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HET driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HET_H__ +#define __REG_HET_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Het Register Frame Definition */ +/** @struct hetBase + * @brief HET Base Register Definition + * + * This structure is used to access the HET module registers. + */ +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +typedef volatile struct hetBase +{ + uint32 GCR; /**< 0x0000: Global control register */ + uint32 PFR; /**< 0x0004: Prescale factor register */ + uint32 ADDR; /**< 0x0008: Current address register */ + uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */ + uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */ + uint32 INTENAS; /**< 0x0014: Interrupt enable set register */ + uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */ + uint32 EXC1; /**< 0x001C: Exception control register 1 */ + uint32 EXC2; /**< 0x0020: Exception control register 2 */ + uint32 PRY; /**< 0x0024: Interrupt priority register */ + uint32 FLG; /**< 0x0028: Interrupt flag register */ + uint32 AND; /**< 0x002C: AND share control register */ + uint32 rsvd1; /**< 0x0030: Reserved */ + uint32 HRSH; /**< 0x0034: High resolution share register */ + uint32 XOR; /**< 0x0038: XOR share register */ + uint32 REQENS; /**< 0x003C: Request enable set register */ + uint32 REQENC; /**< 0x0040: Request enable clear register */ + uint32 REQDS; /**< 0x0044: Request destination select register */ + uint32 rsvd2; /**< 0x0048: Reserved */ + uint32 DIR; /**< 0x004C: Direction register */ + uint32 DIN; /**< 0x0050: Data input register */ + uint32 DOUT; /**< 0x0054: Data output register */ + uint32 DSET; /**< 0x0058: Data output set register */ + uint32 DCLR; /**< 0x005C: Data output clear register */ + uint32 PDR; /**< 0x0060: Open drain register */ + uint32 PULDIS; /**< 0x0064: Pull disable register */ + uint32 PSL; /**< 0x0068: Pull select register */ + uint32 rsvd3; /**< 0x006C: Reserved */ + uint32 rsvd4; /**< 0x0070: Reserved */ + uint32 PCR; /**< 0x0074: Parity control register */ + uint32 PAR; /**< 0x0078: Parity address register */ + uint32 PPR; /**< 0x007C: Parity pin select register */ + uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */ + uint32 SFENA; /**< 0x0084: Suppression filter enable register */ + uint32 rsvd5; /**< 0x0088: Reserved */ + uint32 LBPSEL; /**< 0x008C: Loop back pair select register */ + uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */ + uint32 PINDIS; /**< 0x0094: Pin disable register */ +} hetBASE_t; + +/** @struct hetInstructionBase + * @brief HET Instruction Definition + * + * This structure is used to access the HET RAM. + */ +/** @typedef hetINSTRUCTION_t + * @brief HET Instruction Type Definition + * + * This type is used to access a HET Instruction. + */ +typedef volatile struct hetInstructionBase +{ + uint32 Program; + uint32 Control; + uint32 Data; + uint32 rsvd1; +} hetINSTRUCTION_t; + +/** @struct hetRamBase + * @brief HET RAM Definition + * + * This structure is used to access the HET RAM. + */ +/** @typedef hetRAMBASE_t + * @brief HET RAM Type Definition + * + * This type is used to access the HET RAM. + */ +typedef volatile struct het1RamBase +{ + hetINSTRUCTION_t Instruction[ 160U ]; +} hetRAMBASE_t; + +/** @def hetREG1 + * @brief HET Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG1 ( ( hetBASE_t * ) 0xFFF7B800U ) + +/** @def hetPORT1 + * @brief HET GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET1 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT1 ( ( gioPORT_t * ) 0xFFF7B84CU ) + +/** @def hetREG2 + * @brief HET2 Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG2 ( ( hetBASE_t * ) 0xFFF7B900U ) + +/** @def hetPORT2 + * @brief HET2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET2 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT2 ( ( gioPORT_t * ) 0xFFF7B94CU ) + +#define hetRAM1 ( ( hetRAMBASE_t * ) 0xFF460000U ) + +#define hetRAM2 ( ( hetRAMBASE_t * ) 0xFF440000U ) + +#define NHET1RAMPARLOC ( *( volatile uint32 * ) 0xFF462000U ) +#define NHET1RAMLOC ( *( volatile uint32 * ) 0xFF460000U ) + +#define NHET2RAMPARLOC ( *( volatile uint32 * ) 0xFF442000U ) +#define NHET2RAMLOC ( *( volatile uint32 * ) 0xFF440000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h new file mode 100644 index 00000000000..d5760454f50 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h @@ -0,0 +1,130 @@ +/** @file reg_htu.h + * @brief HTU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HTU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HTU_H__ +#define __REG_HTU_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* htu Register Frame Definition */ +/** @struct htuBase + * @brief HTU Base Register Definition + * + * This structure is used to access the HTU module registers. + */ +/** @typedef htuBASE_t + * @brief HTU Register Frame Type Definition + * + * This type is used to access the HTU Registers. + */ +typedef volatile struct htuBase +{ + uint32 GC; /** 0x00 */ + uint32 CPENA; /** 0x04 */ + uint32 BUSY0; /** 0x08 */ + uint32 BUSY1; /** 0x0C */ + uint32 BUSY2; /** 0x10 */ + uint32 BUSY3; /** 0x14 */ + uint32 ACPE; /** 0x18 */ + uint32 rsvd1; /** 0x1C */ + uint32 RLBECTRL; /** 0x20 */ + uint32 BFINTS; /** 0x24 */ + uint32 BFINTC; /** 0x28 */ + uint32 INTMAP; /** 0x2C */ + uint32 rsvd2; /** 0x30 */ + uint32 INTOFF0; /** 0x34 */ + uint32 INTOFF1; /** 0x38 */ + uint32 BIM; /** 0x3C */ + uint32 RLOSTFL; /** 0x40 */ + uint32 BFINTFL; /** 0x44 */ + uint32 BERINTFL; /** 0x48 */ + uint32 MP1S; /** 0x4C */ + uint32 MP1E; /** 0x50 */ + uint32 DCTRL; /** 0x54 */ + uint32 WPR; /** 0x58 */ + uint32 WMR; /** 0x5C */ + uint32 ID; /** 0x60 */ + uint32 PCR; /** 0x64 */ + uint32 PAR; /** 0x68 */ + uint32 rsvd3; /** 0x6C */ + uint32 MPCS; /** 0x70 */ + uint32 MP0S; /** 0x74 */ + uint32 MP0E; /** 0x78 */ +} htuBASE_t; + +typedef volatile struct htudcp +{ + uint32 IFADDRA; + uint32 IFADDRB; + uint32 IHADDRCT; + uint32 ITCOUNT; +} htudcp_t; + +typedef volatile struct htucdcp +{ + uint32 CFADDRA; + uint32 CFADDRB; + uint32 CFCOUNT; + uint32 rsvd4; +} htucdcp_t; + +#define htuREG1 ( ( htuBASE_t * ) 0xFFF7A400U ) +#define htuREG2 ( ( htuBASE_t * ) 0xFFF7A500U ) + +#define htuDCP1 ( ( htudcp_t * ) 0xFF4E0000U ) +#define htuDCP2 ( ( htudcp_t * ) 0xFF4C0000U ) + +#define htuCDCP1 ( ( htucdcp_t * ) 0xFF4E0100U ) +#define htuCDCP2 ( ( htucdcp_t * ) 0xFF4C0100U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h new file mode 100644 index 00000000000..57331088e93 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h @@ -0,0 +1,136 @@ +/** @file reg_i2c.h + * @brief I2C Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the I2C driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* I2c Register Frame Definition */ +/** @struct i2cBase + * @brief I2C Base Register Definition + * + * This structure is used to access the I2C module registers. + */ +/** @typedef i2cBASE_t + * @brief I2C Register Frame Type Definition + * + * This type is used to access the I2C Registers. + */ +typedef volatile struct i2cBase +{ + uint32 OAR; /**< 0x0000 I2C Own Address register */ + uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */ + uint32 STR; /**< 0x0008 I2C Interrupt Status register */ + uint32 CKL; /**< 0x000C I2C Clock Divider Low register */ + uint32 CKH; /**< 0x0010 I2C Clock Divider High register */ + uint32 CNT; /**< 0x0014 I2C Data Count register */ + uint32 DRR; /**< 0x0018: I2C Data Receive register, */ + uint32 SAR; /**< 0x001C I2C Slave Address register */ + uint32 DXR; /**< 0x0020: I2C Data Transmit register, */ + uint32 MDR; /**< 0x0024 I2C Mode register */ + uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */ + uint32 EMDR; /**< 0x002C I2C Extended Mode register */ + uint32 PSC; /**< 0x0030 I2C Prescaler register */ + uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */ + uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */ + uint32 DMACR; /**< 0x003C I2C DMA Control Register */ + uint32 rsvd7; /**< 0x0040 Reserved */ + uint32 rsvd8; /**< 0x0044 Reserved */ + uint32 PFNC; /**< 0x0048 Pin Function Register */ + uint32 DIR; /**< 0x004C Pin Direction Register */ + uint32 DIN; /**< 0x0050 Pin Data In Register */ + uint32 DOUT; /**< 0x0054 Pin Data Out Register */ + uint32 SET; /**< 0x0058 Pin Data Set Register */ + uint32 CLR; /**< 0x005C Pin Data Clr Register */ + uint32 PDR; /**< 0x0060 Pin Open Drain Output Enable Register */ + uint32 PDIS; /**< 0x0064 Pin Pullup/Pulldown Disable Register */ + uint32 PSEL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */ + uint32 PSRS; /**< 0x006C Pin Slew Rate Select Register */ +} i2cBASE_t; + +/** @def i2cREG1 + * @brief I2C Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C module registers. + */ +#define i2cREG1 ( ( i2cBASE_t * ) 0xFFF7D400U ) + +/** @def i2cREG2 + * @brief I2C2 Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C2 module registers. + */ +#define i2cREG2 ( ( i2cBASE_t * ) 0xFFF7D500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @def i2cPORT1 + * @brief I2C1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C1 + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT1 ( ( gioPORT_t * ) 0xFFF7D44CU ) + +/** @def i2cPORT2 + * @brief I2C2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C2 + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT2 ( ( gioPORT_t * ) 0xFFF7D54CU ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h new file mode 100644 index 00000000000..61966cc2d03 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h @@ -0,0 +1,93 @@ +/** @file reg_l2ramw.h + * @brief L2RAMW Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_L2RAMW_H__ +#define __REG_L2RAMW_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* L2ram Register Frame Definition */ +/** @struct l2ramwBase + * @brief L2RAMW Wrapper Register Frame Definition + * + * This type is used to access the L2RAMW Wrapper Registers. + */ +/** @typedef l2ramwBASE_t + * @brief L2RAMW Wrapper Register Frame Type Definition + * + * This type is used to access the L2RAMW Wrapper Registers. + */ + +typedef volatile struct l2ramwBase +{ + uint32 RAMCTRL; /* 0x0000 */ + uint32 rsvd1[ 3 ]; /* 0x0004 */ + uint32 RAMERRSTATUS; /* 0x0010 */ + uint32 rsvd2[ 4 ]; /* 0x0014 */ + uint32 DIAGDATAVECTOR_H; /* 0x0024 */ + uint32 DIAGDATAVECTOR_L; /* 0x0028 */ + uint32 DIAG_ECC; /* 0x002C */ + uint32 RAMTEST; /* 0x0030 */ + uint32 rsvd3; /* 0x0034 */ + uint32 RAMADDRDECVECT; /* 0x0038 */ + uint32 MEMINITDOMAIN; /* 0x003C */ + uint32 rsvd4; /* 0x0040 */ + uint32 BANKDOMAINMAP0; /* 0x0044 */ + uint32 BANKDOMAINMAP1; /* 0x0048 */ +} l2ramwBASE_t; + +#define l2ramwREG ( ( l2ramwBASE_t * ) ( 0xFFFFF900U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h new file mode 100644 index 00000000000..31681e21ef8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h @@ -0,0 +1,138 @@ +/** @file reg_lin.h + * @brief LIN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the LIN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_LIN_H__ +#define __REG_LIN_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Lin Register Frame Definition */ +/** @struct linBase + * @brief LIN Base Register Definition + * + * This structure is used to access the LIN module registers. + */ +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +typedef volatile struct linBase +{ + uint32 GCR0; /**< 0x0000: Global control register 0 */ + uint32 GCR1; /**< 0x0004: Global control register 1 */ + uint32 GCR2; /**< 0x0008: Global control register 2 */ + uint32 SETINT; /**< 0x000C: Set interrupt enable register */ + uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */ + uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */ + uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */ + uint32 FLR; /**< 0x001C: interrupt flag register */ + uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */ + uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */ + uint32 FORMAT; /**< 0x0028: Format Control Register */ + uint32 BRS; /**< 0x002C: Baud rate selection register */ + uint32 ED; /**< 0x0030: Emulation register */ + uint32 RD; /**< 0x0034: Receive data register */ + uint32 TD; /**< 0x0038: Transmit data register */ + uint32 PIO0; /**< 0x003C: Pin function register */ + uint32 PIO1; /**< 0x0040: Pin direction register */ + uint32 PIO2; /**< 0x0044: Pin data in register */ + uint32 PIO3; /**< 0x0048: Pin data out register */ + uint32 PIO4; /**< 0x004C: Pin data set register */ + uint32 PIO5; /**< 0x0050: Pin data clr register */ + uint32 PIO6; /**< 0x0054: Pin open drain output enable register */ + uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */ + uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */ + uint32 COMP; /**< 0x0060: Compare register */ + uint8 RDx[ 8U ]; /**< 0x0064-0x0068: RX buffer register */ + uint32 MASK; /**< 0x006C: Mask register */ + uint32 ID; /**< 0x0070: Identification Register */ + uint8 TDx[ 8U ]; /**< 0x0074-0x0078: TX buffer register */ + uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */ + uint32 rsvd1[ 4U ]; /**< 0x0080 - 0x8C: Reserved */ + uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */ +} linBASE_t; + +/** @def linREG1 + * @brief LIN1 Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin1 module registers. + */ +#define linREG1 ( ( linBASE_t * ) 0xFFF7E400U ) + +/** @def linPORT1 + * @brief LIN1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN1 + * (use the GIO drivers to access the port pins). + */ +#define linPORT1 ( ( gioPORT_t * ) 0xFFF7E440U ) + +/** @def linREG2 + * @brief LIN2 Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin2 module registers. + */ +#define linREG2 ( ( linBASE_t * ) 0xFFF7E600U ) + +/** @def linPORT2 + * @brief LIN2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN2 + * (use the GIO drivers to access the port pins). + */ +#define linPORT2 ( ( gioPORT_t * ) 0xFFF7E640U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h new file mode 100644 index 00000000000..bb175ba4d0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h @@ -0,0 +1,311 @@ +/** @file reg_mibspi.h + * @brief MIBSPI Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the MIBSPI driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_MIBSPI_H__ +#define __REG_MIBSPI_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Mibspi Register Frame Definition */ +/** @struct mibspiBase + * @brief MIBSPI Register Definition + * + * This structure is used to access the MIBSPI module registers. + */ +/** @typedef mibspiBASE_t + * @brief MIBSPI Register Frame Type Definition + * + * This type is used to access the MIBSPI Registers. + */ +typedef volatile struct mibspiBase +{ + uint32 GCR0; /**< 0x0000: Global Control 0 */ + uint32 GCR1; /**< 0x0004: Global Control 1 */ + uint32 INT0; /**< 0x0008: Interrupt Register */ + uint32 LVL; /**< 0x000C: Interrupt Level */ + uint32 FLG; /**< 0x0010: Interrupt flags */ + uint32 PC0; /**< 0x0014: Function Pin Enable */ + uint32 PC1; /**< 0x0018: Pin Direction */ + uint32 PC2; /**< 0x001C: Pin Input Latch */ + uint32 PC3; /**< 0x0020: Pin Output Latch */ + uint32 PC4; /**< 0x0024: Output Pin Set */ + uint32 PC5; /**< 0x0028: Output Pin Clr */ + uint32 PC6; /**< 0x002C: Open Drain Output Enable */ + uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */ + uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */ + uint32 DAT0; /**< 0x0038: Transmit Data */ + uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ + uint32 BUF; /**< 0x0040: Receive Buffer */ + uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ + uint32 DELAY; /**< 0x0048: Delays */ + uint32 DEF; /**< 0x004C: Default Chip Select */ + uint32 FMT0; /**< 0x0050: Data Format 0 */ + uint32 FMT1; /**< 0x0054: Data Format 1 */ + uint32 FMT2; /**< 0x0058: Data Format 2 */ + uint32 FMT3; /**< 0x005C: Data Format 3 */ + uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ + uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ + uint32 rsvd3; /**< 0x0068: Slew Rate Select */ + uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */ + uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */ + uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */ + uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */ + uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */ + uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */ + uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */ + uint32 rsvd1[ 2U ]; /**< 0x0088: Reserved */ + uint32 TICKCNT; /**< 0x0090: Tick Counter */ + uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */ + uint32 TGCTRL[ 16U ]; /**< 0x0098 - 0x00D4: Transfer Group Control */ + uint32 DMACTRL[ 8U ]; /**< 0x00D8 - 0x00F4: DMA Control */ + uint32 DMACOUNT[ 8U ]; /**< 0x00F8 - 0x0114: DMA Count */ + uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */ + uint32 rsvd2; /**< 0x011C: Reserved */ + uint32 PAR_ECC_CTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control + */ + uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */ + uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */ + uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */ + uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */ + uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ + uint32 EXT_PRESCALE1; /**< 0x0138: SPI Extended Prescale Register 1*/ + uint32 EXT_PRESCALE2; /**< 0x013C: SPI Extended Prescale Register 2*/ + uint32 ECCDIAG_CTRL; /**< 0x0140: ECC Diagnostic Control register*/ + uint32 ECCDIAG_STAT; /**< 0x0144: ECC Diagnostic Status register*/ + uint32 SBERRADDR1; /**< 0x0148: */ + uint8 rsvd4[ 6 ]; /**< 0x014C-0x152: Single Bit Error Address Register - RXRAM*/ + uint32 SBERRADDR0; /**< 0x0152: Single Bit Error Address Register - TXRAM*/ + +} mibspiBASE_t; + +/** @def mibspiREG1 + * @brief MIBSPI1 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG1 ( ( mibspiBASE_t * ) 0xFFF7F400U ) + +/** @def mibspiPORT1 + * @brief MIBSPI1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI1 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U ) + +/** @def mibspiREG2 + * @brief MIBSPI2 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG2 ( ( mibspiBASE_t * ) 0xFFF7F600U ) + +/** @def mibspiPORT2 + * @brief MIBSPI2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI2 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT2 ( ( gioPORT_t * ) 0xFFF7F618U ) + +/** @def mibspiREG3 + * @brief MIBSPI3 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG3 ( ( mibspiBASE_t * ) 0xFFF7F800U ) + +/** @def mibspiPORT3 + * @brief MIBSPI3 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI3 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U ) + +/** @def mibspiREG4 + * @brief MIBSPI4 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG4 ( ( mibspiBASE_t * ) 0xFFF7FA00U ) + +/** @def mibspiPORT4 + * @brief MIBSPI4 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI4 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT4 ( ( gioPORT_t * ) 0xFFF7FA18U ) + +/** @def mibspiREG5 + * @brief MIBSPI5 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG5 ( ( mibspiBASE_t * ) 0xFFF7FC00U ) + +/** @def mibspiPORT5 + * @brief MIBSPI5 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI5 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U ) + +/** @struct mibspiRamBase + * @brief MIBSPI Buffer RAM Definition + * + * This structure is used to access the MIBSPI buffer memory. + */ +/** @typedef mibspiRAM_t + * @brief MIBSPI RAM Type Definition + * + * This type is used to access the MIBSPI RAM. + */ +typedef volatile struct mibspiRamBase +{ + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< tx buffer data */ + uint16 control; /**< tx buffer control */ +#else + uint16 control; /**< tx buffer control */ + uint16 data; /**< tx buffer data */ +#endif + } tx[ 128 ]; + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< rx buffer data */ + uint16 flags; /**< rx buffer flags */ +#else + uint16 flags; /**< rx buffer flags */ + uint16 data; /**< rx buffer data */ +#endif + } rx[ 128 ]; +} mibspiRAM_t; + +/** @def mibspiRAM1 + * @brief MIBSPI1 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM1 ( ( mibspiRAM_t * ) 0xFF0E0000U ) + +/** @def mibspiRAM2 + * @brief MIBSPI2 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM2 ( ( mibspiRAM_t * ) 0xFF080000U ) + +/** @def mibspiRAM3 + * @brief MIBSPI3 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM3 ( ( mibspiRAM_t * ) 0xFF0C0000U ) + +/** @def mibspiRAM4 + * @brief MIBSPI4 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM4 ( ( mibspiRAM_t * ) 0xFF060000U ) + +/** @def mibspiRAM5 + * @brief MIBSPI5 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM5 ( ( mibspiRAM_t * ) 0xFF0A0000U ) + +/** @def mibspiPARRAM1 + * @brief MIBSPI1 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM1 ( *( volatile uint32 * ) ( 0xFF0E0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM2 + * @brief MIBSPI2 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM2 ( *( volatile uint32 * ) ( 0xFF080000U + 0x00000400U ) ) + +/** @def mibspiPARRAM3 + * @brief MIBSPI3 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM3 ( *( volatile uint32 * ) ( 0xFF0C0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM4 + * @brief MIBSPI4 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM4 ( *( volatile uint32 * ) ( 0xFF060000U + 0x00000400U ) ) + +/** @def mibspiPARRAM5 + * @brief MIBSPI5 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM5 ( *( volatile uint32 * ) ( 0xFF0A0000U + 0x00000400U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h new file mode 100644 index 00000000000..6566787f24a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h @@ -0,0 +1,98 @@ +/** @file reg_nmpu.h + * @brief NMPU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_NMPU_H__ +#define __REG_NMPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* NMPU Register Frame Definition */ +/** @struct nmpuBASE_t + * @brief nmpuBASE Register Definition + * + * This structure is used to access the NMPU module registers. + */ +typedef volatile struct nmpuBase +{ + uint32 MPUREV; /**< 0x0000 MPU Revision ID Register */ + uint32 MPULOCK; /**< 0x0004 MPU Lock Register */ + uint32 MPUDIAGCTRL; /**< 0x0008 MPU Diagnostics Control Register */ + uint32 MPUDIAGADDR; /**< 0x000C MPU Diagnostic Address Register */ + uint32 MPUERRSTAT; /**< 0x0010 MPU Error Status Register */ + uint32 MPUERRADDR; /**< 0x0014 MPU Error Address Register */ + uint32 MPUIAM; /**< 0x0018 MPU Input Address Mask Register */ + uint32 rsvd1; /**< 0x001C Reserved */ + uint32 MPUCTRL1; /**< 0x0020 MPU Control Register 1 */ + uint32 MPUCTRL2; /**< 0x0024 MPU Control Register 2 */ + uint32 rsvd2; /**< 0x0028 Reserved */ + uint32 MPUTYPE; /**< 0x002C MPU Type Register */ + uint32 MPUREGBASE; /**< 0x0030 MPU Region Base Address Register */ + uint32 MPUREGSENA; /**< 0x0034 MPU Region Size and Enable Register */ + uint32 MPUREGACR; /**< 0x0038 MPU Region Access Control Register */ + uint32 MPUREGNUM; /**< 0x003C MPU Region Number Register */ +} nmpuBASE_t; + +#define nmpu_emacREG ( ( nmpuBASE_t * ) 0xFCFF1800U ) +#define nmpu_dmaREG ( ( nmpuBASE_t * ) 0xFFFF1A00U ) +#define nmpu_ps_scr_sREG ( ( nmpuBASE_t * ) 0xFFFF1800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h new file mode 100644 index 00000000000..d60aa405008 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h @@ -0,0 +1,96 @@ +/** @file reg_pbist.h + * @brief PBIST Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PBIST_H__ +#define __REG_PBIST_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* PBIST Register Frame Definition */ +/** @struct pbistBase + * @brief PBIST Base Register Definition + * + * This structure is used to access the PBIST module registers. + */ +/** @typedef pbistBASE_t + * @brief PBIST Register Frame Type Definition + * + * This type is used to access the PBIST Registers. + */ +typedef volatile struct pbistBase +{ + uint32 RAMT; /* 0x0160: RAM Configuration Register */ + uint32 DLR; /* 0x0164: Datalogger Register */ + uint32 rsvd1[ 6U ]; /* 0x0168 */ + uint32 PACT; /* 0x0180: PBIST Activate Register */ + uint32 PBISTID; /* 0x0184: PBIST ID Register */ + uint32 OVER; /* 0x0188: Override Register */ + uint32 rsvd2; /* 0x018C */ + uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */ + uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */ + uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */ + uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */ + uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */ + uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */ + uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */ + uint32 rsvd3; /* 0x01AC */ + uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */ + uint32 rsvd4[ 3U ]; /* 0x01B4 */ + uint32 ROM; /* 0x01C0: ROM Mask Register */ + uint32 ALGO; /* 0x01C4: Algorithm Mask Register */ + uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */ + uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */ +} pbistBASE_t; + +#define pbistREG ( ( pbistBASE_t * ) 0xFFFFE560U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h new file mode 100644 index 00000000000..c7454be31f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h @@ -0,0 +1,149 @@ +/** @file reg_pcr.h + * @brief PCR Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PCR_H__ +#define __REG_PCR_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Pcr Register Frame Definition */ +/** @struct pcrBase + * @brief Pcr Register Frame Definition + * + * This type is used to access the Pcr Registers. + */ +/** @typedef pcrBASE_t + * @brief PCR Register Frame Type Definition + * + * This type is used to access the PCR Registers. + */ +typedef volatile struct pcrBase +{ + uint32 PMPROTSET0; /* 0x0000 */ + uint32 PMPROTSET1; /* 0x0004 */ + uint32 rsvd1[ 2U ]; /* 0x0008 */ + uint32 PMPROTCLR0; /* 0x0010 */ + uint32 PMPROTCLR1; /* 0x0014 */ + uint32 rsvd2[ 2U ]; /* 0x0018 */ + uint32 PPROTSET0; /* 0x0020 */ + uint32 PPROTSET1; /* 0x0024 */ + uint32 PPROTSET2; /* 0x0028 */ + uint32 PPROTSET3; /* 0x002C */ + uint32 rsvd3[ 4U ]; /* 0x0030 */ + uint32 PPROTCLR0; /* 0x0040 */ + uint32 PPROTCLR1; /* 0x0044 */ + uint32 PPROTCLR2; /* 0x0048 */ + uint32 PPROTCLR3; /* 0x004C */ + uint32 rsvd4[ 4U ]; /* 0x0050 */ + uint32 PCSPWRDWNSET0; /* 0x0060 */ + uint32 PCSPWRDWNSET1; /* 0x0064 */ + uint32 rsvd5[ 2U ]; /* 0x0068 */ + uint32 PCSPWRDWNCLR0; /* 0x0070 */ + uint32 PCSPWRDWNCLR1; /* 0x0074 */ + uint32 rsvd6[ 2U ]; /* 0x0078 */ + uint32 PSPWRDWNSET0; /* 0x0080 */ + uint32 PSPWRDWNSET1; /* 0x0084 */ + uint32 PSPWRDWNSET2; /* 0x0088 */ + uint32 PSPWRDWNSET3; /* 0x008C */ + uint32 rsvd7[ 4U ]; /* 0x0090 */ + uint32 PSPWRDWNCLR0; /* 0x00A0 */ + uint32 PSPWRDWNCLR1; /* 0x00A4 */ + uint32 PSPWRDWNCLR2; /* 0x00A8 */ + uint32 PSPWRDWNCLR3; /* 0x00AC */ + uint32 rsvd8[ 4U ]; /* 0x00B0 */ + uint32 PDPWRDWNSET; /* 0x00C0 */ + uint32 PDPWRDWNCLR; /* 0x00C4 */ + uint32 rsvd9[ 78U ]; /* 0x00C8 */ + uint32 MSTIDWRENA; /* 0x0200 */ + uint32 MSTIDENA; /* 0x0204 */ + uint32 MSTIDDIAGCTRL; /* 0x0208 */ + uint32 rsvd10[ 61U ]; /* 0x020C */ + struct + { + uint32 PSxMSTID_L; + uint32 PSxMSTID_H; + } PSxMSTID[ 32 ]; /* 0x0300 */ + struct + { + uint32 PPSxMSTID_L; + uint32 PPSxMSTID_H; + } PPSxMSTID[ 8 ]; /* 0x0400 */ + struct + { + uint32 PPSExMSTID_L; + uint32 PPSExMSTID_H; + } PPSExMSTID[ 32 ]; /* 0x0440 */ + uint32 PCSxMSTID[ 32 ]; /* 0x0540 */ + uint32 PPCSxMSTID[ 8 ]; /* 0x05C0 */ +} pcrBASE_t; + +/** @def pcrREG1 + * @brief Pcr1 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr1 registers. + */ +#define pcrREG1 ( ( pcrBASE_t * ) 0xFFFF1000U ) + +/** @def pcrREG2 + * @brief Pcr2 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr2 registers. + */ +#define pcrREG2 ( ( pcrBASE_t * ) 0xFCFF1000U ) + +/** @def pcrREG3 + * @brief Pcr3 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr3 registers. + */ +#define pcrREG3 ( ( pcrBASE_t * ) 0xFFF78000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h new file mode 100644 index 00000000000..e26018aa2ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h @@ -0,0 +1,101 @@ +/** @file reg_pinmux.h + * @brief PINMUX Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PINMUX driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PINMUX_H__ +#define __REG_PINMUX_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @struct pinMuxBase + * @brief PINMUX Register Definition + * + * This structure is used to access the PINMUX module registers. + */ +/** @typedef pinMuxBASE_t + * @brief PINMUX Register Frame Type Definition + * + * This type is used to access the PINMUX Registers. + */ +typedef volatile struct pinMuxBase +{ + uint32 REVISION_REG; /**< 0x00: Revision Register */ + uint32 rsvd1[ 7 ]; /** address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [11]: + * - 0: Read + * - 1: Write + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetDataFault_( void ); + +/** @fn void _coreClearDataFault_(void) + * @brief Clear core data fault status register + */ +void _coreClearDataFault_( void ); + +/** @fn uint32 _coreGetInstructionFault_(void) + * @brief Get core instruction fault status register + * @return The function will return the instruction fault status register value: + * - bit [10,3..0]: + * - 0b00001: Alignment -> address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetInstructionFault_( void ); + +/** @fn void _coreClearInstructionFault_(void) + * @brief Clear core instruction fault status register + */ +void _coreClearInstructionFault_( void ); + +/** @fn uint32 _coreGetDataFaultAddress_(void) + * @brief Get core data fault address register + * @return The function will return the data fault address: + */ +uint32 _coreGetDataFaultAddress_( void ); + +/** @fn void _coreClearDataFaultAddress_(void) + * @brief Clear core data fault address register + */ +void _coreClearDataFaultAddress_( void ); + +/** @fn uint32 _coreGetInstructionFaultAddress_(void) + * @brief Get core instruction fault address register + * @return The function will return the instruction fault address: + */ +uint32 _coreGetInstructionFaultAddress_( void ); + +/** @fn void _coreClearInstructionFaultAddress_(void) + * @brief Clear core instruction fault address register + */ +void _coreClearInstructionFaultAddress_( void ); + +/** @fn uint32 _coreGetAuxiliaryDataFault_(void) + * @brief Get core auxiliary data fault status register + * @return The function will return the auxiliary data fault status register value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryDataFault_( void ); + +/** @fn void _coreClearAuxiliaryDataFault_(void) + * @brief Clear core auxiliary data fault status register + */ +void _coreClearAuxiliaryDataFault_( void ); + +/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void) + * @brief Get core auxiliary instruction fault status register + * @return The function will return the auxiliary instruction fault status register + * value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryInstructionFault_( void ); + +/** @fn void _coreClearAuxiliaryInstructionFault_(void) + * @brief Clear core auxiliary instruction fault status register + */ +void _coreClearAuxiliaryInstructionFault_( void ); + +/** @fn void _disable_IRQ_interrupt_(void) + * @brief Disable IRQ Interrupt mode in CPSR register + * + * This function disables IRQ Interrupt mode in CPSR register. + */ +void _disable_IRQ_interrupt_( void ); + +/** @fn void _enable_IRQ_interrupt_(void) + * @brief Enable IRQ Interrupt mode in CPSR register + * + * This function enables IRQ Interrupt mode in CPSR register. + */ +void _enable_IRQ_interrupt_( void ); + +/** @fn void _enable_interrupt_(void) + * @brief Enable IRQ and FIQ Interrupt mode in CPSR register + * + * This function Enables IRQ and FIQ Interrupt mode in CPSR register. + * User must call this function to enable Interrupts in non-OS environments. + */ +void _enable_interrupt_( void ); + +/** @fn void _esmCcmErrorsClear_(void) + * @brief Clears ESM Error caused due to CCM Errata in RevA Silicon + * + * This function Clears ESM Error caused due to CCM Errata + * in RevA Silicon immediately after powerup. + */ +void _esmCcmErrorsClear_( void ); + +/** @fn void _memInit_(void) + * @brief Initialize RAM + */ +void _memInit_( void ); + +/** @fn void _cacheEnable_(void) + * @brief Initialize RAM + */ +void _cacheEnable_( void ); + +/** @fn void _cacheDisable_(void) + * @brief Enable Cache + */ +void _cacheDisable_( void ); + +/** @fn void _dCacheInvalidate_(void) + * @brief Invalidate DCache. + */ +void _dCacheInvalidate_( void ); + +/** @fn void _iCacheInvalidate_(void) + * @brief Invalidate ICache. + */ +void _iCacheInvalidate_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h new file mode 100644 index 00000000000..79e5348c18e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h @@ -0,0 +1,300 @@ +/** @file sys_dma.h + * @brief DMA Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef DMA_H_ +#define DMA_H_ + +#include "reg_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef enum dmaChannel +{ + DMA_CH0 = 0U, + DMA_CH1, + DMA_CH2, + DMA_CH3, + DMA_CH4, + DMA_CH5, + DMA_CH6, + DMA_CH7, + DMA_CH8, + DMA_CH9, + DMA_CH10, + DMA_CH11, + DMA_CH12, + DMA_CH13, + DMA_CH14, + DMA_CH15, + DMA_CH16, + DMA_CH17, + DMA_CH18, + DMA_CH19, + DMA_CH20, + DMA_CH21, + DMA_CH22, + DMA_CH23, + DMA_CH24, + DMA_CH25, + DMA_CH26, + DMA_CH27, + DMA_CH28, + DMA_CH29, + DMA_CH30, + DMA_CH31 +} dmaChannel_t; + +typedef enum dmaRequest +{ + DMA_REQ0 = 0U, + DMA_REQ1, + DMA_REQ2, + DMA_REQ3, + DMA_REQ4, + DMA_REQ5, + DMA_REQ6, + DMA_REQ7, + DMA_REQ8, + DMA_REQ9, + DMA_REQ10, + DMA_REQ11, + DMA_REQ12, + DMA_REQ13, + DMA_REQ14, + DMA_REQ15, + DMA_REQ16, + DMA_REQ17, + DMA_REQ18, + DMA_REQ19, + DMA_REQ20, + DMA_REQ21, + DMA_REQ22, + DMA_REQ23, + DMA_REQ24, + DMA_REQ25, + DMA_REQ26, + DMA_REQ27, + DMA_REQ28, + DMA_REQ29, + DMA_REQ30, + DMA_REQ31, + DMA_REQ32, + DMA_REQ33, + DMA_REQ34, + DMA_REQ35, + DMA_REQ36, + DMA_REQ37, + DMA_REQ38, + DMA_REQ39, + DMA_REQ40, + DMA_REQ41, + DMA_REQ42, + DMA_REQ43, + DMA_REQ44, + DMA_REQ45, + DMA_REQ46, + DMA_REQ47 +} dmaRequest_t; + +typedef enum dmaTriggerType +{ + DMA_HW, + DMA_SW +} dmaTriggerType_t; + +typedef enum dmaPriorityQueue +{ + LOWPRIORITY, + HIGHPRIORITY +} dmaPriorityQueue_t; + +typedef enum dmaInterrupt +{ + FTC, /**< Frame transfer complete Interrupt */ + LFS, /**< Last frame transfer started Interrupt */ + HBC, /**< First half of block complete Interrupt */ + BTC /**< Block transfer complete Interrupt */ +} dmaInterrupt_t; + +typedef enum dmaIntGroup +{ + DMA_INTA = 0U, /**< Group A Interrupt */ + DMA_INTB = 1U /**< Group B Interrupt (Reserved for Lock-step devices) */ +} dmaIntGroup_t; + +typedef enum dmaMPURegion +{ + DMA_REGION0 = 0U, + DMA_REGION1 = 1U, + DMA_REGION2 = 2U, + DMA_REGION3 = 3U, + DMA_REGION4 = 4U, + DMA_REGION5 = 5U, + DMA_REGION6 = 6U, + DMA_REGION7 = 7U +} dmaMPURegion_t; + +typedef enum dmaRegionAccess +{ + FULLACCESS = 0U, + READONLY = 1U, + WRITEONLY = 2U, + NOACCESS = 3U +} dmaRegionAccess_t; + +typedef enum dmaMPUInt +{ + INTERRUPT_DISABLE = 0U, + INTERRUPTA_ENABLE = 1U, + INTERRUPTB_ENABLE = 3U +} dmaMPUInt_t; + +enum dmaPort +{ + PORTB_READ_PORTB_WRITE = 0x3U, + PORTA_READ_PORTA_WRITE = 0x2U, + PORTA_READ_PORTB_WRITE = 0x1U, + PORTB_READ_PORTA_WRITE = 0x0U +}; + +enum dmaElementSize +{ + ACCESS_8_BIT = 0U, + ACCESS_16_BIT = 1U, + ACCESS_32_BIT = 2U, + ACCESS_64_BIT = 3U +}; + +enum dmaTransferType +{ + FRAME_TRANSFER = 0U, + BLOCK_TRANSFER = 1U +}; + +enum dmaAddressMode +{ + ADDR_FIXED = 0U, + ADDR_INC1 = 1U, + ADDR_OFFSET = 3U +}; + +enum dmaAutoInitMode +{ + AUTOINIT_OFF = 0U, + AUTOINIT_ON = 1U +}; + +typedef struct dmaCTRLPKT +{ + uint32 SADD; /* Initial source address */ + uint32 DADD; /* Initial destination address */ + uint32 CHCTRL; /* Next channel to be triggered + 1 */ + uint32 FRCNT; /* Frame count */ + uint32 ELCNT; /* Element count */ + uint32 ELDOFFSET; /* Element destination offset */ + uint32 ELSOFFSET; /* Element source offset */ + uint32 FRDOFFSET; /* Frame destination offset */ + uint32 FRSOFFSET; /* Frame source offset */ + uint32 PORTASGN; /* DMA port */ + uint32 RDSIZE; /* Read element size */ + uint32 WRSIZE; /* Write element size */ + uint32 TTYPE; /* Trigger type - frame/block */ + uint32 ADDMODERD; /* Addressing mode for source */ + uint32 ADDMODEWR; /* Addressing mode for destination */ + uint32 AUTOINIT; /* Auto-init mode */ +} g_dmaCTRL; + +void dmaEnable( void ); +void dmaDisable( void ); +void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT ); +void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type ); +void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline ); +void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority ); +void dmaEnableInterrupt( dmaChannel_t channel, + dmaInterrupt_t inttype, + dmaIntGroup_t group ); +void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype ); +void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add ); +void dmaEnableRegion( dmaMPURegion_t region, + dmaRegionAccess_t access, + dmaMPUInt_t intenable ); +void dmaDisableRegion( dmaMPURegion_t region ); +void dmaEnableECC( void ); +void dmaDisableECC( void ); + +uint32 dmaGetReq( dmaChannel_t channel ); +boolean dmaIsBusy( void ); +boolean dmaIsChannelActive( dmaChannel_t channel ); +boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype ); + +/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) + * @brief Interrupt callback + * @param[in] inttype Interrupt type + * - FTC + * - LFS + * - HBC + * - BTC + * @param[in] channel channel number 0..15 + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* DMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h new file mode 100644 index 00000000000..312c6265444 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h @@ -0,0 +1,612 @@ +/** @file sys_mpu.h + * @brief System Mpu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Mpu Interface Functions + * . + * which are relevant for the memory protection unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_MPU_H__ +#define __SYS_MPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def mpuREGION1 + * @brief Mpu region 1 + * + * Alias for Mpu region 1 + */ +#define mpuREGION1 0U + +/** @def mpuREGION2 + * @brief Mpu region 2 + * + * Alias for Mpu region 1 + */ +#define mpuREGION2 1U + +/** @def mpuREGION3 + * @brief Mpu region 3 + * + * Alias for Mpu region 3 + */ +#define mpuREGION3 2U + +/** @def mpuREGION4 + * @brief Mpu region 4 + * + * Alias for Mpu region 4 + */ +#define mpuREGION4 3U + +/** @def mpuREGION5 + * @brief Mpu region 5 + * + * Alias for Mpu region 5 + */ +#define mpuREGION5 4U + +/** @def mpuREGION6 + * @brief Mpu region 6 + * + * Alias for Mpu region 6 + */ +#define mpuREGION6 5U + +/** @def mpuREGION7 + * @brief Mpu region 7 + * + * Alias for Mpu region 7 + */ +#define mpuREGION7 6U + +/** @def mpuREGION8 + * @brief Mpu region 8 + * + * Alias for Mpu region 8 + */ +#define mpuREGION8 7U + +/** @def mpuREGION9 + * @brief Mpu region 9 + * + * Alias for Mpu region 9 + */ +#define mpuREGION9 8U + +/** @def mpuREGION10 + * @brief Mpu region 10 + * + * Alias for Mpu region 10 + */ +#define mpuREGION10 9U + +/** @def mpuREGION11 + * @brief Mpu region 11 + * + * Alias for Mpu region 11 + */ +#define mpuREGION11 10U + +/** @def mpuREGION12 + * @brief Mpu region 12 + * + * Alias for Mpu region 12 + */ +#define mpuREGION12 11U + +/** @def mpuREGION13 + * @brief Mpu region 13 + * + * Alias for Mpu region 13 + */ +#define mpuREGION13 12U + +/** @def mpuREGION14 + * @brief Mpu region 14 + * + * Alias for Mpu region 14 + */ +#define mpuREGION14 13U + +/** @def mpuREGION15 + * @brief Mpu region 15 + * + * Alias for Mpu region 15 + */ +#define mpuREGION15 14U + +/** @def mpuREGION16 + * @brief Mpu region 16 + * + * Alias for Mpu region 16 + */ +#define mpuREGION16 15U + +/** @def mpuREGION_ENABLE + * @brief Enable MPU Region + * + * Alias for MPU region enable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_ENABLE 1U + +/** @def mpuREGION_DISABLE + * @brief Disable MPU Region + * + * Alias for MPU region disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_DISABLE 0U + +/** @def mpuSUBREGION0_DISABLE + * @brief Disable MPU Sub Region0 + * + * Alias for MPU subregion0 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION0_DISABLE 0x100U + +/** @def mpuSUBREGION1_DISABLE + * @brief Disable MPU Sub Region1 + * + * Alias for MPU subregion1 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION1_DISABLE 0x200U + +/** @def mpuSUBREGION2_DISABLE + * @brief Disable MPU Sub Region2 + * + * Alias for MPU subregion2 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION2_DISABLE 0x400U + +/** @def mpuSUBREGION3_DISABLE + * @brief Disable MPU Sub Region3 + * + * Alias for MPU subregion3 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION3_DISABLE 0x800U + +/** @def mpuSUBREGION4_DISABLE + * @brief Disable MPU Sub Region4 + * + * Alias for MPU subregion4 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION4_DISABLE 0x1000U + +/** @def mpuSUBREGION5_DISABLE + * @brief Disable MPU Sub Region5 + * + * Alias for MPU subregion5 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION5_DISABLE 0x2000U + +/** @def mpuSUBREGION6_DISABLE + * @brief Disable MPU Sub Region6 + * + * Alias for MPU subregion6 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION6_DISABLE 0x4000U + +/** @def mpuSUBREGION7_DISABLE + * @brief Disable MPU Sub Region7 + * + * Alias for MPU subregion7 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION7_DISABLE 0x8000U + +/** @enum mpuRegionAccessPermission + * @brief Alias names for mpu region access permissions + * + * This enumeration is used to provide alias names for the mpu region access permission: + * - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode + * and execute + * - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode + * and execute + * - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode + * and execute + * - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and + * execute + * - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode + * and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode + * and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode + * and no execution + * + */ +enum mpuRegionAccessPermission +{ + MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access + in user mode and execute */ + MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias no read/write in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias no read/write in privileged mode, read + only in user mode and execute */ + MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias no read/write in privileged mode, + read/write in user mode and execute */ + MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias no read only in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias no read only in privileged mode, read + only in user mode and execute */ + MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, + read only in user mode and no execution */ + MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, + read/write in user mode and no execution */ + MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias no read only in privileged mode, read + only in user mode and no execution */ +}; + +/** @enum mpuRegionType + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_DEVICE_SHAREABLE Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, + * no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, + * no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no + * write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no + * write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cacheable + * and non shared + * - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cacheable + * and shared + * - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, + * write allocate and non shared + * - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, + * write allocate and shared + * - MPU_DEVICE_NONSHAREABLE Memory type device and non sharable + */ +enum mpuRegionType +{ + MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and + sharable */ + MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */ + MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner + write-through, no write allocate and non + shared */ + MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner + write-back, no write allocate and non + shared */ + MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner + write-through, no write allocate and shared + */ + MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner + write-back, no write allocate and shared */ + MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner + non-cacheable and non shared */ + MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner + write-back, write allocate and non shared */ + MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner + non-cacheable and shared */ + MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner + write-back, write allocate and shared */ + MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */ +}; + +/** @enum mpuRegionSize + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_32_BYTES Memory size in bytes + * - MPU_64_BYTES Memory size in bytes + * - MPU_128_BYTES Memory size in bytes + * - MPU_256_BYTES Memory size in bytes + * - MPU_512_BYTES Memory size in bytes + * - MPU_1_KB Memory size in kB + * - MPU_2_KB Memory size in kB + * - MPU_4_KB Memory size in kB + * - MPU_8_KB Memory size in kB + * - MPU_16_KB Memory size in kB + * - MPU_32_KB Memory size in kB + * - MPU_64_KB Memory size in kB + * - MPU_128_KB Memory size in kB + * - MPU_256_KB Memory size in kB + * - MPU_512_KB Memory size in kB + * - MPU_1_MB Memory size in MB + * - MPU_2_MB Memory size in MB + * - MPU_4_MB Memory size in MB + * - MPU_8_MBv Memory size in MB + * - MPU_16_MB Memory size in MB + * - MPU_32_MB Memory size in MB + * - MPU_64_MB Memory size in MB + * - MPU_128_MB Memory size in MB + * - MPU_256_MB Memory size in MB + * - MPU_512_MB Memory size in MB + * - MPU_1_GB Memory size in GB + * - MPU_2_GB Memory size in GB + * - MPU_4_GB Memory size in GB + */ +enum mpuRegionSize +{ + MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */ + MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */ + MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */ + MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */ + MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */ + MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */ + MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */ + MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */ + MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */ + MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */ + MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */ + MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */ + MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */ + MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */ + MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */ + MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */ + MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */ + MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */ + MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */ + MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */ + MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */ + MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */ + MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */ + MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */ + MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */ + MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */ + MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */ + MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */ +}; + +/** @fn void _mpuInit_(void) + * @brief Initialize Mpu + * + * This function initializes memory protection unit. + */ +void _mpuInit_( void ); + +/** @fn void _mpuEnable_(void) + * @brief Enable Mpu + * + * This function enables memory protection unit. + */ +void _mpuEnable_( void ); + +/** @fn void _mpuDisable_(void) + * @brief Disable Mpu + * + * This function disables memory protection unit. + */ +void _mpuDisable_( void ); + +/** @fn void _mpuEnableBackgroundRegion_(void) + * @brief Enable Mpu background region + * + * This function enables background region of the memory protection unit. + */ +void _mpuEnableBackgroundRegion_( void ); + +/** @fn void _mpuDisableBackgroundRegion_(void) + * @brief Disable Mpu background region + * + * This function disables background region of the memory protection unit. + */ +void _mpuDisableBackgroundRegion_( void ); + +/** @fn uint32 _mpuGetNumberOfRegions_(void) + * @brief Returns number of implemented Mpu regions + * @return Number of implemented mpu regions + * + * This function returns the number of implemented mpu regions. + */ +uint32 _mpuGetNumberOfRegions_( void ); + +/** @fn uint32 _mpuAreRegionsSeparate_(void) + * @brief Returns the type of the implemented mpu regions + * @return Mpu type of regions + * + * This function returns 0 when mpu regions are of type unified otherwise regions are of + * type separate. + */ +uint32 _mpuAreRegionsSeparate_( void ); + +/** @fn void _mpuSetRegion_(uint32 region) + * @brief Set mpu region number + * @param[in] region Region number: mpuREGION1..mpuREGION12 + * + * This function selects one of the implemented mpu regions. + */ +void _mpuSetRegion_( uint32 region ); + +/** @fn uint32 _mpuGetRegion_(void) + * @brief Returns the currently selected mpu region + * @return Mpu region number + * + * This function returns currently selected mpu region number. + */ +uint32 _mpuGetRegion_( void ); + +/** @fn void _mpuSetRegionBaseAddress_(uint32 address) + * @brief Set base address of currently selected mpu region + * @param[in] address Base address of the MPU region + * @note The base address must always aligned with region size + * + * This function sets the base address of currently selected mpu region. + */ +void _mpuSetRegionBaseAddress_( uint32 address ); + +/** @fn uint32 _mpuGetRegionBaseAddress_(void) + * @brief Returns base address of currently selected mpu region + * @return Current base address of selected mpu region + * + * This function returns the base address of currently selected mpu region. + */ +uint32 _mpuGetRegionBaseAddress_( void ); + +/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission) + * @brief Set type of currently selected mpu region + * @param[in] type Region Type + * - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and + * sharable + * - MPU_DEVICE_SHAREABLE : Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and + * inner write-through, no write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and + * inner write-back, no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and + * inner write-through, no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and + * inner write-back, no write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and + * inner non-cacheable and non shared + * - MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and + * inner write-back, write allocate and non shared + * - MPU_NORMAL_OINC_SHARED : Memory type normal outer and + * inner non-cacheable and shared + * - MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and + * inner write-back, write allocate and shared + * - MPU_DEVICE_NONSHAREABLE : Memory type device and non + * sharable + * + * @param[in] permission Region Access permission + * - MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged + * mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_NA_EXEC : Alias no read/write in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_RO_EXEC : Alias no read/write in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_RW_USER_RW_EXEC : Alias no read/write in + * privileged mode, read/write in user mode and execute + * - MPU_PRIV_RO_USER_NA_EXEC : Alias no read only in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RO_USER_RO_EXEC : Alias no read only in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged + * mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in + * privileged mode, read only in user mode and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in + * privileged mode, read/write in user mode and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in + * privileged mode, read only in user mode and no execution + * + * This function sets the type of currently selected mpu region. + */ +void _mpuSetRegionTypeAndPermission_( uint32 type, uint32 permission ); + +/** @fn uint32 _mpuGetRegionType_(void) + * @brief Returns the type of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns the type of currently selected mpu region. + */ +uint32 _mpuGetRegionType_( void ); + +/** @fn uint32 _mpuGetRegionPermission_(void) + * @brief Returns permission of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns permission of currently selected mpu region. + */ +uint32 _mpuGetRegionPermission_( void ); + +/** @fn void _mpuSetRegionSizeRegister_(uint32 value) + * @brief Set mpu region size register value + * @param[in] value Value to be written in the MPU Region Size and Enable register + * + * This function sets mpu region size register value. + * + * Sample usuage: + * _mpuSetRegion_(mpuREGION5); + * _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE | + * mpuSUBREGION4_DISABLE); + */ +void _mpuSetRegionSizeRegister_( uint32 value ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h new file mode 100644 index 00000000000..b8dc1fb4feb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h @@ -0,0 +1,331 @@ +/** @file pcr.h + * @brief PCR Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PCR driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PCR_H_ +#define PCR_H_ + +#include "reg_pcr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define QUADRANT0 1U +#define QUADRANT1 2U +#define QUADRANT2 4U +#define QUADRANT3 8U + +typedef enum +{ + PS0 = 0U, + PS1, + PS2, + PS3, + PS4, + PS5, + PS6, + PS7, + PS8, + PS9, + PS10, + PS11, + PS12, + PS13, + PS14, + PS15, + PS16, + PS17, + PS18, + PS19, + PS20, + PS21, + PS22, + PS23, + PS24, + PS25, + PS26, + PS27, + PS28, + PS29, + PS30, + PS31 +} peripheral_Frame_t; + +typedef enum +{ + PPS0 = 0U, + PPS1, + PPS2, + PPS3, + PPS4, + PPS5, + PPS6, + PPS7 +} privileged_Peripheral_Frame_t; + +typedef enum +{ + PPSE0 = 0U, + PPSE1, + PPSE2, + PPSE3, + PPSE4, + PPSE5, + PPSE6, + PPSE7, + PPSE8, + PPSE9, + PPSE10, + PPSE11, + PPSE12, + PPSE13, + PPSE14, + PPSE15, + PPSE16, + PPSE17, + PPSE18, + PPSE19, + PPSE20, + PPSE21, + PPSE22, + PPSE23, + PPSE24, + PPSE25, + PPSE26, + PPSE27, + PPSE28, + PPSE29, + PPSE30, + PPSE31 +} privileged_Peripheral_Extended_Frame_t; + +typedef enum +{ + PCS0 = 0U, + PCS1, + PCS2, + PCS3, + PCS4, + PCS5, + PCS6, + PCS7, + PCS8, + PCS9, + PCS10, + PCS11, + PCS12, + PCS13, + PCS14, + PCS15, + PCS16, + PCS17, + PCS18, + PCS19, + PCS20, + PCS21, + PCS22, + PCS23, + PCS24, + PCS25, + PCS26, + PCS27, + PCS28, + PCS29, + PCS30, + PCS31, + PCS32, + PCS33, + PCS34, + PCS35, + PCS36, + PCS37, + PCS38, + PCS39, + PCS40, + PCS41, + PCS42, + PCS43, + PCS44, + PCS45, + PCS46, + PCS47, + PCS48, + PCS49, + PCS50, + PCS51, + PCS52, + PCS53, + PCS54, + PCS55, + PCS56, + PCS57, + PCS58, + PCS59, + PCS60, + PCS61, + PCS62, + PCS63 +} peripheral_Memory_t; + +typedef enum +{ + PPCS0 = 0U, + PPCS1, + PPCS2, + PPCS3, + PPCS4, + PPCS5, + PPCS6, + PPCS7, + PPCS8, + PPCS9, + PPCS10, + PPCS11, + PPCS12, + PPCS13, + PPCS14, + PPCS15 +} privileged_Peripheral_Memory_t; + +typedef enum +{ + Master_CPU0 = 0U, + Master_CPU1 = 1U, /* Reserved for Lock-Step device */ + Master_DMA = 2U, + Master_HTU1 = 3U, + Master_HTU2 = 4U, + Master_FTU = 5U, + Master_DMM = 7U, + Master_DAP = 9U, + Master_EMAC = 10U +} master_ID_t; + +/** + * @defgroup PCR PCR + * @brief PPeripheral Central Resource Module + * + * Related files: + * - reg_pcr.h + * - sys_pcr.h + * - sys_pcr.c + * + * @addtogroup PCR + * @{ + */ + +void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Frame_Protection_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); +void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); + +void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); +void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); + +void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ); +void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ); + +void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ); +void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ); +void privileged_Peripheral_Memory_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ); +void privileged_Peripheral_Memory_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ); + +void pcrEnableMasterIDCheck( pcrBASE_t * pcr ); +void pcrDisableMasterIDCheck( pcrBASE_t * pcr ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* PCR_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h new file mode 100644 index 00000000000..0365d796e13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h @@ -0,0 +1,119 @@ +/** @file sys_pmm.h + * @brief PMM Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMM_H__ +#define __SYS_PMM_H__ + +#include "reg_pmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pmmLogicPDTag + * @brief PMM Logic Power Domain + * + * Used to define PMM Logic Power Domain + */ +typedef enum pmmLogicPDTag +{ + PMM_LOGICPD1 = 5U, /*-- NOT USED*/ + PMM_LOGICPD2 = 0U, + PMM_LOGICPD3 = 1U, + PMM_LOGICPD4 = 2U, + PMM_LOGICPD5 = 3U, + PMM_LOGICPD6 = 4U +} pmm_LogicPD_t; + +/** @enum pmmModeTag + * @brief PSCON operating mode + * + * Used to define the operating mode of PSCON Compare Block + */ +typedef enum pmmModeTag +{ + LockStep = 0x0U, + SelfTest = 0x6U, + ErrorForcing = 0x9U, + SelfTestErrorForcing = 0xFU +} pmm_Mode_t; + +/** + * @defgroup PMM PMM + * @brief Power Management Module + * + * The PMM provides memory-mapped registers that control the states of the supported power + * domains. The PMM includes interfaces to the Power Mode Controller (PMC) and the Power + * State Controller (PSCON). The PMC and PSCON control the power up/down sequence of each + * power domain. + * + * Related files: + * - reg_pmm.h + * - sys_pmm.h + * - sys_pmm.c + * + * @addtogroup PMM + * @{ + */ + +/* Pmm Interface Functions */ +boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ); +boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ); +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h new file mode 100644 index 00000000000..f60d1f47c55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h @@ -0,0 +1,240 @@ +/** @file sys_pmu.h + * @brief System Pmu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Pmu Interface Functions + * . + * which are relevant for the performance monitor unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMU_H__ +#define __SYS_PMU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def pmuCOUNTER0 + * @brief pmu event counter 0 + * + * Alias for pmu event counter 0 + */ +#define pmuCOUNTER0 0x00000001U + +/** @def pmuCOUNTER1 + * @brief pmu event counter 1 + * + * Alias for pmu event counter 1 + */ +#define pmuCOUNTER1 0x00000002U + +/** @def pmuCOUNTER2 + * @brief pmu event counter 2 + * + * Alias for pmu event counter 2 + */ +#define pmuCOUNTER2 0x00000004U + +/** @def pmuCYCLE_COUNTER + * @brief pmu cycle counter + * + * Alias for pmu event counter + */ +#define pmuCYCLE_COUNTER 0x80000000U + +/** @enum pmuEvent + * @brief pmu event + * + * Alias for pmu event counter increment source + */ +enum pmuEvent +{ + PMU_INST_CACHE_MISS = 0x01U, + PMU_DATA_CACHE_MISS = 0x03U, + PMU_DATA_CACHE_ACCESS = 0x04U, + PMU_DATA_READ_ARCH_EXECUTED = 0x06U, + PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U, + PMU_INST_ARCH_EXECUTED = 0x08U, + PMU_EXCEPTION_TAKEN = 0x09U, + PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU, + PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU, + PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU, + PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU, + PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU, + PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU, + PMU_BRANCH_MISSPREDICTED = 0x10U, + PMU_CYCLE_COUNT = 0x11U, + PMU_PREDICTABLE_BRANCHES = 0x12U, + PMU_INST_BUFFER_STALL = 0x40U, + PMU_DATA_DEPENDENCY_INST_STALL = 0x41U, + PMU_DATA_CACHE_WRITE_BACK = 0x42U, + PMU_EXT_MEMORY_REQUEST = 0x43U, + PMU_LSU_BUSY_STALL = 0x44U, + PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U, + PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U, + PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U, + PMU_ETMEXTOUT_0 = 0x48U, + PMU_ETMEXTOUT_1 = 0x49U, + PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU, + PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU, + PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU, + PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU, + PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU, + PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU, + PMU_STORE_BUFFER_MERGE = 0x50U, + PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U, + PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U, + PMU_INTEGER_DIV_EXECUTED = 0x53U, + PMU_STALL_INTEGER_DIV = 0x54U, + PMU_PLD_INST_LINE_FILL = 0x55U, + PMU_PLD_INST_NO_LINE_FILL = 0x56U, + PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U, + PMU_INST_CACHE_ACCESS = 0x58U, + PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U, + PMU_DUAL_ISSUE_CASE_A = 0x5AU, + PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU, + PMU_DUAL_ISSUE_OTHER = 0x5CU, + PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU, + PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU, + PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U, + PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U, + PMU_PROCESSOR_LIVE_LOCK = 0x62U, + PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U, + PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U, + PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U, + PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U, + PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U, + PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U, + PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU, + PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU, + PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU, + PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU, + PMU_ALL_CORRECTABLE_EVENTS = 0x6EU, + PMU_ALL_FATAL_EVENTS = 0x6FU, + PMU_ALL_CORRECTABLE_FAULTS = 0x70U, + PMU_ALL_FATAL_FAULTS = 0x71U, + PMU_ACP_DCACHE_ACCESS_LOOKUP_INVALIDATE = 0x72U, + PMU_ACP_DCACHE_INVALIDATE = 0x73U +}; + +/** @fn void _pmuInit_(void) + * @brief Initialize Performance Monitor Unit + */ +void _pmuInit_( void ); + +/** @fn void _pmuEnableCountersGlobal_(void) + * @brief Enable and reset cycle counter and all 3 event counters + */ +void _pmuEnableCountersGlobal_( void ); + +/** @fn void _pmuDisableCountersGlobal_(void) + * @brief Disable cycle counter and all 3 event counters + */ +void _pmuDisableCountersGlobal_( void ); + +/** @fn void _pmuResetCycleCounter_(void) + * @brief Reset cycle counter + */ +void _pmuResetCycleCounter_( void ); + +/** @fn void _pmuResetEventCounters_(void) + * @brief Reset event counters 0-2 + */ +void _pmuResetEventCounters_( void ); + +/** @fn void _pmuResetCounters_(void) + * @brief Reset cycle counter and event counters 0-2 + */ +void _pmuResetCounters_( void ); + +/** @fn void _pmuStartCounters_(uint32 counters) + * @brief Starts selected counters + * @param[in] counters - Counter mask + */ +void _pmuStartCounters_( uint32 counters ); + +/** @fn void _pmuStopCounters_(uint32 counters) + * @brief Stops selected counters + * @param[in] counters - Counter mask + */ +void _pmuStopCounters_( uint32 counters ); + +/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event) + * @brief Set event counter count event + * @param[in] counter - Counter select 0..2 + * @param[in] event - Count event + */ +void _pmuSetCountEvent_( uint32 counter, uint32 event ); + +/** @fn uint32 _pmuGetCycleCount_(void) + * @brief Returns current cycle counter value + * + * @return cycle count. + */ +uint32 _pmuGetCycleCount_( void ); + +/** @fn uint32 _pmuGetEventCount_(uint32 counter) + * @brief Returns current event counter value + * @param[in] counter - Counter select 0..2 + * + * @return event counter count. + */ +uint32 _pmuGetEventCount_( uint32 counter ); + +/** @fn uint32 _pmuGetOverflow_(void) + * @brief Returns current overflow register and clear flags + * + * @return overflow flags. + */ +uint32 _pmuGetOverflow_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h new file mode 100644 index 00000000000..3d989cf9acb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h @@ -0,0 +1,386 @@ +/** @file sys_vim.h + * @brief Vectored Interrupt Module Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - VIM Type Definitions + * - VIM General Definitions + * . + * which are relevant for Vectored Interrupt Controller. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_VIM_H__ +#define __SYS_VIM_H__ + +#include "reg_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* VIM Type Definitions */ + +/** @typedef t_isrFuncPTR + * @brief ISR Function Pointer Type Definition + * + * This type is used to access the ISR handler. + */ +typedef void ( *t_isrFuncPTR )( void ); + +/** @enum systemInterrupt + * @brief Alias names for clock sources + * + * This enumeration is used to provide alias names for the clock sources: + * - IRQ + * - FIQ + */ +typedef enum systemInterrupt +{ + SYS_IRQ = 0U, /**< Alias for IRQ interrupt */ + SYS_FIQ = 1U /**< Alias for FIQ interrupt */ +} systemInterrupt_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* VIM General Configuration */ + +#define VIM_CHANNELS 128U + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* Interrupt Handlers */ +extern void custom_dabort( void ); +extern void esmHighInterrupt( void ) __attribute__( ( weak, interrupt( "FIQ" ) ) ); +extern void phantomInterrupt( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void FreeRTOS_Tick_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void vPortYieldWithinAPI( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void FreeRTOS_IRQ_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +#define VIM_ECCSTAT ( *( volatile uint32 * ) 0xFFFFFDECU ) +#define VIM_ECCCTL ( *( volatile uint32 * ) 0xFFFFFDF0U ) +#define VIM_UERRADDR ( *( volatile uint32 * ) 0xFFFFFDF4U ) +#define VIM_FBVECADDR ( *( volatile uint32 * ) 0xFFFFFDF8U ) +#define VIM_SBERRADDR ( *( volatile uint32 * ) 0xFFFFFDFCU ) + +#define VIMRAMECCLOC ( *( volatile uint32 * ) 0xFFF82400U ) +#define VIMRAMLOC ( *( volatile uint32 * ) 0xFFF82000U ) + +/* Configuration registers */ +typedef struct vim_config_reg +{ + uint32 CONFIG_FIRQPR0; + uint32 CONFIG_FIRQPR1; + uint32 CONFIG_FIRQPR2; + uint32 CONFIG_FIRQPR3; + uint32 CONFIG_REQMASKSET0; + uint32 CONFIG_REQMASKSET1; + uint32 CONFIG_REQMASKSET2; + uint32 CONFIG_REQMASKSET3; + uint32 CONFIG_WAKEMASKSET0; + uint32 CONFIG_WAKEMASKSET1; + uint32 CONFIG_WAKEMASKSET2; + uint32 CONFIG_WAKEMASKSET3; + uint32 CONFIG_CAPEVT; + uint32 CONFIG_CHANCTRL[ 24U ]; +} vim_config_reg_t; + +/* Configuration registers initial value */ +#define VIM_FIRQPR0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_REQMASKSET0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 1U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_WAKEMASKSET0_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET1_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET2_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET3_CONFIGVALUE 0xFFFFFFFFU +#define VIM_CAPEVT_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +#define VIM_CHANCTRL0_CONFIGVALUE 0x00010203U +#define VIM_CHANCTRL1_CONFIGVALUE 0x04050607U +#define VIM_CHANCTRL2_CONFIGVALUE 0x08090A0BU +#define VIM_CHANCTRL3_CONFIGVALUE 0x0C0D0E0FU +#define VIM_CHANCTRL4_CONFIGVALUE 0x10111213U +#define VIM_CHANCTRL5_CONFIGVALUE 0x14151617U +#define VIM_CHANCTRL6_CONFIGVALUE 0x18191A1BU +#define VIM_CHANCTRL7_CONFIGVALUE 0x1C1D1E1FU +#define VIM_CHANCTRL8_CONFIGVALUE 0x20212223U +#define VIM_CHANCTRL9_CONFIGVALUE 0x24252627U +#define VIM_CHANCTRL10_CONFIGVALUE 0x28292A2BU +#define VIM_CHANCTRL11_CONFIGVALUE 0x2C2D2E2FU +#define VIM_CHANCTRL12_CONFIGVALUE 0x30313233U +#define VIM_CHANCTRL13_CONFIGVALUE 0x34353637U +#define VIM_CHANCTRL14_CONFIGVALUE 0x38393A3BU +#define VIM_CHANCTRL15_CONFIGVALUE 0x3C3D3E3FU +#define VIM_CHANCTRL16_CONFIGVALUE 0x40414243U +#define VIM_CHANCTRL17_CONFIGVALUE 0x44454647U +#define VIM_CHANCTRL18_CONFIGVALUE 0x48494A4BU +#define VIM_CHANCTRL19_CONFIGVALUE 0x4C4D4E4FU +#define VIM_CHANCTRL20_CONFIGVALUE 0x50515253U +#define VIM_CHANCTRL21_CONFIGVALUE 0x54555657U +#define VIM_CHANCTRL22_CONFIGVALUE 0x58595A5BU +#define VIM_CHANCTRL23_CONFIGVALUE 0x5C5D5E5FU + +/** + * @defgroup VIM VIM + * @brief Vectored Interrupt Manager + * + * The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and + * controlling the many interrupt sources present on a device. Interrupts are caused by + * events outside of the normal flow of program execution. + * + * Related files: + * - reg_vim.h + * - sys_vim.h + * - sys_vim.c + * + * @addtogroup VIM + * @{ + */ +/*VIM Interface functions*/ +void vimInit( void ); +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ); +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ); +void vimDisableInterrupt( uint32 channel ); +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ); +/*@}*/ +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h new file mode 100644 index 00000000000..a80f461245f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h @@ -0,0 +1,477 @@ +/** @file system.h + * @brief System Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_SYSTEM_H__ +#define __SYS_SYSTEM_H__ + +#include "reg_system.h" +#include "reg_flash.h" +#include "reg_l2ramw.h" +#include "reg_ccmr5.h" +#include "sys_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* System General Definitions */ + +/** @enum systemClockSource + * @brief Alias names for clock sources + * + * This enumeration is used to provide alias names for the clock sources: + * - Oscillator + * - Pll1 + * - External1 + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - PLL2 + * - External2 + * - Synchronous VCLK1 + */ +enum systemClockSource +{ + SYS_OSC = 0x0U, /**< Alias for oscillator clock Source */ + SYS_PLL1 = 0x1U, /**< Alias for Pll1 clock Source */ + SYS_EXTERNAL1 = 0x3U, /**< Alias for external clock Source */ + SYS_LPO_LOW = 0x4U, /**< Alias for low power oscillator low clock Source */ + SYS_LPO_HIGH = 0x5U, /**< Alias for low power oscillator high clock Source */ + SYS_PLL2 = 0x6U, /**< Alias for Pll2 clock Source */ + SYS_EXTERNAL2 = 0x7U, /**< Alias for external 2 clock Source */ + SYS_VCLK = 0x9U, /**< Alias for synchronous VCLK1 clock Source */ + SYS_PLL2_ODCLK_8 = 0xEU, /**< Alias for PLL2_post_ODCLK/8 */ + SYS_PLL2_ODCLK_16 = 0xFU /**< Alias for PLL2_post_ODCLK/8 */ +}; + +/** @enum resetSource + * @brief Alias names for reset sources + * + * This enumeration is used to provide alias names for the reset sources: + * - Power On Reset + * - Osc Failure Reset + * - Watch Dog Reset + * - Icepick Reset + * - CPU Reset + * - Software Reset + * - External Reset + * + */ +typedef enum +{ + POWERON_RESET = 0x8000U, /**< Alias for Power On Reset */ + OSC_FAILURE_RESET = 0x4000U, /**< Alias for Osc Failure Reset */ + WATCHDOG_RESET = 0x2000U, /**< Alias for Watch Dog Reset */ + WATCHDOG2_RESET = 0x1000U, /**< Alias for Watch Dog 2 Reset */ + DEBUG_RESET = 0x0800U, /**< Alias for Debug Reset */ + INTERCONNECT_RESET = 0x0080U, /**< Alias for Interconnect Reset */ + CPU0_RESET = 0x0020U, /**< Alias for CPU 0 Reset */ + SW_RESET = 0x0010U, /**< Alias for Software Reset */ + EXT_RESET = 0x0008U, /**< Alias for External Reset */ + NO_RESET = 0x0000U /**< Alias for No Reset */ +} resetSource_t; + +#define SYS_DOZE_MODE 0x000F3F02U +#define SYS_SNOOZE_MODE 0x000F3F03U +#define SYS_SLEEP_MODE 0x000FFFFFU +#define LPO_TRIM_VALUE ( ( ( *( volatile uint32 * ) 0xF00801B4U ) & 0xFFFF0000U ) >> 16U ) +#define SYS_EXCEPTION ( *( volatile uint32 * ) 0xFFFFFFE4U ) + +#define WATCHDOG_STATUS ( *( volatile uint32 * ) 0xFFFFFC98U ) +#define DEVICE_ID_REV ( *( volatile uint32 * ) 0xFFFFFFF0U ) + +/** @def OSC_FREQ + * @brief Oscillator clock source exported from HALCoGen GUI + * + * Oscillator clock source exported from HALCoGen GUI + */ +#define OSC_FREQ 16.0F + +/** @def PLL1_FREQ + * @brief PLL 1 clock source exported from HALCoGen GUI + * + * PLL 1 clock source exported from HALCoGen GUI + */ +#define PLL1_FREQ 300.00F + +/** @def LPO_LF_FREQ + * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI + * + * LPO Low Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_LF_FREQ 0.080F + +/** @def LPO_HF_FREQ + * @brief LPO High Freq Oscillator source exported from HALCoGen GUI + * + * LPO High Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_HF_FREQ 10.000F + +/** @def PLL1_FREQ + * @brief PLL 2 clock source exported from HALCoGen GUI + * + * PLL 2 clock source exported from HALCoGen GUI + */ +#define PLL2_FREQ 300.00F + +/** @def GCLK_FREQ + * @brief GCLK domain frequency exported from HALCoGen GUI + * + * GCLK domain frequency exported from HALCoGen GUI + */ +#define GCLK_FREQ 300.000F + +/** @def HCLK_FREQ + * @brief HCLK domain frequency exported from HALCoGen GUI + * + * HCLK domain frequency exported from HALCoGen GUI + */ +#define HCLK_FREQ 150.000F + +/** @def RTI_FREQ + * @brief RTI Clock frequency exported from HALCoGen GUI + * + * RTI Clock frequency exported from HALCoGen GUI + */ +#define RTI_FREQ 75.000F + +/** @def AVCLK1_FREQ + * @brief AVCLK1 Domain frequency exported from HALCoGen GUI + * + * AVCLK Domain frequency exported from HALCoGen GUI + */ +#define AVCLK1_FREQ 75.000F + +/** @def AVCLK2_FREQ + * @brief AVCLK2 Domain frequency exported from HALCoGen GUI + * + * AVCLK2 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK2_FREQ 0.000F + +/** @def AVCLK3_FREQ + * @brief AVCLK3 Domain frequency exported from HALCoGen GUI + * + * AVCLK3 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK3_FREQ 75.000F + +/** @def AVCLK4_FREQ + * @brief AVCLK4 Domain frequency exported from HALCoGen GUI + * + * AVCLK4 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK4_FREQ 75.000F + +/** @def VCLK1_FREQ + * @brief VCLK1 Domain frequency exported from HALCoGen GUI + * + * VCLK1 Domain frequency exported from HALCoGen GUI + */ +#define VCLK1_FREQ 75.000F + +/** @def VCLK2_FREQ + * @brief VCLK2 Domain frequency exported from HALCoGen GUI + * + * VCLK2 Domain frequency exported from HALCoGen GUI + */ +#define VCLK2_FREQ 75.000F + +/** @def VCLK3_FREQ + * @brief VCLK3 Domain frequency exported from HALCoGen GUI + * + * VCLK3 Domain frequency exported from HALCoGen GUI + */ +#define VCLK3_FREQ 75.000F + +/** @def VCLK4_FREQ + * @brief VCLK4 Domain frequency exported from HALCoGen GUI + * + * VCLK4 Domain frequency exported from HALCoGen GUI + */ +#define VCLK4_FREQ 75.0F + +/** @def SYS_PRE1 + * @brief Alias name for RTI1CLK PRE clock source + * + * This is an alias name for the RTI1CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 "Macro filled using GUI parameter cannot be avoided" + */ +#define SYS_PRE1 ( SYS_PLL1 ) + +/** @def SYS_PRE2 + * @brief Alias name for RTI2CLK pre clock source + * + * This is an alias name for the RTI2CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 "Macro filled using GUI parameter cannot be avoided" + */ +#define SYS_PRE2 ( SYS_PLL1 ) + +/* Configuration registers */ +typedef struct system_config_reg +{ + uint32 CONFIG_SYSPC1; + uint32 CONFIG_SYSPC2; + uint32 CONFIG_SYSPC7; + uint32 CONFIG_SYSPC8; + uint32 CONFIG_SYSPC9; + uint32 CONFIG_CSDIS; + uint32 CONFIG_CDDIS; + uint32 CONFIG_GHVSRC; + uint32 CONFIG_VCLKASRC; + uint32 CONFIG_RCLKSRC; + uint32 CONFIG_MSTGCR; + uint32 CONFIG_MINITGCR; + uint32 CONFIG_MSINENA; + uint32 CONFIG_PLLCTL1; + uint32 CONFIG_PLLCTL2; + uint32 CONFIG_SYSPC10; + uint32 CONFIG_LPOMONCTL; + uint32 CONFIG_CLKTEST; + uint32 CONFIG_DFTCTRLREG1; + uint32 CONFIG_DFTCTRLREG2; + uint32 CONFIG_GPREG1; + uint32 CONFIG_RAMGCR; + uint32 CONFIG_BMMCR1; + uint32 CONFIG_CLKCNTL; + uint32 CONFIG_ECPCNTL; + uint32 CONFIG_DEVCR1; + uint32 CONFIG_SYSECR; + uint32 CONFIG_PLLCTL3; + uint32 CONFIG_STCCLKDIV; + uint32 CONFIG_ECPCNTL1; + uint32 CONFIG_CLK2CNTRL; + uint32 CONFIG_VCLKACON1; + uint32 CONFIG_HCLKCNTL; + uint32 CONFIG_CLKSLIP; + uint32 CONFIG_EFC_CTLEN; +} system_config_reg_t; + +/* Configuration registers initial value */ +#define SYS_SYSPC1_CONFIGVALUE 0U + +#define SYS_SYSPC2_CONFIGVALUE 1U + +#define SYS_SYSPC7_CONFIGVALUE 0U + +#define SYS_SYSPC8_CONFIGVALUE 0U + +#define SYS_SYSPC9_CONFIGVALUE 1U + +#define SYS_CSDIS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x4U ) + +#define SYS_CDDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) ) + +#define SYS_GHVSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ) ) + +#define SYS_VCLKASRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_RCLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_MSTGCR_CONFIGVALUE 0x00000105U + +#define SYS_MINITGCR_CONFIGVALUE 0x5U + +#define SYS_MSINENA_CONFIGVALUE 0U + +#define SYS_PLLCTL1_CONFIGVALUE_1 \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) ) + +#define SYS_PLLCTL1_CONFIGVALUE_2 \ + ( ( ( SYS_PLLCTL1_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) + +#define SYS_PLLCTL2_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 255U << 22U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U ) + +#define SYS_SYSPC10_CONFIGVALUE 0U + +#define SYS_LPOMONCTL_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | LPO_TRIM_VALUE ) +#define SYS_LPOMONCTL_CONFIGVALUE_2 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 16U << 8U ) | 16U ) + +#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U + +#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U + +#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U + +#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU + +#define SYS_RAMGCR_CONFIGVALUE 0x00050000U + +#define SYS_BMMCR1_CONFIGVALUE 0xAU + +#define SYS_CLKCNTL_CONFIGVALUE \ + ( 0x00000100U | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define SYS_ECPCNTL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ) ) + +#define SYS_DEVCR1_CONFIGVALUE 0xAU + +#define SYS_SYSECR_CONFIGVALUE 0x00004000U +#define SYS2_PLLCTL3_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) ) + +#define SYS2_PLLCTL3_CONFIGVALUE_2 \ + ( ( ( SYS2_PLLCTL3_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) +#define SYS2_STCCLKDIV_CONFIGVALUE 0U +#define SYS2_ECPCNTL1_CONFIGVALUE 0x50000000U +#define SYS2_CLK2CNTRL_CONFIGVALUE ( 1U | 0x00000100U ) +#define SYS2_HCLKCNTL_CONFIGVALUE 1U +#define SYS2_VCLKACON1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 1U << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) +#define SYS2_CLKSLIP_CONFIGVALUE 0x5U +#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U + +#define L2FLASH_FBPWRMODE_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) | ( uint32 ) ( ( uint32 ) 3U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 10U ) | ( uint32 ) ( ( uint32 ) 3U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 6U ) | ( uint32 ) ( ( uint32 ) 3U << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ) ) +#define L2FLASH_FRDCNTL_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U ) + +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* FlashW General Definitions */ + +/** @enum flashWPowerModes + * @brief Alias names for flash bank power modes + * + * This enumeration is used to provide alias names for the flash bank power modes: + * - sleep + * - standby + * - active + */ +enum flashWPowerModes +{ + SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ + SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ + SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ +}; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define FSM_WR_ENA_HL ( *( volatile uint32 * ) 0xFFF87288U ) +#define EEPROM_CONFIG_HL ( *( volatile uint32 * ) 0xFFF872B8U ) +#define FSM_SECTOR1 ( *( volatile uint32 * ) 0xFFF872C0U ) +#define FSM_SECTOR2 ( *( volatile uint32 * ) 0xFFF872C4U ) +#define FCFG_BANK ( *( volatile uint32 * ) 0xFFF87400U ) + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/* System Interface Functions */ +void setupPLL( void ); +void trimLPO( void ); +void customTrimLPO( void ); +void setupFlash( void ); +void periphInit( void ); +void mapClocks( void ); +void systemInit( void ); +void systemPowerDown( uint32 mode ); +resetSource_t getResetSource( void ); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h new file mode 100644 index 00000000000..d38f913546f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h @@ -0,0 +1,625 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * + ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.01 29Oct2012 Vishwanath Reddy 0000000000000 Changes for + implementing Error Recovery + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + segmentation changes. + * 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested + by Vector. + * 00.01.04 12Feb2012 Vishwanath Reddy SDOCM00099152 Integration issues + fix. + * 00.01.05 04Mar2013 Vishwanath Reddy SDOCM00099152 Added Deleting a + block feature, bug fixes. + * 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : + copying of unconfigured blocks. + * 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : + Number of 8 bytes writes, fixed issue with copy blocks. + * 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature : CRC + check for unconfigured blocks, Main function modified to complete writes as fast as + possible, Added Non polling mode support. + * 00.01.09 19Apr2013 Vishwanath Reddy SDOCM00099152 Warning removal, + Added feature comparision of data during write. + * 00.01.10 11Jun2013 Vishwanath Reddy SDOCM00101845 Updated version + information. + * 00.01.11 05Jul2013 Vishwanath Reddy SDOCM00101643 Updated version + information. + * 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags + added. + * MISRA C fixes. + Version info corrected. + * 01.13.00 30Dec2013 Vishwanath Reddy 0000000000000 Undated version info + for SDOCM00107976 + * and SDOCM00105795. + * 01.13.01 19May2014 Vishwanath Reddy 0000000000000 Updated version info + for SDOCM00107913 + * and SDOCM00107622. + * 01.13.02 12Jun2014 Vishwanath Reddy 0000000000000 Updated version info + for SDOCM00108238 + * 01.14.00 26Mar2014 Vishwanath Reddy Update version info + for SDOCM00107161. + * 01.15.00 06Jun2014 Vishwanath Reddy Support for + Conqueror. + * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA + warnings. + * 01.16.01 12Sep2014 Vishwanath Reddy SDOCM00112930 Prototype for + TI_Fee_SuspendResumeErase added. + * TI_Fee_EraseCommandType enum added. + * extern added for + TI_Fee_bEraseSuspended. + * 01.17.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization + changes. + * 01.17.01 30Oct2014 Vishwanath Reddy SDOCM00113536 Support for + TMS570LS07xx,TMS570LS09xx, + * TMS570LS05xx, RM44Lx. + * 01.17.02 26Dec2014 Vishwanath Reddy SDOCM00114102 FLEE Errata Fix. + * SDOCM00114104 Change ALL 1's OK + check condition. + * Updated version info. + Added new macros. + * SDOCM00114423 Add new enum + TI_Fee_DeviceType. + * Add new variable + TI_Fee_MaxSectors and + * prototype + TI_FeeInternal_PopulateStructures. + * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version + history. + * Update ti_fee_util.c + file for the + * bugfix "If morethan + one data set is config- + * ured, then a valid + block may get invalidated if + * multiple valid blocks + are present in FEE memory. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + history. + * In + TI_FeeInternal_FeeManager, do not change the + * state to IDLE,after + completing the copy operation. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + history. + * Add a call of + TI_FeeInternal_PollFlashStatus() + * before reading data + from FEE bank in + * TI_FeeInternal_UpdateBlockOffsetArray(), + * TI_Fee_WriteAsync(),TI_Fee_WriteSync(), + * TI_Fee_ReadSync(), + TI_Fee_Read() + * 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update patch version + TI_FEE_SW_PATCH_VERSION. + * TI_FEE_FLASH_CRC_ENABLE is renamed to + * TI_FEE_FLASH_CHECKSUM_ENABLE. + * SDOCM00122429 In ti_fee_types.h, + add error when endianess + * is not defined. + * 01.19.00 08Augu2016 Vishwanath Reddy SDOCM00122592 Update patch version + TI_FEE_MINOR_VERSION. + * Code for using + partially ersed sector is now + * removed. + * Bugfix for FEE + reading from unimplemented memory + * space. + * 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update patch version + TI_FEE_MINOR_VERSION. + * Synchronous write API + modified to avoid copy of + * already copied block. + * 01.19.02 25Janu2017 Vishwanath Reddy SDOCM00122832 Update patch version + TI_FEE_MINOR_VERSION. + * Format API modified + to erase all configured VS. + * SDOCM00122833 In API + TI_Fee_ErrorRecovery, added polling for + * flash status before + calling TI_Fee_Init. + * 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Added + TI_Fee_bIsMainFunctionCalled Global Variable. + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_H + #define TI_FEE_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "hal_stdtypes.h" + #include "fee_interface.h" + #include "ti_fee_types.h" + #include "ti_fee_cfg.h" + /********************************************************************************************************************** + * GLOBAL CONSTANT MACROS + *********************************************************************************************************************/ + /* Fee Published Information */ + #define TI_FEE_MAJOR_VERSION 3U + #define TI_FEE_MINOR_VERSION 0U + #define TI_FEE_PATCH_VERSION 2U + #define TI_FEE_SW_MAJOR_VERSION 1U + #define TI_FEE_SW_MINOR_VERSION 19U + #define TI_FEE_SW_PATCH_VERSION 4U + + #define TI_FEE_VIRTUAL_SECTOR_VERSION 1U + + /* Virtual sector states */ + #define ActiveVSHi 0x0000FFFFU + #define ActiveVSLo 0x00000000U + #define CopyVSHi 0xFFFFFFFFU + #define CopyVSLo 0x00000000U + #define EmptyVSHi 0xFFFFFFFFU + #define EmptyVSLo 0x0000FFFFU + #define InvalidVSHi 0xFFFFFFFFU + #define InvalidVSLo 0xFFFFFFFFU + #define ReadyforEraseVSHi 0x00000000U + #define ReadyforEraseVSLo 0x00000000U + + /* Data Block states*/ + #define EmptyBlockHi 0xFFFFFFFFU + #define EmptyBlockLo 0xFFFFFFFFU + #define StartProgramBlockHi 0xFFFF0000U + #define StartProgramBlockLo 0xFFFFFFFFU + #define ValidBlockHi 0x00000000U + #define ValidBlockLo 0xFFFFFFFFU + #define InvalidBlockHi 0x00000000U + #define InvalidBlockLo 0xFFFF0000U + #define CorruptBlockHi 0x00000000U + #define CorruptBlockLo 0x00000000U + + #define FEE_BANK 0U + + /* Enable/Disable FEE sectors */ + #define FEE_DISABLE_SECTORS_31_00 0x00000000U + #define FEE_DISABLE_SECTORS_63_32 0x00000000U + #define FEE_ENABLE_SECTORS_31_00 0xFFFFFFFFU + #define FEE_ENABLE_SECTORS_63_32 0xFFFFFFFFU + +/********************************************************************************************************************** + * GLOBAL DATA TYPES AND STRUCTURES + *********************************************************************************************************************/ +/* Structures used */ +/* Enum to describe the Fee Status types */ +typedef enum +{ + TI_FEE_OK = 0U, /* Function returned no error */ + TI_FEE_ERROR = 1U /* Function returned an error */ +} TI_Fee_StatusType; + +/* Enum to describe the Virtual Sector State */ +typedef enum +{ + VsState_Invalid = 1U, + VsState_Empty = 2U, + VsState_Copy = 3U, + VsState_Active = 4U, + VsState_ReadyForErase = 5U +} VirtualSectorStatesType; + +/* Enum to describe the Block State */ +typedef enum +{ + Block_StartProg = 1U, + Block_Valid = 2U, + Block_Invalid = 3U +} BlockStatesType; + +/* Enum for error trpes */ +typedef enum +{ + Error_Nil = 0U, + Error_TwoActiveVS = 1U, + Error_TwoCopyVS = 2U, + Error_SetupStateMachine = 3U, + Error_CopyButNoActiveVS = 4U, + Error_NoActiveVS = 5U, + Error_BlockInvalid = 6U, + Error_NullDataPtr = 7U, + Error_NoFreeVS = 8U, + Error_InvalidVirtualSectorParameter = 9U, + Error_ExceedSectorOnBank = 10U, + Error_EraseVS = 11U, + Error_BlockOffsetGtBlockSize = 12U, + Error_LengthParam = 13U, + Error_FeeUninit = 14U, + Error_Suspend = 15U, + Error_InvalidBlockIndex = 16U, + Error_NoErase = 17U, + Error_CurrentAddress = 18U, + Error_Exceed_No_Of_DataSets = 19U +} TI_Fee_ErrorCodeType; + +typedef enum +{ + Suspend_Erase = 0U, + Resume_Erase +} TI_Fee_EraseCommandType; + +/* Enum to describe the Device types */ +typedef enum +{ + CHAMPION = 0U, /* Function returned no error */ + ARCHER = 1U /* Function returned an error */ +} TI_Fee_DeviceType; + +typedef uint32 TI_Fee_AddressType; /* Used for defining variables to indicate number of + bytes for address offset */ +typedef uint32 TI_Fee_LengthType; /* Used for defining variables to indicate number of + bytes per read/write/erase */ +typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType; + +/* Structure used when defining virtual sectors */ +/* The following error checks need to be performed: */ +/* Virtual Sector definitions are not allowed to overlap */ +/* Virtual Sector definition is at least twice the size in bytes of the total size of all + * defined blocks */ +/* We will need to define a formula to indicate if the number of write cycles indicated in + * the block definitions */ +/* is possible in the defined Virtual Sector. */ +/* Ending sector cannot be less than Starting sector */ +typedef struct +{ + uint16 FeeVirtualSectorNumber; /* Virtual Sector's Number - 0 and 0xFFFF values are + not allowed*/ + /* Minimum 1, Maximum 4 */ + uint16 FeeFlashBank; /* Flash Bank to use for virtual sector. */ + /* As we do not allow Flash EEPROM Emulation in Bank 0, + 0 is not a valid option */ + /* Defaultvalue 1, Minimum 1, Maxiumum 7 */ + Fapi_FlashSectorType FeeStartSector; /* Defines the Starting Sector inthe Bank for + this VirtualSector*/ + Fapi_FlashSectorType FeeEndSector; /* Defines the Ending Sector inthe Bank for this + Virtual Sector */ + /* Start and End sectors can be the same, which indicates only + one sector */ + /* is the entire virtual sector. */ + /* Values are based on the FLASH_SECT enum */ + /* Defaultvalue and Min is the same sector defined as the starting + sector */ + /* Max values are based onthe device definition file being used.*/ +} Fee_VirtualSectorConfigType; + +/* Structure used when defining blocks */ +typedef struct +{ + uint16 FeeBlockNumber; /* Block's Number - 0 and 0xFFFF values are not allowed */ + /* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */ + uint16 FeeBlockSize; /* Block's Size - Actual number of bits used is reduced */ + /* by number of bits used for dataset. */ + /* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */ + boolean FeeImmediateData; /* Indicates if the block is used for immediate data */ + /* Default: False */ + uint32 FeeNumberOfWriteCycles; /* Number of write cycles this block requires */ + /* Default: 0, but this will not be a valid number. + Force customer to select a value */ + /* Min 1, Max (2^32)-1 */ + uint8 FeeDeviceIndex; /* Device Index - This will always be 0 */ + /* Fixed value: 0 */ + uint8 FeeNumberOfDataSets; /* Number of DataSets for the Block */ + /* Default value: 1 */ + uint8 FeeEEPNumber; +} Fee_BlockConfigType; + +/* Structure used for Global variables */ +typedef struct +{ + TI_Fee_AddressType Fee_oFlashNextAddress; /* The next Flash Address to write to */ + TI_Fee_AddressType Fee_oCopyCurrentAddress; /* Indicates the Address within the Active + VS which will be copied to Copy VS */ + TI_Fee_AddressType Fee_oCopyNextAddress; /* Indicates the Address within the Copy VS + to which the data from Active VS will be + copied to */ + TI_Fee_AddressType Fee_u32nextwriteaddress; /* Indicates the next free Address within + the curent VS to which the data will be + written */ + TI_Fee_AddressType Fee_oVirtualSectorStartAddress; /* Start Address of the current + Virtual Sector */ + TI_Fee_AddressType Fee_oVirtualSectorEndAddress; /* End Address of the current Virtual + Sector */ + TI_Fee_AddressType Fee_oCopyVirtualSectorAddress; /* Start Address of the Copy Virtual + Address */ + TI_Fee_AddressType Fee_oCurrentStartAddress; /* Start Address of the Previous Block */ + TI_Fee_AddressType Fee_oCurrentBlockHeader; /* Start Address of the Block which is + being currently written*/ + TI_Fee_AddressType Fee_oWriteAddress; /* Address within the VS where data is to be + written */ + TI_Fee_AddressType Fee_oCopyWriteAddress; /* Address within the VS where data is to be + copied */ + TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; /* Start Address of the Active VS + */ + TI_Fee_AddressType Fee_oBlankFailAddress; /* Address of first non-blank location */ + TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress; /* Start Address of the + active VS */ + TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress; /* End Address of the active VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress; /* Start Address of the Copy VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress; /* End Address of the Copy VS */ + TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress; /* Next write address in Active VS + */ + TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress; /* Next write address in Copy VS */ + uint16 Fee_u16CopyBlockSize; /* Indicates the size of current block in bytes which is + been copied from Active to Copy VS */ + uint8 Fee_u8VirtualSectorStart; /* Index of the Start Sector of the VS */ + uint8 Fee_u8VirtualSectorEnd; /* Index of the End Sector of the VS */ + uint32 Fee_au32VirtualSectorStateValue[ TI_FEE_VIRTUAL_SECTOR_OVERHEAD + >> 2U ]; /* Array to store the Virtual + Sector Header and + Information record */ + uint8 Fee_au8VirtualSectorState[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Stores the + state of each + Virtual sector + */ + uint32 Fee_au32VirtualSectorEraseCount[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Array + to + store + the + erase + count + of each + Virtual + Sector*/ + uint16 Fee_au16BlockOffset[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to store within + the VS */ + uint32 Fee_au32BlockHeader[ TI_FEE_BLOCK_OVERHEAD >> 2U ]; /* Array to store the Block + Header value */ + uint8 Fee_au8BlockCopyStatus[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to storeblock + copy status */ + uint8 Fee_u8InternalVirtualSectorStart; /* Indicates internal VS start index */ + uint8 Fee_u8InternalVirtualSectorEnd; /* Indicates internal VS end index */ + TI_FeeModuleStatusType Fee_ModuleState; /* Indicates the state of the FEE module */ + TI_FeeJobResultType Fee_u16JobResult; /* Stores the Job Result of the current command + */ + TI_Fee_StatusType Fee_oStatus; /* Indicates the status of FEE */ + TI_Fee_ErrorCodeType Fee_Error; /* Indicates the Error code */ + uint16 Fee_u16CopyBlockNumber; /* Block number which is currently being copied */ + uint16 Fee_u16BlockIndex; /* Index of the Current Block */ + uint16 Fee_u16BlockCopyIndex; /* Index of the Block being copied from Copy to Active + VS */ + uint16 Fee_u16DataSetIndex; /* Index of the Current DataSet */ + uint16 Fee_u16ArrayIndex; /* Index of the Current DataSet */ + uint16 Fee_u16BlockSize; /* Size of the current block in bytes */ + uint16 Fee_u16BlockSizeinBlockHeader; /* Size of the current block. Used to write into + Block Header */ + uint16 Fee_u16BlockNumberinBlockHeader; /* Number of the current block. Used to write + into Block Header */ + uint8 Fee_u8ActiveVirtualSector; /* Indicates the FeeVirtualSectorNumber for the + Active VS */ + uint8 Fee_u8CopyVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Copy VS + */ + uint32 Fee_u32InternalEraseQueue; /* Indicates which VS can be erased when the FEE is + in BusyInternal State*/ + uint8 Fee_u8WriteCopyVSHeader; /* Indicates the number of bytes of the Copy VS Header + being written */ + uint8 Fee_u8WriteCount; /* Indicates the number of bytes of the Block Header being + written */ + uint8 * Fee_pu8ReadDataBuffer; /* Pointer to read data */ + uint8 * Fee_pu8ReadAddress; /* Pointer to read address */ + uint8 * Fee_pu8Data; /* Pointer to the next data to be written to the VS */ + uint8 * Fee_pu8CopyData; /* Pointer to the next data to be copied to the VS */ + uint8 * Fee_pu8DataStart; /* Pointer to the first data to be written to the VS */ + boolean Fee_bInvalidWriteBit; /* Indicates whether the block is + written/invalidated/erased for the first time */ + boolean Fee_bWriteData; /* Indicates that there is data which is pending to be written + to the Block */ + boolean Fee_bWriteBlockHeader; /* Indicates whether the Block Header has been written + or not */ + boolean bWriteFirstTime; /* Indicates if the block is being written first time */ + boolean Fee_bFindNextVirtualSector; /* Indicates if there is aneed to find next free + VS */ + boolean Fee_bWriteVSHeader; /* Indicates if block header needs to be written */ + boolean Fee_bWriteStartProgram; /* Indicates if start program block header needs to be + written */ + boolean Fee_bWritePartialBlockHeader; /* Indicates if start program block header needs + to be written */ + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) + uint16 Fee_au16UnConfiguredBlockAddress + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Indicates + number of unconfigured blocks to copy */ + uint8 Fee_au8UnConfiguredBlockCopyStatus + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Array to store block + copy status */ + #endif +} TI_Fee_GlobalVarsType; + +/********************************************************************************************************************** + * EXTERN Declarations + *********************************************************************************************************************/ +/* Fee Global Variables */ +extern const Fee_BlockConfigType Fee_BlockConfiguration[ TI_FEE_NUMBER_OF_BLOCKS ]; + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF ) +extern const Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern const Device_FlashType Device_FlashDevice; + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +extern Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern Device_FlashType Device_FlashDevice; +extern uint8 TI_Fee_MaxSectors; + #endif +extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[ TI_FEE_NUMBER_OF_EEPS ]; +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[ TI_FEE_NUMBER_OF_EEPS ]; + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +extern uint32 TI_Fee_u32FletcherChecksum; + #endif +extern uint32 TI_Fee_u32BlockEraseCount; +extern uint8 TI_Fee_u8DataSets; +extern uint8 TI_Fee_u8DeviceIndex; +extern uint32 TI_Fee_u32ActCpyVS; +extern uint8 TI_Fee_u8ErrEraseVS; + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) +extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[ TI_FEE_NUMBER_OF_EEPS ]; + #endif + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern boolean Fee_bDoubleBitError; +extern boolean Fee_bSingleBitError; + #endif + #if( TI_FEE_NUMBER_OF_EEPS == 2U ) +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global; + #endif +extern boolean TI_Fee_FapiInitCalled; +extern boolean TI_Fee_bEraseSuspended; +extern boolean TI_Fee_bIsMainFunctionCalled; + +/********************************************************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + *********************************************************************************************************************/ +/* Interface Functions */ +extern void TI_Fee_Cancel( uint8 u8EEPIndex ); +extern Std_ReturnType TI_Fee_EraseImmediateBlock( uint16 BlockNumber ); +extern TI_FeeModuleStatusType TI_Fee_GetStatus( uint8 u8EEPIndex ); +extern void TI_Fee_GetVersionInfo( Std_VersionInfoType * VersionInfoPtr ); +extern void TI_Fee_Init( void ); +extern Std_ReturnType TI_Fee_InvalidateBlock( uint16 BlockNumber ); +extern Std_ReturnType TI_Fee_Read( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); +extern Std_ReturnType TI_Fee_WriteAsync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern void TI_Fee_MainFunction( void ); +extern TI_Fee_ErrorCodeType TI_FeeErrorCode( uint8 u8EEPIndex ); +extern void TI_Fee_ErrorRecovery( TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector ); +extern TI_FeeJobResultType TI_Fee_GetJobResult( uint8 u8EEPIndex ); +extern void TI_Fee_SuspendResumeErase( TI_Fee_EraseCommandType Command ); + + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern void TI_Fee_ErrorHookSingleBitError( void ); +extern void TI_Fee_ErrorHookDoubleBitError( void ); + #endif + + #if( TI_FEE_DRIVER == 1U ) +extern Std_ReturnType TI_Fee_WriteSync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern Std_ReturnType TI_Fee_Shutdown( void ); +extern boolean TI_Fee_Format( uint32 u32FormatKey ); +extern Std_ReturnType TI_Fee_ReadSync( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); + #endif + +/* TI Fee Internal Functions */ +TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress( uint8 u8EEPIndex ); +TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC( TI_Fee_AddressType oAddress ); +TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - + * TI_FeeInternal_GetVirtualSectorParameter name is required here."*/ +uint32 TI_FeeInternal_GetVirtualSectorParameter( Fapi_FlashSectorType oSector, + uint16 u16Bank, + boolean VirtualSectorInfo, + uint8 u8EEPIndex ); +uint32 TI_FeeInternal_PollFlashStatus( void ); +uint16 TI_FeeInternal_GetBlockSize( uint16 BlockIndex ); +uint16 TI_FeeInternal_GetBlockIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetDataSetIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetBlockNumber( uint16 BlockNumber ); +uint8 TI_FeeInternal_FindNextVirtualSector( uint8 u8EEPIndex ); +uint8 TI_FeeInternal_WriteDataF021( boolean bCopy, + uint16 u16WriteSize, + uint8 u8EEPIndex ); +boolean TI_FeeInternal_BlankCheck( uint32 u32StartAddress, + uint32 u32EndAddress, + uint16 u16Bank, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckReadParameters( uint32 u32BlockSize, + uint16 BlockOffset, + const uint8 * DataBufferPtr, + uint16 Length, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckModuleState( uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_InvalidateErase( uint16 BlockNumber ); +TI_Fee_StatusType TI_FeeInternal_FeeManager( uint8 u8EEPIndex ); +void TI_FeeInternal_WriteVirtualSectorHeader( uint8 FeeVirtualSectorNumber, + VirtualSectorStatesType VsState, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - TI_FeeInternal_GetVirtualSectorIndex + * name is required here."*/ +void TI_FeeInternal_GetVirtualSectorIndex( Fapi_FlashSectorType oSectorStart, + Fapi_FlashSectorType oSectorEnd, + uint16 u16Bank, + boolean bOperation, + uint8 u8EEPIndex ); +void TI_FeeInternal_WritePreviousBlockHeader( boolean bWrite, uint8 u8EEPIndex ); +void TI_FeeInternal_WriteBlockHeader( boolean bWrite, + uint8 u8EEPIndex, + uint16 Fee_BlockSize_u16, + uint16 u16BlockNumber ); +void TI_FeeInternal_SetClearCopyBlockState( uint8 u8EEPIndex, boolean bSetClear ); +void TI_FeeInternal_SanityCheck( uint16 BlockSize, uint8 u8EEPIndex ); +void TI_FeeInternal_StartProgramBlock( uint8 u8EEPIndex ); +void TI_FeeInternal_UpdateBlockOffsetArray( uint8 u8EEPIndex, + boolean bActCpyVS, + uint8 u8VirtualSector ); +void TI_FeeInternal_WriteInitialize( TI_Fee_AddressType oFlashNextAddress, + uint8 * DataBufferPtr, + uint8 u8EEPIndex ); +void TI_FeeInternal_CheckForError( uint8 u8EEPIndex ); +void TI_FeeInternal_EnableRequiredFlashSector( uint32 u32VirtualSectorStartAddress ); +uint16 TI_FeeInternal_GetArrayIndex( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex, + boolean bCallContext ); + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +uint32 TI_FeeInternal_Fletcher16( uint8 const * pu8data, uint16 u16Length ); + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +void TI_FeeInternal_PopulateStructures( TI_Fee_DeviceType DeviceType ); + #endif +#endif /* TI_FEE_H */ +/********************************************************************************************************************** + * END OF FILE: ti_fee.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h new file mode 100644 index 00000000000..60e8117e6c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h @@ -0,0 +1,55 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_cfg.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: HALCoGen + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.00.01 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + *history. + * + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h new file mode 100644 index 00000000000..7dea8d67c26 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h @@ -0,0 +1,260 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 03.00.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + *segmentation changes. 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 + *MISRA C fixes. + * 01.15.00 06Jun2014 Vishwanath Reddy Support for LC + *Varients. 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove + *MISRA warnings. + * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version + *history. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + *history. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + *history. 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update + *version history. SDOCM00122429 Added error when endianess is not defined. 01.19.00 + *08Augu2016 Vishwanath Reddy SDOCM00122592 Update version history. 01.19.01 + *12Augu2016 Vishwanath Reddy SDOCM00122543 Update version history. 01.19.03 + *15May2017 Prathap Srinivasan SDOCM00122917 Update version history. 01.19.04 + *05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_TYPES_H + #define TI_FEE_TYPES_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "Device_header.h" + + #ifndef TI_Fee_None + #define TI_Fee_None \ + 0x00U /*Take no action on single bit errors, (respond with corrected data), \ + */ + /*return error for uncorrectable error reads (multibit errors for ECC or parity + * failures)*/ + /*For devices with no ECC (they may have parity or not) the only valid option is none. + */ + #endif + + #ifndef TI_Fee_Fix + #define TI_Fee_Fix 0x01U /* single bit error will be fixed by reprogramming */ + /* return previous valid data for uncorrectable error reads (multi bit errors for ECC + or parity failures). */ + #endif + + #if !defined( _LITTLE_ENDIAN ) && !defined( _BIG_ENDIAN ) + #error "Target Endianess is not defined. Include F021 header files and library." + #endif + +/*SAFETYMCUSW 74 S MR:18.4 "Reason - union declaration is necessary here."*/ +typedef union +{ + uint16 Fee_u16StatusWord; + #ifdef _BIG_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + } Fee_StatusWordType_ST; + #endif + #ifdef _LITTLE_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + } Fee_StatusWordType_ST; + #endif +} TI_Fee_StatusWordType_UN; + +typedef enum +{ + UNINIT, + IDLE, + /*SAFETYMCUSW 91 S MR:5.2,5.6,5.7 "Reason - BUSY in F021 is a member of + * structure."*/ + BUSY, + BUSY_INTERNAL +} TI_FeeModuleStatusType; + +typedef enum +{ + JOB_OK, + JOB_FAILED, + JOB_PENDING, + JOB_CANCELLED, + BLOCK_INCONSISTENT, + BLOCK_INVALID +} TI_FeeJobResultType; + +#endif /* TI_FEE_TYPES_H */ + +/********************************************************************************************************************** + * END OF FILE: ti_fee_types.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c new file mode 100644 index 00000000000..c9b4ed5f955 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c @@ -0,0 +1,1052 @@ +/** @file adc.c + * @brief ADC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void adcInit(void) + * @brief Initializes ADC Driver + * + * This function initializes the ADC driver. + * + */ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ADC_SourceId_001 */ +/* DesignId : ADC_DesignId_001 */ +/* Requirements : CONQ_ADC_SR2 */ +void adcInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b Initialize @b ADC1: */ + + /** - Reset ADC module */ + adcREG1->RSTCR = 1U; + adcREG1->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG1->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG1->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG1->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG1->BNDEND = ( adcREG1->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup event group sample window */ + adcREG1->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 1 sample window */ + adcREG1->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 2 sample window */ + adcREG1->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC1 EVT pin output value */ + adcREG1->EVTOUT = 0U; + + /** - ADC1 EVT pin direction */ + adcREG1->EVTDIR = 0U; + + /** - ADC1 EVT pin open drain enable */ + adcREG1->EVTPDR = 0U; + + /** - ADC1 EVT pin pullup / pulldown selection */ + adcREG1->EVTPSEL = 1U; + + /** - ADC1 EVT pin pullup / pulldown enable*/ + adcREG1->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG1->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG1->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG1->PARCR = 0x00000005U; + + /** @b Initialize @b ADC2: */ + + /** - Reset ADC module */ + adcREG2->RSTCR = 1U; + adcREG2->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG2->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG2->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG2->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG2->BNDEND = ( adcREG2->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup event group sample window */ + adcREG2->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 1 sample window */ + adcREG2->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 2 sample window */ + adcREG2->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC2 EVT pin output value */ + adcREG2->EVTOUT = 0U; + + /** - ADC2 EVT pin direction */ + adcREG2->EVTDIR = 0U; + + /** - ADC2 EVT pin open drain enable */ + adcREG2->EVTPDR = 0U; + + /** - ADC2 EVT pin pullup / pulldown selection */ + adcREG2->EVTPSEL = 1U; + + /** - ADC2 EVT pin pullup / pulldown enable*/ + adcREG2->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG2->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG2->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG2->PARCR = 0x00000005U; + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** - s_adcSelect is used as constant table for channel selection */ +static const uint32 s_adcSelect[ 2U ][ 3U ] = { + { 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U }, + { + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + } +}; + +/** - s_adcFiFoSize is used as constant table for channel selection */ +static const uint32 s_adcFiFoSize[ 2U ][ 3U ] = { { 16U, 16U, 16U }, { 16U, 16U, 16U } }; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) + * @brief Starts an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function starts a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_002 */ +/* DesignId : ADC_DesignId_002 */ +/* Requirements : CONQ_ADC_SR3 */ +void adcStartConversion( adcBASE_t * adc, uint32 group ) +{ + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Setup FiFo size */ + adc->GxINTCR[ group ] = s_adcFiFoSize[ index ][ group ]; + + /** - Start Conversion */ + adc->GxSEL[ group ] = s_adcSelect[ index ][ group ]; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) + * @brief Stops an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function stops a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_003 */ +/* DesignId : ADC_DesignId_003 */ +/* Requirements : CONQ_ADC_SR4 */ +void adcStopConversion( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Stop Conversion */ + adc->GxSEL[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) + * @brief Resets FiFo read and write pointer. + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function resets the FiFo read and write pointers. + * + */ +/* SourceId : ADC_SourceId_004 */ +/* DesignId : ADC_DesignId_004 */ +/* Requirements : CONQ_ADC_SR5 */ +void adcResetFiFo( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Reset FiFo */ + adc->GxFIFORESETCR[ group ] = 1U; + + /** @note The function adcInit has to be called before this function can be used.\n + * the conversion should be stopped before calling this function. + */ + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) + * @brief Gets converted a ADC values + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @param[out] data Pointer to store ADC converted data + * @return The function will return the number of converted values copied into data + * buffer: + * + * This function writes a ADC message into a ADC message box. + * + */ +/* SourceId : ADC_SourceId_005 */ +/* DesignId : ADC_DesignId_005 */ +/* Requirements : CONQ_ADC_SR6 */ +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ) +{ + uint32 i; + uint32 buf; + uint32 mode; + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + uint32 intcr_reg = adc->GxINTCR[ group ]; + uint32 count = ( intcr_reg >= 256U ) ? s_adcFiFoSize[ index ][ group ] + : ( s_adcFiFoSize[ index ][ group ] + - ( uint32 ) ( intcr_reg & 0xFFU ) ); + adcData_t * ptr = data; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mode = ( adc->OPMODECR & ADC_12_BIT_MODE ); + + if( mode == ADC_12_BIT_MODE ) + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0xFFFU ); + ptr->id = ( uint32 ) ( ( buf >> 16U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + else + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0x3FFU ); + ptr->id = ( uint32 ) ( ( buf >> 10U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + + adc->GxINTFLG[ group ] = 9U; + + /** @note The function adcInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return count; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) + * @brief Checks if FiFo buffer is full + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When FiFo buffer is not full + * - 1: When FiFo buffer is full + * - 3: When FiFo buffer overflow occurred + * + * This function checks FiFo buffer status. + * + */ +/* SourceId : ADC_SourceId_006 */ +/* DesignId : ADC_DesignId_006 */ +/* Requirements : CONQ_ADC_SR7 */ +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read FiFo flags */ + flags = adc->GxINTFLG[ group ] & 3U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) + * @brief Checks if Conversion is complete + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When is not finished + * - 8: When conversion is complete + * + * This function checks if conversion is complete. + * + */ +/* SourceId : ADC_SourceId_007 */ +/* DesignId : ADC_DesignId_007 */ +/* Requirements : CONQ_ADC_SR8 */ +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Read conversion flags */ + flags = adc->GxINTFLG[ group ] & 8U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn void adcCalibration(adcBASE_t *adc) + * @brief Computes offset error using Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * This function computes offset error using Calibration mode + * + */ +/* SourceId : ADC_SourceId_008 */ +/* DesignId : ADC_DesignId_010 */ +/* Requirements : CONQ_ADC_SR11 */ +void adcCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + uint32 conv_val[ 5U ] = { 0U, 0U, 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 4U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + case 2U: /* Test 1 : Bride En = 1 , HiLo =0 */ + adc->CALCR = 0x0200U; + break; + + case 3U: /* Test 1 : Bride En = 1 , HiLo =1 */ + adc->CALCR = 0x0300U; + break; + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 4U ] = conv_val[ 0U ] + conv_val[ 1U ] + conv_val[ 2U ] + conv_val[ 3U ]; + + conv_val[ 4U ] = ( conv_val[ 4U ] / 4U ); + + offset_error = conv_val[ 4U ] - 0x7FFU; + + /*Write the offset error to the Calibration register */ + /* Load 2;s complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error & 0xFFFU; + offset_error = offset_error + 1U; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + /** @note The function adcInit has to be called before using this function. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/** @fn void adcMidPointCalibration(adcBASE_t *adc) + * @brief Computes offset error using Mid Point Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @return This function will return offset error using Mid Point Calibration mode + * + * This function computes offset error using Mid Point Calibration mode + * + */ +/* SourceId : ADC_SourceId_009 */ +/* DesignId : ADC_DesignId_011 */ +/* Requirements : CONQ_ADC_SR12 */ +uint32 adcMidPointCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + uint32 conv_val[ 3U ] = { 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 2U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 2U ] = ( conv_val[ 0U ] ) + ( conv_val[ 1U ] ); + + conv_val[ 2U ] = ( conv_val[ 2U ] / 2U ); + + offset_error = conv_val[ 2U ] - 0x7FFU; + + /* Write the offset error to the Calibration register */ + /* Load 2's complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error + 1U; + offset_error = offset_error & 0xFFFU; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + return ( offset_error ); + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) + * @brief Enable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will enable the notification of a conversion. + * In single conversion mode for conversion complete and + * in continuous conversion mode when the FiFo buffer is full. + * + */ +/* SourceId : ADC_SourceId_010 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : CONQ_ADC_SR9 */ +void adcEnableNotification( adcBASE_t * adc, uint32 group ) +{ + uint32 notif = ( ( ( uint32 ) ( adc->GxMODECR[ group ] ) & 2U ) == 2U ) ? 1U : 8U; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = notif; + + /** @note The function adcInit has to be called before this function can be used.\n + * This function should be called before the conversion is started + */ + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + +/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) + * @brief Disable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will disable the notification of a conversion. + */ +/* SourceId : ADC_SourceId_011 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : CONQ_ADC_SR9 */ +void adcDisableNotification( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} + +/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @param[in] value Value to be set: 0 or 1 + * + * This function will set the ADC EVT pin if configured as an output pin. + */ +/* SourceId : ADC_SourceId_012 */ +/* DesignId : ADC_DesignId_014 */ +/* Requirements : CONQ_ADC_SR13 */ +void adcSetEVTPin( adcBASE_t * adc, uint32 value ) +{ + adc->EVTOUT = value; +} + +/** @fn uint32 adcGetEVTPin(adcBASE_t *adc) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @return Value of the ADC EVT pin: 0 or 1 + * + * This function will return the value of ADC EVT pin. + */ +/* SourceId : ADC_SourceId_013 */ +/* DesignId : ADC_DesignId_015 */ +/* Requirements : CONQ_ADC_SR14 */ +uint32 adcGetEVTPin( adcBASE_t * adc ) +{ + return adc->EVTIN; +} + +/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_014 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : CONQ_ADC_SR15 */ +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC1_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC1_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC1_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; + } + else + { + config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG1->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG1->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG1->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG1->EVSRC; + config_reg->CONFIG_G1SRC = adcREG1->G1SRC; + config_reg->CONFIG_G2SRC = adcREG1->G2SRC; + config_reg->CONFIG_BNDCR = adcREG1->BNDCR; + config_reg->CONFIG_BNDEND = adcREG1->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG1->PARCR; + } +} + +/** @fn void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_015 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : CONQ_ADC_SR15 */ +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC2_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC2_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC2_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC2_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC2_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC2_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC2_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC2_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC2_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC2_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC2_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC2_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC2_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC2_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC2_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC2_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC2_PARCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_OPMODECR = adcREG2->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG2->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG2->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG2->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG2->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG2->EVSRC; + config_reg->CONFIG_G1SRC = adcREG2->G1SRC; + config_reg->CONFIG_G2SRC = adcREG2->G2SRC; + config_reg->CONFIG_BNDCR = adcREG2->BNDCR; + config_reg->CONFIG_BNDEND = adcREG2->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG2->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG2->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG2->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG2->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG2->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG2->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG2->PARCR; + } +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c new file mode 100644 index 00000000000..2dbf833636c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c @@ -0,0 +1,1690 @@ +/** @file can.c + * @brief CAN Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "can.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Global and Static Variables */ + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) +#else +static const uint32 s_canByteOrder[ 8U ] = { 3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U }; +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void canInit(void) + * @brief Initializes CAN Driver + * + * This function initializes the CAN driver. + * + */ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +/* SourceId : CAN_SourceId_001 */ +/* DesignId : CAN_DesignId_001 */ +/* Requirements : CONQ_CAN_SR4 */ +void canInit( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG1->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG1->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG1->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG1->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG1->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG1->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG1->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN1 Port output values */ + canREG1->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG1->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG1->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN2: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG2->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG2->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG2->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG2->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG2->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG2->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG2->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG2->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN2 Port output values */ + canREG2->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG2->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG2->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN3: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG3->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG3->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG3->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + canREG3->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG3->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG3->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG3->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG3->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) ( uint32 ) 9U; + + /** - CAN3 Port output values */ + canREG3->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG3->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG3->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG4->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG4->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG4->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG4->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG4->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG4->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG4->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG4->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG4->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG4->BTR = ( ( uint32 ) 0U << 16U ) | ( ( ( uint32 ) 4U - 1U ) << 12U ) + | ( ( ( ( uint32 ) 6U + ( uint32 ) 4U ) - 1U ) << 8U ) + | ( ( ( uint32 ) 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN4 Port output values */ + canREG4->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG4->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + /** - Leave configuration and initialization mode */ + canREG4->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data) + * @brief Transmits a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of the TX message box wasn't successful + * - 1: When the setup of the TX message box was successful + * + * This function writes a CAN message into a CAN message box. + * + */ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_002 */ +/* DesignId : CAN_DesignId_002 */ +/* Requirements : CONQ_CAN_SR5 */ +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + * - Start Transmission + */ + node->IF1CMD = 0x87U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return: + * - 0: When RX message box hasn't received new data + * - 1: When RX data are stored in the data buffer + * - 3: When RX data are stored in the data buffer and a message was lost + * + * This function writes a CAN message into a CAN message box. + * + */ + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_003 */ +/* DesignId : CAN_DesignId_003 */ +/* Requirements : CONQ_CAN_SR6 */ +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ) +{ + uint32 i; + uint32 size; + uint8 * pData = data; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Check if new data have been arrived: + * - no new data, return 0 + * - new data, get received message + */ + if( ( node->NWDATx[ regIndex ] & bitIndex ) == 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF2 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x17U; + + /** - Copy data into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Get number of received bytes */ + size = node->IF2MCTL & 0xFU; + if( size > 0x8U ) + { + size = 0x8U; + } + /** - Copy RX data into destination buffer */ + for( i = 0U; i < size; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + pData++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ s_canByteOrder[ i ] ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + pData++; +#endif + } + + success = 1U; + } + /** - Check if data have been lost: + * - no data lost, return 1 + * - data lost, return 3 + */ + if( ( node->IF2MCTL & 0x4000U ) == 0x4000U ) + { + success = 3U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetID(canBASE_t *node, uint32 messageBox) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return the ID of the message box. + * + * This function gets the identifier of a CAN message box. + * + */ +/* SourceId : CAN_SourceId_026 */ +/* DesignId : CAN_DesignId_020 */ +/* Requirements : CONQ_CAN_SR39 */ +uint32 canGetID( canBASE_t * node, uint32 messageBox ) +{ + uint32 msgBoxID = 0U; + + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x20U; + + /** - Copy message box number into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /* Read Message Box ID from Arbitration register. */ + msgBoxID = ( node->IF2ARB & 0x1FFFFFFFU ); + + return msgBoxID; +} + +/** @fn uint32 canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal) +* @brief Gets received a CAN message +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* - canREG4: CAN4 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[in] msgBoxArbitVal (32 bit value): +* Bit 31 - Not used. +* Bit 30 - 0 - The 11-bit ("standard") identifier is used for this message +object. * 1 - The 29-bit ("extended") identifier is used for this +message object. * Bit 29 - 0 - Direction = Receive +* 1 - Direction = Transmit +* Bit 28:0 - Message Identifier. +* @return + +* +* This function changes the Identifier and other arbitration parameters of a CAN Message +Box. +* +*/ +/* SourceId : CAN_SourceId_027 */ +/* DesignId : CAN_DesignId_021 */ +/* Requirements : CONQ_CAN_SR40 */ +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ) +{ + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0xA0U; + /* Copy passed value into the arbitration register. */ + node->IF2ARB &= 0x80000000U; + node->IF2ARB |= ( msgBoxArbitVal & 0x7FFFFFFFU ); + + /** - Update message box number. */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ +} + +/** @fn uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox) + * @brief Transmits a CAN Remote Frame. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of Send Remote Frame from message box wasn't successful + * - 1: When the setup of Send Remote Frame from message box was successful + * + * This function triggers Remote Frame Transmission from CAN message box. + * Note : Enable RTR must be set in the Message x Configuration in the GUI( x: 1 - 64) + * + */ +/* SourceId : CAN_SourceId_028 */ +/* DesignId : CAN_DesignId_022 */ +/* Requirements : CONQ_CAN_SR23 */ +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ) +{ + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Request Transmission by setting TxRqst in message box */ + node->IF1CMD = ( uint8 ) 0x84U; + + /** - Trigger Remote Frame Transmit from message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + return success; +} + +/** @fn uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * + * data) + * @brief Fills the Message Object with the data but does not initiate transmission. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return: + * - 0: When the Fill up of the TX message box wasn't successful + * - 1: When the Fill up of the TX message box was successful + * + * This function fills the Message Object with the data but does not initiate + * transmission. + * + */ +/* SourceId : CAN_SourceId_029 */ +/* DesignId : CAN_DesignId_023 */ +/* Requirements : CONQ_CAN_SR24 */ +uint32 canFillMessageObjectData( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + */ + node->IF1CMD = 0x83U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + + return success; +} + +/** @fn uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox) + * @brief Gets Tx message box transmission status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the tx request flag + * + * Checks to see if the Tx message box has a pending Tx request, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_004 */ +/* DesignId : CAN_DesignId_004 */ +/* Requirements : CONQ_CAN_SR7 */ +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->TXRQx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox) + * @brief Gets Rx message box reception status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the Rx message box has pending Rx data, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_005 */ +/* DesignId : CAN_DesignId_005 */ +/* Requirements : CONQ_CAN_SR8 */ +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->NWDATx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox) + * @brief Checks if message box is valid + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the message box is valid for operation, returns + * 0 is flag not set otherwise will return the validation flag itself. + */ + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_006 */ +/* DesignId : CAN_DesignId_006 */ +/* Requirements : CONQ_CAN_SR9 */ +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->MSGVALx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canGetLastError(canBASE_t *node) + * @brief Gets last RX/TX-Error of CAN message traffic + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @return The function will return: + * - canERROR_OK (0): When no CAN error occurred + * - canERROR_STUFF (1): When a stuff error occurred on RX message + * - canERROR_FORMAT (2): When a form/format error occurred on RX message + * - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged + * - canERROR_BIT1 (4): When a TX message monitored dominant level where + * recessive is expected + * - canERROR_BIT0 (5): When a TX message monitored recessive level where + * dominant is expected + * - canERROR_CRC (6): When a RX message has wrong CRC value + * - canERROR_NO (7): When no error occurred since last call of this function + * + * This function returns the last occurred error code of an RX or TX message, + * since the last call of this function. + * + */ + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_007 */ +/* DesignId : CAN_DesignId_007 */ +/* Requirements : CONQ_CAN_SR10 */ +uint32 canGetLastError( canBASE_t * node ) +{ + uint32 errorCode; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Get last error code */ + errorCode = node->ES & 7U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return errorCode; +} + +/** @fn uint32 canGetErrorLevel(canBASE_t *node) + * @brief Gets error level of a CAN node + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @return The function will return: + * - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and + * 255 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * + * This function returns the current error level of a CAN node. + * + */ + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_008 */ +/* DesignId : CAN_DesignId_008 */ +/* Requirements : CONQ_CAN_SR11 */ +uint32 canGetErrorLevel( canBASE_t * node ) +{ + uint32 errorLevel; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + /** - Get error level */ + errorLevel = node->ES & 0xE0U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + return errorLevel; +} + +/** @fn void canEnableErrorNotification(canBASE_t *node) + * @brief Enable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will enable the notification for the reaching the error levels warning, + * passive and bus off. + */ + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_009 */ +/* DesignId : CAN_DesignId_009 */ +/* Requirements : CONQ_CAN_SR12 */ +void canEnableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + node->CTL |= 8U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + +/** @fn void canEnableStatusChangeNotification(canBASE_t *node) + * @brief Enable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will enable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_030 */ +/* DesignId : CAN_DesignId_024 */ +/* Requirements : CONQ_CAN_SR25 */ +void canEnableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL |= 4U; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableStatusChangeNotification(canBASE_t *node) + * @brief Disable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_031 */ +/* DesignId : CAN_DesignId_025 */ +/* Requirements : CONQ_CAN_SR26 */ +void canDisableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL &= ~( uint32 ) ( 4U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableErrorNotification(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable the notification for the reaching the error levels + * warning, passive and bus off. + */ + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_010 */ +/* DesignId : CAN_DesignId_010 */ +/* Requirements : CONQ_CAN_SR13 */ +void canDisableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + node->CTL &= ~( uint32 ) ( 8U ); + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] Loopbacktype Type of Loopback: + * - Internal_Lbk: Internal Loop Back + * - External_Lbk: External Loop Back + * - Internal_Silent_Lbk: Internal Loop Back with Silent mode. + * + * This function will enable can loopback mode + */ +/* SourceId : CAN_SourceId_011 */ +/* DesignId : CAN_DesignId_011 */ +/* Requirements : CONQ_CAN_SR21 */ +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ) +{ + /* Enter Test Mode */ + node->CTL |= ( uint32 ) ( ( uint32 ) 1U << 7U ); + + /* Configure Loopback */ + node->TEST |= ( uint32 ) Loopbacktype; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableloopback(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable can loopback mode + */ +/* SourceId : CAN_SourceId_012 */ +/* DesignId : CAN_DesignId_012 */ +/* Requirements : CONQ_CAN_SR22 */ +void canDisableloopback( canBASE_t * node ) +{ + node->TEST &= ~( uint32 ) ( 0x00000118U ); + + /* Exit Test Mode */ + node->CTL &= ~( uint32 ) ( ( uint32 ) 1U << 7U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir) + * @brief Set Port Direction + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] TxDir - TX Pin direction + * @param[in] RxDir - RX Pin direction + * + * Set the direction of CAN pins at runtime when configured as IO pins. + */ +/* SourceId : CAN_SourceId_013 */ +/* DesignId : CAN_DesignId_013 */ +/* Requirements : CONQ_CAN_SR14 */ +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ) +{ + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFBU ) | ( TxDir << 2U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFBU ) | ( RxDir << 2U ) ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue) + * @brief Write Port Value + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] TxValue - TX Pin value 0 or 1 + * @param[in] RxValue - RX Pin value 0 or 1 + * + * Writes a value to TX and RX pin of a given CAN module when configured as IO pins. + */ +/* SourceId : CAN_SourceId_014 */ +/* DesignId : CAN_DesignId_014 */ +/* Requirements : CONQ_CAN_SR15 */ +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFDU ) | ( TxValue << 1U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFDU ) | ( RxValue << 1U ) ); + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn uint32 canIoTxGetBit(canBASE_t *node) + * @brief Read TX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the TX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_015 */ +/* DesignId : CAN_DesignId_015 */ +/* Requirements : CONQ_CAN_SR16 */ +uint32 canIoTxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + return ( node->TIOC & 1U ); +} + +/** @fn uint32 canIoRxGetBit(canBASE_t *node) + * @brief Read RX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the RX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_016 */ +/* DesignId : CAN_DesignId_016 */ +/* Requirements : CONQ_CAN_SR17 */ +uint32 canIoRxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + + return ( node->RIOC & 1U ); +} + +/** @fn void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_017 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR27 */ +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN1_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN1_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN1_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN1_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN1_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN1_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN1_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN1_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN1_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG1->CTL; + config_reg->CONFIG_ES = canREG1->ES; + config_reg->CONFIG_BTR = canREG1->BTR; + config_reg->CONFIG_TEST = canREG1->TEST; + config_reg->CONFIG_ABOTR = canREG1->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG1->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG1->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG1->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG1->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG1->TIOC; + config_reg->CONFIG_RIOC = canREG1->RIOC; + } +} +/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_018 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR28 */ +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG2->CTL; + config_reg->CONFIG_ES = canREG2->ES; + config_reg->CONFIG_BTR = canREG2->BTR; + config_reg->CONFIG_TEST = canREG2->TEST; + config_reg->CONFIG_ABOTR = canREG2->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG2->TIOC; + config_reg->CONFIG_RIOC = canREG2->RIOC; + } +} +/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_019 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR29 */ +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG3->CTL; + config_reg->CONFIG_ES = canREG3->ES; + config_reg->CONFIG_BTR = canREG3->BTR; + config_reg->CONFIG_TEST = canREG3->TEST; + config_reg->CONFIG_ABOTR = canREG3->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG3->TIOC; + config_reg->CONFIG_RIOC = canREG3->RIOC; + } +} + +/** @fn void can4GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN4 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_032 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR30 */ +void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN4_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN4_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN4_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN4_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN4_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN4_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN4_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN4_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN4_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN4_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN4_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG4->CTL; + config_reg->CONFIG_ES = canREG4->ES; + config_reg->CONFIG_BTR = canREG4->BTR; + config_reg->CONFIG_TEST = canREG4->TEST; + config_reg->CONFIG_ABOTR = canREG4->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG4->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG4->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG4->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG4->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG4->TIOC; + config_reg->CONFIG_RIOC = canREG4->RIOC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c new file mode 100644 index 00000000000..b8ebcd958af --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c @@ -0,0 +1,652 @@ +/** @file crc.c + * @brief CRC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "crc.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void crcInit(void) + * @brief Initializes the crc Driver + * + * This function initializes the crc module. + */ +/* SourceId : CRC_SourceId_001 */ +/* DesignId : CRC_DesignId_001 */ +/* Requirements : CONQ_CRC_SR2 */ +void crcInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b CRC1 */ + /** - Reset PSA*/ + crcREG1->CTRL0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ); + + /** - Pulling PSA out of reset */ + crcREG1->CTRL0 = 0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG1->CTRL2 |= ( uint32 ) 0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG1->INTS = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG1->PCOUNT_REG1 = 0x00000000U; + crcREG1->PCOUNT_REG2 = 0x00000000U; + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG1->SCOUNT_REG1 = 0x00000000U; + crcREG1->SCOUNT_REG2 = 0x00000000U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG1->WDTOPLD1 = 0x00000000U; + crcREG1->WDTOPLD2 = 0x00000000U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG1->BCTOPLD1 = 0x00000000U; + crcREG1->BCTOPLD2 = 0x00000000U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG1->REGL1 = 0x00000000U; + crcREG1->REGL2 = 0x00000000U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG1->REGH1 = 0x00000000U; + crcREG1->REGH2 = 0x00000000U; + + /** - Setup the Channel mode */ + crcREG1->CTRL2 |= ( uint32 ) ( CRC_FULL_CPU ) + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ); + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b CRC2 */ + + /** - Reset PSA*/ + crcREG2->CTRL0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ); + + /** - Pulling PSA out of reset */ + crcREG2->CTRL0 = 0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG2->CTRL2 |= ( uint32 ) 0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG2->INTS = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG2->PCOUNT_REG1 = 0U; + crcREG2->PCOUNT_REG2 = 0U; + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG2->SCOUNT_REG1 = 0U; + crcREG2->SCOUNT_REG2 = 0U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG2->WDTOPLD1 = 0U; + crcREG2->WDTOPLD2 = 0U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG2->BCTOPLD1 = 0U; + crcREG2->BCTOPLD2 = 0U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG2->REGL1 = 0U; + crcREG2->REGL2 = 0U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG2->REGH1 = 0U; + crcREG2->REGH2 = 0U; + + /** - Setup the Channel mode */ + crcREG2->CTRL2 |= ( uint32 ) ( CRC_FULL_CPU ) + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void crcSendPowerDown(crcBASE_t *crc) + * @brief Send crc power down + * @param[in] crc - crc module base address + * + * Send crc power down signal to enter into sleep mode + */ +/* SourceId : CRC_SourceId_002 */ +/* DesignId : CRC_DesignId_002 */ +/* Requirements : CONQ_CRC_SR3 */ +void crcSendPowerDown( crcBASE_t * crc ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + crc->CTRL1 |= 0x00000001U; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/** @fn void crcSignGen(crcBASE_t *crc,crcModConfig_t *param) + * @brief set the mode specific parameters for signature generation + * @param[in] crc - crc module base address + * @param[in] param - structure holding mode specific parameters + * Generate CRC signature + */ +/* SourceId : CRC_SourceId_003 */ +/* DesignId : CRC_DesignId_003 */ +/* Requirements : CONQ_CRC_SR4 */ +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + uint32 i = 0U, psaSigx; + volatile uint64 *ptr64, *psaSigx_ptr64; + ptr64 = param->src_data_pat; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 439 S MR:11.3 "Pointer Manupulation required to find offset" + */ + psaSigx = ( uint32 ) ( &crc->PSA_SIGREGL1 ) + + ( ( uint32 ) ( param->crc_channel ) * 0x40U ); + psaSigx_ptr64 = ( uint64 * ) ( psaSigx ); + + if( param->mode == CRC_AUTO ) + { + /** -do a channel reset + * -clear all interrupts by reading offset register + * -set CRC FAIL interrupt + * -set the pattern count and sector count + * -HW trigger in AUTO mode for CRC register update + * -copy from memory location to CRC register using DMA + * -copy from memory to PSA signature register using DMA + * -frame or block transfer,auto init + * -compare with crc reference + * -do a channel reset + */ + } + else if( param->mode == CRC_SEMI_CPU ) + { + /* after DMA does the transfer,CPU is invoked by CC interrupt to do signature + * verification */ + } + else if( param->mode == CRC_FULL_CPU ) + { + for( i = 0U; i < param->data_length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *psaSigx_ptr64 = *ptr64; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr64++; + } + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + } + else + { + /* Empty */ + } +} + +/** @fn void crcSetConfig(crcBASE_t *crc,crcConfig_t *param) + * @brief Set crc configurations + * @param[in] crc - crc module base address + * @param[in] param - structure for channel configuration + * Set Channel parameters + */ +/* SourceId : CRC_SourceId_004 */ +/* DesignId : CRC_DesignId_004 */ +/* Requirements : CONQ_CRC_SR5 */ +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + switch( param->crc_channel ) + { + case 0U: + crc->CTRL2 &= 0xFFFFFFFCU; + crc->CTRL0 |= 0x00000001U; + crc->CTRL0 &= 0xFFFFFFFEU; + crc->PCOUNT_REG1 = param->pcount; + crc->SCOUNT_REG1 = param->scount; + crc->WDTOPLD1 = param->wdg_preload; + crc->BCTOPLD1 = param->block_preload; + crc->CTRL2 |= param->mode; + break; + case 1U: + crc->CTRL2 &= 0xFFFFFCFFU; + crc->CTRL0 |= 0x00000100U; + crc->CTRL0 &= 0xFFFFFEFFU; + crc->PCOUNT_REG2 = param->pcount; + crc->SCOUNT_REG2 = param->scount; + crc->WDTOPLD2 = param->wdg_preload; + crc->BCTOPLD2 = param->block_preload; + crc->CTRL2 |= ( uint32 ) ( ( uint32 ) param->mode << 8U ); + break; + default: + break; + } + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/** @fn uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel) + * @brief get genearted sector signature + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get Sector signature value of selected channel + */ +/* SourceId : CRC_SourceId_005 */ +/* DesignId : CRC_DesignId_006 */ +/* Requirements : CONQ_CRC_SR7 */ +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ) +{ + uint64 status = 0U; + uint32 CRC_PSA_SECSIGREGH1 = crc->PSA_SECSIGREGH1; + uint32 CRC_PSA_SECSIGREGL1 = crc->PSA_SECSIGREGL1; + uint32 CRC_PSA_SECSIGREGH2 = crc->PSA_SECSIGREGH2; + uint32 CRC_PSA_SECSIGREGL2 = crc->PSA_SECSIGREGL2; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + switch( channel ) + { + case 0U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SECSIGREGL1 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SECSIGREGH1 ) ); + break; + case 1U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SECSIGREGL2 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SECSIGREGH2 ) ); + break; + default: + break; + } + return status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel) + * @brief get failed sector details + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get Failed Sector value of selected channel + */ +/* SourceId : CRC_SourceId_006 */ +/* DesignId : CRC_DesignId_007 */ +/* Requirements : CONQ_CRC_SR8 */ +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ) +{ + uint32 sector = 0U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + switch( channel ) + { + case 0U: + sector = crc->CURSEC_REG1; + break; + case 1U: + sector = crc->CURSEC_REG2; + break; + default: + break; + } + return sector; + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel) + * @brief get highest priority interrupt pending + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * + * Get pending Interrupts of selected channel + */ +/* SourceId : CRC_SourceId_007 */ +/* DesignId : CRC_DesignId_008 */ +/* Requirements : CONQ_CRC_SR9 */ +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + return crc->INT_OFFSET_REG; + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void crcChannelReset(crcBASE_t *crc,uint32 channel) + * @brief Reset the channel configurations + * @param[in] crc - crc module base address + * @param[in] channel-crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Reset configurations of the selected channels. + */ +/* SourceId : CRC_SourceId_008 */ +/* DesignId : CRC_DesignId_009 */ +/* Requirements : CONQ_CRC_SR10 */ +void crcChannelReset( crcBASE_t * crc, uint32 channel ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( channel == 0U ) + { + crc->CTRL0 |= ( uint32 ) ( ( uint32 ) 1U << 0U ); /** Reset the CRC channel */ + crc->CTRL0 &= ~( uint32 ) ( ( uint32 ) 1U << 0U ); /** Exit the reset */ + } + else if( channel == 1U ) + { + crc->CTRL0 |= ( uint32 ) ( ( uint32 ) 1U << 8U ); /** Reset the CRC channel */ + crc->CTRL0 &= ~( uint32 ) ( ( uint32 ) 1U << 8U ); /** Exit the reset */ + } + else + { + /** Empty */ + } + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn crcEnableNotification(crcBASE_t *crc, uint32 flags) + * @brief Enable interrupts + * @param[in] crc - crc module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * CRC_CH2_TO - channel3 timeout error, + * CRC_CH2_UR - channel3 underrun error, + * CRC_CH2_OR - channel3 overrun error, + * CRC_CH2_FAIL - channel3 crc error, + * CRC_CH2_CC - channel3 compression complete interrupt , + * CRC_CH1_TO - channel4 timeout error, + * CRC_CH1_UR - channel4 underrun error, + * CRC_CH1_OR - channel4 overrun error, + * CRC_CH1_FAIL - channel4 crc error, + * CRC_CH1_CC - channel4 compression complete interrupt + * + * Enable Notifications / Interrupts + */ +/* SourceId : CRC_SourceId_009 */ +/* DesignId : CRC_DesignId_010 */ +/* Requirements : CONQ_CRC_SR11 */ +void crcEnableNotification( crcBASE_t * crc, uint32 flags ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + crc->INTS = flags; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn crcDisableNotification(crcBASE_t *crc, uint32 flags) + * @brief Disable interrupts + * @param[in] crc - crc module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * CRC_CH2_TO - channel3 timeout error, + * CRC_CH2_UR - channel3 underrun error, + * CRC_CH2_OR - channel3 overrun error, + * CRC_CH2_FAIL - channel3 crc error, + * CRC_CH2_CC - channel3 compression complete interrupt , + * CRC_CH1_TO - channel4 timeout error, + * CRC_CH1_UR - channel4 underrun error, + * CRC_CH1_OR - channel4 overrun error, + * CRC_CH1_FAIL - channel4 crc error, + * CRC_CH1_CC - channel4 compression complete interrupt + * + * Disable Notifications / Interrupts + */ +/* SourceId : CRC_SourceId_010 */ +/* DesignId : CRC_DesignId_011 */ +/* Requirements : CONQ_CRC_SR12 */ +void crcDisableNotification( crcBASE_t * crc, uint32 flags ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + crc->INTR = flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetPSASig(crcBASE_t *crc,uint32 channel) + * @brief get genearted PSA signature used for FULL CPU mode + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get PSA signature used for FULL CPU mode of selected channel + */ +/* SourceId : CRC_SourceId_011 */ +/* DesignId : CRC_DesignId_005 */ +/* Requirements : CONQ_CRC_SR6 */ +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ) +{ + uint64 status = 0U; + uint32 CRC_PSA_SIGREGH1 = crc->PSA_SIGREGH1; + uint32 CRC_PSA_SIGREGL1 = crc->PSA_SIGREGL1; + uint32 CRC_PSA_SIGREGH2 = crc->PSA_SIGREGH2; + uint32 CRC_PSA_SIGREGL2 = crc->PSA_SIGREGL2; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + switch( channel ) + { + case 0U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SIGREGL1 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SIGREGH1 ) ); + break; + case 1U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SIGREGL2 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SIGREGH2 ) ); + break; + default: + break; + } + return status; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void crc1GetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CRC1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CRC_SourceId_012 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements : CONQ_CRC_SR15 */ +void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRL0 = CRC1_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC1_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC1_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC1_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC1_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC1_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC1_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC1_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC1_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC1_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC1_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC1_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTRL0 = crcREG1->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG1->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG1->CTRL2; + config_reg->CONFIG_INTS = crcREG1->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG1->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG1->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG1->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG1->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG1->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG1->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG1->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG1->BCTOPLD2; + } +} + +/** @fn void crc2GetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CRC2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CRC_SourceId_013 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements : CONQ_CRC_SR15 */ +void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRL0 = CRC2_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC2_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC2_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC2_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC2_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC2_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC2_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC2_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC2_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC2_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC2_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC2_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTRL0 = crcREG2->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG2->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG2->CTRL2; + config_reg->CONFIG_INTS = crcREG2->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG2->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG2->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG2->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG2->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG2->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG2->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG2->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG2->BCTOPLD2; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S new file mode 100644 index 00000000000..2721421d647 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S @@ -0,0 +1,167 @@ +/*-------------------------------------------------------------------------- + dabort.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +--------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + + +/*-------------------------------------------------------------------------------*/ +@ Run Memory Test + + .extern custom_dabort + .extern vHandleMemoryFault + .weak _dabort + .type _dabort, %function + +_dabort: + stmfd r13!, {r0 - r12, lr}@ push registers and link register on to stack + ldr r12, esmsr3 @ ESM Group3 status register + ldr r0, [r12] + tst r0, #0x8 @ check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM + bne ramErrorFound + tst r0, #0x20 @ check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM + bne ramErrorFound2 + +noRAMerror: + tst r0, #0x80 @ check if bit 7 is set, this indicates uncorrectable ECC error on ATCM + bne flashErrorFound + +/* Create a Exception Fault Stack similiar to the way it is created by the ARMvM + * architecture. The auto-pushed exception stack will contain: + * +-------+-----+----------+----------+------+ + * | R0-R3 | R12 | LR (R14) | PC (R15) | CPSR | + * +-------+-----+----------+----------+------+ + * + * <-------><----><---------><---------><-----> + * 4 1 1 1 1 +*/ +MemManage_Handler: + /* Pop the pushed values so we can re-do the stack the way we need it to be */ + LDMFD R13!, {R0 - R12, LR} + /* Abort exceptions increment the LR 0x8 after the fault-inducing instruction */ + SUB LR, #0x8 + + SRSDB SP!, #0x17 /* Save the pre-exception PC and CPSR */ + STMDB SP, { R0-R3, R12, LR }^ /* Save the user R0-R3, R12, and LR */ + SUB SP, SP, #0x18 /* Can't auto-increment SP with ^ operator */ + /* Need the SP in R0 */ + MOV R0, SP + + /* Call vHandleMemoryFault - This will modify the return state if necessary */ + BLX vHandleMemoryFault + + POP { R0-R3, R12, LR } /* Pop the original values off the stack */ + /* Return to the next instruction after the fault was generated */ + RFEIA SP! + +ramErrorFound: + ldr r1, ramctrl @ RAM control register for B0TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x08 + str r2, [r12] @ clear ESM group3 channel3 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + +ramErrorFound2: + ldr r1, ram2ctrl @ RAM control register for B1TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x20 + str r2, [r12] @ clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +ramErrorReal: + b ramErrorReal @ branch here forever as continuing operation is not recommended + +flashErrorFound: + ldr r1, flashbase + ldr r2, [r1, #0x6C] @ read FDIAGCTRL register + + mov r2, r2, lsr #16 + tst r2, #5 @ check if bits 19:16 are 5, this indicates diagnostic mode is enabled + beq flashErrorReal + mov r2, #1 + mov r2, r2, lsl #8 + + str r2, [r1, #0x1C] @ clear FEDACSTATUS error flag + + mov r2, #0x80 + str r2, [r12] @ clear ESM group3 flag for uncorrectable flash ECC error + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +flashErrorReal: + b flashErrorReal @ branch here forever as continuing operation is not recommended + +esmsr3: .word 0xFFFFF520 +ramctrl: .word 0xFFFFF800 +ram2ctrl: .word 0xFFFFF900 +ram1errstat: .word 0xFFFFF810 +ram2errstat: .word 0xFFFFF910 +flashbase: .word 0xFFF87000 + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c new file mode 100644 index 00000000000..4498fab0615 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c @@ -0,0 +1,455 @@ +/** @file dcc.c + * @brief DCC Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "dcc.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : DCC_SourceId_001 */ +/* DesignId : DCC_DesignId_001 */ +/* Requirements : CONQ_DCC_SR4 */ +/** @fn void dccInit(void) + * @brief Initializes the DCC Driver + * + * This function initializes the DCC module. + */ +void dccInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b DCC1 */ + + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 39204U; + + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 792U; + + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 742500U; + + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) DCC1_CNT1_PLL1; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable / Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0xAU << 4U ) | /** Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0xAU << 12U ); /** Done Interrupt */ + + /** @b initialize @b DCC2 */ + + /** DCC2 Clock0 Counter Seed value configuration */ + dccREG2->CNT0SEED = 0U; + + /** DCC2 Clock0 Valid Counter Seed value configuration */ + dccREG2->VALID0SEED = 0U; + + /** DCC2 Clock1 Counter Seed value configuration */ + dccREG2->CNT1SEED = 0U; + + /** DCC2 Clock1 Source 1 Select */ + dccREG2->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | /** DCC Enable Key */ + ( uint32 ) DCC2_CNT1_VCLK; /** DCC2 Clock Source 1 */ + + dccREG2->CNT0CLKSRC = ( uint32 ) DCC2_CNT0_OSCIN; /** DCC2 Clock Source 0 */ + + /** DCC2 Global Control register configuration */ + dccREG2->GCTRL = ( uint32 ) 0xAU | /** Enable DCC2 */ + ( uint32 ) ( ( uint32 ) 0xAU << 4U ) | /** Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0xAU << 12U ); /** Done Interrupt */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_002 */ +/* DesignId : DCC_DesignId_002 */ +/* Requirements : CONQ_DCC_SR5 */ +/** @fn void dccSetCounter0Seed(dccBASE_t *dcc, uint32 cnt0seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0seed - Clock Source 0 Counter seed value + * + * This function sets the seed value for Clock source 0 counter. + * + */ +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + dcc->CNT0SEED = cnt0seed; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_003 */ +/* DesignId : DCC_DesignId_003 */ +/* Requirements : CONQ_DCC_SR6 */ +/** @fn void dccSetTolerance(dccBASE_t *dcc, uint32 valid0seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] valid0seed - Clock Source 0 Counter tolerance value + * + * This function sets the seed value for Clock source 0 tolerance or + * valid counter. + * + */ +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + dcc->VALID0SEED = valid0seed; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_004 */ +/* DesignId : DCC_DesignId_004 */ +/* Requirements : CONQ_DCC_SR7 */ +/** @fn void dccSetCounter1Seed(dccBASE_t *dcc, uint32 cnt1seed) + * @brief Set dcc Clock source 1 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt1seed - Clock Source 1 Counter seed value + * + * This function sets the seed value for Clock source 1 counter. + * + */ +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + dcc->CNT1SEED = cnt1seed; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_005 */ +/* DesignId : DCC_DesignId_005 */ +/* Requirements : CONQ_DCC_SR8 */ +/** @fn void dccSetSeed(dccBASE_t *dcc, uint32 cnt0seed, uint32 valid0seed, uint32 + * cnt1seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0seed - Clock Source 0 Counter seed value. + * @param[in] valid0seed - Clock Source 0 Counter tolerance value. + * @param[in] cnt1seed - Clock Source 1 Counter seed value. + * + * This function sets the seed value for clock source 0, clock source 1 + * and tolerance counter. + * + */ +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + dcc->CNT0SEED = cnt0seed; + dcc->VALID0SEED = valid0seed; + dcc->CNT1SEED = cnt1seed; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_006 */ +/* DesignId : DCC_DesignId_006 */ +/* Requirements : CONQ_DCC_SR9 */ +/** @fn void dccSelectClockSource(dccBASE_t *dcc, uint32 cnt0_Clock_Source, uint32 + * cnt1_Clock_Source) + * @brief Set dcc counter Clock sources + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0_Clock_Source - Clock source for counter 0. + * @param[in] cnt1_Clock_Source - Clock source for counter 1. + * + * This function sets the dcc counter 0 and counter 1 clock sources. + * DCC must be disabled using dccDisable API before calling this + * function. + */ +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + dcc->CNT1CLKSRC = ( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | /** DCC Enable Key */ + ( uint32 ) ( cnt1_Clock_Source + & 0x0000000FU ) ); /* Configure Clock source 1 */ + dcc->CNT0CLKSRC = cnt0_Clock_Source; /* Configure Clock source 0 */ + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_007 */ +/* DesignId : DCC_DesignId_007 */ +/* Requirements : CONQ_DCC_SR10 */ +/** @fn void dccEnable(dccBASE_t *dcc) + * @brief Enable dcc module to begin counting + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * This function enables the dcc counters to begin counting. + * + */ +void dccEnable( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( dcc->GCTRL & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_008 */ +/* DesignId : DCC_DesignId_008 */ +/* Requirements : CONQ_DCC_SR21 */ +/** @fn void dccDisable(dccBASE_t *dcc) + * @brief Make selected dcc module to stop counting + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * This function stops the dcc counters from counting. + * + */ +void dccDisable( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( dcc->GCTRL & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_009 */ +/* DesignId : DCC_DesignId_009 */ +/* Requirements : CONQ_DCC_SR12 */ +/** @fn uint32 dccGetErrStatus(dccBASE_t *dcc) + * @brief Get error status from selected dcc module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * @return The Error status of selected dcc module + * + * Returns the error status of selected dcc module. + * + */ +uint32 dccGetErrStatus( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + return ( dcc->STAT & 0x00000001U ); +} + +/* SourceId : DCC_SourceId_010 */ +/* DesignId : DCC_DesignId_010 */ +/* Requirements : CONQ_DCC_SR13 */ +/** @fn void dccEnableNotification(dccBASE_t *dcc, uint32 notification) + * @brief Enable notification of selected DCC module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] notification Select notification of DCC module: + * - dccNOTIFICATION_DONE: DCC DONE notification + * - dccNOTIFICATION_ERROR: DCC ERROR notification + * + * This function will enable the selected notification of a DCC module. + * It is possible to enable multiple notifications masked. + */ + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( ( dcc->GCTRL & 0xFFFF0F0FU ) | notification ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_011 */ +/* DesignId : DCC_DesignId_011 */ +/* Requirements : CONQ_DCC_SR14 */ +/** @fn void dccDisableNotification(dccBASE_t *dcc, uint32 notification) + * @brief Disable notification of selected DCC module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] notification Select notification of DCC module: + * - dccNOTIFICATION_DONE: DCC DONE notification + * - dccNOTIFICATION_ERROR: DCC ERROR notification + * + * This function will enable the selected notification of a DCC module. + * It is possible to enable multiple notifications masked. + */ + +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( ( dcc->GCTRL & 0xFFFF0F0FU ) | ( ( ~notification ) & 0x0000F0F0U ) ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_012 */ +/* DesignId : DCC_DesignId_012 */ +/* Requirements : CONQ_DCC_SR18 */ +/** @fn void dcc1GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCTRL = DCC1_GCTRL_CONFIGVALUE; + config_reg->CONFIG_CNT0SEED = DCC1_CNT0SEED_CONFIGVALUE; + config_reg->CONFIG_VALID0SEED = DCC1_VALID0SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1SEED = DCC1_CNT1SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1CLKSRC = DCC1_CNT1CLKSRC_CONFIGVALUE; + config_reg->CONFIG_CNT0CLKSRC = DCC1_CNT0CLKSRC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + config_reg->CONFIG_GCTRL = dccREG1->GCTRL; + config_reg->CONFIG_CNT0SEED = dccREG1->CNT0SEED; + config_reg->CONFIG_VALID0SEED = dccREG1->VALID0SEED; + config_reg->CONFIG_CNT1SEED = dccREG1->CNT1SEED; + config_reg->CONFIG_CNT1CLKSRC = dccREG1->CNT1CLKSRC; + config_reg->CONFIG_CNT0CLKSRC = dccREG1->CNT0CLKSRC; + } +} + +/* SourceId : DCC_SourceId_013 */ +/* DesignId : DCC_DesignId_012 */ +/* Requirements : CONQ_DCC_SR19 */ +/** @fn void dcc2GetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCTRL = DCC2_GCTRL_CONFIGVALUE; + config_reg->CONFIG_CNT0SEED = DCC2_CNT0SEED_CONFIGVALUE; + config_reg->CONFIG_VALID0SEED = DCC2_VALID0SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1SEED = DCC2_CNT1SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1CLKSRC = DCC2_CNT1CLKSRC_CONFIGVALUE; + config_reg->CONFIG_CNT0CLKSRC = DCC2_CNT0CLKSRC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + config_reg->CONFIG_GCTRL = dccREG2->GCTRL; + config_reg->CONFIG_CNT0SEED = dccREG2->CNT0SEED; + config_reg->CONFIG_VALID0SEED = dccREG2->VALID0SEED; + config_reg->CONFIG_CNT1SEED = dccREG2->CNT1SEED; + config_reg->CONFIG_CNT1CLKSRC = dccREG2->CNT1CLKSRC; + config_reg->CONFIG_CNT0CLKSRC = dccREG2->CNT0CLKSRC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c new file mode 100644 index 00000000000..b5507af5a21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c @@ -0,0 +1,1062 @@ +/** @file ecap.c + * @brief ECAP Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "ecap.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void ecapInit(void) + * @brief Initializes the eCAP Driver + * + * This function initializes the eCAP module. + */ +/* SourceId : ECAP_SourceId_001 */ +/* DesignId : ECAP_DesignId_001 */ +/* Requirements : CONQ_ECAP_SR2 */ +void ecapInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** @b initialize @b ECAP1 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG1 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG1->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG1->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP2 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG2 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG2->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG2->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP3 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG3 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG3->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG3->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP4 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG4 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG4->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG4->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP5 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG5 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG5->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG5->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP6 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG6 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG6->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG6->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ +} + +/** @fn void ecapSetCounter(ecapBASE_t *ecap, uint32 value) + * @brief Set Time-Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] value 16-bit Counter value + * + * This function sets the Time-Stamp Counter register + */ +/* SourceId : ECAP_SourceId_002 */ +/* DesignId : ECAP_DesignId_002 */ +/* Requirements : CONQ_ECAP_SR3 */ +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ) +{ + ecap->TSCTR = value; +} + +/** @fn void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase) + * @brief Enable counter register load from phase register when a sync event occurs + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] phase Counter value to be loaded when a sync event occurs + * + * This function enables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_003 */ +/* DesignId : ECAP_DesignId_003 */ +/* Requirements : CONQ_ECAP_SR6 */ +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ) +{ + ecap->ECCTL2 |= 0x0020U; + ecap->CTRPHS = phase; +} + +/** @fn void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap) + * @brief Disable counter register load from phase register when a sync event occurs + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_004 */ +/* DesignId : ECAP_DesignId_004 */ +/* Requirements : CONQ_ECAP_SR7 */ +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0020U; +} + +/** @fn void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale) + * @brief Set Event prescaler + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] prescale Event Filter prescale select + * (ecapPrescale_By_1..ecapPrescale_By_62) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_005 */ +/* DesignId : ECAP_DesignId_005 */ +/* Requirements : CONQ_ECAP_SR8 */ +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) 0x3E00U; + ecap->ECCTL1 |= ( uint16 ) prescale; +} + +/** @fn void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 1 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 1 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 1 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 1 + */ +/* SourceId : ECAP_SourceId_006 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 0U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 0U ); +} + +/** @fn void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 2 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 2 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 2 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 2 + */ +/* SourceId : ECAP_SourceId_007 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 2U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 2U ); +} + +/** @fn void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 3 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 3 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 3 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 3 + */ +/* SourceId : ECAP_SourceId_008 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 4U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 4U ); +} + +/** @fn void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 4 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 4 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 4 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 4 + */ +/* SourceId : ECAP_SourceId_009 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 6U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 6U ); +} + +/** @fn void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t mode, ecapEvent_t event) + * @brief Set Capture mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] capMode Capture mode + * - CONTINUOUS + * - ONE_SHOT + * @param[in] event Stop/Wrap value + * - CAPTURE_EVENT1: Stop after Capture Event 1 in one-shot mode / + * Wrap after Capture Event 1 in continuous mode + * - CAPTURE_EVENT2: Stop after Capture Event 2 in one-shot mode / + * Wrap after Capture Event 2 in continuous mode. + * - CAPTURE_EVENT3: Stop after Capture Event 3 in one-shot mode / + * Wrap after Capture Event 3 in continuous mode. + * - CAPTURE_EVENT4: Stop after Capture Event 4 in one-shot mode / + * Wrap after Capture Event 4 in continuous mode. + * + * This function sets the capture mode and stop/wrap value + */ +/* SourceId : ECAP_SourceId_010 */ +/* DesignId : ECAP_DesignId_007 */ +/* Requirements : CONQ_ECAP_SR10 */ +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ) +{ + ecap->ECCTL2 &= 0xFFF8U; + ecap->ECCTL2 |= ( ( uint16 ) ( ( uint16 ) event << 1U ) | ( uint16 ) capMode ); +} + +/** @fn void ecapEnableCapture(ecapBASE_t *ecap) + * @brief Enable Capture + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function enable loading of CAP1-4 registers on a capture event + */ +/* SourceId : ECAP_SourceId_011 */ +/* DesignId : ECAP_DesignId_008 */ +/* Requirements : CONQ_ECAP_SR11 */ +void ecapEnableCapture( ecapBASE_t * ecap ) +{ + ecap->ECCTL1 |= 0x0100U; +} + +/** @fn void ecapDisableCapture(ecapBASE_t *ecap) + * @brief Disable Capture + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disable loading of CAP1-4 registers on a capture event + */ +/* SourceId : ECAP_SourceId_012 */ +/* DesignId : ECAP_DesignId_009 */ +/* Requirements : CONQ_ECAP_SR12 */ +void ecapDisableCapture( ecapBASE_t * ecap ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) 0x0100U; +} + +/** @fn void ecapStartCounter(ecapBASE_t *ecap) + * @brief Start Time Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function starts Time Stamp Counter + */ +/* SourceId : ECAP_SourceId_013 */ +/* DesignId : ECAP_DesignId_010 */ +/* Requirements : CONQ_ECAP_SR4 */ +void ecapStartCounter( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 |= 0x0010U; +} + +/** @fn void ecapStopCounter(ecapBASE_t *ecap)) + * @brief Stop Time Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function stops Time Stamp Counter + */ +/* SourceId : ECAP_SourceId_014 */ +/* DesignId : ECAP_DesignId_011 */ +/* Requirements : CONQ_ECAP_SR5 */ +void ecapStopCounter( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0010U; +} + +/** @fn void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc) + * @brief Set the source of Sync-out signal + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] syncOutSrc Sync-Out Select + * - SyncOut_SyncIn: Sync In used for Sync Out + * - SyncOut_CTRPRD: CTR = PRD used for Sync Out + * - SyncOut_None : Disables Sync Out + * + * This function sets the source of Sync-out signal + */ +/* SourceId : ECAP_SourceId_015 */ +/* DesignId : ECAP_DesignId_012 */ +/* Requirements : CONQ_ECAP_SR13 */ +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x00C0U; + ecap->ECCTL2 |= syncOutSrc; +} + +/** @fn void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint16 + * period, uint16 duty) + * @brief Enable APWM mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] pwmPolarity APWM output polarity select + * - ACTIVE_HIGH + * - ACTIVE_LOW + * @param[in] period APWM period (in terms of ticks) + * @param[in] duty APWM duty (in terms of ticks) + * + * This function enables and sets APWM mode + */ +/* SourceId : ECAP_SourceId_016 */ +/* DesignId : ECAP_DesignId_013 */ +/* Requirements : CONQ_ECAP_SR14 */ +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0400U; + ecap->ECCTL2 |= ( uint16 ) ( ( uint16 ) pwmPolarity << 10U ) + | ( uint16 ) ( ( uint16 ) 1U << 9U ); + ecap->CAP1 = period - 1U; + ecap->CAP2 = duty; +} + +/** @fn void ecapDisableAPWMMode(ecapBASE_t *ecap) + * @brief Disable APWM mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disables APWM mode + */ +/* SourceId : ECAP_SourceId_017 */ +/* DesignId : ECAP_DesignId_014 */ +/* Requirements : CONQ_ECAP_SR15 */ +void ecapDisableAPWMMode( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0200U; +} + +/** @fn void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) + * @brief Enable eCAP interrupt sources + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] interrupts eCAP interrupt sources + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function enables eCAP interrupt sources + */ +/* SourceId : ECAP_SourceId_018 */ +/* DesignId : ECAP_DesignId_015 */ +/* Requirements : CONQ_ECAP_SR16 */ +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ) +{ + ecap->ECEINT |= interrupts; +} + +/** @fn void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) + * @brief Disables eCAP interrupt sources + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] interrupts eCAP interrupt sources + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function disables eCAP interrupt sources + */ +/* SourceId : ECAP_SourceId_019 */ +/* DesignId : ECAP_DesignId_016 */ +/* Requirements : CONQ_ECAP_SR17 */ +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ) +{ + ecap->ECEINT &= ( uint16 ) ~( uint16 ) interrupts; +} + +/** @fn uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events) + * @brief Return Event status + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] events eCAP events + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_Global : Denotes Capture global interrupt + * - ecapInt_All : Denotes All interrupts + * @return Event status + * + * This function returns the event status + */ +/* SourceId : ECAP_SourceId_020 */ +/* DesignId : ECAP_DesignId_017 */ +/* Requirements : CONQ_ECAP_SR18 */ +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ) +{ + return ( ecap->ECFLG & events ); +} + +/** @fn void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events) + * @brief Clear Event status + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] events eCAP events + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_Global : Denotes Capture global interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function clears the event status + */ +/* SourceId : ECAP_SourceId_021 */ +/* DesignId : ECAP_DesignId_018 */ +/* Requirements : CONQ_ECAP_SR19 */ +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ) +{ + ecap->ECCLR = events; +} + +/** @fn void uint32 ecapGetCAP1(ecapBASE_t *ecap) + * @brief Get CAP1 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 1 value + */ +/* SourceId : ECAP_SourceId_022 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP1( ecapBASE_t * ecap ) +{ + return ecap->CAP1; +} + +/** @fn void uint32 ecapGetCAP2(ecapBASE_t *ecap) + * @brief Get CAP2 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 2 value + */ +/* SourceId : ECAP_SourceId_023 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP2( ecapBASE_t * ecap ) +{ + return ecap->CAP2; +} + +/** @fn void uint32 ecapGetCAP3(ecapBASE_t *ecap) + * @brief Get CAP3 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 3 value + */ +/* SourceId : ECAP_SourceId_024 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP3( ecapBASE_t * ecap ) +{ + return ecap->CAP3; +} + +/** @fn void uint32 ecapGetCAP4(ecapBASE_t *ecap) + * @brief Get CAP4 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 4 value + */ +/* SourceId : ECAP_SourceId_025 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP4( ecapBASE_t * ecap ) +{ + return ecap->CAP4; +} + +/** @fn void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_026 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP1_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP1_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP1_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP1_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG1->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG1->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG1->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG1->ECEINT; + } +} + +/** @fn void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_027 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP2_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP2_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP2_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP2_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG2->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG2->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG2->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG2->ECEINT; + } +} + +/** @fn void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_028 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP3_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP3_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP3_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP3_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG3->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG3->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG3->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG3->ECEINT; + } +} + +/** @fn void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_029 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP4_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP4_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP4_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP4_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG4->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG4->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG4->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG4->ECEINT; + } +} + +/** @fn void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_030 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP5_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP5_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP5_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP5_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG5->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG5->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG5->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG5->ECEINT; + } +} + +/** @fn void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_031 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP6_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP6_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP6_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP6_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG6->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG6->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG6->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG6->ECEINT; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c new file mode 100644 index 00000000000..fb35e4511fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c @@ -0,0 +1,1965 @@ +/** + * \file emac.c + * + * \brief EMAC APIs. + * + * This file contains the device abstraction layer APIs for EMAC. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emac.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Defining interface for all the emac instances */ +hdkif_t hdkif_data[ MAX_EMAC_INSTANCE ]; +/*SAFETYMCUSW 25 D MR:8.7 "Statically allocated memory needs to be available to + * entire application." */ +static uint8_t pbuf_array[ MAX_RX_PBUF_ALLOC ][ MAX_TRANSFER_UNIT ]; +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define EMAC_CONTROL_RESET ( 0x01U ) +#define EMAC_SOFT_RESET ( 0x01U ) +#define EMAC_MAX_HEADER_DESC ( 8U ) +#define EMAC_UNICAST_DISABLE ( 0xFFU ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Enables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_001 */ +/* DesignId : ETH_DesignId_001*/ +/* Requirements : CONQ_EMAC_SR9 */ +void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_TXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnTXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_002 */ +/* DesignId : ETH_DesignId_002*/ +/* Requirements : CONQ_EMAC_SR10 */ +void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnTXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Enables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be enabled. + * \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_003 */ +/* DesignId : ETH_DesignId_003*/ +/* Requirements : CONQ_EMAC_SR11 */ +void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnRXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be disabled. + * \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_004 */ +/* DesignId : ETH_DesignId_004*/ +/* Requirements : CONQ_EMAC_SR12 */ +void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnRXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} +/** + * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or + * 100 Mbps + * + * \param emacBase Base address of the EMAC Module registers. + * \param speed speed for setting. + * speed can take the following values. \n + * EMAC_RMIISPEED_10MBPS - 10 Mbps \n + * EMAC_RMIISPEED_100MBPS - 100 Mbps. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_005 */ +/* DesignId : ETH_DesignId_005*/ +/* Requirements : CONQ_EMAC_SR23 */ +void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RMIISPEED ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= speed; +} +/* SourceId : ETH_SourceId_006 */ +/* DesignId : ETH_DesignId_006*/ +/* Requirements : CONQ_EMAC_SR21 */ +/** + * \brief This API set the GMII bit, RX and TX are enabled for receive and transmit. + * Note: This is not the API to enable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +void EMACMIIEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_GMIIEN; +} + +/** + * \brief This API clears the GMII bit, Rx and Tx are held in reset. + * Note: This is not the API to disable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_007 */ +/* DesignId : ETH_DesignId_007*/ +/* Requirements : CONQ_EMAC_SR22 */ +void EMACMIIDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); +} + +/** + * \brief This API sets the duplex mode of operation(full/half) for MAC. + * + * \param emacBase Base address of the EMAC Module registers. + * \param duplexMode duplex mode of operation. + * duplexMode can take the following values. \n + * EMAC_DUPLEX_FULL - Full Duplex \n + * EMAC_DUPLEX_HALF - Half Duplex. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_008 */ +/* DesignId : ETH_DesignId_008*/ +/* Requirements : CONQ_EMAC_SR29 */ +void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_FULLDUPLEX ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= duplexMode; +} + +/** + * \brief API to enable the transmit in the TX Control Register + * After the transmit is enabled, any write to TXHDP of + * a channel will start transmission + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_009 */ +/* DesignId : ETH_DesignId_009*/ +/* Requirements : CONQ_EMAC_SR30 */ +void EMACTxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXEN; +} + +/** + * \brief API to disable the transmit in the TX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_010 */ +/* DesignId : ETH_DesignId_010*/ +/* Requirements : CONQ_EMAC_SR31 */ +void EMACTxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXDIS; +} + +/** + * \brief API to enable the receive in the RX Control Register + * After the receive is enabled, and write to RXHDP of + * a channel, the data can be received in the destination + * specified by the corresponding RX buffer descriptor. + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_011*/ +/* DesignId : ETH_DesignId_011*/ +/* Requirements : CONQ_EMAC_SR32 */ +void EMACRxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXEN; +} + +/** + * \brief API to disable the receive in the RX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_012*/ +/* DesignId : ETH_DesignId_012*/ +/* Requirements : CONQ_EMAC_SR33 */ +void EMACRxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXDIS; +} + +/** + * \brief API to write the TX HDP register. If transmit is enabled, + * write to the TX HDP will immediately start transmission. + * The data will be taken from the buffer pointer of the TX buffer + * descriptor written to the TX HDP + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the TX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_013*/ +/* DesignId : ETH_DesignId_013*/ +/* Requirements : CONQ_EMAC_SR17 */ +void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXHDP( channel ) ) = descHdr; +} + +/** + * \brief API to write the RX HDP register. If receive is enabled, + * write to the RX HDP will enable data reception to point to + * the corresponding RX buffer descriptor's buffer pointer. + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the RX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_014 */ +/* DesignId : ETH_DesignId_014*/ +/* Requirements : CONQ_EMAC_SR18 */ +void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXHDP( channel ) ) = descHdr; +} + +/** + * \brief This API Initializes the EMAC and EMAC Control modules. The + * EMAC Control module is reset, the CPPI RAM is cleared. also, + * all the interrupts are disabled. This API does not enable any + * interrupt or operation of the EMAC. + * + * \param emacCtrlBase Base Address of the EMAC Control module + * registers.\n + * \param emacBase Base address of the EMAC module registers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_015 */ +/* DesignId : ETH_DesignId_015*/ +/* Requirements : CONQ_EMAC_SR1 */ +void EMACInit( uint32 emacCtrlBase, uint32 emacBase ) +{ + uint32 cnt; + + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + } /* Wait */ + + /* Reset the EMAC Module. This clears the CPPI RAM also */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + } /* Wait */ + + HWREG( emacBase + EMAC_MACCONTROL ) = 0U; + HWREG( emacBase + EMAC_RXCONTROL ) = 0U; + HWREG( emacBase + EMAC_TXCONTROL ) = 0U; + + /* Initialize all the header descriptor pointer registers */ + for( cnt = 0U; cnt < EMAC_MAX_HEADER_DESC; cnt++ ) + { + HWREG( emacBase + EMAC_RXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXFREEBUFFER( cnt ) ) = 0xFFU; + } + /* Clear the interrupt enable for all the channels */ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) = 0xFFU; + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) = 0xFFU; + + HWREG( emacBase + EMAC_MACHASH1 ) = 0U; + HWREG( emacBase + EMAC_MACHASH2 ) = 0U; + + HWREG( emacBase + EMAC_RXBUFFEROFFSET ) = 0U; +} + +/** + * \brief Sets the MAC Address in MACSRCADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_016 */ +/* DesignId : ETH_DesignId_016*/ +/* Requirements : CONQ_EMAC_SR5 */ +void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ) +{ + HWREG( emacBase + EMAC_MACSRCADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACSRCADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) ); +} + +/** + * \brief Sets the MAC Address in MACADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param matchFilt Match or Filter + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * matchFilt can take the following values \n + * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match + * or filter incoming packet. \n + * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n + * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_017 */ +/* DesignId : ETH_DesignId_017*/ +/* Requirements : CONQ_EMAC_SR6 */ +void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ) +{ + HWREG( emacBase + EMAC_MACINDEX ) = channel; + + HWREG( emacBase + EMAC_MACADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) + | matchFilt | ( channel << 16U ) ); +} + +/** + * \brief Acknowledges an interrupt processed to the EMAC Control Core. + * + * \param emacBase Base Address of the EMAC module registers. + * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control + * module. + * eoiFlag can take the following values \n + * EMAC_INT_CORE0_TX - Core 0 TX Interrupt + * EMAC_INT_CORE1_TX - Core 1 TX Interrupt + * EMAC_INT_CORE2_TX - Core 2 TX Interrupt + * EMAC_INT_CORE0_RX - Core 0 RX Interrupt + * EMAC_INT_CORE1_RX - Core 1 RX Interrupt + * EMAC_INT_CORE2_RX - Core 2 RX Interrupt + * \return None + * + **/ +/* SourceId : ETH_SourceId_018 */ +/* DesignId : ETH_DesignId_018*/ +/* Requirements : CONQ_EMAC_SR16 */ +void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ) +{ + /* Acknowledge the EMAC Control Core */ + HWREG( emacBase + EMAC_MACEOIVECTOR ) = eoiFlag; +} + +/** + * \brief Writes the the TX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_019 */ +/* DesignId : ETH_DesignId_019*/ +/* Requirements : CONQ_EMAC_SR41 */ +void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_TXCP( channel ) ) = comPtr; +} + +/** + * \brief Writes the the RX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_020 */ +/* DesignId : ETH_DesignId_020*/ +/* Requirements : CONQ_EMAC_SR42 */ +void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_RXCP( channel ) ) = comPtr; +} + +/** + * \brief Enables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_021 */ +/* DesignId : ETH_DesignId_021*/ +/* Requirements : CONQ_EMAC_SR43 */ +void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + + HWREG( + emacBase + + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXBROADEN + | ( ( uint32 ) channel + << ( uint32 ) EMAC_RXMBPENABLE_RXBROADCH_SHIFT ) ); +} + +/** + * \brief Disables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_022 */ +/* DesignId : ETH_DesignId_022*/ +/* Requirements : CONQ_EMAC_SR44 */ +void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + /* Broadcast Frames are filtered. */ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADEN ); +} + +/** + * \brief Enables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_023 */ +/* DesignId : ETH_DesignId_023*/ +/* Requirements : CONQ_EMAC_SR45 */ +void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXMULTEN + | ( channel ) ); +} + +/** + * \brief Disables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_024 */ +/* DesignId : ETH_DesignId_024*/ +/* Requirements : CONQ_EMAC_SR46 */ +void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTEN ); +} + +/** + * \brief Enables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_025 */ +/* DesignId : ETH_DesignId_025*/ +/* Requirements : CONQ_EMAC_SR7 */ +void EMACRxUnicastSet( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXUNICASTSET ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_026 */ +/* DesignId : ETH_DesignId_026*/ +/* Requirements : CONQ_EMAC_SR8 */ +void EMACRxUnicastClear( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXUNICASTCLEAR ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Set the free buffers for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param nBuf Number of free buffers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_027 */ +/* DesignId : ETH_DesignId_027*/ +/* Requirements : CONQ_EMAC_SR15 */ +void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ) +{ + HWREG( emacBase + EMAC_RXFREEBUFFER( channel ) ) = nBuf; +} + +/** + * \brief Gets the interrupt vectors of EMAC, which are pending + * + * \param emacBase Base Address of the EMAC module registers. + * + * \return Vectors + * + **/ +/* SourceId : ETH_SourceId_028 */ +/* DesignId : ETH_DesignId_028*/ +/* Requirements : CONQ_EMAC_SR14 */ +uint32 EMACIntVectorGet( uint32 emacBase ) +{ + return ( HWREG( emacBase + EMAC_MACINVECTOR ) ); +} + +/** + * Function to setup the instance parameters inside the interface + * @param hdkif Network interface structure + * @return none. + */ +/* SourceId : ETH_SourceId_029 */ +/* DesignId : ETH_DesignId_029*/ +/* Requirements : CONQ_EMAC_SR3 */ +void EMACInstConfig( hdkif_t * hdkif ) +{ + hdkif->emac_base = EMAC_0_BASE; + hdkif->emac_ctrl_base = EMAC_CTRL_0_BASE; + hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE; + hdkif->mdio_base = MDIO_BASE; + hdkif->phy_addr = 1U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker. + */ + hdkif->phy_autoneg = &PhyAutoNegotiate; + hdkif->phy_partnerability = &PhyPartnerAbilityGet; +} + +/** + * Function to setup the link. AutoNegotiates with the phy for link + * setup and set the EMAC with the result of autonegotiation. + * @param hdkif Network interface structure. + * @return ERR_OK if everything passed + * others if not passed + */ +/* SourceId : ETH_SourceId_030 */ +/* DesignId : ETH_DesignId_030*/ +/* Requirements : CONQ_EMAC_SR4 */ +uint32 EMACLinkSetup( hdkif_t * hdkif ) +{ + uint32 linkstat = EMAC_ERR_CONNECT; + uint16 partnr_ablty = 0U; + uint32 phyduplex = EMAC_DUPLEX_HALF; + volatile uint32 delay = 0xFFFFFU; + + if( PhyAutoNegotiate( ( uint32 ) hdkif->mdio_base, + ( uint32 ) hdkif->phy_addr, + ( uint16 ) ( ( uint16 ) DP83640_100BTX + | ( uint16 ) DP83640_100BTX_FD + | ( uint16 ) DP83640_10BT + | ( uint16 ) DP83640_10BT_FD ) ) + == TRUE ) + { + linkstat = EMAC_ERR_OK; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA + * checker (due to use of & ?) */ + ( void ) PhyPartnerAbilityGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_ablty ); + + /* Check for 100 Mbps and duplex capability */ + if( ( partnr_ablty & DP83640_100BTX_FD ) != 0U ) + { + phyduplex = EMAC_DUPLEX_FULL; + } + } + + else + { + linkstat = EMAC_ERR_CONNECT; + } + + /* Set the EMAC with the negotiation results if it is successful */ + if( linkstat == EMAC_ERR_OK ) + { + EMACDuplexSet( hdkif->emac_base, phyduplex ); + } + + /* Wait for the MII to settle down */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + delay--; + } + + return linkstat; +} + +/** + * \brief Perform a transmit queue teardown, that is, transmission is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_031 */ +/* DesignId : ETH_DesignId_031*/ +/* Requirements : CONQ_EMAC_SR34 */ +void EMACTxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform a receive queue teardown, that is, reception is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_032 */ +/* DesignId : ETH_DesignId_032*/ +/* Requirements : CONQ_EMAC_SR35 */ +void EMACRxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform multicast frame filtering using the MAC Hash Registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param hashTable The hash table which specifies which bits are to be accepted. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_033 */ +/* DesignId : ETH_DesignId_033*/ +/* Requirements : CONQ_EMAC_SR38 */ +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ) +{ + HWREG( emacBase + EMAC_MACHASH1 ) = ( uint32 ) ( hashTable & 0xFFFFFFFFU ); + HWREG( emacBase + EMAC_MACHASH2 ) = ( uint32 ) ( hashTable >> 32U ); +} + +/** + * \brief Sets the Transmit Queue Priority type in the MACCONTROL Register + * + * \param emacBase Base Address of the EMAC module registers. + * \param txPType The Transmit Queue Priority Type. + * 0 results in a round-robin scheme being used to select the next + *channel, while 1 results in a fixed-priority scheme( channel 7 highest priority). + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_034 */ +/* DesignId : ETH_DesignId_034*/ +/* Requirements : CONQ_EMAC_SR39 */ +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ) +{ + /* 1- The queue uses a fixed-priority (channel 7 highest priority) scheme */ + if( txPType == 1U ) + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXPTYPE; + } + else + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + } +} + +/** + * \brief Performs a soft reset of the EMAC and EMAC Control Modules. + * + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_035 */ +/* DesignId : ETH_DesignId_035*/ +/* Requirements : CONQ_EMAC_SR40 */ +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ) +{ + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + /* Wait for the reset to complete */ + } + + /* Reset the EMAC Module. */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + /* Wait for the Reset to complete */ + } +} + +/** + * \brief Enable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_036 */ +/* DesignId : ETH_DesignId_036*/ +/* Requirements : CONQ_EMAC_SR51 */ +void EMACEnableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_CMDIDLE; +} + +/** + * \brief Disable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_037 */ +/* DesignId : ETH_DesignId_037*/ +/* Requirements : CONQ_EMAC_SR52 */ +void EMACDisableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_CMDIDLE ) ); +} + +/** + * \brief Enables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_038 */ +/* DesignId : ETH_DesignId_038*/ +/* Requirements : CONQ_EMAC_SR70 */ +void EMACEnableLoopback( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + uint32 GMIIENval = 0U; + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Enable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_LOOPBACK; + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Disables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_039 */ +/* DesignId : ETH_DesignId_039*/ +/* Requirements : CONQ_EMAC_SR71 */ +void EMACDisableLoopback( uint32 emacBase ) +{ + uint32 GMIIENval = 0U; + + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Disable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_LOOPBACK ); + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Enable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_040 */ +/* DesignId : ETH_DesignId_040*/ +/* Requirements : CONQ_EMAC_SR24 */ +void EMACTxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXFLOWEN; +} + +/** + * \brief Disable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_041 */ +/* DesignId : ETH_DesignId_041*/ +/* Requirements : CONQ_EMAC_SR25 */ +void EMACTxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_TXFLOWEN ); +} + +/** + * \brief Enable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_042 */ +/* DesignId : ETH_DesignId_042*/ +/* Requirements : CONQ_EMAC_SR26 */ +void EMACRxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_RXBUFFERFLOWEN; +} + +/** + * \brief Disable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_043 */ +/* DesignId : ETH_DesignId_043*/ +/* Requirements : CONQ_EMAC_SR27 */ +void EMACRxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RXBUFFERFLOWEN ); +} + +/** + * \brief Performs byte inversion of 32-bit data to counteract swizzling performed by + *CPU during reads of CPPI RAM.(Due to BE8 format) + * + * \param word The 32-bit word to be swizzled. + * \return uint32 + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : CONQ_EMAC_SR73 */ +uint32 EMACSwizzleData( uint32 word ) +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + return word; +#else + return ( ( ( word << 24U ) & 0xFF000000U ) | ( ( word << 8U ) & 0x00FF0000U ) + | ( ( word >> 8U ) & 0x0000FF00U ) | ( ( word >> 24U ) & 0x000000FFU ) ); +#endif +} + +/** + * \brief Receive flow threshold. These bits contain the threshold value for issuing + *flow control on incoming frames for channel n (when enabled). + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param threshold threshold value for issuing flow control on incoming frames for + *the given channel \return None + * + **/ +/* SourceId : ETH_SourceId_044 */ +/* DesignId : ETH_DesignId_044*/ +/* Requirements : CONQ_EMAC_SR28 */ +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ) +{ + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) &= ( 0x0U ); + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) |= threshold; +} + +/** + * \brief This function reads the contents of the 36 network statistics + *registers that are present in the module. \param emacBase Base Address of the EMAC + *module registers. \param statRegNo The number of the register with RXGOODFRAMES + *(Offset= 0x200) being 0. Refer the Technical Reference Manual for the list of registers + *and their contents. \return uint32 + **/ +/* SourceId : ETH_SourceId_045 */ +/* DesignId : ETH_DesignId_045*/ +/* Requirements : CONQ_EMAC_SR47 */ +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ) +{ + return HWREG( emacBase + EMAC_NETSTATREGS( statRegNo ) ); +} + +/** + * \brief Function to read values of Transmit Interrupt Status registers + *(TXINTSTATMASKED and TXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param txintstat pointer to the emac_tx_int_status Structure that will store the + *register values that have been read \return None + * + **/ +/* SourceId : ETH_SourceId_046 */ +/* DesignId : ETH_DesignId_046*/ +/* Requirements : CONQ_EMAC_SR36 */ +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ) +{ + txintstat->intstatmasked = ( HWREG( emacBase + EMAC_TXINTSTATMASKED ) + & ( ( uint32 ) 1U << channel ) ); + txintstat->intstatraw = ( HWREG( emacBase + EMAC_TXINTSTATRAW ) + & ( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Function to read values of Receive Interrupt Status registers + *(RXINTSTATMASKED, RXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param rxintstat pointer to the emac_rx_int_status Structure that will store the + *register values that have been read. \return None + **/ +/* SourceId : ETH_SourceId_047 */ +/* DesignId : ETH_DesignId_047*/ +/* Requirements : CONQ_EMAC_SR37 */ +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ) +{ + rxintstat->intstatmasked_pend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatmasked_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); + + rxintstat->intstatraw_pend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatraw_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); +} + +/** + * \brief Tx and Rx Buffer Descriptors are initialized. Buffer pointers are allocated to + *the Rx Descriptors. + * + * \param hdkif network interface structure + * \return None + * + **/ +/* SourceId : ETH_SourceId_048 */ +/* DesignId : ETH_DesignId_048*/ +/* Requirements : CONQ_EMAC_SR19,CONQ_EMAC_SR20 */ +void EMACDMAInit( hdkif_t * hdkif ) +{ + uint32 num_bd, pbuf_cnt = 0U; + volatile emac_tx_bd_t *curr_txbd, *last_txbd; + volatile emac_rx_bd_t *curr_bd, *last_bd; + txch_t * txch_dma; + rxch_t * rxch_dma; + uint8_t * p; + + txch_dma = &( hdkif->txchptr ); + + /** + * Initialize the Descriptor Memory For TX and RX + * Only single channel is supported for both TX and RX + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + txch_dma->free_head = ( volatile emac_tx_bd_t * ) ( hdkif->emac_ctrl_ram ); + txch_dma->next_bd_to_process = txch_dma->free_head; + txch_dma->active_tail = NULL; + + /* Set the number of descriptors for the channel */ + num_bd = ( SIZE_EMAC_CTRL_RAM >> 1U ) / sizeof( emac_tx_bd_t ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_txbd = txch_dma->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd = curr_txbd; + + /* Initialize all the TX buffer Descriptors */ + while( num_bd != 0U ) + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list + * is incremented." */ + curr_txbd->next = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) ( curr_txbd + 1U ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd->flags_pktlen = 0U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_txbd = curr_txbd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_txbd->next ); + num_bd--; + } + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd->next = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) txch_dma->free_head ); + + /* Initialize the descriptors for the RX channel */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma = &( hdkif->rxchptr ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is + * incremented." */ + curr_txbd++; + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "Linked List pointer needs to be + * assigned." */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "Linked List pointer needs to be assigned." + */ + /*SAFETYMCUSW 344 S MR:11.5 "Linked List pointer needs to be assigned to a + * different structure." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_head = ( volatile emac_rx_bd_t * ) curr_txbd; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->free_head = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_dma->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = curr_bd; + + /* + ** Static allocation of a specific number of packet buffers as specified by + *MAX_RX_PBUF_ALLOC, whose value is entered by the user in HALCoGen GUI. + */ + + /*Commented part of allocation of pbufs need to check whether its true*/ + + for( pbuf_cnt = 0U; pbuf_cnt < MAX_RX_PBUF_ALLOC; pbuf_cnt++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + p = pbuf_array[ pbuf_cnt ]; + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = EMACSwizzleData( ( uint32 ) p ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( EMAC_BUF_DESC_OWNER ); + if( pbuf_cnt == ( MAX_RX_PBUF_ALLOC - 1U ) ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + else + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd->next = ( emac_rx_bd_t * ) EMACSwizzleData( + ( uint32 ) ( curr_bd + 1U ) ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd++; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_tail = last_bd; +} + +/** + * \brief Initializes the EMAC module for transmission and reception. + * + * \param macaddr MAC Address of the Module. + * \param channel Channel Number. + * + * \return EMAC_ERR_OK if everything gets initialized + * EMAC_ERR_CONN in case of an error in connecting. + * + **/ +/* SourceId : ETH_SourceId_049 */ +/* DesignId : ETH_DesignId_049*/ +/* Requirements : CONQ_EMAC_SR2 */ +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ) +{ + uint32 temp, channel; + volatile uint32 phyID = 0U; + volatile uint32 delay = 0xFFFU; + uint32 phyIdReadCount = 0xFFFFU; + volatile uint32 phyLinkRetries = 0xFFFFU; + hdkif_t * hdkif; + rxch_t * rxch; + uint32 retVal = EMAC_ERR_OK; + uint32 emacBase = 0U; +#if( EMAC_MII_ENABLE == 0U ) + uint16 partnr_spd; +#endif + + hdkif = &hdkif_data[ 0U ]; + EMACInstConfig( hdkif ); + /* set MAC hardware address */ + for( temp = 0U; temp < EMAC_HWADDR_LEN; temp++ ) + { + hdkif->mac_addr[ temp ] = macaddr[ ( EMAC_HWADDR_LEN - 1U ) - temp ]; + } + /*Initialize the EMAC, EMAC Control and MDIO modules. */ + EMACInit( hdkif->emac_ctrl_base, hdkif->emac_base ); + MDIOInit( hdkif->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + delay--; + } + + /* Set the MAC Addresses in EMAC hardware */ + emacBase = hdkif->emac_base; /* MISRA Code Fix (12.2) */ + EMACMACSrcAddrSet( emacBase, hdkif->mac_addr ); + for( channel = 0U; channel < 8U; channel++ ) + { + emacBase = hdkif->emac_base; + EMACMACAddrSet( emacBase, channel, hdkif->mac_addr, EMAC_MACADDR_MATCH ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( phyID == 0U ) && ( phyIdReadCount > 0U ) ) + { + phyID = PhyIDGet( hdkif->mdio_base, hdkif->phy_addr ); + phyIdReadCount--; + } + + if( 0U == phyID ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( ( uint32 ) 0U + == ( ( MDIOPhyAliveStatusGet( hdkif->mdio_base ) >> hdkif->phy_addr ) + & ( uint32 ) 0x01U ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + +#if( EMAC_MII_ENABLE == 0U ) + PhyPartnerSpdGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_spd ); + if( ( partnr_spd & 2U ) == 0U ) + { + EMACRMIISpeedSet( hdkif->emac_base, EMAC_MACCONTROL_RMIISPEED ); + } +#endif + + if( !PhyLinkStatusGet( hdkif->mdio_base, + ( uint32 ) EMAC_PHYADDRESS, + ( uint32 ) phyLinkRetries ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( EMACLinkSetup( hdkif ) != EMAC_ERR_OK ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + /* The transmit and receive buffer descriptors are initialized here. + * Also, packet buffers are allocated to the receive buffer descriptors. + */ + + EMACDMAInit( hdkif ); + + /* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/ + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_RX ); + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_TX ); + + /* Enable GMII bit in the MACCONTROL Rgister*/ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ + EMACMIIEnable( hdkif->emac_base ); + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_BROADCAST_ENABLE ) + EMACRxBroadCastEnable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxBroadCastDisable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_UNICAST_ENABLE ) + EMACRxUnicastSet( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxUnicastClear( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /*Enable Full Duplex or Half-Duplex mode based on GUI Input. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_FULL_DUPLEX_ENABLE ) + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_FULL ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition arameter is taken as input from + * GUI." */ + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_HALF ); +#endif + + /* Enable Loopback based on GUI Input */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_LOOPBACK_ENABLE ) + EMACEnableLoopback( hdkif->emac_base ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACDisableLoopback( hdkif->emac_base ); +#endif + + /* Enable Transmit and Transmit Interrupt */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_TX_ENABLE ) + EMACTxEnable( hdkif->emac_base ); + EMACTxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACTxDisable( hdkif->emac_base ); + EMACTxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /* Enable Receive and Receive Interrupt. Then start receiving by writing to the HDP + * register. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_RX_ENABLE ) + EMACNumFreeBufSet( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) MAX_RX_PBUF_ALLOC ); + EMACRxEnable( hdkif->emac_base ); + EMACRxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); + rxch = &( hdkif->rxchptr ); + /* Write to the RX HDP for channel 0 */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) rxch->active_head, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxDisable( hdkif->emac_base ); + EMACRxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + return retVal; +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf might be + * chained. That is, one pbuf can span more than one tx buffer descriptors + * + * @param hdkif network interface structure + * @param pbuf the pbuf structure which contains the data to be sent using EMAC + * @return boolean. + * -Returns FALSE if a Null pointer was passed for transmission + * -Returns TRUE if valid data is sent and is transmitted. + */ +/* SourceId : ETH_SourceId_050 */ +/* DesignId : ETH_DesignId_050*/ +/* Requirements : CONQ_EMAC_SR49 */ +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ) +{ + txch_t * txch; + pbuf_t * q; + uint32 flags_pktlen; + uint16 totLen; + uint16 qLen; + volatile emac_tx_bd_t *curr_bd, *active_head, *bd_end; + boolean retValue = FALSE; + if( ( pbuf != NULL ) && ( hdkif != NULL ) ) + { + txch = &( hdkif->txchptr ); + + /* Get the buffer descriptor which is free to transmit */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + active_head = curr_bd; + + /* Update the total packet length */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + totLen = pbuf->tot_len; + + curr_bd->flags_pktlen = 0U; + flags_pktlen = ( ( uint32 ) ( totLen ) + | ( EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER ) ); + /* Indicate the start of the packet */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( flags_pktlen ); + + /* Copy pbuf information into TX buffer descriptors */ + q = pbuf; + while( q != NULL ) + { + /* Initialize the buffer pointer and length */ + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = EMACSwizzleData( ( uint32 ) ( q->payload ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + qLen = ( uint16 ) ( q->len ); + curr_bd->bufoff_len = ( uint32 ) EMACSwizzleData( + ( ( uint32 ) ( qLen ) & 0xFFFFU ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + q = q->next; + } + + /* Indicate the start and end of the packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end->next = NULL; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + bd_end->flags_pktlen |= EMACSwizzleData( EMAC_BUF_DESC_EOP ); + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." + */ + txch->free_head = curr_bd; + + /* For the first time, write the HDP with the filled bd */ + if( txch->active_tail == NULL ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /* + * Chain the bd's. If the DMA engine, already reached the end of the chain, + * the EOQ will be set. In that case, the HDP shall be written again. + */ + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->active_tail; + /* Wait for the EOQ bit is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( EMAC_BUF_DESC_EOQ + != ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) ) + { + } + /* Don't write to TXHDP0 until it turns to zero */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( ( uint32 ) 0U != *( ( uint32 * ) 0xFCF78600U ) ) ) + { + } + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) active_head ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( EMAC_BUF_DESC_EOQ + == ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) ) + { + /* Write the Header Descriptor Pointer and start DMA */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch->active_tail = bd_end; + retValue = TRUE; + } + else + { + retValue = FALSE; + } + return retValue; +} + +/** + * Function for processing Tx buffer descriptors. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_051 */ +/* DesignId : ETH_DesignId_051*/ +/* Requirements : CONQ_EMAC_SR13 */ +void EMACTxIntHandler( hdkif_t * hdkif ) +{ + txch_t * txch_int; + volatile emac_tx_bd_t *curr_bd, *next_bd_to_process; + + txch_int = &( hdkif->txchptr ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = next_bd_to_process; + + /* Check for correct start of packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_SOP ) + == EMAC_BUF_DESC_SOP ) + { + /* Make sure that the transmission is over */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_OWNER ) + == EMAC_BUF_DESC_OWNER ) + { + } + + /* Traverse till the end of packet is reached */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_EOP ) + != EMAC_BUF_DESC_EOP ) + { + curr_bd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process->flags_pktlen &= ~( EMACSwizzleData( EMAC_BUF_DESC_SOP ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen &= ~( EMACSwizzleData( EMAC_BUF_DESC_EOP ) ); + + /** + * If there are no more data transmitted, the next interrupt + * shall happen with the pbuf associated with the free_head + */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( curr_bd->next == NULL ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = txch_int->free_head; + } + + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) curr_bd->next ); + } + + /* Acknowledge the EMAC and free the corresponding pbuf */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as + * an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 344 S MR:11.5 "Address stored in pointer is passed as as + * an int parameter." */ + EMACTxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) curr_bd ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = next_bd_to_process; + } +} + +/** + * Function for processing received packets. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_052 */ +/* DesignId : ETH_DesignId_052*/ +/* Requirements : CONQ_EMAC_SR50 */ +void EMACReceive( hdkif_t * hdkif ) +{ + rxch_t * rxch_int; + volatile emac_rx_bd_t *curr_bd, *curr_tail, *last_bd; + + /* The receive structure that holds data about a particular receive channel */ + rxch_int = &( hdkif->rxchptr ); + + /* Get the buffer descriptors which contain the earliest filled data */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_int->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = rxch_int->active_tail; + + /** + * Process the descriptors as long as data is available + * when the DMA is receiving data, SOP flag will be set + */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_SOP ) + == EMAC_BUF_DESC_SOP ) + { + /* Start processing once the packet is loaded */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_OWNER ) + != EMAC_BUF_DESC_OWNER ) + { + /* this bd chain will be freed after processing */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + + /* Get the total length of the packet. curr_bd points to the start + * of the packet. + */ + + /* + * The loop runs till it reaches the end of the packet. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOP ) + != EMAC_BUF_DESC_EOP ) + { + /*Update the flags for the descriptor again and the length of the buffer*/ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( ( uint32 ) EMAC_BUF_DESC_OWNER ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( ( uint32 ) MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_rx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + } + + /* Updating the last descriptor (which contained the EOP flag) */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( ( uint32 ) EMAC_BUF_DESC_OWNER ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( ( uint32 ) MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_rx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + + /* Acknowledge that this packet is processed */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) last_bd ); + + /* The next buffer descriptor is the new head of the linked list. */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->active_head = curr_bd; + + /* The processed descriptor is now the tail of the linked list. */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail = rxch_int->active_tail; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail->next = ( emac_rx_bd_t * ) EMACSwizzleData( + ( uint32 ) rxch_int->free_head ); + + /* The last element in the already processed Rx descriptor chain is now the + * end of list. */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd->next = NULL; + + /** + * Check if the reception has ended. If the EOQ flag is set, the NULL + * Pointer is taken by the DMA engine. So we need to write the RX HDP + * with the next descriptor. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( EMACSwizzleData( curr_tail->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) + == EMAC_BUF_DESC_EOQ ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( rxch_int->free_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + rxch_int->active_tail = last_bd; + } + } +} + +/** @fn void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETH_SourceId_053 */ +/* DesignId : ETH_DesignId_053*/ +/* Requirements : CONQ_EMAC_SR74 */ +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->TXCONTROL = EMAC_TXCONTROL_CONFIGVALUE; + config_reg->RXCONTROL = EMAC_RXCONTROL_CONFIGVALUE; + config_reg->TXINTMASKSET = EMAC_TXINTMASKSET_CONFIGVALUE; + config_reg->TXINTMASKCLEAR = EMAC_TXINTMASKCLEAR_CONFIGVALUE; + config_reg->RXINTMASKSET = EMAC_RXINTMASKSET_CONFIGVALUE; + config_reg->RXINTMASKCLEAR = EMAC_RXINTMASKCLEAR_CONFIGVALUE; + config_reg->MACSRCADDRHI = EMAC_MACSRCADDRHI_CONFIGVALUE; + config_reg->MACSRCADDRLO = EMAC_MACSRCADDRLO_CONFIGVALUE; + config_reg->MDIOCONTROL = EMAC_MDIOCONTROL_CONFIGVALUE; + config_reg->C0RXEN = EMAC_C0RXEN_CONFIGVALUE; + config_reg->C0TXEN = EMAC_C0TXEN_CONFIGVALUE; + } + else + { + config_reg->TXCONTROL = HWREG( EMAC_0_BASE + EMAC_TXCONTROL ); + config_reg->RXCONTROL = HWREG( EMAC_0_BASE + EMAC_RXCONTROL ); + config_reg->TXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_TXINTMASKSET ); + config_reg->TXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_TXINTMASKCLEAR ); + config_reg->RXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_RXINTMASKSET ); + config_reg->RXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_RXINTMASKCLEAR ); + config_reg->MACSRCADDRHI = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRHI ); + config_reg->MACSRCADDRLO = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRLO ); + config_reg->MDIOCONTROL = HWREG( MDIO_0_BASE + MDIO_CONTROL ); + config_reg->C0RXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnRXEN( 0U ) ); + config_reg->C0TXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnTXEN( 0U ) ); + } +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c new file mode 100644 index 00000000000..1274b7d517c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c @@ -0,0 +1,320 @@ +/** @file emif.c + * @brief emif Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void emif_SDRAMInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function has been deprecated. + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF clock + * below 40MHz. Hence the init function needs to be called from the startup before the PLL + * is configured. A new function emif_SDRAM_StartupInit has been added and is called from + * the startup. This function need not be called from the main, and is preserved for + * compatibilty. + */ + +/* SourceId : EMIF_SourceId_001 */ +/* DesignId : EMIF_DesignId_001 */ +/* Requirements : CONQ_EMIF_SR2 */ +void emif_SDRAMInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC1Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_002 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR3 */ +void emif_ASYNC1Init( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + emifREG->CE2CFG = 0x00000000U; + emifREG->CE2CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFFFF00U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) + | ( uint32 ) ( ( uint32 ) 0U ); + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC2Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_003 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR4 */ +void emif_ASYNC2Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + emifREG->CE3CFG = 0x00000000U; + emifREG->CE3CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFF00FFU ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ); + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC3Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_004 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR5 */ +void emif_ASYNC3Init( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + emifREG->CE4CFG = 0x00000000U; + emifREG->CE4CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFF00FFFFU ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void emifGetConfigValue(emif_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the EMIF configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EMIF_SourceId_005 */ +/* DesignId : EMIF_DesignId_003 */ +/* Requirements : CONQ_EMIF_SR6 */ +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_AWCC = EMIF_AWCC_CONFIGVALUE; + config_reg->CONFIG_SDCR = EMIF_SDCR_CONFIGVALUE; + config_reg->CONFIG_SDRCR = EMIF_SDRCR_CONFIGVALUE; + config_reg->CONFIG_CE2CFG = EMIF_CE2CFG_CONFIGVALUE; + config_reg->CONFIG_CE3CFG = EMIF_CE3CFG_CONFIGVALUE; + config_reg->CONFIG_CE4CFG = EMIF_CE4CFG_CONFIGVALUE; + config_reg->CONFIG_CE5CFG = EMIF_CE5CFG_CONFIGVALUE; + config_reg->CONFIG_SDTIMR = EMIF_SDTIMR_CONFIGVALUE; + config_reg->CONFIG_SDSRETR = EMIF_SDSRETR_CONFIGVALUE; + config_reg->CONFIG_INTMSK = EMIF_INTMSK_CONFIGVALUE; + config_reg->CONFIG_PMCR = EMIF_PMCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_AWCC = emifREG->AWCC; + config_reg->CONFIG_SDCR = emifREG->SDCR; + config_reg->CONFIG_SDRCR = emifREG->SDRCR; + config_reg->CONFIG_CE2CFG = emifREG->CE2CFG; + config_reg->CONFIG_CE3CFG = emifREG->CE3CFG; + config_reg->CONFIG_CE4CFG = emifREG->CE4CFG; + config_reg->CONFIG_CE5CFG = emifREG->CE5CFG; + config_reg->CONFIG_SDTIMR = emifREG->SDTIMR; + config_reg->CONFIG_SDSRETR = emifREG->SDSRETR; + config_reg->CONFIG_INTMSK = emifREG->INTMSK; + config_reg->CONFIG_PMCR = emifREG->PMCR; + } +} + +/** @fn void emif_SDRAM_StartupInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function initializes the emif driver for SDRAM (SDRAM initialization function). + * SDRAM Configuration Procedure B as documented in the TRM is implemented. + * + * Note: This function is called in the startup. Do not call the function inside main. + */ + +/* SourceId : EMIF_SourceId_006 */ +/* DesignId : EMIF_DesignId_004 */ +/* Requirements : CONQ_EMIF_SR2 */ +void emif_SDRAM_StartupInit( void ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + volatile uint32 buffer; + + /* Procedure B Step 1: EMIF Clock Frequency is assumed to be configured in the + * startup */ + + /* Procedure B Step 2: Program SDTIMR and SDSRETR to satisfy requirements of SDRAM + * Device */ + emifREG->SDTIMR = ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ); + + emifREG->SDSRETR = ( uint32 ) 0U; + + /* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of + * initialization time */ + emifREG->SDRCR = 1605U; + + /* Procedure B Step 4: Program SDRCR to Trigger Initialization Sequence */ + /** -general clearing of register + * -for NM for setting 16 bit data bus + * -cas latency + * -BIT11_9CLOCK to allow the cl field to be written + * -selecting the banks + * -setting the pagesize + */ + emifREG->SDCR = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 1U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) elements_256 ); + + /* Procedure B Step 5: Read of SDRAM memory location causes processor to wait until + * SDRAM Initialization completes */ + buffer = *PTR; + /* prevents optimization */ + buffer = buffer; + + /* Procedure B Step 6: Program the RR field to the default Refresh Interval of the + * SDRAM*/ + emifREG->SDRCR = 0U; + + /* Place the EMIF in Self Refresh Mode For Clock Change */ + /* Must only write to the upper byte of the SDCR to avoid */ + /* a second intiialization sequence */ + /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */ + *( ( unsigned char * ) ( &emifREG->SDCR ) + 0x3U ) = 0x80U; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c new file mode 100644 index 00000000000..1a16ccee63b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c @@ -0,0 +1,369 @@ +/** @file epc.c + * @brief EPC Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * This file contains APIs for the Error Profiling Controller Module. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "epc.h" +#include "system.h" +#include "reg_esm.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void epcEnableIP1ErrorGen(void) + * @brief Enable ECC error generation for ECC errors on DMA Port A + * + * Enable ECC error generation for ECC errors detected on DMA Port A master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_001 */ +/* DesignId : EPC_DesignId_001 */ +/* Requirements : CONQ_EPC_SR1 */ +void epcEnableIP1ErrorGen( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void epcDisableIP1ErrorGen(void) + * @brief Disable ECC error generation for ECC errors on DMA Port A + * + * Disable ECC error generation for ECC errors detected on DMA Port A master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_002 */ +/* DesignId : EPC_DesignId_002 */ +/* Requirements : CONQ_EPC_SR2 */ +void epcDisableIP1ErrorGen( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void epcEnableIP2ErrorGen(void) + * @brief Enable ECC error generation for ECC errors on PS_SCR_M + * + * Enable ECC error generation for ECC errors detected on PS_SCR_M master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_003 */ +/* DesignId : EPC_DesignId_003 */ +/* Requirements : CONQ_EPC_SR3 */ +void epcEnableIP2ErrorGen( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFF0FFU ) | 0xA00U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void epcDisableIP2ErrorGen(void) + * @brief Disable ECC error generation for ECC errors on PS_SCR_M + * + * Disable ECC error generation for ECC errors detected on PS_SCR_M master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_004 */ +/* DesignId : EPC_DesignId_004 */ +/* Requirements : CONQ_EPC_SR4 */ +void epcDisableIP2ErrorGen( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFF0FFU ) | 0x500U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void epcEnableSERREvent(void) + * @brief Single (correctable) bit error event enable. + * + * These bits (when enabled) cause EPC to + * generate the serr_event if there is a correctable ECC fault address arrives from one + * of the EPC-IP interface and the CAM has an empty entry. + */ +/* SourceId : EPC_SourceId_005 */ +/* DesignId : EPC_DesignId_005 */ +/* Requirements : CONQ_EPC_SR5 */ +void epcEnableSERREvent( void ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void epcDisableSERREvent(void) + * @brief Single (correctable) bit error event disable. + * + * These bits (when enabled) cause EPC to + * disable the serr_event generation. + */ +/* SourceId : EPC_SourceId_006 */ +/* DesignId : EPC_DesignId_006 */ +/* Requirements : CONQ_EPC_SR6 */ +void epcDisableSERREvent( void ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn void epcEnableInterrupt(void) + * @brief CAM or FIFO full interrupt enable. + * + * If this bit is set and CAM is full, CAM Full Interrupt + * is generated. + */ +/* SourceId : EPC_SourceId_007 */ +/* DesignId : EPC_DesignId_007 */ +/* Requirements : CONQ_EPC_SR7 */ +void epcEnableInterrupt( void ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL |= ( uint32 ) ( ( uint32 ) 1U << 24U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void epcDisableInterrupt(void) + * @brief CAM or FIFO full interrupt disable. + * + * Disables interrupt generation in case CAM is full. + */ +/* SourceId : EPC_SourceId_008 */ +/* DesignId : EPC_DesignId_008 */ +/* Requirements : CONQ_EPC_SR8 */ +void epcDisableInterrupt( void ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL &= ~( uint32 ) ( ( uint32 ) 1U << 24U ); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void epcCAMInit(void) + * @brief Initializes CAM. + * + * CAM entries are cleared and available for future CAM usage. + */ +/* SourceId : EPC_SourceId_009 */ +/* DesignId : EPC_DesignId_009 */ +/* Requirements : CONQ_EPC_SR9 */ +void epcCAMInit( void ) +{ + uint8 i; + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + for( i = 0U; i < 8U; i++ ) + { + epcREG1->CAM_INDEX[ i ] = 0x05050505U; + } + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void epcDiagnosticTest(void) + * @brief CAM diagnostic test. + * @return TRUE if diagnostic test passed, FALSE otherwise + * + * This function executes a diagnostic test on EPC and returns the result + */ +/* SourceId : EPC_SourceId_010 */ +/* DesignId : EPC_DesignId_010 */ +/* Requirements : CONQ_EPC_SR14 */ +boolean epcDiagnosticTest( void ) +{ + uint32 epccntrl_bk, camCont_bk, camIndex_bk; + uint32 camAvailable; + boolean status = true; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* Back up EPCCNTRL register */ + epccntrl_bk = epcREG1->EPCCNTRL; + + /* Back up CAM_CONTENT[0] and CAM_INDEX[0] registers */ + camCont_bk = epcREG1->CAM_CONTENT[ 0U ]; + camIndex_bk = epcREG1->CAM_INDEX[ 0U ]; + + /* Enter CAM diagnostic mode and and enable Single (correctable) bit error event + * generation */ + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFF0F0U ) | 0x0A0AU; + + /* Clear first CAM entry */ + epcREG1->CAM_INDEX[ 0U ] = ( epcREG1->CAM_INDEX[ 0U ] & 0xFFFFFFF0U ) | 0x5U; + + /* Identify the number of CAM entries available */ + camAvailable = epcREG1->CAMAVAILSTAT; + + /* New CAM Entry */ + epcREG1->CAM_CONTENT[ 0U ] = 0x1000U; + + /* The number of CAM entries must reduce by 1 */ + if( ( ( esmREG->SR1[ 0U ] & 0x10U ) != 0x10U ) + || ( epcREG1->CAMAVAILSTAT != ( camAvailable - 1U ) ) + || ( epcCheckCAMEntry( 0U ) == true ) ) + { + status = false; + } + + /* Restore CAM_CONTENT and CAM_INDEX[0] registers */ + epcREG1->CAM_CONTENT[ 0U ] = camCont_bk; + epcREG1->CAM_INDEX[ 0U ] = camIndex_bk; + + /* Disable CAM diagnostic mode and restore EPCCNTRL register */ + epcREG1->EPCCNTRL = epccntrl_bk; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + return status; +} + +/** @fn void epcAddCAMEEntry(uint32 address) + * @brief Add a new CAM Entry + * + * Allows you to write a new CAM entry, after checking if there are any available + * entries. + */ +/* SourceId : EPC_SourceId_011 */ +/* DesignId : EPC_DesignId_011 */ +/* Requirements : CONQ_EPC_SR10 */ +boolean epcAddCAMEEntry( uint32 address ) +{ + uint8 i = 0U; + boolean status = false; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + if( epcREG1->CAMAVAILSTAT != 0U ) + { + for( i = 0U; i < 32U; i++ ) + { + if( epcCheckCAMEntry( i ) == true ) + { + epcREG1->CAM_CONTENT[ i ] = address; + status = true; + break; + } + } + } + else + { + status = false; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return status; +} + +/** @fn void epcCheckCAMEntry(uint32 CAMIndex) + * @brief Checks if CAM entry is available. + * + * Checks if the CAM Entry is available and ready for future usage. + */ +/* SourceId : EPC_SourceId_012 */ +/* DesignId : EPC_DesignId_012 */ +/* Requirements : CONQ_EPC_SR11 */ +boolean epcCheckCAMEntry( uint32 index ) +{ + uint32 i, j; + boolean status = false; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + i = index / 4U; + j = ( index % 4U ) * 8U; + + /* Check for availability of CAM Entry for future CAM usage. */ + if( ( epcREG1->CAM_INDEX[ i ] & ( uint32 ) ( ( uint32 ) 0xFU << j ) ) + == ( uint32 ) ( ( uint32 ) 0x5U << j ) ) + { + status = true; + } + else + { + status = false; + } + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + return status; +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c new file mode 100644 index 00000000000..fec49834f0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c @@ -0,0 +1,1273 @@ +/** @file eqep.c + * @brief EQEP Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "eqep.h" +#include "sys_vim.h" + +/*the functions + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void QEPInit(void) + * @brief Initializes the eQEP Driver + * + * This function initializes the eQEP module. + */ +/* SourceId : EQEP_SourceId_001 */ +/* DesignId : EQEP_DesignId_001 */ +/* Requirements : CONQ_QEP_SR1 */ +void QEPInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG1->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG1->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG1->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG1->QPOSCMP = 0x00000000U; + + /** - Clear the time base */ + eqepREG1->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG1->QUPRD = ( uint32 ) 0x00000000U; + + /** - Clear Watchdog Timer register */ + eqepREG1->QWDTMR = ( uint16 ) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG1->QWDPRD = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG1->QDECCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) + | ( uint16 ) ( ( uint16 ) 0U << 13U ) + | ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) + | ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Stobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG1 + ->QEPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) + | ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) + | ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ + << 2U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG1->QPOSCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) + | ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP + << 14U ) + | ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) + | ( uint16 ) ( ( uint16 ) 0x000U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG1->QCAPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) + | ( uint16 ) 0x0000U ); + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG1->QCLR = ( uint16 ) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG1->QEINT = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) ( ( uint16 ) 0U << 4U ) + | ( uint16 ) ( ( uint16 ) 0U << 3U ) + | ( uint16 ) ( ( uint16 ) 0U << 2U ) + | ( uint16 ) ( ( uint16 ) 0U << 1U ) ); + + /** - Clear Capture Timer register */ + eqepREG1->QCTMR = ( uint16 ) 0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG1->QCPRD = ( uint16 ) 0x0000U; + + /** - Clear Period Latch register */ + eqepREG1->QCPRDLAT = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG2->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG2->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG2->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG2->QPOSCMP = 0U; + + /** - Clear the time base */ + eqepREG2->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG2->QUPRD = ( uint32 ) 0U; + + /** - Clear Watchdog Timer register */ + eqepREG2->QWDTMR = ( uint16 ) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG2->QWDPRD = ( uint16 ) 0U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG2->QDECCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) + | ( uint16 ) ( ( uint16 ) 0U << 13U ) + | ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) + | ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Strobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG2 + ->QEPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) + | ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) + | ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ + << 2U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG2->QPOSCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) + | ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP + << 14U ) + | ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) + | ( uint16 ) ( ( uint16 ) 0U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG2->QCAPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) + | ( uint16 ) 0x0000U ); + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG2->QCLR = ( uint16 ) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG2->QEINT = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) ( ( uint16 ) 0U << 4U ) + | ( uint16 ) ( ( uint16 ) 0U << 3U ) + | ( uint16 ) ( ( uint16 ) 0U << 2U ) + | ( uint16 ) ( ( uint16 ) 0U << 1U ) ); + + /** - Clear Capture Timer register */ + eqepREG2->QCTMR = ( uint16 ) 0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG2->QCPRD = ( uint16 ) 0x0000U; + + /** - Clear Period Latch register */ + eqepREG2->QCPRDLAT = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @brief Clears all QEP interrupt flags + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_002 */ +/* DesignId : EQEP_DesignId_002 */ +/* Requirements : CONQ_QEP_SR2 */ +void eqepClearAllInterruptFlags( eqepBASE_t * eqep ) +{ + eqep->QCLR = 0xfffU; + + return; +} /*end of eQEP_clear_all_interrupt_flags() function */ + +/** @brief Clears a single interrupt flag + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Interrupt flag + */ +/* SourceId : EQEP_SourceId_003 */ +/* DesignId : EQEP_DesignId_003 */ +/* Requirements : CONQ_QEP_SR3 */ +void eqepClearInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QCLR |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_clear_interrupt_flag() function */ + +/** @brief Clears the position counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_004 */ +/* DesignId : EQEP_DesignId_004 */ +/* Requirements : CONQ_QEP_SR4 */ +void eqepClearPosnCounter( eqepBASE_t * eqep ) +{ + eqep->QPOSCNT = 0U; + + return; +} /*end of eQEP_clear_posn_counter() function */ + +/** @brief Disables all interrupts + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_005 */ +/* DesignId : EQEP_DesignId_005 */ +/* Requirements : CONQ_QEP_SR5 */ +void eqepDisableAllInterrupts( eqepBASE_t * eqep ) +{ + eqep->QEINT = 0U; + + return; +} /*end of eQEP_disable_all_interrupts () function */ + +/** @brief Disable capture + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_006 */ +/* DesignId : EQEP_DesignId_006 */ +/* Requirements : CONQ_QEP_SR6 */ +void eqepDisableCapture( eqepBASE_t * eqep ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_disable_capture () function */ + +/** @brief Disable gating of index pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_007 */ +/* DesignId : EQEP_DesignId_007 */ +/* Requirements : CONQ_QEP_SR7 */ +void eqepDisableGateIndex( eqepBASE_t * eqep ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_IGATE; + + return; +} /*end of eQEP_disable_gate_index () function */ + +/** @brief Disable individual interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Individual interrupts + */ +/* SourceId : EQEP_SourceId_008 */ +/* DesignId : EQEP_DesignId_008 */ +/* Requirements : CONQ_QEP_SR8 */ +void eqepDisableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QEINT &= ( uint16 ) ~( uint16 ) QEINT_type; + + return; +} /*end of eQEP_disable_interrupt */ + +/** @brief Disable position compare + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_009 */ +/* DesignId : EQEP_DesignId_009 */ +/* Requirements : CONQ_QEP_SR9 */ +void eqepDisablePosnCompare( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_disable_posn_compare () function */ + +/** @brief Disable position compare shadowing + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_010 */ +/* DesignId : EQEP_DesignId_010 */ +/* Requirements : CONQ_QEP_SR10 */ +void eqepDisablePosnCompareShadow( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_disable_posn_compare_shadow () function */ + +/** @brief Disable output sync pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_011 */ +/* DesignId : EQEP_DesignId_011 */ +/* Requirements : CONQ_QEP_SR11 */ +void eqepDisableSyncOut( eqepBASE_t * eqep ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_disable_sync_out () function */ + +/** @brief Disable unit timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_012 */ +/* DesignId : EQEP_DesignId_012 */ +/* Requirements : CONQ_QEP_SR12 */ +void eqepDisableUnitTimer( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_disable_unit_timer () function */ + +/** @brief Disable watchdog timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_013 */ +/* DesignId : EQEP_DesignId_013 */ +/* Requirements : CONQ_QEP_SR13 */ +void eqepDisableWatchdog( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_disable_watchdog () function */ + +/** @brief Enable capture + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_014 */ +/* DesignId : EQEP_DesignId_014 */ +/* Requirements : CONQ_QEP_SR14 */ +void eqepEnableCapture( eqepBASE_t * eqep ) +{ + eqep->QCAPCTL |= eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_enable_capture () function */ + +/** @brief Enable counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_015 */ +/* DesignId : EQEP_DesignId_015 */ +/* Requirements : CONQ_QEP_SR15 */ +void eqepEnableCounter( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_QPEN; + + return; +} /*end of eQEP_enable_counter () function */ + +/** @brief Enable gating of index pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_016 */ +/* DesignId : EQEP_DesignId_016 */ +/* Requirements : CONQ_QEP_SR16 */ +void eqepEnableGateIndex( eqepBASE_t * eqep ) +{ + eqep->QDECCTL |= ( uint16 ) eQEP_Igate_Enable; + + return; +} /*end of eQEP_enable_gate_index () function */ + +/** @brief Enable individual interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT_type Individual interrupts + */ +/* SourceId : EQEP_SourceId_017 */ +/* DesignId : EQEP_DesignId_017 */ +/* Requirements : CONQ_QEP_SR17 */ +void eqepEnableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QEINT |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_enable_interrupt () function */ + +/** @brief Enable position compare + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_018 */ +/* DesignId : EQEP_DesignId_018 */ +/* Requirements : CONQ_QEP_SR18 */ +void eqepEnablePosnCompare( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL |= eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_enable_posn_compare () function */ + +/** @brief Enable position compare shadowing + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_019 */ +/* DesignId : EQEP_DesignId_019 */ +/* Requirements : CONQ_QEP_SR19 */ +void eqepEnablePosnCompareShadow( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL |= eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_enable_posn_compare_shadow () function */ + +/** @brief Enable output sync pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_020 */ +/* DesignId : EQEP_DesignId_020 */ +/* Requirements : CONQ_QEP_SR46 */ +void eqepEnableSyncOut( eqepBASE_t * eqep ) +{ + eqep->QDECCTL |= eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_enable_sync_out () function */ + +/** @brief Enable unit timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_021 */ +/* DesignId : EQEP_DesignId_021 */ +/* Requirements : CONQ_QEP_SR20 */ +void eqepEnableUnitTimer( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_enable_unit_timer () function */ + +/** @brief Enable watchdog timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_022 */ +/* DesignId : EQEP_DesignId_022 */ +/* Requirements : CONQ_QEP_SR21 */ +void eqepEnableWatchdog( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_enable_watchdog () function */ + +/** @brief Manually force QEP interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Individual interrupt + */ +/* SourceId : EQEP_SourceId_023 */ +/* DesignId : EQEP_DesignId_023 */ +/* Requirements : CONQ_QEP_SR22 */ +void eqepForceInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QFRC |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_force_interrupt () function */ + +/** @brief Reads capture period latch + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_024 */ +/* DesignId : EQEP_DesignId_024 */ +/* Requirements : CONQ_QEP_SR23 */ +uint16 eqepReadCapturePeriodLatch( eqepBASE_t * eqep ) +{ + return eqep->QCPRDLAT; +} /*end of eQEP_read_capture_period_latch () function */ + +/** @brief Reads timer latch + * @param[in] eqep Handle to QEP object + * @return Timer value + */ +/* SourceId : EQEP_SourceId_025 */ +/* DesignId : EQEP_DesignId_025 */ +/* Requirements : CONQ_QEP_SR24 */ +uint16 eqepReadCaptureTimerLatch( eqepBASE_t * eqep ) +{ + return eqep->QCTMRLAT; +} /*end of eQEP_read_capture_timer_latch () function */ + +/** @brief Reads interrupt flag value + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Which interrupt to interrogate + * @return Interrupt flag value + */ +/* SourceId : EQEP_SourceId_064 */ +/* DesignId : EQEP_DesignId_064 */ +/* Requirements : CONQ_QEP_SR25 */ +uint16 eqepReadInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + return ( uint16 ) ( eqep->QFLG & ( uint16 ) QEINT_type ); +} /*end of eQEP_read_interrupt_flag () function */ + +/** @brief Reads position compare register + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_026 */ +/* DesignId : EQEP_DesignId_026 */ +/* Requirements : CONQ_QEP_SR26 */ +uint32 eqepReadPosnCompare( eqepBASE_t * eqep ) +{ + return eqep->QPOSCMP; +} /*end of eQEP_read_posn_compare () function */ + +/** @brief Reads position counter + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_027 */ +/* DesignId : EQEP_DesignId_027 */ +/* Requirements : CONQ_QEP_SR27 */ +uint32 eqepReadPosnCount( eqepBASE_t * eqep ) +{ + return eqep->QPOSCNT; +} /*end of eQEP_read_posn_count () function */ + +/** @brief Reads position counter value index pulse latch register + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_028 */ +/* DesignId : EQEP_DesignId_028 */ +/* Requirements : CONQ_QEP_SR28 */ +uint32 eqepReadPosnIndexLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSILAT; +} /*end of eQEP_read_posn_index_latch () function */ + +/** @brief Reads position counter value + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_029 */ +/* DesignId : EQEP_DesignId_029 */ +/* Requirements : CONQ_QEP_SR29 */ +uint32 eqepReadPosnLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSLAT; +} /*end of eQEP_read_posn_latch () function */ + +/** @brief Reads position strobe latch + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_030 */ +/* DesignId : EQEP_DesignId_030 */ +/* Requirements : CONQ_QEP_SR30 */ +uint32 eqepReadPosnStrobeLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSSLAT; +} /*end of eQEP_read_posn_strobe_latch () function */ + +/** @brief Reads status register + * @param[in] eqep Handle to QEP object + * @return Status register value + */ +/* SourceId : EQEP_SourceId_031 */ +/* DesignId : EQEP_DesignId_031 */ +/* Requirements : CONQ_QEP_SR31 */ +uint16 eqepReadStatus( eqepBASE_t * eqep ) +{ + return eqep->QEPSTS; +} /*end of eqepReadStatus () function */ + +/** @brief Resets counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_032 */ +/* DesignId : EQEP_DesignId_032 */ +/* Requirements : CONQ_QEP_SR32 */ +void eqepResetCounter( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_QPEN; + + return; +} /*end of eqepResetCounter () function */ + +/** @brief Sets capture latch mode + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Qclm capture latch mode + */ +/* SourceId : EQEP_SourceId_033 */ +/* DesignId : EQEP_DesignId_033 */ +/* Requirements : CONQ_QEP_SR33 */ +void eqepSetCaptureLatchMode( eqepBASE_t * eqep, QEPCTL_Qclm_t QEPCTL_Qclm ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_QCLM; + eqep->QEPCTL |= QEPCTL_Qclm; + + return; +} /*end of eqepSetCaptureLatchMode () function */ + +/** @brief Sets capture period + * @param[in] eqep Handle to QEP object + * @param[in] period Capture period + */ +/* SourceId : EQEP_SourceId_034 */ +/* DesignId : EQEP_DesignId_034 */ +/* Requirements : CONQ_QEP_SR34 */ +void eqepSetCapturePeriod( eqepBASE_t * eqep, uint16 period ) +{ + eqep->QCPRD = period; + + return; +} /*end of eqepSetCapturePeriod () function */ + +/** @brief Sets capture pre-scaler + * @param[in] eqep Handle to QEP object + * @param[in] QCAPCTL_Ccps Capture pre-scaler + */ +/* SourceId : EQEP_SourceId_035 */ +/* DesignId : EQEP_DesignId_035 */ +/* Requirements : CONQ_QEP_SR35 */ +void eqepSetCapturePrescale( eqepBASE_t * eqep, QCAPCTL_Ccps_t QCAPCTL_Ccps ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_CCPS; + eqep->QCAPCTL |= QCAPCTL_Ccps; +} /*end of eqepSetCapturePrescale () function */ + +/** @brief Sets emulation control + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Freesoft Emulation control bits + */ +/* SourceId : EQEP_SourceId_036 */ +/* DesignId : EQEP_DesignId_036 */ +/* Requirements : CONQ_QEP_SR36 */ +void eqepSetEmuControl( eqepBASE_t * eqep, QEPCTL_Freesoft_t QEPCTL_Freesoft ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_FREESOFT; + eqep->QEPCTL |= QEPCTL_Freesoft; + + return; +} /*end of eqepSetEmuControl () function */ + +/** @brief Sets external clock rate + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Xcr External clock rate + */ +/* SourceId : EQEP_SourceId_037 */ +/* DesignId : EQEP_DesignId_037 */ +/* Requirements : CONQ_QEP_SR37 */ +void eqepSetExtClockRate( eqepBASE_t * eqep, eQEP_Xcr_t eQEP_Xcr ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_XCR; + eqep->QDECCTL |= ( uint16 ) eQEP_Xcr; + + return; +} /*end of eqepSetExtClockRate () function */ + +/** @brief Sets the event which initializes the counter register + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Iei Index event + */ +/* SourceId : EQEP_SourceId_038 */ +/* DesignId : EQEP_DesignId_038 */ +/* Requirements : CONQ_QEP_SR38 */ +void eqepSetIndexEventInit( eqepBASE_t * eqep, QEPCTL_Iei_t QEPCTL_Iei ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_IEI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Iei; + + return; +} /*end of eqepSetIndexEventInit () function */ + +/** @brief Sets the index event which latches the position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Iel Latch event + */ +/* SourceId : EQEP_SourceId_039 */ +/* DesignId : EQEP_DesignId_039 */ +/* Requirements : CONQ_QEP_SR39 */ +void eqepSetIndexEventLatch( eqepBASE_t * eqep, QEPCTL_Iel_t QEPCTL_Iel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_IEL; + eqep->QEPCTL |= QEPCTL_Iel; + + return; +} /*end of eqepSetIndexEventLatch */ + +/** @brief Sets index polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qip Index polarity + */ +/* SourceId : EQEP_SourceId_040 */ +/* DesignId : EQEP_DesignId_040 */ +/* Requirements : CONQ_QEP_SR40 */ +void eqepSetIndexPolarity( eqepBASE_t * eqep, eQEP_Qip_t eQEP_Qip ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QIP; + eqep->QDECCTL |= eQEP_Qip; + + return; +} /*end of eqepSetIndexPolarity () function */ + +/** @brief Sets max position count + * @param[in] eqep Handle to QEP object + * @param[in] max_count Maximum counter value + */ +/* SourceId : EQEP_SourceId_041 */ +/* DesignId : EQEP_DesignId_041 */ +/* Requirements : CONQ_QEP_SR41 */ +void eqepSetMaxPosnCount( eqepBASE_t * eqep, uint32 max_count ) +{ + eqep->QPOSMAX = max_count; + + return; +} /*end of eqepSetMaxPosnCount () function */ + +/** @brief Sets output pulse width when a match occur + * @param[in] eqep Handle to QEP object + * @param[in] pulse_width Pulse width value + */ +/* SourceId : EQEP_SourceId_042 */ +/* DesignId : EQEP_DesignId_042 */ +/* Requirements : CONQ_QEP_SR42 */ +void eqepSetPosnComparePulseWidth( eqepBASE_t * eqep, uint16 pulse_width ) +{ + uint16 pulse_width_masked; + + pulse_width_masked = pulse_width & 4095U; + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCSPW; + eqep->QPOSCTL |= pulse_width_masked; + + return; +} /*end of eqepSetPosnComparePulseWidth () function */ + +/** @brief Sets position compare shadow load mode + * @param[in] eqep Handle to QEP object + * @param[in] QPOSCTL_Pcload PC load event + */ +/* SourceId : EQEP_SourceId_043 */ +/* DesignId : EQEP_DesignId_043 */ +/* Requirements : CONQ_QEP_SR43 */ +void eqepSetPosnCompareShadowLoad( eqepBASE_t * eqep, QPOSCTL_Pcload_t QPOSCTL_Pcload ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCLOAD; + eqep->QPOSCTL |= ( uint16 ) QPOSCTL_Pcload; + + return; +} /*end of eqepSetPosnCompareShadowLoad () function */ + +/** @brief Sets position counter reset mode + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Pcrm Position counter reset mode + */ +/* SourceId : EQEP_SourceId_044 */ +/* DesignId : EQEP_DesignId_044 */ +/* Requirements : CONQ_QEP_SR44 */ +void eqepSetPosnCountResetMode( eqepBASE_t * eqep, QEPCTL_Pcrm_t QEPCTL_Pcrm ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_PCRM; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Pcrm; + + return; +} /*end of eqepSetPosnCountResetMode () function */ + +/** @brief Sets initial position counter value + * @param[in] eqep Handle to QEP object + * @param[in] init_count initial counter value + */ +/* SourceId : EQEP_SourceId_045 */ +/* DesignId : EQEP_DesignId_045 */ +/* Requirements : CONQ_QEP_SR45 */ +void eqepSetPosnInitCount( eqepBASE_t * eqep, uint32 init_count ) +{ + eqep->QPOSINIT = init_count; + + return; +} /*end of eqepSetPosnInitCount () function */ + +/** @brief Selects whether index or strobe pin is used for sync output + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_SPsel Selected pin + */ +/* SourceId : EQEP_SourceId_046 */ +/* DesignId : EQEP_DesignId_046 */ +/* Requirements : CONQ_QEP_SR47 */ +void eqepSetSelectSyncPin( eqepBASE_t * eqep, eQEP_Spsel_t eQEP_SPsel ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SPSEL; + eqep->QDECCTL |= ( uint16 ) eQEP_SPsel; + + return; +} /*end of eQEP_set_select_sync_pin () function */ + +/** @brief Determines if software initialization of position counter enabled + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Swi Enable/disable position counter initialization + */ +/* SourceId : EQEP_SourceId_047 */ +/* DesignId : EQEP_DesignId_047 */ +/* Requirements : CONQ_QEP_SR48 */ +void eqepSetSoftInit( eqepBASE_t * eqep, QEPCTL_Swi_t QEPCTL_Swi ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SWI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Swi; + + return; +} /*end of eQEP_set_soft_init () function */ + +/** @brief Determines strobe initialization of position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sei Strobe initialization of position counter (disabled, + * rising edge of QEPI) or rising/falling depending on direction + */ +/* SourceId : EQEP_SourceId_048 */ +/* DesignId : EQEP_DesignId_048 */ +/* Requirements : CONQ_QEP_SR49 */ +void eqepSetStrobeEventInit( eqepBASE_t * eqep, QEPCTL_Sei_t QEPCTL_Sei ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Sei; + + return; +} /*end of eQEP_set_strobe_event_init () function */ + +/** @brief Sets up strobe latch of position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sel Sets strobe latch of position counter + */ +/* SourceId : EQEP_SourceId_049 */ +/* DesignId : EQEP_DesignId_049 */ +/* Requirements : CONQ_QEP_SR50 */ +void eqepSetStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= QEPCTL_Sel; + + return; +} /*end of eQEP_set_strobe_event_latch () function */ + +/** @brief Sets up strobe polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qsp Strobe polarity + */ +/* SourceId : EQEP_SourceId_050 */ +/* DesignId : EQEP_DesignId_050 */ +/* Requirements : CONQ_QEP_SR51 */ +void eqepSetStrobePolarity( eqepBASE_t * eqep, eQEP_Qsp_t eQEP_Qsp ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QSP; + eqep->QDECCTL |= eQEP_Qsp; + + return; +} /*end of eqepSetStrobePolarity () function */ + +/** @brief Sets up swapping of A/B channels + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Swap Swap/don't swap A/B channels + */ +/* SourceId : EQEP_SourceId_051 */ +/* DesignId : EQEP_DesignId_051 */ +/* Requirements : CONQ_QEP_SR52 */ +void eqepSetSwapQuadInputs( eqepBASE_t * eqep, eQEP_Swap_t eQEP_Swap ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SWAP; + eqep->QDECCTL |= ( uint16 ) eQEP_Swap; + + return; +} /*end of eqepSetSwapQuadInputs () function */ + +/** @brief Sets sync output compare polarity + * @param[in] eqep Handle to QEP object + * @param[in] QPOSCTL_Pcpol Polarity of sync output + */ +/* SourceId : EQEP_SourceId_052 */ +/* DesignId : EQEP_DesignId_052 */ +/* Requirements : CONQ_QEP_SR53 */ +void eqepSetSynchOutputComparePolarity( eqepBASE_t * eqep, QPOSCTL_Pcpol_t QPOSCTL_Pcpol ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCPOL; + eqep->QPOSCTL |= ( uint16 ) QPOSCTL_Pcpol; + + return; +} /*end of eqepSetSynchOutputComparePolarity () function */ + +/** @brief Sets unit timer period + * @param[in] eqep Handle to QEP object + * @param[in] unit_period Unit period + */ +/* SourceId : EQEP_SourceId_053 */ +/* DesignId : EQEP_DesignId_053 */ +/* Requirements : CONQ_QEP_SR54 */ +void eqepSetUnitPeriod( eqepBASE_t * eqep, uint32 unit_period ) +{ + eqep->QUPRD = unit_period; + + return; +} /*end of eqepSetUnitPeriod () function */ + +/** @brief Sets unit timer prescaling + * @param[in] eqep Handle to QEP object + * @param[in] QCAPCTL_Upps Unit timer prescaling + */ +/* SourceId : EQEP_SourceId_054 */ +/* DesignId : EQEP_DesignId_054 */ +/* Requirements : CONQ_QEP_SR55 */ +void eqepSetUnitPosnPrescale( eqepBASE_t * eqep, QCAPCTL_Upps_t QCAPCTL_Upps ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_UPPS; + eqep->QCAPCTL |= ( uint16 ) QCAPCTL_Upps; + + return; +} /*end of eqepSetUnitPosnPrescale () function */ + +/** @brief Sets watchdog period + * @param[in] eqep Handle to QEP object + * @param[in] watchdog_period Watchdog period + */ +/* SourceId : EQEP_SourceId_055 */ +/* DesignId : EQEP_DesignId_055 */ +/* Requirements : CONQ_QEP_SR56 */ +void eqepSetWatchdogPeriod( eqepBASE_t * eqep, uint16 watchdog_period ) +{ + eqep->QWDPRD = watchdog_period; + + return; +} /*end of eqepSetWatchdogPeriod () function */ + +/** @brief Sets strobe event latch + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sel Sets strobe latch of position counter + */ +/* SourceId : EQEP_SourceId_056 */ +/* DesignId : EQEP_DesignId_056 */ +/* Requirements : CONQ_QEP_SR57 */ +void eqepSetupStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Sel; + + return; +} /*end of eqepSetupStrobeEventLatch () function */ + +/** @brief Sets A polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qap Channel A polarity + */ +/* SourceId : EQEP_SourceId_057 */ +/* DesignId : EQEP_DesignId_057 */ +/* Requirements : CONQ_QEP_SR58 */ +void eqepSetAPolarity( eqepBASE_t * eqep, eQEP_Qap_t eQEP_Qap ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QAP; + eqep->QDECCTL |= ( uint16 ) eQEP_Qap; + + return; +} /*end of eqepSetAPolarity () function */ + +/** @brief Sets B polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qbp Channel B polarity + */ +/* SourceId : EQEP_SourceId_058 */ +/* DesignId : EQEP_DesignId_058 */ +/* Requirements : CONQ_QEP_SR59 */ +void eqepSetBPolarity( eqepBASE_t * eqep, eQEP_Qbp_t eQEP_Qbp ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QBP; + eqep->QDECCTL |= ( uint16 ) eQEP_Qbp; + + return; +} /*end of eQEP_set_B_polarity () function */ + +/** @brief Set QEP counting mode + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qsrc Sets QEP counting mode + */ +/* SourceId : EQEP_SourceId_059 */ +/* DesignId : EQEP_DesignId_059 */ +/* Requirements : CONQ_QEP_SR60 */ +void eqepSetQEPSource( eqepBASE_t * eqep, eQEP_Qsrc_t eQEP_Qsrc ) +{ + /* set the value */ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QSRC; + eqep->QDECCTL |= ( uint16 ) eQEP_Qsrc; + + return; +} /*end of eQEP_set_eQEP_source () function */ + +/** @brief Writes a value to the position compare register + * @param[in] eqep Handle to QEP object + * @param[in] posn Position compare register value + */ +/* SourceId : EQEP_SourceId_060 */ +/* DesignId : EQEP_DesignId_060 */ +/* Requirements : CONQ_QEP_SR61 */ +void eqepWritePosnCompare( eqepBASE_t * eqep, uint32 posn ) +{ + eqep->QPOSCMP = posn; + + return; +} /*end of eQEP_write_posn_compare () function */ + +/** @fn void eqep1GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EQEP_SourceId_061 */ +/* DesignId : EQEP_DesignId_061 */ +/* Requirements : CONQ_QEP_SR64 */ +void eqep1GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_QPOSINIT = EQEP1_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP1_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP1_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP1_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP1_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP1_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP1_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP1_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP1_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP1_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG1->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG1->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG1->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG1->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG1->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG1->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG1->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG1->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG1->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG1->QEINT; + } +} + +/** @fn void eqep2GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EQEP_SourceId_062 */ +/* DesignId : EQEP_DesignId_062 */ +/* Requirements : CONQ_QEP_SR65 */ +void eqep2GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_QPOSINIT = EQEP2_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP2_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP2_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP2_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP2_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP2_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP2_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP2_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP2_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP2_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG2->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG2->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG2->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG2->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG2->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG2->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG2->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG2->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG2->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG2->QEINT; + } +} + +/*end of file*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c new file mode 100644 index 00000000000..b5bb5023b4d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c @@ -0,0 +1,273 @@ +/** @file errata.c + * @brief Errata workaround Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Errata workaround API's + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "errata.h" +#include "sys_core.h" +#include "sys_pmu.h" + +/** @fn void errataFailNotification(uint32 flag) + * @brief Errata fail service routine + * + * This function is called if there is a errata workaround fail with appropriate flag + */ +void errataFailNotification( uint32 flag ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/** @fn void errata_PBIST_4(void) + * @brief Workaround for the Errata PBIST#4. + * + * This function is workaround for Errata PBIST#4. + * This function is designed to initialize the ROMs using the PBIST controller. + * The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM. + * This function should be called at startup after system init before using the ROMs. + * + * @note : This Function uses register's which are not exposed to users through + * TRM , to run custom algorithm. User can use this function as Black box. + * + */ +void errata_PBIST_4( void ) +{ + volatile uint32 i = 0U; + uint8 ROM_count; + sint32 PBIST_wait_done_loop; + uint32 pmuCalibration, pmuCount; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* PMU calibration */ + _pmuInit_(); + _pmuEnableCountersGlobal_(); + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + _pmuStopCounters_( pmuCYCLE_COUNTER ); + pmuCalibration = _pmuGetCycleCount_(); + + /* ROM_init Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + *( volatile uint32 * ) 0xFFFF0400U = 0x0000000AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000EE0AU; + + /* Loop for Executing PBIST ROM and STC ROM */ + for( ROM_count = 0U; ROM_count < 4U; ROM_count++ ) + { + PBIST_wait_done_loop = 0; + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST Clocks did not disable */ + if( pbistREG->PACT != 0x0U ) + { + errataFailNotification( PBISTERRATA_FAIL3 ); + } + else + { + /* PBIST ROM clock frequency = GCLK frequency /4 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000205U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000020AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /* wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + for( i = 0U; i < ( 64U + ( 64U * 1U ) ); i++ ) + { /* Wait */ + } + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Load PBIST ALGO to initialize the ROMs */ + *( volatile uint32 * ) 0xFFFFE400U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE440U = 0x00000025U; + *( volatile uint32 * ) 0xFFFFE404U = 0x62400001U; + *( volatile uint32 * ) 0xFFFFE444U = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE408U = 0x00068003U; + *( volatile uint32 * ) 0xFFFFE448U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE40CU = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE44CU = 0x00006860U; + *( volatile uint32 * ) 0xFFFFE410U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE450U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE540U = 0x000003E8U; + *( volatile uint32 * ) 0xFFFFE550U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE530U = 0x00000000U; + + /* SELECT ROM */ + if( ROM_count == 0U ) + { + /* SELECT STC1 ROM1 */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x07B3FFFFU; + pbistREG->RAMT = 0x0E01200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else if( ROM_count == 1U ) + { + /* SELECT STC1 ROM2 */ + *( volatile uint32 * ) 0xFFFFE520U = 0xA88FA473U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00BD719DU; + pbistREG->RAMT = 0x0E02200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 2U; /* CSR */ + } + else if( ROM_count == 2U ) + { + /* SELECT STC2 ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x06E3FFFFU; + pbistREG->RAMT = 0x0F01200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else if( ROM_count == 3U ) + { + /* SELECT PBIST ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0x00000002U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00000000U; + pbistREG->RAMT = 0x0101200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else + { + /* Empty */ + } + + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 0U ] = 8U; /* CMS */ + + /* Start PMU counter */ + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + + /* PBIST_RUN */ + pbistREG->rsvd1[ 1U ] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->MSTCGSTAT & 0x1U ) != 0x1U ) + { + } /* Wait */ + + /* Stop PMU counter */ + _pmuStopCounters_( pmuCYCLE_COUNTER ); + + /* Get CPU cycle count */ + pmuCount = _pmuGetCycleCount_(); + + /* Calculate PBIST test complete time in ROM Clock */ + /* 4 - Divide value ( Default is 4 in HALCoGen) */ + /* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */ + pmuCount = pmuCount - pmuCalibration; + PBIST_wait_done_loop = ( ( sint32 ) pmuCount / 4 ) - 1000; + + /* Check PBIST status results (Address, Status, Count, etc...) */ + if( ( pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 + | pbistREG->FSRDL1 | pbistREG->rsvd4[ 0U ] | pbistREG->rsvd4[ 1U ] ) + != 0U ) + { + /* PBIST Failure for the Algorithm chosen above */ + errataFailNotification( PBISTERRATA_FAIL1 ); + } + + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected */ + if( ( PBIST_wait_done_loop <= 20 ) || ( PBIST_wait_done_loop >= 200 ) ) + { + errataFailNotification( PBISTERRATA_FAIL2 ); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + } + } /* ROM Loop */ + + /* ROM restore default setup */ + /* (must be completed before continuing) */ + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA0AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA05U; + *( volatile uint32 * ) 0xFFFF0400U = 0x00000005U; + + _pmuDisableCountersGlobal_(); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c new file mode 100644 index 00000000000..3fada34da53 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c @@ -0,0 +1,374 @@ +/** @file errata_SSWF021_45.c + * @brief errata for PLLs + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "errata_SSWF021_45_defs.h" +#include "errata_SSWF021_45.h" + +static uint32 check_frequency( uint32 cnt1_clksrc ); +static uint32 disable_plls( uint32 plls ); + +/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count) +* @brief This handles the errata for PLL1 and PLL2. This function is called in device +startup +* +* @param[in] count : Number of retries until both PLLs are locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_both_plls( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while( ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + || ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) == 0U ) ) ) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count) +* @brief This handles the errata for PLL1. This function is called in device startup +* +* @param[in] count : Number of retries until both PLL1 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll1( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1; + /* Check for PLL1 valid or PLL1 slip*/ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count) +* @brief This handles the errata for PLL2. This function is called in device startup +* +* @param[in] count : Number of retries until PLL2 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll2( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL2; + /* Check for PLL2 valid or PLL2 slip */ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0 ] & ESM_SR4_PLL2SLIP ) == 0U ) ) + { + /* Wait */ + } + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 check_frequency(uint32 cnt1_clksrc) + * @brief This function checks for the PLL frequency. + * + * @param[in] cnt1_clksrc : Clock source for Counter1 + * 0U - PLL1 (clock source 0) + * 1U - PLL2 (clock source 1) + * + * @return DCC Error status + * 0 - DCC error has not occurred + * 1 - DCC error has occurred + */ +static uint32 check_frequency( uint32 cnt1_clksrc ) +{ + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0x5U | /** Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + dccREG1->STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) cnt1_clksrc; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + while( dccREG1->STAT == 0U ) + { + /* Wait */ + } + return ( dccREG1->STAT & 0x01U ); +} +/** @fn uint32 disable_plls(uint32 plls) + * @brief This function disables plls and clears the respective ESM flags. + * + * @param[in] plls : Clock source for Counter1 + * 2U - PLL1 + * 40U - PLL2 + * + * @return failCode + * 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 4 = The workaround function was not able to disable at least one of the PLLs. + * The most likely reason is that a PLL is already being used as a clock source. This can + * be caused by the workaround function being called from the wrong place in the code. + */ +static uint32 disable_plls( uint32 plls ) +{ + uint32 timeout, failCode; + + systemREG1->CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout--; + while( ( ( systemREG1->CSVSTAT & ( plls ) ) != 0U ) && ( timeout != 0U ) ) + { + /* Clear ESM and GLBSTAT PLL slip flags */ + systemREG1->GBLSTAT = 0x00000300U; + + if( ( plls & SYS_CLKSRC_PLL1 ) == SYS_CLKSRC_PLL1 ) + { + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + } + if( ( plls & SYS_CLKSRC_PLL2 ) == SYS_CLKSRC_PLL2 ) + { + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + } + timeout--; + /* Wait */ + } + if( timeout == 0U ) + { + failCode = 4U; + } + else + { + failCode = 0U; + } + return failCode; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c new file mode 100644 index 00000000000..8cf11f1fcda --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c @@ -0,0 +1,1068 @@ +/** @file esm.c + * @brief Esm Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the Esm driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "esm.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void esmInit(void) + * @brief Initializes Esm Driver + * + * This function initializes the Esm driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : ESM_SourceId_001 */ +/* DesignId : ESM_DesignId_001 */ +/* Requirements : CONQ_ESM_SR2 */ +void esmInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Disable error pin channels */ + esmREG->DEPAPR1 = 0xFFFFFFFFU; + esmREG->IEPCR4 = 0xFFFFFFFFU; + esmREG->IEPCR7 = 0xFFFFFFFFU; + + /** - Disable interrupts */ + esmREG->IECR1 = 0xFFFFFFFFU; + esmREG->IECR4 = 0xFFFFFFFFU; + esmREG->IECR7 = 0xFFFFFFFFU; + + /** - Clear error status flags */ + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SSR2 = 0xFFFFFFFFU; + esmREG->SR1[ 2U ] = 0xFFFFFFFFU; + + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + + /** - Setup LPC preload */ + esmREG->LTCPR = 16384U - 1U; + + /** - Reset error pin */ + if( esmREG->EPSR == 0U ) + { + esmREG->EKR = 0x00000005U; + } + else + { + esmREG->EKR = 0x00000000U; + } + + /** - Clear interrupt level */ + esmREG->ILCR1 = 0xFFFFFFFFU; + esmREG->ILCR4 = 0xFFFFFFFFU; + esmREG->ILCR7 = 0xFFFFFFFFU; + + /** - Set interrupt level */ + esmREG->ILSR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable error pin channels */ + esmREG->EEPAPR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable interrupts */ + esmREG->IESR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn uint32 esmError(void) + * @brief Return Error status + * + * @return The error status + * + * Returns the error status. + */ +/* SourceId : ESM_SourceId_002 */ +/* DesignId : ESM_DesignId_002 */ +/* Requirements : CONQ_ESM_SR3 */ +uint32 esmError( void ) +{ + uint32 status; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + status = esmREG->EPSR; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_003 */ +/* DesignId : ESM_DesignId_003 */ +/* Requirements : CONQ_ESM_SR4 */ +void esmEnableError( uint64 channels ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + esmREG->IEPSR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->EEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_004 */ +/* DesignId : ESM_DesignId_004 */ +/* Requirements : CONQ_ESM_SR4 */ +void esmEnableErrorUpper( uint64 channels ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + esmREG->IEPSR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_005 */ +/* DesignId : ESM_DesignId_005 */ +/* Requirements : CONQ_ESM_SR5 */ +void esmDisableError( uint64 channels ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + esmREG->IEPCR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->DEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_006 */ +/* DesignId : ESM_DesignId_006 */ +/* Requirements : CONQ_ESM_SR5 */ +void esmDisableErrorUpper( uint64 channels ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + esmREG->IEPCR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} +/** @fn void esmTriggerErrorPinReset(void) + * @brief Trigger error pin reset and switch back to normal operation + * + * Trigger error pin reset and switch back to normal operation. + */ +/* SourceId : ESM_SourceId_007 */ +/* DesignId : ESM_DesignId_007 */ +/* Requirements : CONQ_ESM_SR6 */ +void esmTriggerErrorPinReset( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + esmREG->EKR = 5U; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void esmActivateNormalOperation(void) + * @brief Activate normal operation + * + * Activates normal operation mode. + */ +/* SourceId : ESM_SourceId_008 */ +/* DesignId : ESM_DesignId_008 */ +/* Requirements : CONQ_ESM_SR7 */ +void esmActivateNormalOperation( void ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + esmREG->EKR = 0U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_009 */ +/* DesignId : ESM_DesignId_009 */ +/* Requirements : CONQ_ESM_SR8 */ +void esmEnableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + esmREG->IESR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IESR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_010 */ +/* DesignId : ESM_DesignId_010 */ +/* Requirements : CONQ_ESM_SR8 */ +void esmEnableInterruptUpper( uint64 channels ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + esmREG->IESR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} +/** @fn void esmDisableInterrupt(uint32 channels) + * @brief Disable Group 1 Channels Interrupts for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_011 */ +/* DesignId : ESM_DesignId_011 */ +/* Requirements : CONQ_ESM_SR9 */ +void esmDisableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + esmREG->IECR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IECR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void esmDisableInterrupt(uint64 channels) + * @brief Disable Group 1 Channels Interrupts for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_012 */ +/* DesignId : ESM_DesignId_012 */ +/* Requirements : CONQ_ESM_SR9 */ +void esmDisableInterruptUpper( uint64 channels ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + esmREG->IECR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels for channels 0-63 + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_013 */ +/* DesignId : ESM_DesignId_013 */ +/* Requirements : CONQ_ESM_SR10 */ +void esmSetInterruptLevel( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + esmREG->ILCR4 = ( uint32 ) ( ( ( channels & ( ~flags ) ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILSR4 = ( uint32 ) ( ( ( channels & flags ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILCR1 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR1 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels for channels 64-95 + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_014 */ +/* DesignId : ESM_DesignId_014 */ +/* Requirements : CONQ_ESM_SR10 */ +void esmSetInterruptLevelUpper( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + esmREG->ILCR7 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR7 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatus(uint32 group, uint32 channels) + * @brief Clear Group error status + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_015 */ +/* DesignId : ESM_DesignId_015 */ +/* Requirements : CONQ_ESM_SR14 */ +void esmClearStatus( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + esmREG->SR1[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + if( group == 0U ) + { + esmREG->SR4[ group ] = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatusUpper(uint32 group, uint64 channels) + * @brief Clear Group error status for channels 64-95 + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_016 */ +/* DesignId : ESM_DesignId_016 */ +/* Requirements : CONQ_ESM_SR14 */ +void esmClearStatusUpper( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + esmREG->SR7[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} +/** @fn void esmClearStatusBuffer(uint32 channels) + * @brief Clear Group 2 error status buffer + * + * @param[in] channels - Channel mask + * + * Clear Group 2 error status buffer. + */ +/* SourceId : ESM_SourceId_017 */ +/* DesignId : ESM_DesignId_017 */ +/* Requirements : CONQ_ESM_SR15 */ +void esmClearStatusBuffer( uint32 channels ) +{ + /* USER CODE BEGIN (35) */ + /* USER CODE END */ + + esmREG->SSR2 = channels; + + /* USER CODE BEGIN (36) */ + /* USER CODE END */ +} + +/** @fn void esmSetCounterPreloadValue(uint32 value) + * @brief Set counter preload value + * + * @param[in] value - Counter preload value + * + * Set counter preload value. + */ +/* SourceId : ESM_SourceId_018 */ +/* DesignId : ESM_DesignId_018 */ +/* Requirements : CONQ_ESM_SR11 */ +void esmSetCounterPreloadValue( uint32 value ) +{ + /* USER CODE BEGIN (37) */ + /* USER CODE END */ + + esmREG->LTCPR = value & 0xC000U; + + /* USER CODE BEGIN (38) */ + /* USER CODE END */ +} + +/** @fn uint64 esmGetStatus(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group (Channels from 0-63) + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_019 */ +/* DesignId : ESM_DesignId_019 */ +/* Requirements : CONQ_ESM_SR12 */ +uint64 esmGetStatus( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + if( group == 0U ) + { + ESM_ESTATUS4 = esmREG->SR4[ group ]; + } + else + { + ESM_ESTATUS4 = 0U; + } + ESM_ESTATUS1 = esmREG->SR1[ group ]; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( ( uint64 ) ESM_ESTATUS4 ) << 32U ) | ( uint64 ) ESM_ESTATUS1 ) + & channels; + + /* USER CODE BEGIN (40) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusUpper(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group (Channels from 64-95) + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_020 */ +/* DesignId : ESM_DesignId_020 */ +/* Requirements : CONQ_ESM_SR12 */ +uint64 esmGetStatusUpper( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS7 = esmREG->SR7[ group ]; + + /* USER CODE BEGIN (41) */ + /* USER CODE END */ + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( uint64 ) ESM_ESTATUS7 ) & channels; + + /* USER CODE BEGIN (42) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusBuffer(uint64 channels) + * @brief Return Group 2 channel x Error status buffer + * + * @param[in] channels - Error Channels + * + * @return The channels status + * + * Returns the group 2 buffered status of selected channels. + */ +/* SourceId : ESM_SourceId_021 */ +/* DesignId : ESM_DesignId_021 */ +/* Requirements : CONQ_ESM_SR17 */ +uint32 esmGetStatusBuffer( uint32 channels ) +{ + uint32 status; + + /* USER CODE BEGIN (43) */ + /* USER CODE END */ + status = esmREG->SSR2 & channels; + + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmEnterSelfTest(void) + * @brief Return ESM Self test status + * + * @return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_022 */ +/* DesignId : ESM_DesignId_022 */ +/* Requirements : CONQ_ESM_SR16 */ +esmSelfTestFlag_t esmEnterSelfTest( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (45) */ + /* USER CODE END */ + + uint32 errPinStat = esmREG->EPSR & 0x1U; + uint32 esmKeyReg = esmREG->EKR; + if( ( errPinStat == 0x0U ) && ( esmKeyReg == 0x0U ) ) + { + status = esmSelfTest_NotStarted; + } + else + { + esmREG->EKR = 0xAU; + status = esmSelfTest_Active; + if( ( esmREG->EPSR & 0x1U ) != 0x0U ) + { + status = esmSelfTest_Failed; + } + esmREG->EKR = 0x5U; + } + + /* USER CODE BEGIN (46) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmSelfTestStatus(void) + * @brief Return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_023 */ +/* DesignId : ESM_DesignId_023 */ +/* Requirements : CONQ_ESM_SR17 */ +esmSelfTestFlag_t esmSelfTestStatus( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (47) */ + /* USER CODE END */ + + if( ( esmREG->EPSR & 0x1U ) == 0x0U ) + { + if( esmREG->EKR == 0x5U ) + { + status = esmSelfTest_Active; + } + else + { + status = esmSelfTest_Failed; + } + } + else + { + status = esmSelfTest_Passed; + } + + /* USER CODE BEGIN (48) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +/* SourceId : ESM_SourceId_024 */ +/* DesignId : ESM_DesignId_024 */ +/* Requirements : CONQ_ESM_SR18 */ +void esmGetConfigValue( esm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE; + config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE; + config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE; + config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE; + config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE; + config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE; + config_reg->CONFIG_IEPSR7 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR7 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR7 = ESM_ILSR4_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1; + config_reg->CONFIG_IESR1 = esmREG->IESR1; + config_reg->CONFIG_ILSR1 = esmREG->ILSR1; + config_reg->CONFIG_LTCPR = esmREG->LTCPR; + config_reg->CONFIG_EKR = esmREG->EKR; + config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4; + config_reg->CONFIG_IESR4 = esmREG->IESR4; + config_reg->CONFIG_ILSR4 = esmREG->ILSR4; + config_reg->CONFIG_IEPSR7 = esmREG->IEPSR7; + config_reg->CONFIG_IESR7 = esmREG->IESR7; + config_reg->CONFIG_ILSR7 = esmREG->ILSR7; + } +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/** @fn void esmHighInterrupt(void) + * @brief High Level Interrupt for ESM + */ + +/* SourceId : ESM_SourceId_025 */ +/* DesignId : ESM_DesignId_025 */ +/* Requirements : CONQ_ESM_SR19 */ +void esmHighInterrupt( void ) +{ + /* Note : Group 1 Error */ + /* 1 to 32 -> channel 0 to 31 */ + /* 65 to 96 -> channel 32 to 63 */ + /* 129 to 160 -> channel 64 to 95 */ + /* Note : Group 2 Error */ + /* 33 to 64 -> channel 0 to 31 */ + + uint32 vec = esmREG->IOFFHR - 1U; + + /* USER CODE BEGIN (50) */ + /* USER CODE END */ + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( esmREG, ( vec ) ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( esmREG, ( vec - 32U ) ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( esmREG, ( vec - 32U ) ); + } + else if( ( vec >= 128U ) && ( vec < 160U ) ) + { + esmREG->SR7[ 0U ] = ( uint32 ) 1U << ( vec - 128U ); + esmGroup1Notification( esmREG, ( vec - 96U ) ); + } + else + { + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c new file mode 100644 index 00000000000..9acbe119a7d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c @@ -0,0 +1,2393 @@ +/** @file etpwm.c + * @brief ETPWM Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "etpwm.h" +#include "pinmux.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void etpwmInit(void) + * @brief Initializes the eTPWM Driver + * + * This function initializes the eTPWM module. + * + * @note This function sets the time-base counters in up-count mode. + * Application can configure the module in a different mode using other functions in + * this driver.(Sample code provided in the examples folder) In that case, application + * need not call etpwmInit function. pinmuxInit needs to be called before this function. + * + */ +/* SourceId : ETPWM_SourceId_001 */ +/* DesignId : ETPWM_DesignId_001 */ +/* Requirements : CONQ_EPWM_SR2 */ +void etpwmInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** @b initialize @b ETPWM1 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG1->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG1->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG1->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG1->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG1->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG1->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG1->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG1->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0u << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG1->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG1->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG1->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG1->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG1 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG1->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG1->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG1->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG1->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG1->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG1->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM2 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG2->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG2->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG2->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG2->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG2->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG2->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG2->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG2->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG2->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG2->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG2->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG2->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG2 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG2->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG2->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG2->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG2->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG2->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG2->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM3 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG3->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG3->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG3->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG3->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG3->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG3->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG3->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG3->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG3->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG3->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG3->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG3->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG3 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG3->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG3->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG3->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG3->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG3->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG3->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM4 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG4->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG4->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG4->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG4->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG4->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG4->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG4->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG4->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG4->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG4->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG4->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG4 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG4->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG4->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG4->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG4->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG4->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG4->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM5 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG5->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG5->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG5->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG5->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG5->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG5->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG5->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG5->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG5->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG5->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG5->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG5->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG5 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG5->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG5->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG5->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG5->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG5->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG5->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM6 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG6->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG6->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG6->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG6->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG6->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG6->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG6->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG6->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG6->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG6->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG6->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG6->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG6 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG6->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG6->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG6->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG6->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG6->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG6->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM7 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG7->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG7->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG7->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG7->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG7->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG7->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG7->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG7->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG7->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG7->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG7->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG7 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG7->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG7->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG7->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG7->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG7->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG7->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/** @fn void etpwmStartTBCLK() + * @brief Start the time-base clocks of all eTPWMx modules + * + * This function starts the time-base clocks of all eTPWMx modules. + */ +/* SourceId : ETPWM_SourceId_002 */ +/* DesignId : ETPWM_DesignId_002 */ +/* Requirements : CONQ_EPWM_SR45 */ +void etpwmStartTBCLK( void ) +{ + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMUX[ 166U ] = ( pinMuxReg->PINMUX[ 166U ] + & PINMUX_ETPWM_TBCLK_SYNC_MASK ) + | ( PINMUX_ETPWM_TBCLK_SYNC_ON ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmStopTBCLK() + * @brief Stop the time-base clocks of all eTPWMx modules + * + * This function stops the time-base clocks of all eTPWMx modules. + */ +/* SourceId : ETPWM_SourceId_003 */ +/* DesignId : ETPWM_DesignId_003 */ +/* Requirements : CONQ_EPWM_SR46 */ +void etpwmStopTBCLK( void ) +{ + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMUX[ 166U ] = ( pinMuxReg->PINMUX[ 166U ] + & PINMUX_ETPWM_TBCLK_SYNC_MASK ) + | ( PINMUX_ETPWM_TBCLK_SYNC_OFF ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t + * hspclkdiv) + * @brief Sets the Time-base Clock divider + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param clkdiv Time-base clock divider + * - ClkDiv_by_1 + * - ClkDiv_by_2 + * - ClkDiv_by_4 + * - ClkDiv_by_8 + * - ClkDiv_by_16 + * - ClkDiv_by_32 + * - ClkDiv_by_64 + * - ClkDiv_by_128 + * @param hspclkdiv High Speed Time-base clock divider + * - HspClkDiv_by_1 + * - HspClkDiv_by_2 + * - HspClkDiv_by_4 + * - HspClkDiv_by_6 + * - HspClkDiv_by_8 + * - HspClkDiv_by_10 + * - HspClkDiv_by_12 + * - HspClkDiv_by_14 + * + * This function sets the TimeBase Clock and the High Speed time base clock divider + * TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV) + */ +/* SourceId : ETPWM_SourceId_004 */ +/* DesignId : ETPWM_DesignId_004 */ +/* Requirements : CONQ_EPWM_SR3 */ +void etpwmSetClkDiv( etpwmBASE_t * etpwm, + etpwmClkDiv_t clkdiv, + etpwmHspClkDiv_t hspclkdiv ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x1F80U; + etpwm->TBCTL |= ( uint16 ) clkdiv | ( uint16 ) hspclkdiv; +} + +/** @fn void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) + * @brief Sets period of timebase counter + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param period 16-bit Time-base period + * + * This function sets period of timebase counter + */ +/* SourceId : ETPWM_SourceId_005 */ +/* DesignId : ETPWM_DesignId_005 */ +/* Requirements : CONQ_EPWM_SR4 */ +void etpwmSetTimebasePeriod( etpwmBASE_t * etpwm, uint16 period ) +{ + etpwm->TBPRD = period; +} + +/** @fn void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) + * @brief Sets timebase counter + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param count 16-bit Counter value + * + * This function sets the timebase counter + */ +/* SourceId : ETPWM_SourceId_006 */ +/* DesignId : ETPWM_DesignId_006 */ +/* Requirements : CONQ_EPWM_SR5 */ +void etpwmSetCount( etpwmBASE_t * etpwm, uint16 count ) +{ + etpwm->TBCTR = count; +} + +/** @fn void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for time-base period register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for time-base period register + */ +/* SourceId : ETPWM_SourceId_007 */ +/* DesignId : ETPWM_DesignId_007 */ +/* Requirements : CONQ_EPWM_SR6 */ +void etpwmDisableTimebasePeriodShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL |= 0x0008U; +} + +/** @fn void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) + * @brief Enable shadow mode for time-base period register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function enables shadow mode for time-base period register + */ +/* SourceId : ETPWM_SourceId_008 */ +/* DesignId : ETPWM_DesignId_008 */ +/* Requirements : CONQ_EPWM_SR7 */ +void etpwmEnableTimebasePeriodShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0008U; +} + +/** @fn void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 + * direction) + * @brief Enable counter register load from phase register when a sync event occurs + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param phase Counter value to be loaded when a sync event occurs + * @param direction Direction of the counter after the sync event (Applied only if + * counter is in updown-count mode, ignores otherwise) + * - COUNT_UP + * - COUNT_DOWN + * - Pass 0 if not applied + * + * This function enables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ETPWM_SourceId_009 */ +/* DesignId : ETPWM_DesignId_009 */ +/* Requirements : CONQ_EPWM_SR8 */ +void etpwmEnableCounterLoadOnSync( etpwmBASE_t * etpwm, uint16 phase, uint16 direction ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x2000U; + etpwm->TBCTL |= 0x0004U | direction; + etpwm->TBPHS = phase; +} + +/** @fn void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) + * @brief Disable counter register load from phase register when a sync event occurs + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ETPWM_SourceId_010 */ +/* DesignId : ETPWM_DesignId_010 */ +/* Requirements : CONQ_EPWM_SR9 */ +void etpwmDisableCounterLoadOnSync( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0004U; +} + +/** @fn void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncMode_t syncmode) + * @brief Set the source of EPWMxSYNCO signal + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param syncOutSrc Synchronization Output Select + * - SyncOut_EPWMxSYNCI + * - SyncOut_CtrEqZero + * - SyncOut_CtrEqCmpB + * - SyncOut_Disable + * + * This function sets the source of synchronization output signal + */ +/* SourceId : ETPWM_SourceId_011 */ +/* DesignId : ETPWM_DesignId_011 */ +/* Requirements : CONQ_EPWM_SR10 */ +void etpwmSetSyncOut( etpwmBASE_t * etpwm, etpwmSyncOut_t syncOutSrc ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0030U; + etpwm->TBCTL |= syncOutSrc; +} + +/** @fn void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) + * @brief Set the time-base counter mode + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param countermode Counter Mode + * - CounterMode_Up + * - Countermode_Down + * - CounterMode_UpDown + * - CounterMode_Stop + * + * This function sets the time-base counter mode of operation. + */ +/* SourceId : ETPWM_SourceId_012 */ +/* DesignId : ETPWM_DesignId_012 */ +/* Requirements : CONQ_EPWM_SR11 */ +void etpwmSetCounterMode( etpwmBASE_t * etpwm, etpwmCounterMode_t countermode ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0003U; + etpwm->TBCTL |= countermode; +} + +/** @fn void etpwmTriggerSWSync(etpwmBASE_t *etpwm) + * @brief Trigger a software synchronization pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function triggers a software synchronization pulse. SWFSYNC is valid (operates) + * only when EPWMxSYNCI as SyncOut + */ +/* SourceId : ETPWM_SourceId_013 */ +/* DesignId : ETPWM_DesignId_013 */ +/* Requirements : CONQ_EPWM_SR12 */ +void etpwmTriggerSWSync( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL |= 0x0040U; +} + +/** @fn void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) + * @brief Set the pulse width modulation (ETPWM) run mode + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param runmode Run mode + * - RunMode_SoftStopAfterIncr : Stop after the next time-base + * counter increment + * - RunMode_SoftStopAfterDecr : Stop after the next time-base + * counter decrement + * - RunMode_SoftStopAfterCycle : Stop when counter completes a whole + * cycle + * - RunMode_FreeRun : Free-run + * + * This function select the behaviour of the ePWM time-base counter during emulation + * events + */ +/* SourceId : ETPWM_SourceId_014 */ +/* DesignId : ETPWM_DesignId_014 */ +/* Requirements : CONQ_EPWM_SR13 */ +void etpwmSetRunMode( etpwmBASE_t * etpwm, etpwmRunMode_t runmode ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0xC000U; + etpwm->TBCTL |= runmode; +} + +/** @fn void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) + * @brief Set the Compare A value + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param value 16-bit Compare A value + * + * This function sets the compare A value + */ +/* SourceId : ETPWM_SourceId_015 */ +/* DesignId : ETPWM_DesignId_015 */ +/* Requirements : CONQ_EPWM_SR14 */ +void etpwmSetCmpA( etpwmBASE_t * etpwm, uint16 value ) +{ + etpwm->CMPA = value; +} + +/** @fn void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) + * @brief Set the Compare B value + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param value 16-bit Compare B value + * + * This function sets the compare B register + */ +/* SourceId : ETPWM_SourceId_016 */ +/* DesignId : ETPWM_DesignId_016 */ +/* Requirements : CONQ_EPWM_SR15 */ +void etpwmSetCmpB( etpwmBASE_t * etpwm, uint16 value ) +{ + etpwm->CMPB = value; +} + +/** @fn void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) + * @brief Enable shadow mode for Compare A register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param loadmode Active Counter-Compare A (CMPA) Load From Shadow Select Mode + * - LoadMode_CtrEqZero : Load on CTR = Zero + * - LoadMode_CtrEqPeriod : Load on CTR = PRD + * - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD + * - LoadMode_Freeze : Freeze (no loads possible) + * + * This function enables shadow mode for Compare A register + */ +/* SourceId : ETPWM_SourceId_017 */ +/* DesignId : ETPWM_DesignId_017 */ +/* Requirements : CONQ_EPWM_SR16 */ +void etpwmEnableCmpAShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode ) +{ + etpwm->CMPCTL &= ( uint16 ) ~( uint16 ) 0x0013U; + etpwm->CMPCTL |= loadmode; +} + +/** @fn void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for Compare A register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for Compare A register + */ +/* SourceId : ETPWM_SourceId_018 */ +/* DesignId : ETPWM_DesignId_018 */ +/* Requirements : CONQ_EPWM_SR17 */ +void etpwmDisableCmpAShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->CMPCTL |= 0x0010U; +} + +/** @fn void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) + * @brief Enable shadow mode for Compare B register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param loadmode Active Counter-Compare B (CMPB) Load From Shadow Select Mode + * - LoadMode_CtrEqZero : Load on CTR = Zero + * - LoadMode_CtrEqPeriod : Load on CTR = PRD + * - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD + * - LoadMode_Freeze : Freeze (no loads possible) + * + * This function enables shadow mode for Compare B register + */ +/* SourceId : ETPWM_SourceId_019 */ +/* DesignId : ETPWM_DesignId_019 */ +/* Requirements : CONQ_EPWM_SR18 */ +void etpwmEnableCmpBShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode ) +{ + etpwm->CMPCTL &= ( uint16 ) ~( uint16 ) 0x004CU; + etpwm->CMPCTL |= ( uint16 ) ( ( uint16 ) loadmode << 2U ); +} + +/** @fn void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for Compare B register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for Compare B register + */ +/* SourceId : ETPWM_SourceId_020 */ +/* DesignId : ETPWM_DesignId_020 */ +/* Requirements : CONQ_EPWM_SR19 */ +void etpwmDisableCmpBShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->CMPCTL |= 0x0040U; +} + +/** @fn void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t + * actionqualconfig) + * @brief Configure Action Qualifier submodule to generate PWMA + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param actionqualconfig Action Qualifier configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmActionQualConfig_t configA + * configA.CtrEqZero_Action = ActionQual_Set + * configA.CtrEqPeriod_Action = ActionQual_Disabled + * configA.CtrEqCmpAUp_Action = ActionQual_Clear + * configA.CtrEqCmpADown_Action = ActionQual_Disabled + * configA.CtrEqCmpBUp_Action = ActionQual_Disabled + * configA.CtrEqCmpBDown_Action = ActionQual_Disabled + * void etpwmSetActionQualPwmA(etpwmREG1, configA) + * + * This function configures Action Qualifier submodule to generate PWMA + */ +/* SourceId : ETPWM_SourceId_021 */ +/* DesignId : ETPWM_DesignId_021 */ +/* Requirements : CONQ_EPWM_SR20 */ +void etpwmSetActionQualPwmA( etpwmBASE_t * etpwm, + etpwmActionQualConfig_t actionqualconfig ) +{ + etpwm + ->AQCTLA = ( ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqZero_Action << 0U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqPeriod_Action << 2U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpAUp_Action << 4U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpADown_Action + << 6U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBUp_Action << 8U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBDown_Action + << 10U ) ); +} + +/** @fn void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t + * actionqualconfig) + * @brief Configure Action Qualifier submodule to generate PWMB + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param actionqualconfig Action Qualifier configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmActionQualConfig_t configB + * configB.CtrEqZero_Action = ActionQual_Set + * configB.CtrEqPeriod_Action = ActionQual_Disabled + * configB.CtrEqCmpAUp_Action = ActionQual_Disabled + * configB.CtrEqCmpADown_Action = ActionQual_Disabled + * configB.CtrEqCmpBUp_Action = ActionQual_Clear + * configB.CtrEqCmpBDown_Action = ActionQual_Disabled + * void etpwmSetActionQualPwmB(etpwmREG1, configB) + * + * This function configures Action Qualifier submodule to generate PWMB + */ +/* SourceId : ETPWM_SourceId_022 */ +/* DesignId : ETPWM_DesignId_022 */ +/* Requirements : CONQ_EPWM_SR21 */ +void etpwmSetActionQualPwmB( etpwmBASE_t * etpwm, + etpwmActionQualConfig_t actionqualconfig ) +{ + etpwm + ->AQCTLB = ( ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqZero_Action << 0U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqPeriod_Action << 2U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpAUp_Action << 4U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpADown_Action + << 6U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBUp_Action << 8U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBDown_Action + << 10U ) ); +} + +/** @fn void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) + * @brief Enable DeadBand module + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param deadbandconfig DeadBand configuration + * + * This function configures Action Qualifier submodule to generate PWMB + */ +/* SourceId : ETPWM_SourceId_023 */ +/* DesignId : ETPWM_DesignId_023 */ +/* Requirements : CONQ_EPWM_SR22 */ +void etpwmEnableDeadBand( etpwmBASE_t * etpwm, etpwmDeadBandConfig_t deadbandconfig ) +{ + uint16 halfCycleMask = ( uint16 ) ( ( deadbandconfig.halfCycleEnable ) ? 0x8000U + : 0U ); + etpwm->DBCTL = ( ( uint16 ) deadbandconfig.inputmode + | ( uint16 ) deadbandconfig.outputmode + | ( uint16 ) deadbandconfig.polarity | halfCycleMask ); +} + +/** @fn void etpwmDisableDeadband(etpwmBASE_t *etpwm) + * @brief Disable DeadBand module + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * + * This function bypasses the Deadband submodule + */ +/* SourceId : ETPWM_SourceId_024 */ +/* DesignId : ETPWM_DesignId_024 */ +/* Requirements : CONQ_EPWM_SR23 */ +void etpwmDisableDeadband( etpwmBASE_t * etpwm ) +{ + etpwm->DBCTL = 0U; +} + +/** @fn void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) + * @brief Sets the rising and falling edge delay + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param Rdelay 16-bit rising edge delay in terms of TCLK ticks + * @param Fdelay 16-bit falling edge delay in terms of TCLK ticks + * + * This function sets the rising and falling edge delays in the DeadBand submodule + */ +/* SourceId : ETPWM_SourceId_025 */ +/* DesignId : ETPWM_DesignId_025 */ +/* Requirements : CONQ_EPWM_SR24 */ +void etpwmSetDeadBandDelay( etpwmBASE_t * etpwm, uint16 Rdelay, uint16 Fdelay ) +{ + etpwm->DBRED = Rdelay; + etpwm->DBFED = Fdelay; +} + +/** @fn void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) + * @brief Enable chopping + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param choppingconfig Chopper submodule configuration + * + * This function enables the chopper submodule with the given configuration + */ +/* SourceId : ETPWM_SourceId_026 */ +/* DesignId : ETPWM_DesignId_026 */ +/* Requirements : CONQ_EPWM_SR25 */ +void etpwmEnableChopping( etpwmBASE_t * etpwm, etpwmChoppingConfig_t choppingconfig ) +{ + etpwm->PCCTL = ( ( uint16 ) 0x0001U | ( uint16 ) choppingconfig.oswdth + | ( uint16 ) choppingconfig.freq | ( uint16 ) choppingconfig.duty ); +} + +/** @fn void etpwmDisableChopping(etpwmBASE_t *etpwm) + * @brief Disable chopping + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables the chopper submodule + */ +/* SourceId : ETPWM_SourceId_027 */ +/* DesignId : ETPWM_DesignId_027 */ +/* Requirements : CONQ_EPWM_SR26 */ +void etpwmDisableChopping( etpwmBASE_t * etpwm ) +{ + etpwm->PCCTL = 0U; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) + * @brief Select the tripzone zources + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param sources Trip zone sources (sources can be ORed) + * - CycleByCycle_TZ1 : Enable TZ1 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ2 : Enable TZ2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ3 : Enable TZ3 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ4 : Enable TZ4 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ5 : Enable TZ5 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ6 : Enable TZ6 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCAEVT2 : Enable DCAEVT2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCBEVT2 : Enable DCBEVT2 as a Cycle-by-cycle trip + * source + * - OneShot_TZ1 : Enable TZ1 as a One-shot trip source + * - OneShot_TZ2 : Enable TZ2 as a One-shot trip source + * - OneShot_TZ3 : Enable TZ3 as a One-shot trip source + * - OneShot_TZ4 : Enable TZ4 as a One-shot trip source + * - OneShot_TZ5 : Enable TZ5 as a One-shot trip source + * - OneShot_TZ6 : Enable TZ6 as a One-shot trip source + * - OneShot_DCAEVT1 : Enable DCAEVT1 as a One-shot trip source + * - OneShot_DCBEVT1 : Enable DCBEVT1 as a One-shot trip source + * + * This function selects the tripzone sources for cycle-by-cycle and one-shot trip + */ +/* SourceId : ETPWM_SourceId_028 */ +/* DesignId : ETPWM_DesignId_028 */ +/* Requirements : CONQ_EPWM_SR27 */ +void etpwmEnableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources ) +{ + etpwm->TZSEL |= sources; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) + * @brief Disable the tripzone zources + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param sources Trip zone sources (sources can be ORed) + * - CycleByCycle_TZ1 : Disable TZ1 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ2 : Disable TZ2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ3 : Disable TZ3 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ4 : Disable TZ4 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ5 : Disable TZ5 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ6 : Disable TZ6 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCAEVT2 : Disable DCAEVT2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCBEVT2 : Disable DCBEVT2 as a Cycle-by-cycle trip + * source + * - OneShot_TZ1 : Disable TZ1 as a One-shot trip source + * - OneShot_TZ2 : Disable TZ2 as a One-shot trip source + * - OneShot_TZ3 : Disable TZ3 as a One-shot trip source + * - OneShot_TZ4 : Disable TZ4 as a One-shot trip source + * - OneShot_TZ5 : Disable TZ5 as a One-shot trip source + * - OneShot_TZ6 : Disable TZ6 as a One-shot trip source + * - OneShot_DCAEVT1 : Disable DCAEVT1 as a One-shot trip source + * - OneShot_DCBEVT1 : Disable DCBEVT1 as a One-shot trip source + * + * This function disables the tripzone sources for cycle-by-cycle or one-shot trip + */ +/* SourceId : ETPWM_SourceId_029 */ +/* DesignId : ETPWM_DesignId_029 */ +/* Requirements : CONQ_EPWM_SR28 */ +void etpwmDisableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources ) +{ + etpwm->TZSEL &= ( uint16 ) ~( uint16 ) sources; +} + +/** @fn void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t + * tripactionconfig) + * @brief Set the action for each trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param tripactionconfig Trip action configuration + * + * This function sets the action for each trip event + */ +/* SourceId : ETPWM_SourceId_030 */ +/* DesignId : ETPWM_DesignId_030 */ +/* Requirements : CONQ_EPWM_SR29 */ +void etpwmSetTripAction( etpwmBASE_t * etpwm, etpwmTripActionConfig_t tripactionconfig ) +{ + etpwm->TZCTL = ( ( uint16 ) ( ( uint16 ) tripactionconfig.TripEvent_ActionOnPWMA + << 0U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.TripEvent_ActionOnPWMB + << 2U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCAEVT1_ActionOnPWMA + << 4U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCAEVT2_ActionOnPWMA + << 6U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCBEVT1_ActionOnPWMB + << 8U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCBEVT2_ActionOnPWMB + << 10U ) ); +} + +/** @fn void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) + * @brief Enables interrupt(EPWMx_TZINT) for the trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param interrupts Interrupts to be enabled (Interrupts can be ORed) + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function enables interrupt(EPWMx_TZINT) for the trip event + */ +/* SourceId : ETPWM_SourceId_031 */ +/* DesignId : ETPWM_DesignId_031 */ +/* Requirements : CONQ_EPWM_SR30 */ +void etpwmEnableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts ) +{ + etpwm->TZEINT |= interrupts; +} + +/** @fn void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) + * @brief Disables interrupt(EPWMx_TZINT) for the trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param interrupts Trip Interrupts to be disabled (Interrupts can be ORed) + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function disables interrupt(EPWMx_TZINT) for the trip event + */ +/* SourceId : ETPWM_SourceId_032 */ +/* DesignId : ETPWM_DesignId_032 */ +/* Requirements : CONQ_EPWM_SR31 */ +void etpwmDisableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts ) +{ + etpwm->TZEINT &= ( uint16 ) ~( uint16 ) interrupts; +} + +/** @fn void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) + * @brief Clears the trip event flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param trips Trip events + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function clears the trip event / Digital Compare output event flag + */ +/* SourceId : ETPWM_SourceId_033 */ +/* DesignId : ETPWM_DesignId_033 */ +/* Requirements : CONQ_EPWM_SR32 */ +void etpwmClearTripCondition( etpwmBASE_t * etpwm, etpwmTrip_t trips ) +{ + etpwm->TZCLR = trips; +} + +/** @fn void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) + * @brief Clears the trip interrupt flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function clears the trip interrupt flag + */ +/* SourceId : ETPWM_SourceId_034 */ +/* DesignId : ETPWM_DesignId_034 */ +/* Requirements : CONQ_EPWM_SR33 */ +void etpwmClearTripInterruptFlag( etpwmBASE_t * etpwm ) +{ + etpwm->TZCLR = 1U; +} + +/** @fn void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) + * @brief Force a trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param trip Trip events + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function forces a trip event / Digital Compare trip event via software + */ +/* SourceId : ETPWM_SourceId_035 */ +/* DesignId : ETPWM_DesignId_035 */ +/* Requirements : CONQ_EPWM_SR34 */ +void etpwmForceTripEvent( etpwmBASE_t * etpwm, etpwmTrip_t trip ) +{ + etpwm->TZFRC = trip; +} + +/** @fn void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ADC Start of Conversion A pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMxSOCA Selection Options + * - DCAEVT1 : DCAEVT1.soc event + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMxSOCA Period Select + * - EventPeriod_FirstEvent : Generate SOCA pulse on the first + * event + * - EventPeriod_SecondEvent : Generate SOCA pulse on the second + * event + * - EventPeriod_ThirdEvent : Generate SOCA pulse on the third + * event + * + * This function enables ADC Start of Conversion A pulse + */ +/* SourceId : ETPWM_SourceId_036 */ +/* DesignId : ETPWM_DesignId_036 */ +/* Requirements : CONQ_EPWM_SR35 */ +void etpwmEnableSOCA( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0xF0FFU; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 11U ) + | ( uint16 ) ( ( uint16 ) eventsource << 8U ); + + etpwm->ETPS &= 0xF0FFU; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 8U ); +} + +/** @fn void etpwmDisableSOCA(etpwmBASE_t *etpwm) + * @brief Disable ADC Start of Conversion A pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables ADC Start of Conversion A pulse + */ +/* SourceId : ETPWM_SourceId_037 */ +/* DesignId : ETPWM_DesignId_037 */ +/* Requirements : CONQ_EPWM_SR36 */ +void etpwmDisableSOCA( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0xF0FFU; +} + +/** @fn void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ADC Start of Conversion B pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMxSOCB Selection Options + * - DCBEVT1 : DCBEVT1.soc event + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMxSOCB Period Select + * - EventPeriod_FirstEvent : Generate SOCB pulse on the first + * event + * - EventPeriod_SecondEvent : Generate SOCB pulse on the second + * event + * - EventPeriod_ThirdEvent : Generate SOCB pulse on the third + * event + * + * This function enables ADC Start of Conversion B pulse + */ +/* SourceId : ETPWM_SourceId_038 */ +/* DesignId : ETPWM_DesignId_038 */ +/* Requirements : CONQ_EPWM_SR37 */ +void etpwmEnableSOCB( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0x0FFFU; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 15U ) + | ( uint16 ) ( ( uint16 ) eventsource << 12U ); + + etpwm->ETPS &= 0x0FFFU; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 12U ); +} + +/** @fn void etpwmDisableSOCB(etpwmBASE_t *etpwm) + * @brief Disable ADC Start of Conversion B pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables ADC Start of Conversion B pulse + */ +/* SourceId : ETPWM_SourceId_039 */ +/* DesignId : ETPWM_DesignId_039 */ +/* Requirements : CONQ_EPWM_SR38 */ +void etpwmDisableSOCB( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0x0FFFU; +} + +/** @fn void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ePWM Interrupt + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMx_INT Selection Options + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMx_INT Period Select + * - EventPeriod_FirstEvent : Generate interrupt on the first + * event + * - EventPeriod_SecondEvent : Generate interrupt on the second + * event + * - EventPeriod_ThirdEvent : Generate interrupt on the third + * event + * + * This function enables EPWMx_INT generation + */ +/* SourceId : ETPWM_SourceId_040 */ +/* DesignId : ETPWM_DesignId_040 */ +/* Requirements : CONQ_EPWM_SR39 */ +void etpwmEnableInterrupt( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0xFFF0U; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 3U ) + | ( uint16 ) ( ( uint16 ) eventsource << 0U ); + + etpwm->ETPS &= 0xFFF0U; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 0U ); +} + +/** @fn void etpwmDisableInterrupt(etpwmBASE_t *etpwm) + * @brief Disable ePWM Interrupt + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables EPWMx_INT generation + */ +/* SourceId : ETPWM_SourceId_041 */ +/* DesignId : ETPWM_DesignId_041 */ +/* Requirements : CONQ_EPWM_SR40 */ +void etpwmDisableInterrupt( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0xFFF0U; +} + +/** @fn uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) + * @brief Return event status flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @return event status flag + * Bit 0: ePWM Interrupt(EPWMx_INT) Status Flag + * Bit 2: ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag + * Bit 3: ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag + * + * This function returns the event status flags + */ +/* SourceId : ETPWM_SourceId_042 */ +/* DesignId : ETPWM_DesignId_042 */ +/* Requirements : CONQ_EPWM_SR47 */ +uint16 etpwmGetEventStatus( etpwmBASE_t * etpwm ) +{ + return etpwm->ETFLG; +} + +/** @fn void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) + * @brief Clear event status flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param events status flag (flags can be ORed) + * - Event_Interrupt + * - Event_SOCA + * - Event_SOCB + * + * This function clears the event status flags + */ +/* SourceId : ETPWM_SourceId_043 */ +/* DesignId : ETPWM_DesignId_043 */ +/* Requirements : CONQ_EPWM_SR48 */ +void etpwmClearEventFlag( etpwmBASE_t * etpwm, etpwmEvent_t events ) +{ + etpwm->ETCLR = events; +} + +/** @fn void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) + * @brief Force an event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @return events (events can be ORed) + * - Event_Interrupt + * - Event_SOCA + * - Event_SOCB + * + * This function forces an event + */ +/* SourceId : ETPWM_SourceId_044 */ +/* DesignId : ETPWM_DesignId_044 */ +/* Requirements : CONQ_EPWM_SR49 */ +void etpwmTriggerEvent( etpwmBASE_t * etpwm, etpwmEvent_t events ) +{ + etpwm->ETFRC = events; +} + +/** @fn void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, + * etpwmDigitalCompareConfig_t digitalcompareconfig) + * @brief Enable and configure digital compare events + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param digitalcompareconfig Digital Compare modue configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmDigitalCompareConfig_t config1 + * config1.DCAH_src = TZ1 + * config1.DCAL_src = TZ2 + * config1.DCBH_src = TZ1 + * config1.DCBL_src = TZ3 + * config1.DCAEVT1_event = DCAH_High + * config1.DCAEVT2_event = DCAL_High + * config1.DCBEVT1_event = DCBL_High + * config1.DCBEVT2_event = DCBL_High_DCBH_low + * etpwmEnableDigitalCompareEvents(etpwmREG1, config1) + * + * This function enbales and configures the digital compare events. HTis function can + * also be used to disable digital compare events + */ +/* SourceId : ETPWM_SourceId_045 */ +/* DesignId : ETPWM_DesignId_045 */ +/* Requirements : CONQ_EPWM_SR41 */ +void etpwmEnableDigitalCompareEvents( etpwmBASE_t * etpwm, + etpwmDigitalCompareConfig_t digitalcompareconfig ) +{ + etpwm->DCTRIPSEL = ( ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAH_src << 0U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAL_src << 4U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBH_src << 8U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBL_src + << 12U ) ); + + etpwm->TZDCSEL = ( ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAEVT1_event << 0U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAEVT2_event + << 3U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBEVT1_event + << 6U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBEVT2_event + << 9U ) ); +} + +/** @fn void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_046 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm1GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM1_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM1_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM1_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM1_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM1_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM1_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM1_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM1_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM1_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM1_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM1_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM1_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM1_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM1_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM1_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM1_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM1_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM1_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM1_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM1_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM1_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM1_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM1_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM1_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG1->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG1->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG1->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG1->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG1->CMPA; + config_reg->CONFIG_CMPB = etpwmREG1->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG1->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG1->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG1->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG1->DBRED; + config_reg->CONFIG_DBFED = etpwmREG1->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG1->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG1->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG1->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG1->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG1->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG1->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG1->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG1->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG1->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG1->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG1->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG1->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG1->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG1->DCFWINDOWCNT; + } +} + +/** @fn void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_47 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm2GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM2_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM2_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM2_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM2_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM2_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM2_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM2_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM2_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM2_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM2_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM2_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM2_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM2_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM2_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM2_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM2_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM2_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM2_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM2_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM2_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM2_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM2_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM2_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM2_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM2_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG2->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG2->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG2->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG2->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG2->CMPA; + config_reg->CONFIG_CMPB = etpwmREG2->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG2->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG2->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG2->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG2->DBRED; + config_reg->CONFIG_DBFED = etpwmREG2->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG2->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG2->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG2->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG2->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG2->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG2->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG2->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG2->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG2->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG2->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG2->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG2->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG2->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG2->DCFWINDOWCNT; + } +} + +/** @fn void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_048 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm3GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM3_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM3_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM3_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM3_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM3_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM3_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM3_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM3_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM3_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM3_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM3_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM3_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM3_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM3_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM3_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM3_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM3_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM3_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM3_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM3_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM3_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM3_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM3_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM3_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM3_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG3->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG3->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG3->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG3->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG3->CMPA; + config_reg->CONFIG_CMPB = etpwmREG3->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG3->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG3->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG3->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG3->DBRED; + config_reg->CONFIG_DBFED = etpwmREG3->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG3->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG3->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG3->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG3->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG3->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG3->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG3->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG3->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG3->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG3->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG3->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG3->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG3->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG3->DCFWINDOWCNT; + } +} + +/** @fn void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_049 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm4GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM4_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM4_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM4_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM4_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM4_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM4_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM4_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM4_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM4_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM4_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM4_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM4_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM4_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM4_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM4_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM4_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM4_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM4_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM4_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM4_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM4_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM4_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM4_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM4_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM4_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG4->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG4->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG4->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG4->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG4->CMPA; + config_reg->CONFIG_CMPB = etpwmREG4->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG4->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG4->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG4->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG4->DBRED; + config_reg->CONFIG_DBFED = etpwmREG4->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG4->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG4->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG4->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG4->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG4->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG4->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG4->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG4->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG4->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG4->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG4->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG4->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG4->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG4->DCFWINDOWCNT; + } +} + +/** @fn void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_050 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm5GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM5_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM5_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM5_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM5_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM5_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM5_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM5_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM5_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM5_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM5_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM5_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM5_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM5_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM5_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM5_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM5_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM5_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM5_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM5_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM5_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM5_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM5_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM5_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM5_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM5_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG5->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG5->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG5->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG5->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG5->CMPA; + config_reg->CONFIG_CMPB = etpwmREG5->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG5->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG5->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG5->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG5->DBRED; + config_reg->CONFIG_DBFED = etpwmREG5->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG5->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG5->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG5->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG5->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG5->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG5->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG5->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG5->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG5->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG5->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG5->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG5->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG5->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG5->DCFWINDOWCNT; + } +} + +/** @fn void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_051 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm6GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM6_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM6_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM6_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM6_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM6_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM6_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM6_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM6_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM6_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM6_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM6_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM6_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM6_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM6_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM6_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM6_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM6_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM6_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM6_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM6_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM6_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM6_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM6_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM6_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM6_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG6->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG6->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG6->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG6->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG6->CMPA; + config_reg->CONFIG_CMPB = etpwmREG6->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG6->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG6->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG6->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG6->DBRED; + config_reg->CONFIG_DBFED = etpwmREG6->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG6->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG6->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG6->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG6->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG6->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG6->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG6->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG6->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG6->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG6->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG6->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG6->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG6->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG6->DCFWINDOWCNT; + } +} + +/** @fn void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_052 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm7GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM7_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM7_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM7_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM7_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM7_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM7_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM7_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM7_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM7_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM7_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM7_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM7_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM7_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM7_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM7_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM7_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM7_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM7_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM7_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM7_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM7_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM7_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM7_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM7_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG7->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG7->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG7->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG7->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG7->CMPA; + config_reg->CONFIG_CMPB = etpwmREG7->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG7->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG7->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG7->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG7->DBRED; + config_reg->CONFIG_DBFED = etpwmREG7->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG7->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG7->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG7->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG7->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG7->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG7->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG7->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG7->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG7->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG7->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG7->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG7->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG7->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG7->DCFWINDOWCNT; + } +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c new file mode 100644 index 00000000000..1ba9c6cabb9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c @@ -0,0 +1,505 @@ +/** @file gio.c + * @brief GIO Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "gio.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void gioInit(void) + * @brief Initializes the GIO Driver + * + * This function initializes the GIO module and set the GIO ports + * to the initial values. + */ +/* SourceId : GIO_SourceId_001 */ +/* DesignId : GIO_DesignId_001 */ +/* Requirements : CONQ_GIO_SR2 */ +void gioInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** bring GIO module out of reset */ + gioREG->GCR0 = 1U; + gioREG->ENACLR = 0xFFU; + gioREG->LVLCLR = 0xFFU; + + /** @b initialize @b Port @b A */ + + /** - Port A output values */ + gioPORTA->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A direction */ + gioPORTA->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A open drain enable */ + gioPORTA->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown selection */ + gioPORTA->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown enable*/ + gioPORTA->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** @b initialize @b Port @b B */ + + /** - Port B output values */ + gioPORTB->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B direction */ + gioPORTB->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B open drain enable */ + gioPORTB->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown selection */ + gioPORTB->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown enable*/ + gioPORTB->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b interrupts */ + + /** - interrupt polarity */ + gioREG->POL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - interrupt level */ + gioREG->LVLSET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - clear all pending interrupts */ + gioREG->FLG = 0xFFU; + + /** - enable interrupts */ + gioREG->ENASET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir) + * @brief Set Port Direction + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] dir value to write to DIR register + * + * Set the direction of GIO pins at runtime. + */ +/* SourceId : GIO_SourceId_002 */ +/* DesignId : GIO_DesignId_002 */ +/* Requirements : CONQ_GIO_SR3 */ +void gioSetDirection( gioPORT_t * port, uint32 dir ) +{ + port->DIR = dir; +} + +/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * @param[in] value binary value to write to bit + * + * Writes a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_003 */ +/* DesignId : GIO_DesignId_003 */ +/* Requirements : CONQ_GIO_SR4 */ +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( value != 0U ) + { + port->DSET = ( uint32 ) 1U << bit; + } + else + { + port->DCLR = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioSetPort(gioPORT_t *port, uint32 value) + * @brief Write Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] value value to write to port + * + * Writes a value to all pin of a given GIO port + */ +/* SourceId : GIO_SourceId_004 */ +/* DesignId : GIO_DesignId_004 */ +/* Requirements : CONQ_GIO_SR5 */ +void gioSetPort( gioPORT_t * port, uint32 value ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + port->DOUT = value; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit) + * @brief Read Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Reads a the current value from the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_005 */ +/* DesignId : GIO_DesignId_005 */ +/* Requirements : CONQ_GIO_SR8 */ +uint32 gioGetBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return ( port->DIN >> bit ) & 1U; +} + +/** @fn uint32 gioGetPort(gioPORT_t *port) + * @brief Read Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * + * Reads a the current value of a given GIO port + */ +/* SourceId : GIO_SourceId_006 */ +/* DesignId : GIO_DesignId_006 */ +/* Requirements : CONQ_GIO_SR7 */ +uint32 gioGetPort( gioPORT_t * port ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return port->DIN; +} + +/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Toggle a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_007 */ +/* DesignId : GIO_DesignId_007 */ +/* Requirements : CONQ_GIO_SR6 */ +void gioToggleBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( port->DIN & ( uint32 ) ( ( uint32 ) 1U << bit ) ) != 0U ) + { + port->DCLR = ( uint32 ) 1U << bit; + } + else + { + port->DSET = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioEnableNotification(uint32 bit) + * @brief Enable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Enables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_008 */ +/* DesignId : GIO_DesignId_008 */ +/* Requirements : CONQ_GIO_SR9 */ +void gioEnableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENASET = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENASET = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioDisableNotification(uint32 bit) + * @brief Disable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Disables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_009 */ +/* DesignId : GIO_DesignId_009 */ +/* Requirements : CONQ_GIO_SR10 */ +void gioDisableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENACLR = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENACLR = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : GIO_SourceId_010 */ +/* DesignId : GIO_DesignId_010 */ +/* Requirements : CONQ_GIO_SR11 */ +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_INTDET = GIO_INTDET_CONFIGVALUE; + config_reg->CONFIG_POL = GIO_POL_CONFIGVALUE; + config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE; + config_reg->CONFIG_LVLSET = GIO_LVLSET_CONFIGVALUE; + + config_reg->CONFIG_PORTADIR = GIO_PORTADIR_CONFIGVALUE; + config_reg->CONFIG_PORTAPDR = GIO_PORTAPDR_CONFIGVALUE; + config_reg->CONFIG_PORTAPSL = GIO_PORTAPSL_CONFIGVALUE; + config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE; + + config_reg->CONFIG_PORTBDIR = GIO_PORTBDIR_CONFIGVALUE; + config_reg->CONFIG_PORTBPDR = GIO_PORTBPDR_CONFIGVALUE; + config_reg->CONFIG_PORTBPSL = GIO_PORTBPSL_CONFIGVALUE; + config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_INTDET = gioREG->INTDET; + config_reg->CONFIG_POL = gioREG->POL; + config_reg->CONFIG_INTENASET = gioREG->ENASET; + config_reg->CONFIG_LVLSET = gioREG->LVLSET; + + config_reg->CONFIG_PORTADIR = gioPORTA->DIR; + config_reg->CONFIG_PORTAPDR = gioPORTA->PDR; + config_reg->CONFIG_PORTAPSL = gioPORTA->PSL; + config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PORTBDIR = gioPORTB->DIR; + config_reg->CONFIG_PORTBPDR = gioPORTB->PDR; + config_reg->CONFIG_PORTBPSL = gioPORTB->PSL; + config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS; + } +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c new file mode 100644 index 00000000000..8e835f9acf5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c @@ -0,0 +1,2921 @@ +/** @file het.c + * @brief HET Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "het.h" +#include "sys_vim.h" +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Global variables */ + +static const uint32 s_het1pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +static const uint32 s_het2pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het1PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het1PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het2PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het2PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/** @fn void hetInit(void) + * @brief Initializes the het Driver + * + * This function initializes the het 1 module. + */ +/* SourceId : HET_SourceId_001 */ +/* DesignId : HET_DesignId_001 */ +/* Requirements : CONQ_HET_SR10 */ +void hetInit( void ) +{ + /** @b initialize @b HET */ + + /** - Set HET pins default output value */ + hetREG1 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG1->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG1->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG1->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG1->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG1->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG1->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG1->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG1->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG1->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM1, + ( const void * ) het1PROGRAM, + sizeof( het1PROGRAM ) ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG1->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG1->INTENAC = 0xFFFFFFFFU; + hetREG1->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG1->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @b initialize @b HET 2 */ + + /** - Set HET pins default output value */ + hetREG2 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG2->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG2->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG2->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG2->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG2->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG2->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG2->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG2->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Release from reset */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM2, + ( const void * ) het2PROGRAM, + sizeof( het2PROGRAM ) ); + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG2->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG2->INTENAC = 0xFFFFFFFFU; + hetREG2->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG2->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Start pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Start the given pwm signal + */ +/* SourceId : HET_SourceId_002 */ +/* DesignId : HET_DesignId_002 */ +/* Requirements : CONQ_HET_SR11 */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control |= 0x00400000U; +} + +/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Stop pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Stop the given pwm signal + */ +/* SourceId : HET_SourceId_003 */ +/* DesignId : HET_DesignId_003 */ +/* Requirements : CONQ_HET_SR12 */ +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control &= ~( uint32 ) 0x00400000U; +} + +/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty) + * @brief Set duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] pwmDuty duty cycle in %. + * + * Sets a new duty cycle on the given pwm signal + */ +/* SourceId : HET_SourceId_004 */ +/* DesignId : HET_DesignId_004 */ +/* Requirements : CONQ_HET_SR13 */ +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + uint32 pwmPeriod = hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U; + pwmPeriod = pwmPeriod >> 7U; + + if( hetRAM == hetRAM1 ) + { + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + if( pwmDuty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( pwmDuty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data = ( ( ( pwmPeriod * pwmDuty ) / 100U ) + << 7U ) + + 128U; +} + +/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) +* @brief Set period +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] signal signal + - duty cycle in %. +* - period period in us. +* +* Sets a new pwm signal +*/ +/* SourceId : HET_SourceId_005 */ +/* DesignId : HET_DesignId_005 */ +/* Requirements : CONQ_HET_SR14 */ +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + float64 pwmPeriod = 0.0F; + + if( hetRAM == hetRAM1 ) + { + pwmPeriod = ( signal.period * 1000.0F ) / 853.333F; + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPeriod = ( signal.period * 1000.0F ) / 853.333F; + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + if( signal.duty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( signal.duty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Data = ( ( ( ( uint32 ) pwmPeriod * signal.duty ) / 100U ) << 7U ) + 128U; + hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data = ( ( uint32 ) pwmPeriod << 7U ) + - 128U; +} + +/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) + * @brief Get duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given pwm signal. + */ +/* SourceId : HET_SourceId_006 */ +/* DesignId : HET_DesignId_006 */ +/* Requirements : CONQ_HET_SR15 */ +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data - 128U ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } +} + +/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_007 */ +/* DesignId : HET_DesignId_007 */ +/* Requirements : CONQ_HET_SR16 */ +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->FLG = notification << ( pwm << 1U ); + hetREG->INTENAS = notification << ( pwm << 1U ); +} + +/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_008 */ +/* DesignId : HET_DesignId_008 */ +/* Requirements : CONQ_HET_SR17 */ +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->INTENAC = notification << ( pwm << 1U ); +} + +/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Resets edge counter to 0 + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Reset edge counter to 0. + */ +/* SourceId : HET_SourceId_009 */ +/* DesignId : HET_DesignId_009 */ +/* Requirements : CONQ_HET_SR19 */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + hetRAM->Instruction[ edge + 17U ].Data = 0U; +} + +/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Get current edge counter value + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Gets current edge counter value. + */ +/* SourceId : HET_SourceId_010 */ +/* DesignId : HET_DesignId_010 */ +/* Requirements : CONQ_HET_SR20 */ +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + return hetRAM->Instruction[ edge + 17U ].Data >> 7U; +} + +/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_011 */ +/* DesignId : HET_DesignId_011 */ +/* Requirements : CONQ_HET_SR21 */ +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->FLG = ( uint32 ) 0x20000U << edge; + hetREG->INTENAS = ( uint32 ) 0x20000U << edge; +} + +/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_012 */ +/* DesignId : HET_DesignId_012 */ +/* Requirements : CONQ_HET_SR22 */ +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->INTENAC = ( uint32 ) 0x20000U << edge; +} + +/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal) + * @brief Get capture signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] cap captured signal: + * - cap0: Captured signal 0 + * - cap1: Captured signal 1 + * - cap2: Captured signal 2 + * - cap3: Captured signal 3 + * - cap4: Captured signal 4 + * - cap5: Captured signal 5 + * - cap6: Captured signal 6 + * - cap7: Captured signal 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given capture signal. + */ +/* SourceId : HET_SourceId_013 */ +/* DesignId : HET_DesignId_013 */ +/* Requirements : CONQ_HET_SR24 */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( cap << 1U ) + 25U ].Data ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( cap << 1U ) + 26U ].Data ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } +} + +/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Resets timestamp + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * + * Resets loop count based timestamp. + */ +/* SourceId : HET_SourceId_014 */ +/* DesignId : HET_DesignId_014 */ +/* Requirements : CONQ_HET_SR25 */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ) +{ + hetRAM->Instruction[ 0U ].Data = 0U; +} + +/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Returns timestamp + * + * Returns loop count based timestamp. + */ +/* SourceId : HET_SourceId_015 */ +/* DesignId : HET_DesignId_015 */ +/* Requirements : CONQ_HET_SR26 */ +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ) +{ + return hetRAM->Instruction[ 57U ].Data; +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_016 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : CONQ_HET_SR29 */ +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET1_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET1_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET1_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET1_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET1_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET1_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET1_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET1_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET1_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET1_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET1_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG1->GCR; + config_reg->CONFIG_PFR = hetREG1->PFR; + config_reg->CONFIG_INTENAS = hetREG1->INTENAS; + config_reg->CONFIG_INTENAC = hetREG1->INTENAC; + config_reg->CONFIG_PRY = hetREG1->PRY; + config_reg->CONFIG_AND = hetREG1->AND; + config_reg->CONFIG_HRSH = hetREG1->HRSH; + config_reg->CONFIG_XOR = hetREG1->XOR; + config_reg->CONFIG_DIR = hetREG1->DIR; + config_reg->CONFIG_PDR = hetREG1->PDR; + config_reg->CONFIG_PULDIS = hetREG1->PULDIS; + config_reg->CONFIG_PSL = hetREG1->PSL; + config_reg->CONFIG_PCR = hetREG1->PCR; + } +} + +/** @fn void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_017 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : CONQ_HET_SR29 */ +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET2_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET2_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET2_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET2_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET2_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET2_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET2_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET2_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET2_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET2_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET2_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET2_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET2_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG2->GCR; + config_reg->CONFIG_PFR = hetREG2->PFR; + config_reg->CONFIG_INTENAS = hetREG2->INTENAS; + config_reg->CONFIG_INTENAC = hetREG2->INTENAC; + config_reg->CONFIG_PRY = hetREG2->PRY; + config_reg->CONFIG_AND = hetREG2->AND; + config_reg->CONFIG_HRSH = hetREG2->HRSH; + config_reg->CONFIG_XOR = hetREG2->XOR; + config_reg->CONFIG_DIR = hetREG2->DIR; + config_reg->CONFIG_PDR = hetREG2->PDR; + config_reg->CONFIG_PULDIS = hetREG2->PULDIS; + config_reg->CONFIG_PSL = hetREG2->PSL; + config_reg->CONFIG_PCR = hetREG2->PCR; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c new file mode 100644 index 00000000000..fb2de140c7b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c @@ -0,0 +1,1005 @@ +/** @file i2c.c + * @brief I2C Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "i2c.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_i2CTransfer + * @brief Interrupt mode globals + * + */ +static struct g_i2cTransfer +{ + uint32 mode; + uint32 length; + uint8 * data; +} g_i2cTransfer_t[ 2U ]; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : I2C_SourceId_001 */ +/* DesignId : I2C_DesignId_001 */ +/* Requirements : CONQ_I2C_SR5 */ +/** @fn void i2cInit(void) + * @brief Initializes the i2c Driver + * + * This function initializes the i2c module. + */ +void i2cInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + /** @b initialize @b I2C1 */ + + /** - i2c Enter reset */ + i2cREG1->MDR = ( uint32 ) ( ( uint32 ) 0U << 5U ); + + /** - set i2c mode */ + i2cREG1->MDR = ( uint32 ) ( ( uint32 ) 0U << 15U ) /* nack mode */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* free running */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* start condition - master mode + only */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* stop condition */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* Master/Slave mode */ + | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) /* Transmitter/receiver */ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) /* xpanded address */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* repeat mode */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* digital loopback */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* start byte - master only */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* free data format */ + | ( uint32 ) ( ( uint32 ) I2C_8_BIT ); /* bit count */ + + /** - set i2c extended mode */ + i2cREG1->EMDR = ( uint32 ) 0U << 1U; /* Ignore Nack Enable/Disable */ + + /** - set i2c Backward Compatibility mode */ + i2cREG1->EMDR |= 0U; + + /** - Disable DMA */ + i2cREG1->DMACR = 0x00U; + + /** - set i2c data count */ + i2cREG1->CNT = 8U; + + /** - disable all interrupts */ + i2cREG1->IMR = 0x00U; + + /** - set prescale */ + i2cREG1->PSC = 8U; + + /** - set clock rate */ + i2cREG1->CKH = 37U; + i2cREG1->CKL = 37U; + + /** - set i2c pins functional mode */ + i2cREG1->PFNC = ( 0U ); + + /** - set i2c pins default output value */ + i2cREG1->DOUT = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG1->DIR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG1->PDR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG1->PDIS = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG1->PSEL = ( uint32 ) ( ( uint32 ) 1U << 1U ) /* sda pin */ + | ( uint32 ) ( 1U ); /* scl pin */ + + /** - set interrupt enable */ + i2cREG1->IMR = ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Address as slave interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Stop Condition detect interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Transmit data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Receive data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Register Access ready interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* No Acknowledgment interrupt */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Arbitration Lost interrupt */ + + i2cREG1->MDR |= ( uint32 ) I2C_RESET_OUT; /* i2c out of reset */ + + /** - initialize global transfer variables */ + g_i2cTransfer_t[ 0U ].mode = ( uint32 ) 0U << 4U; + g_i2cTransfer_t[ 0U ].length = 0U; + + /** @b initialize @b I2C2 */ + + /** - i2c Enter reset */ + i2cREG2->MDR = ( uint32 ) ( ( uint32 ) 0U << 5U ); + + /** - set i2c mode */ + i2cREG2->MDR = ( uint32 ) ( ( uint32 ) 0U << 15U ) /* nack mode */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* free running */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* start condition - master mode + only */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* stop condition */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* Master/Slave mode */ + | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) /* Transmitter/receiver */ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) /* Expanded address */ + | ( uint32 ) ( ( uint32 ) 0 << 7U ) /* repeat mode */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* digital loopback */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* start byte - master only */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* free data format */ + | ( uint32 ) ( I2C_2_BIT ); /* bit count */ + + /** - set i2c extended mode */ + i2cREG2->EMDR = ( uint32 ) 0U << 1U; /* Ignore Nack Enable/Disable */ + + /** - set i2c Backward Compatibility mode */ + i2cREG2->EMDR |= 0U; + + /** - Disable DMA */ + i2cREG2->DMACR = 0x00U; + + /** - set i2c data count */ + i2cREG2->CNT = 8U; + + /** - disable all interrupts */ + i2cREG2->IMR = 0x00U; + + /** - set prescale */ + i2cREG2->PSC = 8U; + + /** - set clock rate */ + i2cREG2->CKH = 37U; + i2cREG2->CKL = 37U; + + /** - set i2c pins functional mode */ + i2cREG2->PFNC = ( 0U ); + + /** - set i2c pins default output value */ + i2cREG2->DOUT = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG2->DIR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG2->PDR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG2->PDIS = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG2->PSEL = ( uint32 ) ( ( uint32 ) 1U << 1U ) /* sda pin */ + | ( uint32 ) ( 1U ); /* scl pin */ + + /** - set interrupt enable */ + i2cREG2->IMR = ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Address as slave interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Stop Condition detect interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Transmit data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Receive data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Register Access ready interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* No Acknowledgment interrupt */ + | ( uint32 ) ( 0U ); /* Arbitration Lost interrupt */ + + i2cREG2->MDR |= ( uint32 ) I2C_RESET_OUT; /* i2c out of reset */ + + /** - initialize global transfer variables */ + g_i2cTransfer_t[ 1U ].mode = ( uint32 ) 0U << 4U; + g_i2cTransfer_t[ 1U ].length = 0U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_002 */ +/* DesignId : I2C_DesignId_002 */ +/* Requirements : CONQ_I2C_SR6 */ +/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd) + * @brief Set I2C Own Address + * @param[in] oadd - I2C Own address (7-bit or 10 -bit address) + * @param[in] i2c - i2c module base address + * Set the Own address of the I2C module. + */ +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ) +{ + i2c->OAR = oadd; /* set own address */ +} + +/* SourceId : I2C_SourceId_003 */ +/* DesignId : I2C_DesignId_003 */ +/* Requirements : CONQ_I2C_SR7 */ +/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd) + * @brief Set Port Direction + * @param[in] sadd - I2C Slave address + * @param[in] i2c - i2c module base address + * Set the Slave address to communicate which is must in Master mode. + */ +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ) +{ + i2c->SAR = sadd; /* set slave address */ +} + +/* SourceId : I2C_SourceId_004 */ +/* DesignId : I2C_DesignId_004 */ +/* Requirements : CONQ_I2C_SR8 */ +/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] i2c - i2c module base address + * @param[in] baud - baudrate in KHz + * + * Change the i2c baudrate at runtime. The I2C module needs to be taken to reset( nIRS=0 + * in I2CMDR) in order to change baud rate. + */ +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ) +{ + uint32 prescale; + uint32 d; + uint32 ck; + float64 vclk = 75.000F * 1000000.0F; + float64 divider = 0.0F; + uint32 temp = 0U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + divider = vclk / 8000000.0F; + prescale = ( uint32 ) divider - 1U; + + if( prescale >= 2U ) + { + d = 5U; + } + else + { + d = ( prescale != 0U ) ? 6U : 7U; + } + + temp = 2U * baud * 1000U * ( prescale + 1U ); + divider = vclk / ( ( float64 ) temp ); + ck = ( uint32 ) divider - d; + + i2c->PSC = prescale; + i2c->CKH = ck; + i2c->CKL = ck; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_005 */ +/* DesignId : I2C_DesignId_015 */ +/* Requirements : CONQ_I2C_SR20 */ +/** @fn void i2cSetStart(i2cBASE_t *i2c) + * @brief Set i2c start condition + * @param[in] i2c - i2c module base address + * Set i2c to generate a start bit (Only in Master mode) + */ +void i2cSetStart( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + i2c->MDR |= ( uint32 ) I2C_START_COND; /* set start condition */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_006 */ +/* DesignId : I2C_DesignId_016 */ +/* Requirements : CONQ_I2C_SR21 */ +/** @fn void i2cSetStop(i2cBASE_t *i2c) + * @brief Set i2c stop condition + * @param[in] i2c - i2c module base address + * Set i2c to generate a stop bit (Only in Master mode) + */ +void i2cSetStop( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + i2c->MDR |= ( uint32 ) I2C_STOP_COND; /* generate stop condition */ + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_007 */ +/* DesignId : I2C_DesignId_017 */ +/* Requirements : CONQ_I2C_SR22 */ +/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32 cnt) + * @brief Set i2c data count + * @param[in] i2c - i2c module base address + * @param[in] cnt - data count + * Set i2c count to a transfer value after which the stop condition needs to be + * generated. (Only in Master Mode) + */ +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + i2c->CNT = cnt; /* set i2c count */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_008 */ +/* DesignId : I2C_DesignId_005 */ +/* Requirements : CONQ_I2C_SR9 */ +/** @fn uint32 i2cIsTxReady(i2cBASE_t *i2c) + * @brief Check if Tx buffer empty + * @param[in] i2c - i2c module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 i2cIsTxReady( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return i2c->STR & ( uint32 ) I2C_TX_INT; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_009 */ +/* DesignId : I2C_DesignId_006 */ +/* Requirements : CONQ_I2C_SR10 */ +/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8 byte) + * @brief Send Byte + * @param[in] i2c - i2c module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use i2cIsTxReady to check for Tx buffer empty + * before calling i2cSendByte to avoid waiting. + */ +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_TX_INT ) == 0U ) + { + } /* Wait */ + i2c->DXR = ( uint32 ) byte; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_010 */ +/* DesignId : I2C_DesignId_007 */ +/* Requirements : CONQ_I2C_SR11 */ +/** @fn void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] i2c - i2c module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, i2cSend must not be called again until the + * transfer is complete, when the i2cNotification callback will + * be called. In polling mode, i2cSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( g_i2cTransfer_t[ index ].mode & ( uint32 ) I2C_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + i2c->DXR = ( uint32 ) *g_i2cTransfer_t[ index ].data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data++; + /* Length -1 since one data is written already */ + g_i2cTransfer_t[ index ].length = ( length - 1U ); + /* Enable Transmit Interrupt */ + i2c->IMR |= ( uint32 ) I2C_TX_INT; + } + else + { + /* send the data */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in + * Transmit/Receive polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_TX_INT ) == 0U ) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + i2c->DXR = ( uint32 ) *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; + length--; + } + } + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_011 */ +/* DesignId : I2C_DesignId_008 */ +/* Requirements : CONQ_I2C_SR12 */ +/** @fn uint32 i2cIsRxReady(i2cBASE_t *i2c) + * @brief Check if Rx buffer full + * @param[in] i2c - i2c module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 i2cIsRxReady( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return i2c->STR & ( uint32 ) I2C_RX_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_012 */ +/* DesignId : I2C_DesignId_023 */ +/* Requirements : CONQ_I2C_SR13 */ +/** @fn uint32 i2cIsStopDetected(i2cBASE_t *i2c) + * @brief Check if Stop Condition Detected + * @param[in] i2c - i2c module base address + * + * @return The Stop Condition Detected flag + * + * Checks to see if the Stop Condition Detected flag is set, + * returns 0 if flags not set otherwise will return the Stop + * Condition Detected flag itself. + */ +uint32 i2cIsStopDetected( i2cBASE_t * i2c ) +{ + return i2c->STR & ( uint32 ) I2C_SCD_INT; +} + +/* SourceId : I2C_SourceId_013 */ +/* DesignId : I2C_DesignId_010 */ +/* Requirements : CONQ_I2C_SR15 */ +/** @fn uint32 i2cRxError(i2cBASE_t *i2c) + * @brief Return Rx Error flags + * @param[in] i2c - i2c module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +uint32 i2cRxError( i2cBASE_t * i2c ) +{ + uint32 status = i2c->STR & ( ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + i2c->STR = ( uint32 ) ( ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : I2C_SourceId_014 */ +/* DesignId : I2C_DesignId_009 */ +/* Requirements : CONQ_I2C_SR14 */ +/** @fn void i2cClearSCD(i2cBASE_t *i2c) + * @brief Clears the Stop condition detect flags. + * @param[in] i2c - i2c module base address + * + * This function is called to clear the Stop condition detect(SCD) flag + */ +void i2cClearSCD( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + i2c->STR = ( uint32 ) I2C_SCD_INT; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_015 */ +/* DesignId : I2C_DesignId_011 */ +/* Requirements : CONQ_I2C_SR16 */ +/** @fn uint8 i2cReceiveByte(i2cBASE_t *i2c) + * @brief Receive Byte + * @param[in] i2c - i2c module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use i2cIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +uint8 i2cReceiveByte( i2cBASE_t * i2c ) +{ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_RX_INT ) == 0U ) + { + } /* Wait */ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + return ( ( uint8 ) i2c->DRR ); +} + +/* SourceId : I2C_SourceId_016 */ +/* DesignId : I2C_DesignId_012 */ +/* Requirements : CONQ_I2C_SR17 */ +/** @fn void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] i2c - i2c module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, i2cReceive must not be called + * again until the transfer is complete, when the i2cNotification + * callback will be called. In polling mode, i2cReceive will not + * return until the transfer is complete. + */ +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + if( ( i2c->IMR & ( uint32 ) I2C_RX_INT ) != 0U ) + { + /* we are in interrupt mode */ + /* clear error flags */ + i2c->STR = ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT; + + g_i2cTransfer_t[ index ].length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data = data; + } + else + { /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive + polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_RX_INT ) == 0U ) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( ( uint8 ) i2c->DRR ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_017 */ +/* DesignId : I2C_DesignId_018 */ +/* Requirements : CONQ_I2C_SR24 */ +/** @fn void i2cEnableLoopback(i2cBASE_t *i2c) + * @brief Enable Loopback mode for self test + * @param[in] i2c - i2c module base address + * + * This function enables the Loopback mode for self test. + */ +void i2cEnableLoopback( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + /* enable digital loopback */ + i2c->MDR |= ( ( uint32 ) 1U << 6U ); + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_018 */ +/* DesignId : I2C_DesignId_019 */ +/* Requirements : CONQ_I2C_SR25 */ +/** @fn void i2cDisableLoopback(i2cBASE_t *i2c) + * @brief Enable Loopback mode for self test + * @param[in] i2c - i2c module base address + * + * This function disable the Loopback mode. + */ +void i2cDisableLoopback( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + i2c->MDR &= 0xFFFFFFBFU; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_019 */ +/* DesignId : I2C_DesignId_013 */ +/* Requirements : CONQ_I2C_SR18 */ +/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Enable interrupts + * @param[in] i2c - i2c module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * i2c_FE_INT - framing error, + * i2c_OE_INT - overrun error, + * i2c_PE_INT - parity error, + * i2c_RX_INT - receive buffer ready, + * i2c_TX_INT - transmit buffer ready, + * i2c_WAKE_INT - wakeup, + * i2c_BREAK_INT - break detect + */ +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + g_i2cTransfer_t[ index ].mode |= ( flags & ( uint32 ) I2C_TX_INT ); + i2c->IMR = ( flags & ( uint32 ) ( ~( uint32 ) I2C_TX_INT ) ); +} + +/* SourceId : I2C_SourceId_020 */ +/* DesignId : I2C_DesignId_014 */ +/* Requirements : CONQ_I2C_SR19 */ +/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Disable interrupts + * @param[in] i2c - i2c module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * i2c_FE_INT - framing error, + * i2c_OE_INT - overrun error, + * i2c_PE_INT - parity error, + * i2c_RX_INT - receive buffer ready, + * i2c_TX_INT - transmit buffer ready, + * i2c_WAKE_INT - wakeup, + * i2c_BREAK_INT - break detect + */ +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + uint32 int_mask; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + g_i2cTransfer_t[ index ].mode &= ( uint32 ) ~( flags & ( uint32 ) I2C_TX_INT ); + int_mask = i2c->IMR & ( uint32 ) ( ~( uint32 ) ( flags | ( uint32 ) I2C_TX_INT ) ); + i2c->IMR = int_mask; +} + +/* SourceId : I2C_SourceId_021 */ +/* DesignId : I2C_DesignId_020 */ +/* Requirements : CONQ_I2C_SR23 */ +/** @fn i2cSetMode(i2cBASE_t *i2c, uint32 mode) + * @brief Sets Master or Slave mode. + * @param[in] i2c - i2c module base address + * @param[in] mode - Mode can be either: + * I2C_MASTER - Master Mode, + * I2C_SLAVE - Slave Mode + */ +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ) +{ + uint32 temp_mdr; + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* set Master or Slave Mode */ + temp_mdr = ( i2c->MDR & ( ~I2C_MASTER ) ); + i2c->MDR = ( temp_mdr | mode ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_022 */ +/* DesignId : I2C_DesignId_021 */ +/* Requirements : CONQ_I2C_SR28 */ +/** @fn void i2c1GetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the I2C1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OAR = I2C1_OAR_CONFIGVALUE; + config_reg->CONFIG_IMR = I2C1_IMR_CONFIGVALUE; + config_reg->CONFIG_CLKL = I2C1_CLKL_CONFIGVALUE; + config_reg->CONFIG_CLKH = I2C1_CLKH_CONFIGVALUE; + config_reg->CONFIG_CNT = I2C1_CNT_CONFIGVALUE; + config_reg->CONFIG_SAR = I2C1_SAR_CONFIGVALUE; + config_reg->CONFIG_MDR = I2C1_MDR_CONFIGVALUE; + config_reg->CONFIG_EMDR = I2C1_EMDR_CONFIGVALUE; + config_reg->CONFIG_PSC = I2C1_PSC_CONFIGVALUE; + config_reg->CONFIG_DMAC = I2C1_DMAC_CONFIGVALUE; + config_reg->CONFIG_FUN = I2C1_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = I2C1_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = I2C1_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = I2C1_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = I2C1_PSL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_OAR = i2cREG1->OAR; + config_reg->CONFIG_IMR = i2cREG1->IMR; + config_reg->CONFIG_CLKL = i2cREG1->CKL; + config_reg->CONFIG_CLKH = i2cREG1->CKH; + config_reg->CONFIG_CNT = i2cREG1->CNT; + config_reg->CONFIG_SAR = i2cREG1->SAR; + config_reg->CONFIG_MDR = i2cREG1->MDR; + config_reg->CONFIG_EMDR = i2cREG1->EMDR; + config_reg->CONFIG_PSC = i2cREG1->PSC; + config_reg->CONFIG_DMAC = i2cREG1->DMACR; + config_reg->CONFIG_FUN = i2cREG1->PFNC; + config_reg->CONFIG_DIR = i2cREG1->DIR; + config_reg->CONFIG_ODR = i2cREG1->PDR; + config_reg->CONFIG_PD = i2cREG1->PDIS; + config_reg->CONFIG_PSL = i2cREG1->PSEL; + } +} + +/* SourceId : I2C_SourceId_023 */ +/* DesignId : I2C_DesignId_021 */ +/* Requirements : CONQ_I2C_SR29 */ +/** @fn void i2c2GetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the I2C1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OAR = I2C2_OAR_CONFIGVALUE; + config_reg->CONFIG_IMR = I2C2_IMR_CONFIGVALUE; + config_reg->CONFIG_CLKL = I2C2_CLKL_CONFIGVALUE; + config_reg->CONFIG_CLKH = I2C2_CLKH_CONFIGVALUE; + config_reg->CONFIG_CNT = I2C2_CNT_CONFIGVALUE; + config_reg->CONFIG_SAR = I2C2_SAR_CONFIGVALUE; + config_reg->CONFIG_MDR = I2C2_MDR_CONFIGVALUE; + config_reg->CONFIG_EMDR = I2C2_EMDR_CONFIGVALUE; + config_reg->CONFIG_PSC = I2C2_PSC_CONFIGVALUE; + config_reg->CONFIG_DMAC = I2C2_DMAC_CONFIGVALUE; + config_reg->CONFIG_FUN = I2C2_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = I2C2_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = I2C2_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = I2C2_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = I2C2_PSL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_OAR = i2cREG2->OAR; + config_reg->CONFIG_IMR = i2cREG2->IMR; + config_reg->CONFIG_CLKL = i2cREG2->CKL; + config_reg->CONFIG_CLKH = i2cREG2->CKH; + config_reg->CONFIG_CNT = i2cREG2->CNT; + config_reg->CONFIG_SAR = i2cREG2->SAR; + config_reg->CONFIG_MDR = i2cREG2->MDR; + config_reg->CONFIG_EMDR = i2cREG2->EMDR; + config_reg->CONFIG_PSC = i2cREG2->PSC; + config_reg->CONFIG_DMAC = i2cREG2->DMACR; + config_reg->CONFIG_FUN = i2cREG2->PFNC; + config_reg->CONFIG_DIR = i2cREG2->DIR; + config_reg->CONFIG_ODR = i2cREG2->PDR; + config_reg->CONFIG_PD = i2cREG2->PDIS; + config_reg->CONFIG_PSL = i2cREG2->PSEL; + } +} + +/** @fn i2cSetDirection(i2cBASE_t *i2c, uint32 dir) + * @brief Sets I2C as transmitter or receiver. + * @param[in] i2c - i2c module base address + * @param[in] dir - This can be one of the following: + * I2C_TRANSMITTER - Transmit Mode, + * I2C_RECEIVER - Receive Mode + */ +/* SourceId : I2C_SourceId_026 */ +/* DesignId : */ +/* Requirements : */ +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ) +{ + /* USER CODE BEGIN (58) */ + /* USER CODE END */ + + /* set Transmit/Receive mode */ + i2c->MDR &= ~I2C_TRANSMITTER; + i2c->MDR |= dir; + + /* USER CODE BEGIN (59) */ + /* USER CODE END */ +} + +/** @fn i2cIsMasterReady(i2cBASE_t *i2c) + * @brief Indicates whether MST bit is set or cleared to indicate that stop + * condition was generated. This API should be called after Master Tx or Rx + * to check if the transaction is complete. + * @param[in] i2c - i2c module base address + * @return boolean value to indicate whether MST bit is cleared after STOP bit is + * generated. + * - TRUE, if MST bit is cleared. + * - FALSE, if MST bit is set. + */ +/* SourceId : I2C_SourceId_027 */ +/* DesignId : */ +/* Requirements : */ +bool i2cIsMasterReady( i2cBASE_t * i2c ) +{ + bool retVal = 0U; + /* USER CODE BEGIN (60) */ + /* USER CODE END */ + + /* check if MST bit is cleared. */ + if( ( i2c->MDR & I2C_MASTER ) == 0 ) + { + retVal = true; + } + else + { + retVal = false; + } + return retVal; + + /* USER CODE BEGIN (61) */ + /* USER CODE END */ +} + +/** @fn i2cIsBusBusy(i2cBASE_t *i2c) + * @brief Returns the state of the bus busy flag. True if it is set and false otherwise. + * @param[in] i2c - i2c module base address + * @return boolean value to indicate whether BB bit is set in the status register. + * - TRUE, if BB bit is set. + * - FALSE, if BB bit is cleared. + */ +/* SourceId : I2C_SourceId_028 */ +/* DesignId : */ +/* Requirements : */ +bool i2cIsBusBusy( i2cBASE_t * i2c ) +{ + bool retVal = 0U; + /* USER CODE BEGIN (62) */ + /* USER CODE END */ + + /* check if BB bit is set. */ + if( ( i2c->STR & I2C_BUSBUSY ) == I2C_BUSBUSY ) + { + retVal = true; + } + else + { + retVal = false; + } + return retVal; + + /* USER CODE BEGIN (63) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c new file mode 100644 index 00000000000..265d2415ba0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c @@ -0,0 +1,943 @@ +/** @file lin.c + * @brief LIN Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "lin.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : LIN_SourceId_001 */ +/* DesignId : LIN_DesignId_001 */ +/* Requirements : CONQ_LIN_SR5 */ +/** @fn void linInit(void) + * @brief Initializes the lin Driver + * + * This function initializes the lin module. + */ +void linInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG1->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG1->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG1->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module either as master/salve + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG1->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG1->MBRSR = ( uint32 ) 3370U; + + /** - Setup baud rate prescaler */ + linREG1->BRS = ( uint32 ) 233U; + + /** - Setup RX and TX reception masks */ + linREG1->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG1->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG1->FORMAT = ( ( linREG1->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG1->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG1->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG1->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG1->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG1->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG1->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG1->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG1->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG1->GCR1 |= 0x00000080U; + + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG2->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG2->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG2->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module either as master/salve + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG2->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG2->MBRSR = ( uint32 ) 3370U; + + /** - Setup baud rate prescaler */ + linREG2->BRS = ( uint32 ) 233U; + + /** - Setup RX and TX reception masks */ + linREG2->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG2->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG2->FORMAT = ( ( linREG2->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG2->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG2->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG2->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG2->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG2->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG2->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG2->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG2->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG2->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_002 */ +/* DesignId : LIN_DesignId_002 */ +/* Requirements : CONQ_LIN_SR6 */ +/** @fn void linSetFunctional(linBASE_t *lin, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] lin - lin module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCFUN register at runtime, this allows to + * dynamically change the functionality of the LIN pins between functional + * and GIO mode. + */ +void linSetFunctional( linBASE_t * lin, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + lin->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_003 */ +/* DesignId : LIN_DesignId_003 */ +/* Requirements : CONQ_LIN_SR7 */ +/** @fn void linSendHeader(linBASE_t *lin, uint8 identifier) + * @brief Send lin header. + * @param[in] lin - lin module base address + * @param[in] identifier - lin header id + * + * Send lin header including sync break field, sync field and identifier. + */ +void linSendHeader( linBASE_t * lin, uint8 identifier ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + lin->ID = ( ( lin->ID & 0xFFFFFF00U ) | ( uint32 ) identifier ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_004 */ +/* DesignId : LIN_DesignId_004 */ +/* Requirements : CONQ_LIN_SR8 */ +/** @fn void linSendWakupSignal(linBASE_t *lin) + * @brief Send lin wakeup signal. + * @param[in] lin - lin module base address + * + * Send lin wakeup signal to terminate the sleep mode of any lin node connected to the + * BUS. + */ +void linSendWakupSignal( linBASE_t * lin ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + lin->TDx[ 0U ] = 0xF0U; + lin->GCR2 |= 0x00000100U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_005 */ +/* DesignId : LIN_DesignId_005 */ +/* Requirements : CONQ_LIN_SR9 */ +/** @fn void linEnterSleep(linBASE_t *lin) + * @brief Take Module to Sleep. + * @param[in] lin - lin module base address + * + * Application must call this function to take Module to Sleep when Sleep command is + * received. This function can also be called to forcefully enter Sleep when no activity + * on BUS. + */ +void linEnterSleep( linBASE_t * lin ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + lin->GCR2 |= 0x00000001U; + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_006 */ +/* DesignId : LIN_DesignId_006 */ +/* Requirements : CONQ_LIN_SR10 */ +/** @fn void linSoftwareReset(linBASE_t *lin) + * @brief Perform software reset. + * @param[in] lin - lin module base address + * + * Perform software reset of lin module. + * This function will reset the lin state machine and clear all pending flags. + * It is required to call this function after a wakeup signal has been sent. + */ +void linSoftwareReset( linBASE_t * lin ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + lin->GCR1 &= ~( uint32 ) ( 0x00000080U ); + lin->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_007 */ +/* DesignId : LIN_DesignId_007 */ +/* Requirements : CONQ_LIN_SR11 */ +/** @fn uint32 linIsTxReady(linBASE_t *lin) + * @brief Check if Tx buffer empty + * @param[in] lin - lin module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 linIsTxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return lin->FLR & LIN_TX_READY; +} + +/* SourceId : LIN_SourceId_008 */ +/* DesignId : LIN_DesignId_008 */ +/* Requirements : CONQ_LIN_SR12 */ +/** @fn void linSetLength(linBASE_t *lin, uint32 length) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] length - number of data words in bytes. Range: 1-8. + * + * Send data response length in bytes. + */ +void linSetLength( linBASE_t * lin, uint32 length ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + lin->FORMAT = ( ( lin->FORMAT & 0xFFF8FFFFU ) | ( ( length - 1U ) << 16U ) ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_009 */ +/* DesignId : LIN_DesignId_009 */ +/* Requirements : CONQ_LIN_SR13 */ +/** @fn void linSend(linBASE_t *lin, uint8 * data) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data'. + * The number of data to transmit must be set with 'linSetLength' before. + */ +void linSend( linBASE_t * lin, uint8 * data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + uint8 * pData = data + length; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + lin->TDx[ length - i ] = *pData; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData--; + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_010 */ +/* DesignId : LIN_DesignId_010 */ +/* Requirements : CONQ_LIN_SR14 */ +/** @fn uint32 linIsRxReady(linBASE_t *lin) + * @brief Check if Rx buffer full + * @param[in] lin - lin module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 linIsRxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return lin->FLR & LIN_RX_INT; +} + +/* SourceId : LIN_SourceId_011 */ +/* DesignId : LIN_DesignId_011 */ +/* Requirements : CONQ_LIN_SR15 */ +/** @fn uint32 linTxRxError(linBASE_t *lin) + * @brief Return Tx and Rx Error flags + * @param[in] lin - lin module base address + * + * @return The Tx and Rx error flags + * + * Returns the bit, physical bus, checksum, inconsistent sync field, + * no response, framing, overrun, parity and timeout error flags. + * It also clears the error flags before returning. + */ +uint32 linTxRxError( linBASE_t * lin ) +{ + uint32 status = lin->FLR + & ( LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT + | LIN_TOAWUS_INT | LIN_TO_INT ); + + lin->FLR = LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT | LIN_TOAWUS_INT + | LIN_TO_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : LIN_SourceId_012 */ +/* DesignId : LIN_DesignId_012 */ +/* Requirements : CONQ_LIN_SR16 */ +/** @fn uint32 linGetIdentifier(linBASE_t *lin) + * @brief Get last received identifier + * @param[in] lin - lin module base address + * + * @return Identifier + * + * Read last received identifier. + */ +uint32 linGetIdentifier( linBASE_t * lin ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + return ( uint32 ) ( ( uint32 ) ( lin->ID & 0x00FF0000U ) >> 16U ); +} + +/* SourceId : LIN_SourceId_013 */ +/* DesignId : LIN_DesignId_013 */ +/* Requirements : CONQ_LIN_SR17 */ +/** @fn void linGetData(linBASE_t *lin, uint8 * const data) + * @brief Read received data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data buffer + * + * Read a block of bytes and place it into the data buffer pointed to by 'data'. + */ +void linGetData( linBASE_t * lin, uint8 * const data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + uint8 * pData = data; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *pData = lin->RDx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + pData++; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_014 */ +/* DesignId : LIN_DesignId_016 */ +/* Requirements : CONQ_LIN_SR20 */ +/** @fn void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + lin->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + lin->IODFTCTRL = ( ( uint32 ) ( 0x00000A00U ) + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_015 */ +/* DesignId : LIN_DesignId_017 */ +/* Requirements : CONQ_LIN_SR21 */ +/** @fn void linDisableLoopback(linBASE_t *lin) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * + * This function disable the Loopback mode. + */ +void linDisableLoopback( linBASE_t * lin ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + lin->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_016 */ +/* DesignId : LIN_DesignId_014 */ +/* Requirements : CONQ_LIN_SR18 */ +/** @fn linEnableNotification(linBASE_t *lin, uint32 flags) + * @brief Enable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +void linEnableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + lin->SETINT = flags; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_017 */ +/* DesignId : LIN_DesignId_015 */ +/* Requirements : CONQ_LIN_SR19 */ +/** @fn linDisableNotification(linBASE_t *lin, uint32 flags) + * @brief Disable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +void linDisableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + lin->CLEARINT = flags; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_018 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : CONQ_LIN_SR25 */ +/** @fn void lin1GetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN1_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN1_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN1_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN1_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN1_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN1_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN1_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN1_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN1_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN1_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN1_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN1_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN1_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN1_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN1_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = linREG1->GCR0; + config_reg->CONFIG_GCR1 = linREG1->GCR1; + config_reg->CONFIG_GCR2 = linREG1->GCR2; + config_reg->CONFIG_SETINT = linREG1->SETINT; + config_reg->CONFIG_SETINTLVL = linREG1->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG1->FORMAT; + config_reg->CONFIG_BRSR = linREG1->BRS; + config_reg->CONFIG_FUN = linREG1->PIO0; + config_reg->CONFIG_DIR = linREG1->PIO1; + config_reg->CONFIG_ODR = linREG1->PIO6; + config_reg->CONFIG_PD = linREG1->PIO7; + config_reg->CONFIG_PSL = linREG1->PIO8; + config_reg->CONFIG_COMP = linREG1->COMP; + config_reg->CONFIG_MASK = linREG1->MASK; + config_reg->CONFIG_MBRSR = linREG1->MBRSR; + } +} + +/* SourceId : LIN_SourceId_019 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : CONQ_LIN_SR26 */ +/** @fn void lin2GetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN2_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN2_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN2_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN2_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN2_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN2_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN2_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN2_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN2_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN2_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN2_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN2_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN2_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN2_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN2_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = linREG2->GCR0; + config_reg->CONFIG_GCR1 = linREG2->GCR1; + config_reg->CONFIG_GCR2 = linREG2->GCR2; + config_reg->CONFIG_SETINT = linREG2->SETINT; + config_reg->CONFIG_SETINTLVL = linREG2->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG2->FORMAT; + config_reg->CONFIG_BRSR = linREG2->BRS; + config_reg->CONFIG_FUN = linREG2->PIO0; + config_reg->CONFIG_DIR = linREG2->PIO1; + config_reg->CONFIG_ODR = linREG2->PIO6; + config_reg->CONFIG_PD = linREG2->PIO7; + config_reg->CONFIG_PSL = linREG2->PIO8; + config_reg->CONFIG_COMP = linREG2->COMP; + config_reg->CONFIG_MASK = linREG2->MASK; + config_reg->CONFIG_MBRSR = linREG2->MBRSR; + } +} + +/* SourceId : LIN_SourceId_024 */ +/* DesignId : */ +/* Requirements : */ +/** @fn uint32 linGetStatusFlag(linBASE_t *lin) + * @brief Get LIN status register value + * @param[in] lin - lin module base address + * + * @return Status Flag register content + * + * Read current Status Flag register. + */ +uint32 linGetStatusFlag( linBASE_t * lin ) +{ + return lin->FLR; +} + +/* SourceId : LIN_SourceId_025 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void linClearStatusFlag(linBASE_t *lin, uint32 flags) + * @brief Clear LIN status register + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be or'ed value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect, + * LIN_BUSY_FLAG - Bus Busy Flag, + * LIN_TXEMPTY_INT - Transmit Empty Flag + * + * Clear Status Flags passed as parameter. + */ +void linClearStatusFlag( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + lin->FLR = flags; + /* USER CODE BEGIN (45) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c new file mode 100644 index 00000000000..958a14a5cad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c @@ -0,0 +1,251 @@ +/** + * \file mdio.c + * + * \brief MDIO APIs. + * + * This file contains the device abstraction layer APIs for MDIO. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "hw_reg_access.h" +#include "mdio.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define PHY_REG_MASK ( 0x1FU ) +#define PHY_ADDR_MASK ( 0x1FU ) +#define PHY_DATA_MASK ( 0xFFFFU ) +#define PHY_REG_SHIFT ( 21U ) +#define PHY_ADDR_SHIFT ( 16U ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ + +/** + * \brief Reads a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param dataPtr Pointer where the read value shall be written. + * + * \return status of the read \n + * TRUE - read is successful.\n + * FALSE - read is not acknowledged properly. + * + **/ +/* SourceId : ETH_SourceId_059 */ +/* DesignId : ETH_DesignId_059*/ +/* Requirements : CONQ_EMAC_SR62 */ +boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ) +{ + boolean retVal = FALSE; + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( ( ( uint32 ) MDIO_USERACCESS0_READ ) + | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) ); + + /* wait for command completion */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + /* Store the data if the read is acknowledged */ + if( ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) & MDIO_USERACCESS0_ACK ) + == MDIO_USERACCESS0_ACK ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Output is a 16 bit Value to be stored - + * Advisory as per MISRA" */ + *dataPtr = ( uint16 ) ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) + & PHY_DATA_MASK ); + retVal = TRUE; + } + + return retVal; +} + +/** + * \brief Writes a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param RegVal Value to be written. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_058 */ +/* DesignId : ETH_DesignId_058*/ +/* Requirements : CONQ_EMAC_SR63 */ +void MDIOPhyRegWrite( uint32 baseAddr, uint32 phyAddr, uint32 regNum, uint16 RegVal ) +{ + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( MDIO_USERACCESS0_WRITE | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) + | RegVal ); + + /* wait for command completion*/ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ +} +/** + * \brief Reads the alive status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * is alive. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO alive register state + * + **/ +/* SourceId : ETH_SourceId_062 */ +/* DesignId : ETH_DesignId_062*/ +/* Requirements : CONQ_EMAC_SR64 */ +uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_ALIVE ) ); +} + +/** + * \brief Reads the link status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * link is active. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO link register state + * + **/ +/* SourceId : ETH_SourceId_061 */ +/* DesignId : ETH_DesignId_061*/ +/* Requirements : CONQ_EMAC_SR67 */ +uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_LINK ) ); +} + +/** + * \brief Initializes the MDIO peripheral. This enables the MDIO state + * machine, uses standard pre-amble and set the clock divider value. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param mdioInputFreq The clock input to the MDIO module + * \param mdioOutputFreq The clock output required on the MDIO bus + * \return None + * + **/ +/* SourceId : ETH_SourceId_060 */ +/* DesignId : ETH_DesignId_060*/ +/* Requirements : CONQ_EMAC_SR59 */ +void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ) +{ + uint32 clkDiv = ( mdioInputFreq / mdioOutputFreq ) - 1U; + HWREG( baseAddr + MDIO_CONTROL ) = ( ( clkDiv & MDIO_CONTROL_CLKDIV ) + | MDIO_CONTROL_ENABLE | MDIO_CONTROL_PREAMBLE + | MDIO_CONTROL_FAULTENB ); +} + +/** + * \brief Function to enable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : CONQ_EMAC_SR60 */ +void MDIOEnable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + | MDIO_CONTROL_ENABLE; +} + +/** + * \brief Function to disable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_057 */ +/* DesignId : ETH_DesignId_057*/ +/* Requirements : CONQ_EMAC_SR61 */ +void MDIODisable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + & ( ~MDIO_CONTROL_ENABLE ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c new file mode 100644 index 00000000000..cca2730f813 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c @@ -0,0 +1,3408 @@ +/** @file mibspi.c + * @brief MIBSPI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "mibspi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : MIBSPI_SourceId_001 */ +/* DesignId : MIBSPI_DesignId_001 */ +/* Requirements : CONQ_MIBSPI_SR9 */ +/** @fn void mibspiInit(void) + * @brief Initializes the MIBSPI Driver + * + * This function initializes the MIBSPI module. + */ +void mibspiInit( void ) +{ + uint32 i; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b MIBSPI1 */ + + /** bring MIBSPI out of reset */ + mibspiREG1->GCR0 = 0U; + mibspiREG1->GCR0 = 1U; + + /** enable MIBSPI1 multibuffered mode and enable buffer RAM */ + mibspiREG1->MIBSPIE = ( mibspiREG1->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI1 master mode and clock configuration */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI1 enable pin configuration */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG1->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG1->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG1->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG1->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG1->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG1->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG1->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG1->PAR_ECC_CTRL = ( mibspiREG1->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG1->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG1->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG1->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG1->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG1->LTGPEND = ( mibspiREG1->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG1->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG1->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI1 @b Port */ + + /** - MIBSPI1 Port output values */ + mibspiREG1->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port direction */ + mibspiREG1->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port open drain enable */ + mibspiREG1->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown selection */ + mibspiREG1->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown enable*/ + mibspiREG1->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /* MIBSPI1 set all pins to functional */ + mibspiREG1->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - Finally start MIBSPI1 */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI2 */ + + /** bring MIBSPI out of reset */ + mibspiREG2->GCR0 = 0U; + mibspiREG2->GCR0 = 1U; + + /** enable MIBSPI2 multibuffered mode and enable buffer RAM */ + mibspiREG2->MIBSPIE = ( mibspiREG2->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI2 master mode and clock configuration */ + mibspiREG2->GCR1 = ( mibspiREG2->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI2 enable pin configuration */ + mibspiREG2->INT0 = ( mibspiREG2->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG2->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG2->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG2->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG2->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG2->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG2->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG2->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG2->PAR_ECC_CTRL = ( mibspiREG2->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG2->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG2->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG2->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG2->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG2->LTGPEND = ( mibspiREG2->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG2->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG2->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG2->INT0 = ( mibspiREG2->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI2 @b Port */ + + /** - MIBSPI2 Port output values */ + mibspiREG2->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port direction */ + mibspiREG2->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port open drain enable */ + mibspiREG2->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port pullup / pulldown selection */ + mibspiREG2->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port pullup / pulldown enable*/ + mibspiREG2->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI2 set all pins to functional */ + mibspiREG2->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI2 */ + mibspiREG2->GCR1 = ( mibspiREG2->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI3 */ + + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = ( mibspiREG3->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG3->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG3->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->PAR_ECC_CTRL = ( mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG3->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG3->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG3->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG3->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI4 */ + + /** bring MIBSPI out of reset */ + mibspiREG4->GCR0 = 0U; + mibspiREG4->GCR0 = 1U; + + /** enable MIBSPI4 multibuffered mode and enable buffer RAM */ + mibspiREG4->MIBSPIE = ( mibspiREG4->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI4 master mode and clock configuration */ + mibspiREG4->GCR1 = ( mibspiREG4->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI4 enable pin configuration */ + mibspiREG4->INT0 = ( mibspiREG4->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG4->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG4->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG4->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG4->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG4->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG4->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG4->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG4->PAR_ECC_CTRL = ( mibspiREG4->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG4->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG4->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG4->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG4->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG4->LTGPEND = ( mibspiREG4->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG4->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG4->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG4->INT0 = ( mibspiREG4->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI4 @b Port */ + + /** - MIBSPI4 Port output values */ + mibspiREG4->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port direction */ + mibspiREG4->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port open drain enable */ + mibspiREG4->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port pullup / pulldown selection */ + mibspiREG4->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port pullup / pulldown enable*/ + mibspiREG4->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI4 set all pins to functional */ + mibspiREG4->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI4 */ + mibspiREG4->GCR1 = ( mibspiREG4->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI5 */ + + /** bring MIBSPI out of reset */ + mibspiREG5->GCR0 = 0U; + mibspiREG5->GCR0 = 1U; + + /** enable MIBSPI5 multibuffered mode and enable buffer RAM */ + mibspiREG5->MIBSPIE = ( mibspiREG5->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI5 master mode and clock configuration */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI5 enable pin configuration */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG5->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG5->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG5->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG5->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG5->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG5->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG5->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG5->PAR_ECC_CTRL = ( mibspiREG5->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG5->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG5->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG5->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG5->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG5->LTGPEND = ( mibspiREG5->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG5->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG5->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI5 @b Port */ + + /** - MIBSPI5 Port output values */ + mibspiREG5->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port direction */ + mibspiREG5->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port open drain enable */ + mibspiREG5->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown selection */ + mibspiREG5->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown enable*/ + mibspiREG5->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /* MIBSPI5 set all pins to functional */ + mibspiREG5->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - Finally start MIBSPI5 */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_002 */ +/* DesignId : */ +/* Requirements : */ +/** @fn boolean mibspiIsBuffInitialized(mibspiBASE_t *mibspi) + * @brief Checks if Mibspi buffer is initialized. + * @param[in] mibspi - Mibspi module base address + * + * This function brings Mibspi module out of reset. + */ +boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi ) +{ + volatile boolean status; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + if( ( mibspi->FLG & 0x01000000U ) != 0x01000000U ) + { + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + return ( status ); +} + +/* SourceId : MIBSPI_SourceId_003 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void mibspiOutofReset(mibspiBASE_t *mibspi) + * @brief Bring Mibspi Module Out of Reset + * @param[in] mibspi - Mibspi module base address + * + * This function brings Mibspi module out of reset. + */ +void mibspiOutofReset( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + mibspi->GCR0 |= 0x1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_004 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void mibspiReset(mibspiBASE_t *mibspi) + * @brief Take Mibspi Module to Reset + * @param[in] mibspi - Mibspi module base address + * + * This function takes Mibspi module to reset. + */ +void mibspiReset( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + mibspi->GCR0 = 0x0U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_005 */ +/* DesignId : MIBSPI_DesignId_002 */ +/* Requirements : CONQ_MIBSPI_SR10 */ +/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] mibspi - mibspi module base address + * @param[in] port - Value to write to PC0 register + * + * Change the value of the PC0 register at runtime, this allows to + * dynamically change the functionality of the MIBSPI pins between functional + * and GIO mode. + */ +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + mibspi->PC0 = port; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_006 */ +/* DesignId : MIBSPI_DesignId_003 */ +/* Requirements : CONQ_MIBSPI_SR11 */ +/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Set Buffer Data + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] data - new data for transfer group + * + * This function updates the data for the specified transfer group, + * the length of the data must match the length of the transfer group. + */ +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + mibspiRAM_t * ram = mibspi == mibspiREG1 + ? mibspiRAM1 + : ( mibspi == mibspiREG2 + ? mibspiRAM2 + : ( mibspi == mibspiREG3 + ? mibspiRAM3 + : ( mibspi == mibspiREG4 ? mibspiRAM4 + : mibspiRAM5 ) ) ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + ram->tx[ start ].data = *data; + data++; + start++; + } + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_007 */ +/* DesignId : MIBSPI_DesignId_004 */ +/* Requirements : CONQ_MIBSPI_SR12 */ +/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Retrieves Buffer Data from receive buffer + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[out] data - pointer to data array + * + * @return error flags from data buffer, if there was a receive error on + * one of the buffers this will be reflected in the return value. + * + * This function transfers the data from the specified transfer group receive + * buffers to the data array, the length of the data must match the length + * of the transfer group. + */ +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + mibspiRAM_t * ram = mibspi == mibspiREG1 + ? mibspiRAM1 + : ( mibspi == mibspiREG2 + ? mibspiRAM2 + : ( mibspi == mibspiREG3 + ? mibspiRAM3 + : ( mibspi == mibspiREG4 ? mibspiRAM4 + : mibspiRAM5 ) ) ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + uint16 mibspiFlags = 0U; + uint32 ret; + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + mibspiFlags |= ram->rx[ start ].flags; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *data = ram->rx[ start ].data; + data++; + start++; + } + + ret = ( ( uint32 ) mibspiFlags >> 8U ) & 0x5FU; + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + return ret; +} + +/* SourceId : MIBSPI_SourceId_008 */ +/* DesignId : MIBSPI_DesignId_005 */ +/* Requirements : CONQ_MIBSPI_SR13 */ +/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) + * @brief Transmit Transfer Group + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * Initiates a transfer for the specified transfer group. + */ +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mibspi->TGCTRL[ group ] |= 0x80000000U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_009 */ +/* DesignId : MIBSPI_DesignId_006 */ +/* Requirements : CONQ_MIBSPI_SR14 */ +/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) + * @brief Check for Transfer Group Ready + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * @return TRUE is transfer complete, otherwise FALSE. + * + * Checks to see if the transfer for the specified transfer group + * has finished. + */ +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ) +{ + boolean status; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( ( ( ( ( mibspi->TGINTFLG & 0xFFFF0000U ) >> 16U ) >> group ) & 1U ) == 1U ) + { + mibspi->TGINTFLG = ( mibspi->TGINTFLG & 0x0000FFFFU ) + | ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return ( status ); +} + +/* SourceId : MIBSPI_SourceId_010 */ +/* DesignId : MIBSPI_DesignId_009 */ +/* Requirements : CONQ_MIBSPI_SR17 */ +/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + mibspi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + mibspi->IOLPKTSTCR = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_011 */ +/* DesignId : MIBSPI_DesignId_010 */ +/* Requirements : CONQ_MIBSPI_SR18 */ +/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * + * This function disable the Loopback mode. + */ +void mibspiDisableLoopback( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + mibspi->IOLPKTSTCR = 0x00000500U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_012 */ +/* DesignId : MIBSPI_DesignId_011 */ +/* Requirements : CONQ_MIBSPI_SR21 */ +/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) + * @brief Set the Pmode for the selected Data Format register + * @param[in] mibspi - Mibspi module base address + * @param[in] Pmode - Mibspi Parellel mode + * PMODE_NORMAL + * PMODE_2_DATALINE + * PMODE_4_DATALINE + * PMODE_8_DATALINE + * @param[in] DFMT - Mibspi Data Format register + * DATA_FORMAT0 + * DATA_FORMAT1 + * DATA_FORMAT2 + * DATA_FORMAT3 + * + * This function sets the Pmode for the selected Data Format register. + */ +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ) +{ + uint32 pmctrl_reg; + /* Set the Pmode for the selected Data Format register */ + pmctrl_reg = ( mibspi->PMCTRL + & ( ~( uint32 ) ( ( uint32 ) 0xFFU << ( 8U * DFMT ) ) ) ); + mibspi->PMCTRL = ( pmctrl_reg + | ( uint32 ) ( ( uint32 ) Pmode << ( ( 8U * DFMT ) ) ) ); +} + +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_007 */ +/* Requirements : CONQ_MIBSPI_SR15 */ +/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 + * level) + * @brief Enable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] level - Interrupt level + * + * This function enables the transfer group finished interrupt. + */ +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + if( level != 0U ) + { + mibspi->TGITLVST = ( mibspi->TGITLVST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + else + { + mibspi->TGITLVCR = ( mibspi->TGITLVCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + mibspi->TGITENST = ( mibspi->TGITENST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_014 */ +/* DesignId : MIBSPI_DesignId_008 */ +/* Requirements : CONQ_MIBSPI_SR16 */ +/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Disable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * This function disables the transfer group finished interrupt. + */ +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + mibspi->TGITENCR = ( mibspi->TGITENCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_015 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR22 */ +/** @fn void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI1_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI1_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI1_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI1_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI1_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI1_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI1_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI1_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI1_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI1_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI1_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI1_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI1_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI1_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI1_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI1_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI1_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI1_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI1_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI1_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI1_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI1_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI1_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG1->GCR1; + config_reg->CONFIG_INT0 = mibspiREG1->INT0; + config_reg->CONFIG_LVL = mibspiREG1->LVL; + config_reg->CONFIG_PCFUN = mibspiREG1->PC0; + config_reg->CONFIG_PCDIR = mibspiREG1->PC1; + config_reg->CONFIG_PCPDR = mibspiREG1->PC6; + config_reg->CONFIG_PCDIS = mibspiREG1->PC7; + config_reg->CONFIG_PCPSL = mibspiREG1->PC8; + config_reg->CONFIG_DELAY = mibspiREG1->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG1->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG1->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG1->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG1->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG1->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG1->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG1->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG1->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG1->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG1->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG1->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG1->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG1->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG1->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG1->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_016 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR23 */ +/** @fn void mibspi2GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI2_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI2_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI2_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI2_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI2_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI2_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI2_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI2_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI2_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI2_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI2_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI2_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI2_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI2_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI2_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI2_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI2_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI2_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI2_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI2_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI2_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI2_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI2_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG2->GCR1; + config_reg->CONFIG_INT0 = mibspiREG2->INT0; + config_reg->CONFIG_LVL = mibspiREG2->LVL; + config_reg->CONFIG_PCFUN = mibspiREG2->PC0; + config_reg->CONFIG_PCDIR = mibspiREG2->PC1; + config_reg->CONFIG_PCPDR = mibspiREG2->PC6; + config_reg->CONFIG_PCDIS = mibspiREG2->PC7; + config_reg->CONFIG_PCPSL = mibspiREG2->PC8; + config_reg->CONFIG_DELAY = mibspiREG2->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG2->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG2->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG2->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG2->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG2->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG2->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG2->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG2->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG2->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG2->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG2->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG2->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG2->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG2->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG2->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_017 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR24 */ +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG3->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG3->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG3->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG3->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG3->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG3->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG3->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG3->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG3->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_018 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR25 */ +/** @fn void mibspi4GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI4_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI4_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI4_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI4_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI4_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI4_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI4_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI4_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI4_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI4_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI4_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI4_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI4_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI4_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI4_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI4_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI4_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI4_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI4_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI4_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI4_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI4_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG4->GCR1; + config_reg->CONFIG_INT0 = mibspiREG4->INT0; + config_reg->CONFIG_LVL = mibspiREG4->LVL; + config_reg->CONFIG_PCFUN = mibspiREG4->PC0; + config_reg->CONFIG_PCDIR = mibspiREG4->PC1; + config_reg->CONFIG_PCPDR = mibspiREG4->PC6; + config_reg->CONFIG_PCDIS = mibspiREG4->PC7; + config_reg->CONFIG_PCPSL = mibspiREG4->PC8; + config_reg->CONFIG_DELAY = mibspiREG4->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG4->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG4->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG4->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG4->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG4->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG4->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG4->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG4->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG4->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG4->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG4->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG4->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG4->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG4->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG4->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_019 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR26 */ +/** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI5_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI5_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI5_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI5_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI5_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI5_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI5_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI5_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI5_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI5_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI5_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI5_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI5_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI5_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI5_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI5_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI5_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI5_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI5_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI5_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI5_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI5_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI5_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG5->GCR1; + config_reg->CONFIG_INT0 = mibspiREG5->INT0; + config_reg->CONFIG_LVL = mibspiREG5->LVL; + config_reg->CONFIG_PCFUN = mibspiREG5->PC0; + config_reg->CONFIG_PCDIR = mibspiREG5->PC1; + config_reg->CONFIG_PCPDR = mibspiREG5->PC6; + config_reg->CONFIG_PCDIS = mibspiREG5->PC7; + config_reg->CONFIG_PCPSL = mibspiREG5->PC8; + config_reg->CONFIG_DELAY = mibspiREG5->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG5->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG5->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG5->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG5->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG5->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG5->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG5->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG5->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG5->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG5->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG5->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG5->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG5->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG5->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG5->PAR_ECC_CTRL; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c new file mode 100644 index 00000000000..786f8d6871a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c @@ -0,0 +1,403 @@ +/** @file nmpu.c + * @brief NMPU Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "nmpu.h" + +/** @fn void nmpuEnable(nmpuBASE_t * nmpu) + * @brief Enable memory protection + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function enables memory protection + */ +/* SourceId : NMPU_SourceId_001 */ +/* DesignId : NMPU_DesignId_001 */ +/* Requirements : CONQ_NMPU_SR1 */ +void nmpuEnable( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL1 = 0xAU; /* Enable Memory Protection */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void nmpuDisable(nmpuBASE_t * nmpu) + * @brief Disable memory protection + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function disables memory protection + */ +/* SourceId : NMPU_SourceId_002 */ +/* DesignId : NMPU_DesignId_002 */ +/* Requirements : CONQ_NMPU_SR2 */ +void nmpuDisable( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL1 = 0x5U; /* Disable Memory Protection */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void nmpuEnableErrorGen(nmpuBASE_t * nmpu) + * @brief Enable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function enables error pulse output to ESM + */ +/* SourceId : NMPU_SourceId_003 */ +/* DesignId : NMPU_DesignId_003 */ +/* Requirements : CONQ_NMPU_SR3 */ +void nmpuEnableErrorGen( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL2 = 0xAU; /* Enable Error pulse output to ESM */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void nmpuDisableErrorGen(nmpuBASE_t * nmpu) + * @brief Disable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function disables error pulse output to ESM + */ +/* SourceId : NMPU_SourceId_004 */ +/* DesignId : NMPU_DesignId_004 */ +/* Requirements : CONQ_NMPU_SR4 */ +void nmpuDisableErrorGen( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL2 = 0x5U; /* Disable Error pulse output to ESM */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn boolean nmpuEnableRegion(nmpuBASE_t * nmpu, uint32 region, nmpuRegionAttributes_t +config) +* @brief Enable NMPU region +* +* @param[in] nmpu NMPU module instance +* - nmpu_emacREG : EMAC-NMPU (2 regions) +* - nmpu_dmaREG : DMA-NMPU (8 regions) +* - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 +regions) +* @param[in] region region number (NMPU_REGION0..NMPU_REGION7) +* @param[in] config struct containing the following elements: + - baseaddr : 32-bit vase address (must be multiple of +region size) + - regionsize : Region size (Refer enum nmpuRegionSize) + - accesspermission : Access Permission (Refer enum +nmpuAccessPermission) +* @return Returns TRUE if the input parameters are valid. +* +* This function enables an NMPU region. This function will not enable the NMPU module. +Application must call the routine nmpuEnable to so the same. +*/ +/* SourceId : NMPU_SourceId_005 */ +/* DesignId : NMPU_DesignId_005 */ +/* Requirements : CONQ_NMPU_SR5 */ +boolean nmpuEnableRegion( nmpuBASE_t * nmpu, + nmpuReg_t region, + nmpuRegionAttributes_t config ) +{ + boolean status = TRUE; + uint32 addrMask; + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + if( ( uint32 ) region >= ( nmpu->MPUTYPE >> 8U ) ) + { + /* Invalid region */ + status = FALSE; + } + + addrMask = ( uint32 ) 2U << ( config.regionsize ); + addrMask = addrMask - 1U; + if( ( config.baseaddr & addrMask ) != 0U ) + { + /* Invalid Baseaddress - Not a multiple of region size */ + status = FALSE; + } + + if( status == TRUE ) + { + /* Set the region attributes */ + nmpu->MPULOCK = 0xAU; + nmpu->MPUREGNUM = region; + nmpu->MPUREGBASE = ( ( uint32 ) ( config.baseaddr ) ); + nmpu->MPUREGSENA = ( ( uint32 ) ( config.regionsize ) << 1U ) | 1U; + nmpu->MPUREGACR = ( ( uint32 ) ( config.accesspermission ) << 8U ); + nmpu->MPULOCK = 0x5U; + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuDisableRegion(nmpuBASE_t * nmpu, uint32 region) + * @brief Disable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @param[in] region region number (NMPU_REGION0..NMPU_REGION7) + * @return Returns TRUE if the input parameters are valid. + * + * This function disables an NMPU region. + */ +/* SourceId : NMPU_SourceId_006 */ +/* DesignId : NMPU_DesignId_006 */ +/* Requirements : CONQ_NMPU_SR6 */ +boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region ) +{ + boolean status; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( uint32 ) region >= ( nmpu->MPUTYPE >> 8U ) ) + { + /* Invalid region */ + status = FALSE; + } + else + { + nmpu->MPULOCK = 0xAU; + nmpu->MPUREGNUM = region; + nmpu->MPUREGSENA = 0U; + nmpu->MPULOCK = 0x5U; + status = TRUE; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuErr_t nmpuGetErrorStatus(nmpuBASE_t * nmpu) + * @brief Get the error status + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Returns any of the following: + * - NMPU_ERROR_NONE : No error + * - NMPU_ERROR_AP_READ : Access permission Read Error + * - NMPU_ERROR_AP_WRITE : Access permission Write Error + * - NMPU_ERROR_BG_READ : Backgroung Read Error + * - NMPU_ERROR_BG_WRITE : Backgroung Write Error + * + * This function returns the status of NMPU error + */ +/* SourceId : NMPU_SourceId_007 */ +/* DesignId : NMPU_DesignId_007 */ +/* Requirements : CONQ_NMPU_SR7 */ +nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu ) +{ + nmpuErr_t status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( ( nmpu->MPUERRSTAT & 0x1U ) == 0x1U ) + { + if( ( nmpu->MPUERRSTAT & 0x02000000U ) == 0x02000000U ) + { + if( ( nmpu->MPUERRSTAT & 0x10000000U ) == 0x10000000U ) + { + status = NMPU_ERROR_AP_READ; + } + else + { + status = NMPU_ERROR_AP_WRITE; + } + } + else + { + if( ( nmpu->MPUERRSTAT & 0x10000000U ) == 0x10000000U ) + { + status = NMPU_ERROR_BG_READ; + } + else + { + status = NMPU_ERROR_BG_WRITE; + } + } + } + else + { + status = NMPU_ERROR_NONE; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuReg_t nmpuGetErrorRegion(nmpuBASE_t * nmpu) + * @brief Get the region for which an access permission error was detected + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Region where access permission error was detected + * + * This function returns the region for which an access permission error was detected + */ +/* SourceId : NMPU_SourceId_008 */ +/* DesignId : NMPU_DesignId_008 */ +/* Requirements : CONQ_NMPU_SR9 */ +nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return ( nmpuReg_t ) ( ( nmpu->MPUERRSTAT & 0x70000U ) >> 16U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn uint32 nmpuGetErrorAddress(nmpuBASE_t * nmpu) + * @brief Get the address for MPU compare fail + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Address for MPU compare fail + * + * This function returns the address for MPU compare fail + */ +/* SourceId : NMPU_SourceId_009 */ +/* DesignId : NMPU_DesignId_009 */ +/* Requirements : CONQ_NMPU_SR8 */ +uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + return ( nmpu->MPUERRADDR ); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void nmpuClearErrorStatus(nmpuBASE_t * nmpu) + * @brief Clear error status + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function clears the error status flags + */ +/* SourceId : NMPU_SourceId_010 */ +/* DesignId : NMPU_DesignId_010 */ +/* Requirements : CONQ_NMPU_SR10 */ +void nmpuClearErrorStatus( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + nmpu->MPUERRSTAT = 1U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c new file mode 100644 index 00000000000..ea9e93c4b16 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c @@ -0,0 +1,330 @@ +/** @file notification.c + * @brief User Notification Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file defines empty notification routines to avoid + * linker errors, Driver expects user to define the notification. + * The user needs to either remove this file and use their custom + * notification function or place their code sequence in this file + * between the provided USER CODE BEGIN and USER CODE END. + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include +#include "esm.h" +#include "can.h" +#include "gio.h" +#include "lin.h" +#include "mibspi.h" +#include "sci.h" +#include "het.h" +#include "dcc.h" +#include "i2c.h" +#include "crc.h" +#include "etpwm.h" +#include "eqep.h" +#include "ecap.h" +#include "epc.h" +#include "emac.h" +#include "sys_dma.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ +void esmGroup1Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +void esmGroup2Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +void esmGroup3Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + for( ;; ) + { + } /* Wait */ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +void adcNotification( adcBASE_t * adc, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +void canErrorNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +void canStatusChangeNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +void canMessageNotification( canBASE_t * node, uint32 messageBox ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +void dccNotification( dccBASE_t * dcc, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +void gioNotification( gioPORT_t * port, uint32 bit ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ +void linNotification( linBASE_t * lin, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +void sciNotification( sciBASE_t * sci, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ +void edgeNotification( hetBASE_t * hetREG, uint32 edge ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (40) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ +void hetNotification( hetBASE_t * het, uint32 offset ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +void crcNotification( crcBASE_t * crc, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (45) */ +/* USER CODE END */ + +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + +void etpwmNotification( etpwmBASE_t * node ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (47) */ + /* USER CODE END */ +} +void etpwmTripNotification( etpwmBASE_t * node, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (48) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + +void eqepNotification( eqepBASE_t * eqep, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (52) */ +/* USER CODE END */ + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + +void ecapNotification( ecapBASE_t * ecap, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (54) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + +void epcCAMFullNotification( void ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (57) */ + /* USER CODE END */ +} +void epcFIFOFullNotification( uint32 epcFIFOStatus ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (58) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + +void emacTxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (60) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ +void emacRxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (62) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (63) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c new file mode 100644 index 00000000000..e5a51eee03b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c @@ -0,0 +1,433 @@ +/** + * \file phy_dp83640.c + * + * \brief APIs for configuring DP83640. + * + * This file contains the device abstraction APIs for PHY DP83640. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : CONQ_EMAC_SR69 */ +uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : CONQ_EMAC_SR67 */ +boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * DP83640_100BTX - 100BaseTX + * DP83640_100BTX_FD - Full duplex capabilty for 100BaseTX + * DP83640_10BT - 10BaseT + * DP83640_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : CONQ_EMAC_SR66 */ +boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : CONQ_EMAC_SR68 */ +boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : CONQ_EMAC_SR65 */ +void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint16 regVal = 0U; + uint16 * regPtr = ®Val; + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET ); + + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, regPtr ); + /* : This bit is self-clearing and returns 1 until the reset process is complete. */ + while( ( regVal & PHY_SOFTRESET ) != 0U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, regPtr ); + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : CONQ_EMAC_SR72 */ +void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + uint16 * regPtr = ®Val; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regPtr ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : CONQ_EMAC_SR73 */ +void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + uint16 * regPtr = ®Val; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regPtr ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : CONQ_EMAC_SR75 */ +uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c new file mode 100644 index 00000000000..d6954591150 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c @@ -0,0 +1,401 @@ +/** + * \file phy_Tlk111.c + * + * \brief APIs for configuring Tlk111. + * + * This file contains the device abstraction APIs for PHY Tlk111. + */ + +/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com + * ALL RIGHTS RESERVED + */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_tlk111.h" + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : ETH_SR49 */ +uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR1, Tlk111_SWSCR1_Val ); + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR2, Tlk111_SWSCR2_Val ); + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR3, Tlk111_SWSCR3_Val ); + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_SWSCR1, + ( Tlk111_SWSCR1_Val | Tlk111_SWStrapDone ) ); +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : ETH_SR47 */ +boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * Tlk111_100BTX - 100BaseTX + * Tlk111_100BTX_FD - Full duplex capabilty for 100BaseTX + * Tlk111_10BT - 10BaseT + * Tlk111_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : ETH_SR46 */ +boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : ETH_SR48 */ +boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : ETH_SR44 */ +void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_LPBK_ENABLE ); + /* A wait of 3us is required before allowing further operation. */ + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : ETH_SR51 */ +void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : ETH_SR51 */ +void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : ETH_SR53 */ +uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} + +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c new file mode 100644 index 00000000000..a8bca743bfa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c @@ -0,0 +1,559 @@ +/** @file pinmux.c + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include "pinmux.h" + +#define PINMUX_GIOB_DISABLE_HET2_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 179 ] = ( pinMuxReg->PINMUX[ 179 ] \ + & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +#define PINMUX_GIOA_DISABLE_HET1_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 179 ] = ( pinMuxReg->PINMUX[ 179 ] \ + & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +#define PINMUX_ETHERNET_SELECT( interface ) \ + ( pinMuxReg->PINMUX[ 160 ] = ( pinMuxReg->PINMUX[ 160 ] & PINMUX_ETHERNET_MASK ) \ + | ( PINMUX_ETHERNET_##interface ) ) + +#define PINMUX_ETPWM1_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM1_MASK ) \ + | ( PINMUX_ETPWM1_##interface ) ) + +#define PINMUX_ETPWM2_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM2_MASK ) \ + | ( PINMUX_ETPWM2_##interface ) ) + +#define PINMUX_ETPWM3_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM3_MASK ) \ + | ( PINMUX_ETPWM3_##interface ) ) + +#define PINMUX_ETPWM4_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM4_MASK ) \ + | ( PINMUX_ETPWM4_##interface ) ) + +#define PINMUX_ETPWM5_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM5_MASK ) \ + | ( PINMUX_ETPWM5_##interface ) ) + +#define PINMUX_ETPWM6_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM6_MASK ) \ + | ( PINMUX_ETPWM6_##interface ) ) + +#define PINMUX_ETPWM7_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM7_MASK ) \ + | ( PINMUX_ETPWM7_##interface ) ) + +#define PINMUX_ETPWM_TZ1_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] & PINMUX_TZ1_MASK ) \ + | ( PINMUX_TZ1_##interface ) ) + +#define PINMUX_ETPWM_TZ2_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] & PINMUX_TZ2_MASK ) \ + | ( PINMUX_TZ2_##interface ) ) + +#define PINMUX_ETPWM_TZ3_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TZ3_MASK ) \ + | ( PINMUX_TZ3_##interface ) ) + +#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_EPWM1SYNCI_MASK ) \ + | ( PINMUX_EPWM1SYNCI_##interface ) ) + +#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 165 ] \ + & PINMUX_ETPWM_TIME_BASE_SYNC_MASK ) \ + | ( PINMUX_ETPWM_TIME_BASE_SYNC_##state ) ) + +#define PINMUX_ETPWM_SOC1A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC1A_MASK ) \ + | ( PINMUX_ETPWM_SOC1A_##state ) ) + +#define PINMUX_ETPWM_SOC2A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC2A_MASK ) \ + | ( PINMUX_ETPWM_SOC2A_##state ) ) + +#define PINMUX_ETPWM_SOC3A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC3A_MASK ) \ + | ( PINMUX_ETPWM_SOC3A_##state ) ) + +#define PINMUX_ETPWM_SOC4A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC4A_MASK ) \ + | ( PINMUX_ETPWM_SOC4A_##state ) ) + +#define PINMUX_ETPWM_SOC5A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC5A_MASK ) \ + | ( PINMUX_ETPWM_SOC5A_##state ) ) + +#define PINMUX_ETPWM_SOC6A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC6A_MASK ) \ + | ( PINMUX_ETPWM_SOC6A_##state ) ) + +#define PINMUX_ETPWM_SOC7A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC7A_MASK ) \ + | ( PINMUX_ETPWM_SOC7A_##state ) ) + +#define PINMUX_GATE_EMIF_CLK_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 9 ] = ( pinMuxReg->PINMUX[ 9 ] & PINMUX_GATE_EMIF_CLK_MASK ) \ + | ( PINMUX_GATE_EMIF_CLK_##state ) ) + +#define PINMUX_ALT_ADC_TRIGGER_SELECT( num ) \ + ( pinMuxReg->PINMUX[ 161 ] = ( pinMuxReg->PINMUX[ 161 ] \ + & PINMUX_ALT_ADC_TRIGGER_MASK ) \ + | ( PINMUX_ALT_ADC_TRIGGER_##num ) ) + +#define PINMUX_EMIF_OUTPUT_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 174 ] = ( pinMuxReg->PINMUX[ 174 ] \ + & PINMUX_EMIF_OUTPUT_ENABLE_MASK ) \ + | ( PINMUX_EMIF_OUTPUT_ENABLE_##state ) ) + +#define PINMUX_EQEP1A_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] \ + & PINMUX_EQEP1A_FILTER_MASK ) \ + | ( PINMUX_EQEP1A_FILTER_##state ) ) + +#define PINMUX_EQEP1B_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] \ + & PINMUX_EQEP1B_FILTER_MASK ) \ + | ( PINMUX_EQEP1B_FILTER_##state ) ) + +#define PINMUX_EQEP1I_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP1I_FILTER_MASK ) \ + | ( PINMUX_EQEP1I_FILTER_##state ) ) + +#define PINMUX_EQEP1S_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP1S_FILTER_MASK ) \ + | ( PINMUX_EQEP1S_FILTER_##state ) ) + +#define PINMUX_EQEP2A_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP2A_FILTER_MASK ) \ + | ( PINMUX_EQEP2A_FILTER_##state ) ) + +#define PINMUX_EQEP2B_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP2B_FILTER_MASK ) \ + | ( PINMUX_EQEP2B_FILTER_##state ) ) + +#define PINMUX_EQEP2I_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] \ + & PINMUX_EQEP2I_FILTER_MASK ) \ + | ( PINMUX_EQEP2I_FILTER_##state ) ) + +#define PINMUX_EQEP2S_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] \ + & PINMUX_EQEP2S_FILTER_MASK ) \ + | ( PINMUX_EQEP2S_FILTER_##state ) ) + +#define PINMUX_ECAP1_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP1_FILTER_MASK ) \ + | ( PINMUX_ECAP1_FILTER_##state ) ) + +#define PINMUX_ECAP2_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP2_FILTER_MASK ) \ + | ( PINMUX_ECAP2_FILTER_##state ) ) + +#define PINMUX_ECAP3_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP3_FILTER_MASK ) \ + | ( PINMUX_ECAP3_FILTER_##state ) ) + +#define PINMUX_ECAP4_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP4_FILTER_MASK ) \ + | ( PINMUX_ECAP4_FILTER_##state ) ) + +#define PINMUX_ECAP5_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] & PINMUX_ECAP5_FILTER_MASK ) \ + | ( PINMUX_ECAP5_FILTER_##state ) ) + +#define PINMUX_ECAP6_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] & PINMUX_ECAP6_FILTER_MASK ) \ + | ( PINMUX_ECAP6_FILTER_##state ) ) + +#define PINMUX_GIOA0_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA0_DMA_MASK ) \ + | ( PINMUX_GIOA0_DMA_##state ) ) + +#define PINMUX_GIOA1_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA1_DMA_MASK ) \ + | ( PINMUX_GIOA1_DMA_##state ) ) + +#define PINMUX_GIOA2_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA2_DMA_MASK ) \ + | ( PINMUX_GIOA2_DMA_##state ) ) + +#define PINMUX_GIOA3_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA3_DMA_MASK ) \ + | ( PINMUX_GIOA3_DMA_##state ) ) + +#define PINMUX_GIOA4_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA4_DMA_MASK ) \ + | ( PINMUX_GIOA4_DMA_##state ) ) + +#define PINMUX_GIOA5_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA5_DMA_MASK ) \ + | ( PINMUX_GIOA5_DMA_##state ) ) + +#define PINMUX_GIOA6_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA6_DMA_MASK ) \ + | ( PINMUX_GIOA6_DMA_##state ) ) + +#define PINMUX_GIOA7_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA7_DMA_MASK ) \ + | ( PINMUX_GIOA7_DMA_##state ) ) + +#define PINMUX_GIOB0_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB0_DMA_MASK ) \ + | ( PINMUX_GIOB0_DMA_##state ) ) + +#define PINMUX_GIOB1_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB1_DMA_MASK ) \ + | ( PINMUX_GIOB1_DMA_##state ) ) + +#define PINMUX_GIOB2_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB2_DMA_MASK ) \ + | ( PINMUX_GIOB2_DMA_##state ) ) + +#define PINMUX_GIOB3_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB3_DMA_MASK ) \ + | ( PINMUX_GIOB3_DMA_##state ) ) + +#define PINMUX_GIOB4_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB4_DMA_MASK ) \ + | ( PINMUX_GIOB4_DMA_##state ) ) + +#define PINMUX_GIOB5_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB5_DMA_MASK ) \ + | ( PINMUX_GIOB5_DMA_##state ) ) + +#define PINMUX_GIOB6_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB6_DMA_MASK ) \ + | ( PINMUX_GIOB6_DMA_##state ) ) + +#define PINMUX_GIOB7_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB7_DMA_MASK ) \ + | ( PINMUX_GIOB7_DMA_##state ) ) + +#define PINMUX_TEMP1_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TEMP1_ENABLE_MASK ) \ + | ( PINMUX_TEMP1_ENABLE_##state ) ) + +#define PINMUX_TEMP2_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TEMP2_ENABLE_MASK ) \ + | ( PINMUX_TEMP2_ENABLE_##state ) ) + +#define PINMUX_TEMP3_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 174 ] = ( pinMuxReg->PINMUX[ 174 ] & PINMUX_TEMP3_ENABLE_MASK ) \ + | ( PINMUX_TEMP3_ENABLE_##state ) ) + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +void muxInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + pinMuxReg->PINMUX[ 0 ] = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_D4_EMIF_ADDR_00 + | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06; + + pinMuxReg->PINMUX[ 1 ] = PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 + | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10; + + pinMuxReg->PINMUX[ 2 ] = PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 + | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14; + + pinMuxReg->PINMUX[ 3 ] = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 + | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18; + + pinMuxReg->PINMUX[ 4 ] = PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 + | PINMUX_BALL_C17_EMIF_ADDR_21; + + pinMuxReg->PINMUX[ 5 ] = 0U; + + pinMuxReg->PINMUX[ 6 ] = 0U; + + pinMuxReg->PINMUX[ 7 ] = 0U; + + pinMuxReg->PINMUX[ 8 ] = PINMUX_BALL_D16_EMIF_BA_1; + + pinMuxReg->PINMUX[ 9 ] = PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 + | PINMUX_BALL_L17_EMIF_nCS_2; + + pinMuxReg->PINMUX[ 10 ] = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 + | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT; + + pinMuxReg->PINMUX[ 11 ] = PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_ETMDATA_08 + | PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_E7_ETMDATA_10; + + pinMuxReg->PINMUX[ 12 ] = PINMUX_BALL_E6_ETMDATA_11 | PINMUX_BALL_E13_ETMDATA_12 + | PINMUX_BALL_E12_ETMDATA_13 | PINMUX_BALL_E11_ETMDATA_14; + + pinMuxReg->PINMUX[ 13 ] = PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_K15_ETMDATA_16 + | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_M15_ETMDATA_18; + + pinMuxReg->PINMUX[ 14 ] = PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_E5_ETMDATA_20 + | PINMUX_BALL_F5_ETMDATA_21 | PINMUX_BALL_G5_ETMDATA_22; + + pinMuxReg->PINMUX[ 15 ] = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_L5_ETMDATA_24 + | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_N5_ETMDATA_26; + + pinMuxReg->PINMUX[ 16 ] = PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_R5_ETMDATA_28 + | PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_R7_ETMDATA_30; + + pinMuxReg->PINMUX[ 17 ] = PINMUX_BALL_R8_ETMDATA_31 | PINMUX_BALL_R9_ETMTRACECLKIN + | PINMUX_BALL_R10_ETMTRACECLKOUT + | PINMUX_BALL_R11_ETMTRACECTL; + + pinMuxReg->PINMUX[ 18 ] = PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 + | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2; + + pinMuxReg->PINMUX[ 19 ] = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 + | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6; + + pinMuxReg->PINMUX[ 20 ] = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 + | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6; + + pinMuxReg->PINMUX[ 21 ] = PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MIBSPI1NCS_0 + | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_MIBSPI1NCS_2; + + pinMuxReg->PINMUX[ 22 ] = PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MIBSPI1NENA + | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0; + + pinMuxReg->PINMUX[ 23 ] = PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_B2_MIBSPI3NCS_2 + | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA; + + pinMuxReg->PINMUX[ 24 ] = PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI + | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_E19_MIBSPI5NCS_0; + + pinMuxReg->PINMUX[ 25 ] = PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 + | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MIBSPI5NENA; + + pinMuxReg->PINMUX[ 26 ] = PINMUX_BALL_J19_MIBSPI5SIMO_0 + | PINMUX_BALL_E16_MIBSPI5SIMO_1 + | PINMUX_BALL_H17_MIBSPI5SIMO_2 + | PINMUX_BALL_G17_MIBSPI5SIMO_3; + + pinMuxReg->PINMUX[ 27 ] = PINMUX_BALL_J18_MIBSPI5SOMI_0 + | PINMUX_BALL_E17_MIBSPI5SOMI_1 + | PINMUX_BALL_H16_MIBSPI5SOMI_2 + | PINMUX_BALL_G16_MIBSPI5SOMI_3; + + pinMuxReg->PINMUX[ 28 ] = PINMUX_BALL_K18_N2HET1_00 | PINMUX_BALL_V2_N2HET1_01 + | PINMUX_BALL_W5_N2HET1_02 | PINMUX_BALL_U1_N2HET1_03; + + pinMuxReg->PINMUX[ 29 ] = PINMUX_BALL_B12_N2HET1_04 | PINMUX_BALL_V6_N2HET1_05 + | PINMUX_BALL_W3_N2HET1_06 | PINMUX_BALL_T1_N2HET1_07; + + pinMuxReg->PINMUX[ 30 ] = PINMUX_BALL_E18_N2HET1_08 | PINMUX_BALL_V7_N2HET1_09 + | PINMUX_BALL_D19_N2HET1_10 | PINMUX_BALL_E3_N2HET1_11; + + pinMuxReg->PINMUX[ 31 ] = PINMUX_BALL_B4_N2HET1_12 | PINMUX_BALL_N2_N2HET1_13 + | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16; + + pinMuxReg->PINMUX[ 32 ] = PINMUX_BALL_A13_N2HET1_17 | PINMUX_BALL_J1_N2HET1_18 + | PINMUX_BALL_B13_N2HET1_19 | PINMUX_BALL_P2_N2HET1_20; + + pinMuxReg->PINMUX[ 33 ] = PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 + | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_N2HET1_24; + + pinMuxReg->PINMUX[ 34 ] = PINMUX_BALL_A14_N2HET1_26 | PINMUX_BALL_K19_N2HET1_28 + | PINMUX_BALL_B11_N2HET1_30 | PINMUX_BALL_D8_N2HET2_01; + + pinMuxReg->PINMUX[ 35 ] = PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_N2HET2_12 + | PINMUX_BALL_D2_N2HET2_13 | PINMUX_BALL_D1_N2HET2_14; + + pinMuxReg->PINMUX[ 36 ] = PINMUX_BALL_P4_N2HET2_19 | PINMUX_BALL_T5_N2HET2_20 + | PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK; + + pinMuxReg->PINMUX[ 37 ] = PINMUX_BALL_E2_N2HET2_03 | PINMUX_BALL_N3_N2HET2_07; + + pinMuxReg->PINMUX[ 80 ] = ( SIGNAL_AD2EVT_T10 | 0x02020200U ); + + pinMuxReg->PINMUX[ 81 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 82 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 83 ] = ( SIGNAL_GIOA_0_A5 | 0x00020202U ); + + pinMuxReg->PINMUX[ 84 ] = SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 + | SIGNAL_GIOA_4_A6; + + pinMuxReg->PINMUX[ 85 ] = SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 + | SIGNAL_GIOB_0_M2; + + pinMuxReg->PINMUX[ 86 ] = SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_F2 | SIGNAL_GIOB_3_W10 + | SIGNAL_GIOB_4_G1; + + pinMuxReg->PINMUX[ 87 ] = SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 + | SIGNAL_MDIO_F4; + + pinMuxReg->PINMUX[ 88 ] = ( SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9 + | 0x00020000U ); + + pinMuxReg->PINMUX[ 89 ] = SIGNAL_MII_COL_W4 | SIGNAL_MII_CRS_V4; + + pinMuxReg->PINMUX[ 90 ] = SIGNAL_MII_RX_DV_U6 | SIGNAL_MII_RX_ER_U5 + | SIGNAL_MII_RXCLK_T4 | SIGNAL_MII_RXD_0_U4; + + pinMuxReg->PINMUX[ 91 ] = SIGNAL_MII_RXD_1_T3 | SIGNAL_MII_RXD_2_U3 + | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_U7; + + pinMuxReg->PINMUX[ 92 ] = SIGNAL_N2HET1_17_A13 | SIGNAL_N2HET1_19_B13 + | SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4; + + pinMuxReg->PINMUX[ 93 ] = SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 + | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17; + + pinMuxReg->PINMUX[ 94 ] = SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 + | SIGNAL_N2HET2_02_D7 | SIGNAL_N2HET2_03_E2; + + pinMuxReg->PINMUX[ 95 ] = SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 + | SIGNAL_N2HET2_06_D11 | SIGNAL_N2HET2_07_N3; + + pinMuxReg->PINMUX[ 96 ] = SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 + | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16; + + pinMuxReg->PINMUX[ 97 ] = SIGNAL_N2HET2_12_D3 | SIGNAL_N2HET2_13_D2 + | SIGNAL_N2HET2_14_D1 | SIGNAL_N2HET2_15_K4; + + pinMuxReg->PINMUX[ 98 ] = SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 + | SIGNAL_N2HET2_20_T5 | SIGNAL_N2HET2_22_T7; + + pinMuxReg->PINMUX[ 99 ] = SIGNAL_nTZ1_1_N19 | SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3; + + pinMuxReg->PINMUX[ 161 ] = 0x02020200U; + + pinMuxReg->PINMUX[ 162 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 163 ] = 0x00020202U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + PINMUX_GATE_EMIF_CLK_ENABLE( OFF ); + PINMUX_EMIF_OUTPUT_ENABLE( OFF ); + PINMUX_GIOA_DISABLE_HET1_ENABLE( OFF ); + PINMUX_GIOB_DISABLE_HET2_ENABLE( OFF ); + PINMUX_ETHERNET_SELECT( MII ); + PINMUX_ALT_ADC_TRIGGER_SELECT( 1 ); + + PINMUX_ETPWM1_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM2_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM3_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM4_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM5_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM6_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM7_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( OFF ); + PINMUX_ETPWM_TZ1_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ2_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ3_ENABLE( ASYNC ); + PINMUX_ETPWM_EPWM1SYNCI_ENABLE( ASYNC ); + + PINMUX_ETPWM_SOC1A_ENABLE( ON ); + PINMUX_ETPWM_SOC2A_ENABLE( ON ); + PINMUX_ETPWM_SOC3A_ENABLE( ON ); + PINMUX_ETPWM_SOC4A_ENABLE( ON ); + PINMUX_ETPWM_SOC5A_ENABLE( ON ); + PINMUX_ETPWM_SOC6A_ENABLE( ON ); + PINMUX_ETPWM_SOC7A_ENABLE( ON ); + + PINMUX_EQEP1A_FILTER_ENABLE( OFF ); + PINMUX_EQEP1B_FILTER_ENABLE( OFF ); + PINMUX_EQEP1I_FILTER_ENABLE( OFF ); + PINMUX_EQEP1S_FILTER_ENABLE( OFF ); + PINMUX_EQEP2A_FILTER_ENABLE( OFF ); + PINMUX_EQEP2B_FILTER_ENABLE( OFF ); + PINMUX_EQEP2I_FILTER_ENABLE( OFF ); + PINMUX_EQEP2S_FILTER_ENABLE( OFF ); + + PINMUX_ECAP1_FILTER_ENABLE( OFF ); + PINMUX_ECAP2_FILTER_ENABLE( OFF ); + PINMUX_ECAP3_FILTER_ENABLE( OFF ); + PINMUX_ECAP4_FILTER_ENABLE( OFF ); + PINMUX_ECAP5_FILTER_ENABLE( OFF ); + PINMUX_ECAP6_FILTER_ENABLE( OFF ); + + PINMUX_GIOA0_DMA_ENABLE( OFF ); + PINMUX_GIOA1_DMA_ENABLE( OFF ); + PINMUX_GIOA2_DMA_ENABLE( OFF ); + PINMUX_GIOA3_DMA_ENABLE( OFF ); + PINMUX_GIOA4_DMA_ENABLE( OFF ); + PINMUX_GIOA5_DMA_ENABLE( OFF ); + PINMUX_GIOA6_DMA_ENABLE( OFF ); + PINMUX_GIOA7_DMA_ENABLE( OFF ); + PINMUX_GIOB0_DMA_ENABLE( OFF ); + PINMUX_GIOB1_DMA_ENABLE( OFF ); + PINMUX_GIOB2_DMA_ENABLE( OFF ); + PINMUX_GIOB3_DMA_ENABLE( OFF ); + PINMUX_GIOB4_DMA_ENABLE( OFF ); + PINMUX_GIOB5_DMA_ENABLE( OFF ); + PINMUX_GIOB6_DMA_ENABLE( OFF ); + PINMUX_GIOB7_DMA_ENABLE( OFF ); + + pinMuxReg->PINMUX[ 174 ] |= ( uint32 ) ( ~( 0XFEFFFFFFU ) ); + + PINMUX_TEMP1_ENABLE( OFF ); + PINMUX_TEMP2_ENABLE( OFF ); + PINMUX_TEMP3_ENABLE( OFF ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c new file mode 100644 index 00000000000..3813fc4b809 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c @@ -0,0 +1,354 @@ +/** @file pom.c + * @brief POM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "pom.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num) + * @brief set the prog start address,overlay address,and size in the respective register + * for specified region number. + * @param[in] Reg_Config_Ptr - this will have the prog start address and overlay + * addresses and size which have to be set in the registers + * @param[in] Region_Num - Region number is used to access registers(for the specified + * region number) + * + */ +/* SourceId : POM_SourceId_001 */ +/* DesignId : POM_DesignId_001 */ +/* Requirements : CONQ_POM_SR3 */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + pomREG->POMRGNCONF_ST[ Region_Num ].POMPROGSTART = Reg_Config_Ptr->Prog_Reg_Sta_Addr; + pomREG->POMRGNCONF_ST[ Region_Num ].POMOVLSTART = Reg_Config_Ptr->Ovly_Reg_Sta_Addr; + pomREG->POMRGNCONF_ST[ Region_Num ].POMREGSIZE = Reg_Config_Ptr->Reg_Size; + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void POM_Reset(void) + * @brief Reset POM module. + */ +/* SourceId : POM_SourceId_002 */ +/* DesignId : POM_DesignId_002 */ +/* Requirements : CONQ_POM_SR4 */ +void POM_Reset( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = 0x5U; + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void void POM_Init(void) + * @brief Initializes the POM driver + * + * This function initializes the POM driver single function handles all the + * regions,timeouts are also handled. POM_Enable() function must be called after + * POM_Init() function. + */ +/* SourceId : POM_SourceId_003 */ +/* DesignId : POM_DesignId_003 */ +/* Requirements : CONQ_POM_SR2 */ +void POM_Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = INTERNAL_RAM | 0x00000005U; + + /* Configure region 1 */ + pomREG->POMRGNCONF_ST[ 0U ].POMPROGSTART = 0x00000000U; + pomREG->POMRGNCONF_ST[ 0U ].POMOVLSTART = 0x00000000U; + pomREG->POMRGNCONF_ST[ 0U ].POMREGSIZE = ( uint32 ) SIZE_64BYTES; + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void POM_Enable(void) + * @brief Enable POM module. + */ +/* SourceId : POM_SourceId_004 */ +/* DesignId : POM_DesignId_004 */ +/* Requirements : CONQ_POM_SR5 */ +void POM_Enable( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = ( ( pomREG->POMGLBCTRL & 0xFFFFFFF0U ) + | ( uint32 ) 0x0000000AU ); + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void pomGetConfigValue(pom_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the POM configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +/* SourceId : POM_SourceId_005 */ +/* DesignId : POM_DesignId_005 */ +/* Requirements : CONQ_POM_SR6 */ +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_POMGLBCTRL = POM_POMGLBCTRL_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART0 = POM_POMPROGSTART0_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART0 = POM_POMOVLSTART0_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE0 = POM_POMREGSIZE0_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART1 = POM_POMPROGSTART1_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART1 = POM_POMOVLSTART1_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE1 = POM_POMREGSIZE1_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART2 = POM_POMPROGSTART2_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART2 = POM_POMOVLSTART2_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE2 = POM_POMREGSIZE2_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART3 = POM_POMPROGSTART3_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART3 = POM_POMOVLSTART3_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE3 = POM_POMREGSIZE3_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART4 = POM_POMPROGSTART4_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART4 = POM_POMOVLSTART4_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE4 = POM_POMREGSIZE4_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART5 = POM_POMPROGSTART5_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART5 = POM_POMOVLSTART5_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE5 = POM_POMREGSIZE5_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART6 = POM_POMPROGSTART6_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART6 = POM_POMOVLSTART6_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE6 = POM_POMREGSIZE6_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART7 = POM_POMPROGSTART7_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART7 = POM_POMOVLSTART7_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE7 = POM_POMREGSIZE7_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART8 = POM_POMPROGSTART8_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART8 = POM_POMOVLSTART8_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE8 = POM_POMREGSIZE8_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART9 = POM_POMPROGSTART9_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART9 = POM_POMOVLSTART9_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE9 = POM_POMREGSIZE9_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART10 = POM_POMPROGSTART10_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART10 = POM_POMOVLSTART10_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE10 = POM_POMREGSIZE10_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART11 = POM_POMPROGSTART11_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART11 = POM_POMOVLSTART11_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE11 = POM_POMREGSIZE11_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART12 = POM_POMPROGSTART12_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART12 = POM_POMOVLSTART12_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE12 = POM_POMREGSIZE12_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART13 = POM_POMPROGSTART13_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART13 = POM_POMOVLSTART13_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE13 = POM_POMREGSIZE13_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART14 = POM_POMPROGSTART14_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART14 = POM_POMOVLSTART14_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE14 = POM_POMREGSIZE14_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART15 = POM_POMPROGSTART15_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART15 = POM_POMOVLSTART15_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE15 = POM_POMREGSIZE15_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART16 = POM_POMPROGSTART16_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART16 = POM_POMOVLSTART16_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE16 = POM_POMREGSIZE16_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART17 = POM_POMPROGSTART17_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART17 = POM_POMOVLSTART17_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE17 = POM_POMREGSIZE17_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART18 = POM_POMPROGSTART18_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART18 = POM_POMOVLSTART18_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE18 = POM_POMREGSIZE18_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART19 = POM_POMPROGSTART19_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART19 = POM_POMOVLSTART19_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE19 = POM_POMREGSIZE19_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART20 = POM_POMPROGSTART20_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART20 = POM_POMOVLSTART20_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE20 = POM_POMREGSIZE20_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART21 = POM_POMPROGSTART21_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART21 = POM_POMOVLSTART21_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE21 = POM_POMREGSIZE21_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART22 = POM_POMPROGSTART22_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART22 = POM_POMOVLSTART22_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE22 = POM_POMREGSIZE22_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART23 = POM_POMPROGSTART23_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART23 = POM_POMOVLSTART23_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE23 = POM_POMREGSIZE23_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART24 = POM_POMPROGSTART24_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART24 = POM_POMOVLSTART24_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE24 = POM_POMREGSIZE24_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART25 = POM_POMPROGSTART25_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART25 = POM_POMOVLSTART25_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE25 = POM_POMREGSIZE25_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART26 = POM_POMPROGSTART26_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART26 = POM_POMOVLSTART26_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE26 = POM_POMREGSIZE26_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART27 = POM_POMPROGSTART27_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART27 = POM_POMOVLSTART27_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE27 = POM_POMREGSIZE27_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART28 = POM_POMPROGSTART28_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART28 = POM_POMOVLSTART28_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE28 = POM_POMREGSIZE28_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART29 = POM_POMPROGSTART29_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART29 = POM_POMOVLSTART29_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE29 = POM_POMREGSIZE29_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART30 = POM_POMPROGSTART30_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART30 = POM_POMOVLSTART30_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE30 = POM_POMREGSIZE30_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART31 = POM_POMPROGSTART31_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART31 = POM_POMOVLSTART31_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE31 = POM_POMREGSIZE31_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_POMGLBCTRL = pomREG->POMGLBCTRL; + config_reg->CONFIG_POMPROGSTART0 = pomREG->POMRGNCONF_ST[ 0 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART0 = pomREG->POMRGNCONF_ST[ 0 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE0 = pomREG->POMRGNCONF_ST[ 0 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART1 = pomREG->POMRGNCONF_ST[ 1 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART1 = pomREG->POMRGNCONF_ST[ 1 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE1 = pomREG->POMRGNCONF_ST[ 1 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART2 = pomREG->POMRGNCONF_ST[ 2 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART2 = pomREG->POMRGNCONF_ST[ 2 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE2 = pomREG->POMRGNCONF_ST[ 2 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART3 = pomREG->POMRGNCONF_ST[ 3 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART3 = pomREG->POMRGNCONF_ST[ 3 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE3 = pomREG->POMRGNCONF_ST[ 3 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART4 = pomREG->POMRGNCONF_ST[ 4 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART4 = pomREG->POMRGNCONF_ST[ 4 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE4 = pomREG->POMRGNCONF_ST[ 4 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART5 = pomREG->POMRGNCONF_ST[ 5 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART5 = pomREG->POMRGNCONF_ST[ 5 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE5 = pomREG->POMRGNCONF_ST[ 5 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART6 = pomREG->POMRGNCONF_ST[ 6 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART6 = pomREG->POMRGNCONF_ST[ 6 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE6 = pomREG->POMRGNCONF_ST[ 6 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART7 = pomREG->POMRGNCONF_ST[ 7 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART7 = pomREG->POMRGNCONF_ST[ 7 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE7 = pomREG->POMRGNCONF_ST[ 7 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART8 = pomREG->POMRGNCONF_ST[ 8 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART8 = pomREG->POMRGNCONF_ST[ 8 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE8 = pomREG->POMRGNCONF_ST[ 8 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART9 = pomREG->POMRGNCONF_ST[ 9 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART9 = pomREG->POMRGNCONF_ST[ 9 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE9 = pomREG->POMRGNCONF_ST[ 9 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART10 = pomREG->POMRGNCONF_ST[ 10 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART10 = pomREG->POMRGNCONF_ST[ 10 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE10 = pomREG->POMRGNCONF_ST[ 10 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART11 = pomREG->POMRGNCONF_ST[ 11 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART11 = pomREG->POMRGNCONF_ST[ 11 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE11 = pomREG->POMRGNCONF_ST[ 11 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART12 = pomREG->POMRGNCONF_ST[ 12 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART12 = pomREG->POMRGNCONF_ST[ 12 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE12 = pomREG->POMRGNCONF_ST[ 12 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART13 = pomREG->POMRGNCONF_ST[ 13 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART13 = pomREG->POMRGNCONF_ST[ 13 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE13 = pomREG->POMRGNCONF_ST[ 13 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART14 = pomREG->POMRGNCONF_ST[ 14 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART14 = pomREG->POMRGNCONF_ST[ 14 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE14 = pomREG->POMRGNCONF_ST[ 14 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART15 = pomREG->POMRGNCONF_ST[ 15 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART15 = pomREG->POMRGNCONF_ST[ 15 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE15 = pomREG->POMRGNCONF_ST[ 15 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART16 = pomREG->POMRGNCONF_ST[ 16 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART16 = pomREG->POMRGNCONF_ST[ 16 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE16 = pomREG->POMRGNCONF_ST[ 16 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART17 = pomREG->POMRGNCONF_ST[ 17 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART17 = pomREG->POMRGNCONF_ST[ 17 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE17 = pomREG->POMRGNCONF_ST[ 17 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART18 = pomREG->POMRGNCONF_ST[ 18 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART18 = pomREG->POMRGNCONF_ST[ 18 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE18 = pomREG->POMRGNCONF_ST[ 18 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART19 = pomREG->POMRGNCONF_ST[ 19 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART19 = pomREG->POMRGNCONF_ST[ 19 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE19 = pomREG->POMRGNCONF_ST[ 19 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART20 = pomREG->POMRGNCONF_ST[ 20 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART20 = pomREG->POMRGNCONF_ST[ 20 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE20 = pomREG->POMRGNCONF_ST[ 20 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART21 = pomREG->POMRGNCONF_ST[ 20 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART21 = pomREG->POMRGNCONF_ST[ 21 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE21 = pomREG->POMRGNCONF_ST[ 21 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART22 = pomREG->POMRGNCONF_ST[ 21 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART22 = pomREG->POMRGNCONF_ST[ 22 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE22 = pomREG->POMRGNCONF_ST[ 22 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART23 = pomREG->POMRGNCONF_ST[ 22 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART23 = pomREG->POMRGNCONF_ST[ 23 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE23 = pomREG->POMRGNCONF_ST[ 23 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART24 = pomREG->POMRGNCONF_ST[ 23 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART24 = pomREG->POMRGNCONF_ST[ 24 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE24 = pomREG->POMRGNCONF_ST[ 24 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART25 = pomREG->POMRGNCONF_ST[ 24 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART25 = pomREG->POMRGNCONF_ST[ 25 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE25 = pomREG->POMRGNCONF_ST[ 25 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART26 = pomREG->POMRGNCONF_ST[ 25 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART26 = pomREG->POMRGNCONF_ST[ 26 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE26 = pomREG->POMRGNCONF_ST[ 26 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART27 = pomREG->POMRGNCONF_ST[ 26 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART27 = pomREG->POMRGNCONF_ST[ 27 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE27 = pomREG->POMRGNCONF_ST[ 27 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART28 = pomREG->POMRGNCONF_ST[ 27 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART28 = pomREG->POMRGNCONF_ST[ 28 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE28 = pomREG->POMRGNCONF_ST[ 28 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART29 = pomREG->POMRGNCONF_ST[ 28 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART29 = pomREG->POMRGNCONF_ST[ 29 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE29 = pomREG->POMRGNCONF_ST[ 29 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART30 = pomREG->POMRGNCONF_ST[ 30 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART30 = pomREG->POMRGNCONF_ST[ 30 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE30 = pomREG->POMRGNCONF_ST[ 30 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART31 = pomREG->POMRGNCONF_ST[ 31 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART31 = pomREG->POMRGNCONF_ST[ 31 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE31 = pomREG->POMRGNCONF_ST[ 31 ].POMREGSIZE; + } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c new file mode 100644 index 00000000000..12377f8e060 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c @@ -0,0 +1,994 @@ +/** @file sci.c + * @brief SCI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +#include +/* USER CODE END */ + +#include "sci.h" +#include "sys_vim.h" +#include "math.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_sciTransfer + * @brief Interrupt mode globals + * + */ +static volatile struct g_sciTransfer +{ + uint32 mode; /* Used to check for TX interrupt Enable */ + uint32 tx_length; /* Transmit data length in number of Bytes */ + uint32 rx_length; /* Receive data length in number of Bytes */ + uint8 * tx_data; /* Transmit data pointer */ + uint8 * rx_data; /* Receive data pointer */ +} g_sciTransfer_t[ 4U ]; + +/* SourceId : SCI_SourceId_001 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : CONQ_SCI_SR5 */ + +/** @fn void sciInit(void) + * @brief Initializes the SCI Driver + * + * This function initializes the SCI module. + */ +void sciInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b SCI3 */ + + /** - bring SCI3 out of reset */ + sciREG3->GCR0 = 0U; + sciREG3->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG3->CLEARINT = 0xFFFFFFFFU; + sciREG3->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG3->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG3->BRS = 40U; /* baudrate */ + + /** - transmission length */ + sciREG3->FORMAT = 8U - 1U; /* length */ + + /** - set SCI3 pins functional mode */ + sciREG3->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI3 pins default output value */ + sciREG3->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins output direction */ + sciREG3->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins open drain enable */ + sciREG3->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins pullup/pulldown enable */ + sciREG3->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins pullup/pulldown select */ + sciREG3->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG3->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG3->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 2U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 2U ].tx_length = 0U; + g_sciTransfer_t[ 2U ].rx_length = 0U; + + /** - Finaly start SCI3 */ + sciREG3->GCR1 |= 0x80U; + + /** @b initialize @b SCI4 */ + + /** - bring SCI4 out of reset */ + sciREG4->GCR0 = 0U; + sciREG4->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG4->CLEARINT = 0xFFFFFFFFU; + sciREG4->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG4->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG4->BRS = 40U; /* baudrate */ + + /** - transmission length */ + sciREG4->FORMAT = 8U - 1U; /* length */ + + /** - set SCI4 pins functional mode */ + sciREG4->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI4 pins default output value */ + sciREG4->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins output direction */ + sciREG4->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins open drain enable */ + sciREG4->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins pullup/pulldown enable */ + sciREG4->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins pullup/pulldown select */ + sciREG4->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG4->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG4->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 3U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 3U ].tx_length = 0U; + g_sciTransfer_t[ 3U ].rx_length = 0U; + + /** - Finaly start SCI4 */ + sciREG4->GCR1 |= 0x80U; + + /* USER CODE BEGIN (3) */ + /** @b initialize @b SCILIN */ + + /** - bring SCI out of reset */ + scilinREG->GCR0 = 0U; + scilinREG->GCR0 = 1U; + + /** - Disable all interrupts */ + scilinREG->CLEARINT = 0xFFFFFFFFU; + scilinREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + scilinREG->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has + no clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits + */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + scilinREG->BRS = 40U; /* baudrate */ + + /** - transmission length */ + scilinREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + scilinREG->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI pins default output value */ + scilinREG->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins output direction */ + scilinREG->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins open drain enable */ + scilinREG->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown enable */ + scilinREG->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown select */ + scilinREG->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + scilinREG->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - set interrupt enable */ + scilinREG->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 1U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 1U ].tx_length = 0U; + g_sciTransfer_t[ 1U ].rx_length = 0U; + + /** - Finaly start SCILIN */ + scilinREG->GCR1 |= 0x80U; + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_002 */ +/* DesignId : SCI_DesignId_002 */ +/* Requirements : CONQ_SCI_SR6 */ + +/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] sci - sci module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCPIO0 register at runtime, this allows to + * dynamically change the functionality of the SCI pins between functional + * and GIO mode. + */ +void sciSetFunctional( sciBASE_t * sci, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + sci->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_003 */ +/* DesignId : SCI_DesignId_003 */ +/* Requirements : CONQ_SCI_SR7 */ + +/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] sci - sci module base address + * @param[in] baud - baudrate in Hz + * + * Change the SCI baudrate at runtime. + */ +void sciSetBaudrate( sciBASE_t * sci, uint32 baud ) +{ + float64 vclk = 75.000 * 1000000.0; + uint32 f = ( ( sci->GCR1 & 2U ) == 2U ) ? 16U : 1U; + uint32 temp; + float64 temp2; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /*SAFETYMCUSW 96 S MR:6.1 "Calculations including int and float cannot be + * avoided" */ + temp = ( f * ( baud ) ); + temp2 = ( ( vclk ) / ( ( float64 ) temp ) ) - 1U; + temp2 = temp2 + 0.5; + sci->BRS = ( uint32 ) ( ( uint32 ) temp2 & 0x00FFFFFFU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_004 */ +/* DesignId : SCI_DesignId_004 */ +/* Requirements : CONQ_SCI_SR8 */ + +/** @fn uint32 sciIsTxReady(sciBASE_t *sci) + * @brief Check if Tx buffer empty + * @param[in] sci - sci module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 sciIsTxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_TX_INT; +} + +/* SourceId : SCI_SourceId_005 */ +/* DesignId : SCI_DesignId_005 */ +/* Requirements : CONQ_SCI_SR9 */ + +/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) + * @brief Send Byte + * @param[in] sci - sci module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use sciIsTxReady to check for Tx buffer empty + * before calling sciSendByte to avoid waiting. + */ +void sciSendByte( sciBASE_t * sci, uint8 byte ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + sci->TD = byte; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_006 */ +/* DesignId : SCI_DesignId_006 */ +/* Requirements : CONQ_SCI_SR10 */ + +/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, sciSend must not be called again until the + * transfer is complete, when the sciNotification callback will + * be called. In polling mode, sciSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +void sciSend( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + uint8 txdata; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + /*SAFETYMCUSW 139 S MR:13.7 "Mode variable is configured in + * sciEnableNotification()" */ + if( ( g_sciTransfer_t[ index ].mode & ( uint32 ) SCI_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + + g_sciTransfer_t[ index ].tx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].tx_data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + txdata = *g_sciTransfer_t[ index ].tx_data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[ index ].tx_data++; + sci->SETINT = ( uint32 ) SCI_TX_INT; + } + else + { + /* send the data */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in + * Transmit/Receive polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + txdata = *data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_007 */ +/* DesignId : SCI_DesignId_007 */ +/* Requirements : CONQ_SCI_SR11 */ + +/** @fn uint32 sciIsRxReady(sciBASE_t *sci) + * @brief Check if Rx buffer full + * @param[in] sci - sci module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 sciIsRxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_RX_INT; +} + +/* SourceId : SCI_SourceId_008 */ +/* DesignId : SCI_DesignId_008 */ +/* Requirements : CONQ_SCI_SR12 */ + +/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) + * @brief Check if Idle Period is Detected + * @param[in] sci - sci module base address + * + * @return The Idle flag + * + * Checks to see if the SCI Idle flag is set, returns 0 is flags + * not set otherwise will return the Ilde flag itself. + */ +uint32 sciIsIdleDetected( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_IDLE; +} + +/* SourceId : SCI_SourceId_009 */ +/* DesignId : SCI_DesignId_009 */ +/* Requirements : CONQ_SCI_SR13 */ + +/** @fn uint32 sciRxError(sciBASE_t *sci) + * @brief Return Rx Error flags + * @param[in] sci - sci module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +uint32 sciRxError( sciBASE_t * sci ) +{ + uint32 status = ( sci->FLR + & ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ) ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT | ( uint32 ) SCI_PE_INT ); + return status; +} + +/* SourceId : SCI_SourceId_010 */ +/* DesignId : SCI_DesignId_010 */ +/* Requirements : CONQ_SCI_SR14 */ + +/** @fn uint32 sciReceiveByte(sciBASE_t *sci) + * @brief Receive Byte + * @param[in] sci - sci module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use sciIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +uint32 sciReceiveByte( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + return ( sci->RD & ( uint32 ) 0x000000FFU ); +} + +/* SourceId : SCI_SourceId_011 */ +/* DesignId : SCI_DesignId_011 */ +/* Requirements : CONQ_SCI_SR15 */ + +/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer to receive data + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, sciReceive must not be called + * again until the transfer is complete, when the sciNotification + * callback will be called. In polling mode, sciReceive will not + * return until the transfer is complete. + */ +void sciReceive( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( sci->SETINT & ( uint32 ) SCI_RX_INT ) == ( uint32 ) SCI_RX_INT ) + { + /* we are in interrupt mode */ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* clear error flags */ + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ); + + g_sciTransfer_t[ index ].rx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].rx_data = data; + } + else + { + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( uint8 ) ( sci->RD & 0x000000FFU ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_012 */ +/* DesignId : SCI_DesignId_014 */ +/* Requirements : CONQ_SCI_SR18 */ + +/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void sciEnableLoopback( sciBASE_t * sci, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + sci->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + sci->IODFTCTRL = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_013 */ +/* DesignId : SCI_DesignId_015 */ +/* Requirements : CONQ_SCI_SR19 */ + +/** @fn void sciDisableLoopback(sciBASE_t *sci) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * + * This function disable the Loopback mode. + */ +void sciDisableLoopback( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + sci->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_014 */ +/* DesignId : SCI_DesignId_012 */ +/* Requirements : CONQ_SCI_SR16 */ + +/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) + * @brief Enable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +void sciEnableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode |= ( flags & ( uint32 ) SCI_TX_INT ); + sci->SETINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_015 */ +/* DesignId : SCI_DesignId_013 */ +/* Requirements : CONQ_SCI_SR17 */ + +/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) + * @brief Disable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +void sciDisableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode &= ( uint32 ) ( ~( flags & ( uint32 ) SCI_TX_INT ) ); + sci->CLEARINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_016 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : */ + +/** @fn sciEnterResetState(sciBASE_t *sci) + * @brief Enter reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +void sciEnterResetState( sciBASE_t * sci ) +{ + sci->GCR1 &= 0xFFFFFF7FU; +} + +/* SourceId : SCI_SourceId_017 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : */ + +/** @fn scixitResetState(sciBASE_t *sci) + * @brief Exit reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +void sciExitResetState( sciBASE_t * sci ) +{ + sci->GCR1 |= 0x00000080U; +} + +/* SourceId : SCI_SourceId_020 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : CONQ_SCI_SR25 */ + +/** @fn void sci3GetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void sci3GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI3_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI3_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI3_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI3_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI3_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI3_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI3_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI3_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI3_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI3_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = sciREG3->GCR0; + config_reg->CONFIG_GCR1 = sciREG3->GCR1; + config_reg->CONFIG_SETINT = sciREG3->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG3->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG3->FORMAT; + config_reg->CONFIG_BRS = sciREG3->BRS; + config_reg->CONFIG_PIO0 = sciREG3->PIO0; + config_reg->CONFIG_PIO1 = sciREG3->PIO1; + config_reg->CONFIG_PIO6 = sciREG3->PIO6; + config_reg->CONFIG_PIO7 = sciREG3->PIO7; + config_reg->CONFIG_PIO8 = sciREG3->PIO8; + } +} + +/* SourceId : SCI_SourceId_021 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : CONQ_SCI_SR26 */ + +/** @fn void sci4GetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI4 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void sci4GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI4_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI4_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI4_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI4_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI4_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI4_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI4_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI4_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI4_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI4_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = sciREG4->GCR0; + config_reg->CONFIG_GCR1 = sciREG4->GCR1; + config_reg->CONFIG_SETINT = sciREG4->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG4->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG4->FORMAT; + config_reg->CONFIG_BRS = sciREG4->BRS; + config_reg->CONFIG_PIO0 = sciREG4->PIO0; + config_reg->CONFIG_PIO1 = sciREG4->PIO1; + config_reg->CONFIG_PIO6 = sciREG4->PIO6; + config_reg->CONFIG_PIO7 = sciREG4->PIO7; + config_reg->CONFIG_PIO8 = sciREG4->PIO8; + } +} + +void sci_print( char * str ) +{ + sciDisplayText( scilinREG, str, strlen( str ) ); +} + +void sciDisplayText( sciBASE_t * sci, char * text, uint32_t length ) +{ + while( length-- ) + { + /* Wait until we hit an idle state */ + while( ( sci->FLR & ( uint32_t ) SCI_IDLE ) == 4U ) + { + /* Wait */ + } + + /* Send out text */ + sciSendByte( sci, *text++ ); + } +} + +void sciDisplayData( sciBASE_t * sci, uint8_t * text, uint32_t length ) +{ + uint8_t txt = 0; + uint8_t txt1 = 0; + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + text = text + ( length - 1 ); +#endif + + while( length-- ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + txt = *text--; +#else + txt = *text++; +#endif + + txt1 = txt; + + txt &= ~( 0xF0 ); + txt1 &= ~( 0x0F ); + txt1 = txt1 >> 4; + + if( txt <= 0x9 ) + { + txt += 0x30; + } + else if( ( txt > 0x9 ) && ( txt < 0xF ) ) + { + txt += 0x37; + } + else + { + txt = 0x30; + } + + if( txt1 <= 0x9 ) + { + txt1 += 0x30; + } + else if( ( txt1 > 0x9 ) && ( txt1 <= 0xF ) ) + { + txt1 += 0x37; + } + else + { + txt1 = 0x30; + } + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt1 ); /* send out text */ + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt ); /* send out text */ + } +} + +/* USER CODE BEGIN (45) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S new file mode 100644 index 00000000000..327c8a42761 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S @@ -0,0 +1,574 @@ +/*------------------------------------------------------------------------------- + sys_core.asm + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +-------------------------------------------------------------------------*/ + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize CPU Registers + + .weak _coreInitRegisters_ + .type _coreInitRegisters_, %function + +_coreInitRegisters_: + + @ After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, lr + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to FIQ mode (M = 10001) + cps #17 + mov lr, r0 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to IRQ mode (M = 10010) + cps #18 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Abort mode (M = 10111) + cps #23 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Undefined Instruction Mode (M = 11011) + cps #27 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to System Mode ( Shares User Mode registers ) (M = 11111) + cps #31 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + mov r2, #0x40000000 + fmxr fpexc, r2 + + fmdrr d0, r1, r1 + fmdrr d1, r1, r1 + fmdrr d2, r1, r1 + fmdrr d3, r1, r1 + fmdrr d4, r1, r1 + fmdrr d5, r1, r1 + fmdrr d6, r1, r1 + fmdrr d7, r1, r1 + fmdrr d8, r1, r1 + fmdrr d9, r1, r1 + fmdrr d10, r1, r1 + fmdrr d11, r1, r1 + fmdrr d12, r1, r1 + fmdrr d13, r1, r1 + fmdrr d14, r1, r1 + fmdrr d15, r1, r1 + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + bx r0 + +/*-------------------------------------------------------------------------------*/ +@ Initialize Stack Pointers + + .weak _coreInitStackPointer_ + .type _coreInitStackPointer_, %function + +_coreInitStackPointer_: + + cps #17 + ldr sp, fiqSp + cps #18 + ldr sp, irqSp + cps #19 + ldr sp, svcSp + cps #23 + ldr sp, abortSp + cps #27 + ldr sp, undefSp + cps #31 + ldr sp, userSp + bx lr + + +undefSp: .word 0x08000000+0x00000100 +svcSp: .word 0x08000000+0x00000200 +fiqSp: .word 0x08000000+0x00000400 +abortSp: .word 0x08000000+0x00000600 +irqSp: .word 0x08000000+0x00000800 +userSp: .word 0x08000000+0x00000800 + +/*-------------------------------------------------------------------------------*/ +@ Get CPSR Value + + .weak _getCPSRValue_ + .type _getCPSRValue_, %function + +_getCPSRValue_: + + mrs r0, CPSR + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Take CPU to IDLE state + + .weak _gotoCPUIdle_ + .type _gotoCPUIdle_, %function + +_gotoCPUIdle_: + + WFI + nop + nop + nop + nop + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable VFP Unit + + .weak _coreEnableVfp_ + .type _coreEnableVfp_, %function + +_coreEnableVfp_: + + mrc p15, #0x00, r0, c1, c0, #0x02 + orr r0, r0, #0xF00000 + mcr p15, #0x00, r0, c1, c0, #0x02 + mov r0, #0x40000000 + fmxr fpexc, r0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Event Bus Export + + .weak _coreEnableEventBusExport_ + .type _coreEnableEventBusExport_, %function + +_coreEnableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + orr r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Event Bus Export + + .weak _coreDisableEventBusExport_ + .type _coreDisableEventBusExport_, %function + +_coreDisableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + bic r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Offset via Vic controller + + .weak _coreEnableIrqVicOffset_ + .type _coreEnableIrqVicOffset_, %function + +_coreEnableIrqVicOffset_: + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x01000000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault status register + + .weak _coreGetDataFault_ + .type _coreGetDataFault_, %function + +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault status register + + .weak _coreClearDataFault_ + .type _coreClearDataFault_, %function + +_coreClearDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault status register + + .weak _coreGetInstructionFault_ + .type _coreGetInstructionFault_, %function + +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault status register + + .weak _coreClearInstructionFault_ + .type _coreClearInstructionFault_, %function + +_coreClearInstructionFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault address register + + .weak _coreGetDataFaultAddress_ + .type _coreGetDataFaultAddress_, %function + +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault address register + + .weak _coreClearDataFaultAddress_ + .type _coreClearDataFaultAddress_, %function + +_coreClearDataFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault address register + + .weak _coreGetInstructionFaultAddress_ + .type _coreGetInstructionFaultAddress_, %function + +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault address register + + .weak _coreClearInstructionFaultAddress_ + .type _coreClearInstructionFaultAddress_, %function + +_coreClearInstructionFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary data fault status register + + .weak _coreGetAuxiliaryDataFault_ + .type _coreGetAuxiliaryDataFault_, %function + +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary data fault status register + + .weak _coreClearAuxiliaryDataFault_ + .type _coreClearAuxiliaryDataFault_, %function + +_coreClearAuxiliaryDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary instruction fault status register + + .weak _coreGetAuxiliaryInstructionFault_ + .type _coreGetAuxiliaryInstructionFault_, %function + +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary instruction fault status register + + .weak _coreClearAuxiliaryInstructionFault_ + .type _coreClearAuxiliaryInstructionFault_, %function + +_coreClearAuxiliaryInstructionFault_: + + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable IRQ interrupt + + .weak _disable_IRQ_interrupt_ + .type _disable_IRQ_interrupt_, %function + +_disable_IRQ_interrupt_: + + cpsid i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - CPU IRQ + + .weak _enable_IRQ_interrupt_ + .type _enable_IRQ_interrupt_, %function + +_enable_IRQ_interrupt_: + + cpsie i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - CPU IRQ & FIQ + + .weak _enable_interrupt_ + .type _enable_interrupt_, %function + +_enable_interrupt_: + + cpsie if + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear ESM CCM errorss + + .weak _esmCcmErrorsClear_ + .type _esmCcmErrorsClear_, %function + +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + +/*-------------------------------------------------------------------------------*/ +@Initialize RAM memory + + .weak _memInit_ + .type _memInit_, %function + +_memInit_: + ldr r12, MINITGCR @Load MINITGCR register address + mov r4, #0xA + str r4, [r12] @Enable global memory hardware initialization + + ldr r11, MSIENA @Load MSIENA register address + mov r4, #0x1 @Bit position 0 of MSIENA corresponds to SRAM + str r4, [r11] @Enable auto hardware initalisation for SRAM +mloop: @Loop till memory hardware initialization comletes + ldr r5, MSTCGSTAT + ldr r4, [r5] + tst r4, #0x100 + beq mloop + + mov r4, #5 + str r4, [r12] @Disable global memory hardware initialization + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Check Initialize RAM memory + + .weak _checkMemInitOn_ + .type _checkMemInitOn_, %function + +_checkMemInitOn_: + ldr r12, MINITGCR @Load MINITGCR register address +mloop5: ldr r4, [r12] + teq r4, #0xA + beq mloop5 + bx lr + + +MINITGCR: .word 0xFFFFFF5C +MSIENA: .word 0xFFFFFF60 +MSTCGSTAT: .word 0xFFFFFF68 + +/*-------------------------------------------------------------------------------*/ +@ Enable caches + + .weak _cacheEnable_ + .type _cacheEnable_, %function + +_cacheEnable_: + + stmfd sp!, {r0-r1} + mov r0,#0 + + MRC p15, #0, r1, c1, c0, #1 @ Read auxiliary control register + BIC r1, r1, #0x1 << 5 @ bit is default set to disable ECC. Clearing bit 5 + MCR p15, #0, r1, c1, c0, #1 @ enable ECC, generate abort on ECC errors, enable + @ hardware recovery + + MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data + ORR R1, R1, #0x1 <<12 @ instruction cache enable + ORR R1, R1, #0x1 <<2 @ data cache enable + DSB + MCR p15, #0, r0, c15, c5, #0 @ Invalidate entire data cache + DSB @ delay is required, manually added + MCR p15, #0, r0, c7, c5, #0 @ Invalidate entire instruction cache + DSB @ delay is required, manually added + MCR p15, #0, R1, c1, c0, #0 @ enabled cache RAMs + ISB + + ldmfd sp!, {r0-r1} + + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable caches + + .weak _cacheDisable_ + .type _cacheDisable_, %function + +_cacheDisable_: + + stmfd sp!, {r1} + + MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data + BIC R1, R1, #0x1 <<12 @ instruction cache disable + BIC R1, R1, #0x1 <<2 @ data cache disable + DSB + MCR p15, #0, R1, c1, c0, #0 @ disabled cache RAMs + ISB + + ldmfd sp!, {r1} + + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Invalidate Data Cache + + .weak _dCacheInvalidate_ + .type _dCacheInvalidate_, %function + +_dCacheInvalidate_: + MOV R0,#0 + DSB + MCR P15, #0, R0, C15, C5, #0 + DSB + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Invalidate Instruction Cache + + .weak _iCacheInvalidate_ + .type _iCacheInvalidate_, %function + +_iCacheInvalidate_: + MOV R0,#0 + DSB + MCR p15, #0, r0, c7, c5, #0 + DSB + bx lr +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c new file mode 100644 index 00000000000..bca5ac8d98b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c @@ -0,0 +1,654 @@ +/** @file sys_dma.c + * @brief DMA Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_dma.h" +#include "sys_vim.h" + +/** @fn void dmaEnable(void) + * @brief enables DMA module + * + * This function brings DMA out of reset + */ +/* SourceId : DMA_SourceId_001 */ +/* DesignId : DMA_DesignId_001 */ +/* Requirements : CONQ_DMA_SR1 */ +void dmaEnable( void ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + dmaREG->GCTRL = 0x00010000U; /* enable dma */ + dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */ + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void dmaDisable(void) + * @brief disables DMA module + * + * This function disables DMA module + */ +/* SourceId : DMA_SourceId_002 */ +/* DesignId : DMA_DesignId_002 */ +/* Requirements : CONQ_DMA_SR2 */ +void dmaDisable( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + while( ( dmaREG->GCTRL & 0x00004000U ) != 0U ) + { + } /* Wait */ + + /* Disable DMA module */ + dmaREG->GCTRL = 0U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void dmaSetCtrlPacket(uint32 channel) + * @brief Set control packet + * + * This function sets control packet + */ +/* SourceId : DMA_SourceId_003 */ +/* DesignId : DMA_DesignId_003 */ +/* Requirements : CONQ_DMA_SR4 */ +void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT ) +{ + uint8 i, j; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + dmaRAMREG->PCP[ channel ].ISADDR = g_dmaCTRLPKT.SADD; + + dmaRAMREG->PCP[ channel ].IDADDR = g_dmaCTRLPKT.DADD; + + dmaRAMREG->PCP[ channel ].ITCOUNT = ( g_dmaCTRLPKT.FRCNT << 16U ) + | g_dmaCTRLPKT.ELCNT; + + dmaRAMREG->PCP[ channel ].CHCTRL = ( g_dmaCTRLPKT.RDSIZE << 14U ) + | ( g_dmaCTRLPKT.WRSIZE << 12U ) + | ( g_dmaCTRLPKT.TTYPE << 8U ) + | ( g_dmaCTRLPKT.ADDMODERD << 3U ) + | ( g_dmaCTRLPKT.ADDMODEWR << 1U ) + | ( g_dmaCTRLPKT.AUTOINIT ); + + dmaRAMREG->PCP[ channel ].CHCTRL |= ( g_dmaCTRLPKT.CHCTRL << 16U ); + + dmaRAMREG->PCP[ channel ].EIOFF = ( g_dmaCTRLPKT.ELDOFFSET << 16U ) + | ( g_dmaCTRLPKT.ELSOFFSET ); + + dmaRAMREG->PCP[ channel ].FIOFF = ( g_dmaCTRLPKT.FRDOFFSET << 16U ) + | ( g_dmaCTRLPKT.FRSOFFSET ); + + i = channel / 8U; /* Find the register to write */ + j = channel % 8U; /* Find the offset */ + j = ( uint8 ) 7U - j; /* Reverse the order */ + j = j * 4U; /* Find the bit position */ + + dmaREG->PAR[ i ] &= ~( ( uint32 ) 0xFU << j ); + dmaREG->PAR[ i ] |= ( g_dmaCTRLPKT.PORTASGN << j ); + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void dmaSetChEnable(uint32 channel,uint32 type) + * @brief Enable channel + * @param[in] channel DMA channel + * @param[in] type Type of triggering + * - DMA_HW: Enables the selected DMA channel for hardware triggering + * - DMA_SW: Enables the selected DMA channel for software triggering + * + * This function enables the DMA channel for hardware or software triggering + */ +/* SourceId : DMA_SourceId_004 */ +/* DesignId : DMA_DesignId_004 */ +/* Requirements : CONQ_DMA_SR5 */ +void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + if( type == DMA_HW ) + { + dmaREG->HWCHENAS = ( uint32 ) 1U << channel; + } + else + { + dmaREG->SWCHENAS = ( uint32 ) 1U << channel; + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void dmaReqAssign(uint32 channel,uint32 reqline) + * @brief Assign DMA request lines to channels + * @param[in] channel DMA channel + * @param[in] reqline DMA request line + * + * This function assigns DMA request lines to channels + */ +/* SourceId : DMA_SourceId_005 */ +/* DesignId : DMA_DesignId_005 */ +/* Requirements : CONQ_DMA_SR3 */ +void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline ) +{ + uint8 i, j; + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + i = channel / 4U; /* Find the register to configure */ + j = channel % 4U; /* Find the offset */ + j = ( uint8 ) 3U - j; /* reverse the byte order */ + j = j * 8U; /* find the bit location */ + + /* Mapping channel 'i' to request line 'j' */ + dmaREG->DREQASI[ i ] &= ~( ( uint32 ) 0xFFU << j ); + dmaREG->DREQASI[ i ] |= ( ( uint32 ) reqline << j ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) + * @brief Assign Priority to the channel + * @param[in] channel DMA channel + * @param[in] priority Priority queue to which channel needs to be assigned + * - LOWPRIORITY : The selected channel will be assigned to low + * priority queue + * - HIGHPRIORITY: The selected channel will be assigned to high + * priority queue + * + * This function assigns the selected priority to the selected channel + */ +/* SourceId : DMA_SourceId_006 */ +/* DesignId : DMA_DesignId_006 */ +/* Requirements : CONQ_DMA_SR6 */ +void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( priority == LOWPRIORITY ) + { + dmaREG->CHPRIOR = ( uint32 ) 1U << channel; + } + else + { + dmaREG->CHPRIOS = ( uint32 ) 1U << channel; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableInterrupt(dmaChannel_t channel, dmaInterrupt_t inttype, + *dmaIntGroup_t group) + * @brief Enable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be enabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for + *the selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled + *for the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + *for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for + *the selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + *channel + * @param[in] group Group to which the interrupt is routed to. + * - DMA_INTA : Group A + * - DMA_INTB : Group B (Do not use this in case of Lock-step + *device) + * + * This function enables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_007 */ +/* DesignId : DMA_DesignId_007 */ +/* Requirements : CONQ_DMA_SR8 */ +void dmaEnableInterrupt( dmaChannel_t channel, + dmaInterrupt_t inttype, + dmaIntGroup_t group ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + dmaREG->GCHIENAS = ( uint32 ) 1U << channel; + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAS = ( uint32 ) 1U << channel; + dmaREG->FTCMAP = ( dmaREG->FTCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case LFS: + dmaREG->LFSINTENAS = ( uint32 ) 1U << channel; + dmaREG->LFSMAP = ( dmaREG->LFSMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case HBC: + dmaREG->HBCINTENAS = ( uint32 ) 1U << channel; + dmaREG->HBCMAP = ( dmaREG->HBCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case BTC: + dmaREG->BTCINTENAS = ( uint32 ) 1U << channel; + dmaREG->BTCMAP = ( dmaREG->BTCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + default: + break; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} +/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) + * @brief Disable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be disabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for the + * selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled for + * the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + * for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for the + * selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + * channel + * + * This function disables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_008 */ +/* DesignId : DMA_DesignId_008 */ +/* Requirements : CONQ_DMA_SR9 */ +void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAR = ( uint32 ) 1U << channel; + break; + case LFS: + dmaREG->LFSINTENAR = ( uint32 ) 1U << channel; + break; + case HBC: + dmaREG->HBCINTENAR = ( uint32 ) 1U << channel; + break; + case BTC: + dmaREG->BTCINTENAR = ( uint32 ) 1U << channel; + break; + default: + break; + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} +/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) + * @brief Configure start and end address of the region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * @param[in] start_add Start address of the the region + * @param[in] end_add End address of the region + * + * This function configure start and end address of the selected region + */ +/* SourceId : DMA_SourceId_009 */ +/* DesignId : DMA_DesignId_009 */ +/* Requirements : CONQ_DMA_SR10 */ +void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + if( region < 4U ) + { + dmaREG->DMAMPR_L[ region ].STARTADD = start_add; + dmaREG->DMAMPR_L[ region ].ENDADD = end_add; + } + else + { + dmaREG->DMAMPR_H[ region - 4U ].STARTADD = start_add; + dmaREG->DMAMPR_H[ region - 4U ].ENDADD = end_add; + } + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, dmaMPUInt_t + * intenable) + * @brief Enable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * @param[in] access Access permission of the selected region + * - FULLACCESS + * - READONLY + * - WRITEONLY + * - NOACCESS + * @param[in] intenable Interrupt to be enabled or not + * - INTERRUPTA_ENABLE : Enable Group A interrupt for the selected + * region + * - INTERRUPTB_ENABLE : Enable Group B interrupt for the selected + * region (Do not use this in case of Lock-step device) + * - INTERRUPT_DISABLE : Disable interrupt for the selected region + * + * This function enables the selected region with selected access permission with or + * without interrupt enable + */ +/* SourceId : DMA_SourceId_010 */ +/* DesignId : DMA_DesignId_010 */ +/* Requirements : CONQ_DMA_SR11 */ +void dmaEnableRegion( dmaMPURegion_t region, + dmaRegionAccess_t access, + dmaMPUInt_t intenable ) +{ + uint8 bitpos = 0U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( region < 4U ) + { + bitpos = region * 8U; + dmaREG->DMAMPCTRL1 &= ~( uint32 ) ( ( uint32 ) 0xFFU << bitpos ); + + dmaREG->DMAMPCTRL1 |= ( ( uint32 ) 1U << bitpos ) /* Enable the region */ + | ( ( uint32 ) access << ( bitpos + 1U ) ) /* Set access + permission for + the region */ + | ( ( uint32 ) intenable + << ( bitpos + 3U ) ); /* Enable or Disable interrupt + */ + } + else + { + bitpos = ( region - 4U ) * 8U; + dmaREG->DMAMPCTRL2 &= ~( ( uint32 ) 0xFFU << bitpos ); + + dmaREG->DMAMPCTRL2 |= ( ( uint32 ) 1U << bitpos ) /* Enable the region */ + | ( ( uint32 ) access << ( bitpos + 1U ) ) /* Set access + permission for + the region */ + | ( ( uint32 ) intenable + << ( bitpos + 3U ) ); /* Enable or Disable interrupt + */ + } + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void dmaDisableRegion(dmaREGION_t region) + * @brief Disable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * + * This function disables the selected region(no address checking done). + */ +/* SourceId : DMA_SourceId_011 */ +/* DesignId : DMA_DesignId_011 */ +/* Requirements : CONQ_DMA_SR12 */ +void dmaDisableRegion( dmaMPURegion_t region ) +{ + uint8 bitpos = 0U; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + if( region < 4U ) + { + bitpos = region * 8U; + dmaREG->DMAMPCTRL1 &= ~( ( uint32 ) 1U << bitpos ); + } + else + { + bitpos = ( region - 4U ) * 8U; + dmaREG->DMAMPCTRL2 &= ~( ( uint32 ) 1U << bitpos ); + } + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableECC(void) + * @brief Enable ECC + * + * This function enables ECC check + */ +/* SourceId : DMA_SourceId_012 */ +/* DesignId : DMA_DesignId_012 */ +/* Requirements : CONQ_DMA_SR13 */ +void dmaEnableECC( void ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + dmaREG->DMAPCR = 0xAU; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void dmaDisableECC(void) + * @brief Disable ECC + * + * This function disables ECC check + */ +/* SourceId : DMA_SourceId_013 */ +/* DesignId : DMA_DesignId_013 */ +/* Requirements : CONQ_DMA_SR14 */ +void dmaDisableECC( void ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + dmaREG->DMAPCR = 0x5U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn uint32 dmaGetReq(uint32 channel) + * @brief Gets the request line number mapped to the selected channel + * @param[in] channel DMA channel + * + * This function returns the request line number mapped to the selected channel + */ +/* SourceId : DMA_SourceId_014 */ +/* DesignId : DMA_DesignId_014 */ +/* Requirements : CONQ_DMA_SR3 */ +uint32 dmaGetReq( dmaChannel_t channel ) +{ + uint8 i, j; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + i = channel / 4U; /* Find the register to configure */ + j = channel % 4U; /* Find the offset */ + j = ( uint8 ) 3U - j; /* reverse the byte order */ + j = j * 8U; /* find the bit location */ + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + return ( ( dmaREG->DREQASI[ i ] >> j ) & 0xFFU ); +} + +/** @fn boolean dmaIsChannelActive(dmaChannel_t channel) + * @brief Gets the status of the DMA channel + * @param[in] channel DMA channel + * + * This function returns TRUE if the channel is currently being processed using one of + * the FIFOs. + */ +/* SourceId : DMA_SourceId_015 */ +/* DesignId : DMA_DesignId_016 */ +/* Requirements : CONQ_DMA_SR21 */ +boolean dmaIsChannelActive( dmaChannel_t channel ) +{ + boolean status; + uint32 bitmask = ( uint32 ) 1U << channel; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + if( ( dmaREG->DMASTAT & bitmask ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + return status; +} + +/** @fn boolean dmaIsBusy(void) + * @brief Gets the status of the DMA bus + * + * This function returns TRUE if DMA's external bus is busy in data transfers + */ +/* SourceId : DMA_SourceId_016 */ +/* DesignId : DMA_DesignId_015 */ +/* Requirements : CONQ_DMA_SR20 */ +boolean dmaIsBusy( void ) +{ + boolean status; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + if( ( dmaREG->GCTRL & 0x4000U ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : DMA_SourceId_017 */ +/* DesignId : DMA_DesignId_017 */ +/* Requirements : CONQ_DMA_SR22 */ +boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype ) +{ + boolean status; + uint32 mask = ( uint32 ) 1U << channel; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + switch( inttype ) + { + case FTC: + status = ( ( dmaREG->FTCFLAG & mask ) != 0U ); + break; + case LFS: + status = ( ( dmaREG->LFSFLAG & mask ) != 0U ); + break; + case HBC: + status = ( ( dmaREG->HBCFLAG & mask ) != 0U ); + break; + case BTC: + status = ( ( dmaREG->BTCFLAG & mask ) != 0U ); + break; + default: + status = FALSE; + break; + } + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S new file mode 100644 index 00000000000..881537438ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S @@ -0,0 +1,75 @@ +/*--------------------------------------------------------------------------- + sys_intvecs.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +----------------------------------------------------------------------------*/ + + .syntax unified + .cpu cortex-r5 + .arm + + .section .intvecs,"a",%progbits + .type resetEntry, %object + .size resetEntry, .-resetEntry + +/*-------------------------------------------------------------------------------*/ +@ import reference for interrupt routines + + .extern _c_int00 + .extern FreeRTOS_SVC_Handler + .extern _dabort + .extern phantomInterrupt + .weak resetEntry + +/*-------------------------------------------------------------------------------*/ +@ interrupt vectors + +resetEntry: + b _c_int00 +undefEntry: + b undefEntry +svcEntry: + b FreeRTOS_SVC_Handler +prefetchEntry: + b prefetchEntry +dataAbortEntry: + b _dabort + b phantomInterrupt + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * IRQVECREG: 0x18 - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * FIQVECREG: 0x1C - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld new file mode 100644 index 00000000000..46df3d4a77d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld @@ -0,0 +1,272 @@ +/*----------------------------------------------------------------------------*/ +/* sys_link.ld */ +/* */ +/* (c) Texas Instruments 2009-2014, All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Entry Point */ +ENTRY(_c_int00) + +/* Highest address of the stack */ +_estack = 0x8080000; /* end of 512K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 4M + RAM (xrw) : ORIGIN = 0x08000000, LENGTH = 512K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/** Common sizes + * 0x0000 0001 == 1B + * 0x0000 0002 == 2B + * 0x0000 0004 == 4B + * 0x0000 0008 == 8B + * 0x0000 0010 == 16B + * 0x0000 0020 == 32B + * 0x0000 0040 == 64B + * 0x0000 0080 == 128B + * 0x0000 0100 == 256B + * 0x0000 0200 == 512B + * 0x0000 0400 == 1K + * 0x0000 0800 == 2K + * 0x0000 1000 == 4K + * 0x0000 2000 == 8K + * 0x0000 4000 == 16K + * 0x0000 8000 == 32K + * 0x0001 0000 == 64K + * 0x0002 0000 == 128K + * 0x0003 0000 == 192K + * 0x0004 0000 == 256K + * 0x0008 0000 == 512K + * 0x0010 0000 == 1024K/1MB + * 0x0014 0000 == 1280KB/1.25 MB + * 0x0020 0000 == 2048K/2MB + * 0x0040 0000 == 4096K/4MB + * 0x0080 0000 == 8192K/8MB + * 0x0100 0000 == 16MB + * 0x0200 0000 == 32MB + * 0x0400 0000 == 64MB + * 0x0800 0000 == 128MB +*/ + +/* Variables used by FreeRTOS-MPU. */ +/* Cover the entirety of flash */ +__FLASH_segment_start__ = ORIGIN( FLASH ); +__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( FLASH ); + +/* Cover the all of System RAM */ +__SRAM_segment_start__ = ORIGIN( RAM ); +__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM ); + +/* All functions marked as "PRIVILEGED_FUNCTION" get placed in this section */ +__privileged_functions_region_size__ = 64K; +__privileged_functions_start__ = ORIGIN( FLASH ); +__privileged_functions_end__ = __privileged_functions_start__ + __privileged_functions_region_size__; + +/* All variables marked as "PRIVILEGED_DATA" get placed in this section, including the heap */ +__privileged_data_region_size__ = 32K; +__privileged_data_start__ = ORIGIN( RAM ); +__privileged_data_end__ = ORIGIN( RAM ) + __privileged_data_region_size__; + +/* A section of memory at the start of "PRIVILEGED_DATA" for different operating mode stacks */ +__privileged_stacks_region_size__ = 2K; +__privileged_stacks_start__ = ORIGIN( RAM ); +__privileged_stacks_end__ = ORIGIN( RAM ) + __privileged_stacks_region_size__; + +/* Memory block for various dev kit peripherals */ +__peripherals_start__ = 0xF0000000; +__peripherals_length__ = 256M; +__peripherals_end__ = __peripherals_start__ + __peripherals_length__; + +/* Seperate memory block for privileged system */ +__privileged_system_start__ = 0xFFF80000; +__privileged_system_length__ = 512K; +__privileged_system_end__ = __privileged_system_start__ + __privileged_system_length__; + +/* The first 2K of space in RAM is used for different processor mode stacks */ +__privileged_stack_region_size = 0x800; + +/* Define output sections */ +SECTIONS +{ + /* The ISR vector goes first into RAM */ + .privileged_functions : + { + . = ALIGN(4); + KEEP(*(.intvecs)) + . = ALIGN(4); + + *(privileged_functions) + . = ALIGN(4); + /* Fill rest of the region with a known value */ + FILL(0xADDEADDE); + /* Ensure that non-privileged code is placed after the region reserved for + * privileged kernel code. This is done for MPU Region Alignment */ + /* Note that dot (.) actually refers to the byte offset from the start of + * the current section (.privileged_functions in this case). As a result, + * setting dot (.) to a value sets the size of the section. */ + . = __privileged_functions_region_size__; + } >FLASH + + .freertos_system_calls : + { + . = ALIGN(4); + /* Place the FreeRTOS System Calls first in the unprivileged region. */ + __syscalls_flash_start__ = .; + *(freertos_system_calls) + __syscalls_flash_end__ = .; + . = ALIGN(4); + + } >FLASH + + /* This variable is used in portASM.S to determine if a FreeRTOS System Call + * was raised from this specific section of flash */ + __syscalls_flash_length__ = __syscalls_flash_end__ - __syscalls_flash_start__; + + /* The program code and other data goes into RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into RAM */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _siPrivData = LOADADDR(.privileged_data); + /* FreeRTOS kernel data. */ + .privileged_data : + { + /* Leave a block of memory for different Processor mode stacks. + * These are set in sys_core.S */ + . = ALIGN(4); + /* Mark the start of the region for debugging purposes. */ + __start_privileged_stack_region = .; + . = __privileged_stack_region_size; + . = ALIGN(4); + /* Mark the end of the region for debugging purposes. */ + __end_privileged_stack_region = .; + + __start_priv_data = .; /* Create a global symbol at privileged data start. */ + *(privileged_data) + . = ALIGN(4); + __end_priv_data = .; /* Create a global symbol at privileged data end. */ + FILL(0xADDE); /* Fill RAM with known value */ + /* Ensure that non-privileged data is placed after the region reserved for + * privileged kernel data. */ + /* Note that dot (.) actually refers to the byte offset from the start of + * the current section (.privileged_data in this case). As a result, setting + * dot (.) to a value sets the size of the section. */ + . = __privileged_data_region_size__; + . = ALIGN(4); + } >RAM AT> FLASH + + /* Used by sys_startup.c to initialize data */ + _sidata = LOADADDR(.data); + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c new file mode 100644 index 00000000000..2a4ece6cb9c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c @@ -0,0 +1,1081 @@ +/** @file sys_pcr.c + * @brief PCR Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the PCR driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pcr.h" + +/** @fn void peripheral_Memory_Protection_Set(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Set Peripheral Memory Protection + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function enables peripheral memory protection (write in privileged mode only) + * for the selected frame + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_001 */ +/* DesignId : PCR_DesignId_001 */ +/* Requirements : CONQ_PCR_SR1 */ +void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PMPROTSET0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PMPROTSET1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_Protection_Clr(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Clear Peripheral Memory Protection + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function disables peripheral memory protection (write in privileged mode only) + * for the selected frame + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_002 */ +/* DesignId : PCR_DesignId_002 */ +/* Requirements : CONQ_PCR_SR2 */ +void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PMPROTCLR0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PMPROTCLR1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_Protection_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Protection + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function enables peripheral frame protection (write in privileged mode only) for + *the selected frame + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_003 */ +/* DesignId : PCR_DesignId_003 */ +/* Requirements : CONQ_PCR_SR3 */ +void peripheral_Frame_Protection_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PPROTSET0 = quadrant << PS * 4U; + } + else if( PS < 16U ) + { + pcr->PPROTSET1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PPROTSET2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PPROTSET3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_Protection_Clr(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Clear Peripheral Frame Protection + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function disables peripheral frame protection (write in privileged mode only) + *for the selected frame + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_004 */ +/* DesignId : PCR_DesignId_004 */ +/* Requirements : CONQ_PCR_SR4 */ +void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PPROTCLR0 = quadrant << PS * 4U; + } + else if( PS < 16U ) + { + pcr->PPROTCLR1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PPROTCLR2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PPROTCLR3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_PowerDown_Set(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Set Peripheral Memory Power Down + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function disables the clocks to the selected peripheral memory + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_005 */ +/* DesignId : PCR_DesignId_005 */ +/* Requirements : CONQ_PCR_SR5 */ +void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PCSPWRDWNSET0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PCSPWRDWNSET1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_PowerDown_Clr(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Clear Peripheral Memory Power Down + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function enables the clocks to the selected peripheral memory + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_006 */ +/* DesignId : PCR_DesignId_006 */ +/* Requirements : CONQ_PCR_SR6 */ +void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PCSPWRDWNCLR0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PCSPWRDWNCLR1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_PowerDown_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Power Down + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function disables the clocks to the selected quadrant(s) + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_007 */ +/* DesignId : PCR_DesignId_007 */ +/* Requirements : CONQ_PCR_SR7 */ +void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PSPWRDWNSET0 = quadrant << ( PS * 4U ); + } + else if( PS < 16U ) + { + pcr->PSPWRDWNSET1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PSPWRDWNSET2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PSPWRDWNSET3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_PowerDown_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Power Down + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function enables the clocks to the selected quadrant(s) + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_008*/ +/* DesignId : PCR_DesignId_008 */ +/* Requirements : CONQ_PCR_SR8 */ +void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PSPWRDWNCLR0 = quadrant << ( PS * 4U ); + } + else if( PS < 16U ) + { + pcr->PSPWRDWNCLR1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PSPWRDWNCLR2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PSPWRDWNCLR3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, peripheral_Frame_t PS, + *uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_009 */ +/* DesignId : PCR_DesignId_010 */ +/* Requirements : CONQ_PCR_SR14 */ +void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, peripheral_Frame_t + *PS, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_010 */ +/* DesignId : PCR_DesignId_009 */ +/* Requirements : CONQ_PCR_SR13 */ +void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Frame_t PPS, uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPS Privileged Peripheral chip select (PPS0..PPS7) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_011 */ +/* DesignId : PCR_DesignId_012 */ +/* Requirements : CONQ_PCR_SR16 */ +void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Frame_t PPS, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPS Privileged Peripheral chip select (PPS0..PPS7) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_012 */ +/* DesignId : PCR_DesignId_011 */ +/* Requirements : CONQ_PCR_SR15 */ +void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Extended_Frame_t PPSE, uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPSE Privileged Peripheral Extended chip select (PPSE0..PPSE31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSEx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_013 */ +/* DesignId : PCR_DesignId_014 */ +/* Requirements : CONQ_PCR_SR18 */ +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Extended_Frame_t PPSE, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPSE Privileged Peripheral Extended chip select (PPSE0..PPSE31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSEx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_014 */ +/* DesignId : PCR_DesignId_013 */ +/* Requirements : CONQ_PCR_SR17 */ +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_MasterIDFilter_Enable(pcrBASE_t *pcr, peripheral_Memory_t + *PCS, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_015 */ +/* DesignId : PCR_DesignId_016 */ +/* Requirements : CONQ_PCR_SR20 */ +void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PCS / 2U; + j = PCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PCSxMSTID[ i ] |= ( uint32 ) 1U << ( master + j ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_MasterIDFilter_Disable(pcrBASE_t *pcr, peripheral_Memory_t + *PCS, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_016 */ +/* DesignId : PCR_DesignId_015 */ +/* Requirements : CONQ_PCR_SR19 */ +void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PCS / 2U; + j = PCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PCSxMSTID[ i ] &= ~( ( uint32 ) 1U << ( master + j ) ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Memory_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Memory_t PPCS, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PPCS Privileged Peripheral memory chip select (PPCS0..PPCS15) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_017 */ +/* DesignId : PCR_DesignId_018 */ +/* Requirements : CONQ_PCR_SR22 */ +void privileged_Peripheral_Memory_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PPCS / 2U; + j = PPCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PPCSxMSTID[ i ] |= ( uint32 ) 1U << ( master + j ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Memory_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Memory_t PPCS, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PPCS Privileged Peripheral memory chip select (PPCS0..PPCS15) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_018 */ +/* DesignId : PCR_DesignId_017 */ +/* Requirements : CONQ_PCR_SR21 */ +void privileged_Peripheral_Memory_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PPCS / 2U; /* Find the index of the register to be written */ + j = PPCS % 2U; /* Find the bit position */ + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PPCSxMSTID[ i ] &= ~( ( uint32 ) 1U << ( master + j ) ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void pcrEnableMasterIDCheck(pcrBASE_t *pcr) + * @brief Enable Master-ID check + * + * @param[in] pcr PCR segment (pcrREG1..pcrREG3) + * + * This function enables master-id check for the selected PCR. + */ +/* SourceId : PCR_SourceId_019 */ +/* DesignId : PCR_DesignId_019 */ +/* Requirements : CONQ_PCR_SR11 */ +void pcrEnableMasterIDCheck( pcrBASE_t * pcr ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + pcr->MSTIDENA = 0xAU; + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn void pcrDisableMasterIDCheck(pcrBASE_t *pcr) + * @brief Disable Master-ID check + * + * @param[in] pcr PCR segment (pcrREG1..pcrREG3) + * + * This function disables master-id check for the selected PCR. + */ +/* SourceId : PCR_SourceId_020 */ +/* DesignId : PCR_DesignId_020*/ +/* Requirements : CONQ_PCR_SR12 */ +void pcrDisableMasterIDCheck( pcrBASE_t * pcr ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + pcr->MSTIDENA = 0x5U; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c new file mode 100644 index 00000000000..ab428fddc7f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c @@ -0,0 +1,77 @@ +/** @file sys_phantom.c + * @brief Phantom Interrupt Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Phantom Interrupt Handler + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_common.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Phantom Interrupt Handler */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +void phantomInterrupt( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/** @fn void custom_dabort(void) + * @brief Custom Data abort routine for the application. + * + * Custom Data abort routine for the application. + */ +void custom_dabort( void ) +{ + /* Need custom data abort handler here. + * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC + * logic. + */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c new file mode 100644 index 00000000000..a6339001706 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c @@ -0,0 +1,229 @@ +/** @file sys_pmm.c + * @brief PCR Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pmm.h" + +#define PMM_LODICPWRSTAT 0x3U +#define PMM_DOMAINON 0x100U +#define PMM_AUTOCLKWAKEENA 0x1U + +/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns on Logic Power Domain + * @param[in] logicPD - Power Domain to be turned on + * - PMM_LOGICPD2: Power domain PD2 will be turned on + * - PMM_LOGICPD3: Power domain PD3 will be turned on + * - PMM_LOGICPD4: Power domain PD4 will be turned on + * - PMM_LOGICPD5: Power domain PD5 will be turned on + * - PMM_LOGICPD6: Power domain PD6 will be turned on + * + * This function turns on the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_001 */ +/* DesignId : PMM_DesignId_001 */ +/* Requirements : CONQ_PMM_SR3 */ +boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + boolean status = TRUE; + + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + /* Power On the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x05000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x00050000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000500U; + } + else if( logicPD == PMM_LOGICPD5 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) | 0x00000005U; + } + else if( logicPD == PMM_LOGICPD6 ) + { + pmmREG->LOGICPDPWRCTRL1 = 0x05000000U; + } + else + { + /* Invalid input */ + status = FALSE; + } + + if( status == TRUE ) + { + if( ( pmmREG->GLOBALCTRL1 & PMM_AUTOCLKWAKEENA ) == 0U ) + { + /* Enable clocks to the power domain */ + pmmREG->PDCLKDISCLR = ( uint32 ) 1U << logicPD; + } + + /* Wait until the domain is powered on */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_DOMAINON ) == 0U ) + { + /* Add timeout code here */ + } + } + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + return status; +} + +/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns off Logic Power Domain + * @param[in] logicPD - Power Domain to be tured off + * - PMM_LOGICPD2: Power domain PD2 will be turned off + * - PMM_LOGICPD3: Power domain PD3 will be turned off + * - PMM_LOGICPD4: Power domain PD4 will be turned off + * - PMM_LOGICPD5: Power doamin PD5 will be turned off + * - PMM_LOGICPD6: Power doamin PD5 will be turned off + * + * This function turns off the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_002 */ +/* DesignId : PMM_DesignId_002 */ +/* Requirements : CONQ_PMM_SR4 */ +boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + boolean status = TRUE; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* Disable clocks to the power domain */ + pmmREG->PDCLKDISSET = ( uint32 ) 1U << logicPD; + + /* Power Down the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x0A000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x000A0000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000A00U; + } + else if( logicPD == PMM_LOGICPD5 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) | 0x0000000AU; + } + else if( logicPD == PMM_LOGICPD6 ) + { + pmmREG->LOGICPDPWRCTRL1 = 0x0A000000U; + } + else + { + /* Invalid input */ + status = FALSE; + } + + if( status == TRUE ) + { + /* Wait until the domain is powered down */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LODICPWRSTAT ) != 0U ) + { + /* Add timeout code here */ + } + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + return status; +} + +/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) + * @brief Check if the power domain is active or not + * @param[in] logicPD - Power Domain to be be checked + * - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not + * - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not + * - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not + * - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not + * - PMM_LOGICPD6: Checks whether Power domain PD6 is active or not + * @return The function will return: + * - TRUE : When the selected power domain is in Active state. + * - FALSE: When the selected power domain is in OFF state. + * + * This function checks whether the selected power domain is active or not. + * + */ +/* SourceId : PMM_SourceId_003 */ +/* DesignId : PMM_DesignId_003 */ +/* Requirements : CONQ_PMM_SR5 */ +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ) +{ + boolean status; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + if( logicPD == PMM_LOGICPD1 ) + { + status = TRUE; + } + else + { + if( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LODICPWRSTAT ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S new file mode 100644 index 00000000000..cf54214b1ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S @@ -0,0 +1,215 @@ +/*------------------------------------------------------------------------------ + sys_pmu.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +---------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize Pmu +@ Note: It will reset all counters + + .weak _pmuInit_ + .type _pmuInit_, %function + +_pmuInit_: + + @ set control register + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #(1 << 4) + 6 + 1 + mcr p15, #0, r0, c9, c12, #0 + @ clear flags + mov r0, #0 + sub r0, r0, #1 + mcr p15, #0, r0, c9, c12, #3 + @ select counter 0 event + mov r0, #0 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 1 event + mov r0, #1 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 2 event + mov r0, #2 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Counters Global [Cycle, Event [0..2]] +@ Note: It will reset all counters + + .weak _pmuEnableCountersGlobal_ + .type _pmuEnableCountersGlobal_, %function + +_pmuEnableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #7 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Counters Global [Cycle, Event [0..2]] + + .weak _pmuDisableCountersGlobal_ + .type _pmuDisableCountersGlobal_, %function + +_pmuDisableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter + + .weak _pmuResetCycleCounter_ + .type _pmuResetCycleCounter_, %function + +_pmuResetCycleCounter_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #4 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Event Counters [0..2] + + .weak _pmuResetEventCounters_ + .type _pmuResetEventCounters_, %function + +_pmuResetEventCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #2 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter abd Event Counters [0..2] + + .weak _pmuResetCounters_ + .type _pmuResetCounters_, %function + +_pmuResetCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #6 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Start Counters [Cycle, 0..2] + + .weak _pmuStartCounters_ + .type _pmuStartCounters_, %function + +_pmuStartCounters_: + + mcr p15, #0, r0, c9, c12, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Stop Counters [Cycle, 0..2] + + .weak _pmuStopCounters_ + .type _pmuStopCounters_, %function + +_pmuStopCounters_: + + mcr p15, #0, r0, c9, c12, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Set Count event + + .weak _pmuSetCountEvent_ + .type _pmuSetCountEvent_, %function + +_pmuSetCountEvent_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mcr p15, #0, r1, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Cycle Count + + .weak _pmuGetCycleCount_ + .type _pmuGetCycleCount_, %function + +_pmuGetCycleCount_: + + mrc p15, #0, r0, c9, c13, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Event Counter Count Value + + .weak _pmuGetEventCount_ + .type _pmuGetEventCount_, %function + +_pmuGetEventCount_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mrc p15, #0, r0, c9, c13, #2 @ read event counter + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Overflow Flags + + .weak _pmuGetOverflow_ + .type _pmuGetOverflow_, %function + +_pmuGetOverflow_: + + mrc p15, #0, r0, c9, c12, #3 @ read overflow + mov r1, #0 + sub r1, r1, #1 + mcr p15, #0, r1, c9, c12, #3 @ clear flags + bx lr + +/*-------------------------------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c new file mode 100644 index 00000000000..b3771880625 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c @@ -0,0 +1,298 @@ +/** @file sys_startup.c + * @brief Startup Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Include Files + * - Type Definitions + * - External Functions + * - VIM RAM Setup + * - Startup Routine + * . + * which are relevant for the Startup. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "sys_common.h" +#include "system.h" +#include "sys_vim.h" +#include "sys_core.h" +#include "esm.h" +#include "sys_mpu.h" +#include "errata_SSWF021_45.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* External Functions */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(main should be declared by the user)" + */ +extern void main( void ); +/*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be present)" + */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(Extern declaration present in the + * library)" */ +extern void exit( int _status ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +void handlePLLLockFail( void ); +/* Startup Routine */ +void _c_int00( void ) __attribute__( ( noreturn ) ); +#define PLL_RETRIES 5U +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +__attribute__( ( naked ) ) + +/* SourceId : STARTUP_SourceId_001 */ +/* DesignId : STARTUP_DesignId_001 */ +/* Requirements : CONQ_STARTUP_SR1 */ +void _c_int00( void ) +{ + register resetSource_t rstSrc; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /* Initialize Core Registers to avoid CCM Error */ + _coreInitRegisters_(); + + /* Initialize Stack Pointers */ + _coreInitStackPointer_(); + + /* Reset handler: the following instructions read from the system exception status + * register to identify the cause of the CPU reset. + */ + rstSrc = getResetSource(); + + switch( rstSrc ) + { + case POWERON_RESET: + /* Initialize L2RAM to avoid ECC errors right after power on */ + _memInit_(); + + /* Add condition to check whether PLL can be started successfully */ + if( _errata_SSWF021_45_both_plls( PLL_RETRIES ) != 0U ) + { + /* Put system in a safe state */ + handlePLLLockFail(); + } + break; + + /*SAFETYMCUSW 62 S MR:15.2, 15.5 "Need to continue to handle + * POWERON Reset" */ + case DEBUG_RESET: + case EXT_RESET: + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /* Initialize L2RAM to avoid ECC errors right after power on */ + if( rstSrc != POWERON_RESET ) + { + _memInit_(); + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /* Check if there were ESM group3 errors during power-up. + * These could occur during eFuse auto-load or during reads from flash OTP + * during power-up. Device operation is not reliable and not recommended + * in this case. */ + if( ( esmREG->SR1[ 2 ] ) != 0U ) + { + esmGroup3Notification( esmREG, esmREG->SR1[ 2 ] ); + } + + /* Initialize System - Clock, Flash settings with Efuse self check */ + systemInit(); + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Enable IRQ offset via Vic controller */ + _coreEnableIrqVicOffset_(); + + /* Initialize VIM table */ + vimInit(); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + /* Configure system response to error conditions signaled to the ESM group1 */ + /* This function can be configured from the ESM tab of HALCoGen */ + esmInit(); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + break; + + case OSC_FAILURE_RESET: + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + break; + + case WATCHDOG_RESET: + case WATCHDOG2_RESET: + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + break; + + case CPU0_RESET: + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + break; + + case SW_RESET: + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + break; + + default: + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + break; + } + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + { + extern uint32 _sidata, _sdata, _edata; + extern uint32 _siPrivData, __privileged_data_start__, __privileged_data_end__; + uint32 *src, *dst; + + src = &_sidata; + dst = &_sdata; + + while( dst < &_edata ) + { + *dst++ = *src++; + } + + src = &_siPrivData; + dst = &__privileged_data_start__; + + while( dst < &__privileged_data_end__ ) + { + *dst++ = *src++; + } + } + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* call the application */ + /*SAFETYMCUSW 296 S MR:8.6 "Startup code(library functions at block scope)" + */ + /*SAFETYMCUSW 326 S MR:8.2 "Startup code(Declaration for main in library)" + */ + /*SAFETYMCUSW 60 D MR:8.8 "Startup code(Declaration for main in + * library;Only doing an extern for the same)" */ + main(); + + /*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be + * present)" */ + exit( 0 ); + /* USER CODE BEGIN (77) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void handlePLLLockFail(void) + * @brief This function handles PLL lock fail. + */ +/* USER CODE BEGIN (30) */ +/* USER CODE END */ +void handlePLLLockFail( void ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + while( 1 ) + { + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (33) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c new file mode 100644 index 00000000000..fd3b1c86be6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c @@ -0,0 +1,855 @@ +/** @file sys_vim.c + * @brief VIM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_vim.h" +#include "system.h" +#include "esm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Vim Ram Definition */ +/** @struct vimRam + * @brief Vim Ram Definition + * + * This type is used to access the Vim Ram. + */ +/** @typedef vimRAM_t + * @brief Vim Ram Type Definition + * + * This type is used to access the Vim Ram. + */ +typedef volatile struct vimRam +{ + t_isrFuncPTR ISR[ VIM_CHANNELS ]; +} vimRAM_t; + +#define vimRAM ( ( vimRAM_t * ) 0xFFF82000U ) + +static const t_isrFuncPTR s_vim_init[ 128U ] = { + &phantomInterrupt, &esmHighInterrupt, /* Channel 0 */ + &phantomInterrupt, /* Channel 1 */ + &FreeRTOS_IRQ_Handler, /* Channel 2 */ + &phantomInterrupt, /* Channel 3 */ + &phantomInterrupt, /* Channel 4 */ + &phantomInterrupt, /* Channel 5 */ + &phantomInterrupt, /* Channel 6 */ + &phantomInterrupt, /* Channel 7 */ + &phantomInterrupt, /* Channel 8 */ + &phantomInterrupt, /* Channel 9 */ + &phantomInterrupt, /* Channel 10 */ + &phantomInterrupt, /* Channel 11 */ + &phantomInterrupt, /* Channel 12 */ + &phantomInterrupt, /* Channel 13 */ + &phantomInterrupt, /* Channel 14 */ + &phantomInterrupt, /* Channel 15 */ + &phantomInterrupt, /* Channel 16 */ + &phantomInterrupt, /* Channel 17 */ + &phantomInterrupt, /* Channel 18 */ + &phantomInterrupt, /* Channel 19 */ + &phantomInterrupt, /* Channel 20 */ + &FreeRTOS_IRQ_Handler, /* Channel 21 */ + &phantomInterrupt, /* Channel 22 */ + &phantomInterrupt, /* Channel 23 */ + &phantomInterrupt, /* Channel 24 */ + &phantomInterrupt, /* Channel 25 */ + &phantomInterrupt, /* Channel 26 */ + &phantomInterrupt, /* Channel 27 */ + &phantomInterrupt, /* Channel 28 */ + &phantomInterrupt, /* Channel 29 */ + &phantomInterrupt, /* Channel 30 */ + &phantomInterrupt, /* Channel 31 */ + &phantomInterrupt, /* Channel 32 */ + &phantomInterrupt, /* Channel 33 */ + &phantomInterrupt, /* Channel 34 */ + &phantomInterrupt, /* Channel 35 */ + &phantomInterrupt, /* Channel 36 */ + &phantomInterrupt, /* Channel 37 */ + &phantomInterrupt, /* Channel 38 */ + &phantomInterrupt, /* Channel 39 */ + &phantomInterrupt, /* Channel 40 */ + &phantomInterrupt, /* Channel 41 */ + &phantomInterrupt, /* Channel 42 */ + &phantomInterrupt, /* Channel 43 */ + &phantomInterrupt, /* Channel 44 */ + &phantomInterrupt, /* Channel 45 */ + &phantomInterrupt, /* Channel 46 */ + &phantomInterrupt, /* Channel 47 */ + &phantomInterrupt, /* Channel 48 */ + &phantomInterrupt, /* Channel 49 */ + &phantomInterrupt, /* Channel 50 */ + &phantomInterrupt, /* Channel 51 */ + &phantomInterrupt, /* Channel 52 */ + &phantomInterrupt, /* Channel 53 */ + &phantomInterrupt, /* Channel 54 */ + &phantomInterrupt, /* Channel 55 */ + &phantomInterrupt, /* Channel 56 */ + &phantomInterrupt, /* Channel 57 */ + &phantomInterrupt, /* Channel 58 */ + &phantomInterrupt, /* Channel 59 */ + &phantomInterrupt, /* Channel 60 */ + &phantomInterrupt, /* Channel 61 */ + &phantomInterrupt, /* Channel 62 */ + &phantomInterrupt, /* Channel 63 */ + &phantomInterrupt, /* Channel 64 */ + &phantomInterrupt, /* Channel 65 */ + &phantomInterrupt, /* Channel 66 */ + &phantomInterrupt, /* Channel 67 */ + &phantomInterrupt, /* Channel 68 */ + &phantomInterrupt, /* Channel 69 */ + &phantomInterrupt, /* Channel 70 */ + &phantomInterrupt, /* Channel 71 */ + &phantomInterrupt, /* Channel 72 */ + &phantomInterrupt, /* Channel 73 */ + &phantomInterrupt, /* Channel 74 */ + &phantomInterrupt, /* Channel 75 */ + &phantomInterrupt, /* Channel 76 */ + &phantomInterrupt, /* Channel 77 */ + &phantomInterrupt, /* Channel 78 */ + &phantomInterrupt, /* Channel 79 */ + &phantomInterrupt, /* Channel 80 */ + &phantomInterrupt, /* Channel 81 */ + &phantomInterrupt, /* Channel 82 */ + &phantomInterrupt, /* Channel 83 */ + &phantomInterrupt, /* Channel 84 */ + &phantomInterrupt, /* Channel 85 */ + &phantomInterrupt, /* Channel 86 */ + &phantomInterrupt, /* Channel 87 */ + &phantomInterrupt, /* Channel 88 */ + &phantomInterrupt, /* Channel 89 */ + &phantomInterrupt, /* Channel 90 */ + &phantomInterrupt, /* Channel 91 */ + &phantomInterrupt, /* Channel 92 */ + &phantomInterrupt, /* Channel 93 */ + &phantomInterrupt, /* Channel 94 */ + &phantomInterrupt, /* Channel 95 */ + &phantomInterrupt, /* Channel 96 */ + &phantomInterrupt, /* Channel 97 */ + &phantomInterrupt, /* Channel 98 */ + &phantomInterrupt, /* Channel 99 */ + &phantomInterrupt, /* Channel 100 */ + &phantomInterrupt, /* Channel 101 */ + &phantomInterrupt, /* Channel 102 */ + &phantomInterrupt, /* Channel 103 */ + &phantomInterrupt, /* Channel 104 */ + &phantomInterrupt, /* Channel 105 */ + &phantomInterrupt, /* Channel 106 */ + &phantomInterrupt, /* Channel 107 */ + &phantomInterrupt, /* Channel 108 */ + &phantomInterrupt, /* Channel 109 */ + &phantomInterrupt, /* Channel 110 */ + &phantomInterrupt, /* Channel 111 */ + &phantomInterrupt, /* Channel 112 */ + &phantomInterrupt, /* Channel 113 */ + &phantomInterrupt, /* Channel 114 */ + &phantomInterrupt, /* Channel 115 */ + &phantomInterrupt, /* Channel 116 */ + &phantomInterrupt, /* Channel 117 */ + &phantomInterrupt, /* Channel 118 */ + &phantomInterrupt, /* Channel 119 */ + &phantomInterrupt, /* Channel 120 */ + &phantomInterrupt, /* Channel 121 */ + &phantomInterrupt, /* Channel 122 */ + &phantomInterrupt, /* Channel 123 */ + &phantomInterrupt, /* Channel 124 */ + &phantomInterrupt, /* Channel 125 */ + &phantomInterrupt, /* Channel 126 */ +}; +void vimECCErrorHandler( void ); + +/* SourceId : VIM_SourceId_001 */ +/* DesignId : VIM_DesignId_001 */ +/* Requirements : CONQ_VIM_SR2 */ +/** @fn void vimInit(void) + * @brief Initializes VIM module + * + * This function initializes VIM RAM and registers + */ + +void vimInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable ECC for VIM RAM */ + /* Errata VIM#28 Workaround: Disable Single Bit error correction */ + vimREG->ECCCTL = ( uint32 ) ( ( uint32 ) 0xAU << 0U ) + | ( uint32 ) ( ( uint32 ) 0x5U << 16U ); + + /* Initialize VIM table */ + { + uint32 i; + + for( i = 0U; i < VIM_CHANNELS; i++ ) + { + vimRAM->ISR[ i ] = s_vim_init[ i ]; + } + } + vimREG->FBVECADDR = ( uint32 ) &vimECCErrorHandler; + + /* set IRQ/FIQ priorities */ + vimREG->FIRQPR0 = ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR1 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR2 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR3 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + /* enable interrupts */ + vimREG->REQMASKSET0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 1U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 1U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET1 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET2 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET3 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + /* Set Capture event sources */ + vimREG->CAPEVT = ( ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ); + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_002 */ +/* DesignId : VIM_DesignId_002 */ +/* Requirements : CONQ_VIM_SR5 */ +/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler) + * @brief Map selected interrupt request to the selected channel + * + * @param[in] request: Interrupt request number 2..95 + * @param[in] channel: VIM Channel number 2..95 + * @param[in] handler: Address of the interrupt handler + * + * This function will map selected interrupt request to the selected channel. + * + */ +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ) +{ + uint32 i, j; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + i = channel >> 2U; /* Find the register to configure */ + j = channel - ( i << 2U ); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /*Mapping the required interrupt request to the required channel*/ + vimREG->CHANCTRL[ i ] &= ~( uint32 ) ( ( uint32 ) 0xFFU << j ); + vimREG->CHANCTRL[ i ] |= ( request << j ); + + /*Updating VIMRAM*/ + vimRAM->ISR[ channel + 1U ] = handler; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_003 */ +/* DesignId : VIM_DesignId_003 */ +/* Requirements : CONQ_VIM_SR3 */ +/** @fn void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype) + * @brief Enable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..95 + * @param[in] inttype: Interrupt type + * - SYS_IRQ: Selected channel will be enabled as IRQ + * - SYS_FIQ: Selected channel will be enabled as FIQ + * + * This function will enable interrupt for the selected channel. + * + */ +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( channel >= 96U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR3 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 96U ) ); + } + else + { + vimREG->FIRQPR3 |= ( ( uint32 ) 1U << ( channel - 96U ) ); + } + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR2 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 64U ) ); + } + else + { + vimREG->FIRQPR2 |= ( ( uint32 ) 1U << ( channel - 64U ) ); + } + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR1 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 32U ) ); + } + else + { + vimREG->FIRQPR1 |= ( ( uint32 ) 1U << ( channel - 32U ) ); + } + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR0 &= ~( uint32 ) ( ( uint32 ) 1U << channel ); + } + else + { + vimREG->FIRQPR0 |= ( ( uint32 ) 1U << channel ); + } + vimREG->REQMASKSET0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_004 */ +/* DesignId : VIM_DesignId_004 */ +/* Requirements : CONQ_VIM_SR5 */ +/** @fn void vimDisableInterrupt(uint32 channel) + * @brief Disable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..95 + * + * This function will disable interrupt for the selected channel. + * + */ +void vimDisableInterrupt( uint32 channel ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + if( channel >= 96U ) + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* SourceId : VIM_SourceId_005 */ +/* DesignId : VIM_DesignId_005 */ +/* Requirements : CONQ_VIM_SR7 */ +/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE; + config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE; + config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE; + config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE; + config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 0U ] = VIM_CHANCTRL0_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 1U ] = VIM_CHANCTRL1_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 2U ] = VIM_CHANCTRL2_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 3U ] = VIM_CHANCTRL3_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 4U ] = VIM_CHANCTRL4_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 5U ] = VIM_CHANCTRL5_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 6U ] = VIM_CHANCTRL6_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 7U ] = VIM_CHANCTRL7_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 8U ] = VIM_CHANCTRL8_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 9U ] = VIM_CHANCTRL9_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 10U ] = VIM_CHANCTRL10_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 11U ] = VIM_CHANCTRL11_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 12U ] = VIM_CHANCTRL12_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 13U ] = VIM_CHANCTRL13_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 14U ] = VIM_CHANCTRL14_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 15U ] = VIM_CHANCTRL15_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 16U ] = VIM_CHANCTRL16_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 17U ] = VIM_CHANCTRL17_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 18U ] = VIM_CHANCTRL18_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 19U ] = VIM_CHANCTRL19_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 20U ] = VIM_CHANCTRL20_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 21U ] = VIM_CHANCTRL21_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 22U ] = VIM_CHANCTRL22_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 23U ] = VIM_CHANCTRL23_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0; + config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1; + config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2; + config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3; + config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0; + config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1; + config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2; + config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3; + config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0; + config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1; + config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2; + config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3; + config_reg->CONFIG_CAPEVT = vimREG->CAPEVT; + config_reg->CONFIG_CHANCTRL[ 0U ] = vimREG->CHANCTRL[ 0U ]; + config_reg->CONFIG_CHANCTRL[ 1U ] = vimREG->CHANCTRL[ 1U ]; + config_reg->CONFIG_CHANCTRL[ 2U ] = vimREG->CHANCTRL[ 2U ]; + config_reg->CONFIG_CHANCTRL[ 3U ] = vimREG->CHANCTRL[ 3U ]; + config_reg->CONFIG_CHANCTRL[ 4U ] = vimREG->CHANCTRL[ 4U ]; + config_reg->CONFIG_CHANCTRL[ 5U ] = vimREG->CHANCTRL[ 5U ]; + config_reg->CONFIG_CHANCTRL[ 6U ] = vimREG->CHANCTRL[ 6U ]; + config_reg->CONFIG_CHANCTRL[ 7U ] = vimREG->CHANCTRL[ 7U ]; + config_reg->CONFIG_CHANCTRL[ 8U ] = vimREG->CHANCTRL[ 8U ]; + config_reg->CONFIG_CHANCTRL[ 9U ] = vimREG->CHANCTRL[ 9U ]; + config_reg->CONFIG_CHANCTRL[ 10U ] = vimREG->CHANCTRL[ 10U ]; + config_reg->CONFIG_CHANCTRL[ 11U ] = vimREG->CHANCTRL[ 11U ]; + config_reg->CONFIG_CHANCTRL[ 12U ] = vimREG->CHANCTRL[ 12U ]; + config_reg->CONFIG_CHANCTRL[ 13U ] = vimREG->CHANCTRL[ 13U ]; + config_reg->CONFIG_CHANCTRL[ 14U ] = vimREG->CHANCTRL[ 14U ]; + config_reg->CONFIG_CHANCTRL[ 15U ] = vimREG->CHANCTRL[ 15U ]; + config_reg->CONFIG_CHANCTRL[ 16U ] = vimREG->CHANCTRL[ 16U ]; + config_reg->CONFIG_CHANCTRL[ 17U ] = vimREG->CHANCTRL[ 17U ]; + config_reg->CONFIG_CHANCTRL[ 18U ] = vimREG->CHANCTRL[ 18U ]; + config_reg->CONFIG_CHANCTRL[ 19U ] = vimREG->CHANCTRL[ 19U ]; + config_reg->CONFIG_CHANCTRL[ 20U ] = vimREG->CHANCTRL[ 20U ]; + config_reg->CONFIG_CHANCTRL[ 21U ] = vimREG->CHANCTRL[ 21U ]; + config_reg->CONFIG_CHANCTRL[ 22U ] = vimREG->CHANCTRL[ 22U ]; + config_reg->CONFIG_CHANCTRL[ 23U ] = vimREG->CHANCTRL[ 23U ]; + } +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/* SourceId : VIM_SourceId_006 */ +/* DesignId : VIM_DesignId_006 */ +/* Requirements : CONQ_VIM_SR6 */ +void vimECCErrorHandler( void ) +{ + uint32 vec; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Identify the corrupted address */ + uint32 error_addr = vimREG->UERRADDR; + + /* Identify the channel number */ + uint32 error_channel = ( ( error_addr & 0x3FFU ) >> 2U ); + + /* Correct the corrupted location */ + vimRAM->ISR[ error_channel ] = s_vim_init[ error_channel ]; + + /* Clear Parity Error Flag */ + vimREG->ECCSTAT = 1U; + + /* Disable and enable the highest priority pending channel */ + if( vimREG->FIQINDEX != 0U ) + { + vec = vimREG->FIQINDEX - 1U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Read 32 bit volatile register" */ + vec = vimREG->IRQINDEX - 1U; + } + if( vec == 0U ) + { + vimREG->INTREQ0 = 1U; + vec = esmREG->IOFFHR - 1U; + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( esmREG, vec ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( esmREG, ( vec - 32U ) ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( esmREG, ( vec - 32U ) ); + } + else if( ( vec >= 128U ) && ( vec < 160U ) ) + { + esmREG->SR7[ 0U ] = ( uint32 ) 1U << ( vec - 128U ); + esmGroup2Notification( esmREG, ( vec - 96U ) ); + } + else + { + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + esmREG->SR4[ 1U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + } + else if( vec < 32U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << vec; + vimREG->REQMASKSET0 = ( uint32 ) 1U << vec; + } + else if( vec < 64U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( vec - 32U ); + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( vec - 32U ); + } + else if( vec < 96U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( vec - 64U ); + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( vec - 64U ); + } + else + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( vec - 96U ); + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( vec - 96U ); + } + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c new file mode 100644 index 00000000000..c12435362e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c @@ -0,0 +1,652 @@ +/** @file system.c + * @brief System Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "system.h" +#include "reg_pcr.h" +#include "pinmux.h" + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void systemInit(void) + * @brief Initializes System Driver + * + * This function initializes the System driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : SYSTEM_SourceId_001 */ +/* DesignId : SYSTEM_DesignId_001 */ +/* Requirements : CONQ_SYSTEM_SR3 */ +void setupPLL( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* Disable PLL1 and PLL2 */ + systemREG1->CSDISSET = 0x00000002U | 0x00000040U; + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x42U ) != 0x42U ) + { + /* Wait */ + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x301U; + + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /** - Setup pll control register 1: + * - Setup reset on oscillator slip + * - Setup bypass on pll slip + * - setup Pll output clock divider to max before Lock + * - Setup reset on oscillator fail + * - Setup reference clock divider + * - Setup Pll multiplier + */ + systemREG1->PLLCTL1 = ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) + | ( uint32 ) ( 0x9500U ); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider + * - Setup spreading amount + */ + systemREG1->PLLCTL2 = ( uint32 ) ( ( uint32 ) 255U << 22U ) + | ( uint32 ) ( ( uint32 ) 7U << 12U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U; + + /** @b Initialize @b Pll2: */ + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + systemREG2->PLLCTL3 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) + | ( uint32 ) ( 0x9500U ); + + /** - Enable PLL(s) to start up or Lock */ + systemREG1->CSDIS = 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000004U; +} + +/** @fn void trimLPO(void) + * @brief Initialize LPO trim values + * + * Load TRIM values from OTP if present else call customTrimLPO() function + * + */ +/* SourceId : SYSTEM_SourceId_002 */ +/* DesignId : SYSTEM_DesignId_002 */ +/* Requirements : CONQ_SYSTEM_SR6 */ +void trimLPO( void ) +{ + uint32 u32clocktestConfig; + /* Save user clocktest register configuration */ + u32clocktestConfig = systemREG1->CLKTEST; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO + * clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify + * what the maximum step is so there is no metric to use for the SW implementation - + * the routine can temporarily disable the LPOCLKMON range check so the sudden change + * will not cause a fault.*/ + /* Disable clock range detection*/ + + systemREG1->CLKTEST = ( systemREG1->CLKTEST | ( uint32 ) ( ( uint32 ) 0x1U << 24U ) ) + & ( uint32 ) ( ~( ( uint32 ) 0x1U << 25U ) ); + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) LPO_TRIM_VALUE ); + } + else + { + customTrimLPO(); + } + + /* Restore the user clocktest register value configuration */ + systemREG1->CLKTEST = u32clocktestConfig; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_003 */ +/* DesignId : SYSTEM_DesignId_003 */ +/* Requirements : CONQ_SYSTEM_SR5 */ +void setupFlash( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Setup flash read mode, address wait states and data wait states */ + flashWREG->FRDCNTL = 0x00000000U | ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U; + + /** - Setup flash access wait states for bank 7 */ + FSM_WR_ENA_HL = 0x5U; + EEPROM_CONFIG_HL = 0x00000002U | ( uint32 ) ( ( uint32 ) 9U << 16U ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Disable write access to flash state machine registers */ + FSM_WR_ENA_HL = 0x2U; + + /** - Setup flash bank power modes */ + flashWREG->FBPWRMODE = 0x00000000U + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) /* BANK 7 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) /* BANK 1 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ); /* BANK 0 */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_004 */ +/* DesignId : SYSTEM_DesignId_004 */ +/* Requirements : CONQ_SYSTEM_SR4 */ +void periphInit( void ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /** - Disable Peripherals before peripheral powerup*/ + systemREG1->CLKCNTL &= 0xFFFFFEFFU; + + /** - Release peripherals from reset and enable clocks to all peripherals */ + /** - Power-up all peripherals */ + pcrREG1->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + pcrREG2->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + pcrREG3->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + /** - Enable Peripherals */ + systemREG1->CLKCNTL |= 0x00000100U; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : CONQ_SYSTEM_SR7 */ +void mapClocks( void ) +{ + uint32 SYS_CSVSTAT, SYS_CSDIS; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /** @b Initialize @b Clock @b Tree: */ + /** - Setup system clock divider for HCLK */ + systemREG2->HCLKCNTL = 1U; + + /** - Disable / Enable clock domain */ + systemREG1->CDDIS = ( uint32 ) ( ( uint32 ) 0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* AVCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* AVCLK4 , 1 - OFF, 0 - ON + */ + + /* Always check the CSDIS register to make sure the clock source is turned on and + * check the CSVSTAT register to make sure the clock source is valid. Then write to + * GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + while( ( SYS_CSVSTAT & ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + != ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + { + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + } /* Wait */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and + * after wakeup */ + systemREG1->GHVSRC = ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + systemREG1->RCLKSRC = ( uint32 ) ( ( uint32 ) 1U << 24U ) /* RTI2 divider (Not + applicable for lock-step + device) */ + | ( uint32 ) ( ( uint32 ) SYS_VCLK + << 16U ) /* RTI2 clock source (Not applicable + for lock-step device) */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* RTI1 divider */ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); /* RTI1 clock source + */ + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + systemREG1->VCLKASRC = ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xF0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 24U ); + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xFFF0FFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ); + + systemREG2->CLK2CNTRL = ( systemREG2->CLK2CNTRL & 0xFFFFFFF0U ) + | ( uint32 ) ( ( uint32 ) 1U << 0U ); + + systemREG2->VCLKACON1 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed + * value */ + systemREG1->PLLCTL1 = ( systemREG1->PLLCTL1 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + /*SAFETYMCUSW 134 S MR:12.2 " Clear and write to the volatile register " */ + systemREG2->PLLCTL3 = ( systemREG2->PLLCTL3 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + + /* Enable/Disable Frequency modulation */ + systemREG1->PLLCTL2 |= 0x00000000U; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_006 */ +/* DesignId : SYSTEM_DesignId_006 */ +/* Requirements : CONQ_SYSTEM_SR2 */ +void systemInit( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /* Configure PLL control registers and enable PLLs. + * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock. + * This initialization sequence performs all the tasks that are not + * required to be done at full application speed while the PLL locks. + */ + setupPLL(); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* Enable clocks to peripherals and release peripheral reset */ + periphInit(); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* Configure device-level multiplexing and I/O multiplexing */ + muxInit(); + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /** - Set up flash address and data wait states based on the target CPU clock + * frequency The number of address and data wait states for the target CPU clock + * frequency are specified in the specific part's datasheet. + */ + setupFlash(); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */ + trimLPO(); + + /* + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF + * clock below 40MHz. Hence the init function needs to be called from the startup + * before the PLL is configured. + */ + emif_SDRAM_StartupInit(); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /** - Wait for PLLs to start up and map clock domains to desired clock sources */ + mapClocks(); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /** - set ECLK pins functional mode */ + systemREG1->SYSPC1 = 0U; + + /** - set ECLK pins default output value */ + systemREG1->SYSPC4 = 0U; + + /** - set ECLK pins output direction */ + systemREG1->SYSPC2 = 1U; + + /** - set ECLK pins open drain enable */ + systemREG1->SYSPC7 = 0U; + + /** - set ECLK pins pullup/pulldown enable */ + systemREG1->SYSPC8 = 0U; + + /** - set ECLK pins pullup/pulldown select */ + systemREG1->SYSPC9 = 1U; + + /** - Setup ECLK */ + systemREG1->ECPCNTL = ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_007 */ +/* DesignId : SYSTEM_DesignId_007 */ +/* Requirements : CONQ_SYSTEM_SR8 */ +void systemPowerDown( uint32 mode ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + /* Disable clock sources */ + systemREG1->CSDISSET = mode & 0x000000FFU; + + /* Disable clock domains */ + systemREG1->CDDIS = ( mode >> 8U ) & 0x00000FFFU; + + /* Idle CPU */ + /*SAFETYMCUSW 88 S MR:2.1 "Assembly in C needed" */ + _gotoCPUIdle_(); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_008 */ +/* DesignId : SYSTEM_DesignId_008 */ +/* Requirements : CONQ_SYSTEM_SR9 */ +resetSource_t getResetSource( void ) +{ + register resetSource_t rst_source; + + if( ( SYS_EXCEPTION & ( uint32 ) POWERON_RESET ) != 0U ) + { + /* power-on reset condition */ + rst_source = POWERON_RESET; + /* Clear all exception status Flag and proceed since it's power up */ + SYS_EXCEPTION = 0x0000FFFFU; + } + + else if( ( SYS_EXCEPTION & ( uint32 ) EXT_RESET ) != 0U ) + { + SYS_EXCEPTION = ( uint32 ) EXT_RESET; + /*** Check for other causes of EXT_RESET that would take precedence **/ + if( ( SYS_EXCEPTION & ( uint32 ) OSC_FAILURE_RESET ) != 0U ) + { + /* Reset caused due to oscillator failure. Add user code here to handle + * oscillator failure */ + rst_source = OSC_FAILURE_RESET; + SYS_EXCEPTION = ( uint32 ) OSC_FAILURE_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) WATCHDOG_RESET ) != 0U ) + { + /* Reset caused due watchdog violation */ + rst_source = WATCHDOG_RESET; + SYS_EXCEPTION = ( uint32 ) WATCHDOG_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) WATCHDOG2_RESET ) != 0U ) + { + /* Reset caused due watchdog violation */ + rst_source = WATCHDOG2_RESET; + SYS_EXCEPTION = ( uint32 ) WATCHDOG2_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) SW_RESET ) != 0U ) + { + /* Reset caused due to software reset. */ + rst_source = SW_RESET; + SYS_EXCEPTION = ( uint32 ) SW_RESET; + } + else + { + /* Reset caused due to External reset. */ + rst_source = EXT_RESET; + } + } + else if( ( SYS_EXCEPTION & ( uint32 ) DEBUG_RESET ) != 0U ) + { + /* Reset caused due Debug reset request */ + rst_source = DEBUG_RESET; + SYS_EXCEPTION = ( uint32 ) DEBUG_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) CPU0_RESET ) != 0U ) + { + /* Reset caused due to CPU0 reset. CPU reset can be caused by CPU self-test + * completion, or by toggling the "CPU RESET" bit of the CPU Reset Control + * Register. */ + rst_source = CPU0_RESET; + SYS_EXCEPTION = ( uint32 ) CPU0_RESET; + } + else + { + /* No_reset occured. */ + rst_source = NO_RESET; + } + return rst_source; +} + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_009 */ +/* DesignId : SYSTEM_DesignId_009 */ +/* Requirements : CONQ_SYSTEM_SR10 */ +/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + */ +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE; + config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE; + config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE; + config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE; + config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE; + config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE; + config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE; + config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE; + config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE; + config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE; + config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE; + config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE; + config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE; + config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2; + config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE; + config_reg->CONFIG_SYSPC10 = SYS_SYSPC10_CONFIGVALUE; + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1; + } + else + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2; + } + config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE; + config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE; + config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE; + config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE; + config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE; + config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE; + config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE; + config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2; + config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL1 = SYS2_ECPCNTL1_CONFIGVALUE; + config_reg->CONFIG_CLK2CNTRL = SYS2_CLK2CNTRL_CONFIGVALUE; + config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE; + config_reg->CONFIG_HCLKCNTL = SYS2_HCLKCNTL_CONFIGVALUE; + config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE; + config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE; + } + else + { + config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1; + config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2; + config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7; + config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8; + config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9; + config_reg->CONFIG_CSDIS = systemREG1->CSDIS; + config_reg->CONFIG_CDDIS = systemREG1->CDDIS; + config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC; + config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC; + config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC; + config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR; + config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR; + config_reg->CONFIG_MSINENA = systemREG1->MSINENA; + config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1; + config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2; + config_reg->CONFIG_SYSPC10 = systemREG1->SYSPC10; + config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL; + config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST; + config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1; + config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2; + config_reg->CONFIG_GPREG1 = systemREG1->GPREG1; + config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR; + config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1; + config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL; + config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL; + config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1; + config_reg->CONFIG_SYSECR = systemREG1->SYSECR; + config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3; + config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV; + config_reg->CONFIG_ECPCNTL1 = systemREG2->ECPCNTL1; + config_reg->CONFIG_CLK2CNTRL = systemREG2->CLK2CNTRL; + config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1; + config_reg->CONFIG_HCLKCNTL = systemREG2->HCLKCNTL; + config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP; + config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN; + } +} + +/** @fn customTrimLPO(void) + * @brief custom function to initilize LPO trim values + * + * This function initializes default LPO trim values if OTP value is 0XFFFF, + * user can also write their own code to handle this case . + * + */ +void customTrimLPO( void ) +{ + /* User can write logic to handle the case where LPO trim is set to 0xFFFFu */ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + /* Load default trimLPO value */ + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 16U ); + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt new file mode 100644 index 00000000000..2b34de673c9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt @@ -0,0 +1,214 @@ +cmake_minimum_required(VERSION 3.25) + +SET(CMAKE_CROSSCOMPILING "TRUE" CACHE STRING "Set Cross Compiling to true" FORCE) + +# Strip the default MacOSX flags that cause cross-compilations to fail. +SET(CMAKE_OSX_DEPLOYMENT_TARGET "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) +SET(CMAKE_OSX_SYSROOT "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) + +# Set the compiler before declaring the project for the test build +SET(CMAKE_C_COMPILER "arm-none-eabi-gcc") +SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") + +# Set the system processor and name before declaring the project +# Needs to be set here otherwise it will fail the test compilation +SET(CMAKE_SYSTEM_NAME "Generic" CACHE STRING "Target system is a generic ARM Processor") +SET(CMAKE_SYSTEM_PROCESSOR "armv7-r" CACHE STRING "Target system is an ARM7r Processor") + +# Set the ASM and C compilation flags +SET(CMAKE_ASM_FLAGS "-mcpu=cortex-r5 -mfpu=vfpv3-d16 -Og -g -ggdb -Wall -MMD -MP") +SET(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -specs=\"nosys.specs\" -specs=\"nano.specs\"") +SET(CMAKE_C_FLAGS "${CMAKE_ASM_FLAGS} -marm -mfloat-abi=hard") + +project(RM57_FreeRTOS C ASM) + +SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR} CACHE STRING "") + +# Increase the debug level of the CMAKE build +SET(CMAKE_VERBOSE_MAKEFILE ON) + +# Get the absolute path to the Demo Directory +SET(DEMO_DIR_REL "${CMAKE_CURRENT_SOURCE_DIR}") +GET_FILENAME_COMPONENT(DEMO_DIR ${DEMO_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Board Files +SET(BOARD_FILES_DIR_REL "${DEMO_DIR}/BoardFiles") +GET_FILENAME_COMPONENT(BOARD_FILES_DIR ${BOARD_FILES_DIR_REL} ABSOLUTE) + +SET(FREERTOS_CONFIG_FILE_DIRECTORY "${DEMO_DIR}/include" CACHE STRING "Config File Path") +SET(FREERTOS_PORT "GCC_ARM_CRX_MPU" CACHE STRING "FreeRTOS Port to Use") + +ADD_LIBRARY(freertos_config INTERFACE) +TARGET_INCLUDE_DIRECTORIES(freertos_config SYSTEM + INTERFACE + INCLUDE ${FREERTOS_CONFIG_FILE_DIRECTORY} +) + +# Clone the tag of the FreeRTOS-Kernel last tested with this project. +INCLUDE(FetchContent) + +FetchContent_Declare( + FreeRTOS-Kernel + GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git + # Last tested FreeRTOS-Kernel Commit + GIT_TAG e8289dfee6e00660b5ad028e9f931ffb76c95840 + SOURCE_DIR "${DEMO_DIR}/../../Source" + USES_TERMINAL_DOWNLOAD YES + USES_TERMINAL_UPDATE YES + BUILD_COMMAND "" +) + +# Uncomment the following lines to use Fetch-Content to clone Kernel. +# FetchContent_GetProperties(FreeRTOS-Kernel) +# if(NOT FreeRTOS-Kernel_POPULATED) +# FetchContent_Populate(FreeRTOS-Kernel) +# endif() + + +# Get the absolute path to the FreeRTOS-Kernel Directory +SET(FREERTOS_KERNEL_DIR_REL "${DEMO_DIR}/../../Source") +GET_FILENAME_COMPONENT(FREERTOS_KERNEL_DIR ${FREERTOS_KERNEL_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Port Directory +SET(PORT_DIR_REL "${FREERTOS_KERNEL_DIR}/portable/GCC/ARM_CRx_MPU") +GET_FILENAME_COMPONENT(PORT_DIR ${PORT_DIR_REL} ABSOLUTE) + +# Debug +MESSAGE("Project: ${PROJECT_NAME}") +MESSAGE("Demo Directory: ${DEMO_DIR}") +MESSAGE("FREERTOS_KERNEL_DIR: ${FREERTOS_KERNEL_DIR}") +MESSAGE("PORT_DIR: ${PORT_DIR}") + +INCLUDE_DIRECTORIES( + ${DEMO_DIR} + ${DEMO_DIR}/include + ${BOARD_FILES_DIR}/include + ${FREERTOS_KERNEL_DIR}/include + ${PORT_DIR} +) + +# Source files used for the FreeRTOS Demos +SET(FREERTOS_DEMO_SOURCES + ${DEMO_DIR}/source/main.c + ${DEMO_DIR}/source/irq_demo.c + ${DEMO_DIR}/source/mpu_demo.c + ${DEMO_DIR}/source/notification_demo.c + ${DEMO_DIR}/source/queue_demo.c + ${DEMO_DIR}/source/reg_test.c + ${DEMO_DIR}/source/reg_test_GCC.S +) + +# Source files used for the Board Support Package +ADD_LIBRARY(TI_BOARD_SUPPORT_PACKAGE OBJECT + ${BOARD_FILES_DIR}/source/adc.c + ${BOARD_FILES_DIR}/source/can.c + ${BOARD_FILES_DIR}/source/crc.c + ${BOARD_FILES_DIR}/source/dabort.S + ${BOARD_FILES_DIR}/source/dcc.c + ${BOARD_FILES_DIR}/source/ecap.c + ${BOARD_FILES_DIR}/source/emac.c + ${BOARD_FILES_DIR}/source/emif.c + ${BOARD_FILES_DIR}/source/epc.c + ${BOARD_FILES_DIR}/source/eqep.c + ${BOARD_FILES_DIR}/source/errata.c + ${BOARD_FILES_DIR}/source/errata_SSWF021_45.c + ${BOARD_FILES_DIR}/source/esm.c + ${BOARD_FILES_DIR}/source/etpwm.c + ${BOARD_FILES_DIR}/source/gio.c + ${BOARD_FILES_DIR}/source/het.c + ${BOARD_FILES_DIR}/source/i2c.c + ${BOARD_FILES_DIR}/source/lin.c + ${BOARD_FILES_DIR}/source/mdio.c + ${BOARD_FILES_DIR}/source/mibspi.c + ${BOARD_FILES_DIR}/source/nmpu.c + ${BOARD_FILES_DIR}/source/notification.c + ${BOARD_FILES_DIR}/source/phy_dp83640.c + ${BOARD_FILES_DIR}/source/phy_tlk111.c + ${BOARD_FILES_DIR}/source/pinmux.c + ${BOARD_FILES_DIR}/source/pom.c + ${BOARD_FILES_DIR}/source/sci.c + ${BOARD_FILES_DIR}/source/sys_core.S + ${BOARD_FILES_DIR}/source/sys_dma.c + ${BOARD_FILES_DIR}/source/sys_intvecs.S + ${BOARD_FILES_DIR}/source/sys_link.ld + ${BOARD_FILES_DIR}/source/sys_pcr.c + ${BOARD_FILES_DIR}/source/sys_phantom.c + ${BOARD_FILES_DIR}/source/sys_pmm.c + ${BOARD_FILES_DIR}/source/sys_pmu.S + ${BOARD_FILES_DIR}/source/sys_startup.c + ${BOARD_FILES_DIR}/source/system.c + ${BOARD_FILES_DIR}/source/sys_vim.c +) + +# FreeRTOS Kernel Files +ADD_LIBRARY(FREERTOS_KERNEL OBJECT + ${FREERTOS_KERNEL_DIR}/croutine.c + ${FREERTOS_KERNEL_DIR}/event_groups.c + ${FREERTOS_KERNEL_DIR}/list.c + ${FREERTOS_KERNEL_DIR}/queue.c + ${FREERTOS_KERNEL_DIR}/stream_buffer.c + ${FREERTOS_KERNEL_DIR}/tasks.c + ${FREERTOS_KERNEL_DIR}/timers.c + ${FREERTOS_KERNEL_DIR}/portable/Common/mpu_wrappers_v2.c +) + +ADD_LIBRARY(FREERTOS_PORT OBJECT + ${PORT_DIR}/mpu_wrappers_v2_asm.S + ${PORT_DIR}/portASM.S + ${PORT_DIR}/port.c +) + +# On Mac the C_LINK flags by default adds "-Wl,-search_paths_first -Wl,-headerpad_max_install_names" which +# Causes the executable that gets built to strip the symbols, so force set it to empty here. +SET(CMAKE_C_LINK_FLAGS "") +SET(CMAKE_EXE_LINKER_FLAGS "-Wl,-Map,\"RTOSDemo.map\" -Wl,-T\"${BOARD_FILES_DIR}/source/sys_link.ld\"") + +# Debug +MESSAGE("Demo Sources: ${FREERTOS_DEMO_SOURCES}") +MESSAGE("FreeRTOS Sources: ${FREERTOS_KERNEL_SOURCES}") +MESSAGE("Port Sources: ${FREERTOS_PORT_SOURCES}") + +# Create Full Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Full.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Register Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Register_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Queue Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Queue_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create MPU Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_MPU_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create IRQ Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_IRQ_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Notification Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Notification_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# These options are explained in the demo_tasks.h file +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Full.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x1F") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Register_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x1") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Queue_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x2") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_MPU_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x4") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_IRQ_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x8") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Notification_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x10") + +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Full.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Register_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Queue_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_MPU_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_IRQ_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Notification_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/README.md b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/README.md new file mode 100644 index 00000000000..5943aaae229 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/README.md @@ -0,0 +1,66 @@ +# Intro + +This directory contains a FreeRTOS project to build either a Blinky, or MPU demo +for the [RM57L843](https://www.ti.com/product/RM57L843). + +It is set up to blink LEDs on the Texas Instruments +[LAUNCHXL2-RM57L](https://www.ti.com/tool/LAUNCHXL2-RM57L) +and the [TMDXRM57LHDK](https://www.ti.com/tool/TMDXRM57LHDK) Development Kits. + +The code related to the Main Demo Files can be found in the +[source](./source) directory. +The code related to the board setup can be found in the +[BoardFiles](./BoardFiles) directory + +## Building + +This demo can either be loaded into Texas Instrument's +[Code Composer Studio (CCS)](https://www.ti.com/tool/CCSTUDIO). +or built using [CMake](https://cmake.org/). + +### CCS Build + +If building with CCS you need to install CCS, and then install the +[ARM Compiler Tools](https://software-dl.ti.com/ccs/esd/documents/ccs_compiler-installation-selection.html#compiler-installation) +as well as the Hercules Safety MCUs +[device support targets](https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_installation.html#device-support). + +After doing this, you can then open this directory in CCS, which will load up the +project. If everything installed correctly you should then be able to build and flash +to the board. + +Please be aware there is a filter on [CMakeLists.txt](./CMakeLists.txt) and the *build* +directory in the CCS project. + +This is to keep CCS from attempting to use resources generated with a CMAKE build. +If a directory other than "build" is selected when building using CMAKE, CCS will +attempt to use the the files in that directory, leading to build issues in CCS. +At time of writing this can be fixed by right clicking the folder in CCS +and selecting "Exclude from build". + +### CMake build + +When using CMake you will need to install a compatible version of the +[Arm GNU Toolchain](https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain) +and add this to your `PATH`. + +After doing this inspect the [demo_task.h](./include/demo_tasks.h#L30) file to see +what the possible demo configurations are, and select your desired demo config. + +The `all` options builds all combinations of these. +Example Usage: + +```sh +cmake -S . -B build; +make -C build all; +``` + +The generated binaries can then be found in the `build` directory. +These binaries can then be flashed to the board by using +[Uniflash](https://www.ti.com/tool/UNIFLASH) or by using CCS. + +## UART Output + +Rudimentary UART output is available by opening a Serial Connection +to the board. The settings for the UART are a BAUD rate of 115200, 1 stopbit, +and None Parity diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h new file mode 100644 index 00000000000..b57382ff863 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h @@ -0,0 +1,185 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Section of the file that can't be included in ASM Pre-processor */ +#ifndef FREERTOS_ASSEMBLY + #include + #ifndef configASSERT + +/* debug ASSERT The first option calls a function that prints to UART + * The second one loops for when using a debugger. */ +extern void vAssertCalled( const char * pcFileName, uint32_t ulLine ); + #define configASSERT( x ) \ + if( ( x ) == pdFALSE ) \ + { \ + vAssertCalled( __func__, __LINE__ ); \ + } + +extern void vMainSetupTimerInterrupt( void ); + #define configCLEAR_TICK_INTERRUPT() + #define configSETUP_TICK_INTERRUPT() vMainSetupTimerInterrupt() + #endif /* configASSERT */ +#endif /* FREERTOS_ASSEMBLY */ + +#ifndef FREERTOS_CONFIG_H + #define FREERTOS_CONFIG_H + + /*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + + /** Code Composer Studio will throw errors about NULL not being defined. + * as such wrap a define for NULL to 0 to remove the errors. + */ + #ifndef NULL + #define NULL 0x0 + #endif + + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1U + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0U + #define configENABLE_ACCESS_CONTROL_LIST 1U + + #define configENABLE_MPU 1U + #define configENABLE_FPU 1U + #define configUSE_MPU_WRAPPERS_V1 0U + #define configTOTAL_MPU_REGIONS 16UL + + #define configNUMBER_OF_CORES 1U + #define configUSE_PREEMPTION 1U + #define configUSE_IDLE_HOOK 1U + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + #define configUSE_TICK_HOOK 0 + #define configMAX_PRIORITIES ( 30UL ) + #define configQUEUE_REGISTRY_SIZE 10U + #define configSUPPORT_STATIC_ALLOCATION 1U + #define configSUPPORT_DYNAMIC_ALLOCATION 0U + + #define configCPU_CLOCK_HZ ( 110000000U ) + #define configTICK_RATE_HZ ( 1000U ) + #define configMINIMAL_STACK_SIZE ( 0x80 ) + #define configSYSTEM_CALL_STACK_SIZE configMINIMAL_STACK_SIZE + #define configTOTAL_HEAP_SIZE ( ( 80 * 512 ) ) + #define configMAX_TASK_NAME_LEN ( 0x20U ) + #define configUSE_TRACE_FACILITY 0U + #define configUSE_16_BIT_TICKS 0 + #define configIDLE_SHOULD_YIELD 0 + #define configUSE_CO_ROUTINES 0 + #define configUSE_MUTEXES 1U + #define configUSE_RECURSIVE_MUTEXES 1U + #define configUSE_EVENT_GROUPS 0U + #define configCHECK_FOR_STACK_OVERFLOW 0 + #define configUSE_QUEUE_SETS 1U + #define configUSE_COUNTING_SEMAPHORES 1U + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1U + #define configUSE_POSIX_ERRNO 0 + #define configUSE_TIME_SLICING 0 + #define configUSE_C_RUNTIME_TLS_SUPPORT 0 + #define configUSE_NEWLIB_REENTRANT 0 + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 + #define configUSE_MALLOC_FAILED_HOOK 0 + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + #define configAPPLICATION_ALLOCATED_HEAP 0 + #define configUSE_SB_COMPLETED_CALLBACK 0 + #define configRUN_MULTIPLE_PRIORITIES 0 + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING 0 + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + #define configUSE_MINI_LIST_ITEM 0 + #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 0x20UL + + /* Timer related defines. */ + #define configUSE_TIMERS 1 + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 6UL ) + #define configTIMER_QUEUE_LENGTH 20 + #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + #define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 + #define INCLUDE_xTimerPendFunctionCall 1 + + #define configUSE_TASK_NOTIFICATIONS 1 + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 3 + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. */ + + #define INCLUDE_vTaskPrioritySet 1 + #define INCLUDE_uxTaskPriorityGet 1 + #define INCLUDE_vTaskDelete 1 + #define INCLUDE_vTaskCleanUpResources 0 + #define INCLUDE_vTaskSuspend 1 + #define INCLUDE_xTaskDelayUntil 1 + #define INCLUDE_vTaskDelay 1 + #define INCLUDE_uxTaskGetStackHighWaterMark 1 + #define INCLUDE_xTaskGetSchedulerState 1 + #define INCLUDE_xTaskGetIdleTaskHandle 1 + #define INCLUDE_xSemaphoreGetMutexHolder 1 + #define INCLUDE_eTaskGetState 1 + #define INCLUDE_xTaskAbortDelay 1 + #define INCLUDE_xTaskGetHandle 1 + + /** Note: These value come from the Board Support Package. They are pulled directly + * from sys_vim.h, and reg_vim.h. These values correspond to hardware registers + * and keys exclusive to the board that this demo was written for. + */ + + /** @brief Address of MCU Register used to mark the end of an IRQ */ + #define configEOI_ADDRESS 0xFFFFFE70UL + + /** @brief Address of Real Time Interrupt (RTI) used for the system clock */ + #define configRTI_ADDRESS 0xFFFFFC88UL + + /** @brief Value used to clear a RTI Interrupt */ + #define configRTI_CLEAR_VALUE 0x1 + + /** @brief Address of Register used to trigger Software Interrupts (SWI) */ + #define configSWI_ADDRESS 0xFFFFFFB0UL + + /** @brief Key value that is written to the SWI Interrupt Register */ + #define configSWI_KEY_VAL 0x7500UL + + /** @brief Address of Register used to clear SWI Interrupts */ + #define configSWI_CLEAR_ADDRESS 0xFFFFFFF4UL + + /** @brief Value to write to clear a Software Interrupt (SWI) */ + #define configSWI_CLEAR_VAL 0x0 + + /** @brief Trigger a pending context swap from inside an ISR */ + #define portYIELD_FROM_ISR( x ) \ + if( x != pdFALSE ) \ + { \ + configPEND_YIELD_REG = configPEND_YIELD_KEY_VAL; \ + ( void ) configPEND_YIELD_REG; \ + } + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h new file mode 100644 index 00000000000..c6c430642ef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h @@ -0,0 +1,207 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEMO_TASKS_H +#define DEMO_TASKS_H + +/* ----------------------------------- Demo Option ----------------------------------- */ + +/** @brief Create Tasks that are written in assembly to test context swaps */ +#define REGISTER_DEMO 0x1 + +/** @brief Demo that uses timers, timer callbacks, and Queues */ +#define QUEUE_DEMO 0x2 + +/** @brief Demo that causes data aborts and clears them to show MPU usage */ +#define MPU_DEMO 0x4 + +/** @brief Demo that causes and unwinds a Nested IRQ */ +#define IRQ_DEMO 0x8 + +/** @brief Demo that uses the Task Notification APIs */ +#define NOTIFICATION_DEMO 0x10 + +/** @brief Build Register, Queue, MPU, IRQ, and Notification demos */ +#define FULL_DEMO ( REGISTER_DEMO | QUEUE_DEMO | MPU_DEMO | IRQ_DEMO | NOTIFICATION_DEMO ) + +/** @brief Bitfield used to select the Demo Tasks to build and run + * + * @note This project contains multiple demo and test tasks. A bitfield is used + * to select which demos and tests are built and run as part of the executable. + * More information about what these demos and tests do can be found in their + * corresponding files. + * + * Bit 1 Set: Include the Register Test Tasks + * + * Bit 2 Set: Include the Queue Send and Receive Test Tasks + * + * Bit 3 Set: Include the MPU Data Abort Test Tasks + * + * Bit 4 Set: Include the Nested IRQ Test Tasks + * + * Bit 5 Set: Include the Notification Test Tasks + * + */ +#ifndef mainDEMO_TYPE + #define mainDEMO_TYPE ( FULL_DEMO ) +#endif /* mainDEMO_TYPE */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "portmacro.h" +#include "mpu_wrappers.h" + +/* These tasks have been given pseudo random priority values for testing. + * Except for the queue send and receive task any of these tasks priorities + * should be able to be set to any valid priority without issue. */ + +/** @brief Priority at which the Privileged Register Task is created. */ +#define demoREG_PRIVILEGED_TASK_PRIORITY ( configMAX_PRIORITIES - 2UL ) + +/** @brief Priority at which the Unprivileged Register Task is created. */ +#define demoREG_UNPRIVILEGED_TASK_PRIORITY ( configMAX_PRIORITIES - 1UL ) + +/** @brief Priority at which the prvQueueSendTask is created. */ +#define demoQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL ) + +/** @brief Priority at which the prvQueueReceiveTask is created. */ +#define demoQUEUE_RECEIVE_TASK_PRIORITY ( demoQUEUE_SEND_TASK_PRIORITY + 1UL ) + +/** @brief Priority at which the MPU Read & Write Task is created. */ +#define demoMPU_READ_WRITE_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) + +/** @brief Priority at which the MPU Read Only Task is created. */ +#define demoMPU_READ_ONLY_TASK_PRIORITY ( tskIDLE_PRIORITY + 4UL ) + +/** @brief Priority at which the Nested IRQ Test Task is created. */ +#define demoIRQ_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 2UL ) + +/** @brief Priority at which the Notification Demo Task is created. */ +#define demoNOTIFICATION_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 1UL ) + +/* ------------------------------- Register Test Tasks ------------------------------- */ + +/* @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest1Implementation( void ); + +/** @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest2Implementation( void ); + +/** @brief Creates the Register Test Tasks implemented in reg_test_GCC.S + * @return pdPASS if all tasks are created, pdFAIL if they are not. + */ +BaseType_t xCreateRegisterTestTasks( void ); + +/* ----------------------------- Demo Tasks Declarations ----------------------------- */ + +/** + * @brief Create two tasks, a queue, and a timer, which are used to blink an LED. + * + * @return + * pdPASS if all objects are created. + * pdFAIL if any object cannot be created. + */ +BaseType_t xCreateQueueTasks( void ); + +/** + * @brief Create the MPU Tasks that trigger data aborts. + * + * @note The MPU demo creates 2 unprivileged tasks - One of which has Read Only + * access to a shared memory region while the other has Read Write access. The + * task with Read Only access then tries to write to the shared memory which + * results in a Memory fault. The fault handler examines that it is the fault + * generated by the task with Read Only access and if so, it recovers from the + * fault gracefully by moving the Program Counter to the next instruction to the + * one which generated the fault. If any other memory access violation occurs, + * the fault handler will get stuck in an infinite loop. + */ +BaseType_t xCreateMPUTasks( void ); + +/** @brief Create a task that waits for a response from a nested IRQ + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateIRQTestTask( void ); + +/** + * @brief Create tasks that send task notifications back and forth. + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateNotificationTestTask( void ); + +/** @brief Interrupt Handler used for Software Raised Interrupts */ +PRIVILEGED_FUNCTION void vIRQDemoHandler( void ); + +/* Registers required to configure the Real Time Interrupt (RTI). */ +#define portRTI_GCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC00UL ) ) +#define portRTI_TBCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC04UL ) ) +#define portRTI_COMPCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC0CUL ) ) +#define portRTI_CNT0_FRC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC10UL ) ) +#define portRTI_CNT0_UC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC14UL ) ) +#define portRTI_CNT0_CPUC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC18UL ) ) +#define portRTI_CNT0_COMP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC50UL ) ) +#define portRTI_CNT0_UDCP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC54UL ) ) +#define portRTI_SETINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC80UL ) ) +#define portRTI_CLEARINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC84UL ) ) +#define portRTI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFC88UL ) ) +#define portEND_OF_INTERRUPT_REG ( ( ( volatile uint32_t * ) configEOI_ADDRESS ) ) + + +/* Registers used by the Vectored Interrupt Manager */ +typedef void ( *ISRFunction_t )( void ); +#define portVIM_IRQ_INDEX ( *( ( volatile uint32_t * ) 0xFFFFFE00 ) ) +#define portVIM_IRQ_VEC_REG ( *( ( volatile ISRFunction_t * ) 0xFFFFFE70 ) ) + +#define portSSI_INT_REG_BASE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) + +#define portSSI_INT_REG_ONE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) +#define portSSI_ONE_KEY 0x7500UL + +#define portSSI_INT_REG_TWO ( ( ( volatile uint32_t * ) 0xFFFFFFB4 ) ) +#define portSSI_TWO_KEY 0x8400UL + +#define portSSI_INT_REG_THREE ( ( ( volatile uint32_t * ) 0xFFFFFFB8 ) ) +#define portSSI_THREE_KEY 0x9300UL + +#define portSSI_INT_REG_FOUR ( ( ( volatile uint32_t * ) 0xFFFFFFBC ) ) +#define portSSI_FOUR_KEY 0xA200UL + +#define portSSI_VEC_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF4 ) ) +#define portSSI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF8 ) ) + +/* --------------------------- Shared Function Deceleration --------------------------- */ + +/** @brief Function to toggle LEDs on the RM57-XL2 Launchpad + * @param ulLED Which LED to flicker + */ +void vToggleLED( uint32_t ulLED ); + +/* ----------------------------------------------------------------------------------- */ + +#endif /* DEMO_TASKS_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c new file mode 100644 index 00000000000..87ae969bdc3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c @@ -0,0 +1,291 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if( mainDEMO_TYPE & IRQ_DEMO ) + +/** @brief TCB used by the IRQ Test Task */ +PRIVILEGED_DATA static StaticTask_t xIRQTestTaskTCB; + +/** @brief MPU Region Aligned Stack used by the IRQ Test Task */ + +PRIVILEGED_DATA static StackType_t uxIRQTestTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4UL ) ) ); + + /** @brief Parameters that are passed into the IRQ test task solely for + * the purpose of ensuring parameters are passed into tasks correctly. */ + #define irqTASK_PARAMETER ( 0xFEEDBEEFUL ) + +/** @brief Statically allocated task handle for the IRQ Test task. */ +PRIVILEGED_DATA static TaskHandle_t xIRQTaskHandle; + +PRIVILEGED_DATA volatile static uint32_t ulIntNestTestVal; +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Unprivileged IRQ Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task raises Software Interrupts (SWI) in the form of IRQs using the + * Vectored Interrupt Manager (VIM) built into the RM57 by Texas Instrument (TI). + * It does this through use of the Software Interrupt Registers (SSIRs). + * More information about these can be found in the following document: + * https://www.ti.com/document-viewer/RM57L843/datasheet#system_information_and_electrical_specifications/SPNS1607150 + */ +static void prvIRQTestTask( void * pvParameters ) +{ + /* Ensure that the correct parameter was passed to the task */ + configASSERT( ( uint32_t ) pvParameters == irqTASK_PARAMETER ); + volatile uint32_t * xSoftwareInterruptRegister; + volatile TickType_t ulLoopCount; + volatile TickType_t xPreIRQTickCount; + for( ;; ) + { + /* Disable IRQs to raise a Software Based IRQ */ + // portDISABLE_INTERRUPTS(); + sci_print( "IRQ Test Task Starting IRQ Nesting Test!\r\n" ); + ulIntNestTestVal = 0xFFFFUL; + + /* Get the tick count before raising the SWI */ + xPreIRQTickCount = xTaskGetTickCount(); + + /* Trigger an IRQ by writing to the SSI Register with a data value */ + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + *xSoftwareInterruptRegister = portSSI_FOUR_KEY | 0x44UL; + + /* When using a debugger IRQs can be paused/delayed. + * This loop exists to keep the compiler from optimizing it out + * while also giving the debugger time to trigger the IRQ. */ + ulLoopCount = xPreIRQTickCount; + while( ( ulLoopCount + xPreIRQTickCount ) < ( xPreIRQTickCount + 0x20UL ) ) + { + if( 0xFFFFUL != ulIntNestTestVal ) + { + ulLoopCount++; + } + else + { + ulLoopCount = 0xFFFF0000UL; + } + } + + if( 0x4UL == ulIntNestTestVal ) + { + sci_print( "IRQ Test Task reported correct unwinding!\r\n" ); + vToggleLED( 0x1 ); + } + else + { + sci_print( "IRQ Test Task did not receive the correct nesting value!\r\n" ); + configASSERT( 0x0 ); + } + + sci_print( "IRQ Test Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 3150UL ) ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +void vIRQDemoHandler( void ) /* PRIVILEGED_FUNCTION */ +{ + sci_print( "\tSWI Based IRQ was raised!\r\n" ); + volatile uint32_t ulSSIRegisterValue; + volatile uint32_t ulSSIIntFlagValue; + volatile uint32_t * xSoftwareInterruptRegister; + /* The 4 different SWI Registers use a bitfield to mark that they where raised */ + { + /* Determine what channel raised the IRQ without clearing the interrupt */ + ulSSIIntFlagValue = portSSI_INTFLAG_REG; + if( 0x1UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x11UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #1 Raised with Data Value 0x11, clearing the " + "IRQs...\r\n" ); + /* Read to mark this IRQ as cleared */ + /* Mark the Nested Channel 1 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x1101UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 2 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x2202UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 3 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x3303UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 4 IRQ as cleared */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x4404UL == ulSSIIntFlagValue ); + + /* Should be no other IRQs raised, mask out the data */ + ulSSIIntFlagValue = ( portSSI_VEC_REG ) & 0XFFUL; + configASSERT( 0x0UL == ulSSIIntFlagValue ); + } + } + + else if( 0x2UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x22UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #2 triggering nested Channel #1 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + *xSoftwareInterruptRegister = portSSI_ONE_KEY | 0x11UL; + __asm volatile( "CPSIE I" ); + } + } + + else if( 0x4UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x33UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #3 triggering nested Channel #2 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + *xSoftwareInterruptRegister = portSSI_TWO_KEY | 0x22UL; + __asm volatile( "CPSIE I" ); + } + } + + else /* if( 0x8UL & ulSSIIntFlagValue ) */ + { + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + if( ulSSIRegisterValue & 0x44UL ) + { + ulIntNestTestVal = 0x1UL; + sci_print( "\t\tSWI Channel #4 triggering nested Channel #3 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + *xSoftwareInterruptRegister = portSSI_THREE_KEY | 0x33UL; + __asm volatile( "CPSIE I" ); + } + } + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateIRQTestTask( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + uint32_t ulSRAMBaseAddress = ( uint32_t ) __SRAM_segment_start__; + uint32_t ulSRAMRegionSize = ( uint32_t ) __SRAM_segment_end__ - ulSRAMBaseAddress; + uint32_t ulSRAMRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + BaseType_t xReturn = pdFAIL; + /* Create the register check tasks, as described at the top of this file. */ + TaskParameters_t xIRQTestTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvIRQTestTask, + /* The name of the task. */ + .pcName = "IRQTestTask", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE, + /* Parameter passed into the task. */ + .pvParameters = ( void * ) irqTASK_PARAMETER, + /* Priority of the task. */ + .uxPriority = ( configTIMER_TASK_PRIORITY + 0x2UL ) | portPRIVILEGE_BIT, + .puxStackBuffer = uxIRQTestTaskStack, + .pxTaskBuffer = &xIRQTestTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { ( void * ) ulSRAMBaseAddress, ulSRAMRegionSize, ulSRAMRegionAttr }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, + #endif + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, ulPeriphRegionSize, ulPeriphRegionAttr }, + } + }; + + /* Create the first register test task as a privileged task */ + xReturn = xTaskCreateRestrictedStatic( &( xIRQTestTaskParameters ), + &( xIRQTaskHandle ) ); + if( pdPASS == xReturn ) + { + sci_print( "Created the IRQ Test Task\r\n" ); + } + else + { + sci_print( "Failed to create the IRQ Test Task\r\n" ); + } + + ulIntNestTestVal = 0xFEEDBEEFUL; + return xReturn; +} +#endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/main.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/main.c new file mode 100644 index 00000000000..edb1396da4f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/main.c @@ -0,0 +1,475 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* ------------------------------------------------------------------------- */ +/** + * @file main.c + * @brief File implementing RM57L843 specific functions + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "portmacro.h" +#include "task.h" +#include "timers.h" + +/* Standard includes. */ +#include +#include + +/* HalCoGen includes. */ +#include "system.h" +#include "gio.h" +#include "het.h" +#include "reg_vim.h" +#include "sci.h" +#include "sys_vim.h" +#include "system.h" + +/* Demo Tasks include */ +#include "demo_tasks.h" + +/* ----------------------- Microcontroller Registers ----------------------- */ + +/** @brief Configure the hardware to start the scheduler timer. */ +PRIVILEGED_FUNCTION void vMainSetupTimerInterrupt( void ); + +/** @brief Set up necessary hardware registers */ +PRIVILEGED_FUNCTION static void prvSetupHardware( void ); + +/** @brief Landing point function for any failed configASSERT() check. + * @param pcFuncName The function that raised the assert. + * @param ulLine The line that the assert was called from. + * @note Unprivileged tasks shall pre-fetch abort if their assert fails. */ +FREERTOS_SYSTEM_CALL void vAssertCalled( const char * pcFileName, uint32_t ulLine ); + +PRIVILEGED_FUNCTION void vApplicationIRQHandler( void ); +/* --------------------- Static Task Memory Allocation --------------------- */ + +/** @brief Statically declared TCB Used by the Idle Task */ +PRIVILEGED_DATA static StaticTask_t xTimerTaskTCB; + +/** @brief Statically declared MPU aligned stack used by the timer task */ +PRIVILEGED_DATA static StackType_t uxTimerTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Statically declared TCB Used by the Idle Task */ +PRIVILEGED_DATA static StaticTask_t xIdleTaskTCB; + +/** @brief Statically declared MPU aligned stack used by the idle task */ +PRIVILEGED_DATA static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Simple variable to show how the idle tick hook can be used */ +PRIVILEGED_DATA static volatile TickType_t ulIdleTickHookCount = 0x0; + +extern PRIVILEGED_DATA volatile uint32_t ulPortYieldRequired; + +/* ------------------------------------------------------------------------- */ + +int main( void ) +{ + UBaseType_t xReturn = pdPASS; + ulIdleTickHookCount = 0x0; + prvSetupHardware(); + + sci_print( "\r\n---------------------------- Create FreeRTOS Tasks" + "----------------------------\r\n\r\n" ); + +#if( mainDEMO_TYPE & REGISTER_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Register test tasks\r\n" ); + xReturn = xCreateRegisterTestTasks(); + } + } +#endif /* ( mainDEMO_TYPE & REGISTER_DEMO ) */ + +#if( mainDEMO_TYPE & QUEUE_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Queue Demo Tasks\r\n" ); + xReturn = xCreateQueueTasks(); + } + } +#endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ + +#if( mainDEMO_TYPE & MPU_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the MPU Demo Tasks\r\n" ); + xReturn = xCreateMPUTasks(); + } + } +#endif + +#if( mainDEMO_TYPE & IRQ_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the IRQ Demo Tasks\r\n" ); + xReturn = xCreateIRQTestTask(); + } + } +#endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ + +#if( mainDEMO_TYPE & NOTIFICATION_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Notification Demo Tasks\r\n" ); + xReturn = xCreateNotificationTestTask(); + } + } +#endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ + + if( pdPASS == xReturn ) + { + sci_print( "\r\n--------------------------- Start of FreeRTOS Demos" + "---------------------------\r\n\r\n" ); + vTaskStartScheduler(); + } + else + { + sci_print( "Failed to create the Demo Tasks\r\n" ); + configASSERT( pdFAIL ); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was an error when creating the necessary FreeRTOS objects. */ + configASSERT( 0x0 ); + return 0; +} +/*---------------------------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + systemInit(); + gioInit(); + hetInit(); + sciInit(); + + /* Setup gioPORTB for when using the RM57 Launchpad */ + gioPORTB->DIR |= ( 0x01 << 6 ); /*configure GIOB[6] as output */ + gioPORTB->DIR |= ( 0x01 << 7 ); /*configure GIOB[7] as output */ + + /* Configure HET as master, pull functionality, and switch on. */ + hetREG1->GCR = 0x01000001; + hetREG1->PULDIS = 0x00000000; + + /* Configure pins connected to LEDs NHET[0,2,4,5,25,16,17,18,20,27,29,31] + * as output. */ + hetREG1->DIR = 0xAA178035; + hetREG1->DOUT = 0x0; + + /* Enable notifications for the SCI register */ + /* Use a BAUD rate of 115200, 1 stop bit, and None Parity */ + sciEnableNotification( scilinREG, SCI_RX_INT ); +} + +/*---------------------------------------------------------------------------*/ + +void vToggleLED( uint32_t ulLEDNum ) +{ + uint32_t ulLEDVal; + uint32_t ulGIOVal; + + if( 0x0 == ulLEDNum ) + { + /* RM57 TMDX Dev Kit LED1 use NHET[27], Launchpad LED2 uses GIOB[6] */ + ulLEDVal = 1UL << 27UL; + ulGIOVal = 1UL << 6UL; + } + else + { + /* RM57 TMDX Dev Kit LED2 use NHET[5], Launchpad LED3 uses GIOB[7] */ + ulLEDVal = 1UL << 5UL; + ulGIOVal = 1UL << 7UL; + } + + if( ( hetREG1->DOUT & ulLEDVal ) == 0 ) + { + hetREG1->DOUT |= ulLEDVal; + gioPORTB->DOUT |= ulGIOVal; + } + else + { + hetREG1->DOUT &= ~ulLEDVal; + gioPORTB->DOUT &= ~ulGIOVal; + } +} + +/*---------------------------------------------------------------------------*/ + +void vMainSetupTimerInterrupt( void ) +{ + /* Disable timer 0. */ + portRTI_GCTRL_REG &= 0xFFFFFFFEUL; + + /* Use the internal counter. */ + portRTI_TBCTRL_REG = 0x00000000U; + + /* COMPSEL0 will use the RTIFRC0 counter. */ + portRTI_COMPCTRL_REG = 0x00000000U; + + /* Initialise the counter and the prescale counter registers. */ + portRTI_CNT0_UC0_REG = 0x00000000U; + portRTI_CNT0_FRC0_REG = 0x00000000U; + + /* Set Prescalar for RTI clock. */ + portRTI_CNT0_CPUC0_REG = 0x00000001U; + portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + + /* Clear interrupts. */ + portRTI_INTFLAG_REG = 0x0007000FU; + portRTI_CLEARINTENA_REG = 0x00070F0FU; + + /* Enable the compare 0 interrupt. */ + portRTI_SETINTENA_REG = 0x00000001U; + portRTI_GCTRL_REG |= 0x00000001U; +} + +/*---------------------------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the + * idle task. It is essential that code added to this hook function never + * attempts to block in any way (for example, call xQueueReceive() with a + * block time specified, or call vTaskDelay()). If application tasks make + * use of the vTaskDelete() API function to delete themselves then it is + * also important that vApplicationIdleHook() is permitted to return to its + * calling function, because it is the responsibility of the idle task to + * clean up memory allocated by the kernel to any task that has since + * deleted itself. */ + ulIdleTickHookCount++; + if( ( TickType_t ) 0xF00000 == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xF0 0000 times!\r\n" ); + } + + else if( ( TickType_t ) 0xFFFFFFFF == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xFFFFFFFF times! " + "Setting it to 0x0!\r\n" ); + ulIdleTickHookCount = 0x0; + } +} + +/*---------------------------------------------------------------------------*/ + +void vAssertCalled( const char * pcFuncName, uint32_t ulLine ) /* FREERTOS_SYSTEM_CALL */ +{ + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + volatile const char * callingFunc = pcFuncName; + volatile uint32_t callingLine = ulLine; + + /* These variables can be inspected in a debugger. */ + if( callingFunc != ( char * ) callingLine ) + { + __asm volatile( "NOP" ); + } + + /* NOTE: Unprivileged tasks cannot enter critical sections on the ARM_CRx_MPU port. + * Meaning unprivileged tasks will cause a pre-fetch abort if they fail an assert. */ + taskENTER_CRITICAL(); + { + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + } + } + taskEXIT_CRITICAL(); +} + +/*---------------------------------------------------------------------------*/ + +/** @brief Default IRQ Handler used in the ARM_Cortex_RX ports. + * @note This Handler is directly tied to the Texas Instrument's Hercules + * Vectored Interrupt Manager (VIM). For more information about what + * this is and how it operates please refer to their document: + * https://www.ti.com/lit/pdf/spna218 + */ +void vApplicationIRQHandler( void ) +{ + /* Load the IRQ Channel Number and Function PTR from the VIM */ + volatile uint32_t ulIRQChannelIndex = portVIM_IRQ_INDEX; + volatile ISRFunction_t xIRQFncPtr = portVIM_IRQ_VEC_REG; + + /* Setup Bit Mask Clear Values */ + volatile uint32_t ulPendingIRQMask; + + volatile uint32_t ulPendISRReg0 = vimREG->REQMASKCLR0; + volatile uint32_t ulPendISRReg1 = vimREG->REQMASKCLR1; + volatile uint32_t ulPendISRReg2 = vimREG->REQMASKCLR2; + volatile uint32_t ulPendISRReg3 = vimREG->REQMASKCLR3; + + if( NULL == xIRQFncPtr ) + { + sci_print( "Received a NULL Function Pointer from the IRQ VIM\r\n" ); + configASSERT( pdFALSE ); + } + else + { + if( 0U != ulIRQChannelIndex ) + { + ulIRQChannelIndex--; + } + + if( ulIRQChannelIndex <= 31U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ulIRQChannelIndex; + vimREG->REQMASKCLR0 = ulPendingIRQMask; + vimREG->REQMASKCLR1 = 0xFFFFFFFFU; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 63U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 32U ); + vimREG->REQMASKCLR1 = ulPendingIRQMask; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 95U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 64U ); + vimREG->REQMASKCLR2 = ulPendingIRQMask; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 96U ); + vimREG->REQMASKCLR3 = ulPendingIRQMask; + } + } + /* + * Channel 0 is the ESM handler, treat this as a special case. + * phantomInterrupt() + * Keep interrupts disabled, this function does not return + */ + + if( 0UL == ulIRQChannelIndex ) + { + sci_print( "Phantom interrupt?\r\n" ); + configASSERT( pdFALSE ); + ( *xIRQFncPtr )(); + } + else if( ( phantomInterrupt == xIRQFncPtr ) ) + { + sci_print( "IRQ With no registered function in sys_vim.c has been raised\r\n" ); + configASSERT( pdFALSE ); + } + else + { + /* Information about the mapping of Interrupts in the VIM to their + * causes can be found in the RM57L843 Data Sheet: + * https://www.ti.com/document-viewer/RM57L843/datasheet#system_information_and_electrical_specifications/SPNS1607150 */ + /* An IRQ Raised by Channel Two of the VIM is RTI Compare Interrupt 0. */ + if( 2UL == ulIRQChannelIndex ) + { + /* This is the System Tick Timer Interrupt */ + ulPortYieldRequired = xTaskIncrementTick(); + /* Acknowledge the System Tick Timer Interrupt */ + portRTI_INTFLAG_REG = 0x1UL; + } + /* An IRQ Raised by Channel 21 of the VIM is a Software Interrupt (SSI). */ + else if( 21UL == ulIRQChannelIndex ) + { +#if( mainDEMO_TYPE & IRQ_DEMO ) + /* This is an interrupt raised by Software */ + vIRQDemoHandler(); +#else + sci_print( "SWI of unknown cause was raised!\r\n" ); + configASSERT( 0x0 ); +#endif + + /* Register read is needed to mark the end of the IRQ */ + volatile uint32_t ulEndOfIntRegVal = *portEND_OF_INTERRUPT_REG; + *portEND_OF_INTERRUPT_REG = ulEndOfIntRegVal; + } + else + { + sci_print( "Unmapped IRQ Channel Number Raised\r\n" ); + } + } + + vimREG->REQMASKSET0 = ulPendISRReg0; + vimREG->REQMASKSET1 = ulPendISRReg1; + vimREG->REQMASKSET2 = ulPendISRReg2; + vimREG->REQMASKSET3 = ulPendISRReg3; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/mpu_demo.c new file mode 100644 index 00000000000..bf70680322d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/mpu_demo.c @@ -0,0 +1,508 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "mpu_wrappers.h" + +/* Board Includes */ +#include "sci.h" + +/* Demo includes */ +#include "demo_tasks.h" + +/** @brief Size of the smallest valid MPU region, 32 bytes. */ +#define SHARED_MEMORY_SIZE 0x20UL + +#if( ( ( SHARED_MEMORY_SIZE % 2UL ) != 0UL ) || ( SHARED_MEMORY_SIZE < 32UL ) ) + #error SHARED_MEMORY_SIZE Must be a power of 2 that is larger than 32 +#endif /* ( ( SHARED_MEMORY_SIZE % 2UL ) != 0UL ) || ( SHARED_MEMORY_SIZE < 32UL ) */ +/** + * @brief Memory region used to track Memory Fault intentionally caused by the + * RO Access task. + * + * @note RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal + * memory. Illegal memory access causes Memory Fault and the fault handler + * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We + * recover gracefully from an expected fault by jumping to the next instruction. + * + */ +static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 }; + +#if( mainDEMO_TYPE & MPU_DEMO ) + +/* --------------------- Static Task Memory Allocation --------------------- */ + +/** @brief static variable that will be placed in privileged data */ +static volatile uint32_t ulStaticUnprotectedData = 0xFEED; + +/** @brief Memory regions shared between the two MPU Tasks. */ +static volatile uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory1[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory2[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory3[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory4[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + + #if( configTOTAL_MPU_REGIONS == 16 ) +static volatile uint8_t ucSharedMemory5[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory6[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory7[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +static volatile uint8_t ucSharedMemory8[ SHARED_MEMORY_SIZE ] + __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + #endif /* configTOTAL_MPU_REGIONS == 16 */ + +/* These tasks will use over 288 bytes as of time of writing. + * Minimal Cortex R MPU region sizes are 32, 64, 128, 256, and 512 bytes. Regions must + * aligned to their size. Due to this limitation these regions declare 512, or 0x200, + * bytes and align to that size. */ + +/** @brief Statically declared MPU aligned stack used by the Read Only task */ +static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Statically declared TCB Used by the Idle Task */ +PRIVILEGED_DATA static StaticTask_t xROAccessTaskTCB; + +/** @brief Statically declared MPU aligned stack used by the Read Write task */ +static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4U ) ) ); + +/** @brief Statically declared TCB Used by the Read Write Task */ +PRIVILEGED_DATA static StaticTask_t xRWAccessTaskTCB; + +/* ----------------------- Task Function Declaration ----------------------- */ + +/** @brief Task function used by the task with RO access to shared memory + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvROAccessTask( void * pvParameters ); + +/** @brief Task function used by the task with RW access to shared memory + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvRWAccessTask( void * pvParameters ); + +/* --------------------- MPU Demo Function Definitions --------------------- */ + +static void prvROAccessTask( void * pvParameters ) +{ + volatile uint8_t ucVal = 0x0; + + /* Unused parameters. */ + ( void ) pvParameters; + + for( ;; ) + { + /* This task performs the following sequence for all the shared memory + * regions: + * + * 1. Perform a read access to the shared memory. Since this task has + * RO access to the shared memory, the read operation is successful. + * + * 2. Set ucROTaskFaultTracker[ 0 ] to 1 before performing a write to + * the shared memory. Since this task has Read Only access to the + * shared memory, the write operation would result in a Memory Fault. + * Setting ucROTaskFaultTracker[ 0 ] to 1 tells the Memory Fault + * Handler that this is an expected fault. The handler recovers from + * the expected fault gracefully by jumping to the next instruction. + * + * 3. Perform a write to the shared memory resulting in a memory fault. + * + * 4. Ensure that the write access did generate MemFault and the fault + * handler did clear the ucROTaskFaultTracker[ 0 ]. + */ + /* Perform the above mentioned sequence on ucSharedMemory. */ + ucVal = ucSharedMemory[ 0 ]; + ucVal = 1U; + ucROTaskFaultTracker[ 0 ] = ucVal; + ucSharedMemory[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory1. */ + ucVal = ucSharedMemory1[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory1[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory2. */ + ucVal = ucSharedMemory2[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory2[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory3. */ + ucVal = ucSharedMemory3[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory3[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory4. */ + ucVal = ucSharedMemory4[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory4[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + #if( configTOTAL_MPU_REGIONS == 16 ) + { + /* Perform the above mentioned sequence on ucSharedMemory5. */ + ucVal = ucSharedMemory5[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory5[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory6. */ + ucVal = ucSharedMemory6[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory6[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory7. */ + ucVal = ucSharedMemory7[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory7[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + + /* Perform the above mentioned sequence on ucSharedMemory8. */ + ucVal = ucSharedMemory8[ 0 ]; + ucROTaskFaultTracker[ 0 ] = 1U; + ucSharedMemory8[ 0 ] = 0U; + ucVal = ucROTaskFaultTracker[ 0 ]; + configASSERT( ucVal == 0U ); + } + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + vToggleLED( 0x0 ); + sci_print( "Read Only MPU Task sleeping before next loop!\r\n\r\n" ); + + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 4004UL ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRWAccessTask( void * pvParameters ) +{ + volatile uint32_t ulVal = ( uint32_t ) pvParameters; + + for( ;; ) + { + /* This task has RW access to ucSharedMemory */ + ucSharedMemory[ 0 ] += 2U; + ucSharedMemory1[ 0 ]++; + ucSharedMemory2[ 0 ]++; + ucSharedMemory3[ 0 ]++; + ucSharedMemory4[ 0 ]++; + #if( configTOTAL_MPU_REGIONS == 16 ) + { + ucSharedMemory5[ 0 ]++; + ucSharedMemory6[ 0 ]++; + ucSharedMemory7[ 0 ]++; + ucSharedMemory8[ 0 ]++; + } + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + /* Set ucVal to 0 */ + ulVal = ( uint32_t ) ucSharedMemory[ 0 ]; + + /* Mark that we will trigger a data abort */ + ucROTaskFaultTracker[ 1 ] = 1U; + /* Attempt to set ulVal to ulStaticUnprotectedData. + * This will trigger a data abort as this task did not grant itself + * access to this variable. The Data abort handler at the bottom of this + * file will then see the raised value in the fault tracker, mark it low, + * and cause this task to resume from the following instruction. + */ + ulVal = ulStaticUnprotectedData; + + /* The value of ucVal should not have changed */ + configASSERT( ulVal != ucSharedMemory[ 0 ] ); + + vToggleLED( 0x1 ); + sci_print( "Read & Write MPU Task sleeping before next loop!\r\n\r\n" ); + + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 4321UL ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xCreateMPUTasks( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + BaseType_t xReturn = pdPASS; + + uint32_t ulReadMemoryPermissions = portMPU_REGION_PRIV_RW_USER_RO_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + uint32_t ulWriteMemoryPermissions = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + ulStaticUnprotectedData = 0xC3; + + TaskParameters_t + xROAccessTaskParameters = { .pvTaskCode = prvROAccessTask, + .pcName = "ROAccess", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = demoMPU_READ_ONLY_TASK_PRIORITY, + .puxStackBuffer = xROAccessTaskStack, + .pxTaskBuffer = &xROAccessTaskTCB, + .xRegions = { + /* Region 0 */ + { ( void * ) ucSharedMemory, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 1 */ + { ( void * ) ucSharedMemory1, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 2 */ + { ( void * ) ucSharedMemory2, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 3 */ + { ( void * ) ucSharedMemory3, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 4 */ + { ( void * ) ucSharedMemory4, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* Region 5 */ + { ( void * ) ucSharedMemory5, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 6 */ + { ( void * ) ucSharedMemory6, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 7 */ + { ( void * ) ucSharedMemory7, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + /* Region 8 */ + { ( void * ) ucSharedMemory8, + SHARED_MEMORY_SIZE, + ulReadMemoryPermissions }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Second to last Configurable Region */ + { ( void * ) ucROTaskFaultTracker, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + TaskParameters_t + xRWAccessTaskParameters = { .pvTaskCode = prvRWAccessTask, + .pcName = "RWAccess", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = ( void * ) ( 0xFF ), + .uxPriority = demoMPU_READ_WRITE_TASK_PRIORITY, + .puxStackBuffer = xRWAccessTaskStack, + .pxTaskBuffer = &xRWAccessTaskTCB, + .xRegions = { + /* First Configurable Region 0 */ + { ( void * ) ucSharedMemory, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 1 */ + { ( void * ) ucSharedMemory1, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 2 */ + { ( void * ) ucSharedMemory2, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 3 */ + { ( void * ) ucSharedMemory3, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 4 */ + { ( void * ) ucSharedMemory4, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 5 */ + { ( void * ) ucSharedMemory5, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 6 */ + { ( void * ) ucSharedMemory6, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 7 */ + { ( void * ) ucSharedMemory7, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* MPU Region 8 */ + { ( void * ) ucSharedMemory8, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Second to Last MPU Region */ + { ( void * ) ucROTaskFaultTracker, + SHARED_MEMORY_SIZE, + ulWriteMemoryPermissions }, + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + /* Create an unprivileged task with RO access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xROAccessTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + /* Create an unprivileged task with RW access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xRWAccessTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + sci_print( "Created the MPU Tasks\r\n" ); + } + else + { + sci_print( "Failed to create the Read Write MPU Task\r\n" ); + } + } + else + { + sci_print( "Failed to create the Read Write MPU Task\r\n" ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ +#endif /* ( mainDEMO_TYPE & MPU_DEMO ) */ + +PRIVILEGED_FUNCTION portDONT_DISCARD void vHandleMemoryFault( + uint32_t * pulFaultStackAddress ) +{ + volatile uint32_t ulPC; + volatile uint32_t ulOffendingInstruction; + + /* Is this an expected fault? */ + if( ( ucROTaskFaultTracker[ 0 ] == 1U ) || ( ucROTaskFaultTracker[ 1 ] == 1U ) ) + { + /* Read program counter. */ + ulPC = pulFaultStackAddress[ 6 ]; + + /* Read the offending instruction. */ + ulOffendingInstruction = *( uint32_t * ) ulPC; + + /** From ARM docs: + * Bits [31:28] are the conditional field + * Bits [27:24] are the operation code + * If bits [31:28] are 0b1111, the instruction can only be executed + * unconditionally If bits [31:28] are not 0b1111, the op code determines what the + * instruction is doing If bits [27:24] are 0b01x0 it is a load/store word If bits + * [27:24] are 0b0111 it is a media instruction + */ + + /* Extract bits[31:25] of the offending instruction. */ + ulOffendingInstruction = ulOffendingInstruction & 0xFF000000; + ulOffendingInstruction = ( ulOffendingInstruction >> 24 ); + + /* Check if we were called by a load/store word instruction */ + if( ( ulOffendingInstruction == 0x00E4 ) || ( ulOffendingInstruction == 0x00E5 ) + || ( ulOffendingInstruction == 0x00E6 ) ) + { + /* Increment the program counter to move to the next instruction */ + ulPC += 0x4; + } + else + { + sci_print( "Unexpected Instruction caused an MPU fault\r\n" ); + configASSERT( 0 ); + } + + /* Save the new program counter on the stack. */ + pulFaultStackAddress[ 6 ] = ulPC; + + /* Mark the fault as handled. */ + if( ucROTaskFaultTracker[ 0 ] == 1U ) + { + ucROTaskFaultTracker[ 0 ] = 0U; + sci_print( "Cleared an MPU Read Only Task Fault\r\n" ); + } + else if( ucROTaskFaultTracker[ 1 ] == 1U ) + { + sci_print( "Cleared an MPU Write Only Task Fault\r\n" ); + ucROTaskFaultTracker[ 1 ] = 0U; + } + else + { + sci_print( "TaskFaultTracker value changed, Are IRQs disabled? \r\n" ); + /* Sit in a loop forever */ + configASSERT( 0 ); + } + } + else + { + sci_print( "Unexpected MPU Fault\r\n" ); + /* This is an unexpected fault - loop forever. */ + configASSERT( 0 ); + } +} + +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c new file mode 100644 index 00000000000..b4fd35c983e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c @@ -0,0 +1,242 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if( mainDEMO_TYPE & NOTIFICATION_DEMO ) + + /** @brief Parameters that are passed into the notification test task solely + * for the purpose of ensuring parameters are passed into tasks correctly. */ + #define notificationTASK_PARAMETER ( 0xFEEDBEEFUL ) + + /** @brief Value sent back and forth between the tasks */ + #define notificationTEST_VALUE 0x1234UL + +/** @brief TCB used by the Notification Test Task */ +PRIVILEGED_DATA static StaticTask_t xNotificationTestTaskTCB; + +/** @brief MPU Region Aligned Stack used by the Notification Test Task */ +static StackType_t uxNotificationTestTaskStack[ configMINIMAL_STACK_SIZE ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x4UL ) ) ); + +/** @brief Statically allocated task handle for the Notification Test task. */ +static TaskHandle_t xNotificationTaskOneHandle; + +/* ----------------------------------------------------------------------------------- */ + +static void prvNotifyCheck( BaseType_t ulRetVal ) +{ + if( pdPASS == ulRetVal ) + { + sci_print( "Notification API Returned a passing value!\r\n" ); + } + else + { + sci_print( "Notification API did not return pdPASS.\r\n" ); + configASSERT( ulRetVal ); + } +} + +/** @brief Entry point for the Unprivileged Notification Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task sends itself and another task notifications using the + * cross-task notification APIs. + */ +static void prvNotificationTestTask( void * pvParameters ) +{ + BaseType_t xReturned; + UBaseType_t ulNotificationValue; + + /* Ensure that the correct parameter was passed to the task */ + configASSERT( ( uint32_t ) pvParameters == notificationTEST_VALUE ); + for( ;; ) + { + /* Clear the notification value each loop */ + ulNotificationValue = 0x0UL; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0x0UL, 0x0UL, &ulNotificationValue, 0x0UL ); + configASSERT( pdFAIL == xReturned ); + configASSERT( 0x0UL == ulNotificationValue ); + + /* Tell the task to notify itself twice */ + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + /* Perform a non-blocking notification read, should see two "gives" */ + ulNotificationValue = ulTaskNotifyTake( pdTRUE, 0x0 ); + + /* Two notifications have been sent to this task by itself */ + configASSERT( 0x2UL == ulNotificationValue ); + sci_print( "Notification Task correctly sent itself two notifications!\r\n" ); + + /* Now make the task send itself a notification with a value */ + xReturned = xTaskNotify( xTaskGetCurrentTaskHandle(), + notificationTEST_VALUE, + eSetValueWithOverwrite ); + prvNotifyCheck( xReturned ); + + /* Clear ulNotificationValue before using it */ + ulNotificationValue = 0x0UL; + + /* Receive the value sent using xTaskNotify */ + xReturned = xTaskNotifyWait( 0, + ( uint32_t ) 0xFFFFFFFFUL, + &ulNotificationValue, + ( TickType_t ) 0x50UL ); + prvNotifyCheck( xReturned ); + + if( notificationTEST_VALUE == ulNotificationValue ) + { + sci_print( "Notification Task got the expected value!\r\n" ); + } + else + { + sci_print( "Notification Task did NOT get the expected value!\r\n" ); + configASSERT( 0x0UL ); + } + + /* Reset the variable before using it */ + ulNotificationValue = 0x0UL; + + /* There should be no value to receive this time */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, ( TickType_t ) 0x0UL ); + if( ( pdPASS == xReturned ) || ( 0x0 != ulNotificationValue ) ) + { + sci_print( "Notification Task received a value when there should have been " + "none" ); + configASSERT( 0x0UL ); + } + + xTaskNotify( xTaskGetCurrentTaskHandle(), + ulNotificationValue, + eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* First time a notification was pending. */ + configASSERT( xReturned == pdTRUE ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* Second time the notification was already clear. */ + configASSERT( xReturned == pdFALSE ); + + sci_print( "Notification Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times */ + vTaskDelay( pdMS_TO_TICKS( 2750UL ) ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateNotificationTestTask( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + BaseType_t xReturn = pdFAIL; + /* Create the register check tasks, as described at the top of this file. */ + TaskParameters_t xNotificationTestTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvNotificationTestTask, + /* The name of the task. */ + .pcName = "NotificationTestTask", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE, + /* Parameter passed into the task. */ + .pvParameters = ( void * ) notificationTEST_VALUE, + /* Priority of the task. */ + .uxPriority = ( demoNOTIFICATION_TASK_PRIORITY ), + .puxStackBuffer = uxNotificationTestTaskStack, + .pxTaskBuffer = &xNotificationTestTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { ( void * ) &xNotificationTaskOneHandle, + ( uint32_t ) sizeof( TaskHandle_t ), + portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | + portMPU_REGION_NORMAL_OIWTNOWA_SHARED }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, + #endif + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, ulPeriphRegionSize, ulPeriphRegionAttr }, + } + }; + + /* Create the notification test task */ + xReturn = xTaskCreateRestrictedStatic( &( xNotificationTestTaskParameters ), + &( xNotificationTaskOneHandle ) ); + if( pdPASS == xReturn ) + { + sci_print( "Created the Notification Test Task\r\n" ); + } + else + { + sci_print( "Failed to create the Notification Test Task\r\n" ); + } + + return xReturn; +} +#endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c new file mode 100644 index 00000000000..7b73606df80 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c @@ -0,0 +1,448 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file queue_demo.c + * @brief Use the Queue APIs to send data from a sender task to a receiver task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" + +/* Board Support Package Includes */ +#include "sci.h" +#include "reg_system.h" + +/* Demo Specific Includes */ +#include "demo_tasks.h" + +#if( mainDEMO_TYPE & QUEUE_DEMO ) + + /* ------------------------------ Demo Task Configs ------------------------------ */ + + /** @brief The rate at which data is sent to the queue from the send task. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) + + /** @brief The rate at which data is sent to the queue from the timer. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + + /** @brief The number of items the queue can hold at once. */ + #define queueQUEUE_LENGTH ( 2 ) + + /** @brief Value sent from the send task to the receive task */ + #define queueVALUE_SENT_FROM_TASK ( 0x1234UL ) + + /** @brief Value sent from the timer to the receive task */ + #define queueVALUE_SENT_FROM_TIMER ( 0x4321UL ) + +/* --------------------- Task Function Declaration --------------------- */ + +/** @brief Function run by the task that receives data from the queue. + * @note + * The queue receive task is implemented by the prvQueueReceiveTask() + * function in this file. prvQueueReceiveTask() waits for data to arrive on + * the queue. When data is received, the task checks the value of the data, + * then outputs a message to indicate if the data came from the queue send + * task or the queue send software timer. */ +static void prvQueueReceiveTask( void * pvParameters ); + +/** @brief Function run by the task that sends data to a queue. + * @note + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It uses vTaskDelayUntil() to create a periodic task that + * sends queueVALUE_SENT_FROM_TASK to the queue every 200 milliseconds. */ +static void prvQueueSendTask( void * pvParameters ); + +/** @brief The callback function executed when the timer expires. + * @note + * The timer is an auto-reload timer with a period of two seconds. Its + * callback function sends the value queueVALUE_SENT_FROM_TIMER to the + * queue. The callback function is implemented by prvQueueSendTimerCallback(). + */ +static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); + +/*-------------------- Static Task Memory Allocation ------------------- */ + +/** @brief Statically allocated, and MPU aligned, Queue object */ +static StaticQueue_t xStaticQueue __attribute__( ( aligned( 0x80 ) ) ); + +/** @brief Statically allocated, and MPU aligned, Storage for the Queue */ +static uint8_t xQueueStorage[ 0x20 ] __attribute__( ( aligned( 0x80 ) ) ); + +/** @brief Statically allocated, and MPU aligned, QueueHandle */ +static QueueHandle_t xQueue __attribute__( ( aligned( 0x20 ) ) ); + +/* Each task needs to know the other tasks handle so they can send signals to + * each other. The handle is obtained from the task's name. */ + +/** @brief Task name for the queue send task. */ +static const char * pcSendTaskName = "SendTaskName"; + +/** @brief Task name for the queue receive task. */ +static const char * pcReceiveTaskName = "ReceiveTaskName"; + +/** @brief Static MPU aligned stack used by the Queue Send Task */ +static StackType_t xQueueSendTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/** @brief Static TCB Used by the Queue Send Task */ +PRIVILEGED_DATA static StaticTask_t xQueueSendTaskTCB; + +/** @brief Static MPU aligned stack used by the Queue Receive Task */ +static StackType_t xQueueReceiveTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/** @brief Static TCB Used by the Queue Receive Task */ +PRIVILEGED_DATA static StaticTask_t xQueueReceiveTaskTCB; + +/** @brief A software timer that is started from the tick hook. */ +static TimerHandle_t xTimer = NULL; + +/** @brief Statically allocated timer object. */ +static StaticTimer_t xStaticTimer; + +/** @brief Statically allocated task handle for the queue receive task. */ +static TaskHandle_t xReceiveTaskHandle; + +/** @brief Statically allocated task handle for the queue send task. */ +static TaskHandle_t xSendTaskHandle; + +/* ------------------------------------------------------------------------------------ */ + +BaseType_t prvCreateQueueTasks( void ) +{ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __peripherals_start__[]; + extern uint32_t __peripherals_end__[]; + + uint32_t ulPeriphRegionStart = ( uint32_t ) __peripherals_start__; + uint32_t ulPeriphRegionSize = ( uint32_t ) __peripherals_end__ - ulPeriphRegionStart; + uint32_t ulPeriphRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_DEVICE_SHAREABLE; + + BaseType_t xReturn = pdPASS; + + uint32_t ulRegionAttr = portMPU_REGION_PRIV_RW_USER_RW_NOEXEC + | portMPU_REGION_NORMAL_OIWTNOWA_SHARED; + + /* Start the two tasks as described in the comments at the top of this file. */ + TaskParameters_t + xQueueReceiveTaskParameters = { .pvTaskCode = prvQueueReceiveTask, + .pcName = pcReceiveTaskName, + .usStackDepth = configMINIMAL_STACK_SIZE / 2U, + .pvParameters = NULL, + .uxPriority = demoQUEUE_RECEIVE_TASK_PRIORITY, + .puxStackBuffer = xQueueReceiveTaskStack, + .pxTaskBuffer = &xQueueReceiveTaskTCB, + .xRegions = { + /* First Configurable Region 0 */ + { ( void * ) &xStaticQueue, + ( uint32_t ) sizeof( StaticQueue_t ), + ulRegionAttr }, + /* Region 1 */ + { ( void * ) &xQueueStorage, + ( uint32_t ) sizeof( xQueueStorage ), + ulRegionAttr }, + /* Region 2 */ + { ( void * ) &xQueue, + ( uint32_t ) sizeof( QueueHandle_t ), + ulRegionAttr }, + /* Region 3 */ + { 0, 0, 0 }, + /* Region 4 */ + { 0, 0, 0 }, + /* Region 5 */ + { 0, 0, 0 }, + /* Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* Region 7 */ + { 0, 0, 0 }, + /* Region 8 */ + { 0, 0, 0 }, + /* Region 9 */ + { 0, 0, 0 }, + /* Region 10 */ + { 0, 0, 0 }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + TaskParameters_t + xQueueSendTaskParameters = { .pvTaskCode = prvQueueSendTask, + .pcName = pcSendTaskName, + .usStackDepth = configMINIMAL_STACK_SIZE / 2U, + .pvParameters = NULL, + .uxPriority = demoQUEUE_SEND_TASK_PRIORITY, + .puxStackBuffer = xQueueSendTaskStack, + .pxTaskBuffer = &xQueueSendTaskTCB, + .xRegions = { + /* First Configurable Region 0 */ + { ( void * ) &xStaticQueue, + ( uint32_t ) sizeof( StaticQueue_t ), + ulRegionAttr }, + /* Region 1 */ + { ( void * ) &xQueueStorage, + ( uint32_t ) sizeof( xQueueStorage ), + ulRegionAttr }, + /* Region 2 */ + { ( void * ) &xQueue, + ( uint32_t ) sizeof( QueueHandle_t ), + ulRegionAttr }, + /* Region 3 */ + { 0, 0, 0 }, + /* Region 4 */ + { 0, 0, 5 }, + /* Region 5 */ + { 0, 0, 0 }, + /* Region 6 */ + { 0, 0, 0 }, + #if( configTOTAL_MPU_REGIONS == 16 ) + /* Region 7 */ + { 0, 0, 0 }, + /* Region 8 */ + { 0, 0, 0 }, + /* Region 9 */ + { 0, 0, 0 }, + /* Region 10 */ + { 0, 0, 0 }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + /* Last Configurable MPU Region */ + { ( void * ) ulPeriphRegionStart, + ulPeriphRegionSize, + ulPeriphRegionAttr }, + } }; + + /* Create an unprivileged task with RO access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xQueueReceiveTaskParameters ), + &( xReceiveTaskHandle ) ); + + if( pdPASS == xReturn ) + { + sci_print( "Created the Queue Receive Task\r\n" ); + /* Create an unprivileged task with RW access to ucSharedMemory. */ + xReturn = xTaskCreateRestrictedStatic( &( xQueueSendTaskParameters ), + &xSendTaskHandle ); + if( pdPASS == xReturn ) + { + sci_print( "Created the Queue Send Task\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + return xReturn; +} + +BaseType_t xCreateQueueTasks( void ) +{ + BaseType_t xReturn = pdPASS; + + /* The Receive Task MUST be a higher priority than the send task. */ + configASSERT( demoQUEUE_RECEIVE_TASK_PRIORITY > demoQUEUE_SEND_TASK_PRIORITY ); + + /* Create the queue used by the queue tasks . */ + xQueue = xQueueCreateStatic( queueQUEUE_LENGTH, + sizeof( uint32_t ), + xQueueStorage, + &xStaticQueue ); + + if( xQueue != NULL ) + { + sci_print( "Created the Queue for the tasks\r\n" ); + + /** @brief The debugging text name for the timer */ + const char * pcTimerName = "Timer"; + /** @brief Mark that this is an auto-reload timer. */ + const BaseType_t xAutoReload = ( BaseType_t ) pdTRUE; + /** @brief Timer ID that is not used in this demo. */ + void * const pvTimerID = NULL; + /** @brief Callback function for the timer */ + TimerCallbackFunction_t pxCallbackFunction = prvQueueSendTimerCallback; + + /* Create a statically allocated timer */ + xTimer = xTimerCreateStatic( pcTimerName, + ( const TickType_t ) queueTIMER_SEND_FREQUENCY_MS, + xAutoReload, + pvTimerID, + pxCallbackFunction, + &( xStaticTimer ) ); + } + else + { + sci_print( "Failed to create the Queue for the tasks\r\n" ); + xReturn = pdFAIL; + } + + if( NULL != xTimer ) + { + sci_print( "Created the Queue Timer\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Timer\r\n" ); + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + xReturn = prvCreateQueueTasks(); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + /* Use an Access Control List to allow the tasks to use this queue */ + vGrantAccessToQueue( xReceiveTaskHandle, xQueue ); + vGrantAccessToQueue( xSendTaskHandle, xQueue ); + + /* The scheduler has not started so use a block time of 0. */ + xReturn = xTimerStart( xTimer, 0 ); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + sci_print( "Started the Timer\r\n" ); + } + else + { + sci_print( "Failed to start the Queue Timer\r\n" ); + } + + return xReturn; +} + +/*-----------------------------------------------------------------------*/ + +static void prvQueueSendTask( void * pvParameters ) +{ + TickType_t xNextWakeTime; + const TickType_t xBlockTime = queueTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TASK; + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Move this task to the blocked state for xBlockTime milliseconds. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in + * ticks. While in the Blocked state this task will not consume any + * CPU time. */ + xTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock + * and write to the console. 0 is used as the block time so the send + * operation will not block. It shouldn't need to block as the queue + * should always have at least one space at this point in the code. + */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} + +/*-----------------------------------------------------------------------*/ + +static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) +{ + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TIMER; + + /* This is the software timer callback function. The software timer has + * a period of two seconds. This callback function will execute if the + * timer expires, which will happen every two seconds. */ + + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; + + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon + * task, so must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); +} + +/*-----------------------------------------------------------------------*/ + +static void prvQueueReceiveTask( void * pvParameters ) +{ + uint32_t ulReceivedValue = 0; + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, + * but is it an expected value? */ + if( ulReceivedValue == queueVALUE_SENT_FROM_TASK ) + { + vToggleLED( 0x0 ); + } + else if( ulReceivedValue == queueVALUE_SENT_FROM_TIMER ) + { + vToggleLED( 0x1 ); + } + else + { + /* Invalid value received. Force an assert. */ + configASSERT( ulReceivedValue == !ulReceivedValue ); + } + } +} +/* --------------------------------------------------------------------- */ + +#endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c new file mode 100644 index 00000000000..e662b54ff7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c @@ -0,0 +1,246 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +/* ----------------------------------------------------------------------------------- */ + +/** @brief TCB used by Register Test Task One */ +PRIVILEGED_DATA static StaticTask_t xRegTestOneTaskTCB; + +/** @brief Small MPU Region Aligned Stack used by Register Test Task One */ +PRIVILEGED_DATA static StackType_t uxRegTestOneTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/** @brief TCB used by Register Test Two Task */ +PRIVILEGED_DATA static StaticTask_t xRegTestTwoTaskTCB; + +/** @brief Small MPU Region Aligned Stack used by Register Test Task Two */ +static StackType_t uxRegTestTwoTaskStack[ configMINIMAL_STACK_SIZE / 2U ] + __attribute__( ( aligned( configMINIMAL_STACK_SIZE * 0x2U ) ) ); + +/* Parameters that are passed into the register check tasks solely for the + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Array to track the number of loops the register test tasks have run. + * + * @note Smallest valid MPU region size for Armv7-R is 32 bytes. + * Register Test One will use loopCount[0]; + * Register Test Two Will use loopCount[1]; + */ +uint32_t loopCounter[ 0x8 ] __attribute__( ( aligned( 0x20 ) ) ); + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Privileged Register Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry1( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + else + { + /** The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Unprivileged Register Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry2( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + else + { + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateRegisterTestTasks( void ) +{ + BaseType_t xReturn = pdFAIL; + /* Create the register check tasks, as described at the top of this file. */ + TaskParameters_t xRegTestOneTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvRegTestTaskEntry1, + /* The name of the task. */ + .pcName = "RegTestOne", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE / 0x2, + /* Parameter passed into the task. */ + .pvParameters = mainREG_TEST_TASK_1_PARAMETER, + /* Priority of the task. */ + .uxPriority = demoREG_PRIVILEGED_TASK_PRIORITY | portPRIVILEGE_BIT, + .puxStackBuffer = uxRegTestOneTaskStack, + .pxTaskBuffer = &xRegTestOneTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { loopCounter, + 0x20, + portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_NORMAL_OIWTNOWA_SHARED, + }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, +#if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, +#endif + /* Final MPU Region */ + { 0, 0, 0 }, + } + }; + + TaskParameters_t xRegTestTwoTaskParameters = { + /* The function that implements the task. */ + .pvTaskCode = prvRegTestTaskEntry2, + /* The name of the task. */ + .pcName = "RegTestTwo", + /* Size of stack to allocate for the task - in words not bytes!. */ + .usStackDepth = configMINIMAL_STACK_SIZE / 0x2, + /* Parameter passed into the task. */ + .pvParameters = mainREG_TEST_TASK_2_PARAMETER, + /* Priority of the task. */ + .uxPriority = demoREG_UNPRIVILEGED_TASK_PRIORITY, + .puxStackBuffer = uxRegTestTwoTaskStack, + .pxTaskBuffer = &xRegTestTwoTaskTCB, + .xRegions = { + /* MPU Region 0 */ + { loopCounter, + 0x20, + portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | portMPU_REGION_NORMAL_OIWTNOWA_SHARED, + }, + /* MPU Region 1 */ + { 0, 0, 0 }, + /* MPU Region 2 */ + { 0, 0, 0 }, + /* MPU Region 3 */ + { 0, 0, 0 }, + /* MPU Region 4 */ + { 0, 0, 0 }, + /* MPU Region 5 */ + { 0, 0, 0 }, + /* MPU Region 6 */ + { 0, 0, 0 }, +#if( configTOTAL_MPU_REGIONS == 16 ) + /* MPU Region 7 */ + { 0, 0, 0 }, + /* MPU Region 8 */ + { 0, 0, 0 }, + /* MPU Region 9 */ + { 0, 0, 0 }, + /* MPU Region 10 */ + { 0, 0, 0 }, +#endif + /* Final MPU Region */ + { 0, 0, 0 }, + } + }; + + /* Create the first register test task as a privileged task */ + xReturn = xTaskCreateRestrictedStatic( &( xRegTestOneTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + /* Create the second register test task as an unprivileged task */ + xReturn = xTaskCreateRestrictedStatic( &( xRegTestTwoTaskParameters ), NULL ); + if( pdPASS == xReturn ) + { + sci_print( "Created the Unprivileged Regsiter Test Task\r\n" ); + } + else + { + sci_print( "Failed to create the Unprivileged Regsiter Test Task\r\n" ); + } + } + else + { + sci_print( "Failed to create the Privileged Regsiter Test Task\r\n" ); + } + + return xReturn; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S new file mode 100644 index 00000000000..43b8fc7d050 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S @@ -0,0 +1,448 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#define FREERTOS_ASSEMBLY + #include "portmacro_asm.h" + #include "FreeRTOSConfig.h" +#undef FREERTOS_ASSEMBLY + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern vPortYield + .extern MPU_vTaskDelay + .extern + .extern loopCounter + .text + .arm + +/*-----------------------------------------------------------*/ + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + MOV R0, #0xFF + MOV R1, #0x11 + MOV R2, #0x22 + MOV R3, #0x33 + MOV R4, #0x44 + MOV R5, #0x55 + MOV R6, #0x66 + MOV R7, #0x77 + MOV R8, #0x88 + MOV R9, #0x99 + MOV R10, #0xAA + MOV R11, #0xBB + MOV R12, #0xCC + MOV R14, #0xEE + + /* Fill each FPU register with a known value. */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg1_loop: + /* Perform a yield to increase test coverage */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B reg1_error_loopf + B 0xDEACFC + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + CMP R0, #0xFF + BLNE reg1_error_loop + CMP R1, #0x11 + BLNE reg1_error_loop + CMP R2, #0x22 + BLNE reg1_error_loop + CMP R3, #0x33 + BLNE reg1_error_loop + CMP R4, #0x44 + BLNE reg1_error_loop + CMP R5, #0x55 + BLNE reg1_error_loop + CMP R6, #0x66 + BLNE reg1_error_loop + CMP R7, #0x77 + BLNE reg1_error_loop + CMP R8, #0x88 + BLNE reg1_error_loop + CMP R9, #0x99 + BLNE reg1_error_loop + CMP R10, #0xAA + BLNE reg1_error_loop + CMP R11, #0xBB + BLNE reg1_error_loop + CMP R12, #0xCC + BLNE reg1_error_loop + CMP R14, #0xEE + BLNE reg1_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0] + ADD R1, R1, #1 + STR R1, [R0] + POP { R0-R1 } + + /* Delay for 0x100 ticks before running again */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x100 + /* As this is a privileged task, it can directly call vTaskDelay */ + LDR R1, =vTaskDelay + BLX R1 + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B 0xDEACFD + NOP + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + MOV R0, #0xFF000000 + MOV R1, #0x11000000 + MOV R2, #0x22000000 + MOV R3, #0x33000000 + MOV R4, #0x44000000 + MOV R5, #0x55000000 + MOV R6, #0x66000000 + MOV R7, #0x77000000 + MOV R8, #0x88000000 + MOV R9, #0x99000000 + MOV R10, #0xAA000000 + MOV R11, #0xBB000000 + MOV R12, #0xCC000000 + MOV R14, #0xEE000000 + + /* Likewise the floating point registers */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg2_loop: + + /* Yield to increase test coverage */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B 0xDEACFE + +reg2_loopf_pass: + + CMP R0, #0xFF000000 + BLNE reg2_error_loop + CMP R1, #0x11000000 + BLNE reg2_error_loop + CMP R2, #0x22000000 + BLNE reg2_error_loop + CMP R3, #0x33000000 + BLNE reg2_error_loop + CMP R4, #0x44000000 + BLNE reg2_error_loop + CMP R5, #0x55000000 + BLNE reg2_error_loop + CMP R6, #0x66000000 + BLNE reg2_error_loop + CMP R7, #0x77000000 + BLNE reg2_error_loop + CMP R8, #0x88000000 + BLNE reg2_error_loop + CMP R9, #0x99000000 + BLNE reg2_error_loop + CMP R10, #0xAA000000 + BLNE reg2_error_loop + CMP R11, #0xBB000000 + BLNE reg2_error_loop + CMP R12, #0xCC000000 + BLNE reg2_error_loop + CMP R14, #0xEE000000 + BLNE reg2_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0, #+0x4] + ADD R1, R1, #1 + STR R1, [R0, #+0x4] + POP { R0-R1 } + + /* Delay for 0x200 ticks before running again */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x200 + /* Unprivileged tasks need to use the MPU wrapped functions. + * Change this to be BLX vTaskDelay to trigger a pre-fetch abort. */ + BLX MPU_vTaskDelay + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B 0xDEACFF + NOP + +/* End of file */ +.end + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml new file mode 100644 index 00000000000..aa13978c68b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt new file mode 100644 index 00000000000..d783fef4d6a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/.gitignore new file mode 100644 index 00000000000..2da29b4dd75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/.gitignore @@ -0,0 +1,16 @@ +# STM32Cube IDE. +.settings/ +Debug/ + +# Keil uVision. +DebugConfig/ +RTE/ +EventRecorderStub.scvd +*.uvguix.* + +# IAR +settings +Listings +Objects +BuildLogs +BrowseInfo diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h index 2b18a173e35..f31f1ba1295 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -150,6 +150,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c index 0ed000aacea..80f640c279b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h index 0cf3a6ff713..676db4e07cc 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/app_main.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c index d348648da27..d7f651f20e1 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h index 286c534d9d8..279d995fc41 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Demo/mpu_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject index 7b757048ab5..d0879ed0934 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.cproject @@ -10,21 +10,23 @@ + - - - - - @@ -123,21 +99,22 @@ + - - + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project index 6f28b16c855..c8122883a3f 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.project @@ -58,6 +58,15 @@ + + 1701334040509 + FreeRTOS + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-examples + + 1576807148309 FreeRTOS/portable diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000000..99f26c0203a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c index 08089fed022..4c5226fa9e7 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c index e5e1bc2d948..b89d75ed854 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/GCC/Startup/sysmem.c @@ -60,7 +60,7 @@ register char * stack_ptr asm("sp"); _sbrk Increase program data space. Malloc and related functions depend on this **/ -caddr_t _sbrk(int incr) +char * _sbrk(int incr) { extern char end asm("end"); static char *heap_end; @@ -73,11 +73,11 @@ caddr_t _sbrk(int incr) if (heap_end + incr > stack_ptr) { errno = ENOMEM; - return (caddr_t) -1; + return (char *) -1; } heap_end += incr; - return (caddr_t) prev_heap_end; + return prev_heap_end; } diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd index f9ec12dc601..14ae941fc01 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewd @@ -1,1419 +1,1648 @@ - 3 - - MPUDemo - - ARM - - 1 - - C-SPY - 2 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 1 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - IJET_ID - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - 2 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - PEMICRO_ID - 2 - - 3 - 1 - 1 - - - - - - - - STLINK_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - TIFET_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - - XDS100_ID - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - + 4 + + MPUDemo + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp index 3e46c9d732d..319fc210023 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/IAR/MPUDemo.ewp @@ -1,6 +1,6 @@ - 3 + 4 MPUDemo @@ -11,24 +11,24 @@ General 3 - 35 + 36 1 1 + ICCARM 2 - 37 + 38 1 1 + + AARM 2 - 11 + 12 1 1 + @@ -677,14 +695,6 @@ inputOutputBased - - BUILDACTION - 1 - - - - - ILINK 0 @@ -1080,6 +1090,11 @@ + + BUILDACTION + 2 + + Config diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx index 5aa766a9025..eb35aaaca0d 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/MPUDemo.uvprojx @@ -10,14 +10,14 @@ MPUDemo 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 STM32L475VGTx STMicroelectronics - Keil.STM32L4xx_DFP.2.6.2 - https://www.keil.com/pack/ + Keil.STM32L4xx_DFP.2.6.1 + http://www.keil.com/pack/ IRAM(0x20000000-0x20017FFF) IRAM2(0x10000000-0x10007FFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") @@ -159,7 +159,7 @@ 1 1 0 - 1 + 0 1 0 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c index b4589e05d93..7ffad820603 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_GCC_IAR_Keil/Projects/Keil/memfault_handler.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/.gitignore new file mode 100644 index 00000000000..3f2767e0c3e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/.gitignore @@ -0,0 +1,4 @@ +Listings/ +Objects/ +EventRecorderStub.scvd +*.uvguix.* diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h index 722108fef76..56d196b7d44 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -144,6 +144,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RegTest.c index 0af4655930c..4b9552e0b23 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/GCC_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx index 3fbf7dbf0fa..bf65ae49a13 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx @@ -10,7 +10,7 @@ RTOSDemo 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::..\..\Program Files (x86)\ARM_Compiler_5.06u7 + 5060960::V5.06 update 7 (build 960)::.\ARM_Compiler_5.06u7 0 @@ -463,6 +463,57 @@ mpu_wrappers_v2.c 1 ..\..\..\Source\portable\Common\mpu_wrappers_v2.c + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --diag_suppress=1296 + + + + + + + stream_buffer.c diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RegTest.c index 1f7f98fe7a2..3cc36fbd5aa 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/Keil_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/main.c index 868b8dc5fa5..2a4ebfde762 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -53,22 +53,22 @@ /*-----------------------------------------------------------*/ /* Misc constants. */ -#define mainDONT_BLOCK ( 0 ) +#define mainDONT_BLOCK ( 0 ) /* GCC specifics. */ -#define mainALIGN_TO( x ) __attribute__((aligned(x))) +#define mainALIGN_TO( x ) __attribute__( ( aligned( x ) ) ) /* Hardware register addresses. */ -#define mainVTOR ( * ( volatile uint32_t * ) 0xE000ED08 ) +#define mainVTOR ( *( volatile uint32_t * ) 0xE000ED08 ) /* The period of the timer must be less than the rate at which -configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the -check task will think the timer has stopped. */ -#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 ) + * configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the + * check task will think the timer has stopped. */ +#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 ) /* The name of the task that is deleted by the Idle task is used in a couple of -places, so is #defined. */ -#define mainTASK_TO_DELETE_NAME "DeleteMe" + * places, so is #defined. */ +#define mainTASK_TO_DELETE_NAME "DeleteMe" /*-----------------------------------------------------------*/ /* Prototypes for functions that implement tasks. -----------*/ @@ -96,8 +96,8 @@ places, so is #defined. */ * User mode, and vRegTest2Implementation() receives the task handle using its * parameter. */ -extern void vRegTest1Implementation( void *pvParameters ); -extern void vRegTest2Implementation( void *pvParameters ); +extern void vRegTest1Implementation( void * pvParameters ); +extern void vRegTest2Implementation( void * pvParameters ); /* * The second two register test tasks are similar to the first two, but do test @@ -108,9 +108,9 @@ extern void vRegTest2Implementation( void *pvParameters ); * * The functions ending 'Implementation' are called by the register check tasks. */ -static void prvRegTest3Task( void *pvParameters ); +static void prvRegTest3Task( void * pvParameters ); extern void vRegTest3Implementation( void ); -static void prvRegTest4Task( void *pvParameters ); +static void prvRegTest4Task( void * pvParameters ); extern void vRegTest4Implementation( void ); /* @@ -128,7 +128,7 @@ extern void vRegTest4Implementation( void ); * either pass or fail to the terminal, depending on the status of the reg * test tasks (no write is performed in the simulator!). */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); /* * Prototype for a task created in User mode using the original vTaskCreate() @@ -147,13 +147,13 @@ static void prvOldStyleUserModeTask( void ); * vTaskCreate() API function. The task demonstrates the characteristics of * such a task, before simply deleting itself. */ -static void prvOldStylePrivilegedModeTask( void *pvParameters ); +static void prvOldStylePrivilegedModeTask( void * pvParameters ); /* * A task that exercises the API of various RTOS objects before being deleted by * the Idle task. This is done for MPU API code coverage test purposes. */ -static void prvTaskToDelete( void *pvParameters ); +static void prvTaskToDelete( void * pvParameters ); /* * Functions called by prvTaskToDelete() to exercise the MPU API. @@ -174,7 +174,7 @@ static void prvSetupHardware( void ); * is simpler to call from asm code than the normal vTaskDelete() API function. * It has the noinline attribute because it is called from asm code. */ -void vMainDeleteMe( void ) __attribute__((noinline)); +void vMainDeleteMe( void ) __attribute__( ( noinline ) ); /* * Used by the first two reg test tasks and a software timer callback function @@ -183,7 +183,8 @@ void vMainDeleteMe( void ) __attribute__((noinline)); * task detects an error it will delete itself, and in so doing prevent itself * from sending any more 'I'm Alive' messages to the check task. */ -void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber ); +void vMainSendImAlive( QueueHandle_t xHandle, + uint32_t ulTaskNumber ); /* * The check task is created with access to three memory regions (plus its @@ -205,20 +206,21 @@ static void prvTimerCallback( TimerHandle_t xExpiredTimer ); * The callback function and a function that is pended used when exercising the * timer API. */ -static void prvPendedFunctionCall( void *pvParameter1, uint32_t ulParameter2 ); +static void prvPendedFunctionCall( void * pvParameter1, + uint32_t ulParameter2 ); static void prvTestTimerCallback( TimerHandle_t xTimer ); /*-----------------------------------------------------------*/ /* The handle of the queue used to communicate between tasks and between tasks -and interrupts. Note that this is a global scope variable that falls outside of -any MPU region. As such other techniques have to be used to allow the tasks -to gain access to the queue. See the comments in the tasks themselves for -further information. */ + * and interrupts. Note that this is a global scope variable that falls outside of + * any MPU region. As such other techniques have to be used to allow the tasks + * to gain access to the queue. See the comments in the tasks themselves for + * further information. */ QueueHandle_t xGlobalScopeCheckQueue = NULL; /* Holds the handle of a task that is deleted in the idle task hook - this is -done for code coverage test purposes only. */ + * done for code coverage test purposes only. */ static TaskHandle_t xTaskToDelete = NULL; /* The timer that periodically sends data to the check task on the queue. */ @@ -227,102 +229,102 @@ static TimerHandle_t xTimer = NULL; /* Just used to check start up code for initialised an uninitialised data. */ volatile uint32_t ul1 = 0x123, ul2 = 0; -#if defined ( __GNUC__ ) - /* Memory map read directl from linker variables. */ - extern uint32_t __FLASH_segment_start__[]; - extern uint32_t __FLASH_segment_end__[]; - extern uint32_t __SRAM_segment_start__[]; - extern uint32_t __SRAM_segment_end__[]; - extern uint32_t __privileged_functions_start__[]; - extern uint32_t __privileged_functions_end__[]; - extern uint32_t __privileged_data_start__[]; - extern uint32_t __privileged_data_end__[]; - extern uint32_t __privileged_functions_actual_end__[]; - extern uint32_t __privileged_data_actual_end__[]; -#else - extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; - extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; - - /* Must be set manually to match memory map. */ - const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x00000000UL; - const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x00080000UL; - const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000UL; - const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20008000UL; - const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x00000000UL; - const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x00010000UL; - const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); - const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); - const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000UL; - const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20004000UL; -#endif +#if defined( __GNUC__ ) + /* Memory map read directl from linker variables. */ + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + extern uint32_t __privileged_functions_actual_end__[]; + extern uint32_t __privileged_data_actual_end__[]; +#else /* if defined( __GNUC__ ) */ + extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; + extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; + +/* Must be set manually to match memory map. */ + const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x00000000UL; + const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x00080000UL; + const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000UL; + const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20008000UL; + const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x00000000UL; + const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x00010000UL; + const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); + const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); + const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000UL; + const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20004000UL; +#endif /* if defined( __GNUC__ ) */ /*-----------------------------------------------------------*/ /* Data used by the 'check' task. ---------------------------*/ /*-----------------------------------------------------------*/ /* Define the constants used to allocate the check task stack. Note that the -stack size is defined in words, not bytes. */ -#define mainCHECK_TASK_STACK_SIZE_WORDS 128 -#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * stack size is defined in words, not bytes. */ +#define mainCHECK_TASK_STACK_SIZE_WORDS 128 +#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stack that will be used by the check task. The kernel will - automatically create an MPU region for the stack. The stack alignment must - match its size, so if 128 words are reserved for the stack then it must be - aligned to ( 128 * 4 ) bytes. */ + * automatically create an MPU region for the stack. The stack alignment must + * match its size, so if 128 words are reserved for the stack then it must be + * aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainCHECK_TASK_STACK_ALIGNMENT ); /* Declare three arrays - an MPU region will be created for each array -using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE -MPU FUNCTIONALITY, the data is not used by the check tasks primary function -of monitoring the reg test tasks and printing out status information. - -Note that the arrays allocate slightly more RAM than is actually assigned to -the MPU region. This is to permit writes off the end of the array to be -detected even when the arrays are placed in adjacent memory locations (with no -gaps between them). The align size must be a power of two. */ -#define mainREAD_WRITE_ARRAY_SIZE 130 -#define mainREAD_WRITE_ALIGN_SIZE 128 + * using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE + * MPU FUNCTIONALITY, the data is not used by the check tasks primary function + * of monitoring the reg test tasks and printing out status information. + * + * Note that the arrays allocate slightly more RAM than is actually assigned to + * the MPU region. This is to permit writes off the end of the array to be + * detected even when the arrays are placed in adjacent memory locations (with no + * gaps between them). The align size must be a power of two. */ +#define mainREAD_WRITE_ARRAY_SIZE 130 +#define mainREAD_WRITE_ALIGN_SIZE 128 char cReadWriteArray[ mainREAD_WRITE_ARRAY_SIZE ] mainALIGN_TO( mainREAD_WRITE_ALIGN_SIZE ); -#define mainREAD_ONLY_ARRAY_SIZE 260 -#define mainREAD_ONLY_ALIGN_SIZE 256 +#define mainREAD_ONLY_ARRAY_SIZE 260 +#define mainREAD_ONLY_ALIGN_SIZE 256 char cReadOnlyArray[ mainREAD_ONLY_ARRAY_SIZE ] mainALIGN_TO( mainREAD_ONLY_ALIGN_SIZE ); -#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 -#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 +#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 +#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 char cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] mainALIGN_TO( mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ); /* The following two variables are used to communicate the status of the second -two register check tasks (tasks 3 and 4) to the check task. If the variables -keep incrementing, then the register check tasks have not discovered any errors. -If a variable stops incrementing, then an error has been found. The variables -overlay the array that the check task has access to so they can be read by the -check task without causing a memory fault. The check task has the highest -priority so will have finished with the array before the register test tasks -start to access it. */ -volatile uint32_t *pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); + * two register check tasks (tasks 3 and 4) to the check task. If the variables + * keep incrementing, then the register check tasks have not discovered any errors. + * If a variable stops incrementing, then an error has been found. The variables + * overlay the array that the check task has access to so they can be read by the + * check task without causing a memory fault. The check task has the highest + * priority so will have finished with the array before the register test tasks + * start to access it. */ +volatile uint32_t * pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), * pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); /* Fill in a TaskParameters_t structure to define the check task - this is the -structure passed to the xTaskCreateRestricted() function. */ + * structure passed to the xTaskCreateRestricted() function. */ static const TaskParameters_t xCheckTaskParameters = { - prvCheckTask, /* pvTaskCode - the function that implements the task. */ - "Check", /* pcName */ - mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ - ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT,/* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ - xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - - /* xRegions - In this case the xRegions array is used to create MPU regions - for all three of the arrays declared directly above. Each MPU region is - created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE - MPU FUNCTIONALITY, the data is not used by the check tasks primary function - of monitoring the reg test tasks and printing out status information.*/ - { - /* Base address Length Parameters */ - { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, - { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, - { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } - } + prvCheckTask, /* pvTaskCode - the function that implements the task. */ + "Check", /* pcName */ + mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ + ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ + xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + + /* xRegions - In this case the xRegions array is used to create MPU regions + * for all three of the arrays declared directly above. Each MPU region is + * created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE + * MPU FUNCTIONALITY, the data is not used by the check tasks primary function + * of monitoring the reg test tasks and printing out status information.*/ + { + /* Base address Length Parameters */ + { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, + { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, + { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } + } }; @@ -332,14 +334,14 @@ static const TaskParameters_t xCheckTaskParameters = /*-----------------------------------------------------------*/ /* Define the constants used to allocate the reg test task stacks. Note that -that stack size is defined in words, not bytes. */ -#define mainREG_TEST_STACK_SIZE_WORDS 128 -#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * that stack size is defined in words, not bytes. */ +#define mainREG_TEST_STACK_SIZE_WORDS 128 +#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stacks that will be used by the reg test tasks. The kernel will -automatically create an MPU region for the stack. The stack alignment must -match its size, so if 128 words are reserved for the stack then it must be -aligned to ( 128 * 4 ) bytes. */ + * automatically create an MPU region for the stack. The stack alignment must + * match its size, so if 128 words are reserved for the stack then it must be + * aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xRegTest1Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); static portSTACK_TYPE xRegTest2Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); static portSTACK_TYPE xRegTest3Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); @@ -348,69 +350,69 @@ static portSTACK_TYPE xRegTest4Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_ /* Fill in a TaskParameters_t structure per reg test task to define the tasks. */ static const TaskParameters_t xRegTest1Parameters = { - vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */ - "RegTest1", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ - xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */ + "RegTest1", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ + xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ static TaskParameters_t xRegTest2Parameters = { - vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */ - "RegTest2", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ - tskIDLE_PRIORITY, /* uxPriority */ - xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */ + "RegTest2", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + tskIDLE_PRIORITY, /* uxPriority */ + xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ static const TaskParameters_t xRegTest3Parameters = { - prvRegTest3Task, /* pvTaskCode - the function that implements the task. */ - "RegTest3", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) configREG_TEST_TASK_3_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ - xRegTest3Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + prvRegTest3Task, /* pvTaskCode - the function that implements the task. */ + "RegTest3", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) configREG_TEST_TASK_3_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ + xRegTest3Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ static const TaskParameters_t xRegTest4Parameters = { - prvRegTest4Task, /* pvTaskCode - the function that implements the task. */ - "RegTest4", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) configREG_TEST_TASK_4_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ - xRegTest4Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + prvRegTest4Task, /* pvTaskCode - the function that implements the task. */ + "RegTest4", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) configREG_TEST_TASK_4_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ + xRegTest4Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ @@ -418,690 +420,709 @@ static const TaskParameters_t xRegTest4Parameters = /*-----------------------------------------------------------*/ /* Define the constants used to allocate the stack of the task that is -deleted. Note that that stack size is defined in words, not bytes. */ -#define mainDELETE_TASK_STACK_SIZE_WORDS 128 -#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * deleted. Note that that stack size is defined in words, not bytes. */ +#define mainDELETE_TASK_STACK_SIZE_WORDS 128 +#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stack that will be used by the task that gets deleted. The -kernel will automatically create an MPU region for the stack. The stack -alignment must match its size, so if 128 words are reserved for the stack -then it must be aligned to ( 128 * 4 ) bytes. */ + * kernel will automatically create an MPU region for the stack. The stack + * alignment must match its size, so if 128 words are reserved for the stack + * then it must be aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xDeleteTaskStack[ mainDELETE_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainTASK_TO_DELETE_STACK_ALIGNMENT ); static TaskParameters_t xTaskToDeleteParameters = { - prvTaskToDelete, /* pvTaskCode - the function that implements the task. */ - mainTASK_TO_DELETE_NAME, /* pcName */ - mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ - ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this task is privileged because it creates and deletes kernel objects. */ - xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - } + prvTaskToDelete, /* pvTaskCode - the function that implements the task. */ + mainTASK_TO_DELETE_NAME, /* pcName */ + mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this task is privileged because it creates and deletes kernel objects. */ + xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + } }; /*-----------------------------------------------------------*/ int main( void ) { - /* Used to check linker configuration. */ - configASSERT( ul1 == 0x123 ); - configASSERT( ul2 == 0 ); - prvSetupHardware(); - - /* Create the queue used to pass "I'm alive" messages to the check task. */ - xGlobalScopeCheckQueue = xQueueCreate( 1, sizeof( uint32_t ) ); - - /* One check task uses the task parameter to receive the queue handle. - This allows the file scope variable to be accessed from within the task. - The pvParameters member of xRegTest2Parameters can only be set after the - queue has been created so is set here. */ - xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue; - - /* Create three test tasks. Handles to the created tasks are not required, - hence the second parameter is NULL. */ - xTaskCreateRestricted( &xRegTest1Parameters, NULL ); - xTaskCreateRestricted( &xRegTest2Parameters, NULL ); - xTaskCreateRestricted( &xCheckTaskParameters, NULL ); - - /* Create a task that does nothing but ensure some of the MPU API functions - can be called correctly, then get deleted. This is done for code coverage - test purposes only. The task's handle is saved in xTaskToDelete so it can - get deleted in the idle task hook. */ - xTaskCreateRestricted( &xTaskToDeleteParameters, &xTaskToDelete ); - - xTaskCreate( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ - "Task2", /* Text name for the task. */ - 100, /* Stack depth in words. */ - NULL, /* Task parameters. */ - ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ - NULL /* Handle. */ - ); - - /* Create the third and fourth register check tasks, as described at the top - of this file. */ - xTaskCreateRestricted( &xRegTest3Parameters, NULL ); - xTaskCreateRestricted( &xRegTest4Parameters, NULL ); - - /* Create and start the software timer. */ - xTimer = xTimerCreate( "Timer", /* Test name for the timer. */ - mainTIMER_PERIOD, /* Period of the timer. */ - pdTRUE, /* The timer will auto-reload itself. */ - ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */ - prvTimerCallback ); /* The function called when the timer expires. */ - configASSERT( xTimer ); - xTimerStart( xTimer, mainDONT_BLOCK ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - for( ;; ); + TaskHandle_t xRegTest1TaskHandle, xRegTest2TaskHandle, xCheckTaskHandle; + + /* Used to check linker configuration. */ + configASSERT( ul1 == 0x123 ); + configASSERT( ul2 == 0 ); + prvSetupHardware(); + + /* Create the queue used to pass "I'm alive" messages to the check task. */ + xGlobalScopeCheckQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + + /* One check task uses the task parameter to receive the queue handle. + * This allows the file scope variable to be accessed from within the task. + * The pvParameters member of xRegTest2Parameters can only be set after the + * queue has been created so is set here. */ + xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue; + + /* Create three test tasks. */ + xTaskCreateRestricted( &xRegTest1Parameters, &( xRegTest1TaskHandle ) ); + xTaskCreateRestricted( &xRegTest2Parameters, &( xRegTest2TaskHandle ) ); + xTaskCreateRestricted( &xCheckTaskParameters, &( xCheckTaskHandle ) ); + + vGrantAccessToQueue( xRegTest1TaskHandle, xGlobalScopeCheckQueue ); + vGrantAccessToQueue( xRegTest2TaskHandle, xGlobalScopeCheckQueue ); + vGrantAccessToQueue( xCheckTaskHandle, xGlobalScopeCheckQueue ); + + /* Create a task that does nothing but ensure some of the MPU API functions + * can be called correctly, then get deleted. This is done for code coverage + * test purposes only. The task's handle is saved in xTaskToDelete so it can + * get deleted in the idle task hook. */ + xTaskCreateRestricted( &xTaskToDeleteParameters, &xTaskToDelete ); + + xTaskCreate( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ + "Task2", /* Text name for the task. */ + 100, /* Stack depth in words. */ + NULL, /* Task parameters. */ + ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ + NULL /* Handle. */ + ); + + /* Create the third and fourth register check tasks, as described at the top + * of this file. */ + xTaskCreateRestricted( &xRegTest3Parameters, NULL ); + xTaskCreateRestricted( &xRegTest4Parameters, NULL ); + + /* Create and start the software timer. */ + xTimer = xTimerCreate( "Timer", /* Test name for the timer. */ + mainTIMER_PERIOD, /* Period of the timer. */ + pdTRUE, /* The timer will auto-reload itself. */ + ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */ + prvTimerCallback ); /* The function called when the timer expires. */ + configASSERT( xTimer ); + xTimerStart( xTimer, mainDONT_BLOCK ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + * task. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { /* This task is created in privileged mode so can access the file scope -queue variable. Take a stack copy of this before the task is set into user -mode. Once that task is in user mode the file scope queue variable will no -longer be accessible but the stack copy will. */ -QueueHandle_t xQueue = xGlobalScopeCheckQueue; -int32_t lMessage; -uint32_t ulStillAliveCounts[ 3 ] = { 0 }; -const char *pcStatusMessage = "PASS\r\n"; -uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0; + * queue variable. Take a stack copy of this before the task is set into user + * mode. Once that task is in user mode the file scope queue variable will no + * longer be accessible but the stack copy will. */ + QueueHandle_t xQueue = xGlobalScopeCheckQueue; + int32_t lMessage; + uint32_t ulStillAliveCounts[ 3 ] = { 0 }; + const char * pcStatusMessage = "PASS\r\n"; + uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0; /* The register test tasks that also test the floating point registers increment -a counter on each iteration of their loop. The counters are inside the array -that this task has access to. */ -volatile uint32_t *pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); + * a counter on each iteration of their loop. The counters are inside the array + * that this task has access to. */ + volatile uint32_t * pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), * pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); /* ulCycleCount is incremented on each cycle of the check task. It can be -viewed updating in the Keil watch window as the simulator does not print to -the ITM port. */ -volatile uint32_t ulCycleCount = 0; - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* Demonstrate how the various memory regions can and can't be accessed. - The task privilege level is set down to user mode within this function. */ - prvTestMemoryRegions(); - - /* Clear overlaid reg test counters before entering the loop below. */ - *pulOverlaidCounter3 = 0UL; - *pulOverlaidCounter4 = 0UL; - - /* This loop performs the main function of the task, which is blocking - on a message queue then processing each message as it arrives. */ - for( ;; ) - { - /* Wait for the next message to arrive. */ - xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); - - switch( lMessage ) - { - case configREG_TEST_1_STILL_EXECUTING : - case configREG_TEST_2_STILL_EXECUTING : - case configTIMER_STILL_EXECUTING : - /* Message from the first or second register check task, or - the timer callback function. Increment the count of the - number of times the message source has sent the message as - the message source must still be executed. */ - ( ulStillAliveCounts[ lMessage ] )++; - break; - - case configPRINT_SYSTEM_STATUS : - /* Message from tick hook, time to print out the system - status. If messages have stopped arriving from either of - the first two reg test task or the timer callback then the - status must be set to fail. */ - if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) ) - { - /* One or both of the test tasks are no longer sending - 'still alive' messages. */ - pcStatusMessage = "FAIL\r\n"; - } - else - { - /* Reset the count of 'still alive' messages. */ - memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); - } - - /* Check that the register test 3 task is still incrementing - its counter, and therefore still running. */ - if( ulLastRegTest3CountValue == *pulOverlaidCounter3 ) - { - pcStatusMessage = "FAIL\r\n"; - } - ulLastRegTest3CountValue = *pulOverlaidCounter3; - - /* Check that the register test 4 task is still incrementing - its counter, and therefore still running. */ - if( ulLastRegTest4Value == *pulOverlaidCounter4 ) - { - pcStatusMessage = "FAIL\r\n"; - } - ulLastRegTest4Value = *pulOverlaidCounter4; - - /**** Print pcStatusMessage here. ****/ - ( void ) pcStatusMessage; - - /* The cycle count can be viewed updating in the Keil watch - window if ITM printf is not being used. */ - ulCycleCount++; - break; - - default : - /* Something unexpected happened. Delete this task so the - error is apparent (no output will be displayed). */ - vMainDeleteMe(); - break; - } - } + * viewed updating in the Keil watch window as the simulator does not print to + * the ITM port. */ + volatile uint32_t ulCycleCount = 0; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* Demonstrate how the various memory regions can and can't be accessed. + * The task privilege level is set down to user mode within this function. */ + prvTestMemoryRegions(); + + /* Clear overlaid reg test counters before entering the loop below. */ + *pulOverlaidCounter3 = 0UL; + *pulOverlaidCounter4 = 0UL; + + /* This loop performs the main function of the task, which is blocking + * on a message queue then processing each message as it arrives. */ + for( ; ; ) + { + /* Wait for the next message to arrive. */ + xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); + + switch( lMessage ) + { + case configREG_TEST_1_STILL_EXECUTING: + case configREG_TEST_2_STILL_EXECUTING: + case configTIMER_STILL_EXECUTING: + + /* Message from the first or second register check task, or + * the timer callback function. Increment the count of the + * number of times the message source has sent the message as + * the message source must still be executed. */ + ( ulStillAliveCounts[ lMessage ] )++; + break; + + case configPRINT_SYSTEM_STATUS: + + /* Message from tick hook, time to print out the system + * status. If messages have stopped arriving from either of + * the first two reg test task or the timer callback then the + * status must be set to fail. */ + if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) ) + { + /* One or both of the test tasks are no longer sending + * 'still alive' messages. */ + pcStatusMessage = "FAIL\r\n"; + } + else + { + /* Reset the count of 'still alive' messages. */ + memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); + } + + /* Check that the register test 3 task is still incrementing + * its counter, and therefore still running. */ + if( ulLastRegTest3CountValue == *pulOverlaidCounter3 ) + { + pcStatusMessage = "FAIL\r\n"; + } + + ulLastRegTest3CountValue = *pulOverlaidCounter3; + + /* Check that the register test 4 task is still incrementing + * its counter, and therefore still running. */ + if( ulLastRegTest4Value == *pulOverlaidCounter4 ) + { + pcStatusMessage = "FAIL\r\n"; + } + + ulLastRegTest4Value = *pulOverlaidCounter4; + + /**** Print pcStatusMessage here. ****/ + ( void ) pcStatusMessage; + + /* The cycle count can be viewed updating in the Keil watch + * window if ITM printf is not being used. */ + ulCycleCount++; + break; + + default: + + /* Something unexpected happened. Delete this task so the + * error is apparent (no output will be displayed). */ + vMainDeleteMe(); + break; + } + } } /*-----------------------------------------------------------*/ static void prvTestMemoryRegions( void ) { -int32_t x; -char cTemp; - - /* The check task (from which this function is called) is created in the - Privileged mode. The privileged array can be both read from and written - to while this task is privileged. */ - cPrivilegedOnlyAccessArray[ 0 ] = 'a'; - if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) - { - /* Something unexpected happened. Delete this task so the error is - apparent (no output will be displayed). */ - vMainDeleteMe(); - } - - /* Writing off the end of the RAM allocated to this task will *NOT* cause a - protection fault because the task is still executing in a privileged mode. - Uncomment the following to test. */ - /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ - - /* Now set the task into user mode. */ - portSWITCH_TO_USER_MODE(); - - /* Accessing the privileged only array will now cause a fault. Uncomment - the following line to test. */ - /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ - - /* The read/write array can still be successfully read and written. */ - for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ ) - { - cReadWriteArray[ x ] = 'a'; - if( cReadWriteArray[ x ] != 'a' ) - { - /* Something unexpected happened. Delete this task so the error is - apparent (no output will be displayed). */ - vMainDeleteMe(); - } - } - - /* But attempting to read or write off the end of the RAM allocated to this - task will cause a fault. Uncomment either of the following two lines to - test. */ - /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ - /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ - - /* The read only array can be successfully read... */ - for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ ) - { - cTemp = cReadOnlyArray[ x ]; - } - - /* ...but cannot be written. Uncomment the following line to test. */ - /* cReadOnlyArray[ 0 ] = 'a'; */ - - /* Writing to the first and last locations in the stack array should not - cause a protection fault. Note that doing this will cause the kernel to - detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than - 1, hence the test is commented out by default. */ - /* xCheckTaskStack[ 0 ] = 0; - xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */ - - /* Writing off either end of the stack array should cause a protection - fault, uncomment either of the following two lines to test. */ - /* xCheckTaskStack[ -1 ] = 0; */ - /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ - - ( void ) cTemp; + int32_t x; + char cTemp; + + /* The check task (from which this function is called) is created in the + * Privileged mode. The privileged array can be both read from and written + * to while this task is privileged. */ + cPrivilegedOnlyAccessArray[ 0 ] = 'a'; + + if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + * apparent (no output will be displayed). */ + vMainDeleteMe(); + } + + /* Writing off the end of the RAM allocated to this task will *NOT* cause a + * protection fault because the task is still executing in a privileged mode. + * Uncomment the following to test. */ + /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ + + /* Now set the task into user mode. */ + portSWITCH_TO_USER_MODE(); + + /* Accessing the privileged only array will now cause a fault. Uncomment + * the following line to test. */ + /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ + + /* The read/write array can still be successfully read and written. */ + for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ ) + { + cReadWriteArray[ x ] = 'a'; + + if( cReadWriteArray[ x ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + * apparent (no output will be displayed). */ + vMainDeleteMe(); + } + } + + /* But attempting to read or write off the end of the RAM allocated to this + * task will cause a fault. Uncomment either of the following two lines to + * test. */ + /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ + /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ + + /* The read only array can be successfully read... */ + for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ ) + { + cTemp = cReadOnlyArray[ x ]; + } + + /* ...but cannot be written. Uncomment the following line to test. */ + /* cReadOnlyArray[ 0 ] = 'a'; */ + + /* Writing to the first and last locations in the stack array should not + * cause a protection fault. Note that doing this will cause the kernel to + * detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than + * 1, hence the test is commented out by default. */ + + /* xCheckTaskStack[ 0 ] = 0; + * xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */ + + /* Writing off either end of the stack array should cause a protection + * fault, uncomment either of the following two lines to test. */ + /* xCheckTaskStack[ -1 ] = 0; */ + /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ + + ( void ) cTemp; } /*-----------------------------------------------------------*/ static void prvExerciseEventGroupAPI( void ) { -EventGroupHandle_t xEventGroup; -EventBits_t xBits; -const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01; - - /* Exercise some event group functions. */ - xEventGroup = xEventGroupCreate(); - configASSERT( xEventGroup ); - - /* No bits should be set. */ - xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK ); - configASSERT( xBits == ( EventBits_t ) 0 ); - - /* Set bits and read back to ensure the bits were set. */ - xEventGroupSetBits( xEventGroup, xBitsToWaitFor ); - xBits = xEventGroupGetBits( xEventGroup ); - configASSERT( xBits == xBitsToWaitFor ); - - /* Clear a bit and read back again using a different API function. */ - xEventGroupClearBits( xEventGroup, xBitToClear ); - xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK ); - configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) ); - - /* Finished with the event group. */ - vEventGroupDelete( xEventGroup ); + EventGroupHandle_t xEventGroup; + EventBits_t xBits; + const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01; + + /* Exercise some event group functions. */ + xEventGroup = xEventGroupCreate(); + configASSERT( xEventGroup ); + + /* No bits should be set. */ + xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK ); + configASSERT( xBits == ( EventBits_t ) 0 ); + + /* Set bits and read back to ensure the bits were set. */ + xEventGroupSetBits( xEventGroup, xBitsToWaitFor ); + xBits = xEventGroupGetBits( xEventGroup ); + configASSERT( xBits == xBitsToWaitFor ); + + /* Clear a bit and read back again using a different API function. */ + xEventGroupClearBits( xEventGroup, xBitToClear ); + xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK ); + configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) ); + + /* Finished with the event group. */ + vEventGroupDelete( xEventGroup ); } /*-----------------------------------------------------------*/ static void prvExerciseSemaphoreAPI( void ) { -SemaphoreHandle_t xSemaphore; -const UBaseType_t uxMaxCount = 5, uxInitialCount = 0; - - /* Most of the semaphore API is common to the queue API and is already being - used. This function uses a few semaphore functions that are unique to the - RTOS objects, rather than generic and used by queues also. - - First create and use a counting semaphore. */ - xSemaphore = xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ); - configASSERT( xSemaphore ); - - /* Give the semaphore a couple of times and ensure the count is returned - correctly. */ - xSemaphoreGive( xSemaphore ); - xSemaphoreGive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 ); - vSemaphoreDelete( xSemaphore ); - - /* Create a recursive mutex, and ensure the mutex holder and count are - returned returned correctly. */ - xSemaphore = xSemaphoreCreateRecursiveMutex(); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphore ); - xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); - xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) ); - xSemaphoreGiveRecursive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); - xSemaphoreGiveRecursive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); - vSemaphoreDelete( xSemaphore ); - - /* Create a normal mutex, and sure the mutex holder and count are returned - returned correctly. */ - xSemaphore = xSemaphoreCreateMutex(); - configASSERT( xSemaphore ); - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */ - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); - xSemaphoreGive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); - vSemaphoreDelete( xSemaphore ); + SemaphoreHandle_t xSemaphore; + const UBaseType_t uxMaxCount = 5, uxInitialCount = 0; + + /* Most of the semaphore API is common to the queue API and is already being + * used. This function uses a few semaphore functions that are unique to the + * RTOS objects, rather than generic and used by queues also. + * + * First create and use a counting semaphore. */ + xSemaphore = xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ); + configASSERT( xSemaphore ); + + /* Give the semaphore a couple of times and ensure the count is returned + * correctly. */ + xSemaphoreGive( xSemaphore ); + xSemaphoreGive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 ); + vSemaphoreDelete( xSemaphore ); + + /* Create a recursive mutex, and ensure the mutex holder and count are + * returned returned correctly. */ + xSemaphore = xSemaphoreCreateRecursiveMutex(); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphore ); + xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); + xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) ); + xSemaphoreGiveRecursive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); + xSemaphoreGiveRecursive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); + vSemaphoreDelete( xSemaphore ); + + /* Create a normal mutex, and sure the mutex holder and count are returned + * returned correctly. */ + xSemaphore = xSemaphoreCreateMutex(); + configASSERT( xSemaphore ); + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */ + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); + xSemaphoreGive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); + vSemaphoreDelete( xSemaphore ); } /*-----------------------------------------------------------*/ static void prvExerciseTaskNotificationAPI( void ) { -uint32_t ulNotificationValue; -BaseType_t xReturned; - - /* The task should not yet have a notification pending. */ - xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); - configASSERT( xReturned == pdFAIL ); - configASSERT( ulNotificationValue == 0UL ); - - /* Exercise the 'give' and 'take' versions of the notification API. */ - xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); - xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); - ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK ); - configASSERT( ulNotificationValue == 2 ); - - /* Exercise the 'notify' and 'clear' API. */ - ulNotificationValue = 20; - xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); - ulNotificationValue = 0; - xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); - configASSERT( xReturned == pdPASS ); - configASSERT( ulNotificationValue == 20 ); - xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); - xReturned = xTaskNotifyStateClear( NULL ); - configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */ - xReturned = xTaskNotifyStateClear( NULL ); - configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */ + uint32_t ulNotificationValue; + BaseType_t xReturned; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotificationValue == 0UL ); + + /* Exercise the 'give' and 'take' versions of the notification API. */ + xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK ); + configASSERT( ulNotificationValue == 2 ); + + /* Exercise the 'notify' and 'clear' API. */ + ulNotificationValue = 20; + xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); + ulNotificationValue = 0; + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotificationValue == 20 ); + xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */ + xReturned = xTaskNotifyStateClear( NULL ); + configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */ } /*-----------------------------------------------------------*/ -static void prvTaskToDelete( void *pvParameters ) +static void prvTaskToDelete( void * pvParameters ) { - /* Remove compiler warnings about unused parameters. */ - ( void ) pvParameters; - - /* Check the enter and exit critical macros are working correctly. If the - SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will - fault. */ - #if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) - { - taskENTER_CRITICAL(); - taskEXIT_CRITICAL(); - } - #endif - - /* Exercise the API of various RTOS objects. */ - prvExerciseEventGroupAPI(); - prvExerciseSemaphoreAPI(); - prvExerciseTaskNotificationAPI(); - prvExerciseStreamBufferAPI(); - prvExerciseTimerAPI(); - - /* For code coverage test purposes it is deleted by the Idle task. */ - configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 ); - configASSERT( uxTaskGetStackHighWaterMark2( NULL ) > 0 ); - /* Run time stats are not being gathered - this is just to exercise - API. */ - configASSERT( ulTaskGetIdleRunTimeCounter() == 0 ); - vTaskSuspend( NULL ); + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Check the enter and exit critical macros are working correctly. If the + * SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will + * fault. */ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + { + taskENTER_CRITICAL(); + taskEXIT_CRITICAL(); + } + #endif + + /* Exercise the API of various RTOS objects. */ + prvExerciseEventGroupAPI(); + prvExerciseSemaphoreAPI(); + prvExerciseTaskNotificationAPI(); + prvExerciseStreamBufferAPI(); + prvExerciseTimerAPI(); + + /* For code coverage test purposes it is deleted by the Idle task. */ + configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 ); + configASSERT( uxTaskGetStackHighWaterMark2( NULL ) > 0 ); + + /* Run time stats are not being gathered - this is just to exercise + * API. */ + configASSERT( ulTaskGetIdleRunTimeCounter() == 0 ); + vTaskSuspend( NULL ); } /*-----------------------------------------------------------*/ -static void prvPendedFunctionCall( void *pvParameter1, uint32_t ulParameter2 ) +static void prvPendedFunctionCall( void * pvParameter1, + uint32_t ulParameter2 ) { -uint32_t *pulCounter = ( uint32_t * ) pvParameter1; + uint32_t * pulCounter = ( uint32_t * ) pvParameter1; - /* Increment the paramater to show the pended function has executed. */ - ( *pulCounter )++; + /* Increment the paramater to show the pended function has executed. */ + ( *pulCounter )++; } /*-----------------------------------------------------------*/ static void prvTestTimerCallback( TimerHandle_t xTimer ) { -uint32_t ulTimerID; + uint32_t ulTimerID; - /* Increment the timer's ID to show the callback has executed. */ - ulTimerID = ( uint32_t ) pvTimerGetTimerID( xTimer ); - ulTimerID++; - vTimerSetTimerID( xTimer, ( void * ) ulTimerID ); + /* Increment the timer's ID to show the callback has executed. */ + ulTimerID = ( uint32_t ) pvTimerGetTimerID( xTimer ); + ulTimerID++; + vTimerSetTimerID( xTimer, ( void * ) ulTimerID ); } /*-----------------------------------------------------------*/ static void prvExerciseTimerAPI( void ) { -TimerHandle_t xTimer; -const char * const pcTimerName = "TestTimer"; -const TickType_t x3ms = pdMS_TO_TICKS( 3 ); -uint32_t ulValueForTesting = 0; - - xTimer = xTimerCreate( pcTimerName, - x3ms, - pdFALSE, /* Created as a one-shot timer. */ - 0, - prvTestTimerCallback ); - configASSERT( xTimer ); - configASSERT( xTimerIsTimerActive( xTimer ) == pdFALSE ); - configASSERT( xTimerGetTimerDaemonTaskHandle() != NULL ); - configASSERT( strcmp( pcTimerName, pcTimerGetName( xTimer ) ) == 0 ); - configASSERT( xTimerGetPeriod( xTimer ) == x3ms ); - - /* Pend a function then wait for it to execute. All it does is increment - its parameter. */ - xTimerPendFunctionCall( prvPendedFunctionCall, &ulValueForTesting, 0, 0 ); - vTaskDelay( x3ms ); - configASSERT( ulValueForTesting == 1 ); - - /* Timer was created as a one-shot timer. Its callback just increments the - timer's ID - so set the ID to 0, let the timer run for a number of timeout - periods, then check the timer has only executed once. */ - vTimerSetTimerID( xTimer, ( void * ) 0 ); - xTimerStart( xTimer, 0 ); - vTaskDelay( 3UL * x3ms ); - configASSERT( ( ( uint32_t ) ( pvTimerGetTimerID( xTimer ) ) ) == 1UL ); - - /* Now change the timer to be an auto-reload timer and check it executes - the expected number of times. */ - vTimerSetReloadMode( xTimer, pdTRUE ); - xTimerStart( xTimer, 0 ); - vTaskDelay( 3UL * x3ms ); - configASSERT( ( uint32_t ) ( pvTimerGetTimerID( xTimer ) ) > 3UL ); - configASSERT( xTimerStop( xTimer, 0 ) != pdFAIL ); - - /* Clean up at the end. */ - xTimerDelete( xTimer, portMAX_DELAY ); + TimerHandle_t xTimer; + const char * const pcTimerName = "TestTimer"; + const TickType_t x3ms = pdMS_TO_TICKS( 3 ); + uint32_t ulValueForTesting = 0; + + xTimer = xTimerCreate( pcTimerName, + x3ms, + pdFALSE, /* Created as a one-shot timer. */ + 0, + prvTestTimerCallback ); + configASSERT( xTimer ); + configASSERT( xTimerIsTimerActive( xTimer ) == pdFALSE ); + configASSERT( xTimerGetTimerDaemonTaskHandle() != NULL ); + configASSERT( strcmp( pcTimerName, pcTimerGetName( xTimer ) ) == 0 ); + configASSERT( xTimerGetPeriod( xTimer ) == x3ms ); + + /* Pend a function then wait for it to execute. All it does is increment + * its parameter. */ + xTimerPendFunctionCall( prvPendedFunctionCall, &ulValueForTesting, 0, 0 ); + vTaskDelay( x3ms ); + configASSERT( ulValueForTesting == 1 ); + + /* Timer was created as a one-shot timer. Its callback just increments the + * timer's ID - so set the ID to 0, let the timer run for a number of timeout + * periods, then check the timer has only executed once. */ + vTimerSetTimerID( xTimer, ( void * ) 0 ); + xTimerStart( xTimer, 0 ); + vTaskDelay( 3UL * x3ms ); + configASSERT( ( ( uint32_t ) ( pvTimerGetTimerID( xTimer ) ) ) == 1UL ); + + /* Now change the timer to be an auto-reload timer and check it executes + * the expected number of times. */ + vTimerSetReloadMode( xTimer, pdTRUE ); + xTimerStart( xTimer, 0 ); + vTaskDelay( 3UL * x3ms ); + configASSERT( ( uint32_t ) ( pvTimerGetTimerID( xTimer ) ) > 3UL ); + configASSERT( xTimerStop( xTimer, 0 ) != pdFAIL ); + + /* Clean up at the end. */ + xTimerDelete( xTimer, portMAX_DELAY ); } /*-----------------------------------------------------------*/ static void prvExerciseStreamBufferAPI( void ) { -uint8_t ucBuffer[ 10 ]; -BaseType_t x, xRead; -size_t xReturned; -StreamBufferHandle_t xStreamBuffer; - - /* Just makes API calls to ensure the MPU versions are used. */ - - xStreamBuffer = xStreamBufferCreate( sizeof( ucBuffer ) , 1 ); - configASSERT( xStreamBuffer ); - - for( x = 0; x < ( sizeof( ucBuffer ) * 2 ); x++ ) - { - /* Write and check the value is written, then read and check the value - read is expected. */ - xReturned = xStreamBufferSend( xStreamBuffer, - ( void * ) &x, - sizeof( x ), - 0 ); - configASSERT( xReturned == sizeof( x ) ); - - xReturned = xStreamBufferReceive( xStreamBuffer, - ( void * ) &xRead, - sizeof( xRead ), - 0 ); - configASSERT( xReturned == sizeof( xRead ) ); - configASSERT( xRead == x ); - configASSERT( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); - configASSERT( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); - configASSERT( xStreamBufferSpacesAvailable( xStreamBuffer ) == sizeof( ucBuffer ) ); - configASSERT( xStreamBufferBytesAvailable( xStreamBuffer ) == 0 ); - } - - /* Call the functions that have not been exercised yet before finishing by - deleting the stream buffer. */ - configASSERT( xStreamBufferSetTriggerLevel( xStreamBuffer, 0 ) == pdTRUE ); - configASSERT( xStreamBufferReset( xStreamBuffer ) == pdPASS ); - vStreamBufferDelete( xStreamBuffer ); + uint8_t ucBuffer[ 10 ]; + BaseType_t x, xRead; + size_t xReturned; + StreamBufferHandle_t xStreamBuffer; + + /* Just makes API calls to ensure the MPU versions are used. */ + + xStreamBuffer = xStreamBufferCreate( sizeof( ucBuffer ), 1 ); + configASSERT( xStreamBuffer ); + + for( x = 0; x < ( sizeof( ucBuffer ) * 2 ); x++ ) + { + /* Write and check the value is written, then read and check the value + * read is expected. */ + xReturned = xStreamBufferSend( xStreamBuffer, + ( void * ) &x, + sizeof( x ), + 0 ); + configASSERT( xReturned == sizeof( x ) ); + + xReturned = xStreamBufferReceive( xStreamBuffer, + ( void * ) &xRead, + sizeof( xRead ), + 0 ); + configASSERT( xReturned == sizeof( xRead ) ); + configASSERT( xRead == x ); + configASSERT( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + configASSERT( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + configASSERT( xStreamBufferSpacesAvailable( xStreamBuffer ) == sizeof( ucBuffer ) ); + configASSERT( xStreamBufferBytesAvailable( xStreamBuffer ) == 0 ); + } + + /* Call the functions that have not been exercised yet before finishing by + * deleting the stream buffer. */ + configASSERT( xStreamBufferSetTriggerLevel( xStreamBuffer, 0 ) == pdTRUE ); + configASSERT( xStreamBufferReset( xStreamBuffer ) == pdPASS ); + vStreamBufferDelete( xStreamBuffer ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile const uint32_t *pul; -volatile uint32_t ulReadData; - - /* The idle task, and therefore this function, run in Supervisor mode and - can therefore access all memory. Try reading from corners of flash and - RAM to ensure a memory fault does not occur. - - Start with the edges of the privileged data area. */ - pul = __privileged_data_start__; - ulReadData = *pul; - pul = __privileged_data_end__ - 1; - ulReadData = *pul; - - /* Next the standard SRAM area. */ - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* And the standard Flash area - the start of which is marked for - privileged access only. */ - pul = __FLASH_segment_start__; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Reading off the end of Flash or SRAM space should cause a fault. - Uncomment one of the following two pairs of lines to test. */ - - /* pul = __FLASH_segment_end__ + 4; - ulReadData = *pul; */ - - /* pul = __SRAM_segment_end__ + 1; - ulReadData = *pul; */ - - /* One task is created purely so it can be deleted - done for code coverage - test purposes. */ - if( xTaskToDelete != NULL ) - { - if( eTaskGetState( xTaskToDelete ) == eSuspended ) - { - /* The task has finished its tests and can be deleted. */ - vTaskDelete( xTaskToDelete ); - xTaskToDelete = NULL; - } - } - - ( void ) ulReadData; + volatile const uint32_t * pul; + volatile uint32_t ulReadData; + + /* The idle task, and therefore this function, run in Supervisor mode and + * can therefore access all memory. Try reading from corners of flash and + * RAM to ensure a memory fault does not occur. + * + * Start with the edges of the privileged data area. */ + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Next the standard SRAM area. */ + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* And the standard Flash area - the start of which is marked for + * privileged access only. */ + pul = __FLASH_segment_start__; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading off the end of Flash or SRAM space should cause a fault. + * Uncomment one of the following two pairs of lines to test. */ + + /* pul = __FLASH_segment_end__ + 4; + * ulReadData = *pul; */ + + /* pul = __SRAM_segment_end__ + 1; + * ulReadData = *pul; */ + + /* One task is created purely so it can be deleted - done for code coverage + * test purposes. */ + if( xTaskToDelete != NULL ) + { + if( eTaskGetState( xTaskToDelete ) == eSuspended ) + { + /* The task has finished its tests and can be deleted. */ + vTaskDelete( xTaskToDelete ); + xTaskToDelete = NULL; + } + } + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ static void prvOldStyleUserModeTask( void ) { /*const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;*/ -volatile const uint32_t *pul; -volatile uint32_t ulReadData; + volatile const uint32_t * pul; + volatile uint32_t ulReadData; /* The following lines are commented out to prevent the unused variable -compiler warnings when the tests that use the variable are also commented out. */ + * compiler warnings when the tests that use the variable are also commented out. */ /* extern uint32_t __privileged_functions_start__[]; */ /* const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; */ - /* This task is created in User mode using the original xTaskCreate() API - function. It should have access to all Flash and RAM except that marked - as Privileged access only. Reading from the start and end of the non- - privileged RAM should not cause a problem (the privileged RAM is the first - block at the bottom of the RAM memory). */ - pul = __privileged_data_end__ + 1; - ulReadData = *pul; - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* Likewise reading from the start and end of the non-privileged Flash - should not be a problem (the privileged Flash is the first block at the - bottom of the Flash memory). */ - pul = __privileged_functions_end__ + 1; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Standard peripherals are accessible. */ - /*ulReadData = *pulStandardPeripheralRegister;*/ - - /* System peripherals are not accessible. Uncomment the following line - to test. Also uncomment the declaration of pulSystemPeripheralRegister - at the top of this function. - ulReadData = *pulSystemPeripheralRegister; */ - - /* Reading from anywhere inside the privileged Flash or RAM should cause a - fault. This can be tested by uncommenting any of the following pairs of - lines. Also uncomment the declaration of __privileged_functions_start__ - at the top of this function. */ - - /*pul = __privileged_functions_start__; - ulReadData = *pul;*/ - - /*pul = __privileged_functions_end__ - 1; - ulReadData = *pul;*/ - - /*pul = __privileged_data_start__; - ulReadData = *pul;*/ - - /*pul = __privileged_data_end__ - 1; - ulReadData = *pul;*/ - - ( void ) ulReadData; + /* This task is created in User mode using the original xTaskCreate() API + * function. It should have access to all Flash and RAM except that marked + * as Privileged access only. Reading from the start and end of the non- + * privileged RAM should not cause a problem (the privileged RAM is the first + * block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + * should not be a problem (the privileged Flash is the first block at the + * bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Standard peripherals are accessible. */ + /*ulReadData = *pulStandardPeripheralRegister;*/ + + /* System peripherals are not accessible. Uncomment the following line + * to test. Also uncomment the declaration of pulSystemPeripheralRegister + * at the top of this function. + * ulReadData = *pulSystemPeripheralRegister; */ + + /* Reading from anywhere inside the privileged Flash or RAM should cause a + * fault. This can be tested by uncommenting any of the following pairs of + * lines. Also uncomment the declaration of __privileged_functions_start__ + * at the top of this function. */ + + /*pul = __privileged_functions_start__; + * ulReadData = *pul;*/ + + /*pul = __privileged_functions_end__ - 1; + * ulReadData = *pul;*/ + + /*pul = __privileged_data_start__; + * ulReadData = *pul;*/ + + /*pul = __privileged_data_end__ - 1; + * ulReadData = *pul;*/ + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ -static void prvOldStylePrivilegedModeTask( void *pvParameters ) +static void prvOldStylePrivilegedModeTask( void * pvParameters ) { -volatile const uint32_t *pul; -volatile uint32_t ulReadData; -const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */ + volatile const uint32_t * pul; + volatile uint32_t ulReadData; + const volatile uint32_t * pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */ + /*const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;*/ - ( void ) pvParameters; - - /* This task is created in Privileged mode using the original xTaskCreate() - API function. It should have access to all Flash and RAM including that - marked as Privileged access only. So reading from the start and end of the - non-privileged RAM should not cause a problem (the privileged RAM is the - first block at the bottom of the RAM memory). */ - pul = __privileged_data_end__ + 1; - ulReadData = *pul; - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* Likewise reading from the start and end of the non-privileged Flash - should not be a problem (the privileged Flash is the first block at the - bottom of the Flash memory). */ - pul = __privileged_functions_end__ + 1; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Reading from anywhere inside the privileged Flash or RAM should also - not be a problem. */ - pul = __privileged_functions_start__; - ulReadData = *pul; - pul = __privileged_functions_end__ - 1; - ulReadData = *pul; - pul = __privileged_data_start__; - ulReadData = *pul; - pul = __privileged_data_end__ - 1; - ulReadData = *pul; - - /* Finally, accessing both System and normal peripherals should both be - possible. */ - ulReadData = *pulSystemPeripheralRegister; - /*ulReadData = *pulStandardPeripheralRegister;*/ - - /* Must not just run off the end of a task function, so delete this task. - Note that because this task was created using xTaskCreate() the stack was - allocated dynamically and I have not included any code to free it again. */ - vTaskDelete( NULL ); - - ( void ) ulReadData; + ( void ) pvParameters; + + /* This task is created in Privileged mode using the original xTaskCreate() + * API function. It should have access to all Flash and RAM including that + * marked as Privileged access only. So reading from the start and end of the + * non-privileged RAM should not cause a problem (the privileged RAM is the + * first block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + * should not be a problem (the privileged Flash is the first block at the + * bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading from anywhere inside the privileged Flash or RAM should also + * not be a problem. */ + pul = __privileged_functions_start__; + ulReadData = *pul; + pul = __privileged_functions_end__ - 1; + ulReadData = *pul; + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Finally, accessing both System and normal peripherals should both be + * possible. */ + ulReadData = *pulSystemPeripheralRegister; + /*ulReadData = *pulStandardPeripheralRegister;*/ + + /* Must not just run off the end of a task function, so delete this task. + * Note that because this task was created using xTaskCreate() the stack was + * allocated dynamically and I have not included any code to free it again. */ + vTaskDelete( NULL ); + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ void vMainDeleteMe( void ) { - vTaskDelete( NULL ); + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber ) +void vMainSendImAlive( QueueHandle_t xHandle, + uint32_t ulTaskNumber ) { - if( xHandle != NULL ) - { - xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); - } + if( xHandle != NULL ) + { + xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ @@ -1112,158 +1133,167 @@ static void prvSetupHardware( void ) void vApplicationTickHook( void ) { -static uint32_t ulCallCount = 0; -const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 1000 ); -const uint32_t ulMessage = configPRINT_SYSTEM_STATUS; -portBASE_TYPE xDummy; - - /* If configUSE_TICK_HOOK is set to 1 then this function will get called - from each RTOS tick. It is called from the tick interrupt and therefore - will be executing in the privileged state. */ - - ulCallCount++; - - /* Is it time to print out the pass/fail message again? */ - if( ulCallCount >= ulCallsBetweenSends ) - { - ulCallCount = 0; - - /* Send a message to the check task to command it to check that all - the tasks are still running then print out the status. - - This is running in an ISR so has to use the "FromISR" version of - xQueueSend(). Because it is in an ISR it is running with privileges - so can access xGlobalScopeCheckQueue directly. */ - xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy ); - } + static uint32_t ulCallCount = 0; + const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 1000 ); + const uint32_t ulMessage = configPRINT_SYSTEM_STATUS; + portBASE_TYPE xDummy; + + /* If configUSE_TICK_HOOK is set to 1 then this function will get called + * from each RTOS tick. It is called from the tick interrupt and therefore + * will be executing in the privileged state. */ + + ulCallCount++; + + /* Is it time to print out the pass/fail message again? */ + if( ulCallCount >= ulCallsBetweenSends ) + { + ulCallCount = 0; + + /* Send a message to the check task to command it to check that all + * the tasks are still running then print out the status. + * + * This is running in an ISR so has to use the "FromISR" version of + * xQueueSend(). Because it is in an ISR it is running with privileges + * so can access xGlobalScopeCheckQueue directly. */ + xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy ); + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this - function will automatically get called if a task overflows its stack. */ - ( void ) pxTask; - ( void ) pcTaskName; - for( ;; ); + /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this + * function will automatically get called if a task overflows its stack. */ + ( void ) pxTask; + ( void ) pcTaskName; + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will - be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() - is called automatically when a task, queue or semaphore is created. */ - for( ;; ); + /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will + * be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() + * is called automatically when a task, queue or semaphore is created. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvTimerCallback( TimerHandle_t xExpiredTimer ) { -uint32_t ulCount; + uint32_t ulCount; - /* The count of the number of times this timer has expired is saved in the - timer's ID. Obtain the current count. */ - ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer ); + /* The count of the number of times this timer has expired is saved in the + * timer's ID. Obtain the current count. */ + ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer ); - /* Increment the count, and save it back into the timer's ID. */ - ulCount++; - vTimerSetTimerID( xTimer, ( void * ) ulCount ); + /* Increment the count, and save it back into the timer's ID. */ + ulCount++; + vTimerSetTimerID( xTimer, ( void * ) ulCount ); - /* Let the check task know the timer is still running. */ - vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING ); + /* Let the check task know the timer is still running. */ + vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING ); } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ -static void prvRegTest3Task( void *pvParameters ) +static void prvRegTest3Task( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == configREG_TEST_TASK_3_PARAMETER ) - { - /* Run the unprivileged mode access tests that used to be executed - form an unprivileged task created using the xTaskCreate() API. - Since the heap moved to the privileged data section xTaskCreate() can - no longer be used to create unprivileged tasks. */ - prvOldStyleUserModeTask(); - - /* Start the part of the test that is written in assembler. */ - vRegTest3Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == configREG_TEST_TASK_3_PARAMETER ) + { + /* Run the unprivileged mode access tests that used to be executed + * form an unprivileged task created using the xTaskCreate() API. + * Since the heap moved to the privileged data section xTaskCreate() can + * no longer be used to create unprivileged tasks. */ + prvOldStyleUserModeTask(); + + /* Start the part of the test that is written in assembler. */ + vRegTest3Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -static void prvRegTest4Task( void *pvParameters ) +static void prvRegTest4Task( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == configREG_TEST_TASK_4_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest4Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == configREG_TEST_TASK_4_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest4Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/.gitignore new file mode 100644 index 00000000000..3f2767e0c3e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/.gitignore @@ -0,0 +1,4 @@ +Listings/ +Objects/ +EventRecorderStub.scvd +*.uvguix.* diff --git a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/FreeRTOSConfig.h index 3a460f9cbe3..1f9d6553c75 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -145,6 +145,9 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Set configUSE_MPU_WRAPPERS_V1 to 0 to use new MPU wrapper. * See https://freertos.org/a00110.html#configUSE_MPU_WRAPPERS_V1 for details. */ #define configUSE_MPU_WRAPPERS_V1 ( 0 ) +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to use access control list. + * See https://freertos.org/a00110.html#configENABLE_ACCESS_CONTROL_LIST for details. */ +#define configENABLE_ACCESS_CONTROL_LIST ( 1 ) /* See https://freertos.org/a00110.html#configPROTECTED_KERNEL_OBJECT_POOL_SIZE for details. */ #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE ( 150 ) /* See https://freertos.org/a00110.html#configSYSTEM_CALL_STACK_SIZE for details. */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/GCC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/GCC_Specific/RegTest.c index 57412954d1c..06a1c6b54b9 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/GCC_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/GCC_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx index 7181cca8ab4..5c5d0df8dbe 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx @@ -10,7 +10,7 @@ RTOSDemo 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::..\..\Program Files (x86)\ARM_Compiler_5.06u7 + 5060960::V5.06 update 7 (build 960)::.\ARM_Compiler_5.06u7 0 @@ -458,6 +458,57 @@ mpu_wrappers_v2.c 1 ..\..\..\Source\portable\Common\mpu_wrappers_v2.c + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --diag_suppress=1296 + + + + + + + stream_buffer.c diff --git a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RegTest.c index 0821c57f703..c9cae6af16a 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/RegTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/main.c index dcc952cd47e..b85440d9e41 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -53,22 +53,22 @@ /*-----------------------------------------------------------*/ /* Misc constants. */ -#define mainDONT_BLOCK ( 0 ) +#define mainDONT_BLOCK ( 0 ) /* GCC specifics. */ -#define mainALIGN_TO( x ) __attribute__((aligned(x))) +#define mainALIGN_TO( x ) __attribute__( ( aligned( x ) ) ) /* Hardware register addresses. */ -#define mainVTOR ( * ( volatile uint32_t * ) 0xE000ED08 ) +#define mainVTOR ( *( volatile uint32_t * ) 0xE000ED08 ) /* The period of the timer must be less than the rate at which -configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the -check task will think the timer has stopped. */ -#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 ) + * configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the + * check task will think the timer has stopped. */ +#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 ) /* The name of the task that is deleted by the Idle task is used in a couple of -places, so is #defined. */ -#define mainTASK_TO_DELETE_NAME "DeleteMe" + * places, so is #defined. */ +#define mainTASK_TO_DELETE_NAME "DeleteMe" /*-----------------------------------------------------------*/ /* Prototypes for functions that implement tasks. -----------*/ @@ -96,8 +96,8 @@ places, so is #defined. */ * User mode, and vRegTest2Implementation() receives the task handle using its * parameter. */ -extern void vRegTest1Implementation( void *pvParameters ); -extern void vRegTest2Implementation( void *pvParameters ); +extern void vRegTest1Implementation( void * pvParameters ); +extern void vRegTest2Implementation( void * pvParameters ); /* * The second two register test tasks are similar to the first two, but do test @@ -113,9 +113,9 @@ extern void vRegTest2Implementation( void *pvParameters ); */ static StackType_t xRegTest3Stack[ configMINIMAL_STACK_SIZE ], xRegTest4Stack[ configMINIMAL_STACK_SIZE ]; static StaticTask_t xRegTest3Buffer, xRegTest4Buffer; -static void prvRegTest3Task( void *pvParameters ); +static void prvRegTest3Task( void * pvParameters ); extern void vRegTest3Implementation( void ); -static void prvRegTest4Task( void *pvParameters ); +static void prvRegTest4Task( void * pvParameters ); extern void vRegTest4Implementation( void ); /* @@ -133,7 +133,7 @@ extern void vRegTest4Implementation( void ); * either pass or fail to the terminal, depending on the status of the reg * test tasks (no write is performed in the simulator!). */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); /* * Prototype for a task created in User mode using the original vTaskCreate() @@ -145,7 +145,7 @@ static void prvCheckTask( void *pvParameters ); * this function are now called from an unprivileged register check task created * using the xTaskCreateRestricted() API. */ -static void prvOldStyleUserModeTask( void ); +static void prvOldStyleUserModeTask( void ); /* * Prototype for a task created in Privileged mode using the @@ -157,13 +157,13 @@ static void prvOldStyleUserModeTask( void ); */ static PRIVILEGED_DATA StackType_t xPrivilegedModeTaskStack[ configMINIMAL_STACK_SIZE ]; static PRIVILEGED_DATA StaticTask_t xPrivilegedModeTaskBuffer; -static void prvOldStylePrivilegedModeTask( void *pvParameters ); +static void prvOldStylePrivilegedModeTask( void * pvParameters ); /* * A task that exercises the API of various RTOS objects before being deleted by * the Idle task. This is done for MPU API code coverage test purposes. */ -static void prvTaskToDelete( void *pvParameters ); +static void prvTaskToDelete( void * pvParameters ); /* * Functions called by prvTaskToDelete() to exercise the MPU API. @@ -182,7 +182,7 @@ static void prvSetupHardware( void ); * is simpler to call from asm code than the normal vTaskDelete() API function. * It has the noinline attribute because it is called from asm code. */ -void vMainDeleteMe( void ) __attribute__((noinline)); +void vMainDeleteMe( void ) __attribute__( ( noinline ) ); /* * Used by the first two reg test tasks and a software timer callback function @@ -191,7 +191,8 @@ void vMainDeleteMe( void ) __attribute__((noinline)); * task detects an error it will delete itself, and in so doing prevent itself * from sending any more 'I'm Alive' messages to the check task. */ -void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber ); +void vMainSendImAlive( QueueHandle_t xHandle, + uint32_t ulTaskNumber ); /* * The check task is created with access to three memory regions (plus its @@ -212,130 +213,130 @@ static void prvTimerCallback( TimerHandle_t xExpiredTimer ); /*-----------------------------------------------------------*/ /* The handle of the queue used to communicate between tasks and between tasks -and interrupts. Note that this is a global scope variable that falls outside of -any MPU region. As such other techniques have to be used to allow the tasks -to gain access to the queue. See the comments in the tasks themselves for -further information. */ + * and interrupts. Note that this is a global scope variable that falls outside of + * any MPU region. As such other techniques have to be used to allow the tasks + * to gain access to the queue. See the comments in the tasks themselves for + * further information. */ QueueHandle_t xGlobalScopeCheckQueue = NULL; /* xGlobalScopeCheckQueue is created using xQueueCreateStatic(), so the storage -area and variable used to hold the queue data structure must also be provided. -These are placed in a prviliged segment. */ + * area and variable used to hold the queue data structure must also be provided. + * These are placed in a prviliged segment. */ static PRIVILEGED_DATA StaticQueue_t xGlobalScopeQueueBuffer; uint8_t PRIVILEGED_DATA ucGlobalScopeQueueStorageArea[ 1 * sizeof( uint32_t ) ]; /* Holds the handle of a task that is deleted in the idle task hook - this is -done for code coverage test purposes only. */ + * done for code coverage test purposes only. */ static TaskHandle_t xTaskToDelete = NULL; /* The timer that periodically sends data to the check task on the queue. This -is created with xTimerCreateStatic(), so the variable in which the timer's data -structure will be stored must also be provided. The structure is placed in the -kernel's privileged data region. */ + * is created with xTimerCreateStatic(), so the variable in which the timer's data + * structure will be stored must also be provided. The structure is placed in the + * kernel's privileged data region. */ static TimerHandle_t xTimer = NULL; static PRIVILEGED_DATA StaticTimer_t xTimerBuffer; -#if defined ( __GNUC__ ) - extern uint32_t __FLASH_segment_start__[]; - extern uint32_t __FLASH_segment_end__[]; - extern uint32_t __SRAM_segment_start__[]; - extern uint32_t __SRAM_segment_end__[]; - extern uint32_t __privileged_functions_start__[]; - extern uint32_t __privileged_functions_end__[]; - extern uint32_t __privileged_data_start__[]; - extern uint32_t __privileged_data_end__[]; - extern uint32_t __privileged_functions_actual_end__[]; - extern uint32_t __privileged_data_actual_end__[]; -#else - extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; - extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; - - const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x00000000UL; - const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x00080000UL; - const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000UL; - const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20008000UL; - const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x00000000UL; - const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x00010000UL; - const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); - const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); - const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000UL; - const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20004000UL; -#endif +#if defined( __GNUC__ ) + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + extern uint32_t __privileged_functions_actual_end__[]; + extern uint32_t __privileged_data_actual_end__[]; +#else /* if defined( __GNUC__ ) */ + extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; + extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; + + const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x00000000UL; + const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x00080000UL; + const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000UL; + const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20008000UL; + const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x00000000UL; + const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x00010000UL; + const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); + const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); + const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000UL; + const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20004000UL; +#endif /* if defined( __GNUC__ ) */ /*-----------------------------------------------------------*/ /* Data used by the 'check' task. ---------------------------*/ /*-----------------------------------------------------------*/ /* Define the constants used to allocate the check task stack. Note that the -stack size is defined in words, not bytes. */ -#define mainCHECK_TASK_STACK_SIZE_WORDS 128 -#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * stack size is defined in words, not bytes. */ +#define mainCHECK_TASK_STACK_SIZE_WORDS 128 +#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stack that will be used by the check task. The kernel will -automatically create an MPU region for the stack. The stack alignment must -match its size, so if 128 words are reserved for the stack then it must be -aligned to ( 128 * 4 ) bytes. */ + * automatically create an MPU region for the stack. The stack alignment must + * match its size, so if 128 words are reserved for the stack then it must be + * aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainCHECK_TASK_STACK_ALIGNMENT ); /* Declare the variable in which the check task's data structures will be -stored. PRIVILEGED_DATA is used to place this in the kernel's RAM segment. */ + * stored. PRIVILEGED_DATA is used to place this in the kernel's RAM segment. */ static PRIVILEGED_DATA StaticTask_t xCheckTaskBuffer; /* Declare three arrays - an MPU region will be created for each array -using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE -MPU FUNCTIONALITY, the data is not used by the check tasks primary function -of monitoring the reg test tasks and printing out status information. - -Note that the arrays allocate slightly more RAM than is actually assigned to -the MPU region. This is to permit writes off the end of the array to be -detected even when the arrays are placed in adjacent memory locations (with no -gaps between them). The align size must be a power of two. */ -#define mainREAD_WRITE_ARRAY_SIZE 130 -#define mainREAD_WRITE_ALIGN_SIZE 128 + * using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE + * MPU FUNCTIONALITY, the data is not used by the check tasks primary function + * of monitoring the reg test tasks and printing out status information. + * + * Note that the arrays allocate slightly more RAM than is actually assigned to + * the MPU region. This is to permit writes off the end of the array to be + * detected even when the arrays are placed in adjacent memory locations (with no + * gaps between them). The align size must be a power of two. */ +#define mainREAD_WRITE_ARRAY_SIZE 130 +#define mainREAD_WRITE_ALIGN_SIZE 128 char cReadWriteArray[ mainREAD_WRITE_ARRAY_SIZE ] mainALIGN_TO( mainREAD_WRITE_ALIGN_SIZE ); -#define mainREAD_ONLY_ARRAY_SIZE 260 -#define mainREAD_ONLY_ALIGN_SIZE 256 +#define mainREAD_ONLY_ARRAY_SIZE 260 +#define mainREAD_ONLY_ALIGN_SIZE 256 char cReadOnlyArray[ mainREAD_ONLY_ARRAY_SIZE ] mainALIGN_TO( mainREAD_ONLY_ALIGN_SIZE ); -#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 -#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 +#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130 +#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128 char cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] mainALIGN_TO( mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ); /* The following two variables are used to communicate the status of the second -two register check tasks (tasks 3 and 4) to the check task. If the variables -keep incrementing, then the register check tasks have not discovered any errors. -If a variable stops incrementing, then an error has been found. The variables -overlay the array that the check task has access to so they can be read by the -check task without causing a memory fault. The check task has the highest -priority so will have finished with the array before the register test tasks -start to access it. */ -volatile uint32_t *pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); + * two register check tasks (tasks 3 and 4) to the check task. If the variables + * keep incrementing, then the register check tasks have not discovered any errors. + * If a variable stops incrementing, then an error has been found. The variables + * overlay the array that the check task has access to so they can be read by the + * check task without causing a memory fault. The check task has the highest + * priority so will have finished with the array before the register test tasks + * start to access it. */ +volatile uint32_t * pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), * pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); /* Fill in a TaskParameters_t structure to define the check task - this is the -structure passed to the xTaskCreateRestricted() function. */ + * structure passed to the xTaskCreateRestricted() function. */ static const TaskParameters_t xCheckTaskParameters = { - prvCheckTask, /* pvTaskCode - the function that implements the task. */ - "Check", /* pcName */ - mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ - ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT,/* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ - xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - - /* xRegions - In this case the xRegions array is used to create MPU regions - for all three of the arrays declared directly above. Each MPU region is - created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE - MPU FUNCTIONALITY, the data is not used by the check tasks primary function - of monitoring the reg test tasks and printing out status information.*/ - { - /* Base address Length Parameters */ - { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, - { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, - { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } - }, - - &xCheckTaskBuffer /* Additional structure member present when the task is being created without any dynamic memory allocation. */ + prvCheckTask, /* pvTaskCode - the function that implements the task. */ + "Check", /* pcName */ + mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */ + ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */ + xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + + /* xRegions - In this case the xRegions array is used to create MPU regions + * for all three of the arrays declared directly above. Each MPU region is + * created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE + * MPU FUNCTIONALITY, the data is not used by the check tasks primary function + * of monitoring the reg test tasks and printing out status information.*/ + { + /* Base address Length Parameters */ + { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE }, + { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY }, + { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE } + }, + + &xCheckTaskBuffer /* Additional structure member present when the task is being created without any dynamic memory allocation. */ }; @@ -344,58 +345,58 @@ static const TaskParameters_t xCheckTaskParameters = /*-----------------------------------------------------------*/ /* Define the constants used to allocate the reg test task stacks. Note that -that stack size is defined in words, not bytes. */ -#define mainREG_TEST_STACK_SIZE_WORDS 128 -#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * that stack size is defined in words, not bytes. */ +#define mainREG_TEST_STACK_SIZE_WORDS 128 +#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stacks that will be used by the reg test tasks. The kernel will -automatically create an MPU region for the stack. The stack alignment must -match its size, so if 128 words are reserved for the stack then it must be -aligned to ( 128 * 4 ) bytes. */ + * automatically create an MPU region for the stack. The stack alignment must + * match its size, so if 128 words are reserved for the stack then it must be + * aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xRegTest1Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); static portSTACK_TYPE xRegTest2Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT ); /* The reg test tasks are created using the xTaskCreateRestrictedStatic() API -function, so variables that hold the task's data structures must also be -provided. The are placed in the kernel's privileged memory section. */ + * function, so variables that hold the task's data structures must also be + * provided. The are placed in the kernel's privileged memory section. */ static PRIVILEGED_DATA StaticTask_t xRegTest1TaskBuffer, xRegTest2TaskBuffer; /* Fill in a TaskParameters_t structure per reg test task to define the tasks. */ static const TaskParameters_t xRegTest1Parameters = { - vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */ - "RegTest1", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ - tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ - xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - }, - - &xRegTest1TaskBuffer /* Additional parameter required when the task is created with xTaskCreateRestrictedStatic(). */ + vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */ + "RegTest1", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */ + tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */ + xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + }, + + &xRegTest1TaskBuffer /* Additional parameter required when the task is created with xTaskCreateRestrictedStatic(). */ }; /*-----------------------------------------------------------*/ static TaskParameters_t xRegTest2Parameters = { - vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */ - "RegTest2", /* pcName */ - mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ - tskIDLE_PRIORITY, /* uxPriority */ - xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - }, - - &xRegTest2TaskBuffer /* Additional parameter required when the task is created with xTaskCreateRestrictedStatic(). */ + vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */ + "RegTest2", /* pcName */ + mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + tskIDLE_PRIORITY, /* uxPriority */ + xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + }, + + &xRegTest2TaskBuffer /* Additional parameter required when the task is created with xTaskCreateRestrictedStatic(). */ }; /*-----------------------------------------------------------*/ @@ -403,37 +404,37 @@ static TaskParameters_t xRegTest2Parameters = /*-----------------------------------------------------------*/ /* Define the constants used to allocate the stack of the task that is -deleted. Note that the stack size is defined in words, not bytes. */ -#define mainDELETE_TASK_STACK_SIZE_WORDS 128 -#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) + * deleted. Note that the stack size is defined in words, not bytes. */ +#define mainDELETE_TASK_STACK_SIZE_WORDS 128 +#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) ) /* Declare the stack that will be used by the task that gets deleted. The -kernel will automatically create an MPU region for the stack. The stack -alignment must match its size, so if 128 words are reserved for the stack -then it must be aligned to ( 128 * 4 ) bytes. */ + * kernel will automatically create an MPU region for the stack. The stack + * alignment must match its size, so if 128 words are reserved for the stack + * then it must be aligned to ( 128 * 4 ) bytes. */ static portSTACK_TYPE xDeleteTaskStack[ mainDELETE_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainTASK_TO_DELETE_STACK_ALIGNMENT ); /* The task that gets deleted is created using xTaskCreateRestrictedStatic(), -so the variable that stores the task's data structure must also be provided. -This is placed in the kernel's privileged data segment. */ + * so the variable that stores the task's data structure must also be provided. + * This is placed in the kernel's privileged data segment. */ static PRIVILEGED_DATA StaticTask_t xStaticDeleteTaskBuffer; static TaskParameters_t xTaskToDeleteParameters = { - prvTaskToDelete, /* pvTaskCode - the function that implements the task. */ - mainTASK_TO_DELETE_NAME, /* pcName */ - mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */ - ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ - ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this task is privileged because it creates and deletes kernel objects. */ - xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ - { /* xRegions - this task does not use any non-stack data hence all members are zero. */ - /* Base address Length Parameters */ - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00 } - }, - - &xStaticDeleteTaskBuffer /* Additional parameter required when xTaskCreateRestrictedStatic() is used. */ + prvTaskToDelete, /* pvTaskCode - the function that implements the task. */ + mainTASK_TO_DELETE_NAME, /* pcName */ + mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */ + ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */ + ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT, /* uxPriority - this task is privileged because it creates and deletes kernel objects. */ + xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */ + { /* xRegions - this task does not use any non-stack data hence all members are zero. */ + /* Base address Length Parameters */ + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00 } + }, + + &xStaticDeleteTaskBuffer /* Additional parameter required when xTaskCreateRestrictedStatic() is used. */ }; /*-----------------------------------------------------------*/ @@ -442,544 +443,561 @@ volatile uint32_t ul1 = 0x123, ul2 = 0; int main( void ) { - configASSERT( ul1 == 0x123 ); - configASSERT( ul2 == 0 ); - prvSetupHardware(); - - /* Create the queue used to pass "I'm alive" messages to the check task. */ - xGlobalScopeCheckQueue = xQueueCreateStatic( 1, sizeof( uint32_t ), ucGlobalScopeQueueStorageArea, &xGlobalScopeQueueBuffer ); - - /* One check task uses the task parameter to receive the queue handle. - This allows the file scope variable to be accessed from within the task. - The pvParameters member of xRegTest2Parameters can only be set after the - queue has been created so is set here. */ - xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue; - - /* Create three test tasks. Handles to the created tasks are not required, - hence the second parameter is NULL. */ - xTaskCreateRestrictedStatic( &xRegTest1Parameters, NULL ); - xTaskCreateRestrictedStatic( &xRegTest2Parameters, NULL ); - xTaskCreateRestrictedStatic( &xCheckTaskParameters, NULL ); - - /* Create a task that does nothing but ensure some of the MPU API functions - can be called correctly, then get deleted. This is done for code coverage - test purposes only. The task's handle is saved in xTaskToDelete so it can - get deleted in the idle task hook. */ - xTaskCreateRestrictedStatic( &xTaskToDeleteParameters, &xTaskToDelete ); - - /* Create the tasks that are created using the original xTaskCreate() API - function. */ - xTaskCreateStatic( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ - "Task2", /* Text name for the task. */ - 100, /* Stack depth in words. */ - NULL, /* Task parameters. */ - ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ - xPrivilegedModeTaskStack, /* Used as the task's stack. */ - &xPrivilegedModeTaskBuffer /* Used to hold the task's data structure. */ - ); - - /* Create the third and fourth register check tasks, as described at the top - of this file. */ - xTaskCreateStatic( prvRegTest3Task, "Reg3", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_3_PARAMETER, tskIDLE_PRIORITY, xRegTest3Stack, &xRegTest3Buffer ); - xTaskCreateStatic( prvRegTest4Task, "Reg4", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_4_PARAMETER, tskIDLE_PRIORITY, xRegTest4Stack, &xRegTest4Buffer ); - - /* Create and start the software timer. */ - xTimer = xTimerCreateStatic( "Timer", /* Test name for the timer. */ - mainTIMER_PERIOD, /* Period of the timer. */ - pdTRUE, /* The timer will auto-reload itself. */ - ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */ - prvTimerCallback, /* The function called when the timer expires. */ - &xTimerBuffer ); /* The variable in which the created timer's data structure will be stored. */ - configASSERT( xTimer ); - xTimerStart( xTimer, mainDONT_BLOCK ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient memory to create the idle - task. */ - for( ;; ); + TaskHandle_t xRegTest1TaskHandle, xRegTest2TaskHandle, xCheckTaskHandle; + + configASSERT( ul1 == 0x123 ); + configASSERT( ul2 == 0 ); + prvSetupHardware(); + + /* Create the queue used to pass "I'm alive" messages to the check task. */ + xGlobalScopeCheckQueue = xQueueCreateStatic( 1, sizeof( uint32_t ), ucGlobalScopeQueueStorageArea, &xGlobalScopeQueueBuffer ); + + /* One check task uses the task parameter to receive the queue handle. + * This allows the file scope variable to be accessed from within the task. + * The pvParameters member of xRegTest2Parameters can only be set after the + * queue has been created so is set here. */ + xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue; + + /* Create three test tasks. */ + xTaskCreateRestrictedStatic( &xRegTest1Parameters, &( xRegTest1TaskHandle ) ); + xTaskCreateRestrictedStatic( &xRegTest2Parameters, &( xRegTest2TaskHandle ) ); + xTaskCreateRestrictedStatic( &xCheckTaskParameters, &( xCheckTaskHandle ) ); + + vGrantAccessToQueue( xRegTest1TaskHandle, xGlobalScopeCheckQueue ); + vGrantAccessToQueue( xRegTest2TaskHandle, xGlobalScopeCheckQueue ); + vGrantAccessToQueue( xCheckTaskHandle, xGlobalScopeCheckQueue ); + + /* Create a task that does nothing but ensure some of the MPU API functions + * can be called correctly, then get deleted. This is done for code coverage + * test purposes only. The task's handle is saved in xTaskToDelete so it can + * get deleted in the idle task hook. */ + xTaskCreateRestrictedStatic( &xTaskToDeleteParameters, &xTaskToDelete ); + + /* Create the tasks that are created using the original xTaskCreate() API + * function. */ + xTaskCreateStatic( prvOldStylePrivilegedModeTask, /* The function that implements the task. */ + "Task2", /* Text name for the task. */ + 100, /* Stack depth in words. */ + NULL, /* Task parameters. */ + ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */ + xPrivilegedModeTaskStack, /* Used as the task's stack. */ + &xPrivilegedModeTaskBuffer /* Used to hold the task's data structure. */ + ); + + /* Create the third and fourth register check tasks, as described at the top + * of this file. */ + xTaskCreateStatic( prvRegTest3Task, "Reg3", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_3_PARAMETER, tskIDLE_PRIORITY, xRegTest3Stack, &xRegTest3Buffer ); + xTaskCreateStatic( prvRegTest4Task, "Reg4", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_4_PARAMETER, tskIDLE_PRIORITY, xRegTest4Stack, &xRegTest4Buffer ); + + /* Create and start the software timer. */ + xTimer = xTimerCreateStatic( "Timer", /* Test name for the timer. */ + mainTIMER_PERIOD, /* Period of the timer. */ + pdTRUE, /* The timer will auto-reload itself. */ + ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */ + prvTimerCallback, /* The function called when the timer expires. */ + &xTimerBuffer ); /* The variable in which the created timer's data structure will be stored. */ + configASSERT( xTimer ); + xTimerStart( xTimer, mainDONT_BLOCK ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + * task. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { /* This task is created in privileged mode so can access the file scope -queue variable. Take a stack copy of this before the task is set into user -mode. Once that task is in user mode the file scope queue variable will no -longer be accessible but the stack copy will. */ -QueueHandle_t xQueue = xGlobalScopeCheckQueue; -int32_t lMessage; -uint32_t ulStillAliveCounts[ 3 ] = { 0 }; -const char *pcStatusMessage = "PASS\r\n"; -uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0; + * queue variable. Take a stack copy of this before the task is set into user + * mode. Once that task is in user mode the file scope queue variable will no + * longer be accessible but the stack copy will. */ + QueueHandle_t xQueue = xGlobalScopeCheckQueue; + int32_t lMessage; + uint32_t ulStillAliveCounts[ 3 ] = { 0 }; + const char * pcStatusMessage = "PASS\r\n"; + uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0; /* The register test tasks that also test the floating point registers increment -a counter on each iteration of their loop. The counters are inside the array -that this task has access to. */ -volatile uint32_t *pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); + * a counter on each iteration of their loop. The counters are inside the array + * that this task has access to. */ + volatile uint32_t * pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), * pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] ); /* ulCycleCount is incremented on each cycle of the check task. It can be -viewed updating in the Keil watch window as the simulator does not print to -the ITM port. */ -volatile uint32_t ulCycleCount = 0; - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* Demonstrate how the various memory regions can and can't be accessed. - The task privilege level is set down to user mode within this function. */ - prvTestMemoryRegions(); - - /* Clear overlaid reg test counters before entering the loop below. */ - *pulOverlaidCounter3 = 0UL; - *pulOverlaidCounter4 = 0UL; - - /* This loop performs the main function of the task, which is blocking - on a message queue then processing each message as it arrives. */ - for( ;; ) - { - /* Wait for the next message to arrive. */ - xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); - - switch( lMessage ) - { - case configREG_TEST_1_STILL_EXECUTING : - case configREG_TEST_2_STILL_EXECUTING : - case configTIMER_STILL_EXECUTING : - /* Message from the first or second register check task, or - the timer callback function. Increment the count of the - number of times the message source has sent the message as - the message source must still be executed. */ - ( ulStillAliveCounts[ lMessage ] )++; - break; - - case configPRINT_SYSTEM_STATUS : - /* Message from tick hook, time to print out the system - status. If messages have stopped arriving from either of - the first two reg test task or the timer callback then the - status must be set to fail. */ - if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) ) - { - /* One or both of the test tasks are no longer sending - 'still alive' messages. */ - pcStatusMessage = "FAIL\r\n"; - } - else - { - /* Reset the count of 'still alive' messages. */ - memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); - } - - /* Check that the register test 3 task is still incrementing - its counter, and therefore still running. */ - if( ulLastRegTest3CountValue == *pulOverlaidCounter3 ) - { - pcStatusMessage = "FAIL\r\n"; - } - ulLastRegTest3CountValue = *pulOverlaidCounter3; - - /* Check that the register test 4 task is still incrementing - its counter, and therefore still running. */ - if( ulLastRegTest4Value == *pulOverlaidCounter4 ) - { - pcStatusMessage = "FAIL\r\n"; - } - ulLastRegTest4Value = *pulOverlaidCounter4; - - /**** Print pcStatusMessage here. ****/ - ( void ) pcStatusMessage; - - /* The cycle count can be viewed updating in the Keil watch - window if ITM printf is not being used. */ - ulCycleCount++; - break; - - default : - /* Something unexpected happened. Delete this task so the - error is apparent (no output will be displayed). */ - vMainDeleteMe(); - break; - } - } + * viewed updating in the Keil watch window as the simulator does not print to + * the ITM port. */ + volatile uint32_t ulCycleCount = 0; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* Demonstrate how the various memory regions can and can't be accessed. + * The task privilege level is set down to user mode within this function. */ + prvTestMemoryRegions(); + + /* Clear overlaid reg test counters before entering the loop below. */ + *pulOverlaidCounter3 = 0UL; + *pulOverlaidCounter4 = 0UL; + + /* This loop performs the main function of the task, which is blocking + * on a message queue then processing each message as it arrives. */ + for( ; ; ) + { + /* Wait for the next message to arrive. */ + xQueueReceive( xQueue, &lMessage, portMAX_DELAY ); + + switch( lMessage ) + { + case configREG_TEST_1_STILL_EXECUTING: + case configREG_TEST_2_STILL_EXECUTING: + case configTIMER_STILL_EXECUTING: + + /* Message from the first or second register check task, or + * the timer callback function. Increment the count of the + * number of times the message source has sent the message as + * the message source must still be executed. */ + ( ulStillAliveCounts[ lMessage ] )++; + break; + + case configPRINT_SYSTEM_STATUS: + + /* Message from tick hook, time to print out the system + * status. If messages have stopped arriving from either of + * the first two reg test task or the timer callback then the + * status must be set to fail. */ + if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) ) + { + /* One or both of the test tasks are no longer sending + * 'still alive' messages. */ + pcStatusMessage = "FAIL\r\n"; + } + else + { + /* Reset the count of 'still alive' messages. */ + memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) ); + } + + /* Check that the register test 3 task is still incrementing + * its counter, and therefore still running. */ + if( ulLastRegTest3CountValue == *pulOverlaidCounter3 ) + { + pcStatusMessage = "FAIL\r\n"; + } + + ulLastRegTest3CountValue = *pulOverlaidCounter3; + + /* Check that the register test 4 task is still incrementing + * its counter, and therefore still running. */ + if( ulLastRegTest4Value == *pulOverlaidCounter4 ) + { + pcStatusMessage = "FAIL\r\n"; + } + + ulLastRegTest4Value = *pulOverlaidCounter4; + + /**** Print pcStatusMessage here. ****/ + ( void ) pcStatusMessage; + + /* The cycle count can be viewed updating in the Keil watch + * window if ITM printf is not being used. */ + ulCycleCount++; + break; + + default: + + /* Something unexpected happened. Delete this task so the + * error is apparent (no output will be displayed). */ + vMainDeleteMe(); + break; + } + } } /*-----------------------------------------------------------*/ static void prvTestMemoryRegions( void ) { -int32_t x; -char cTemp; - - /* The check task (from which this function is called) is created in the - Privileged mode. The privileged array can be both read from and written - to while this task is privileged. */ - cPrivilegedOnlyAccessArray[ 0 ] = 'a'; - if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) - { - /* Something unexpected happened. Delete this task so the error is - apparent (no output will be displayed). */ - vMainDeleteMe(); - } - - /* Writing off the end of the RAM allocated to this task will *NOT* cause a - protection fault because the task is still executing in a privileged mode. - Uncomment the following to test. */ - /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ - - /* Now set the task into user mode. */ - portSWITCH_TO_USER_MODE(); - - /* Accessing the privileged only array will now cause a fault. Uncomment - the following line to test. */ - /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ - - /* The read/write array can still be successfully read and written. */ - for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ ) - { - cReadWriteArray[ x ] = 'a'; - if( cReadWriteArray[ x ] != 'a' ) - { - /* Something unexpected happened. Delete this task so the error is - apparent (no output will be displayed). */ - vMainDeleteMe(); - } - } - - /* But attempting to read or write off the end of the RAM allocated to this - task will cause a fault. Uncomment either of the following two lines to - test. */ - /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ - /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ - - /* The read only array can be successfully read... */ - for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ ) - { - cTemp = cReadOnlyArray[ x ]; - } - - /* ...but cannot be written. Uncomment the following line to test. */ - /* cReadOnlyArray[ 0 ] = 'a'; */ - - /* Writing to the first and last locations in the stack array should not - cause a protection fault. Note that doing this will cause the kernel to - detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than - 1, hence the test is commented out by default. */ - /* xCheckTaskStack[ 0 ] = 0; - xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */ - - /* Writing off either end of the stack array should cause a protection - fault, uncomment either of the following two lines to test. */ - /* xCheckTaskStack[ -1 ] = 0; */ - /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ - - ( void ) cTemp; + int32_t x; + char cTemp; + + /* The check task (from which this function is called) is created in the + * Privileged mode. The privileged array can be both read from and written + * to while this task is privileged. */ + cPrivilegedOnlyAccessArray[ 0 ] = 'a'; + + if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + * apparent (no output will be displayed). */ + vMainDeleteMe(); + } + + /* Writing off the end of the RAM allocated to this task will *NOT* cause a + * protection fault because the task is still executing in a privileged mode. + * Uncomment the following to test. */ + /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/ + + /* Now set the task into user mode. */ + portSWITCH_TO_USER_MODE(); + + /* Accessing the privileged only array will now cause a fault. Uncomment + * the following line to test. */ + /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/ + + /* The read/write array can still be successfully read and written. */ + for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ ) + { + cReadWriteArray[ x ] = 'a'; + + if( cReadWriteArray[ x ] != 'a' ) + { + /* Something unexpected happened. Delete this task so the error is + * apparent (no output will be displayed). */ + vMainDeleteMe(); + } + } + + /* But attempting to read or write off the end of the RAM allocated to this + * task will cause a fault. Uncomment either of the following two lines to + * test. */ + /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */ + /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */ + + /* The read only array can be successfully read... */ + for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ ) + { + cTemp = cReadOnlyArray[ x ]; + } + + /* ...but cannot be written. Uncomment the following line to test. */ + /* cReadOnlyArray[ 0 ] = 'a'; */ + + /* Writing to the first and last locations in the stack array should not + * cause a protection fault. Note that doing this will cause the kernel to + * detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than + * 1, hence the test is commented out by default. */ + + /* xCheckTaskStack[ 0 ] = 0; + * xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */ + + /* Writing off either end of the stack array should cause a protection + * fault, uncomment either of the following two lines to test. */ + /* xCheckTaskStack[ -1 ] = 0; */ + /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */ + + ( void ) cTemp; } /*-----------------------------------------------------------*/ static void prvExerciseEventGroupAPI( void ) { -EventGroupHandle_t xEventGroup; -StaticEventGroup_t xEventGroupBuffer; -EventBits_t xBits; -const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01; - - /* Exercise some event group functions. */ - xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); - configASSERT( xEventGroup ); - - /* No bits should be set. */ - xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK ); - configASSERT( xBits == ( EventBits_t ) 0 ); - - /* Set bits and read back to ensure the bits were set. */ - xEventGroupSetBits( xEventGroup, xBitsToWaitFor ); - xBits = xEventGroupGetBits( xEventGroup ); - configASSERT( xBits == xBitsToWaitFor ); - - /* Clear a bit and read back again using a different API function. */ - xEventGroupClearBits( xEventGroup, xBitToClear ); - xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK ); - configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) ); - - /* Finished with the event group. */ - vEventGroupDelete( xEventGroup ); + EventGroupHandle_t xEventGroup; + StaticEventGroup_t xEventGroupBuffer; + EventBits_t xBits; + const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01; + + /* Exercise some event group functions. */ + xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + configASSERT( xEventGroup ); + + /* No bits should be set. */ + xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK ); + configASSERT( xBits == ( EventBits_t ) 0 ); + + /* Set bits and read back to ensure the bits were set. */ + xEventGroupSetBits( xEventGroup, xBitsToWaitFor ); + xBits = xEventGroupGetBits( xEventGroup ); + configASSERT( xBits == xBitsToWaitFor ); + + /* Clear a bit and read back again using a different API function. */ + xEventGroupClearBits( xEventGroup, xBitToClear ); + xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK ); + configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) ); + + /* Finished with the event group. */ + vEventGroupDelete( xEventGroup ); } /*-----------------------------------------------------------*/ static void prvExerciseSemaphoreAPI( void ) { -SemaphoreHandle_t xSemaphore; -StaticSemaphore_t xSemaphoreBuffer; -const UBaseType_t uxMaxCount = 5, uxInitialCount = 0; - - /* Most of the semaphore API is common to the queue API and is already being - used. This function uses a few semaphore functions that are unique to the - RTOS objects, rather than generic and used by queues also. - - First create and use a counting semaphore. */ - xSemaphore = xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, &xSemaphoreBuffer ); - configASSERT( xSemaphore ); - - /* Give the semaphore a couple of times and ensure the count is returned - correctly. */ - xSemaphoreGive( xSemaphore ); - xSemaphoreGive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 ); - vSemaphoreDelete( xSemaphore ); - - /* Create a recursive mutex, and ensure the mutex holder and count are - returned returned correctly. */ - xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xSemaphoreBuffer ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphore ); - xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); - xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) ); - xSemaphoreGiveRecursive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); - xSemaphoreGiveRecursive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); - vSemaphoreDelete( xSemaphore ); - - /* Create a normal mutex, and sure the mutex holder and count are returned - returned correctly. */ - xSemaphore = xSemaphoreCreateMutexStatic( &xSemaphoreBuffer ); - configASSERT( xSemaphore ); - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */ - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); - xSemaphoreGive( xSemaphore ); - configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); - configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); - vSemaphoreDelete( xSemaphore ); + SemaphoreHandle_t xSemaphore; + StaticSemaphore_t xSemaphoreBuffer; + const UBaseType_t uxMaxCount = 5, uxInitialCount = 0; + + /* Most of the semaphore API is common to the queue API and is already being + * used. This function uses a few semaphore functions that are unique to the + * RTOS objects, rather than generic and used by queues also. + * + * First create and use a counting semaphore. */ + xSemaphore = xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, &xSemaphoreBuffer ); + configASSERT( xSemaphore ); + + /* Give the semaphore a couple of times and ensure the count is returned + * correctly. */ + xSemaphoreGive( xSemaphore ); + xSemaphoreGive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 ); + vSemaphoreDelete( xSemaphore ); + + /* Create a recursive mutex, and ensure the mutex holder and count are + * returned returned correctly. */ + xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xSemaphoreBuffer ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphore ); + xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); + xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) ); + xSemaphoreGiveRecursive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); + xSemaphoreGiveRecursive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); + vSemaphoreDelete( xSemaphore ); + + /* Create a normal mutex, and sure the mutex holder and count are returned + * returned correctly. */ + xSemaphore = xSemaphoreCreateMutexStatic( &xSemaphoreBuffer ); + configASSERT( xSemaphore ); + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */ + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() ); + xSemaphoreGive( xSemaphore ); + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 ); + configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL ); + vSemaphoreDelete( xSemaphore ); } /*-----------------------------------------------------------*/ static void prvExerciseTaskNotificationAPI( void ) { -uint32_t ulNotificationValue; -BaseType_t xReturned; - - /* The task should not yet have a notification pending. */ - xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); - configASSERT( xReturned == pdFAIL ); - configASSERT( ulNotificationValue == 0UL ); - - /* Exercise the 'give' and 'take' versions of the notification API. */ - xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); - xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); - ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK ); - configASSERT( ulNotificationValue == 2 ); - - /* Exercise the 'notify' and 'clear' API. */ - ulNotificationValue = 20; - xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); - ulNotificationValue = 0; - xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); - configASSERT( xReturned == pdPASS ); - configASSERT( ulNotificationValue == 20 ); - xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); - xReturned = xTaskNotifyStateClear( NULL ); - configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */ - xReturned = xTaskNotifyStateClear( NULL ); - configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */ + uint32_t ulNotificationValue; + BaseType_t xReturned; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotificationValue == 0UL ); + + /* Exercise the 'give' and 'take' versions of the notification API. */ + xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK ); + configASSERT( ulNotificationValue == 2 ); + + /* Exercise the 'notify' and 'clear' API. */ + ulNotificationValue = 20; + xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); + ulNotificationValue = 0; + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK ); + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotificationValue == 20 ); + xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */ + xReturned = xTaskNotifyStateClear( NULL ); + configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */ } /*-----------------------------------------------------------*/ -static void prvTaskToDelete( void *pvParameters ) +static void prvTaskToDelete( void * pvParameters ) { - /* Remove compiler warnings about unused parameters. */ - ( void ) pvParameters; - - /* Check the enter and exit critical macros are working correctly. If the - SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will - fault. */ - taskENTER_CRITICAL(); - taskEXIT_CRITICAL(); - - /* Exercise the API of various RTOS objects. */ - prvExerciseEventGroupAPI(); - prvExerciseSemaphoreAPI(); - prvExerciseTaskNotificationAPI(); - - /* For code coverage test purposes it is deleted by the Idle task. */ - configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 ); - vTaskSuspend( NULL ); + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Check the enter and exit critical macros are working correctly. If the + * SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will + * fault. */ + taskENTER_CRITICAL(); + taskEXIT_CRITICAL(); + + /* Exercise the API of various RTOS objects. */ + prvExerciseEventGroupAPI(); + prvExerciseSemaphoreAPI(); + prvExerciseTaskNotificationAPI(); + + /* For code coverage test purposes it is deleted by the Idle task. */ + configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 ); + vTaskSuspend( NULL ); } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile const uint32_t *pul; -volatile uint32_t ulReadData; - - /* The idle task, and therefore this function, run in Supervisor mode and - can therefore access all memory. Try reading from corners of flash and - RAM to ensure a memory fault does not occur. - - Start with the edges of the privileged data area. */ - pul = __privileged_data_start__; - ulReadData = *pul; - pul = __privileged_data_end__ - 1; - ulReadData = *pul; - - /* Next the standard SRAM area. */ - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* And the standard Flash area - the start of which is marked for - privileged access only. */ - pul = __FLASH_segment_start__; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Reading off the end of Flash or SRAM space should cause a fault. - Uncomment one of the following two pairs of lines to test. */ - - /* pul = __FLASH_segment_end__ + 4; - ulReadData = *pul; */ - - /* pul = __SRAM_segment_end__ + 1; - ulReadData = *pul; */ - - /* One task is created purely so it can be deleted - done for code coverage - test purposes. */ - if( xTaskToDelete != NULL ) - { - vTaskDelete( xTaskToDelete ); - xTaskToDelete = NULL; - } - - ( void ) ulReadData; + volatile const uint32_t * pul; + volatile uint32_t ulReadData; + + /* The idle task, and therefore this function, run in Supervisor mode and + * can therefore access all memory. Try reading from corners of flash and + * RAM to ensure a memory fault does not occur. + * + * Start with the edges of the privileged data area. */ + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Next the standard SRAM area. */ + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* And the standard Flash area - the start of which is marked for + * privileged access only. */ + pul = __FLASH_segment_start__; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading off the end of Flash or SRAM space should cause a fault. + * Uncomment one of the following two pairs of lines to test. */ + + /* pul = __FLASH_segment_end__ + 4; + * ulReadData = *pul; */ + + /* pul = __SRAM_segment_end__ + 1; + * ulReadData = *pul; */ + + /* One task is created purely so it can be deleted - done for code coverage + * test purposes. */ + if( xTaskToDelete != NULL ) + { + vTaskDelete( xTaskToDelete ); + xTaskToDelete = NULL; + } + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ static void prvOldStyleUserModeTask( void ) { /*const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;*/ -volatile const uint32_t *pul; -volatile uint32_t ulReadData; + volatile const uint32_t * pul; + volatile uint32_t ulReadData; /* The following lines are commented out to prevent the unused variable -compiler warnings when the tests that use the variable are also commented out. */ + * compiler warnings when the tests that use the variable are also commented out. */ /* extern uint32_t __privileged_functions_start__[]; */ /* const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; */ - /* This task is created in User mode using the original xTaskCreate() API - function. It should have access to all Flash and RAM except that marked - as Privileged access only. Reading from the start and end of the non- - privileged RAM should not cause a problem (the privileged RAM is the first - block at the bottom of the RAM memory). */ - pul = __privileged_data_end__ + 1; - ulReadData = *pul; - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* Likewise reading from the start and end of the non-privileged Flash - should not be a problem (the privileged Flash is the first block at the - bottom of the Flash memory). */ - pul = __privileged_functions_end__ + 1; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Standard peripherals are accessible. */ - /*ulReadData = *pulStandardPeripheralRegister;*/ - - /* System peripherals are not accessible. Uncomment the following line - to test. Also uncomment the declaration of pulSystemPeripheralRegister - at the top of this function. - ulReadData = *pulSystemPeripheralRegister; */ - - /* Reading from anywhere inside the privileged Flash or RAM should cause a - fault. This can be tested by uncommenting any of the following pairs of - lines. Also uncomment the declaration of __privileged_functions_start__ - at the top of this function. */ - - /*pul = __privileged_functions_start__; - ulReadData = *pul;*/ - - /*pul = __privileged_functions_end__ - 1; - ulReadData = *pul;*/ - - /*pul = __privileged_data_start__; - ulReadData = *pul;*/ - - /*pul = __privileged_data_end__ - 1; - ulReadData = *pul;*/ - - ( void ) ulReadData; + /* This task is created in User mode using the original xTaskCreate() API + * function. It should have access to all Flash and RAM except that marked + * as Privileged access only. Reading from the start and end of the non- + * privileged RAM should not cause a problem (the privileged RAM is the first + * block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + * should not be a problem (the privileged Flash is the first block at the + * bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Standard peripherals are accessible. */ + /*ulReadData = *pulStandardPeripheralRegister;*/ + + /* System peripherals are not accessible. Uncomment the following line + * to test. Also uncomment the declaration of pulSystemPeripheralRegister + * at the top of this function. + * ulReadData = *pulSystemPeripheralRegister; */ + + /* Reading from anywhere inside the privileged Flash or RAM should cause a + * fault. This can be tested by uncommenting any of the following pairs of + * lines. Also uncomment the declaration of __privileged_functions_start__ + * at the top of this function. */ + + /*pul = __privileged_functions_start__; + * ulReadData = *pul;*/ + + /*pul = __privileged_functions_end__ - 1; + * ulReadData = *pul;*/ + + /*pul = __privileged_data_start__; + * ulReadData = *pul;*/ + + /*pul = __privileged_data_end__ - 1; + * ulReadData = *pul;*/ + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ -static void prvOldStylePrivilegedModeTask( void *pvParameters ) +static void prvOldStylePrivilegedModeTask( void * pvParameters ) { -volatile const uint32_t *pul; -volatile uint32_t ulReadData; -const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */ + volatile const uint32_t * pul; + volatile uint32_t ulReadData; + const volatile uint32_t * pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */ + /*const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;*/ - ( void ) pvParameters; - - /* This task is created in Privileged mode using the original xTaskCreate() - API function. It should have access to all Flash and RAM including that - marked as Privileged access only. So reading from the start and end of the - non-privileged RAM should not cause a problem (the privileged RAM is the - first block at the bottom of the RAM memory). */ - pul = __privileged_data_end__ + 1; - ulReadData = *pul; - pul = __SRAM_segment_end__ - 1; - ulReadData = *pul; - - /* Likewise reading from the start and end of the non-privileged Flash - should not be a problem (the privileged Flash is the first block at the - bottom of the Flash memory). */ - pul = __privileged_functions_end__ + 1; - ulReadData = *pul; - pul = __FLASH_segment_end__ - 1; - ulReadData = *pul; - - /* Reading from anywhere inside the privileged Flash or RAM should also - not be a problem. */ - pul = __privileged_functions_start__; - ulReadData = *pul; - pul = __privileged_functions_end__ - 1; - ulReadData = *pul; - pul = __privileged_data_start__; - ulReadData = *pul; - pul = __privileged_data_end__ - 1; - ulReadData = *pul; - - /* Finally, accessing both System and normal peripherals should both be - possible. */ - ulReadData = *pulSystemPeripheralRegister; - /*ulReadData = *pulStandardPeripheralRegister;*/ - - /* Must not just run off the end of a task function, so delete this task. - Note that because this task was created using xTaskCreate() the stack was - allocated dynamically and I have not included any code to free it again. */ - vTaskDelete( NULL ); - - ( void ) ulReadData; + ( void ) pvParameters; + + /* This task is created in Privileged mode using the original xTaskCreate() + * API function. It should have access to all Flash and RAM including that + * marked as Privileged access only. So reading from the start and end of the + * non-privileged RAM should not cause a problem (the privileged RAM is the + * first block at the bottom of the RAM memory). */ + pul = __privileged_data_end__ + 1; + ulReadData = *pul; + pul = __SRAM_segment_end__ - 1; + ulReadData = *pul; + + /* Likewise reading from the start and end of the non-privileged Flash + * should not be a problem (the privileged Flash is the first block at the + * bottom of the Flash memory). */ + pul = __privileged_functions_end__ + 1; + ulReadData = *pul; + pul = __FLASH_segment_end__ - 1; + ulReadData = *pul; + + /* Reading from anywhere inside the privileged Flash or RAM should also + * not be a problem. */ + pul = __privileged_functions_start__; + ulReadData = *pul; + pul = __privileged_functions_end__ - 1; + ulReadData = *pul; + pul = __privileged_data_start__; + ulReadData = *pul; + pul = __privileged_data_end__ - 1; + ulReadData = *pul; + + /* Finally, accessing both System and normal peripherals should both be + * possible. */ + ulReadData = *pulSystemPeripheralRegister; + /*ulReadData = *pulStandardPeripheralRegister;*/ + + /* Must not just run off the end of a task function, so delete this task. + * Note that because this task was created using xTaskCreate() the stack was + * allocated dynamically and I have not included any code to free it again. */ + vTaskDelete( NULL ); + + ( void ) ulReadData; } /*-----------------------------------------------------------*/ void vMainDeleteMe( void ) { - vTaskDelete( NULL ); + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber ) +void vMainSendImAlive( QueueHandle_t xHandle, + uint32_t ulTaskNumber ) { - if( xHandle != NULL ) - { - xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); - } + if( xHandle != NULL ) + { + xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ @@ -990,159 +1008,167 @@ static void prvSetupHardware( void ) void vApplicationTickHook( void ) { -static uint32_t ulCallCount = 0; -const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 1000 ); -const uint32_t ulMessage = configPRINT_SYSTEM_STATUS; -portBASE_TYPE xDummy; - - /* If configUSE_TICK_HOOK is set to 1 then this function will get called - from each RTOS tick. It is called from the tick interrupt and therefore - will be executing in the privileged state. */ - - ulCallCount++; - - /* Is it time to print out the pass/fail message again? */ - if( ulCallCount >= ulCallsBetweenSends ) - { - ulCallCount = 0; - - /* Send a message to the check task to command it to check that all - the tasks are still running then print out the status. - - This is running in an ISR so has to use the "FromISR" version of - xQueueSend(). Because it is in an ISR it is running with privileges - so can access xGlobalScopeCheckQueue directly. */ - xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy ); - } + static uint32_t ulCallCount = 0; + const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 1000 ); + const uint32_t ulMessage = configPRINT_SYSTEM_STATUS; + portBASE_TYPE xDummy; + + /* If configUSE_TICK_HOOK is set to 1 then this function will get called + * from each RTOS tick. It is called from the tick interrupt and therefore + * will be executing in the privileged state. */ + + ulCallCount++; + + /* Is it time to print out the pass/fail message again? */ + if( ulCallCount >= ulCallsBetweenSends ) + { + ulCallCount = 0; + + /* Send a message to the check task to command it to check that all + * the tasks are still running then print out the status. + * + * This is running in an ISR so has to use the "FromISR" version of + * xQueueSend(). Because it is in an ISR it is running with privileges + * so can access xGlobalScopeCheckQueue directly. */ + xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy ); + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this - function will automatically get called if a task overflows its stack. */ - ( void ) pxTask; - ( void ) pcTaskName; - for( ;; ); + /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this + * function will automatically get called if a task overflows its stack. */ + ( void ) pxTask; + ( void ) pcTaskName; + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will - be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() - is called automatically when a task, queue or semaphore is created. */ - for( ;; ); + /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will + * be called automatically if a call to pvPortMalloc() fails. pvPortMalloc() + * is called automatically when a task, queue or semaphore is created. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ static void prvTimerCallback( TimerHandle_t xExpiredTimer ) { -uint32_t ulCount; + uint32_t ulCount; - /* The count of the number of times this timer has expired is saved in the - timer's ID. Obtain the current count. */ - ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer ); + /* The count of the number of times this timer has expired is saved in the + * timer's ID. Obtain the current count. */ + ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer ); - /* Increment the count, and save it back into the timer's ID. */ - ulCount++; - vTimerSetTimerID( xTimer, ( void * ) ulCount ); + /* Increment the count, and save it back into the timer's ID. */ + ulCount++; + vTimerSetTimerID( xTimer, ( void * ) ulCount ); - /* Let the check task know the timer is still running. */ - vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING ); + /* Let the check task know the timer is still running. */ + vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING ); } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ -static void prvRegTest3Task( void *pvParameters ) +static void prvRegTest3Task( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == configREG_TEST_TASK_3_PARAMETER ) - { - /* Run the unprivileged mode access tests that used to be executed - form an unprivileged task created using the xTaskCreate() API. - Since the heap moved to the privileged data section xTaskCreate() can - no longer be used to create unprivileged tasks. */ - prvOldStyleUserModeTask(); - - /* Start the part of the test that is written in assembler. */ - vRegTest3Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == configREG_TEST_TASK_3_PARAMETER ) + { + /* Run the unprivileged mode access tests that used to be executed + * form an unprivileged task created using the xTaskCreate() API. + * Since the heap moved to the privileged data section xTaskCreate() can + * no longer be used to create unprivileged tasks. */ + prvOldStyleUserModeTask(); + + /* Start the part of the test that is written in assembler. */ + vRegTest3Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -static void prvRegTest4Task( void *pvParameters ) +static void prvRegTest4Task( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == configREG_TEST_TASK_4_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest4Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == configREG_TEST_TASK_4_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest4Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.ccsproject b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.ccsproject new file mode 100644 index 00000000000..7fdda62015b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.ccsproject @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.clang-format b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.clang-format new file mode 100644 index 00000000000..c745d9c66fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.clang-format @@ -0,0 +1,104 @@ +--- +Language: Cpp +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: None +AlignConsecutiveBitFields: AcrossEmptyLinesAndComments +AlignConsecutiveDeclarations: None +AlignConsecutiveMacros: AcrossEmptyLinesAndComments +AlignEscapedNewlines: Left +AlignOperands: AlignAfterOperator +AlignTrailingComments: true +AllowAllArgumentsOnNextLine: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: Never +AllowShortCaseLabelsOnASingleLine: false +AllowShortEnumsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: false +AllowShortLambdasOnASingleLine: All +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: Yes +BinPackArguments: false +BinPackParameters: false +BitFieldColonSpacing: Both +BraceWrapping: + AfterCaseLabel: true + AfterClass: true + AfterControlStatement: Always + AfterEnum: true + AfterExternBlock: false + AfterFunction: true + AfterNamespace: true + AfterStruct: true + AfterUnion: true + BeforeCatch: true + BeforeElse: true + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakBeforeBinaryOperators: NonAssignment +BreakBeforeBraces: Custom +BreakBeforeConceptDeclarations: true +BreakBeforeTernaryOperators: true +BreakConstructorInitializers: BeforeColon +BreakInheritanceList: BeforeColon +BreakStringLiterals: true +ColumnLimit: 90 +CompactNamespaces: false +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +EmptyLineBeforeAccessModifier: Always +FixNamespaceComments: true +IncludeBlocks: Preserve +IndentCaseBlocks: false +IndentCaseLabels: true +IndentExternBlock: NoIndent +IndentGotoLabels: true +IndentPPDirectives: BeforeHash +IndentWidth: 4 +IndentWrappedFunctionNames: true +KeepEmptyLinesAtTheStartOfBlocks: false +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +PenaltyBreakAssignment: 1000 +PenaltyBreakBeforeFirstCallParameter: 200 +PenaltyBreakComment: 50 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 100 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 100 +PenaltyIndentedWhitespace: 0 +PenaltyReturnTypeOnItsOwnLine: 10000 +PointerAlignment: Middle +ReflowComments: true +SortIncludes: false +SortUsingDeclarations: true +SpaceAfterCStyleCast: true +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: false +SpaceBeforeCpp11BracedList: true +SpaceBeforeCtorInitializerColon: false +SpaceBeforeInheritanceColon: false +SpaceBeforeParens: Never +SpaceBeforeRangeBasedForLoopColon: false +SpaceBeforeSquareBrackets: false +SpaceInEmptyBlock: false +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInConditionalStatement: true +SpacesInContainerLiterals: true +SpacesInCStyleCastParentheses: true +SpacesInParentheses: true +SpacesInSquareBrackets: true +TabWidth: 4 +UseCRLF: false +UseTab: Never +... + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject new file mode 100644 index 00000000000..29e8979ae89 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore new file mode 100644 index 00000000000..ba04ae8d56e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore @@ -0,0 +1,4 @@ +[Bb]uild +[Dd]ebug +.settings/ +.launches/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project new file mode 100644 index 00000000000..cadb79efb9e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project @@ -0,0 +1,112 @@ + + + RM57_DEMO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + FreeRTOS-Kernel + 2 + FREERTOS_KERNEL_DIR + + + + + 1703728734708 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-CMakeLists.txt + + + + 1703728734721 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-build + + + + 1703284519364 + FreeRTOS-Kernel + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.c + + + + 1703284519366 + FreeRTOS-Kernel + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-examples + + + + 1720520309667 + FreeRTOS-Kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1720518946690 + FreeRTOS-Kernel/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-ARM_CRx_No_GIC + + + + + + BOARD_FILES_DIR + $%7BPROJECT_LOC%7D/BoardFiles + + + DEMO_TASKS_DIR + $%7BPARENT-1-PROJECT_LOC%7D/DemoTasks + + + FREERTOS_KERNEL_DIR + $%7BPARENT-2-PROJECT_LOC%7D/Source + + + FREERTOS_PORT_DIR + $%7BFREERTOS_KERNEL_DIR%7D/portable/GCC/ARM_CRx_No_GIC + + + REPOSITORY_ROOT + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace new file mode 100644 index 00000000000..a132b0b1a0d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace @@ -0,0 +1,50 @@ +{ + "folders": [ + { + "path": ".." + }, + { + "path": "../../../Source", + "name": "FreeRTOS-Kernel" + }, + { + "path": "../../../Source/portable/GCC/ARM_CRx_No_GIC", + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_No_GIC", + "../../Source/include", + "../../Source", + ], + } + ], + "settings": { + "files.associations": { + "*.h": "c", + "variant": "c" + }, + + "files.exclude": { + "**/.launches/**": true, + "**/.settings/**": true, + "**/.ccsproject/**": true, + "**/examples**": true, + "**/.github**": true, + "**/.git[a-hj-z-]**": true, + "**/portable/**": true + + }, + + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_No_GIC", + "../../Source/include", + "../../Source", + ], + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil new file mode 100644 index 00000000000..49910de8bf4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil @@ -0,0 +1,11975 @@ +# RM57L843ZWT 02/13/23 13:55:32 +# +ARCH=RM57L843ZWT +# +DRIVER.TOOLS.VAR.GCC.VALUE=1 +DRIVER.TOOLS.VAR.ARM.VALUE=0 +DRIVER.TOOLS.VAR.IAR.VALUE=0 +DRIVER.TOOLS.VAR.GHS.VALUE=0 +DRIVER.TOOLS.VAR.TI.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OIWTNOWA_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_0.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_1_WAIT_STATE_FREQ.VALUE=32.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=mibspi4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2 +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_1.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=180.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.LIN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0002 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=epcFullInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=sci4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=ecap5Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=150.000 +DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=300.00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=dmaBTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x6FFFFFFF +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=etpwm5TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_isrStub +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OIWBWA_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x00007fff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=90.0 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08000500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=etpwm1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SIZE.VALUE=512_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_STACK.VALUE=12 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=FreeRTOS_Tick_Handler +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=can4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=ecap6Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x00080000 +DRIVER.SYSTEM.VAR.CORE_MPU_TOTAL_REGION.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=256_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=dmaFTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_8_WAIT_STATE_FREQ.VALUE=144.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt +DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=40 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=300.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48 +DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=8 +DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001 +DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=etpwm1TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0xF8000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x1B +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_NUM.VALUE=3 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=lin2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=dmaLFSAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_6_WAIT_STATE_FREQ.VALUE=112.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SIZE_VALUE.VALUE=0x12 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE +DRIVER.SYSTEM.VAR.CRC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_WAIT_STATES.VALUE=9 +DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08000600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_HCLK_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=sci4LowLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_4_WAIT_STATE_FREQ.VALUE=80.0 +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=120.0 +DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=lin1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=eqep1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=etpwm7Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=0 +DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_ECC_AVAILABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x000C +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_CACHE_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=9.375 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=etpwm2TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_10_WAIT_STATE_FREQ.VALUE=176.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_NA_EXEC +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0x003fffff +DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=VCLKA4_DIVR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_2_WAIT_STATE_FREQ.VALUE=48.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=18.750 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.MIBSPI2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=150 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_LAST.VALUE=15 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_FIRST.VALUE=13 +DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=eqep2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0007F800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=150 +DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=0.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=etpwm3Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00008020 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00200000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_0_WAIT_STATE_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=135.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5 +DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=128 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.LIN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=ecap1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68 +DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_9_WAIT_STATE_FREQ.VALUE=160.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00400000 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=etpwm3TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=EMACRxIntISR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=45.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=75.000 +DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_MAX_WAIT_STATES.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x000B +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=mibspi4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt +DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESERVED_ENTRY.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=crc2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=can4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=ecap2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.I2C1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_7_WAIT_STATE_FREQ.VALUE=128.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=vPortYieldWithinAPI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=lin1HighLevelInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08000700 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=etpwm4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0807ffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x0E +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=75.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL_VAL.VALUE=9500 +DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=dmaHBCAInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13 +DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=8 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_5_WAIT_STATE_FREQ.VALUE=96.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=i2c2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=ecap3nterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=32_KB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=mibspi2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt +DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SCI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=vPortSWI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1 +DRIVER.SYSTEM.VAR.CRC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0002 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=etpwm4TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3 +DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=75.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_M3.VALUE=0 +DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OIWTNOWA_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x001F7FE0 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00200000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_11_WAIT_STATE_FREQ.VALUE=192.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sci3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_3_WAIT_STATE_FREQ.VALUE=64.0 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08000400 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000020000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=lin2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=ecap4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=0 +DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE +DRIVER.SYSTEM.VAR.CLKT_RESERVED_SOURCE_ENABLE.VALUE=0x00000004 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=512_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=0 +DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=9500 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=300.00 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_BASE_ADDRESS.VALUE=0xFFF80000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=etpwm5Interrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2 +DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.AJSM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SPL_SOURCE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9 +DRIVER.SYSTEM.VAR.VIM_ECC_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SCI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_MAPPING.VALUE=111 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_MAPPING.VALUE=103 +DRIVER.SYSTEM.VAR.VIM_PHANTOM_NAME.VALUE=phantomInterrupt +DRIVER.OS.VAR.OS_USERECERSIVEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_USETIMERS.VALUE=0 +DRIVER.OS.VAR.OS_USECNTSEMAPHORE.VALUE=0 +DRIVER.OS.VAR.OS_GENERATERUNTIMESTATS.VALUE=0 +DRIVER.OS.VAR.OS_USEMPU.VALUE=0 +DRIVER.OS.VAR.OS_TOTALHEAPSIZE.VALUE=8192 +DRIVER.OS.VAR.OS_USEVERBOSESTACK.VALUE=2 +DRIVER.OS.VAR.OS_TIMERPRIORITY.VALUE=0 +DRIVER.OS.VAR.OS_SVCENABLE.VALUE=0 +DRIVER.OS.VAR.OS_MAXTASKNAMELEN.VALUE=16 +DRIVER.OS.VAR.OS_MAXPRIORITIES.VALUE=5 +DRIVER.OS.VAR.OS_TIMERTASKSTACKDEPTH.VALUE=0 +DRIVER.OS.VAR.OS_COROUTINEPRIORITIES.VALUE=2 +DRIVER.OS.VAR.OS_USECOROUTINES.VALUE=0 +DRIVER.OS.VAR.OS_USEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_CPUCLOCKHZ.VALUE=75000000 +DRIVER.OS.VAR.OS_USEMALLOCFAILEDHOOK.VALUE=0 +DRIVER.OS.VAR.OS_MINSTACKSIZE.VALUE=128 +DRIVER.OS.VAR.OS_SYSTEM_MODE.VALUE=0x1F +DRIVER.OS.VAR.OS_USEPREEMPTION.VALUE=1 +DRIVER.OS.VAR.OS_IDLESHOULDYIELD.VALUE=1 +DRIVER.OS.VAR.OS_USEIDLEHOOK.VALUE=0 +DRIVER.OS.VAR.OS_TICKRATEHZ.VALUE=1000 +DRIVER.OS.VAR.OS_TIMERPQUEUELENGTH.VALUE=0 +DRIVER.OS.VAR.OS_USETRACE.VALUE=0 +DRIVER.OS.VAR.OS_USESTACK.VALUE=0 +DRIVER.OS.VAR.OS_USETICKHOOK.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL93_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL85_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL77_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL69_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL94_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL86_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL78_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL88_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL81_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL73_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL65_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL70_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL94_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL86_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL78_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL91_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL83_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL75_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL67_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL82_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL74_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL66_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=218.453 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL31_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL23_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL15_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL95_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL87_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL79_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL88_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL82_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL74_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL66_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL82_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL74_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL66_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL60_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL52_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL44_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL36_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL28_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL80_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL72_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL64_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=75 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL93_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL85_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL77_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL69_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL95_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL87_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL79_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL95_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL87_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL79_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL80_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL72_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL64_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL81_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL73_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL65_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_INT_LEVEL.VALUE=0 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+DRIVER.SCI.VAR.SCI3_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI4_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_BASE_PORT.VALUE=0xFFF7E740 +DRIVER.SCI.VAR.SCI4_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI2_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI4_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI3_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI1_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_BASE_PORT.VALUE=0xFFF7E640 +DRIVER.SCI.VAR.SCI3_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI3_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI2_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI4_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI1_BASE.VALUE=0xFFF7E400 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI1_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_BASE.VALUE=0xFFF7E600 +DRIVER.SCI.VAR.SCI2_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI3_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI3_BASE.VALUE=0xFFF7E500 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI2_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_BASE_PORT.VALUE=0xFFF7E540 +DRIVER.SCI.VAR.SCI4_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI2_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI2_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_BASE_RAM.VALUE=0xFF080000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.MIBSPI.VAR.MIBSPI4_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI4_BASE_RAM.VALUE=0xFF060000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_BASE.VALUE=0xFFF7F600 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF060000 +DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400 +DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF080000 +DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00 +DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_BASE.VALUE=0xFFF7E200 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_4_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_4_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_RAMBASE.VALUE=0xFF180000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=106.67 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000 +DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=106.67 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000 +DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=7 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=7 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN1_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN1_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.LIN.VAR.LIN2_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN2_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN2_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_MAXPRESCALE.VALUE=3370 +DRIVER.LIN.VAR.LIN2_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN1_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN1_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN2_RXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_FEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN2_IDINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN2_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN2_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BASE.VALUE=0xFFF7E400 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN2_TOINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN2_BEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_ACTUALBAUDRATE.VALUE=20.032 +DRIVER.LIN.VAR.LIN1_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN2_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN2_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN2_RXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PRESCALE.VALUE=233 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN2_BASE.VALUE=0xFFF7E600 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN2_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN2_BASE_PORT.VALUE=0xFFF7E640 +DRIVER.LIN.VAR.LIN1_BAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN2_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN2_MAXBAUDRATE.VALUE=22.255 +DRIVER.LIN.VAR.LIN1_RXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_FEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN2_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_ISFEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_ACTUALBAUDRATE.VALUE=20.032 +DRIVER.LIN.VAR.LIN1_IDINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN1_BEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_RXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN1_PRESCALE.VALUE=233 +DRIVER.LIN.VAR.LIN1_ISFEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN2_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN2_MAXPRESCALE.VALUE=3370 +DRIVER.LIN.VAR.LIN2_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_MAXBAUDRATE.VALUE=22.255 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN2_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN2_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=149888 +DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0 +DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000008 +DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50 +DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000 +DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10 +DRIVER.HET.VAR.HET2_BIT20_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.053 +DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3 +DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0 +DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000 +DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00002000 +DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.106 +DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9 +DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT26_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0 +DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16 +DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.053 +DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000 +DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0 +DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT31_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT23_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT15_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE2_EVENT.VALUE=1 +DRIVER.HET.VAR.HET2_BIT11_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PIN_ENABLE.VALUE=0 +DRIVER.HET.VAR.HET1_CAP3_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET1_BIT24_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT16_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT5_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT27_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT19_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_EDGE6_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT24_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_BIT16_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_BIT2_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM6_DUTY_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE3_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE5_PIN_SELECT.VALUE=21 +DRIVER.HET.VAR.HET2_BIT21_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT13_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM7_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET1_BIT27_DOUT.VALUE=0 +DRIVER.HET.VAR.HET1_BIT19_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_CAP5_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET2_PWM4_ENA.VALUE=0 +DRIVER.HET.VAR.HET2_BIT8_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM1_POLARITY.VALUE=3 +DRIVER.HET.VAR.HET2_CAP2_PIN_SELECT.VALUE=4 +DRIVER.HET.VAR.HET2_BIT4_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM0_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=149888 +DRIVER.HET.VAR.HET2_BIT1_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT20_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT12_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM7_ACTION.VALUE=3 +DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=149888 +DRIVER.HET.VAR.HET2_BIT26_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_BIT24_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT18_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_BIT16_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM3_DUTY_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM3_POLARITY.VALUE=3 +DRIVER.HET.VAR.HET2_BIT28_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT0_XORSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.106 +DRIVER.HET.VAR.HET2_BIT29_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_BIT6_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_CAP5_PIN_SELECT.VALUE=26 +DRIVER.HET.VAR.HET1_BIT28_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT10_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE7_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM0_ACTION.VALUE=3 +DRIVER.HET.VAR.HET2_BIT1_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_EDGE7_EVENT.VALUE=1 +DRIVER.HET.VAR.HET1_EDGE5_BOTH.VALUE=0 +DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=75136 +DRIVER.HET.VAR.HET1_BIT3_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_EDGE7_POLARITY.VALUE=0 +DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM3_DUTY.VALUE=50 +DRIVER.HET.VAR.HET1_PWM1_PERIOD_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT30_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT22_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT14_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT4_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE4_EVENT.VALUE=1 +DRIVER.HET.VAR.HET1_BIT5_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_MASTER.VALUE=1 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+DRIVER.I2C.VAR.I2C2_ICRRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C2_BASE.VALUE=0xFFF7D500 +DRIVER.I2C.VAR.I2C2_AASLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_AAS.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICCH.VALUE=37 +DRIVER.I2C.VAR.I2C2_BCM.VALUE=0 +DRIVER.I2C.VAR.I2C2_BC.VALUE=2_BIT +DRIVER.I2C.VAR.I2C1_MODCLK.VALUE=8 +DRIVER.I2C.VAR.I2C1_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICCL.VALUE=37 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_ADDRMODE.VALUE=7BIT_AMODE +DRIVER.I2C.VAR.I2C2_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C1_RXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C2_BC_VALUE.VALUE=0x0003 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C1_ICXRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICCH.VALUE=37 +DRIVER.I2C.VAR.I2C1_NACKINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICCL.VALUE=37 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C1_TXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C2_LENGTH.VALUE=8 +DRIVER.I2C.VAR.I2C1_EVENPARITY.VALUE=0 +DRIVER.I2C.VAR.I2C1_RM_ENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICRRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ALINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_PRESCALE.VALUE=8 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C1_SCDLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C2_TXRX_VALUE.VALUE=0 +DRIVER.I2C.VAR.I2C1_STPCND.VALUE=1 +DRIVER.I2C.VAR.I2C2_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C1_BAUDRATE.VALUE=100 +DRIVER.I2C.VAR.I2C2_STACND.VALUE=1 +DRIVER.I2C.VAR.I2C2_RXDMA.VALUE=0 +DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10 +DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00 +DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40 +DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0 +DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792 +DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00 +DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=300.0 +DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400 +DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0xA +DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1 +DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0 +DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=742500 +DRIVER.PINMUX.VAR.EQEP2A_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC4A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP5_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.EMIF_OUTPUT_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT" +DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_ETMDATA_08 | PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_E7_ETMDATA_10" +DRIVER.PINMUX.VAR.PINMUX20.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6" +DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_E6_ETMDATA_11 | PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_E12_ETMDATA_13 | PINMUX_BALL_E11_ETMDATA_14" +DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MIBSPI1NCS_0 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_MIBSPI1NCS_2" +DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_M15_ETMDATA_18" +DRIVER.PINMUX.VAR.ECAP3_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX30.VALUE="PINMUX_BALL_E18_N2HET1_08 | PINMUX_BALL_V7_N2HET1_09 | PINMUX_BALL_D19_N2HET1_10 | PINMUX_BALL_E3_N2HET1_11" +DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0" +DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21 | PINMUX_BALL_G5_ETMDATA_22" +DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX31.VALUE="PINMUX_BALL_B4_N2HET1_12 | PINMUX_BALL_N2_N2HET1_13 | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16" +DRIVER.PINMUX.VAR.PINMUX23.VALUE="PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_B2_MIBSPI3NCS_2 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA" +DRIVER.PINMUX.VAR.PINMUX15.VALUE="PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_L5_ETMDATA_24 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_N5_ETMDATA_26" +DRIVER.PINMUX.VAR.PINMUX32.VALUE="PINMUX_BALL_A13_N2HET1_17 | PINMUX_BALL_J1_N2HET1_18 | PINMUX_BALL_B13_N2HET1_19 | PINMUX_BALL_P2_N2HET1_20" +DRIVER.PINMUX.VAR.PINMUX24.VALUE="PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_E19_MIBSPI5NCS_0" +DRIVER.PINMUX.VAR.PINMUX16.VALUE="PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_R5_ETMDATA_28 | PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_R7_ETMDATA_30" +DRIVER.PINMUX.VAR.SIGNAL56_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL48_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX131_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_N2HET1_24" +DRIVER.PINMUX.VAR.PINMUX25.VALUE="PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MIBSPI5NENA" +DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_R8_ETMDATA_31 | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_R10_ETMTRACECLKOUT | PINMUX_BALL_R11_ETMTRACECTL" +DRIVER.PINMUX.VAR.SIGNAL56_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL48_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX131_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB6_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.EQEP2B_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_BALL_A14_N2HET1_26 | PINMUX_BALL_K19_N2HET1_28 | PINMUX_BALL_B11_N2HET1_30 | PINMUX_BALL_D8_N2HET2_01" +DRIVER.PINMUX.VAR.PINMUX26.VALUE="PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2 | PINMUX_BALL_G17_MIBSPI5SIMO_3" +DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2" +DRIVER.PINMUX.VAR.MUX131_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX35.VALUE="PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_N2HET2_12 | PINMUX_BALL_D2_N2HET2_13 | PINMUX_BALL_D1_N2HET2_14" +DRIVER.PINMUX.VAR.PINMUX27.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3" +DRIVER.PINMUX.VAR.PINMUX19.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6" +DRIVER.PINMUX.VAR.MUX131_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX36.VALUE="PINMUX_BALL_P4_N2HET2_19 | PINMUX_BALL_T5_N2HET2_20 | PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK" +DRIVER.PINMUX.VAR.PINMUX28.VALUE="PINMUX_BALL_K18_N2HET1_00 | PINMUX_BALL_V2_N2HET1_01 | PINMUX_BALL_W5_N2HET1_02 | PINMUX_BALL_U1_N2HET1_03" +DRIVER.PINMUX.VAR.MUX131_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX37.VALUE="PINMUX_BALL_E2_N2HET2_03 | PINMUX_BALL_N3_N2HET2_07" +DRIVER.PINMUX.VAR.PINMUX29.VALUE="PINMUX_BALL_B12_N2HET1_04 | PINMUX_BALL_V6_N2HET1_05 | PINMUX_BALL_W3_N2HET1_06 | PINMUX_BALL_T1_N2HET1_07" +DRIVER.PINMUX.VAR.MUX131_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX80.VALUE=SIGNAL_AD2EVT_T10 +DRIVER.PINMUX.VAR.SIGNAL41_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL33_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL25_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL17_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.TEMP2_ENABLE.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX81.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL41_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL33_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL25_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL17_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX90.VALUE="SIGNAL_MII_RX_DV_U6 | SIGNAL_MII_RX_ER_U5 | SIGNAL_MII_RXCLK_T4 | SIGNAL_MII_RXD_0_U4" +DRIVER.PINMUX.VAR.PINMUX82.VALUE=0 +DRIVER.PINMUX.VAR.MUX127_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX119_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_133_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_125_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_117_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_109_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX91.VALUE="SIGNAL_MII_RXD_1_T3 | SIGNAL_MII_RXD_2_U3 | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_U7" +DRIVER.PINMUX.VAR.PINMUX83.VALUE=SIGNAL_GIOA_0_A5 +DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX92.VALUE="SIGNAL_N2HET1_17_A13 | SIGNAL_N2HET1_19_B13 | SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4" +DRIVER.PINMUX.VAR.PINMUX84.VALUE="SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 | SIGNAL_GIOA_4_A6" +DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX93.VALUE="SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17" +DRIVER.PINMUX.VAR.PINMUX85.VALUE="SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 | SIGNAL_GIOB_0_M2" +DRIVER.PINMUX.VAR.MUX100_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB0_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA2_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX94.VALUE="SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 | SIGNAL_N2HET2_02_D7 | SIGNAL_N2HET2_03_E2" +DRIVER.PINMUX.VAR.PINMUX86.VALUE="SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_F2 | SIGNAL_GIOB_3_W10 | SIGNAL_GIOB_4_G1" +DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_110_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX95.VALUE="SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 | SIGNAL_N2HET2_06_D11 | SIGNAL_N2HET2_07_N3" +DRIVER.PINMUX.VAR.PINMUX87.VALUE="SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 | SIGNAL_MDIO_F4" +DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX96.VALUE="SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16" +DRIVER.PINMUX.VAR.PINMUX88.VALUE="SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9" +DRIVER.PINMUX.VAR.SIGNAL10_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX97.VALUE="SIGNAL_N2HET2_12_D3 | SIGNAL_N2HET2_13_D2 | SIGNAL_N2HET2_14_D1 | SIGNAL_N2HET2_15_K4" +DRIVER.PINMUX.VAR.PINMUX89.VALUE="SIGNAL_MII_COL_W4 | SIGNAL_MII_CRS_V4" +DRIVER.PINMUX.VAR.SIGNAL10_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX98.VALUE="SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 | SIGNAL_N2HET2_20_T5 | SIGNAL_N2HET2_22_T7" +DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX99.VALUE="SIGNAL_nTZ1_1_N19 | SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3" +DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1A_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1I_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_SOC3A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.TEMP3_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX120_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX112_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM3_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA_DISABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL4_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL4_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL61_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL53_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL45_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL37_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL29_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP3_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.MUX129_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TBCLK_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX129_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL30_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL22_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL14_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.I2C1.VALUE=0 +DRIVER.PINMUX.VAR.I2C2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL47_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL39_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX130_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL47_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL39_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL8_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX130_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX114_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX106_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1A_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL1_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GIOA0_DMA.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL32_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL24_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL16_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL32_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL24_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL16_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX97_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX89_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.GIOB5_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA7_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PIN_MUX_131_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_123_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_115_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX90_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX82_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX74_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX66_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1S_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX131_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX51_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.GIOA1_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ECAP5_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_SOC2A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.MUX51_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX41_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX33_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX25_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GIOA1_DMA.VALUE=0 +DRIVER.PINMUX.VAR.MUX51_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX51_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX35_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_SELECT.VALUE=1 +DRIVER.PINMUX.VAR.MUX98_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_92_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_84_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_76_SELECT.VALUE=0 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+DRIVER.PINMUX.VAR.ETPWM_EPWM1SYNCI.VALUE=ASYNC +DRIVER.PINMUX.VAR.ETPWM6_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.SIGNAL58_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX133_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL58_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC1A.VALUE=1 +DRIVER.PINMUX.VAR.SCI.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX133_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC2A.VALUE=1 +DRIVER.PINMUX.VAR.MUX133_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX125_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX117_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX109_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL7_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC3A.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL51_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL43_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL35_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL27_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL19_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX110_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC4A.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL51_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL43_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL35_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL27_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL19_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX128_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_129_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC5A.VALUE=1 +DRIVER.PINMUX.VAR.ETPWM.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1S_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX110_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC6A.VALUE=1 +DRIVER.PINMUX.VAR.MUX110_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX102_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_130_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_122_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_114_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC7A.VALUE=1 +DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL20_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL12_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL20_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL12_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX93_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX85_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX77_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX69_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ECAP1_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_TZ3_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1B_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_SOC5A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.ETPWM6_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX121_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX113_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX105_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL6_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GIOB7_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ECAP6_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SIGNAL50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SPI2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL49_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX132_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL49_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.TEMP1_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SPI4.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.RMII.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_D4_EMIF_ADDR_00 | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06" +DRIVER.PINMUX.VAR.MUX132_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10" +DRIVER.PINMUX.VAR.MUX132_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB1_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA3_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14" +DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18" +DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C17_EMIF_ADDR_21" +DRIVER.PINMUX.VAR.SIGNAL50_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL42_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL34_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL26_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL18_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX5.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL50_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL42_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL34_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL26_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL18_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX6.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_127_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_119_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_A.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX7.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX8.VALUE=PINMUX_BALL_D16_EMIF_BA_1 +DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_L17_EMIF_nCS_2" +DRIVER.PINMUX.VAR.MUX101_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_120_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_112_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TZ1_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX132_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM +DRIVER.CRC.VAR.CRC2_CH2_WDTO.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_BASE.VALUE=0xFE000000 +DRIVER.CRC.VAR.CRC1_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400 +DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_BASE.VALUE=0xFB000000 +DRIVER.CRC.VAR.CRC1_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_BCTO.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0 +DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_BCTO.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC2_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_CVH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_RES_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_CVL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC1_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC1_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_CVH.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC2_CH2_CVL.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_PCP.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_SCP.VALUE=0 +DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC2_CH2_PCP.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC2_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC2_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC2_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH2_SCP.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC2_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC2_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT +DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH2_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC1_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.CRC1_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT +DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_WDTO.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC2_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.EMAC.VAR.EMAC_PHY_CUSTOM.VALUE=0 +DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF +DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800 +DRIVER.EMAC.VAR.EMAC_PHY_DP83640.VALUE=1 +DRIVER.EMAC.VAR.EMAC_LOOPBACK_ENA.VALUE=0 +DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900 +DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000 +DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF +DRIVER.EMAC.VAR.EMAC_TRANSMIT_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHY_TLK111.VALUE=0 +DRIVER.EMAC.VAR.EMAC_CHANNELNUMBER.VALUE=0 +DRIVER.EMAC.VAR.EMAC_RX_PBUF_ALLOC.VALUE=10 +DRIVER.EMAC.VAR.EMAC_UNICAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_FULL_DUPLEX_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=1 +DRIVER.EMAC.VAR.EMAC_MII_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000 +DRIVER.EMAC.VAR.EMAC_BROADCAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_RECEIVE_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0 +DRIVER.EMIF.VAR.EMIF_AVAILABLE.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=213 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=213 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=427 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_INIT_TIME.VALUE=200 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=1605 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_CLK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001 +DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=427 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0 +DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0 +DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0 +DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1 +DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1 +DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM +DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0 +DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000 +DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200 +DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM3_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM6_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP5_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP5_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP2_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP6_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_BASE.VALUE=0xFCF79300 +DRIVER.ECAP.VAR.ECAP4_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP5_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP4_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_BASE.VALUE=0xFCF79400 +DRIVER.ECAP.VAR.ECAP2_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP6_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP3_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP3_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP3_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_BASE.VALUE=0xFCF79500 +DRIVER.ECAP.VAR.ECAP5_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP4_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_BASE.VALUE=0xFCF79600 +DRIVER.ECAP.VAR.ECAP6_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP4_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_BASE.VALUE=0xFCF79700 +DRIVER.ECAP.VAR.ECAP3_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_BASE.VALUE=0xFCF79800 +DRIVER.ECAP.VAR.ECAP6_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT4.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP2_QUPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_BASE.VALUE=0xFCF79900 +DRIVER.EQEP.VAR.EQEP1_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_BASE.VALUE=0xFCF79A00 +DRIVER.EQEP.VAR.EQEP1_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP2_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP1_PCSPW.VALUE=0x000 +DRIVER.EQEP.VAR.EQEP1_POSCMP.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP1_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP2_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP2_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP2_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCSPW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.EQEP.VAR.EQEP2_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP1_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP1_WDPRD.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP1_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSCMP.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QUPRD.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP2_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_NUMBER.VALUE=11 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_END.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_START_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_START.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_START.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_START.VALUE=8 +DRIVER.FEE.VAR.FEE_VS29_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VS30_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS22_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS14_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_END.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VS7_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_READ_CYCLE_COUNT.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_NUMBER_OF_VIRTUAL_SECTORS.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX15_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_CRC_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_START.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_START.VALUE=17 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_NUMBER.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_END.VALUE=19 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_END.VALUE=11 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_NUMBER.VALUE=3 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_NUMBER.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_NUMBER.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_NUMBER.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_SECTORS_EEP1.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_END.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_END.VALUE=12 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_START.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VS27_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS19_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS20_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS12_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_DRIVER_INDEX.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_END.VALUE=29 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_END.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_END.VALUE=13 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX9_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX13_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX2_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_START.VALUE=29 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_START.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_START.VALUE=13 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_NUMBER.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_NUMBER_OF_EEPS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_NUMBER.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_END.VALUE=30 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_NUMBER.VALUE=29 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_END.VALUE=22 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_END.VALUE=14 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_NUMBER.VALUE=30 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_NUMBER.VALUE=22 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_NUMBER.VALUE=14 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_DEVICE_INDEX.VALUE=0 +DRIVER.FEE.VAR.FEE_PAGE_OVERHEAD.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_NUMBER.VALUE=3 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MAJOR_VERSION.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_START.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_START.VALUE=18 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_END.VALUE=31 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_END.VALUE=23 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_END.VALUE=15 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_END.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_START.VALUE=0 +DRIVER.FEE.VAR.FEE_VS33_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS25_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS17_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_SECTOR_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VS10_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUALPAGE_SIZE.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS3_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX7_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_END.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_END.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_END.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_END.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX11_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_WRITECOUNTER_SAVE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VS_INDEX.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_NUMBER.VALUE=15 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_PATCH_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_START.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_START.VALUE=5 +DRIVER.FEE.VAR.FEE_JOBERROR_NOTIFICATION.VALUE=JobErrorNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_NUMBER.VALUE=6 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_NUMBER.VALUE=27 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_NUMBER.VALUE=19 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_END.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_NUMBER.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_END.VALUE=17 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_NUMBER.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_NUMBER.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_END.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_SIZE.VALUE=0x10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_TOTAL_BLOCKS_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_NUMBER.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_START.VALUE=30 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_START.VALUE=22 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_START.VALUE=14 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_SIZE.VALUE=8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX.VALUE=1 +DRIVER.FEE.VAR.FEE_VS31_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS23_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS15_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_27_END.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_19_END.VALUE=18 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_END.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VS8_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_MAXIMUM_BLOCKING_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_NO_OF_UNCONFIGURED_BLOCKS_TO_COPY.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_BANK_NUM.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_START.VALUE=27 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_END.VALUE=27 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_END.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_START.VALUE=1 +DRIVER.FEE.VAR.FEE_SECTOR_OVERHEAD.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_NUMBER.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_NUMBER.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_NUMBER.VALUE=17 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MINOR_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_NUMBER.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_NUMBER.VALUE=6 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_END.VALUE=28 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_END.VALUE=5 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_START.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_START.VALUE=6 +DRIVER.FEE.VAR.FEE_VS28_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VERSIONINFO_API.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DATASETS.VALUE=1 +DRIVER.FEE.VAR.MAX_BLOCK_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS21_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS13_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_WRITE_CYCLES.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_OFFSET.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_END.VALUE=6 +DRIVER.FEE.VAR.FEE_NUMBER_OF_BLOCKS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_BANK.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX14_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX3_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_NUMBER_OF_EIGHTBYTEWRITES.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_32_START.VALUE=31 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_24_START.VALUE=23 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_16_START.VALUE=15 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_NUMBER.VALUE=11 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_NUMBER.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_END.VALUE=7 +DRIVER.FEE.VAR.FEE_END_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_NUMBER.VALUE=31 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_NUMBER.VALUE=23 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_NUMBER.VALUE=15 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_HANDLING.VALUE=TI_Fee_None +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_DEVERROR_DETECT.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_START.VALUE=28 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_END.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_START.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VS26_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS18_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS11_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX8_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_MAX_NUMBER_OF_LINKS.VALUE=256 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX12_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_DATASELECT_BITS.VALUE=0 +DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=150.000 +DRIVER.FEE.VAR.FEE_TOTAL_SECTORS.VALUE=32 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_NUMBER.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_START.VALUE=19 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_START.VALUE=11 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_START.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_NUMBER.VALUE=28 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_NUMBER.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_NUMBER.VALUE=9 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_START.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_START.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_START.VALUE=16 +DRIVER.FEE.VAR.FEE_JOBEND_NOTIFICATION.VALUE=JobEndNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VS32_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS24_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_ENABLE_ECC.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_OVERHEAD.VALUE=24 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VS9_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS2_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX10_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_NUMBER.VALUE=14 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_START.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_CHECK_BANK7_ACCESS.VALUE=STD_OFF +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_POLLING_MODE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_NUMBER.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_NUMBER.VALUE=18 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_SIZE.VALUE=0 +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_1.VALUE=0xFFFFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_0.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_0.VALUE=0xFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_1.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_1.VALUE=0xD2 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_2.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_3.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_0.VALUE=0xFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_1.VALUE=0xD2 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_1.VALUE=0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg new file mode 100644 index 00000000000..b26c9d9f031 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg @@ -0,0 +1,1041 @@ + + + + RM57Lx + RM57L843ZWT_FREERTOS + FreeRTOS.dil + gcc + + + 04.07.01 + + + + + + + + + + + + + + + + + + + + + + + + + hal_stdtypes.h + include\hal_stdtypes.h + + + sys_common.h + include\sys_common.h + + + reg_system.h + include\reg_system.h + + + reg_flash.h + include\reg_flash.h + + + reg_l2ramw.h + include\reg_l2ramw.h + + + reg_vim.h + include\reg_vim.h + + + reg_pbist.h + include\reg_pbist.h + + + reg_stc.h + include\reg_stc.h + + + reg_efc.h + include\reg_efc.h + + + reg_pcr.h + include\reg_pcr.h + + + reg_pmm.h + include\reg_pmm.h + + + reg_dma.h + include\reg_dma.h + + + reg_ccmr5.h + include\reg_ccmr5.h + + + sys_core.h + include\sys_core.h + + + system.h + include\system.h + + + sys_vim.h + include\sys_vim.h + + + sys_mpu.h + include\sys_mpu.h + + + sys_pmu.h + include\sys_pmu.h + + + sys_pcr.h + include\sys_pcr.h + + + sys_pmm.h + include\sys_pmm.h + + + sys_dma.h + include\sys_dma.h + + + sys_core.s + source\sys_core.s + + + sys_intvecs.s + source\sys_intvecs.s + + + sys_mpu.s + source\sys_mpu.s + + + sys_pmu.s + source\sys_pmu.s + + + sys_pcr.c + source\sys_pcr.c + + + sys_pmm.c + source\sys_pmm.c + + + sys_dma.c + source\sys_dma.c + + + system.c + source\system.c + + + sys_phantom.c + source\sys_phantom.c + + + sys_startup.c + source\sys_startup.c + + + sys_vim.c + source\sys_vim.c + + + sys_main.c + source\sys_main.c + + + notification.c + source\notification.c + + + sys_link.ld + source\sys_link.ld + + + reg_epc.h + include\reg_epc.h + + + reg_nmpu.h + include\reg_nmpu.h + + + reg_scm.h + include\reg_scm.h + + + reg_sdcmmr.h + include\reg_sdcmmr.h + + + epc.h + include\epc.h + + + epc.c + source\epc.c + + + nmpu.h + include\nmpu.h + + + nmpu.c + source\nmpu.c + + + errata.h + include\errata.h + + + errata.c + source\errata.c + + + Test.h + + + errata_SSWF021_45.h + include\errata_SSWF021_45.h + + + errata_SSWF021_45_defs.h + include\errata_SSWF021_45_defs.h + + + errata_SSWF021_45.c + source\errata_SSWF021_45.c + + + os_projdefs.h + + + FreeRTOSConfig.h + + + os_portmacro.h + + + os_mpu_wrappers.h + + + os_portable.h + + + FreeRTOS.h + + + os_list.h + + + os_queue.h + + + os_semphr.h + + + os_croutine.h + + + os_StackMacros.h + + + os_task.h + + + os_timer.h + + + os_port.c + + + os_portasm.s + + + os_tasks.c + + + os_queue.c + + + os_list.c + + + os_croutine.c + + + os_timer.c + + + os_mpu_wrappers.c + + + os_heap.c + + + os_event_groups.c + + + os_event_groups.h + + + reg_pinmux.h + + + pinmux.h + + + pinmux.c + + + reg_gio.h + + + gio.h + + + gio.c + + + reg_esm.h + + + esm.h + + + esm.c + + + reg_sci.h + + + sci.h + + + sci.c + + + reg_lin.h + + + lin.h + + + lin.c + + + reg_mibspi.h + + + mibspi.h + + + mibspi.c + + + reg_spi.h + + + spi.h + + + + reg_can.h + + + can.h + + + can.c + + + reg_adc.h + + + adc.h + + + adc.c + + + + + + + + + std_nhet.h + + + reg_het.h + + + het.h + + + het.c + + + reg_htu.h + + + htu.h + + + + + + + + + reg_i2c.h + + + i2c.h + + + i2c.c + + + emac.h + + + hw_emac.h + + + hw_emac_ctrl.h + + + hw_mdio.h + + + hw_reg_access.h + + + mdio.h + + + emac.c + + + mdio.c + + + phy_dp83640.c + + + phy_dp83640.h + + + phy_tlk111.c + + + phy_tlk111.h + + + emac_phyConfig.h + + + reg_dcc.h + + + dcc.h + + + dcc.c + + + reg_rtp.h + + + rtp.h + + + + reg_dmm.h + + + dmm.h + + + + reg_emif.h + + + emif.h + + + emif.c + + + reg_pom.h + + + pom.h + + + pom.c + + + reg_crc.h + + + crc.h + + + crc.c + + + reg_etpwm.h + + + etpwm.h + + + etpwm.c + + + reg_ecap.h + + + ecap.h + + + ecap.c + + + reg_eqep.h + + + eqep.h + + + eqep.c + + + Device_RM57.h + + + Device_header.h + + + Device_types.h + + + ti_fee_cfg.h + + + MemMap.h + + + ti_fee_types.h + + + ti_fee.h + + + fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + include\os_projdefs.h + + + include\FreeRTOSConfig.h + + + include\os_portmacro.h + + + include\os_mpu_wrappers.h + + + include\os_portable.h + + + include\FreeRTOS.h + + + include\os_list.h + + + include\os_queue.h + + + include\os_semphr.h + + + include\os_croutine.h + + + include\os_StackMacros.h + + + include\os_task.h + + + include\os_timer.h + + + source\os_port.c + + + source\os_portasm.s + + + source\os_tasks.c + + + source\os_queue.c + + + source\os_list.c + + + source\os_croutine.c + + + source\os_timer.c + + + source\os_mpu_wrappers.c + + + source\os_heap.c + + + source\os_event_groups.c + + + include\os_event_groups.h + + + + + + + include\reg_pinmux.h + + + include\pinmux.h + + + source\pinmux.c + + + + + + + include\reg_gio.h + + + include\gio.h + + + source\gio.c + + + + + + + include\reg_esm.h + + + include\esm.h + + + source\esm.c + + + + + + + include\reg_sci.h + + + include\sci.h + + + source\sci.c + + + + + + + include\reg_lin.h + + + include\lin.h + + + source\lin.c + + + + + + + include\reg_mibspi.h + + + include\mibspi.h + + + source\mibspi.c + + + + + + + include\reg_spi.h + + + include\spi.h + + + + + + + + + + include\reg_can.h + + + include\can.h + + + source\can.c + + + + + + + include\reg_adc.h + + + include\adc.h + + + source\adc.c + + + + + + + include\std_nhet.h + + + include\reg_het.h + + + include\het.h + + + source\het.c + + + include\reg_htu.h + + + include\htu.h + + + + + + + include\reg_i2c.h + + + include\i2c.h + + + source\i2c.c + + + + + + + include\emac.h + + + include\hw_emac.h + + + include\hw_emac_ctrl.h + + + include\hw_mdio.h + + + include\hw_reg_access.h + + + include\mdio.h + + + source\emac.c + + + source\mdio.c + + + source\phy_dp83640.c + + + include\phy_dp83640.h + + + source\phy_tlk111.c + + + include\phy_tlk111.h + + + include\emac_phyConfig.h + + + + + + + include\reg_dcc.h + + + include\dcc.h + + + source\dcc.c + + + + + + + include\reg_rtp.h + + + include\rtp.h + + + + + + + + + + include\reg_dmm.h + + + include\dmm.h + + + + + + + + + + include\reg_emif.h + + + include\emif.h + + + source\emif.c + + + + + + + include\reg_pom.h + + + include\pom.h + + + source\pom.c + + + + + + + include\reg_crc.h + + + include\crc.h + + + source\crc.c + + + + + + + include\reg_etpwm.h + + + include\etpwm.h + + + source\etpwm.c + + + + + + + include\reg_ecap.h + + + include\ecap.h + + + source\ecap.c + + + + + + + include\reg_eqep.h + + + include\eqep.h + + + source\eqep.c + + + + + + + include\Device_RM57.h + + + include\Device_header.h + + + include\Device_types.h + + + include\ti_fee_cfg.h + + + include\MemMap.h + + + include\ti_fee_types.h + + + include\ti_fee.h + + + include\fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml new file mode 100644 index 00000000000..b8ddc17d97a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h new file mode 100644 index 00000000000..b8d0e928377 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h @@ -0,0 +1,114 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_RM57.c + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the number of sectors. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_RM57_H + #define DEVICE_RM57_H + + /** @def DEVICE_CONFIGURATION_VERSION + * @brief Device Configuration Version + * + * @note Indicates the current version of the device files + */ + #define DEVICE_CONFIGURATION_VERSION \ + 0U /* Indicates the current version of the device files */ + + /** @def DEVICE_NUMBER_OF_FLASH_BANKS + * @brief Number of Flash Banks + * + * @note Defines the number of Flash Banks on the device + */ + #define DEVICE_NUMBER_OF_FLASH_BANKS \ + 1U /* Defines the number of Flash Banks on the device */ + + /** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS + * @brief Maximum number of Sectors + * + * @note Defines the maxium number of sectors in all banks + */ + #define DEVICE_BANK_MAX_NUMBER_OF_SECTORS \ + 32U /* Defines the maxium number of sectors in all banks */ + + /** @def DEVICE_BANK1_NUMBER_OF_SECTORS + * @brief Number of Sectors + * + * @note Defines the number of sectors in bank1 + */ + #define DEVICE_BANK1_NUMBER_OF_SECTORS \ + 32U /* Defines the number of sectors in bank1 */ + + /** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS + * @brief Number of Sectors + * + * @note Defines the number of Read Cycle Thresholds + */ + #define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS \ + 4U /* Defines the number of Read Cycle Thresholds */ + + /* Include Files */ + #ifndef _PLATFORM_TYPES_H_ + #define _PLATFORM_TYPES_H_ + #endif + #ifndef _L2FMC + #define _L2FMC + #endif + #include "F021.h" + #include "hal_stdtypes.h" + #include "Device_types.h" + +#endif /* DEVICE_RM57_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h new file mode 100644 index 00000000000..99b1e37ae0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h @@ -0,0 +1,65 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_header.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file includes the header file. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef TI_FEE_DEVICEHEADER_H +#define TI_FEE_DEVICEHEADER_H + +/* Uncomment the appropriate include file depending on the device you are using */ +#include "Device_RM57.h" + +/* End of file */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h new file mode 100644 index 00000000000..96add2784e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h @@ -0,0 +1,133 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the structures. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_TYPES_H + #define DEVICE_TYPES_H + + #include "hal_stdtypes.h" + +/* Enum to describe the type of error handling on the device */ +typedef enum +{ + Device_ErrorHandlingNone, /* Device has no error handling */ + Device_ErrorHandlingParity, /* Device has parity error handling */ + Device_ErrorHandlingEcc /* Device has ECC error handling */ +} Device_FlashErrorCorrectionProcessType; + +/* Enum to describe the ARM core on the device*/ +typedef enum +{ + Device_CoreNone, /* To indicate that the device has a single core */ + Device_Arm7, /* To indicate that the device has a ARM7 core */ + Device_CortexR4, /* To indicate that the device has a CortexR4 core */ + Device_CortexM3 /* To indicate that the device has a CortexM3 core */ +} Device_ArmCoreType; + +/* Structure defines an individual sector within a bank */ +typedef struct +{ + Fapi_FlashSectorType Device_Sector; /* Sector number */ + uint32 Device_SectorStartAddress; /* Starting address of the sector */ + uint32 Device_SectorLength; /* Length of the sector */ + uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */ + uint32 Device_EccAddress; + uint32 Device_EccLength; +} Device_SectorType; + +/* Structure defines an individual bank */ +typedef struct +{ + Fapi_FmcRegistersType * Device_ControlRegister; + Fapi_FlashBankType Device_Core; /* Core number for this bank */ + Device_SectorType Device_SectorInfo[ DEVICE_BANK_MAX_NUMBER_OF_SECTORS ]; /* Array of + the + Sectors + within a + bank */ +} Device_BankType; + +/* Structure defines the Flash structure of the device */ +typedef struct +{ + uint8 Device_DeviceName[ 12 ]; /* Device name */ + uint32 Device_EngineeringId; /* Device Engineering ID */ + Device_FlashErrorCorrectionProcessType + Device_FlashErrorHandlingProcessInfo; /* Indicates + which + type + of bit + Error + handling + is on + the + device + */ + Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device + */ + boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash + interrupts for processing Flash */ + uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS + */ + uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS + */ + Device_BankType Device_BankInfo[ DEVICE_NUMBER_OF_FLASH_BANKS ]; /* Array of Banks on + the device */ +} Device_FlashType; + +#endif /* DEVICE_TYPES_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h new file mode 100644 index 00000000000..8781cbf7be2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h @@ -0,0 +1,39 @@ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MEM_MAP_H__ +#define __MEM_MAP_H__ + +#endif /* __MEM_MAP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h new file mode 100644 index 00000000000..b9d8118372d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h @@ -0,0 +1,344 @@ +/** @file adc.h + * @brief ADC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +#include "reg_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ADC General Definitions */ + +/** @def adcGROUP0 + * @brief Alias name for ADC event group + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP0 0U + +/** @def adcGROUP1 + * @brief Alias name for ADC group 1 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP1 1U + +/** @def adcGROUP2 + * @brief Alias name for ADC group 2 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP2 2U + +/** @def ADC_12_BIT_MODE + * @brief Alias name for ADC 12-bit mode of operation + */ +#define ADC_12_BIT_MODE 0x80000000U + +/** @enum adcResolution + * @brief Alias names for data resolution + * This enumeration is used to provide alias names for the data resolution: + * - 12 bit resolution + * - 10 bit resolution + * - 8 bit resolution + */ + +enum adcResolution +{ + ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */ + ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */ + ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */ +}; + +/** @enum adcFiFoStatus + * @brief Alias names for FiFo status + * This enumeration is used to provide alias names for the current FiFo states: + * - FiFo is not full + * - FiFo is full + * - FiFo overflow occurred + */ + +enum adcFiFoStatus +{ + ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */ + ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */ + ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */ +}; + +/** @enum adcConversionStatus + * @brief Alias names for conversion status + * This enumeration is used to provide alias names for the current conversion states: + * - Conversion is not finished + * - Conversion is finished + */ + +enum adcConversionStatus +{ + ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished + */ + ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */ +}; + +/** @enum adc1HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc1HwTriggerSource +{ + ADC1_EVENT = 0U, /**< Alias for event pin */ + ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + + ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/** @enum adc2HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc2HwTriggerSource +{ + ADC2_EVENT = 0U, /**< Alias for event pin */ + ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct adcData + * @brief ADC Conversion data structure + * + * This type is used to pass adc conversion data. + */ +/** @typedef adcData_t + * @brief ADC Data Type Definition + */ +typedef struct adcData +{ + uint32 id; /**< Channel/Pin Id */ + uint16 value; /**< Conversion data value */ +} adcData_t; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +typedef struct adc_config_reg +{ + uint32 CONFIG_OPMODECR; + uint32 CONFIG_CLOCKCR; + uint32 CONFIG_GxMODECR[ 3U ]; + uint32 CONFIG_G0SRC; + uint32 CONFIG_G1SRC; + uint32 CONFIG_G2SRC; + uint32 CONFIG_BNDCR; + uint32 CONFIG_BNDEND; + uint32 CONFIG_G0SAMP; + uint32 CONFIG_G1SAMP; + uint32 CONFIG_G2SAMP; + uint32 CONFIG_G0SAMPDISEN; + uint32 CONFIG_G1SAMPDISEN; + uint32 CONFIG_G2SAMPDISEN; + uint32 CONFIG_PARCR; +} adc_config_reg_t; + +#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC1_CLOCKCR_CONFIGVALUE ( 7U ) + +#define ADC1_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC1_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC1_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC1_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) + +#define ADC1_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC1_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC1_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC1_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC1_PARCR_CONFIGVALUE ( 0x00000005U ) + +#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC2_CLOCKCR_CONFIGVALUE ( 7U ) + +#define ADC2_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC2_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC2_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC2_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) + +#define ADC2_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC2_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC2_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC2_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC2_PARCR_CONFIGVALUE ( 0x00000005U ) + +/** + * @defgroup ADC ADC + * @brief Analog To Digital Converter Module. + * + * The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit + *resolution + * + * Related Files + * - reg_adc.h + * - adc.h + * - adc.c + * @addtogroup ADC + * @{ + */ + +/* ADC Interface Functions */ + +void adcInit( void ); +void adcStartConversion( adcBASE_t * adc, uint32 group ); +void adcStopConversion( adcBASE_t * adc, uint32 group ); +void adcResetFiFo( adcBASE_t * adc, uint32 group ); +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ); +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ); +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ); +void adcEnableNotification( adcBASE_t * adc, uint32 group ); +void adcDisableNotification( adcBASE_t * adc, uint32 group ); +void adcCalibration( adcBASE_t * adc ); +uint32 adcMidPointCalibration( adcBASE_t * adc ); +void adcSetEVTPin( adcBASE_t * adc, uint32 value ); +uint32 adcGetEVTPin( adcBASE_t * adc ); + +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void adcNotification(adcBASE_t *adc, uint32 group) + * @brief Group notification + * @param[in] adc Pointer to ADC node: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group number of ADC node: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * @note This function has to be provide by the user. + */ +void adcNotification( adcBASE_t * adc, uint32 group ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h new file mode 100644 index 00000000000..d1c122e6712 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h @@ -0,0 +1,926 @@ +/** @file can.h + * @brief CAN Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CAN_H__ +#define __CAN_H__ + +#include "reg_can.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CAN General Definitions */ + +/** @def canLEVEL_ACTIVE + * @brief Alias name for CAN error operation level active (Error counter 0-95) + */ +#define canLEVEL_ACTIVE 0x00U + +/** @def canLEVEL_WARNING + * @brief Alias name for CAN error operation level warning (Error counter 96-127) + */ +#define canLEVEL_WARNING 0x40U + +/** @def canLEVEL_PASSIVE + * @brief Alias name for CAN error operation level passive (Error counter 128-255) + */ +#define canLEVEL_PASSIVE 0x20U + +/** @def canLEVEL_BUS_OFF + * @brief Alias name for CAN error operation level bus off (Error counter 256) + */ +#define canLEVEL_BUS_OFF 0x80U + +/** @def canLEVEL_PARITY_ERR + * @brief Alias name for CAN Parity error (Error counter 256-511) + */ +#define canLEVEL_PARITY_ERR 0x100U + +/** @def canLEVEL_TxOK + * @brief Alias name for CAN Sucessful Transmission + */ +#define canLEVEL_TxOK 0x08U + +/** @def canLEVEL_RxOK + * @brief Alias name for CAN Sucessful Reception + */ +#define canLEVEL_RxOK 0x10U + +/** @def canLEVEL_WakeUpPnd + * @brief Alias name for CAN Initiated a WakeUp to system + */ +#define canLEVEL_WakeUpPnd 0x200U + +/** @def canLEVEL_PDA + * @brief Alias name for CAN entered low power mode successfully. + */ +#define canLEVEL_PDA 0x400U + +/** @def canERROR_NO + * @brief Alias name for no CAN error occurred + */ +#define canERROR_OK 0U + +/** @def canERROR_STUFF + * @brief Alias name for CAN stuff error an RX message + */ +#define canERROR_STUFF 1U + +/** @def canERROR_FORMAT + * @brief Alias name for CAN form/format error an RX message + */ +#define canERROR_FORMAT 2U + +/** @def canERROR_ACKNOWLEDGE + * @brief Alias name for CAN TX message wasn't acknowledged + */ +#define canERROR_ACKNOWLEDGE 3U + +/** @def canERROR_BIT1 + * @brief Alias name for CAN TX message sending recessive level but monitoring dominant + */ +#define canERROR_BIT1 4U + +/** @def canERROR_BIT0 + * @brief Alias name for CAN TX message sending dominant level but monitoring recessive + */ +#define canERROR_BIT0 5U + +/** @def canERROR_CRC + * @brief Alias name for CAN RX message received wrong CRC + */ +#define canERROR_CRC 6U + +/** @def canERROR_NO + * @brief Alias name for CAN no message has send or received since last call of + * CANGetLastError + */ +#define canERROR_NO 7U + +/** @def canMESSAGE_BOX1 + * @brief Alias name for CAN message box 1 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX1 1U + +/** @def canMESSAGE_BOX2 + * @brief Alias name for CAN message box 2 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX2 2U + +/** @def canMESSAGE_BOX3 + * @brief Alias name for CAN message box 3 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX3 3U + +/** @def canMESSAGE_BOX4 + * @brief Alias name for CAN message box 4 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX4 4U + +/** @def canMESSAGE_BOX5 + * @brief Alias name for CAN message box 5 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX5 5U + +/** @def canMESSAGE_BOX6 + * @brief Alias name for CAN message box 6 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX6 6U + +/** @def canMESSAGE_BOX7 + * @brief Alias name for CAN message box 7 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX7 7U + +/** @def canMESSAGE_BOX8 + * @brief Alias name for CAN message box 8 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX8 8U + +/** @def canMESSAGE_BOX9 + * @brief Alias name for CAN message box 9 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX9 9U + +/** @def canMESSAGE_BOX10 + * @brief Alias name for CAN message box 10 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX10 10U + +/** @def canMESSAGE_BOX11 + * @brief Alias name for CAN message box 11 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX11 11U + +/** @def canMESSAGE_BOX12 + * @brief Alias name for CAN message box 12 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX12 12U + +/** @def canMESSAGE_BOX13 + * @brief Alias name for CAN message box 13 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX13 13U + +/** @def canMESSAGE_BOX14 + * @brief Alias name for CAN message box 14 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX14 14U + +/** @def canMESSAGE_BOX15 + * @brief Alias name for CAN message box 15 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX15 15U + +/** @def canMESSAGE_BOX16 + * @brief Alias name for CAN message box 16 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX16 16U + +/** @def canMESSAGE_BOX17 + * @brief Alias name for CAN message box 17 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX17 17U + +/** @def canMESSAGE_BOX18 + * @brief Alias name for CAN message box 18 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX18 18U + +/** @def canMESSAGE_BOX19 + * @brief Alias name for CAN message box 19 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX19 19U + +/** @def canMESSAGE_BOX20 + * @brief Alias name for CAN message box 20 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX20 20U + +/** @def canMESSAGE_BOX21 + * @brief Alias name for CAN message box 21 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX21 21U + +/** @def canMESSAGE_BOX22 + * @brief Alias name for CAN message box 22 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX22 22U + +/** @def canMESSAGE_BOX23 + * @brief Alias name for CAN message box 23 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX23 23U + +/** @def canMESSAGE_BOX24 + * @brief Alias name for CAN message box 24 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX24 24U + +/** @def canMESSAGE_BOX25 + * @brief Alias name for CAN message box 25 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX25 25U + +/** @def canMESSAGE_BOX26 + * @brief Alias name for CAN message box 26 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX26 26U + +/** @def canMESSAGE_BOX27 + * @brief Alias name for CAN message box 27 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX27 27U + +/** @def canMESSAGE_BOX28 + * @brief Alias name for CAN message box 28 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX28 28U + +/** @def canMESSAGE_BOX29 + * @brief Alias name for CAN message box 29 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX29 29U + +/** @def canMESSAGE_BOX30 + * @brief Alias name for CAN message box 30 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX30 30U + +/** @def canMESSAGE_BOX31 + * @brief Alias name for CAN message box 31 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX31 31U + +/** @def canMESSAGE_BOX32 + * @brief Alias name for CAN message box 32 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX32 32U + +/** @def canMESSAGE_BOX33 + * @brief Alias name for CAN message box 33 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX33 33U + +/** @def canMESSAGE_BOX34 + * @brief Alias name for CAN message box 34 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX34 34U + +/** @def canMESSAGE_BOX35 + * @brief Alias name for CAN message box 35 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX35 35U + +/** @def canMESSAGE_BOX36 + * @brief Alias name for CAN message box 36 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX36 36U + +/** @def canMESSAGE_BOX37 + * @brief Alias name for CAN message box 37 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX37 37U + +/** @def canMESSAGE_BOX38 + * @brief Alias name for CAN message box 38 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX38 38U + +/** @def canMESSAGE_BOX39 + * @brief Alias name for CAN message box 39 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX39 39U + +/** @def canMESSAGE_BOX40 + * @brief Alias name for CAN message box 40 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX40 40U + +/** @def canMESSAGE_BOX41 + * @brief Alias name for CAN message box 41 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX41 41U + +/** @def canMESSAGE_BOX42 + * @brief Alias name for CAN message box 42 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX42 42U + +/** @def canMESSAGE_BOX43 + * @brief Alias name for CAN message box 43 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX43 43U + +/** @def canMESSAGE_BOX44 + * @brief Alias name for CAN message box 44 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX44 44U + +/** @def canMESSAGE_BOX45 + * @brief Alias name for CAN message box 45 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX45 45U + +/** @def canMESSAGE_BOX46 + * @brief Alias name for CAN message box 46 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX46 46U + +/** @def canMESSAGE_BOX47 + * @brief Alias name for CAN message box 47 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX47 47U + +/** @def canMESSAGE_BOX48 + * @brief Alias name for CAN message box 48 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX48 48U + +/** @def canMESSAGE_BOX49 + * @brief Alias name for CAN message box 49 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX49 49U + +/** @def canMESSAGE_BOX50 + * @brief Alias name for CAN message box 50 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX50 50U + +/** @def canMESSAGE_BOX51 + * @brief Alias name for CAN message box 51 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX51 51U + +/** @def canMESSAGE_BOX52 + * @brief Alias name for CAN message box 52 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX52 52U + +/** @def canMESSAGE_BOX53 + * @brief Alias name for CAN message box 53 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX53 53U + +/** @def canMESSAGE_BOX54 + * @brief Alias name for CAN message box 54 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX54 54U + +/** @def canMESSAGE_BOX55 + * @brief Alias name for CAN message box 55 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX55 55U + +/** @def canMESSAGE_BOX56 + * @brief Alias name for CAN message box 56 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX56 56U + +/** @def canMESSAGE_BOX57 + * @brief Alias name for CAN message box 57 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX57 57U + +/** @def canMESSAGE_BOX58 + * @brief Alias name for CAN message box 58 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX58 58U + +/** @def canMESSAGE_BOX59 + * @brief Alias name for CAN message box 59 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX59 59U + +/** @def canMESSAGE_BOX60 + * @brief Alias name for CAN message box 60 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX60 60U + +/** @def canMESSAGE_BOX61 + * @brief Alias name for CAN message box 61 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX61 61U + +/** @def canMESSAGE_BOX62 + * @brief Alias name for CAN message box 62 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX62 62U + +/** @def canMESSAGE_BOX63 + * @brief Alias name for CAN message box 63 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX63 63U + +/** @def canMESSAGE_BOX64 + * @brief Alias name for CAN message box 64 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX64 64U + +/** @enum canloopBackType + * @brief canLoopback type definition + */ +/** @typedef canloopBackType_t + * @brief canLoopback type Type Definition + * + * This type is used to select the can module Loopback type Digital or Analog loopback. + */ +typedef enum canloopBackType +{ + Internal_Lbk = 0x00000010U, + External_Lbk = 0x00000100U, + Internal_Silent_Lbk = 0x00000018U +} canloopBackType_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct can_config_reg +{ + uint32 CONFIG_CTL; + uint32 CONFIG_ES; + uint32 CONFIG_BTR; + uint32 CONFIG_TEST; + uint32 CONFIG_ABOTR; + uint32 CONFIG_INTMUX0; + uint32 CONFIG_INTMUX1; + uint32 CONFIG_INTMUX2; + uint32 CONFIG_INTMUX3; + uint32 CONFIG_TIOC; + uint32 CONFIG_RIOC; +} can_config_reg_t; + +/* Configuration registers initial value for CAN1*/ +#define CAN1_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN1_ES_CONFIGVALUE 0x00000007U +#define CAN1_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN1_TEST_CONFIGVALUE 0x00000080U +#define CAN1_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN1_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN1_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN1_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN1_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN2*/ +#define CAN2_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN2_ES_CONFIGVALUE 0x00000007U +#define CAN2_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN2_TEST_CONFIGVALUE 0x00000080U +#define CAN2_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN2_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN2_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN2_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN3*/ +#define CAN3_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN3_ES_CONFIGVALUE 0x00000007U +#define CAN3_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN3_TEST_CONFIGVALUE 0x00000080U +#define CAN3_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN3_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN3_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN3_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN4*/ +#define CAN4_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN4_ES_CONFIGVALUE 0x00000007U +#define CAN4_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN4_TEST_CONFIGVALUE 0x00000080U +#define CAN4_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN4_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN4_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN4_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN4_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN4_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN4_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/** + * @defgroup CAN CAN + * @brief Controller Area Network Module. + * + * The Controller Area Network is a high-integrity, serial, multi-master communication + * protocol for distributed real-time applications. This CAN module is implemented + * according to ISO 11898-1 and is suitable for industrial, automotive and general + * embedded communications + * + * Related Files + * - reg_can.h + * - can.h + * - can.c + * @addtogroup CAN + * @{ + */ + +/* CAN Interface Functions */ + +void canInit( void ); +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ); +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ); +uint32 canGetID( canBASE_t * node, uint32 messageBox ); +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ); +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ); +uint32 canFillMessageObjectData( canBASE_t * node, + uint32 messageBox, + const uint8 * data ); +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ); +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ); +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ); +uint32 canGetLastError( canBASE_t * node ); +uint32 canGetErrorLevel( canBASE_t * node ); +void canEnableErrorNotification( canBASE_t * node ); +void canDisableErrorNotification( canBASE_t * node ); +void canEnableStatusChangeNotification( canBASE_t * node ); +void canDisableStatusChangeNotification( canBASE_t * node ); +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ); +void canDisableloopback( canBASE_t * node ); +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ); +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ); +uint32 canIoTxGetBit( canBASE_t * node ); +uint32 canIoRxGetBit( canBASE_t * node ); +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +/** @fn void canErrorNotification(canBASE_t *node, uint32 notification) + * @brief Error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Error notification code: + * - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 + * and 63 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256 + * + * @note This function has to be provide by the user. + */ +void canErrorNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification) + * @brief Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Status change notification code: + * - canLEVEL_TxOK (0x08) : When sucessful transmission + * - canLEVEL_RxOK (0x10) : When sucessful reception + * - canLEVEL_WakeUpPnd (0x200): When sucessful WakeUp to system initiated + * - canLEVEL_PDA (0x400): When sucessful low power mode entrance + * + * @note This function has to be provide by the user. + */ +void canStatusChangeNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox) + * @brief Message notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * + * @note This function has to be provide by the user. + */ +void canMessageNotification( canBASE_t * node, uint32 messageBox ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h new file mode 100644 index 00000000000..28291143d45 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h @@ -0,0 +1,344 @@ +/** @file crc.h + * @brief CRC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + +#include "reg_crc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CRC General Definitions */ + +/** @def CRCLEVEL_ACTIVE + * @brief Alias name for CRC error operation level active + */ +#define CRCLEVEL_ACTIVE 0x00U + +/** @def CRC_AUTO + * @brief Alias name for CRC auto mode + */ +#define CRC_AUTO 0x00000001U + +/** @def CRC_SEMI_CPU + * @brief Alias name for semi cpu mode setting + */ +#define CRC_SEMI_CPU 0x00000002U + +/** @def CRC_FULL_CPU + * @brief Alias name for CRC cpu full mode + */ +#define CRC_FULL_CPU 0x00000003U + +/** @def CRC_CH4_TO + * @brief Alias name for channel4 time out interrupt flag + */ +#define CRC_CH4_TO 0x10000000U + +/** @def CRC_CH4_UR + * @brief Alias name for channel4 underrun interrupt flag + */ +#define CRC_CH4_UR 0x08000000U + +/** @def CRC_CH4_OR + * @brief Alias name for channel4 overrun interrupt flag + */ +#define CRC_CH4_OR 0x04000000U + +/** @def CRC_CH4_FAIL + * @brief Alias name for channel4 crc fail interrupt flag + */ +#define CRC_CH4_FAIL 0x02000000U + +/** @def CRC_CH4_CC + * @brief Alias name for channel4 compression complete interrupt flag + */ +#define CRC_CH4_CC 0x01000000U + +/** @def CRC_CH3_TO + * @brief Alias name for channel3 time out interrupt flag + */ +#define CRC_CH3_TO 0x00100000U + +/** @def CRC_CH3_UR + * @brief Alias name for channel3 underrun interrupt flag + */ +#define CRC_CH3_UR 0x00080000U + +/** @def CRC_CH3_OR + * @brief Alias name for channel3 overrun interrupt flag + */ +#define CRC_CH3_OR 0x00040000U + +/** @def CRC_CH3_FAIL + * @brief Alias name for channel3 crc fail interrupt flag + */ +#define CRC_CH3_FAIL 0x00020000U + +/** @def CRC_CH3_CC + * @brief Alias name for channel3 compression complete interrupt flag + */ +#define CRC_CH3_CC 0x00010000U + +/** @def CRC_CH2_TO + * @brief Alias name for channel2 time out interrupt flag + */ +#define CRC_CH2_TO 0x00001000U + +/** @def CRC_CH2_UR + * @brief Alias name for channel2 underrun interrupt flag + */ +#define CRC_CH2_UR 0x00000800U + +/** @def CRC_CH2_OR + * @brief Alias name for channel2 overrun interrupt flag + */ +#define CRC_CH2_OR 0x00000400U + +/** @def CRC_CH2_FAIL + * @brief Alias name for channel2 crc fail interrupt flag + */ +#define CRC_CH2_FAIL 0x00000200U + +/** @def CRC_CH2_CC + * @brief Alias name for channel2 compression complete interrupt flag + */ +#define CRC_CH2_CC 0x00000100U + +/** @def CRC_CH1_TO + * @brief Alias name for channel1 time out interrupt flag + */ +#define CRC_CH1_TO 0x00000010U + +/** @def CRC_CH1_UR + * @brief Alias name for channel1 underrun interrupt flag + */ +#define CRC_CH1_UR 0x00000008U + +/** @def CRC_CH1_OR + * @brief Alias name for channel1 overrun interrupt flag + */ +#define CRC_CH1_OR 0x00000004U + +/** @def CRC_CH1_FAIL + * @brief Alias name for channel1 crc fail interrupt flag + */ +#define CRC_CH1_FAIL 0x00000002U + +/** @def CRC_CH1_CC + * @brief Alias name for channel1 compression complete interrupt flag + */ +#define CRC_CH1_CC 0x00000001U + +/** @def CRC_CH1 + * @brief Alias name for channel1 + */ +#define CRC_CH1 0x00000000U + +/** @def CRC_CH1 + * @brief Alias name for channel2 + */ +#define CRC_CH2 0x00000001U + +/** @def CRC_CH3 + * @brief Alias name for channel3 + */ +#define CRC_CH3 0x00000002U + +/** @def CRC_CH4 + * @brief Alias name for channel4 + */ +#define CRC_CH4 0x00000003U + +/** @struct crcModConfig + * @brief CRC mode specific parameters + * + * This type is used to pass crc mode specific parameters + */ +/** @typedef crcModConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcModConfig +{ + uint32 mode; /**< Mode of operation */ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint64 * src_data_pat; /**< Pattern data */ + uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/ +} crcModConfig_t; + +/** @struct crcConfig + * @brief CRC configuration for different modes + * + * This type is used to pass crc configuration + */ +/** @typedef crcConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcConfig +{ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint32 mode; /**< Mode of operation */ + uint32 pcount; /**< Pattern count*/ + uint32 scount; /**< Sector count */ + uint32 wdg_preload; /**< Watchdog period */ + uint32 block_preload; /**< Block period*/ + +} crcConfig_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +typedef struct crc_config_reg +{ + uint32 CONFIG_CTRL0; + uint32 CONFIG_CTRL1; + uint32 CONFIG_CTRL2; + uint32 CONFIG_INTS; + uint32 CONFIG_PCOUNT_REG1; + uint32 CONFIG_SCOUNT_REG1; + uint32 CONFIG_WDTOPLD1; + uint32 CONFIG_BCTOPLD1; + uint32 CONFIG_PCOUNT_REG2; + uint32 CONFIG_SCOUNT_REG2; + uint32 CONFIG_WDTOPLD2; + uint32 CONFIG_BCTOPLD2; +} crc_config_reg_t; + +#define CRC1_CTRL0_CONFIGVALUE 0x00000000U +#define CRC1_CTRL1_CONFIGVALUE 0x00000000U +#define CRC1_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC1_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC1_PCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_SCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_WDTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_BCTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_PCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_SCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_WDTOPLD2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_BCTOPLD2_CONFIGVALUE ( 0x00000000U ) + +#define CRC2_CTRL0_CONFIGVALUE 0x00000000U +#define CRC2_CTRL1_CONFIGVALUE 0x00000000U +#define CRC2_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC2_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC2_PCOUNT_REG1_CONFIGVALUE ( 0U ) +#define CRC2_SCOUNT_REG1_CONFIGVALUE ( 0U ) +#define CRC2_WDTOPLD1_CONFIGVALUE ( 0U ) +#define CRC2_BCTOPLD1_CONFIGVALUE ( 0U ) +#define CRC2_PCOUNT_REG2_CONFIGVALUE ( 0U ) +#define CRC2_SCOUNT_REG2_CONFIGVALUE ( 0U ) +#define CRC2_WDTOPLD2_CONFIGVALUE ( 0U ) +#define CRC2_BCTOPLD2_CONFIGVALUE ( 0U ) + +/** + * @defgroup CRC CRC + * @brief Cyclic Redundancy Check Controller Module. + * + * The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) + * to verify the integrity of memory system. A signature representing the contents of the + * memory is obtained when the contents of the memory are read into CRC controller. The + * responsibility of CRC controller is to calculate the signature for a set of data and + * then compare the calculated signature value against a pre-determined good signature + * value. CRC controller supports two channels to perform CRC calculation on multiple + * memories in parallel and can be used on any memory system. + * + * Related Files + * - reg_crc.h + * - crc.h + * - crc.c + * @addtogroup CRC + * @{ + */ + +/* CRC Interface Functions */ +void crcInit( void ); +void crcSendPowerDown( crcBASE_t * crc ); +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ); +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ); +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ); +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ); +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ); +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ); +void crcChannelReset( crcBASE_t * crc, uint32 channel ); +void crcEnableNotification( crcBASE_t * crc, uint32 flags ); +void crcDisableNotification( crcBASE_t * crc, uint32 flags ); +void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); +void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void crcNotification(crcBASE_t *crc, uint32 flags) + * @brief Interrupt callback + * @param[in] crc - crc module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void crcNotification( crcBASE_t * crc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h new file mode 100644 index 00000000000..d53db2648be --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h @@ -0,0 +1,353 @@ +/** @file dcc.h + * @brief DCC Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DCC_H__ +#define __DCC_H__ + +#include "reg_dcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DCC General Definitions */ + +/** @def dcc1CNT0_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 0 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U + +/** @def dcc1CNT0_CLKSRC_TCK + * @brief Alias name for DCC1 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc1CNT1_CLKSRC_PLL1 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL1 + * + * This is an alias name for the Clock Source PLL for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U + +/** @def dcc1CNT1_CLKSRC_PLL2 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL2 + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U + +/** @def dcc1CNT1_CLKSRC_LFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source LFLPO + * + * This is an alias name for the Clock Source LFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U + +/** @def dcc1CNT1_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN1 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1 + * + * This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN2 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2 + * + * This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U + +/** @def dcc1CNT1_CLKSRC_VCLK + * @brief Alias name for DCC1 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc1CNT1_CLKSRC_N2HET1_31 + * @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31 + * + * This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU + +/** @def dcc2CNT0_CLKSRC_TCK + * @brief Alias name for DCC2 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc2CNT1_CLKSRC_VCLK + * @brief Alias name for DCC2 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc2CNT1_CLKSRC_ODCLK8 + * @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/8 + * + * This is an alias name for the Clock Source PLL2_post_ODCLK/8 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_ODCLK8 0x0000A001U + +/** @def dcc2CNT1_CLKSRC_ODCLK16 + * @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/16 + * + * This is an alias name for the Clock Source PLL2_post_ODCLK/16 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_ODCLK16 0x0000A002U + +/** @def dcc2CNT1_CLKSRC_N2HET1_0 + * @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0 + * + * This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU + +/** @def dccNOTIFICATION_DONE + * @brief Alias name for DCC Done notification + * + * This is an alias name for the DCC Done notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_DONE 0x0000A000U + +/** @def dccNOTIFICATION_ERROR + * @brief Alias name for DCC Error notification + * + * This is an alias name for the DCC Error notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_ERROR 0x000000A0U + +/** @enum dcc1clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc1clocksource +{ + DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/ + DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/ + DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/ + DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/ + DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/ + DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/** @enum dcc2clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc2clocksource +{ + DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC2_CNT1_ODCLK8 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC2_CNT1_ODCLK16 = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/* Configuration registers */ +typedef struct dcc_config_reg +{ + uint32 CONFIG_GCTRL; + uint32 CONFIG_CNT0SEED; + uint32 CONFIG_VALID0SEED; + uint32 CONFIG_CNT1SEED; + uint32 CONFIG_CNT1CLKSRC; + uint32 CONFIG_CNT0CLKSRC; +} dcc_config_reg_t; + +/* Configuration registers initial value */ +#define DCC1_GCTRL_CONFIGVALUE \ + ( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) ) +#define DCC1_CNT0SEED_CONFIGVALUE 39204U +#define DCC1_VALID0SEED_CONFIGVALUE 792U +#define DCC1_CNT1SEED_CONFIGVALUE 742500U +#define DCC1_CNT1CLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 10U << 12U ) | ( uint32 ) DCC1_CNT1_PLL1 ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define DCC1_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC1_CNT0_OSCIN ) + +#define DCC2_GCTRL_CONFIGVALUE \ + ( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) ) +#define DCC2_CNT0SEED_CONFIGVALUE 0U +#define DCC2_VALID0SEED_CONFIGVALUE 0U +#define DCC2_CNT1SEED_CONFIGVALUE 0U +#define DCC2_CNT1CLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | ( uint32 ) DCC2_CNT1_VCLK ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define DCC2_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC2_CNT0_OSCIN ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** + * @defgroup DCC DCC + * @brief Dual-Clock Comparator Module + * + * The primary purpose of a DCC module is to measure the frequency of a clock signal + * using a second known clock signal as a reference. This capability can be used to ensure + * the correct frequency range for several different device clock sources, thereby + * enhancing the system safety metrics. + * + * Related Files + * - reg_dcc.h + * - dcc.h + * - dcc .c + * @addtogroup DCC + * @{ + */ + +/* DCC Interface Functions */ +void dccInit( void ); +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ); +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ); +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ); +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ); +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ); +void dccEnable( dccBASE_t * dcc ); +void dccDisable( dccBASE_t * dcc ); +uint32 dccGetErrStatus( dccBASE_t * dcc ); + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ); +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ); +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags) + * @brief Interrupt callback + * @param[in] dcc - dcc module base address + * @param[in] flags - status flags + * + * This is a callback function provided by the application. It is call when + * a dcc is complete or detected error. + */ +void dccNotification( dccBASE_t * dcc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h new file mode 100644 index 00000000000..306c304460f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h @@ -0,0 +1,164 @@ +/** @file dmm.h + * @brief DMM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DMM_H__ +#define __DMM_H__ + +#include "reg_dmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct dmm_config_reg +{ + uint32 CONFIG_PC0; + uint32 CONFIG_PC1; + uint32 CONFIG_PC3; + uint32 CONFIG_PC6; + uint32 CONFIG_PC7; + uint32 CONFIG_PC8; +} dmm_config_reg_t; + +#define DMM_PC3_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC1_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +#define DMM_PC6_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC8_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +#define DMM_PC7_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC0_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +/** + * @defgroup DMM DMM + * @brief Data Modification Module. + * + * The DMM module provides the capability to modify data in the entire 4 GB address space + *of the device from an external peripheral, with minimal interruption of the application. + * + * Related Files + * - reg_dmm.h + * - dmm.h + * - dmm.c + * @addtogroup DMM + * @{ + */ +/* DMM Interface Functions */ + +void dmmInit( void ); +void dmmGetConfigValue( dmm_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h new file mode 100644 index 00000000000..8400703d3e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h @@ -0,0 +1,347 @@ +/** @file ecap.h + * @brief ECAP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#include "reg_ecap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @brief Enumeration to define the capture (CAP) interrupts + */ +typedef enum +{ + ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */ + ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */ + ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */ + ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */ + ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */ + ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */ + ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */ + ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */ + ecapInt_All = 0x00FFU /*< Denotes All interrupts */ +} ecapInterrupt_t; + +/** @brief Enumeration to define the capture (CAP) prescaler values + */ +typedef enum +{ + ecapPrescale_By_1 = ( ( uint16 ) 0U << 9U ), /*< Divide by 1 */ + ecapPrescale_By_2 = ( ( uint16 ) 1U << 9U ), /*< Divide by 2 */ + ecapPrescale_By_4 = ( ( uint16 ) 2U << 9U ), /*< Divide by 4 */ + ecapPrescale_By_6 = ( ( uint16 ) 3U << 9U ), /*< Divide by 6 */ + ecapPrescale_By_8 = ( ( uint16 ) 4U << 9U ), /*< Divide by 8 */ + ecapPrescale_By_10 = ( ( uint16 ) 5U << 9U ), /*< Divide by 10 */ + ecapPrescale_By_12 = ( ( uint16 ) 6U << 9U ), /*< Divide by 12 */ + ecapPrescale_By_14 = ( ( uint16 ) 7U << 9U ), /*< Divide by 14 */ + ecapPrescale_By_16 = ( ( uint16 ) 8U << 9U ), /*< Divide by 16 */ + ecapPrescale_By_18 = ( ( uint16 ) 9U << 9U ), /*< Divide by 18 */ + ecapPrescale_By_20 = ( ( uint16 ) 10U << 9U ), /*< Divide by 20 */ + ecapPrescale_By_22 = ( ( uint16 ) 11U << 9U ), /*< Divide by 22 */ + ecapPrescale_By_24 = ( ( uint16 ) 12U << 9U ), /*< Divide by 24 */ + ecapPrescale_By_26 = ( ( uint16 ) 13U << 9U ), /*< Divide by 26 */ + ecapPrescale_By_28 = ( ( uint16 ) 14U << 9U ), /*< Divide by 28 */ + ecapPrescale_By_30 = ( ( uint16 ) 15U << 9U ), /*< Divide by 30 */ + ecapPrescale_By_32 = ( ( uint16 ) 16U << 9U ), /*< Divide by 32 */ + ecapPrescale_By_34 = ( ( uint16 ) 17U << 9U ), /*< Divide by 34 */ + ecapPrescale_By_36 = ( ( uint16 ) 18U << 9U ), /*< Divide by 36 */ + ecapPrescale_By_38 = ( ( uint16 ) 19U << 9U ), /*< Divide by 38 */ + ecapPrescale_By_40 = ( ( uint16 ) 20U << 9U ), /*< Divide by 40 */ + ecapPrescale_By_42 = ( ( uint16 ) 21U << 9U ), /*< Divide by 42 */ + ecapPrescale_By_44 = ( ( uint16 ) 22U << 9U ), /*< Divide by 44 */ + ecapPrescale_By_46 = ( ( uint16 ) 23U << 9U ), /*< Divide by 46 */ + ecapPrescale_By_48 = ( ( uint16 ) 24U << 9U ), /*< Divide by 48 */ + ecapPrescale_By_50 = ( ( uint16 ) 25U << 9U ), /*< Divide by 50 */ + ecapPrescale_By_52 = ( ( uint16 ) 26U << 9U ), /*< Divide by 52 */ + ecapPrescale_By_54 = ( ( uint16 ) 27U << 9U ), /*< Divide by 54 */ + ecapPrescale_By_56 = ( ( uint16 ) 28U << 9U ), /*< Divide by 56 */ + ecapPrescale_By_58 = ( ( uint16 ) 29U << 9U ), /*< Divide by 58 */ + ecapPrescale_By_60 = ( ( uint16 ) 30U << 9U ), /*< Divide by 60 */ + ecapPrescale_By_62 = ( ( uint16 ) 31U << 9U ) /*< Divide by 62 */ +} ecapPrescale_t; + +/** @brief Enumeration to define the Sync Out options + */ +typedef enum +{ + SyncOut_SyncIn = ( ( uint16 ) 0U << 6U ), /*< Sync In used for Sync Out */ + SyncOut_CTRPRD = ( ( uint16 ) 1U << 6U ), /*< CTR = PRD used for Sync Out */ + SyncOut_None = ( ( uint16 ) 2U << 6U ) /*< Disables Sync Out */ +} ecapSyncOut_t; + +/** @brief Enumeration to define the Polarity + */ +typedef enum +{ + RISING_EDGE = 0U, + FALLING_EDGE = 1U +} ecapEdgePolarity_t; + +typedef enum +{ + ACTIVE_HIGH = 0U, + ACTIVE_LOW = 1U +} ecapAPWMPolarity_t; + +/** @brief Enumeration to define the Mode of operation + */ +typedef enum +{ + CONTINUOUS = 0U, + ONE_SHOT = 1U +} ecapMode_t; + +/** @brief Enumeration to define the capture events + */ +typedef enum +{ + CAPTURE_EVENT1 = 0U, + CAPTURE_EVENT2 = 1U, + CAPTURE_EVENT3 = 2U, + CAPTURE_EVENT4 = 3U +} ecapEvent_t; + +typedef enum +{ + RESET_ENABLE = 1U, + RESET_DISABLE = 0U +} ecapReset_t; + +typedef struct ecap_config_reg +{ + uint32 CONFIG_CTRPHS; + uint16 CONFIG_ECCTL1; + uint16 CONFIG_ECCTL2; + uint16 CONFIG_ECEINT; +} ecap_config_reg_t; + +#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP1_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP1_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP1_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP2_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP2_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP2_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP3_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP3_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP3_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP4_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP4_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP4_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP5_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP5_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP5_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP6_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP6_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP6_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) +/** + * @defgroup eCAP eCAP + * @brief Enhanced Capture Module. + * + * The enhanced Capture (eCAP) module is essential in systems where accurate timing of + *external events is important. This microcontroller implements 6 instances of the eCAP + *module. + * + * Related Files + * - reg_ecap.h + * - ecap.h + * - ecap.c + * @addtogroup eCAP + * @{ + */ +void ecapInit( void ); +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ); +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ); +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ); +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ); +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ); +void ecapEnableCapture( ecapBASE_t * ecap ); +void ecapDisableCapture( ecapBASE_t * ecap ); +void ecapStartCounter( ecapBASE_t * ecap ); +void ecapStopCounter( ecapBASE_t * ecap ); +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ); +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ); +void ecapDisableAPWMMode( ecapBASE_t * ecap ); +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ); +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ); +uint32 ecapGetCAP1( ecapBASE_t * ecap ); +uint32 ecapGetCAP2( ecapBASE_t * ecap ); +uint32 ecapGetCAP3( ecapBASE_t * ecap ); +uint32 ecapGetCAP4( ecapBASE_t * ecap ); +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); + +/** @brief Interrupt callback + * @param[in] ecap Handle to CAP object + * @param[in] flags Copy of interrupt flags + */ +void ecapNotification( ecapBASE_t * ecap, uint16 flags ); + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /*end of _CAP_H_ definition */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h new file mode 100644 index 00000000000..11b377794cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h @@ -0,0 +1,438 @@ +/** + * \file emac.h + * + * \brief EMAC APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __EMAC_H__ +#define __EMAC_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "hw_reg_access.h" +#include "hw_emac.h" +#include "hw_emac_ctrl.h" +#include "mdio.h" +#include "emac_phyConfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/*****************************************************************************/ +/* +** Macros which can be used as speed parameter to the API EMACRMIISpeedSet +*/ +#define EMAC_RMIISPEED_10MBPS ( 0x00000000U ) +#define EMAC_RMIISPEED_100MBPS ( 0x00008000U ) + +/* Macros for enabling taken as inputs from HALCoGen GUI. */ +#define EMAC_TX_ENABLE ( 1U ) +#define EMAC_RX_ENABLE ( 1U ) +#define EMAC_MII_ENABLE ( 1U ) +#define EMAC_FULL_DUPLEX_ENABLE ( 1U ) +#define EMAC_LOOPBACK_ENABLE ( 0U ) +#define EMAC_BROADCAST_ENABLE ( 1U ) +#define EMAC_UNICAST_ENABLE ( 1U ) +#define EMAC_CHANNELNUMBER ( 0U ) +#define EMAC_PHYADDRESS ( 1U ) + +/* + * Macros to indicate EMAC Channel Numbers + */ +#define EMAC_CHANNEL_0 ( 0x00000000U ) +#define EMAC_CHANNEL_1 ( 0x00000001U ) +#define EMAC_CHANNEL_2 ( 0x00000002U ) +#define EMAC_CHANNEL_3 ( 0x00000003U ) +#define EMAC_CHANNEL_4 ( 0x00000004U ) +#define EMAC_CHANNEL_5 ( 0x00000005U ) +#define EMAC_CHANNEL_6 ( 0x00000006U ) +#define EMAC_CHANNEL_7 ( 0x00000007U ) +/* Macros which can be used as duplexMode parameter to the API +** EMACDuplexSet +*/ +#define EMAC_DUPLEX_FULL ( 0x00000001U ) +#define EMAC_DUPLEX_HALF ( 0x00000000U ) + +/* +** Macros which can be used as matchFilt parameters to the API +** EMACMACAddrSet +*/ +/* Address not used to match/filter incoming packets */ +#define EMAC_MACADDR_NO_MATCH_NO_FILTER ( 0x00000000U ) + +/* Address will be used to filter incoming packets */ +#define EMAC_MACADDR_FILTER ( 0x00100000U ) + +/* Address will be used to match incoming packets */ +#define EMAC_MACADDR_MATCH ( 0x00180000U ) + +/* +** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API +*/ +#define EMAC_INT_CORE0_RX ( 0x1U ) +#define EMAC_INT_CORE1_RX ( 0x5U ) +#define EMAC_INT_CORE2_RX ( 0x9U ) + +/* +** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API +*/ +#define EMAC_INT_CORE0_TX ( 0x2U ) +#define EMAC_INT_CORE1_TX ( 0x6U ) +#define EMAC_INT_CORE2_TX ( 0xAU ) +/* Base Addresses */ +#define EMAC_CTRL_RAM_0_BASE 0xFC520000U +#define EMAC_0_BASE 0xFCF78000U +#define EMAC_CTRL_0_BASE 0xFCF78800U +#define MDIO_0_BASE 0xFCF78900U + +/*MAC address length*/ +#define EMAC_HWADDR_LEN 6U +#define MAX_EMAC_INSTANCE 1U +#define SIZE_EMAC_CTRL_RAM 0x2000U +#define MAX_TRANSFER_UNIT 1514U +#define MAX_RX_PBUF_ALLOC ( 10U ) +#define MIN_PKT_LEN 60U +#define MIN_PACKET_SIZE ( 46U ) + +#define EMAC_BUF_DESC_OWNER 0x20000000U +#define EMAC_BUF_DESC_SOP 0x80000000U +#define EMAC_BUF_DESC_EOP 0x40000000U +#define EMAC_BUF_DESC_EOQ 0x10000000U + +#define EMAC_NETSTATREGS( n ) ( ( uint32 ) 0x200U + ( uint32 ) ( ( n ) * 4U ) ) + +/* Error Signalling Macros */ +#define EMAC_ERR_CONNECT 0x2U /* Not connected. */ +#define EMAC_ERR_OK 0x1U /* No error, everything OK. */ + +/* Macros for Configuration Value Registers */ +#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_MACSRCADDRHI_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 24U ) | ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MACSRCADDRLO_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU +#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U +#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U + +/* Structure to store pending status from the Tx Interrupt Status Registers. */ +typedef struct emac_tx_int_status +{ + volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit + Interrupt Status (Masked) Register (TXINTSTATMASKED) + */ + volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit + Interrupt Status (Unmasked) Register (TXINTSTATRAW) */ +} emac_tx_int_status_t; + +/* Structure to store pending status from the Rx Interrupt Status Registers. */ +typedef struct emac_rx_int_status +{ + volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the + Receive Interrupt Status (Unmasked) + Register (RXINTSTATRAW) */ + + volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive + Interrupt Status (Unmasked) Register + (RXINTSTATRAW) */ + +} emac_rx_int_status_t; + +/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure.*/ +typedef struct emac_tx_bd +{ + volatile struct emac_tx_bd * next; + volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be + transmitted. */ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_tx_bd_t; + +/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure. */ +typedef struct emac_rx_bd +{ + volatile struct emac_rx_bd * next; /*Used as a pointer for next element in the linked + list of descriptors.*/ + volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received + data.*/ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_rx_bd_t; + +/** + * Helper struct to hold the data used to operate on a particular + * receive channel + */ +typedef struct rxch_struct +{ + volatile emac_rx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can receive new data.*/ + volatile emac_rx_bd_t * active_head; /*Used to point to the active descriptor in the + chain which is receiving.*/ + volatile emac_rx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ +} rxch_t; + +/** + * Helper struct to hold the data used to operate on a particular + * transmit channel + */ +typedef struct txch_struct +{ + volatile emac_tx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can transmit new data.*/ + volatile emac_tx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ + volatile emac_tx_bd_t * next_bd_to_process; /*Used to point to the next descriptor in + the chain to be processed.*/ +} txch_t; +/** + * Helper struct to hold private data used to operate the ethernet interface. + */ +typedef struct hdkif_struct +{ + /* MAC Address of the Module. */ + uint8_t mac_addr[ 6 ]; + + /* emac base address */ + uint32 emac_base; + + /* emac controller base address */ + volatile uint32 emac_ctrl_base; + volatile uint32 emac_ctrl_ram; + + /* mdio base address */ + volatile uint32 mdio_base; + + /* phy parameters for this instance - for future use */ + uint32 phy_addr; + boolean ( *phy_autoneg )( uint32 param1, uint32 param2, uint16 param3 ); + boolean ( *phy_partnerability )( uint32 param4, uint32 param5, uint16 * param6 ); + + /* The tx/rx channels for the interface */ + txch_t txchptr; + rxch_t rxchptr; +} hdkif_t; + +/*Ethernet Frame Structure */ +typedef struct ethernet_frame +{ + uint8 dest_addr[ 6 ]; /* Destination MAC Address */ + uint8 src_addr[ 6 ]; /*Source MAC Address. */ + uint16 frame_length; /* Data Frame Length */ + uint8 data[ 1500 ]; /* Data */ +} ethernet_frame_t; + +/* Struct used to take packet data input from the user for transmit APIs. */ +typedef struct pbuf_struct +{ + /** next pbuf in singly linked pbuf chain */ + struct pbuf_struct * next; + + /** + * Pointer to the actual ethernet packet/packet fragment to be transmitted. + * The packet needs to be in the following format: + * |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2 + *bytes)| Data (46- 1500 bytes) The data can be split up over multiple pbufs which are + *linked as a linked list. + **/ + uint8 * payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + uint16 tot_len; + + /** length of this buffer */ + uint16 len; + +} pbuf_t; + +/* Structure to hold the values of the EMAC Configuration Registers. */ +typedef struct emac_config_reg_struct +{ + /* EMAC Module Register Values */ + uint32 TXCONTROL; /* Transmit Control Register. */ + uint32 RXCONTROL; /* Receive Control Register */ + uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */ + uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */ + uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */ + uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/ + uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/ + uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/ + + /*MDIO Module Registers */ + uint32 MDIOCONTROL; /*MDIO Control Register. */ + + /* EMAC Control Module Registers */ + uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ +} emac_config_reg_t; +/*****************************************************************************/ +/** + * @defgroup EMACMDIO EMAC/MDIO + * @brief Ethernet Media Access Controller/Management Data Input/Output. + * + * The EMAC controls the flow of packet data from the system to the PHY. The MDIO module + *controls PHY configuration and status monitoring. + * + * Both the EMAC and the MDIO modules interface to the system core through a custom + *interface that allows efficient data transmission and reception. This custom interface + *is referred to as the EMAC control module and is considered integral to the EMAC/MDIO + *peripheral + * + * Related Files + * - emac.h + * - emac.c + * - hw_emac.h + * - hw_emac_ctrl.h + * - hw_mdio.h + * - hw_reg_access.h + * - mdio.h + * - mdio.c + * @addtogroup EMACMDIO + * @{ + */ +/* +** Prototypes for the APIs +*/ +extern uint32 EMACLinkSetup( hdkif_t * hdkif ); +extern void EMACInstConfig( hdkif_t * hdkif ); +extern void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ); +extern void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ); +extern void EMACTxEnable( uint32 emacBase ); +extern void EMACTxDisable( uint32 emacBase ); +extern void EMACRxEnable( uint32 emacBase ); +extern void EMACRxDisable( uint32 emacBase ); +uint32 EMACSwizzleData( uint32 word ); +extern void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACInit( uint32 emacCtrlBase, uint32 emacBase ); +extern void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ); +extern void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ); +extern void EMACMIIEnable( uint32 emacBase ); +extern void EMACMIIDisable( uint32 emacBase ); +extern void EMACRxUnicastSet( uint32 emacBase, uint32 channel ); +extern void EMACRxUnicastClear( uint32 emacBase, uint32 channel ); +extern void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ); +extern void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ); +extern uint32 EMACIntVectorGet( uint32 emacBase ); +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ); +void EMACTxTeardown( uint32 emacBase, uint32 channel ); +void EMACRxTeardown( uint32 emacBase, uint32 channel ); +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ); +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ); +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ); +void EMACEnableIdleState( uint32 emacBase ); +void EMACDisableIdleState( uint32 emacBase ); +void EMACEnableLoopback( uint32 emacBase ); +void EMACDisableLoopback( uint32 emacBase ); +void EMACTxFlowControlEnable( uint32 emacBase ); +void EMACTxFlowControlDisable( uint32 emacBase ); +void EMACRxFlowControlEnable( uint32 emacBase ); +void EMACRxFlowControlDisable( uint32 emacBase ); +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ); +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ); +void EMACDMAInit( hdkif_t * hdkif ); +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ); +void EMACTxIntHandler( hdkif_t * hdkif ); +void EMACReceive( hdkif_t * hdkif ); +/* Notification Function to which received packets are passed after processing */ +void emacTxNotification( hdkif_t * hdkif ); +void emacRxNotification( hdkif_t * hdkif ); +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ); +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ); +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __EMAC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h new file mode 100644 index 00000000000..035722af057 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h @@ -0,0 +1,45 @@ +/** + * \file emac_phyConfig.h + * + * \brief PHY Configuration file for selecting and configuring the required PHY. + * + * This file contains the mappings of the PHY APIs so that the right one is chosen based + * on the user's preference. + */ + +/* (c) Texas Instruments 2009-2014, All rights reserved. */ + +#ifndef _EMAC_PHYCONFIG_H_ +#define _EMAC_PHYCONFIG_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define PhyIDGet Dp83640IDGet +#define PhyLinkStatusGet Dp83640LinkStatusGet +#define PhyAutoNegotiate Dp83640AutoNegotiate +#define PhyPartnerAbilityGet Dp83640PartnerAbilityGet +#define PhyReset Dp83640Reset +#define PhyEnableLoopback Dp83640EnableLoopback +#define PhyDisableLoopback Dp83640DisableLoopback +#define PhyGetTimeStamp Dp83640GetTimeStamp +#define PhyPartnerSpdGet Dp83640PartnerSpdGet + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* _EMAC_PHYCONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h new file mode 100644 index 00000000000..8e65dcacc63 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h @@ -0,0 +1,216 @@ +/** @file emif.h + * @brief emif Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ + +#include "reg_emif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum emif_pins + * @brief Alias for emif pins + * + */ +enum emif_pins +{ + emif_wait_pin0 = 0U, + emif_wait_pin1 = 1U +}; + +/** @enum emif_size + * @brief Alias for emif page size + * + */ +enum emif_size +{ + elements_256 = 0U, + elements_512 = 1U, + elements_1024 = 2U, + elements_2048 = 3U +}; + +/** @enum emif_port + * @brief Alias for emif port + * + */ +enum emif_port +{ + emif_8_bit_port = 0U, + emif_16_bit_port = 1U +}; + +/** @enum emif_pagesize + * @brief Alias for emif pagesize + * + */ +enum emif_pagesize +{ + emif_4_words = 0U, + emif_8_words = 1U +}; + +/** @enum emif_wait_polarity + * @brief Alias for emif wait polarity + * + */ +enum emif_wait_polarity +{ + emif_pin_low = 0U, + emif_pin_high = 1U +}; + +#define PTR ( ( volatile uint32 * ) ( 0x80000000U ) ) + +/* Configuration registers */ +typedef struct emif_config_reg +{ + uint32 CONFIG_AWCC; + uint32 CONFIG_SDCR; + uint32 CONFIG_SDRCR; + uint32 CONFIG_CE2CFG; + uint32 CONFIG_CE3CFG; + uint32 CONFIG_CE4CFG; + uint32 CONFIG_CE5CFG; + uint32 CONFIG_SDTIMR; + uint32 CONFIG_SDSRETR; + uint32 CONFIG_INTMSK; + uint32 CONFIG_PMCR; +} emif_config_reg_t; + +/* Configuration registers initial value for EMIF*/ +#define EMIF_AWCC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) \ + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) 0xC0000000U ) + +#define EMIF_SDCR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 31U ) | ( uint32 ) ( ( uint32 ) 1U << 14U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) elements_256 ) ) + +#define EMIF_SDRCR_CONFIGVALUE 0U + +#define EMIF_CE2CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE3CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE4CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE5CFG_CONFIGVALUE 0x3FFFFFFDU + +#define EMIF_SDTIMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | 0x00000000U ) + +#define EMIF_SDSRETR_CONFIGVALUE 0U +#define EMIF_INTMSK_CONFIGVALUE 0x00000000U +#define EMIF_PMCR_CONFIGVALUE \ + ( 0xFC000000U | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +/** + * @defgroup EMIF EMIF + * @brief External Memory Interface. + * + * This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories + *utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU + *to connect to a variety of external devices including: + * - Single data rate (SDR) SDRAM + * - Asynchronous devices including NOR Flash and SRAM + * The most common use for the EMIF is to interface with both a flash device and an SDRAM + *device simultaneously. contains an example of operating the EMIF in this configuration. + * + * Related Files + * - reg_emif.h + * - emif.h + * - emif.c + * @addtogroup EMIF + * @{ + */ +/* EMIF Interface Functions */ + +void emif_SDRAMInit( void ); +void emif_SDRAM_StartupInit( void ); +void emif_ASYNC1Init( void ); +void emif_ASYNC2Init( void ); +void emif_ASYNC3Init( void ); +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /*EMIF_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h new file mode 100644 index 00000000000..920b963568f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h @@ -0,0 +1,134 @@ +/** @file epc.h + * @brief EPC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EPC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYS_EPC_H_ +#define SYS_EPC_H_ + +#include "reg_epc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +enum CAMIndex +{ + CAMIndex_0 = 0U, + CAMIndex_1 = 1U, + CAMIndex_2 = 2U, + CAMIndex_3 = 3U, + CAMIndex_4 = 4U, + CAMIndex_5 = 5U, + CAMIndex_6 = 6U, + CAMIndex_7 = 7U, + CAMIndex_8 = 8U, + CAMIndex_9 = 9U, + CAMIndex_10 = 10U, + CAMIndex_11 = 11U, + CAMIndex_12 = 12U, + CAMIndex_13 = 13U, + CAMIndex_14 = 14U, + CAMIndex_15 = 15U, + CAMIndex_16 = 16U, + CAMIndex_17 = 17U, + CAMIndex_18 = 18U, + CAMIndex_19 = 19U, + CAMIndex_20 = 20U, + CAMIndex_21 = 21U, + CAMIndex_22 = 22U, + CAMIndex_23 = 23U, + CAMIndex_24 = 24U, + CAMIndex_25 = 25U, + CAMIndex_26 = 26U, + CAMIndex_27 = 27U, + CAMIndex_28 = 28U, + CAMIndex_29 = 29U, + CAMIndex_30 = 30U, + CAMIndex_31 = 31U +}; + +/** + * @defgroup EPC EPC + * @brief Error Profiling Controller + * + * Related files: + * - reg_epc.h + * - sys_epc.h + * - sys_epc.c + * + * @addtogroup EPC + * @{ + */ + +void epcEnableIP1ErrorGen( void ); +void epcDisableIP1ErrorGen( void ); +void epcEnableIP2ErrorGen( void ); +void epcDisableIP2ErrorGen( void ); +void epcEnableSERREvent( void ); +void epcDisableSERREvent( void ); +void epcEnableInterrupt( void ); +void epcDisableInterrupt( void ); +void epcCAMInit( void ); +boolean epcDiagnosticTest( void ); +boolean epcAddCAMEEntry( uint32 address ); +boolean epcCheckCAMEntry( uint32 index ); + +void epcCAMFullNotification( void ); +void epcFIFOFullNotification( uint32 epcFIFOStatus ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* SYS_EPC_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h new file mode 100644 index 00000000000..274a69ca691 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h @@ -0,0 +1,863 @@ +/** @file eqep.h + * @brief EQEP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __eQEP_H__ +#define __eQEP_H__ + +#include "reg_eqep.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define QEP_BASE_ADDR ( 0x00006B00U ) /* "Reason - TI_Fee_Fix is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_Fee_None is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None + #endif + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_MAXIMUM_BLOCKING_TIME is a + * symbolic constant"*/ + #define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_OPERATING_FREQUENCY is a + * symbolic constant."*/ + #define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE + * is a symbolic constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_CHECKSUM_ENABLE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - NVM_DATASET_SELECTION_BITS is a + * symbolic constant."*/ + #define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EEPS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_INDEX is a symbolic + * constant."*/ + #define TI_FEE_INDEX FEE_INDEX + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PAGE_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_BLOCK_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_PAGE_SIZE is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/ + #define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY \ + FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a + * symbolic constant."*/ + #define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_END_NOTIFICATION is a + * symbolic constant."*/ + #define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is + * a symbolic constant."*/ + #define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_POLLING_MODE is a symbolic + * constant."*/ + #define TI_FEE_POLLING_MODE FEE_POLLING_MODE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #ifndef FEE_CHECK_BANK7_ACCESS + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #endif + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_TOTAL_BLOCKS_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUALSECTOR_SIZE is a + * symbolic constant."*/ + #define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PHYSICALSECTOR_SIZE is a + * symbolic constant."*/ + #define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/ + #define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC \ + FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_USEPARTIALERASEDSECTOR is a + * symbolic constant."*/ + #define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR + + /*----------------------------------------------------------------------------*/ + /* Virtual Sector Configuration */ + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a + * symbolic constant."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + * is a symbolic constant."*/ + /*SAFETYMCUSW 384 S MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + + /*----------------------------------------------------------------------------*/ + /* Block Configuration */ + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_FEE_VARIABLE_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_VARIABLE_DATASETS STD_ON + + #endif /* TI_FEE_DRIVER */ + +#endif /* FEE_INTERFACE_H */ +/********************************************************************************************************************** + * END OF FILE: fee_interface.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h new file mode 100644 index 00000000000..ea64d9e5806 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h @@ -0,0 +1,182 @@ +/** @file gio.h + * @brief GIO Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GIO_H__ +#define __GIO_H__ + +#include "reg_gio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef struct gio_config_reg +{ + uint32 CONFIG_INTDET; + uint32 CONFIG_POL; + uint32 CONFIG_INTENASET; + uint32 CONFIG_LVLSET; + + uint32 CONFIG_PORTADIR; + uint32 CONFIG_PORTAPDR; + uint32 CONFIG_PORTAPSL; + uint32 CONFIG_PORTAPULDIS; + + uint32 CONFIG_PORTBDIR; + uint32 CONFIG_PORTBPDR; + uint32 CONFIG_PORTBPSL; + uint32 CONFIG_PORTBPULDIS; +} gio_config_reg_t; + +#define GIO_INTDET_CONFIGVALUE 0U +#define GIO_POL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_INTENASET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_LVLSET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_PORTADIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +#define GIO_PORTBDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +/** + * @defgroup GIO GIO + * @brief General-Purpose Input/Output Module. + * + * The GIO module provides the family of devices with input/output (I/O) capability. + * The I/O pins are bidirectional and bit-programmable. + * The GIO module also supports external interrupt capability. + * + * Related Files + * - reg_gio.h + * - gio.h + * - gio.c + * @addtogroup GIO + * @{ + */ + +/* GIO Interface Functions */ +void gioInit( void ); +void gioSetDirection( gioPORT_t * port, uint32 dir ); +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ); +void gioSetPort( gioPORT_t * port, uint32 value ); +uint32 gioGetBit( gioPORT_t * port, uint32 bit ); +uint32 gioGetPort( gioPORT_t * port ); +void gioToggleBit( gioPORT_t * port, uint32 bit ); +void gioEnableNotification( gioPORT_t * port, uint32 bit ); +void gioDisableNotification( gioPORT_t * port, uint32 bit ); +void gioNotification( gioPORT_t * port, uint32 bit ); +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h new file mode 100644 index 00000000000..1def1eafe6e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h @@ -0,0 +1,185 @@ +/** @file hal_stdtypes.h + * @brief HALCoGen standard types header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Type and Global definitions which are relevant for all drivers. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HAL_STDTYPES_H__ +#define __HAL_STDTYPES_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include +#include + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +/************************************************************/ +/* Type Definitions */ +/************************************************************/ +#ifndef _UINT64_DECLARED +typedef uint64_t uint64; + #define _UINT64_DECLARED +#endif + +#ifndef _UINT32_DECLARED +typedef uint32_t uint32; + #define _UINT32_DECLARED +#endif + +#ifndef _UINT16_DECLARED +typedef uint16_t uint16; + #define _UINT16_DECLARED +#endif + +#ifndef _UINT8_DECLARED +typedef uint8_t uint8; + #define _UINT8_DECLARED +#endif + +#ifndef _BOOLEAN_DECLARED + #ifdef __cplusplus +typedef bool boolean; + #else +typedef _Bool boolean; + #endif + #define _BOOLEAN_DECLARED +#endif + +#ifndef _SINT64_DECLARED +typedef int64_t sint64; + #define _SINT64_DECLARED +#endif + +#ifndef _SINT32_DECLARED +typedef int32_t sint32; + #define _SINT32_DECLARED +#endif + +#ifndef _SINT16_DECLARED +typedef int16_t sint16; + #define _SINT16_DECLARED +#endif + +#ifndef _SINT8_DECLARED +typedef int8_t sint8; + #define _SINT8_DECLARED +#endif + +#ifndef _FLOAT32_DECLARED +typedef float float32; + #define _FLOAT32_DECLARED +#endif + +#ifndef _FLOAT64_DECLARED +typedef double float64; + #define _FLOAT64_DECLARED +#endif + +typedef uint8 Std_ReturnType; + +typedef struct +{ + uint16 vendorID; + uint16 moduleID; + uint8 instanceID; + uint8 sw_major_version; + uint8 sw_minor_version; + uint8 sw_patch_version; +} Std_VersionInfoType; + +/*****************************************************************************/ +/* SYMBOL DEFINITIONS */ +/*****************************************************************************/ +#ifndef STATUSTYPEDEFINED + #define STATUSTYPEDEFINED + #define E_OK 0x00U + +typedef unsigned char StatusType; +#endif + +#ifndef E_NOT_OK + #define E_NOT_OK 0x01U +#endif + +#ifndef STD_ON + #define STD_ON 0x01U +#endif + +#ifndef STD_OFF + #define STD_OFF 0x00U +#endif + +/************************************************************/ +/* Global Definitions */ +/************************************************************/ +/** @def NULL + * @brief NULL definition + */ +#ifndef NULL + #define NULL ( ( void * ) 0U ) +#endif + +/** @def TRUE + * @brief definition for TRUE + */ +#ifndef TRUE + #define TRUE true +#endif + +/** @def FALSE + * @brief BOOLEAN definition for FALSE + */ +#ifndef FALSE + #define FALSE false +#endif + +/*****************************************************************************/ +/* Define: NULL_PTR */ +/* Description: Void pointer to 0 */ +/*****************************************************************************/ +#ifndef NULL_PTR + #define NULL_PTR ( ( void * ) 0x0U ) +#endif +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* __HAL_STDTYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h new file mode 100644 index 00000000000..ba0e72753eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h @@ -0,0 +1,633 @@ +/** @file het.h + * @brief HET Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HET_H__ +#define __HET_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "reg_het.h" +#include + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @def pwm0 + * @brief Pwm signal 0 + * + * Alias for pwm signal 0 + */ +#define pwm0 0U + +/** @def pwm1 + * @brief Pwm signal 1 + * + * Alias for pwm signal 1 + */ +#define pwm1 1U + +/** @def pwm2 + * @brief Pwm signal 2 + * + * Alias for pwm signal 2 + */ +#define pwm2 2U + +/** @def pwm3 + * @brief Pwm signal 3 + * + * Alias for pwm signal 3 + */ +#define pwm3 3U + +/** @def pwm4 + * @brief Pwm signal 4 + * + * Alias for pwm signal 4 + */ +#define pwm4 4U + +/** @def pwm5 + * @brief Pwm signal 5 + * + * Alias for pwm signal 5 + */ +#define pwm5 5U + +/** @def pwm6 + * @brief Pwm signal 6 + * + * Alias for pwm signal 6 + */ +#define pwm6 6U + +/** @def pwm7 + * @brief Pwm signal 7 + * + * Alias for pwm signal 7 + */ +#define pwm7 7U + +/** @def edge0 + * @brief Edge signal 0 + * + * Alias for edge signal 0 + */ +#define edge0 0U + +/** @def edge1 + * @brief Edge signal 1 + * + * Alias for edge signal 1 + */ +#define edge1 1U + +/** @def edge2 + * @brief Edge signal 2 + * + * Alias for edge signal 2 + */ +#define edge2 2U + +/** @def edge3 + * @brief Edge signal 3 + * + * Alias for edge signal 3 + */ +#define edge3 3U + +/** @def edge4 + * @brief Edge signal 4 + * + * Alias for edge signal 4 + */ +#define edge4 4U + +/** @def edge5 + * @brief Edge signal 5 + * + * Alias for edge signal 5 + */ +#define edge5 5U + +/** @def edge6 + * @brief Edge signal 6 + * + * Alias for edge signal 6 + */ +#define edge6 6U + +/** @def edge7 + * @brief Edge signal 7 + * + * Alias for edge signal 7 + */ +#define edge7 7U + +/** @def cap0 + * @brief Capture signal 0 + * + * Alias for capture signal 0 + */ +#define cap0 0U + +/** @def cap1 + * @brief Capture signal 1 + * + * Alias for capture signal 1 + */ +#define cap1 1U + +/** @def cap2 + * @brief Capture signal 2 + * + * Alias for capture signal 2 + */ +#define cap2 2U + +/** @def cap3 + * @brief Capture signal 3 + * + * Alias for capture signal 3 + */ +#define cap3 3U + +/** @def cap4 + * @brief Capture signal 4 + * + * Alias for capture signal 4 + */ +#define cap4 4U + +/** @def cap5 + * @brief Capture signal 5 + * + * Alias for capture signal 5 + */ +#define cap5 5U + +/** @def cap6 + * @brief Capture signal 6 + * + * Alias for capture signal 6 + */ +#define cap6 6U + +/** @def cap7 + * @brief Capture signal 7 + * + * Alias for capture signal 7 + */ +#define cap7 7U + +/** @def pwmEND_OF_DUTY + * @brief Pwm end of duty + * + * Alias for pwm end of duty notification + */ +#define pwmEND_OF_DUTY 2U + +/** @def pwmEND_OF_PERIOD + * @brief Pwm end of period + * + * Alias for pwm end of period notification + */ +#define pwmEND_OF_PERIOD 4U + +/** @def pwmEND_OF_BOTH + * @brief Pwm end of duty and period + * + * Alias for pwm end of duty and period notification + */ +#define pwmEND_OF_BOTH 6U + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/** @struct hetBase + * @brief HET Register Definition + * + * This structure is used to access the HET module registers. + */ +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +enum hetPinSelect +{ + PIN_HET_0 = 0U, + PIN_HET_1 = 1U, + PIN_HET_2 = 2U, + PIN_HET_3 = 3U, + PIN_HET_4 = 4U, + PIN_HET_5 = 5U, + PIN_HET_6 = 6U, + PIN_HET_7 = 7U, + PIN_HET_8 = 8U, + PIN_HET_9 = 9U, + PIN_HET_10 = 10U, + PIN_HET_11 = 11U, + PIN_HET_12 = 12U, + PIN_HET_13 = 13U, + PIN_HET_14 = 14U, + PIN_HET_15 = 15U, + PIN_HET_16 = 16U, + PIN_HET_17 = 17U, + PIN_HET_18 = 18U, + PIN_HET_19 = 19U, + PIN_HET_20 = 20U, + PIN_HET_21 = 21U, + PIN_HET_22 = 22U, + PIN_HET_23 = 23U, + PIN_HET_24 = 24U, + PIN_HET_25 = 25U, + PIN_HET_26 = 26U, + PIN_HET_27 = 27U, + PIN_HET_28 = 28U, + PIN_HET_29 = 29U, + PIN_HET_30 = 30U, + PIN_HET_31 = 31U +}; + +/** @struct hetSignal + * @brief HET Signal Definition + * + * This structure is used to define a pwm signal. + */ +/** @typedef hetSIGNAL_t + * @brief HET Signal Type Definition + * + * This type is used to access HET Signal Information. + */ +typedef struct hetSignal +{ + uint32 duty; /**< Duty cycle in % of the period */ + float64 period; /**< Period in us */ +} hetSIGNAL_t; + +/* Configuration registers */ +typedef struct het_config_reg +{ + uint32 CONFIG_GCR; + uint32 CONFIG_PFR; + uint32 CONFIG_INTENAS; + uint32 CONFIG_INTENAC; + uint32 CONFIG_PRY; + uint32 CONFIG_AND; + uint32 CONFIG_HRSH; + uint32 CONFIG_XOR; + uint32 CONFIG_DIR; + uint32 CONFIG_PDR; + uint32 CONFIG_PULDIS; + uint32 CONFIG_PSL; + uint32 CONFIG_PCR; +} het_config_reg_t; + +/* Configuration registers initial value for HET1*/ +#define HET1_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET1_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U ) + +#define HET1_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET1_GCR_CONFIGVALUE \ + ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ) + +/* Configuration registers initial value for HET2*/ +#define HET2_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET2_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U ) + +#define HET2_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET2_GCR_CONFIGVALUE \ + ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ) + +/** + * @defgroup HET HET + * @brief HighEnd Timer Module. + * + * The HET is a software-controlled timer with a dedicated specialized timer micromachine + *and a set of 30 instructions. The HET micromachine is connected to a port of up to 32 + *input/output (I/O) pins. + * + * Related Files + * - reg_het.h + * - het.h + * - het.c + * - reg_htu.h + * - htu.h + * - std_nhet.h + * @addtogroup HET + * @{ + */ + +/* HET Interface Functions */ +void hetInit( void ); + +/* PWM Interface Functions */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ); +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ); +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ); +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); + +/* Edge Interface Functions */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeNotification( hetBASE_t * hetREG, uint32 edge ); + +/* Captured Signal Interface Functions */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ); + +/* Timestamp Interface Functions */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ); +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ); +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void hetNotification(hetBASE_t *het, uint32 offset) + * @brief het interrupt callback + * @param[in] het - Het module base address + * - hetREG1: HET1 module base address pointer + * - hetREG2: HET2 module base address pointer + * @param[in] offset - het interrupt offset / Source number + * + * @note This function has to be provide by the user. + * + * This is a interrupt callback that is provided by the application and is call upon + * an het interrupt. The parameter passed to the callback is a copy of the interrupt + * offset register which is used to decode the interrupt source. + */ +void hetNotification( hetBASE_t * het, uint32 offset ); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h new file mode 100644 index 00000000000..414c09fc037 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h @@ -0,0 +1,70 @@ +/** @file htu.h + * @brief HTU Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HTU_H__ +#define __HTU_H__ + +#include "reg_htu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* HTU General Definitions */ + +#define HTU1PARLOC ( *( volatile uint32 * ) 0xFF4E0200U ) +#define HTU2PARLOC ( *( volatile uint32 * ) 0xFF4C0200U ) + +#define HTU1RAMLOC ( *( volatile uint32 * ) 0xFF4E0000U ) +#define HTU2RAMLOC ( *( volatile uint32 * ) 0xFF4C0000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h new file mode 100644 index 00000000000..7ca60027f51 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h @@ -0,0 +1,1304 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_H_ +#define _HW_EMAC_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_BASE ( 0xFCF78000U ) +#define EMAC_CTRL_BASE ( 0xFCF78800U ) +#define EMAC_CTRL_RAM_BASE ( 0xFC520000U ) + +#define EMAC_TXREVID ( 0x0U ) +#define EMAC_TXCONTROL ( 0x4U ) +#define EMAC_TXTEARDOWN ( 0x8U ) +#define EMAC_RXREVID ( 0x10U ) +#define EMAC_RXCONTROL ( 0x14U ) +#define EMAC_RXTEARDOWN ( 0x18U ) +#define EMAC_TXINTSTATRAW ( 0x80U ) +#define EMAC_TXINTSTATMASKED ( 0x84U ) +#define EMAC_TXINTMASKSET ( 0x88U ) +#define EMAC_TXINTMASKCLEAR ( 0x8CU ) +#define EMAC_MACINVECTOR ( 0x90U ) +#define EMAC_MACEOIVECTOR ( 0x94U ) +#define EMAC_RXINTSTATRAW ( 0xA0U ) +#define EMAC_RXINTSTATMASKED ( 0xA4U ) +#define EMAC_RXINTMASKSET ( 0xA8U ) +#define EMAC_RXINTMASKCLEAR ( 0xACU ) +#define EMAC_MACINTSTATRAW ( 0xB0U ) +#define EMAC_MACINTSTATMASKED ( 0xB4U ) +#define EMAC_MACINTMASKSET ( 0xB8U ) +#define EMAC_MACINTMASKCLEAR ( 0xBCU ) +#define EMAC_RXMBPENABLE ( 0x100U ) +#define EMAC_RXUNICASTSET ( 0x104U ) +#define EMAC_RXUNICASTCLEAR ( 0x108U ) +#define EMAC_RXMAXLEN ( 0x10CU ) +#define EMAC_RXBUFFEROFFSET ( 0x110U ) +#define EMAC_RXFILTERLOWTHRESH ( 0x114U ) +#define EMAC_RXFLOWTHRESH( n ) ( ( uint32 ) 0x120U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXFREEBUFFER( n ) ( ( uint32 ) 0x140U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_MACCONTROL ( 0x160U ) +#define EMAC_MACSTATUS ( 0x164U ) +#define EMAC_EMCONTROL ( 0x168U ) +#define EMAC_FIFOCONTROL ( 0x16CU ) +#define EMAC_MACCONFIG ( 0x170U ) +#define EMAC_SOFTRESET ( 0x174U ) +#define EMAC_MACSRCADDRLO ( 0x1D0U ) +#define EMAC_MACSRCADDRHI ( 0x1D4U ) +#define EMAC_MACHASH1 ( 0x1D8U ) +#define EMAC_MACHASH2 ( 0x1DCU ) +#define EMAC_BOFFTEST ( 0x1E0U ) +#define EMAC_TPACETEST ( 0x1E4U ) +#define EMAC_RXPAUSE ( 0x1E8U ) +#define EMAC_TXPAUSE ( 0x1ECU ) +#define EMAC_RXGOODFRAMES ( 0x200U ) +#define EMAC_RXBCASTFRAMES ( 0x204U ) +#define EMAC_RXMCASTFRAMES ( 0x208U ) +#define EMAC_RXPAUSEFRAMES ( 0x20CU ) +#define EMAC_RXCRCERRORS ( 0x210U ) +#define EMAC_RXALIGNCODEERRORS ( 0x214U ) +#define EMAC_RXOVERSIZED ( 0x218U ) +#define EMAC_RXJABBER ( 0x21CU ) +#define EMAC_RXUNDERSIZED ( 0x220U ) +#define EMAC_RXFRAGMENTS ( 0x224U ) +#define EMAC_RXFILTERED ( 0x228U ) +#define EMAC_RXQOSFILTERED ( 0x22CU ) +#define EMAC_RXOCTETS ( 0x230U ) +#define EMAC_TXGOODFRAMES ( 0x234U ) +#define EMAC_TXBCASTFRAMES ( 0x238U ) +#define EMAC_TXMCASTFRAMES ( 0x23CU ) +#define EMAC_TXPAUSEFRAMES ( 0x240U ) +#define EMAC_TXDEFERRED ( 0x244U ) +#define EMAC_TXCOLLISION ( 0x248U ) +#define EMAC_TXSINGLECOLL ( 0x24CU ) +#define EMAC_TXMULTICOLL ( 0x250U ) +#define EMAC_TXEXCESSIVECOLL ( 0x254U ) +#define EMAC_TXLATECOLL ( 0x258U ) +#define EMAC_TXUNDERRUN ( 0x25CU ) +#define EMAC_TXCARRIERSENSE ( 0x260U ) +#define EMAC_TXOCTETS ( 0x264U ) +#define EMAC_FRAME64 ( 0x268U ) +#define EMAC_FRAME65T127 ( 0x26CU ) +#define EMAC_FRAME128T255 ( 0x270U ) +#define EMAC_FRAME256T511 ( 0x274U ) +#define EMAC_FRAME512T1023 ( 0x278U ) +#define EMAC_FRAME1024TUP ( 0x27CU ) +#define EMAC_NETOCTETS ( 0x208U ) +#define EMAC_RXSOFOVERRUNS ( 0x284U ) +#define EMAC_RXMOFOVERRUNS ( 0x288U ) +#define EMAC_RXDMAOVERRUNS ( 0x28CU ) +#define EMAC_MACADDRLO ( 0x500U ) +#define EMAC_MACADDRHI ( 0x504U ) +#define EMAC_MACINDEX ( 0x508U ) +#define EMAC_TXHDP( n ) ( ( uint32 ) 0x600U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXHDP( n ) ( ( uint32 ) 0x620U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_TXCP( n ) ( ( uint32 ) 0x640U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXCP( n ) ( ( uint32 ) 0x660U + ( uint32 ) ( ( n ) * 4U ) ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* TXREVID */ + +#define EMAC_TXREVID_TXREV ( 0xFFFFFFFFU ) +#define EMAC_TXREVID_TXREV_SHIFT ( 0x00000000U ) + +/* TXCONTROL */ + +#define EMAC_TXCONTROL_TXEN ( 0x00000001U ) +#define EMAC_TXCONTROL_TXEN_SHIFT ( 0x00000000U ) +#define EMAC_TXCONTROL_TXDIS ( 0x00000000U ) + +/* TXTEARDOWN */ + +#define EMAC_TXTEARDOWN_TXTDNCH ( 0x00000007U ) +#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 ( 0x00000007U ) + +/* RXREVID */ + +#define EMAC_RXREVID_RXREV ( 0xFFFFFFFFU ) +#define EMAC_RXREVID_RXREV_SHIFT ( 0x00000000U ) + +/* RXCONTROL */ + +#define EMAC_RXCONTROL_RXEN ( 0x00000001U ) +#define EMAC_RXCONTROL_RXEN_SHIFT ( 0x00000000U ) +#define EMAC_RXCONTROL_RXDIS ( 0x00000000U ) + +/* RXTEARDOWN */ + +#define EMAC_RXTEARDOWN_RXTDNCH ( 0x00000007U ) +#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 ( 0x00000007U ) + +/* TXINTSTATRAW */ + +#define EMAC_TXINTSTATRAW_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATRAW_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATRAW_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATRAW_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATRAW_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATRAW_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATRAW_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATRAW_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTSTATMASKED */ + +#define EMAC_TXINTSTATMASKED_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATMASKED_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATMASKED_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATMASKED_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATMASKED_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATMASKED_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATMASKED_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATMASKED_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTMASKSET */ + +#define EMAC_TXINTMASKSET_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKSET_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKSET_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKSET_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKSET_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKSET_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKSET_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKSET_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKSET_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKSET_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKSET_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKSET_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKSET_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKSET_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKSET_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKSET_TX0MASK_SHIFT ( 0x00000000U ) + +/* TXINTMASKCLEAR */ + +#define EMAC_TXINTMASKCLEAR_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKCLEAR_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKCLEAR_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKCLEAR_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKCLEAR_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKCLEAR_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKCLEAR_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKCLEAR_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT ( 0x00000000U ) + +/* MACINVECTOR */ + +#define EMAC_MACINVECTOR_STATPEND ( 0x08000000U ) +#define EMAC_MACINVECTOR_STATPEND_SHIFT ( 0x0000001BU ) + +#define EMAC_MACINVECTOR_HOSTPEND ( 0x04000000U ) +#define EMAC_MACINVECTOR_HOSTPEND_SHIFT ( 0x0000001AU ) + +#define EMAC_MACINVECTOR_LINKINT0 ( 0x02000000U ) +#define EMAC_MACINVECTOR_LINKINT0_SHIFT ( 0x00000019U ) + +#define EMAC_MACINVECTOR_USERINT0 ( 0x01000000U ) +#define EMAC_MACINVECTOR_USERINT0_SHIFT ( 0x00000018U ) + +#define EMAC_MACINVECTOR_TXPEND ( 0x00FF0000U ) +#define EMAC_MACINVECTOR_TXPEND_SHIFT ( 0x00000010U ) + +#define EMAC_MACINVECTOR_RXTHRESHPEND ( 0x0000FF00U ) +#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_MACINVECTOR_RXPEND ( 0x000000FFU ) +#define EMAC_MACINVECTOR_RXPEND_SHIFT ( 0x00000000U ) + +/* MACEOIVECTOR */ + +#define EMAC_MACEOIVECTOR_INTVECT ( 0x0000001FU ) +#define EMAC_MACEOIVECTOR_INTVECT_SHIFT ( 0x00000000U ) +/*----INTVECT Tokens----*/ +#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH ( 0x00000000U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0RX ( 0x00000001U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0TX ( 0x00000002U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0MISC ( 0x00000003U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH ( 0x00000004U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RX ( 0x00000005U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1TX ( 0x00000006U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1MISC ( 0x00000007U ) + +/* RXINTSTATRAW */ + +#define EMAC_RXINTSTATRAW_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATRAW_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATRAW_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATRAW_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATRAW_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATRAW_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATRAW_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATRAW_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATRAW_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATRAW_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATRAW_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATRAW_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATRAW_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATRAW_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATRAW_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATRAW_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTSTATMASKED */ + +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATMASKED_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATMASKED_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATMASKED_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATMASKED_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATMASKED_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATMASKED_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATMASKED_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATMASKED_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTMASKSET */ + +#define EMAC_RXINTMASKSET_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKSET_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKSET_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKSET_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKSET_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKSET_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKSET_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKSET_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKSET_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKSET_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKSET_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKSET_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKSET_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKSET_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKSET_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKSET_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKSET_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKSET_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKSET_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKSET_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKSET_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKSET_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKSET_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKSET_RX0MASK_SHIFT ( 0x00000000U ) + +/* RXINTMASKCLEAR */ + +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKCLEAR_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKCLEAR_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKCLEAR_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKCLEAR_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKCLEAR_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKCLEAR_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKCLEAR_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKCLEAR_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT ( 0x00000000U ) + +/* MACINTSTATRAW */ + +#define EMAC_MACINTSTATRAW_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATRAW_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATRAW_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTSTATMASKED */ + +#define EMAC_MACINTSTATMASKED_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATMASKED_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTMASKSET */ + +#define EMAC_MACINTMASKSET_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKSET_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKSET_STATMASK_SHIFT ( 0x00000000U ) + +/* MACINTMASKCLEAR */ + +#define EMAC_MACINTMASKCLEAR_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKCLEAR_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT ( 0x00000000U ) + +/* RXMBPENABLE */ + +#define EMAC_RXMBPENABLE_RXPASSCRC ( 0x40000000U ) +#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT ( 0x0000001EU ) +#define EMAC_RXMBPENABLE_RXQOSEN ( 0x20000000U ) +#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT ( 0x0000001DU ) +#define EMAC_RXMBPENABLE_RXNOCHAIN ( 0x10000000U ) +#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT ( 0x0000001CU ) +#define EMAC_RXMBPENABLE_RXCMFEN ( 0x01000000U ) +#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT ( 0x00000018U ) +#define EMAC_RXMBPENABLE_RXCSFEN ( 0x00800000U ) +#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT ( 0x00000017U ) +#define EMAC_RXMBPENABLE_RXCEFEN ( 0x00400000U ) +#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT ( 0x00000016U ) +#define EMAC_RXMBPENABLE_RXCAFEN ( 0x00200000U ) +#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT ( 0x00000015U ) +/*----RXCAFEN Tokens----*/ +#define EMAC_RXMBPENABLE_RXPROMCH ( 0x00070000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT ( 0x00000010U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXBROADEN ( 0x00002000U ) +#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT ( 0x0000000DU ) +#define EMAC_RXMBPENABLE_RXBROADCH ( 0x00000700U ) +#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT ( 0x00000008U ) +/*----RXBROADCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXMULTEN ( 0x00000020U ) +#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH ( 0x00000007U ) +#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT ( 0x00000000U ) +/*----RXMULTCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 ( 0x00000007U ) + +/* RXUNICASTSET */ + +#define EMAC_RXUNICASTSET_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTSET_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTSET_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTSET_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTSET_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXUNICASTCLEAR */ + +#define EMAC_RXUNICASTCLEAR_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXMAXLEN */ + +#define EMAC_RXMAXLEN_RXMAXLEN ( 0x0000FFFFU ) +#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT ( 0x00000000U ) + +/* RXBUFFEROFFSET */ + +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET ( 0x0000FFFFU ) +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT ( 0x00000000U ) + +/* RXFILTERLOWTHRESH */ + +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH ( 0x000000FFU ) +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FLOWTHRESH */ + +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX1FLOWTHRESH */ + +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX2FLOWTHRESH */ + +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX3FLOWTHRESH */ + +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX4FLOWTHRESH */ + +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX5FLOWTHRESH */ + +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX6FLOWTHRESH */ + +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX7FLOWTHRESH */ + +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FREEBUFFER */ + +#define EMAC_RX0FREEBUFFER_RX0FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT ( 0x00000000U ) + +/* RX1FREEBUFFER */ + +#define EMAC_RX1FREEBUFFER_RX1FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT ( 0x00000000U ) + +/* RX2FREEBUFFER */ + +#define EMAC_RX2FREEBUFFER_RX2FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT ( 0x00000000U ) + +/* RX3FREEBUFFER */ + +#define EMAC_RX3FREEBUFFER_RX3FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT ( 0x00000000U ) + +/* RX4FREEBUFFER */ + +#define EMAC_RX4FREEBUFFER_RX4FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT ( 0x00000000U ) + +/* RX5FREEBUFFER */ + +#define EMAC_RX5FREEBUFFER_RX5FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT ( 0x00000000U ) + +/* RX6FREEBUFFER */ + +#define EMAC_RX6FREEBUFFER_RX6FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT ( 0x00000000U ) + +/* RX7FREEBUFFER */ + +#define EMAC_RX7FREEBUFFER_RX7FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT ( 0x00000000U ) + +/* MACCONTROL */ + +#define EMAC_MACCONTROL_RMIISPEED ( 0x00008000U ) +#define EMAC_MACCONTROL_RMIISPEED_SHIFT ( 0x0000000FU ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK ( 0x00004000U ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT ( 0x0000000EU ) +#define EMAC_MACCONTROL_RXOWNERSHIP ( 0x00002000U ) +#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT ( 0x0000000DU ) +#define EMAC_MACCONTROL_CMDIDLE ( 0x00000800U ) +#define EMAC_MACCONTROL_CMDIDLE_SHIFT ( 0x0000000BU ) +#define EMAC_MACCONTROL_TXSHORTGAPEN ( 0x00000400U ) +#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT ( 0x0000000AU ) +#define EMAC_MACCONTROL_TXPTYPE ( 0x00000200U ) +#define EMAC_MACCONTROL_TXPTYPE_SHIFT ( 0x00000009U ) +#define EMAC_MACCONTROL_TXPACE ( 0x00000040U ) +#define EMAC_MACCONTROL_TXPACE_SHIFT ( 0x00000006U ) +#define EMAC_MACCONTROL_GMIIEN ( 0x00000020U ) +#define EMAC_MACCONTROL_GMIIEN_SHIFT ( 0x00000005U ) +#define EMAC_MACCONTROL_TXFLOWEN ( 0x00000010U ) +#define EMAC_MACCONTROL_TXFLOWEN_SHIFT ( 0x00000004U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN ( 0x00000008U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT ( 0x00000003U ) +#define EMAC_MACCONTROL_LOOPBACK ( 0x00000002U ) +#define EMAC_MACCONTROL_LOOPBACK_SHIFT ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT ( 0x00000000U ) + +/* MACSTATUS */ + +#define EMAC_MACSTATUS_IDLE ( 0x80000000U ) +#define EMAC_MACSTATUS_IDLE_SHIFT ( 0x0000001FU ) +#define EMAC_MACSTATUS_TXERRCODE ( 0x00F00000U ) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT ( 0x00000014U ) +/*----TXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_TXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCODE_SOPERROR ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCODE_NOEOP ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLPTR ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLEN ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCODE_LENERROR ( 0x00000006U ) + +#define EMAC_MACSTATUS_TXERRCH ( 0x00070000U ) +#define EMAC_MACSTATUS_TXERRCH_SHIFT ( 0x00000010U ) +/*----TXERRCH Tokens----*/ +#define EMAC_MACSTATUS_TXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_TXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXERRCODE ( 0x0000F000U ) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT ( 0x0000000CU ) +/*----RXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_RXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCODE_NULLPTR ( 0x00000004U ) + +#define EMAC_MACSTATUS_RXERRCH ( 0x00000700U ) +#define EMAC_MACSTATUS_RXERRCH_SHIFT ( 0x00000008U ) +/*----RXERRCH Tokens----*/ +#define EMAC_MACSTATUS_RXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_RXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_RXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_RXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_RXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_RXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXQOSACT ( 0x00000004U ) +#define EMAC_MACSTATUS_RXQOSACT_SHIFT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT_SHIFT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT_SHIFT ( 0x00000000U ) + +/* EMCONTROL */ + +#define EMAC_EMCONTROL_SOFT ( 0x00000002U ) +#define EMAC_EMCONTROL_SOFT_SHIFT ( 0x00000001U ) + +#define EMAC_EMCONTROL_FREE ( 0x00000001U ) +#define EMAC_EMCONTROL_FREE_SHIFT ( 0x00000000U ) + +/* FIFOCONTROL */ + +#define EMAC_FIFOCONTROL_TXCELLTHRESH ( 0x00000003U ) +#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT ( 0x00000000U ) + +/* MACCONFIG */ + +#define EMAC_MACCONFIG_TXCELLDEPTH ( 0xFF000000U ) +#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT ( 0x00000018U ) + +#define EMAC_MACCONFIG_RXCELLDEPTH ( 0x00FF0000U ) +#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT ( 0x00000010U ) + +#define EMAC_MACCONFIG_ADDRESSTYPE ( 0x0000FF00U ) +#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT ( 0x00000008U ) + +#define EMAC_MACCONFIG_MACCFIG ( 0x000000FFU ) +#define EMAC_MACCONFIG_MACCFIG_SHIFT ( 0x00000000U ) + +/* SOFTRESET */ + +#define EMAC_SOFTRESET_SOFTRESET ( 0x00000001U ) +#define EMAC_SOFTRESET_SOFTRESET_SHIFT ( 0x00000000U ) + +/* MACSRCADDRLO */ + +#define EMAC_MACSRCADDRLO_MACSRCADDR0 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1 ( 0x000000FFU ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT ( 0x00000000U ) + +/* MACSRCADDRHI */ + +#define EMAC_MACSRCADDRHI_MACSRCADDR2 ( 0xFF000000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR3 ( 0x00FF0000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR4 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR5 ( 0x000000FFU ) +#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT ( 0x00000000U ) + +/* MACHASH1 */ + +#define EMAC_MACHASH1_MACHASH1 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH1_MACHASH1_SHIFT ( 0x00000000U ) + +/* MACHASH2 */ + +#define EMAC_MACHASH2_MACHASH2 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH2_MACHASH2_SHIFT ( 0x00000000U ) + +/* BOFFTEST */ + +#define EMAC_BOFFTEST_RNDNUM ( 0x03FF0000U ) +#define EMAC_BOFFTEST_RNDNUM_SHIFT ( 0x00000010U ) + +#define EMAC_BOFFTEST_COLLCOUNT ( 0x0000F000U ) +#define EMAC_BOFFTEST_COLLCOUNT_SHIFT ( 0x0000000CU ) + +#define EMAC_BOFFTEST_TXBACKOFF ( 0x000003FFU ) +#define EMAC_BOFFTEST_TXBACKOFF_SHIFT ( 0x00000000U ) + +/* TPACETEST */ + +#define EMAC_TPACETEST_PACEVAL ( 0x0000001FU ) +#define EMAC_TPACETEST_PACEVAL_SHIFT ( 0x00000000U ) + +/* RXPAUSE */ + +#define EMAC_RXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_RXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* TXPAUSE */ + +#define EMAC_TXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_TXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* RXGOODFRAMES */ + +#define EMAC_RXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXBCASTFRAMES */ + +#define EMAC_RXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXMCASTFRAMES */ + +#define EMAC_RXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXPAUSEFRAMES */ + +#define EMAC_RXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXCRCERRORS */ + +#define EMAC_RXCRCERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXCRCERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXALIGNCODEERRORS */ + +#define EMAC_RXALIGNCODEERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXOVERSIZED */ + +#define EMAC_RXOVERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOVERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXJABBER */ + +#define EMAC_RXJABBER_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXJABBER_COUNT_SHIFT ( 0x00000000U ) + +/* RXUNDERSIZED */ + +#define EMAC_RXUNDERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXUNDERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXFRAGMENTS */ + +#define EMAC_RXFRAGMENTS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFRAGMENTS_COUNT_SHIFT ( 0x00000000U ) + +/* RXFILTERED */ + +#define EMAC_RXFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXQOSFILTERED */ + +#define EMAC_RXQOSFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXQOSFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXOCTETS */ + +#define EMAC_RXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* TXGOODFRAMES */ + +#define EMAC_TXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXBCASTFRAMES */ + +#define EMAC_TXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXMCASTFRAMES */ + +#define EMAC_TXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXPAUSEFRAMES */ + +#define EMAC_TXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXDEFERRED */ + +#define EMAC_TXDEFERRED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXDEFERRED_COUNT_SHIFT ( 0x00000000U ) + +/* TXCOLLISION */ + +#define EMAC_TXCOLLISION_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCOLLISION_COUNT_SHIFT ( 0x00000000U ) + +/* TXSINGLECOLL */ + +#define EMAC_TXSINGLECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXSINGLECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXMULTICOLL */ + +#define EMAC_TXMULTICOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMULTICOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXEXCESSIVECOLL */ + +#define EMAC_TXEXCESSIVECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXLATECOLL */ + +#define EMAC_TXLATECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXLATECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXUNDERRUN */ + +#define EMAC_TXUNDERRUN_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXUNDERRUN_COUNT_SHIFT ( 0x00000000U ) + +/* TXCARRIERSENSE */ + +#define EMAC_TXCARRIERSENSE_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCARRIERSENSE_COUNT_SHIFT ( 0x00000000U ) + +/* TXOCTETS */ + +#define EMAC_TXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME64 */ + +#define EMAC_FRAME64_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME64_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME65T127 */ + +#define EMAC_FRAME65T127_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME65T127_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME128T255 */ + +#define EMAC_FRAME128T255_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME128T255_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME256T511 */ + +#define EMAC_FRAME256T511_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME256T511_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME512T1023 */ + +#define EMAC_FRAME512T1023_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME512T1023_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME1024TUP */ + +#define EMAC_FRAME1024TUP_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME1024TUP_COUNT_SHIFT ( 0x00000000U ) + +/* NETOCTETS */ + +#define EMAC_NETOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_NETOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* RXSOFOVERRUNS */ + +#define EMAC_RXSOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXMOFOVERRUNS */ + +#define EMAC_RXMOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXDMAOVERRUNS */ + +#define EMAC_RXDMAOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* MACADDRLO */ + +#define EMAC_MACADDRLO_VALID ( 0x00100000U ) +#define EMAC_MACADDRLO_VALID_SHIFT ( 0x00000014U ) +#define EMAC_MACADDRLO_MATCHFILT ( 0x00080000U ) +#define EMAC_MACADDRLO_MATCHFILT_SHIFT ( 0x00000013U ) +#define EMAC_MACADDRLO_CHANNEL ( 0x00070000U ) +#define EMAC_MACADDRLO_CHANNEL_SHIFT ( 0x00000010U ) +#define EMAC_MACADDRLO_MACADDR0 ( 0x0000FF00U ) +#define EMAC_MACADDRLO_MACADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACADDRLO_MACADDR1 ( 0x000000FFU ) +#define EMAC_MACADDRLO_MACADDR1_SHIFT ( 0x00000000U ) + +/* MACADDRHI */ + +#define EMAC_MACADDRHI_MACADDR2 ( 0xFF000000U ) +#define EMAC_MACADDRHI_MACADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACADDRHI_MACADDR3 ( 0x00FF0000U ) +#define EMAC_MACADDRHI_MACADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACADDRHI_MACADDR4 ( 0x0000FF00U ) +#define EMAC_MACADDRHI_MACADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACADDRHI_MACADDR5 ( 0x000000FFU ) +#define EMAC_MACADDRHI_MACADDR5_SHIFT ( 0x00000000U ) + +/* MACINDEX */ + +#define EMAC_MACINDEX_MACINDEX ( 0x0000001FU ) +#define EMAC_MACINDEX_MACINDEX_SHIFT ( 0x00000000U ) + +/* TX0HDP */ + +#define EMAC_TX0HDP_TX0HDP ( 0xFFFFFFFFU ) +#define EMAC_TX0HDP_TX0HDP_SHIFT ( 0x00000000U ) + +/* TX1HDP */ + +#define EMAC_TX1HDP_TX1HDP ( 0xFFFFFFFFU ) +#define EMAC_TX1HDP_TX1HDP_SHIFT ( 0x00000000U ) + +/* TX2HDP */ + +#define EMAC_TX2HDP_TX2HDP ( 0xFFFFFFFFU ) +#define EMAC_TX2HDP_TX2HDP_SHIFT ( 0x00000000U ) + +/* TX3HDP */ + +#define EMAC_TX3HDP_TX3HDP ( 0xFFFFFFFFU ) +#define EMAC_TX3HDP_TX3HDP_SHIFT ( 0x00000000U ) + +/* TX4HDP */ + +#define EMAC_TX4HDP_TX4HDP ( 0xFFFFFFFFU ) +#define EMAC_TX4HDP_TX4HDP_SHIFT ( 0x00000000U ) + +/* TX5HDP */ + +#define EMAC_TX5HDP_TX5HDP ( 0xFFFFFFFFU ) +#define EMAC_TX5HDP_TX5HDP_SHIFT ( 0x00000000U ) + +/* TX6HDP */ + +#define EMAC_TX6HDP_TX6HDP ( 0xFFFFFFFFU ) +#define EMAC_TX6HDP_TX6HDP_SHIFT ( 0x00000000U ) + +/* TX7HDP */ + +#define EMAC_TX7HDP_TX7HDP ( 0xFFFFFFFFU ) +#define EMAC_TX7HDP_TX7HDP_SHIFT ( 0x00000000U ) + +/* RX0HDP */ + +#define EMAC_RX0HDP_RX0HDP ( 0xFFFFFFFFU ) +#define EMAC_RX0HDP_RX0HDP_SHIFT ( 0x00000000U ) + +/* RX1HDP */ + +#define EMAC_RX1HDP_RX1HDP ( 0xFFFFFFFFU ) +#define EMAC_RX1HDP_RX1HDP_SHIFT ( 0x00000000U ) + +/* RX2HDP */ + +#define EMAC_RX2HDP_RX2HDP ( 0xFFFFFFFFU ) +#define EMAC_RX2HDP_RX2HDP_SHIFT ( 0x00000000U ) + +/* RX3HDP */ + +#define EMAC_RX3HDP_RX3HDP ( 0xFFFFFFFFU ) +#define EMAC_RX3HDP_RX3HDP_SHIFT ( 0x00000000U ) + +/* RX4HDP */ + +#define EMAC_RX4HDP_RX4HDP ( 0xFFFFFFFFU ) +#define EMAC_RX4HDP_RX4HDP_SHIFT ( 0x00000000U ) + +/* RX5HDP */ + +#define EMAC_RX5HDP_RX5HDP ( 0xFFFFFFFFU ) +#define EMAC_RX5HDP_RX5HDP_SHIFT ( 0x00000000U ) + +/* RX6HDP */ + +#define EMAC_RX6HDP_RX6HDP ( 0xFFFFFFFFU ) +#define EMAC_RX6HDP_RX6HDP_SHIFT ( 0x00000000U ) + +/* RX7HDP */ + +#define EMAC_RX7HDP_RX7HDP ( 0xFFFFFFFFU ) +#define EMAC_RX7HDP_RX7HDP_SHIFT ( 0x00000000U ) + +/* TX0CP */ + +#define EMAC_TX0CP_TX0CP ( 0xFFFFFFFFU ) +#define EMAC_TX0CP_TX0CP_SHIFT ( 0x00000000U ) + +/* TX1CP */ + +#define EMAC_TX1CP_TX1CP ( 0xFFFFFFFFU ) +#define EMAC_TX1CP_TX1CP_SHIFT ( 0x00000000U ) + +/* TX2CP */ + +#define EMAC_TX2CP_TX2CP ( 0xFFFFFFFFU ) +#define EMAC_TX2CP_TX2CP_SHIFT ( 0x00000000U ) + +/* TX3CP */ + +#define EMAC_TX3CP_TX3CP ( 0xFFFFFFFFU ) +#define EMAC_TX3CP_TX3CP_SHIFT ( 0x00000000U ) + +/* TX4CP */ + +#define EMAC_TX4CP_TX4CP ( 0xFFFFFFFFU ) +#define EMAC_TX4CP_TX4CP_SHIFT ( 0x00000000U ) + +/* TX5CP */ + +#define EMAC_TX5CP_TX5CP ( 0xFFFFFFFFU ) +#define EMAC_TX5CP_TX5CP_SHIFT ( 0x00000000U ) + +/* TX6CP */ + +#define EMAC_TX6CP_TX6CP ( 0xFFFFFFFFU ) +#define EMAC_TX6CP_TX6CP_SHIFT ( 0x00000000U ) + +/* TX7CP */ + +#define EMAC_TX7CP_TX7CP ( 0xFFFFFFFFU ) +#define EMAC_TX7CP_TX7CP_SHIFT ( 0x00000000U ) + +/* RX0CP */ + +#define EMAC_RX0CP_RX0CP ( 0xFFFFFFFFU ) +#define EMAC_RX0CP_RX0CP_SHIFT ( 0x00000000U ) + +/* RX1CP */ + +#define EMAC_RX1CP_RX1CP ( 0xFFFFFFFFU ) +#define EMAC_RX1CP_RX1CP_SHIFT ( 0x00000000U ) + +/* RX2CP */ + +#define EMAC_RX2CP_RX2CP ( 0xFFFFFFFFU ) +#define EMAC_RX2CP_RX2CP_SHIFT ( 0x00000000U ) + +/* RX3CP */ + +#define EMAC_RX3CP_RX3CP ( 0xFFFFFFFFU ) +#define EMAC_RX3CP_RX3CP_SHIFT ( 0x00000000U ) + +/* RX4CP */ + +#define EMAC_RX4CP_RX4CP ( 0xFFFFFFFFU ) +#define EMAC_RX4CP_RX4CP_SHIFT ( 0x00000000U ) + +/* RX5CP */ + +#define EMAC_RX5CP_RX5CP ( 0xFFFFFFFFU ) +#define EMAC_RX5CP_RX5CP_SHIFT ( 0x00000000U ) + +/* RX6CP */ + +#define EMAC_RX6CP_RX6CP ( 0xFFFFFFFFU ) +#define EMAC_RX6CP_RX6CP_SHIFT ( 0x00000000U ) + +/* RX7CP */ + +#define EMAC_RX7CP_RX7CP ( 0xFFFFFFFFU ) +#define EMAC_RX7CP_RX7CP_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h new file mode 100644 index 00000000000..764e8f748f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h @@ -0,0 +1,92 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_CTRL_H_ +#define _HW_EMAC_CTRL_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_CTRL_REVID ( 0x0U ) +#define EMAC_CTRL_SOFTRESET ( 0x4U ) +#define EMAC_CTRL_INTCONTROL ( 0xCU ) +#define EMAC_CTRL_C0RXTHRESHEN ( 0x10U ) +#define EMAC_CTRL_CnRXEN( n ) ( ( uint32 ) 0x14u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnTXEN( n ) ( ( uint32 ) 0x18u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnMISCEN( n ) \ + ( ( uint32 ) 0x1Cu + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnRXTHRESHEN( n ) \ + ( ( uint32 ) 0x20u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_C0RXTHRESHSTAT ( 0x40U ) +#define EMAC_CTRL_C0RXSTAT ( 0x44U ) +#define EMAC_CTRL_C0TXSTAT ( 0x48U ) +#define EMAC_CTRL_C0MISCSTAT ( 0x4CU ) +#define EMAC_CTRL_C1RXTHRESHSTAT ( 0x50U ) +#define EMAC_CTRL_C1RXSTAT ( 0x54U ) +#define EMAC_CTRL_C1TXSTAT ( 0x58U ) +#define EMAC_CTRL_C1MISCSTAT ( 0x5CU ) +#define EMAC_CTRL_C2RXTHRESHSTAT ( 0x60U ) +#define EMAC_CTRL_C2RXSTAT ( 0x64U ) +#define EMAC_CTRL_C2TXSTAT ( 0x68U ) +#define EMAC_CTRL_C2MISCSTAT ( 0x6CU ) +#define EMAC_CTRL_C0RXIMAX ( 0x70U ) +#define EMAC_CTRL_C0TXIMAX ( 0x74U ) +#define EMAC_CTRL_C1RXIMAX ( 0x78U ) +#define EMAC_CTRL_C1TXIMAX ( 0x7CU ) +#define EMAC_CTRL_C2RXIMAX ( 0x80U ) +#define EMAC_CTRL_C2TXIMAX ( 0x84U ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h new file mode 100644 index 00000000000..d12203353d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h @@ -0,0 +1,235 @@ +/* + * hw_mdio.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_MDIO_H_ +#define _HW_MDIO_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define MDIO_BASE ( 0xFCF78900U ) + +#define MDIO_REVID ( 0x0U ) +#define MDIO_CONTROL ( 0x4U ) +#define MDIO_ALIVE ( 0x8U ) +#define MDIO_LINK ( 0xCU ) +#define MDIO_LINKINTRAW ( 0x10U ) +#define MDIO_LINKINTMASKED ( 0x14U ) +#define MDIO_USERINTRAW ( 0x20U ) +#define MDIO_USERINTMASKED ( 0x24U ) +#define MDIO_USERINTMASKSET ( 0x28U ) +#define MDIO_USERINTMASKCLEAR ( 0x2CU ) +#define MDIO_USERACCESS0 ( 0x80U ) +#define MDIO_USERPHYSEL0 ( 0x84U ) +#define MDIO_USERACCESS1 ( 0x88U ) +#define MDIO_USERPHYSEL1 ( 0x8CU ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REVID */ + +#define MDIO_REVID_REV ( 0xFFFFFFFFU ) +#define MDIO_REVID_REV_SHIFT ( 0x00000000U ) + +/* CONTROL */ + +#define MDIO_CONTROL_IDLE ( 0x80000000U ) +#define MDIO_CONTROL_IDLE_SHIFT ( 0x0000001FU ) +/*----IDLE Tokens----*/ +#define MDIO_CONTROL_IDLE_NO ( 0x00000000U ) +#define MDIO_CONTROL_IDLE_YES ( 0x00000001U ) + +#define MDIO_CONTROL_ENABLE ( 0x40000000U ) +#define MDIO_CONTROL_ENABLE_SHIFT ( 0x0000001EU ) + +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL ( 0x1F000000U ) +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT ( 0x00000018U ) + +#define MDIO_CONTROL_PREAMBLE ( 0x00100000U ) +#define MDIO_CONTROL_PREAMBLE_SHIFT ( 0x00000014U ) +/*----PREAMBLE Tokens----*/ + +#define MDIO_CONTROL_FAULT ( 0x00080000U ) +#define MDIO_CONTROL_FAULT_SHIFT ( 0x00000013U ) + +#define MDIO_CONTROL_FAULTENB ( 0x00040000U ) +#define MDIO_CONTROL_FAULTENB_SHIFT ( 0x00000012U ) +/*----FAULTENB Tokens----*/ + +#define MDIO_CONTROL_CLKDIV ( 0x0000FFFFU ) +#define MDIO_CONTROL_CLKDIV_SHIFT ( 0x00000000U ) +/*----CLKDIV Tokens----*/ + +/* ALIVE */ + +#define MDIO_ALIVE_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_ALIVE_REGVAL_SHIFT ( 0x00000000U ) + +/* LINK */ + +#define MDIO_LINK_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_LINK_REGVAL_SHIFT ( 0x00000000U ) + +/* LINKINTRAW */ + +#define MDIO_LINKINTRAW_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTRAW_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTRAW_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTRAW_USERPHY0_SHIFT ( 0x00000000U ) + +/* LINKINTMASKED */ + +#define MDIO_LINKINTMASKED_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTMASKED_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTMASKED_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTMASKED_USERPHY0_SHIFT ( 0x00000000U ) + +/* USERINTRAW */ + +#define MDIO_USERINTRAW_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTRAW_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTRAW_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTRAW_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKED */ + +#define MDIO_USERINTMASKED_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKED_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKED_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKED_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKSET */ + +#define MDIO_USERINTMASKSET_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKSET_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKCLEAR */ + +#define MDIO_USERINTMASKCLEAR_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKCLEAR_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERACCESS0 */ + +#define MDIO_USERACCESS0_GO ( 0x80000000U ) +#define MDIO_USERACCESS0_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS0_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS0_READ ( 0x00000000U ) +#define MDIO_USERACCESS0_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS0_ACK ( 0x20000000U ) +#define MDIO_USERACCESS0_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS0_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS0_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS0_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS0_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS0_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS0_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL0 */ + +#define MDIO_USERPHYSEL0_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL0_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL0_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL0_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USERACCESS1 */ + +#define MDIO_USERACCESS1_GO ( 0x80000000U ) +#define MDIO_USERACCESS1_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS1_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS1_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS1_ACK ( 0x20000000U ) +#define MDIO_USERACCESS1_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS1_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS1_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS1_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS1_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS1_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS1_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL1 */ + +#define MDIO_USERPHYSEL1_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL1_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL1_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL1_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h new file mode 100644 index 00000000000..f1417768169 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h @@ -0,0 +1,80 @@ +/* + * hw_reg_access.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_REG_ACCESS_H_ +#define _HW_REG_ACCESS_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * + * Macros for hardware access, both direct and via the bit-band region. + * + *****************************************************************************/ +#define HWREG( x ) ( *( ( volatile uint32 * ) ( x ) ) ) +#define HWREGH( x ) ( *( ( volatile uint16 * ) ( x ) ) ) +#define HWREGB( x ) ( *( ( volatile uint8 * ) ( x ) ) ) +#define HWREGBITW( x, b ) \ + ( HWREG( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITH( x, b ) \ + ( HWREGH( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITB( x, b ) \ + ( HWREGB( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HW_TYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h new file mode 100644 index 00000000000..5cb77563052 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h @@ -0,0 +1,290 @@ +/** @file I2C.h + * @brief I2C Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +#include "reg_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum i2cMode + * @brief Alias names for i2c modes + * This enumeration is used to provide alias names for I2C modes: + */ +enum i2cMode +{ + I2C_FD_FORMAT = 0x0008U, /* Free Data Format */ + I2C_START_BYTE = 0x0010U, + I2C_RESET_OUT = 0x0020U, + I2C_RESET_IN = 0x0000U, + I2C_DLOOPBACK = 0x0040U, + I2C_REPEATMODE = 0x0080U, /* In Master Mode only */ + I2C_10BIT_AMODE = 0x0100U, + I2C_7BIT_AMODE = 0x0000U, + I2C_TRANSMITTER = 0x0200U, + I2C_RECEIVER = 0x0000U, + I2C_MASTER = 0x0400U, + I2C_SLAVE = 0x0000U, + I2C_STOP_COND = 0x0800U, /* In Master Mode only */ + I2C_START_COND = 0x2000U, /* In Master Mode only */ + I2C_FREE_RUN = 0x4000U, + I2C_NACK_MODE = 0x8000U +}; + +/** @enum i2cBitCount + * @brief Alias names for i2c bit count + * This enumeration is used to provide alias names for I2C bit count: + */ +enum i2cBitCount +{ + I2C_2_BIT = 0x2U, + I2C_3_BIT = 0x3U, + I2C_4_BIT = 0x4U, + I2C_5_BIT = 0x5U, + I2C_6_BIT = 0x6U, + I2C_7_BIT = 0x7U, + I2C_8_BIT = 0x0U +}; + +/** @enum i2cIntFlags + * @brief Interrupt Flag Definitions + * + * Used with I2CEnableNotification, I2CDisableNotification + */ +enum i2cIntFlags +{ + I2C_AL_INT = 0x0001U, /* arbitration lost */ + I2C_NACK_INT = 0x0002U, /* no acknowledgment */ + I2C_ARDY_INT = 0x0004U, /* access ready */ + I2C_RX_INT = 0x0008U, /* receive data ready */ + I2C_TX_INT = 0x0010U, /* transmit data ready */ + I2C_SCD_INT = 0x0020U, /* stop condition detect */ + I2C_AAS_INT = 0x0040U /* address as slave */ +}; + +/** @enum i2cStatFlags + * @brief Interrupt Status Definitions + * + */ +enum i2cStatFlags +{ + I2C_AL = 0x0001U, /* arbitration lost */ + I2C_NACK = 0x0002U, /* no acknowledgement */ + I2C_ARDY = 0x0004U, /* access ready */ + I2C_RX = 0x0008U, /* receive data ready */ + I2C_TX = 0x0010U, /* transmit data ready */ + I2C_SCD = 0x0020U, /* stop condition detect */ + I2C_AD0 = 0x0100U, /* address Zero Status */ + I2C_AAS = 0x0200U, /* address as slave */ + I2C_XSMT = 0x0400U, /* Transmit shift empty not */ + I2C_RXFULL = 0x0800U, /* receive full */ + I2C_BUSBUSY = 0x1000U, /* bus busy */ + I2C_NACKSNT = 0x2000U, /* No Ack Sent */ + I2C_SDIR = 0x4000U /* Slave Direction */ +}; + +/** @enum i2cDMA + * @brief I2C DMA definitions + * + * Used before i2c transfer + */ +enum i2cDMA +{ + I2C_TXDMA = 0x20U, + I2C_RXDMA = 0x10U +}; + +/* Configuration registers */ +typedef struct i2c_config_reg +{ + uint32 CONFIG_OAR; + uint32 CONFIG_IMR; + uint32 CONFIG_CLKL; + uint32 CONFIG_CLKH; + uint32 CONFIG_CNT; + uint32 CONFIG_SAR; + uint32 CONFIG_MDR; + uint32 CONFIG_EMDR; + uint32 CONFIG_PSC; + uint32 CONFIG_DMAC; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; +} i2c_config_reg_t; + +/* Configuration registers initial value for I2C*/ +#define I2C1_OAR_CONFIGVALUE 0x00000000U +#define I2C1_IMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( ( uint32 ) 0U ) ) + +#define I2C1_CLKL_CONFIGVALUE 37U +#define I2C1_CLKH_CONFIGVALUE 37U +#define I2C1_CNT_CONFIGVALUE 8U +#define I2C1_SAR_CONFIGVALUE 0x000003FFU +#define I2C1_MDR_CONFIGVALUE \ + ( 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( ( uint32 ) I2C_TRANSMITTER ) \ + | ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \ + | ( ( uint32 ) 0U ) | ( ( uint32 ) I2C_8_BIT ) | ( uint32 ) I2C_RESET_OUT ) + +#define I2C1_EMDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PSC_CONFIGVALUE 8U +#define I2C1_DMAC_CONFIGVALUE 0x00000000U +#define I2C1_FUN_CONFIGVALUE 0U +#define I2C1_DIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_ODR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PD_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) ) + +/* Configuration registers initial value for I2C*/ +#define I2C2_OAR_CONFIGVALUE 0x00000000U +#define I2C2_IMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( ( uint32 ) 0U ) ) + +#define I2C2_CLKL_CONFIGVALUE 37U +#define I2C2_CLKH_CONFIGVALUE 37U +#define I2C2_CNT_CONFIGVALUE 8U +#define I2C2_SAR_CONFIGVALUE 0x000003FFU +#define I2C2_MDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) \ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) | ( uint32 ) ( ( uint32 ) I2C_2_BIT ) \ + | ( uint32 ) I2C_RESET_OUT ) + +#define I2C2_EMDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PSC_CONFIGVALUE 8U +#define I2C2_DMAC_CONFIGVALUE 0x00000000U +#define I2C2_FUN_CONFIGVALUE 0U +#define I2C2_DIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_ODR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PD_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) ) + +/** + * @defgroup I2C I2C + * @brief Inter-Integrated Circuit Module. + * + * The I2C is a multi-master communication module providing an interface between the + * Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor + * I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support + * any slave or master I2C compatible device. + * + * Related Files + * - reg_i2c.h + * - i2c.h + * - i2c.c + * @addtogroup I2C + * @{ + */ + +/* I2C Interface Functions */ +void i2cInit( void ); +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ); +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ); +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ); +uint32 i2cIsTxReady( i2cBASE_t * i2c ); +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ); +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ); +uint32 i2cIsRxReady( i2cBASE_t * i2c ); +uint32 i2cIsStopDetected( i2cBASE_t * i2c ); +void i2cClearSCD( i2cBASE_t * i2c ); +uint32 i2cRxError( i2cBASE_t * i2c ); +uint8 i2cReceiveByte( i2cBASE_t * i2c ); +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ); +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cSetStart( i2cBASE_t * i2c ); +void i2cSetStop( i2cBASE_t * i2c ); +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ); +void i2cEnableLoopback( i2cBASE_t * i2c ); +void i2cDisableLoopback( i2cBASE_t * i2c ); +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ); +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ); +bool i2cIsMasterReady( i2cBASE_t * i2c ); +bool i2cIsBusBusy( i2cBASE_t * i2c ); +void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); +void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Interrupt callback + * @param[in] i2c - I2C module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h new file mode 100644 index 00000000000..36d037b8fe3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h @@ -0,0 +1,317 @@ +/** @file lin.h + * @brief LIN Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __LIN_H__ +#define __LIN_H__ + +#include "reg_lin.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def LIN_BREAK_INT + * @brief Alias for break detect interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BREAK_INT 0x00000001U + +/** @def LIN_WAKEUP_INT + * @brief Alias for wakeup interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_WAKEUP_INT 0x00000002U + +/** @def LIN_TO_INT + * @brief Alias for time out interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TO_INT 0x00000010U + +/** @def LIN_TOAWUS_INT + * @brief Alias for time out after wakeup signal interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOAWUS_INT 0x00000040U + +/** @def LIN_TOA3WUS_INT + * @brief Alias for time out after 3 wakeup signals interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOA3WUS_INT 0x00000080U + +/** @def LIN_TX_READY + * @brief Alias for transmit buffer ready flag + * + * Used with linIsTxReady. + */ +#define LIN_TX_READY 0x00000100U + +/** @def LIN_RX_INT + * @brief Alias for receive buffer ready interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_RX_INT 0x00000200U + +/** @def LIN_ID_INT + * @brief Alias for received matching identifier interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ID_INT 0x00002000U + +/** @def LIN_PE_INT + * @brief Alias for parity error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PE_INT 0x01000000U + +/** @def LIN_OE_INT + * @brief Alias for overrun error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_OE_INT 0x02000000U + +/** @def LIN_FE_INT + * @brief Alias for framing error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_FE_INT 0x04000000U + +/** @def LIN_NRE_INT + * @brief Alias for no response error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_NRE_INT 0x08000000U + +/** @def LIN_ISFE_INT + * @brief Alias for inconsistent sync field error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ISFE_INT 0x10000000U + +/** @def LIN_CE_INT + * @brief Alias for checksum error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_CE_INT 0x20000000U + +/** @def LIN_PBE_INT + * @brief Alias for physical bus error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PBE_INT 0x40000000U + +/** @def LIN_BE_INT + * @brief Alias for bit error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BE_INT 0x80000000U + +/** @struct linBase + * @brief LIN Register Definition + * + * This structure is used to access the LIN module registers. + */ +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +enum linPinSelect +{ + PIN_LIN_TX = 4U, + PIN_LIN_RX = 2U +}; + +/* Configuration registers */ +typedef struct lin_config_reg +{ + uint32 CONFIG_GCR0; + uint32 CONFIG_GCR1; + uint32 CONFIG_GCR2; + uint32 CONFIG_SETINT; + uint32 CONFIG_SETINTLVL; + uint32 CONFIG_FORMAT; + uint32 CONFIG_BRSR; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; + uint32 CONFIG_COMP; + uint32 CONFIG_MASK; + uint32 CONFIG_MBRSR; +} lin_config_reg_t; + +/* Configuration registers initial value for LIN*/ +#define LIN1_GCR0_CONFIGVALUE 0x00000001U +#define LIN1_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN1_GCR2_CONFIGVALUE 0x00000000U +#define LIN1_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN1_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN1_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN1_BRSR_CONFIGVALUE ( 233U ) +#define LIN1_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN1_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN1_MBRSR_CONFIGVALUE ( 3370U ) +#define LIN1_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN1_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/* Configuration registers initial value for LIN*/ +#define LIN2_GCR0_CONFIGVALUE 0x00000001U +#define LIN2_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN2_GCR2_CONFIGVALUE 0x00000000U +#define LIN2_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN2_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN2_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN2_BRSR_CONFIGVALUE ( 233U ) +#define LIN2_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN2_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN2_MBRSR_CONFIGVALUE ( 3370U ) +#define LIN2_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN2_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/** + * @defgroup LIN LIN + * @brief Local Interconnect Network Module. + * + * The LIN standard is based on the SCI (UART) serial data link format. The communication + *concept is single-master/multiple-slave with a message identification for multi-cast + *transmission between any network nodes. + * + * Related Files + * - reg_lin.h + * - lin.h + * - lin.c + * @addtogroup LIN + * @{ + */ + +/* LIN Interface Functions */ +void linInit( void ); +void linSetFunctional( linBASE_t * lin, uint32 port ); +void linSendHeader( linBASE_t * lin, uint8 identifier ); +void linSendWakupSignal( linBASE_t * lin ); +void linEnterSleep( linBASE_t * lin ); +void linSoftwareReset( linBASE_t * lin ); +uint32 linIsTxReady( linBASE_t * lin ); +void linSetLength( linBASE_t * lin, uint32 length ); +void linSend( linBASE_t * lin, uint8 * data ); +uint32 linIsRxReady( linBASE_t * lin ); +uint32 linTxRxError( linBASE_t * lin ); +uint32 linGetIdentifier( linBASE_t * lin ); +void linGetData( linBASE_t * lin, uint8 * const data ); +void linEnableNotification( linBASE_t * lin, uint32 flags ); +void linDisableNotification( linBASE_t * lin, uint32 flags ); +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ); +void linDisableLoopback( linBASE_t * lin ); +void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +uint32 linGetStatusFlag( linBASE_t * lin ); +void linClearStatusFlag( linBASE_t * lin, uint32 flags ); + +/** @fn void linNotification(linBASE_t *lin, uint32 flags) + * @brief Interrupt callback + * @param[in] lin - lin module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void linNotification( linBASE_t * lin, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h new file mode 100644 index 00000000000..f936f915c91 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h @@ -0,0 +1,94 @@ +/** + * \file mdio.h + * + * \brief MDIO APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MDIO_H__ +#define __MDIO_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "system.h" +#include "hw_mdio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* MDIO input and output frequencies in Hz */ +#define MDIO_FREQ_INPUT ( ( uint32 ) ( VCLK3_FREQ * 1000000.00F ) ) +#define MDIO_FREQ_OUTPUT 1000000U +/*****************************************************************************/ + +/** + * @addtogroup EMACMDIO + * @{ + */ +/* +** Prototypes for the APIs +*/ +extern uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ); +extern uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ); +extern void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ); +extern boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ); +extern void MDIOPhyRegWrite( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + uint16 RegVal ); +extern void MDIOEnable( uint32 baseAddr ); +extern void MDIODisable( uint32 baseAddr ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __MDIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h new file mode 100644 index 00000000000..71d7b98f224 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h @@ -0,0 +1,885 @@ +/** @file mibspi.h + * @brief MIBSPI Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MIBSPI_H__ +#define __MIBSPI_H__ + +#include "reg_mibspi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum triggerEvent + * @brief Transfer Group Trigger Event + */ +enum triggerEvent +{ + TRG_NEVER = 0U, + TRG_RISING = 1U, + TRG_FALLING = 2U, + TRG_BOTH = 3U, + TRG_HIGH = 5U, + TRG_LOW = 6U, + TRG_ALWAYS = 7U +}; + +/** @enum triggerSource + * @brief Transfer Group Trigger Source + */ +enum triggerSource +{ + TRG_DISABLED, + TRG_GIOA0, + TRG_GIOA1, + TRG_GIOA2, + TRG_GIOA3, + TRG_GIOA4, + TRG_GIOA5, + TRG_GIOA6, + TRG_GIOA7, + TRG_HET1_8, + TRG_HET1_10, + TRG_HET1_12, + TRG_HET1_14, + TRG_HET1_16, + TRG_HET1_18, + TRG_TICK +}; + +/** @enum mibspiPinSelect + * @brief mibspi Pin Select + */ +enum mibspiPinSelect +{ + PIN_CS0 = 0U, + PIN_CS1 = 1U, + PIN_CS2 = 2U, + PIN_CS3 = 3U, + PIN_CS4 = 4U, + PIN_CS5 = 5U, + PIN_CS6 = 6U, + PIN_CS7 = 7U, + PIN_ENA = 8U, + PIN_CLK = 9U, + PIN_SIMO = 10U, + PIN_SOMI = 11U, + PIN_SIMO_1 = 17U, + PIN_SIMO_2 = 18U, + PIN_SIMO_3 = 19U, + PIN_SIMO_4 = 20U, + PIN_SIMO_5 = 21U, + PIN_SIMO_6 = 22U, + PIN_SIMO_7 = 23U, + PIN_SOMI_1 = 25U, + PIN_SOMI_2 = 26U, + PIN_SOMI_3 = 27U, + PIN_SOMI_4 = 28U, + PIN_SOMI_5 = 29U, + PIN_SOMI_6 = 30U, + PIN_SOMI_7 = 31U +}; + +/** @enum chipSelect + * @brief Transfer Group Chip Select + */ +enum chipSelect +{ + CS_NONE = 0xFFU, + CS_0 = 0xFEU, + CS_1 = 0xFDU, + CS_2 = 0xFBU, + CS_3 = 0xF7U, + CS_4 = 0xEFU, + CS_5 = 0xDFU, + CS_6 = 0xBFU, + CS_7 = 0x7FU +}; + +/** @typedef mibspiPmode_t + * @brief Mibspi Parellel mode Type Definition + * + * This type is used to represent Mibspi Parellel mode. + */ +typedef enum mibspiPmode +{ + PMODE_NORMAL = 0x0U, + PMODE_2_DATALINE = 0x1U, + PMODE_4_DATALINE = 0x2U, + PMODE_8_DATALINE = 0x3U +} mibspiPmode_t; + +/** @typedef mibspiDFMT_t + * @brief Mibspi Data format selection Type Definition + * + * This type is used to represent Mibspi Data format selection. + */ +typedef enum mibspiDFMT +{ + DATA_FORMAT0 = 0x0U, + DATA_FORMAT1 = 0x1U, + DATA_FORMAT2 = 0x2U, + DATA_FORMAT3 = 0x3U +} mibspiDFMT_t; + +typedef struct mibspi_config_reg +{ + uint32 CONFIG_GCR1; + uint32 CONFIG_INT0; + uint32 CONFIG_LVL; + uint32 CONFIG_PCFUN; + uint32 CONFIG_PCDIR; + uint32 CONFIG_PCPDR; + uint32 CONFIG_PCDIS; + uint32 CONFIG_PCPSL; + uint32 CONFIG_DELAY; + uint32 CONFIG_FMT0; + uint32 CONFIG_FMT1; + uint32 CONFIG_FMT2; + uint32 CONFIG_FMT3; + uint32 CONFIG_MIBSPIE; + uint32 CONFIG_LTGPEND; + uint32 CONFIG_TGCTRL[ 8U ]; + uint32 CONFIG_PAR_ECC_CTRL; +} mibspi_config_reg_t; + +#define MIBSPI1_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI1_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI1_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) +#define MIBSPI1_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) + +#define MIBSPI1_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI1_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI1_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI1_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI1_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI1_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI2_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI2_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) +#define MIBSPI2_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define MIBSPI2_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI2_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI2_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI2_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI2_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI2_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI2_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI2_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI2_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI3_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI3_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI3_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI3_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI3_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI3_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI3_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI3_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI3_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI3_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI4_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI4_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) +#define MIBSPI4_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define MIBSPI4_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI4_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI4_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI4_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI4_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI4_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI4_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI4_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI4_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI5_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI5_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI5_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) +#define MIBSPI5_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) + +#define MIBSPI5_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI5_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI5_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI5_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI5_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI5_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +/** + * @defgroup MIBSPI MIBSPI + * @brief Multi-Buffered Serial Peripheral Interface Module. + * + * The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a + *serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the + *device at a programmed bit-transfer rate. The MibSPI has a programmable buffer memory + *that enables programmed transmission to be completed without CPU intervention + * + * Related Files + * - reg_mibspi.h + * - mibspi.h + * - mibspi.c + * @addtogroup MIBSPI + * @{ + */ + +/* MIBSPI Interface Functions */ +void mibspiInit( void ); +boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi ); +void mibspiOutofReset( mibspiBASE_t * mibspi ); +void mibspiReset( mibspiBASE_t * mibspi ); +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ); +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ); +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ); +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ); +void mibspiDisableLoopback( mibspiBASE_t * mibspi ); +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ); +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) + * @brief Error interrupt callback + * @param[in] mibspi - mibSpi module base address + * @param[in] flags - Copy of error interrupt flags + * + * This is a error callback that is provided by the application and is call upon + * an error interrupt. The paramer passed to the callback is a copy of the error + * interrupt flag register. + */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ); + +/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Transfer complete notification callback + * @param[in] mibspi - mibSpi module base address + * @param[in] group - Transfer group + * + * This is a callback function provided by the application. It is call when + * a transfer is complete. The parameter is the transfer group that triggered + * the interrupt. + */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h new file mode 100644 index 00000000000..47bd39fa1b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h @@ -0,0 +1,165 @@ +/** @file nmpu.h + * @brief NMPU Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NMPU_H_ +#define NMPU_H_ + +#include "reg_nmpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef enum nmpuRegion +{ + NMPU_REGION0 = 0U, + NMPU_REGION1 = 1U, + NMPU_REGION2 = 2U, + NMPU_REGION3 = 3U, + NMPU_REGION4 = 4U, + NMPU_REGION5 = 5U, + NMPU_REGION6 = 6U, + NMPU_REGION7 = 7U +} nmpuReg_t; + +typedef enum nmpuAccessPermission +{ + NMPU_PRIV_NA_USER_NA = 0U, + NMPU_PRIV_RW_USER_NA = 1U, + NMPU_PRIV_RW_USER_RO = 2U, + NMPU_PRIV_RW_USER_RW = 3U, + NMPU_PRIV_RO_USER_NA = 5U, + NMPU_PRIV_RO_USER_RO = 6U +} nmpuAP_t; + +typedef enum nmpuRegionSize +{ + NMPU_SIZE_32_BYTES = 0x4U, + NMPU_SIZE_64_BYTES = 0x5U, + NMPU_SIZE_128_BYTES = 0x6U, + NMPU_SIZE_256_BYTES = 0x7U, + NMPU_SIZE_512_BYTES = 0x8U, + NMPU_SIZE_1_KB = 0x9U, + NMPU_SIZE_2_KB = 0xAU, + NMPU_SIZE_4_KB = 0xBU, + NMPU_SIZE_8_KB = 0xCU, + NMPU_SIZE_16_KB = 0xDU, + NMPU_SIZE_32_KB = 0xEU, + NMPU_SIZE_64_KB = 0xFU, + NMPU_SIZE_128_KB = 0x10U, + NMPU_SIZE_256_KB = 0x11U, + NMPU_SIZE_512_KB = 0x12U, + NMPU_SIZE_1_MB = 0x13U, + NMPU_SIZE_2_MB = 0x14U, + NMPU_SIZE_4_MB = 0x15U, + NMPU_SIZE_8_MB = 0x16U, + NMPU_SIZE_16_MB = 0x17U, + NMPU_SIZE_32_MB = 0x18U, + NMPU_SIZE_64_MB = 0x19U, + NMPU_SIZE_128_MB = 0x1AU, + NMPU_SIZE_256_MB = 0x1BU, + NMPU_SIZE_512_MB = 0x1CU, + NMPU_SIZE_1_GB = 0x1DU, + NMPU_SIZE_2_GB = 0x1EU, + NMPU_SIZE_4_GB = 0x1FU +} nmpuRegionSize_t; + +typedef enum nmpuError +{ + NMPU_ERROR_NONE, + NMPU_ERROR_AP_READ, + NMPU_ERROR_AP_WRITE, + NMPU_ERROR_BG_READ, + NMPU_ERROR_BG_WRITE +} nmpuErr_t; + +typedef struct nmpuRegionAttributes +{ + uint32 baseaddr; + nmpuReg_t regionsize; + nmpuAP_t accesspermission; +} nmpuRegionAttributes_t; + +/** + * @defgroup NMPU NMPU + * @brief System Memory Protection Unit + * + * Related files: + * - reg_nmpu.h + * - sys_nmpu.h + * - sys_nmpu.c + * + * @addtogroup NMPU + * @{ + */ + +void nmpuEnable( nmpuBASE_t * nmpu ); +void nmpuDisable( nmpuBASE_t * nmpu ); +void nmpuEnableErrorGen( nmpuBASE_t * nmpu ); +void nmpuDisableErrorGen( nmpuBASE_t * nmpu ); +boolean nmpuEnableRegion( nmpuBASE_t * nmpu, + nmpuReg_t region, + nmpuRegionAttributes_t config ); +boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region ); +nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu ); +nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu ); +uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu ); +void nmpuClearErrorStatus( nmpuBASE_t * nmpu ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* NMPU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h new file mode 100644 index 00000000000..98d1837da4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h @@ -0,0 +1,139 @@ +/* + * DP83640.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _PHY_DP83640_H_ +#define _PHY_DP83640_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Dp83640GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define DP83640_PHY_ID ( 0x0007C0F0u ) +#define DP83640_PHY_ID_REV_MASK ( 0x0000000Fu ) + +/* Pause operations */ +#define DP83640_PAUSE_NIL ( 0x0000u ) +#define DP83640_PAUSE_SYM ( 0x0400u ) +#define DP83640_PAUSE_ASYM ( 0x0800u ) +#define DP83640_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define DP83640_100BTX_HD ( 0x0000u ) +#define DP83640_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define DP83640_NO_100BTX ( 0x0000u ) +#define DP83640_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define DP83640_10BT_HD ( 0x0000u ) +#define DP83640_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define DP83640_NO_10BT ( 0x0000u ) +#define DP83640_10BT ( 0x0020u ) + +/************************************************************************** + API function Prototypes +***************************************************************************/ +extern uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h new file mode 100644 index 00000000000..610217ea173 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h @@ -0,0 +1,156 @@ +/* + * Tlk111.h + */ + +/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com + * ALL RIGHTS RESERVED + */ + +#ifndef _PHY_TLK111_H_ +#define _PHY_TLK111_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Tlk111GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_SWSCR1 ( 9u ) +#define PHY_SWSCR2 ( 10u ) +#define PHY_SWSCR3 ( 11u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define Tlk111_PHY_ID ( 0x2000A212 ) +#define Tlk111_PHY_ID_REV_MASK ( 0x0000000Fu ) +#define Tlk111_PHY_ID_OUI ( 0x2000A000 ) +#define Tlk111_PHY_ID_OUI_MASK ( 0xFFFFFC00 ) + +/* Pause operations */ +#define Tlk111_PAUSE_NIL ( 0x0000u ) +#define Tlk111_PAUSE_SYM ( 0x0400u ) +#define Tlk111_PAUSE_ASYM ( 0x0800u ) +#define Tlk111_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define Tlk111_100BTX_HD ( 0x0000u ) +#define Tlk111_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define Tlk111_NO_100BTX ( 0x0000u ) +#define Tlk111_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define Tlk111_10BT_HD ( 0x0000u ) +#define Tlk111_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define Tlk111_NO_10BT ( 0x0000u ) +#define Tlk111_10BT ( 0x0020u ) + +/* Software Strap Register 1 */ +#define Tlk111_SWStrapDone ( 1u << 15 ) +#define Tlk111_Auto_MDIX_Ena ( 1u << 14 ) +#define Tlk111_Auto_Neg_Ena ( 1u << 13 ) +#define Tlk111_Auto_AnMode_10BT_HD ( 0u << 11 ) +#define Tlk111_Auto_AnMode_10BT_FD ( 1u << 11 ) +#define Tlk111_Auto_AnMode_100BT_HD ( 2u << 11 ) +#define Tlk111_Auto_AnMode_100BT_FD ( 3u << 11 ) +#define Tlk111_Force_LEDMode1 ( 1u << 10 ) +#define Tlk111_RMII_Enhanced ( 1u << 9 ) +#define Tlk111_TDR_AutoRun ( 1u << 8 ) +#define Tlk111_LinkLoss_Recovery ( 1u << 8 ) +#define Tlk111_FastAutoMdix ( 1u << 6 ) +#define Tlk111_RobustAutoMdix ( 1u << 5 ) +#define Tlk111_FastAnEn ( 1u << 4 ) +#define Tlk111_FastAnSel0 ( 0u << 2 ) +#define Tlk111_FastAnSel1 ( 1u << 2 ) +#define Tlk111_FastAnSel2 ( 2u << 2 ) +#define Tlk111_FastRxDvDetect ( 1u << 1 ) +#define Tlk111_IntPdn_InterruptOut ( 1u << 0 ) + +/* Software Strap Register 2 */ +#define Tlk111_100BT_Force_FE_LinkDrop ( 1u << 15 ) +#define Tlk111_Rsv1 ( 2u << 7 ) +#define Tlk111_FastLinkUpParallel ( 1u << 6 ) +#define Tlk111_ExtendedFDAbility ( 1u << 5 ) +#define Tlk111_ExtendedLEDLink ( 1u << 4 ) +#define Tlk111_IsolateMII_100BT_HD ( 1u << 3 ) +#define Tlk111_RXERR_DuringIdle ( 1u << 2 ) +#define Tlk111_OddNibbleDetectDisable ( 1u << 1 ) +#define Tlk111_RMII_Use_RXCLK ( 1u << 0 ) +#define Tlk111_RMII_Use_XI ( 0u << 0 ) + +/* Software Strap Register 2 */ +#define Tlk111_FastLinkDown ( 1u << 10 ) +#define Tlk111_PolaritySwap ( 1u << 6 ) +#define Tlk111_MDIXSwap ( 1u << 5 ) +#define Tlk111_Bypass4B5B ( 1u << 4 ) +#define Tlk111_FastLinkDownRxErrCnt ( 1u << 3 ) +#define Tlk111_FastLinkDownMLT3ErrCnt ( 1u << 2 ) +#define Tlk111_FastLinkDownLowSnr ( 1u << 1 ) +#define Tlk111_FastLinkDownSigLoss ( 1u << 0 ) + +/* The Values for SWSCR Registers */ +#define Tlk111_SWSCR1_Val \ + ( Tlk111_Auto_MDIX_Ena | Tlk111_Auto_Neg_Ena | Tlk111_Auto_AnMode_100BT_FD \ + | Tlk111_Force_LEDMode1 | Tlk111_IntPdn_InterruptOut ) +#define Tlk111_SWSCR2_Val ( Tlk111_Rsv1 | Tlk111_RXERR_DuringIdle ) +#define Tlk111_SWSCR3_Val ( 0u ) + +/************************************************************************** + API function Prototypes +***************************************************************************/ +extern uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h new file mode 100644 index 00000000000..2ec2e899db4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h @@ -0,0 +1,1762 @@ +/** @file pinmux.h + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __PINMUX_H__ +#define __PINMUX_H__ + +#include "reg_pinmux.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define PINMUX_BALL_N19_SHIFT 0U +#define PINMUX_BALL_D4_SHIFT 8U +#define PINMUX_BALL_D5_SHIFT 16U +#define PINMUX_BALL_C4_SHIFT 24U +#define PINMUX_BALL_C5_SHIFT 0U +#define PINMUX_BALL_C6_SHIFT 8U +#define PINMUX_BALL_C7_SHIFT 16U +#define PINMUX_BALL_C8_SHIFT 24U +#define PINMUX_BALL_C9_SHIFT 0U +#define PINMUX_BALL_C10_SHIFT 8U +#define PINMUX_BALL_C11_SHIFT 16U +#define PINMUX_BALL_C12_SHIFT 24U +#define PINMUX_BALL_C13_SHIFT 0U +#define PINMUX_BALL_D14_SHIFT 8U +#define PINMUX_BALL_C14_SHIFT 16U +#define PINMUX_BALL_D15_SHIFT 24U +#define PINMUX_BALL_C15_SHIFT 0U +#define PINMUX_BALL_C16_SHIFT 8U +#define PINMUX_BALL_C17_SHIFT 16U +#define PINMUX_BALL_D16_SHIFT 24U +#define PINMUX_BALL_K3_SHIFT 0U +#define PINMUX_BALL_R4_SHIFT 8U +#define PINMUX_BALL_N17_SHIFT 16U +#define PINMUX_BALL_L17_SHIFT 24U +#define PINMUX_BALL_K17_SHIFT 0U +#define PINMUX_BALL_M17_SHIFT 8U +#define PINMUX_BALL_R3_SHIFT 16U +#define PINMUX_BALL_P3_SHIFT 24U +#define PINMUX_BALL_D17_SHIFT 0U +#define PINMUX_BALL_E9_SHIFT 8U +#define PINMUX_BALL_E8_SHIFT 16U +#define PINMUX_BALL_E7_SHIFT 24U +#define PINMUX_BALL_E6_SHIFT 0U +#define PINMUX_BALL_E13_SHIFT 8U +#define PINMUX_BALL_E12_SHIFT 16U +#define PINMUX_BALL_E11_SHIFT 24U +#define PINMUX_BALL_E10_SHIFT 0U +#define PINMUX_BALL_K15_SHIFT 8U +#define PINMUX_BALL_L15_SHIFT 16U +#define PINMUX_BALL_M15_SHIFT 24U +#define PINMUX_BALL_N15_SHIFT 0U +#define PINMUX_BALL_E5_SHIFT 8U +#define PINMUX_BALL_F5_SHIFT 16U +#define PINMUX_BALL_G5_SHIFT 24U +#define PINMUX_BALL_K5_SHIFT 0U +#define PINMUX_BALL_L5_SHIFT 8U +#define PINMUX_BALL_M5_SHIFT 16U +#define PINMUX_BALL_N5_SHIFT 24U +#define PINMUX_BALL_P5_SHIFT 0U +#define PINMUX_BALL_R5_SHIFT 8U +#define PINMUX_BALL_R6_SHIFT 16U +#define PINMUX_BALL_R7_SHIFT 24U +#define PINMUX_BALL_R8_SHIFT 0U +#define PINMUX_BALL_R9_SHIFT 8U +#define PINMUX_BALL_R10_SHIFT 16U +#define PINMUX_BALL_R11_SHIFT 24U +#define PINMUX_BALL_B15_SHIFT 0U +#define PINMUX_BALL_B8_SHIFT 8U +#define PINMUX_BALL_B16_SHIFT 16U +#define PINMUX_BALL_B9_SHIFT 24U +#define PINMUX_BALL_C1_SHIFT 0U +#define PINMUX_BALL_E1_SHIFT 8U +#define PINMUX_BALL_B5_SHIFT 16U +#define PINMUX_BALL_H3_SHIFT 24U +#define PINMUX_BALL_M1_SHIFT 0U +#define PINMUX_BALL_F2_SHIFT 8U +#define PINMUX_BALL_W10_SHIFT 16U +#define PINMUX_BALL_J2_SHIFT 24U +#define PINMUX_BALL_F1_SHIFT 0U +#define PINMUX_BALL_R2_SHIFT 8U +#define PINMUX_BALL_F3_SHIFT 16U +#define PINMUX_BALL_G3_SHIFT 24U +#define PINMUX_BALL_J3_SHIFT 0U +#define PINMUX_BALL_G19_SHIFT 8U +#define PINMUX_BALL_V9_SHIFT 16U +#define PINMUX_BALL_V10_SHIFT 24U +#define PINMUX_BALL_V5_SHIFT 0U +#define PINMUX_BALL_B2_SHIFT 8U +#define PINMUX_BALL_C3_SHIFT 16U +#define PINMUX_BALL_W9_SHIFT 24U +#define PINMUX_BALL_W8_SHIFT 0U +#define PINMUX_BALL_V8_SHIFT 8U +#define PINMUX_BALL_H19_SHIFT 16U +#define PINMUX_BALL_E19_SHIFT 24U +#define PINMUX_BALL_B6_SHIFT 0U +#define PINMUX_BALL_W6_SHIFT 8U +#define PINMUX_BALL_T12_SHIFT 16U +#define PINMUX_BALL_H18_SHIFT 24U +#define PINMUX_BALL_J19_SHIFT 0U +#define PINMUX_BALL_E16_SHIFT 8U +#define PINMUX_BALL_H17_SHIFT 16U +#define PINMUX_BALL_G17_SHIFT 24U +#define PINMUX_BALL_J18_SHIFT 0U +#define PINMUX_BALL_E17_SHIFT 8U +#define PINMUX_BALL_H16_SHIFT 16U +#define PINMUX_BALL_G16_SHIFT 24U +#define PINMUX_BALL_K18_SHIFT 0U +#define PINMUX_BALL_V2_SHIFT 8U +#define PINMUX_BALL_W5_SHIFT 16U +#define PINMUX_BALL_U1_SHIFT 24U +#define PINMUX_BALL_B12_SHIFT 0U +#define PINMUX_BALL_V6_SHIFT 8U +#define PINMUX_BALL_W3_SHIFT 16U +#define PINMUX_BALL_T1_SHIFT 24U +#define PINMUX_BALL_E18_SHIFT 0U +#define PINMUX_BALL_V7_SHIFT 8U +#define PINMUX_BALL_D19_SHIFT 16U +#define PINMUX_BALL_E3_SHIFT 24U +#define PINMUX_BALL_B4_SHIFT 0U +#define PINMUX_BALL_N2_SHIFT 8U +#define PINMUX_BALL_N1_SHIFT 16U +#define PINMUX_BALL_A4_SHIFT 24U +#define PINMUX_BALL_A13_SHIFT 0U +#define PINMUX_BALL_J1_SHIFT 8U +#define PINMUX_BALL_B13_SHIFT 16U +#define PINMUX_BALL_P2_SHIFT 24U +#define PINMUX_BALL_H4_SHIFT 0U +#define PINMUX_BALL_B3_SHIFT 8U +#define PINMUX_BALL_J4_SHIFT 16U +#define PINMUX_BALL_P1_SHIFT 24U +#define PINMUX_BALL_A14_SHIFT 0U +#define PINMUX_BALL_K19_SHIFT 8U +#define PINMUX_BALL_B11_SHIFT 16U +#define PINMUX_BALL_D8_SHIFT 24U +#define PINMUX_BALL_D7_SHIFT 0U +#define PINMUX_BALL_D3_SHIFT 8U +#define PINMUX_BALL_D2_SHIFT 16U +#define PINMUX_BALL_D1_SHIFT 24U +#define PINMUX_BALL_P4_SHIFT 0U +#define PINMUX_BALL_T5_SHIFT 8U +#define PINMUX_BALL_T4_SHIFT 16U +#define PINMUX_BALL_U7_SHIFT 24U +#define PINMUX_BALL_E2_SHIFT 0U +#define PINMUX_BALL_N3_SHIFT 8U + +#define PINMUX_GATE_EMIF_CLK_SHIFT 0U +#define PINMUX_EMIF_OUTPUT_ENABLE_SHIFT 8U +#define PINMUX_GIOA_DISABLE_HET1_SHIFT 8U +#define PINMUX_GIOB_DISABLE_HET2_SHIFT 0U +#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0U +#define PINMUX_ETHERNET_SHIFT 24U +#define PINMUX_ETPWM1_SHIFT 0U +#define PINMUX_ETPWM2_SHIFT 8U +#define PINMUX_ETPWM3_SHIFT 16U +#define PINMUX_ETPWM4_SHIFT 24U +#define PINMUX_ETPWM5_SHIFT 0U +#define PINMUX_ETPWM6_SHIFT 8U +#define PINMUX_ETPWM7_SHIFT 16U +#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT 24U +#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT 0U +#define PINMUX_TZ1_SHIFT 16U +#define PINMUX_TZ2_SHIFT 24U +#define PINMUX_TZ3_SHIFT 0U +#define PINMUX_EPWM1SYNCI_SHIFT 8U +#define PINMUX_ETPWM_SOC1A_SHIFT 0U +#define PINMUX_ETPWM_SOC2A_SHIFT 8U +#define PINMUX_ETPWM_SOC3A_SHIFT 16U +#define PINMUX_ETPWM_SOC4A_SHIFT 24U +#define PINMUX_ETPWM_SOC5A_SHIFT 0U +#define PINMUX_ETPWM_SOC6A_SHIFT 8U +#define PINMUX_ETPWM_SOC7A_SHIFT 16U +#define PINMUX_EQEP1A_FILTER_SHIFT 16U +#define PINMUX_EQEP1B_FILTER_SHIFT 24U +#define PINMUX_EQEP1I_FILTER_SHIFT 0U +#define PINMUX_EQEP1S_FILTER_SHIFT 8U +#define PINMUX_EQEP2A_FILTER_SHIFT 16U +#define PINMUX_EQEP2B_FILTER_SHIFT 24U +#define PINMUX_EQEP2I_FILTER_SHIFT 0U +#define PINMUX_EQEP2S_FILTER_SHIFT 8U +#define PINMUX_ECAP1_FILTER_SHIFT 0U +#define PINMUX_ECAP2_FILTER_SHIFT 8U +#define PINMUX_ECAP3_FILTER_SHIFT 16U +#define PINMUX_ECAP4_FILTER_SHIFT 24U +#define PINMUX_ECAP5_FILTER_SHIFT 0U +#define PINMUX_ECAP6_FILTER_SHIFT 8U +#define PINMUX_GIOA0_DMA_SHIFT 0U +#define PINMUX_GIOA1_DMA_SHIFT 8U +#define PINMUX_GIOA2_DMA_SHIFT 16U +#define PINMUX_GIOA3_DMA_SHIFT 24U +#define PINMUX_GIOA4_DMA_SHIFT 0U +#define PINMUX_GIOA5_DMA_SHIFT 8U +#define PINMUX_GIOA6_DMA_SHIFT 16U +#define PINMUX_GIOA7_DMA_SHIFT 24U +#define PINMUX_GIOB0_DMA_SHIFT 0U +#define PINMUX_GIOB1_DMA_SHIFT 8U +#define PINMUX_GIOB2_DMA_SHIFT 16U +#define PINMUX_GIOB3_DMA_SHIFT 24U +#define PINMUX_GIOB4_DMA_SHIFT 0U +#define PINMUX_GIOB5_DMA_SHIFT 8U +#define PINMUX_GIOB6_DMA_SHIFT 16U +#define PINMUX_GIOB7_DMA_SHIFT 24U +#define PINMUX_TEMP1_ENABLE_SHIFT 16U +#define PINMUX_TEMP2_ENABLE_SHIFT 24U +#define PINMUX_TEMP3_ENABLE_SHIFT 0U + +#define PINMUX_BALL_N19_MASK \ + ( ~( uint32 ) ( ( uint32 ) uint32 )( ( uint32 ) 0xFFU << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_D4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_C4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C7_SHIFT ) ) +#define PINMUX_BALL_C8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C8_SHIFT ) ) +#define PINMUX_BALL_C9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C9_SHIFT ) ) +#define PINMUX_BALL_C10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C10_SHIFT ) ) +#define PINMUX_BALL_C11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C11_SHIFT ) ) +#define PINMUX_BALL_C12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C12_SHIFT ) ) +#define PINMUX_BALL_C13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C13_SHIFT ) ) +#define PINMUX_BALL_D14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D14_SHIFT ) ) +#define PINMUX_BALL_C14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C14_SHIFT ) ) +#define PINMUX_BALL_D15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D15_SHIFT ) ) +#define PINMUX_BALL_C15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C15_SHIFT ) ) +#define PINMUX_BALL_C16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C16_SHIFT ) ) +#define PINMUX_BALL_C17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C17_SHIFT ) ) +#define PINMUX_BALL_D16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_K3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_R4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R4_SHIFT ) ) +#define PINMUX_BALL_N17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_L17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L17_SHIFT ) ) +#define PINMUX_BALL_K17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_M17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_R3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R3_SHIFT ) ) +#define PINMUX_BALL_P3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P3_SHIFT ) ) +#define PINMUX_BALL_D17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_E9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E9_SHIFT ) ) +#define PINMUX_BALL_E8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E8_SHIFT ) ) +#define PINMUX_BALL_E7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E7_SHIFT ) ) +#define PINMUX_BALL_E6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E6_SHIFT ) ) +#define PINMUX_BALL_E13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E13_SHIFT ) ) +#define PINMUX_BALL_E12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E12_SHIFT ) ) +#define PINMUX_BALL_E11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E11_SHIFT ) ) +#define PINMUX_BALL_E10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E10_SHIFT ) ) +#define PINMUX_BALL_K15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K15_SHIFT ) ) +#define PINMUX_BALL_L15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L15_SHIFT ) ) +#define PINMUX_BALL_M15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M15_SHIFT ) ) +#define PINMUX_BALL_N15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N15_SHIFT ) ) +#define PINMUX_BALL_E5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E5_SHIFT ) ) +#define PINMUX_BALL_F5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F5_SHIFT ) ) +#define PINMUX_BALL_G5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G5_SHIFT ) ) +#define PINMUX_BALL_K5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K5_SHIFT ) ) +#define PINMUX_BALL_L5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_M5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_N5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_P5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_R5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R10_SHIFT ) ) +#define PINMUX_BALL_R11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R11_SHIFT ) ) +#define PINMUX_BALL_B15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B15_SHIFT ) ) +#define PINMUX_BALL_B8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B8_SHIFT ) ) +#define PINMUX_BALL_B16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B16_SHIFT ) ) +#define PINMUX_BALL_B9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B9_SHIFT ) ) +#define PINMUX_BALL_C1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_E1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_B5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_H3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_M1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_F2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F2_SHIFT ) ) +#define PINMUX_BALL_W10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_J2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J2_SHIFT ) ) +#define PINMUX_BALL_F1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_R2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_F3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_G3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_J3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_G19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_V9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_B2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_C3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_W9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_V8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_H19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_E19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_B6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B6_SHIFT ) ) +#define PINMUX_BALL_W6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W6_SHIFT ) ) +#define PINMUX_BALL_T12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_H18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_J19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_E16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_H17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_G17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_J18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_E17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_H16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_G16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_K18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_V2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_W5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_U1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_B12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_V6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_W3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_T1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_E18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_V7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_D19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_E3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_B4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_N2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_A4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_J1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_B13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_P2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_H4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H4_SHIFT ) ) +#define PINMUX_BALL_B3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_J4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J4_SHIFT ) ) +#define PINMUX_BALL_P1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_A14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_K19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_B11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_D8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D8_SHIFT ) ) +#define PINMUX_BALL_D7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D7_SHIFT ) ) +#define PINMUX_BALL_D3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D2_SHIFT ) ) +#define PINMUX_BALL_D1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D1_SHIFT ) ) +#define PINMUX_BALL_P4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P4_SHIFT ) ) +#define PINMUX_BALL_T5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T5_SHIFT ) ) +#define PINMUX_BALL_T4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T4_SHIFT ) ) +#define PINMUX_BALL_U7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U7_SHIFT ) ) +#define PINMUX_BALL_E2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E2_SHIFT ) ) +#define PINMUX_BALL_N3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N3_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2S_FILTER_SHIFT ) ) +#define PINMUX_ECAP1_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP6_FILTER_SHIFT ) ) + +#define PINMUX_GIOA0_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP3_ENABLE_SHIFT ) ) + +#define PINMUX_BALL_N19_AD1EVT ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_MII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_RMII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_nTZ1_1 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N19_SHIFT ) ) + +#define PINMUX_BALL_D4_EMIF_ADDR_00 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D4_N2HET2_01 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D4_SHIFT ) ) + +#define PINMUX_BALL_D5_EMIF_ADDR_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_D5_N2HET2_03 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D5_SHIFT ) ) + +#define PINMUX_BALL_C4_EMIF_ADDR_06 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_RTP_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_N2HET2_11 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C4_SHIFT ) ) + +#define PINMUX_BALL_C5_EMIF_ADDR_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_RTP_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_N2HET2_13 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C5_SHIFT ) ) + +#define PINMUX_BALL_C6_EMIF_ADDR_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_RTP_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_N2HET2_15 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C6_SHIFT ) ) + +#define PINMUX_BALL_C7_EMIF_ADDR_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C7_SHIFT ) ) +#define PINMUX_BALL_C7_RTP_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C7_SHIFT ) ) + +#define PINMUX_BALL_C8_EMIF_ADDR_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C8_SHIFT ) ) +#define PINMUX_BALL_C8_RTP_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C8_SHIFT ) ) + +#define PINMUX_BALL_C9_EMIF_ADDR_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C9_SHIFT ) ) +#define PINMUX_BALL_C9_RTP_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C9_SHIFT ) ) + +#define PINMUX_BALL_C10_EMIF_ADDR_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C10_SHIFT ) ) +#define PINMUX_BALL_C10_RTP_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C10_SHIFT ) ) + +#define PINMUX_BALL_C11_EMIF_ADDR_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C11_SHIFT ) ) +#define PINMUX_BALL_C11_RTP_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C11_SHIFT ) ) + +#define PINMUX_BALL_C12_EMIF_ADDR_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C12_SHIFT ) ) +#define PINMUX_BALL_C12_RTP_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C12_SHIFT ) ) + +#define PINMUX_BALL_C13_EMIF_ADDR_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C13_SHIFT ) ) +#define PINMUX_BALL_C13_RTP_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C13_SHIFT ) ) + +#define PINMUX_BALL_D14_EMIF_ADDR_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D14_SHIFT ) ) +#define PINMUX_BALL_D14_RTP_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D14_SHIFT ) ) + +#define PINMUX_BALL_C14_EMIF_ADDR_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C14_SHIFT ) ) +#define PINMUX_BALL_C14_RTP_DATA_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C14_SHIFT ) ) + +#define PINMUX_BALL_D15_EMIF_ADDR_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D15_SHIFT ) ) +#define PINMUX_BALL_D15_RTP_DATA_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D15_SHIFT ) ) + +#define PINMUX_BALL_C15_EMIF_ADDR_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C15_SHIFT ) ) +#define PINMUX_BALL_C15_RTP_nENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C15_SHIFT ) ) + +#define PINMUX_BALL_C16_EMIF_ADDR_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C16_SHIFT ) ) +#define PINMUX_BALL_C16_RTP_nSYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C16_SHIFT ) ) + +#define PINMUX_BALL_C17_EMIF_ADDR_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C17_SHIFT ) ) +#define PINMUX_BALL_C17_RTP_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C17_SHIFT ) ) + +#define PINMUX_BALL_D16_EMIF_BA_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_8_25 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_N2HET2_05 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D16_SHIFT ) ) + +#define PINMUX_BALL_K3_RESERVED ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_K3_EMIF_CLK ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_K3_ECLK2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K3_SHIFT ) ) + +#define PINMUX_BALL_R4_EMIF_nCAS \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R4_SHIFT ) ) +#define PINMUX_BALL_R4_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R4_SHIFT ) ) + +#define PINMUX_BALL_N17_EMIF_nCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_RTP_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_N2HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N17_SHIFT ) ) + +#define PINMUX_BALL_L17_EMIF_nCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L17_SHIFT ) ) +#define PINMUX_BALL_L17_GIOB_4 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_L17_SHIFT ) ) + +#define PINMUX_BALL_K17_EMIF_nCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_RTP_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_N2HET2_09 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K17_SHIFT ) ) + +#define PINMUX_BALL_M17_EMIF_nCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_M17_RTP_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_M17_GIOB_5 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M17_SHIFT ) ) + +#define PINMUX_BALL_R3_EMIF_nRAS \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R3_SHIFT ) ) +#define PINMUX_BALL_R3_GIOB_6 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R3_SHIFT ) ) + +#define PINMUX_BALL_P3_EMIF_nWAIT \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P3_SHIFT ) ) +#define PINMUX_BALL_P3_GIOB_7 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P3_SHIFT ) ) + +#define PINMUX_BALL_D17_EMIF_nWE \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_D17_EMIF_RNW \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D17_SHIFT ) ) + +#define PINMUX_BALL_E9_ETMDATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E9_SHIFT ) ) +#define PINMUX_BALL_E9_EMIF_ADDR_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E9_SHIFT ) ) + +#define PINMUX_BALL_E8_ETMDATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E8_SHIFT ) ) +#define PINMUX_BALL_E8_EMIF_ADDR_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E8_SHIFT ) ) + +#define PINMUX_BALL_E7_ETMDATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E7_SHIFT ) ) +#define PINMUX_BALL_E7_EMIF_ADDR_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E7_SHIFT ) ) + +#define PINMUX_BALL_E6_ETMDATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E6_SHIFT ) ) +#define PINMUX_BALL_E6_EMIF_ADDR_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E6_SHIFT ) ) + +#define PINMUX_BALL_E13_ETMDATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E13_SHIFT ) ) +#define PINMUX_BALL_E13_EMIF_BA_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E13_SHIFT ) ) + +#define PINMUX_BALL_E12_ETMDATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E12_SHIFT ) ) +#define PINMUX_BALL_E12_EMIF_nOE \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E12_SHIFT ) ) + +#define PINMUX_BALL_E11_ETMDATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E11_SHIFT ) ) +#define PINMUX_BALL_E11_EMIF_nDQM_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E11_SHIFT ) ) + +#define PINMUX_BALL_E10_ETMDATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E10_SHIFT ) ) +#define PINMUX_BALL_E10_EMIF_nDQM_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E10_SHIFT ) ) + +#define PINMUX_BALL_K15_ETMDATA_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K15_SHIFT ) ) +#define PINMUX_BALL_K15_EMIF_DATA_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K15_SHIFT ) ) + +#define PINMUX_BALL_L15_ETMDATA_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L15_SHIFT ) ) +#define PINMUX_BALL_L15_EMIF_DATA_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_L15_SHIFT ) ) + +#define PINMUX_BALL_M15_ETMDATA_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M15_SHIFT ) ) +#define PINMUX_BALL_M15_EMIF_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M15_SHIFT ) ) + +#define PINMUX_BALL_N15_ETMDATA_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N15_SHIFT ) ) +#define PINMUX_BALL_N15_EMIF_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N15_SHIFT ) ) + +#define PINMUX_BALL_E5_ETMDATA_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E5_SHIFT ) ) +#define PINMUX_BALL_E5_EMIF_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E5_SHIFT ) ) + +#define PINMUX_BALL_F5_ETMDATA_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F5_SHIFT ) ) +#define PINMUX_BALL_F5_EMIF_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F5_SHIFT ) ) + +#define PINMUX_BALL_G5_ETMDATA_22 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G5_SHIFT ) ) +#define PINMUX_BALL_G5_EMIF_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G5_SHIFT ) ) + +#define PINMUX_BALL_K5_ETMDATA_23 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K5_SHIFT ) ) +#define PINMUX_BALL_K5_EMIF_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K5_SHIFT ) ) + +#define PINMUX_BALL_L5_ETMDATA_24 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_EMIF_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_N2HET2_24 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_MIBSPI5NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_L5_SHIFT ) ) + +#define PINMUX_BALL_M5_ETMDATA_25 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_EMIF_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_N2HET2_25 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_MIBSPI5NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_M5_SHIFT ) ) + +#define PINMUX_BALL_N5_ETMDATA_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_N5_EMIF_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_N5_N2HET2_26 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N5_SHIFT ) ) + +#define PINMUX_BALL_P5_ETMDATA_27 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_P5_EMIF_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_P5_N2HET2_27 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P5_SHIFT ) ) + +#define PINMUX_BALL_R5_ETMDATA_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_EMIF_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_N2HET2_28 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_GIOA_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R5_SHIFT ) ) + +#define PINMUX_BALL_R6_ETMDATA_29 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_EMIF_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_N2HET2_29 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_GIOA_1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R6_SHIFT ) ) + +#define PINMUX_BALL_R7_ETMDATA_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_EMIF_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_N2HET2_30 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R7_SHIFT ) ) + +#define PINMUX_BALL_R8_ETMDATA_31 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_EMIF_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_N2HET2_31 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_GIOA_4 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R8_SHIFT ) ) + +#define PINMUX_BALL_R9_ETMTRACECLKIN \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R9_EXTCLKIN2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R9_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R9_SHIFT ) ) + +#define PINMUX_BALL_R10_ETMTRACECLKOUT \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R10_SHIFT ) ) +#define PINMUX_BALL_R10_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R10_SHIFT ) ) + +#define PINMUX_BALL_R11_ETMTRACECTL \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R11_SHIFT ) ) +#define PINMUX_BALL_R11_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R11_SHIFT ) ) + +#define PINMUX_BALL_B15_FRAYTX1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B15_SHIFT ) ) +#define PINMUX_BALL_B15_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B15_SHIFT ) ) + +#define PINMUX_BALL_B8_FRAYTX2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B8_SHIFT ) ) +#define PINMUX_BALL_B8_GIOB_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B8_SHIFT ) ) + +#define PINMUX_BALL_B16_FRAYTXEN1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B16_SHIFT ) ) +#define PINMUX_BALL_B16_GIOB_1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B16_SHIFT ) ) + +#define PINMUX_BALL_B9_FRAYTXEN2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B9_SHIFT ) ) +#define PINMUX_BALL_B9_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B9_SHIFT ) ) + +#define PINMUX_BALL_C1_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_N2HET2_00 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_eQEP2I ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_C1_SHIFT ) ) + +#define PINMUX_BALL_E1_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_E1_N2HET2_02 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E1_SHIFT ) ) + +#define PINMUX_BALL_B5_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_EXTCLKIN ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_eTPWM1A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B5_SHIFT ) ) + +#define PINMUX_BALL_H3_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_N2HET2_04 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_eTPWM1B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H3_SHIFT ) ) + +#define PINMUX_BALL_M1_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_N2HET2_06 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_eTPWM2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_M1_SHIFT ) ) + +#define PINMUX_BALL_F2_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F2_SHIFT ) ) +#define PINMUX_BALL_F2_DCAN4TX ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F2_SHIFT ) ) + +#define PINMUX_BALL_W10_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_W10_DCAN4RX \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W10_SHIFT ) ) + +#define PINMUX_BALL_J2_GIOB_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J2_SHIFT ) ) +#define PINMUX_BALL_J2_nERROR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J2_SHIFT ) ) + +#define PINMUX_BALL_F1_GIOB_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_F1_nERROR2 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_F1_nTZ1_2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_F1_SHIFT ) ) + +#define PINMUX_BALL_R2_MIBSPI1NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MIBSPI1SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MII_TXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_ECAP6 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_R2_SHIFT ) ) + +#define PINMUX_BALL_F3_MIBSPI1NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_MII_COL ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_N2HET1_17 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_eQEP1S ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_F3_SHIFT ) ) + +#define PINMUX_BALL_G3_MIBSPI1NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_MDIO ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_N2HET1_19 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G3_SHIFT ) ) + +#define PINMUX_BALL_J3_MIBSPI1NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_N2HET1_21 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_nTZ1_3 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_J3_SHIFT ) ) + +#define PINMUX_BALL_G19_MIBSPI1NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_MII_RXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_N2HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_ECAP4 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_G19_SHIFT ) ) + +#define PINMUX_BALL_V9_MIBSPI3CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_EXT_SEL_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_eQEP1A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V9_SHIFT ) ) + +#define PINMUX_BALL_V10_MIBSPI3NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_AD2EVT ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_eQEP1I \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V10_SHIFT ) ) + +#define PINMUX_BALL_V5_MIBSPI3NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_MDCLK ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_N2HET1_25 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V5_SHIFT ) ) + +#define PINMUX_BALL_B2_MIBSPI3NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_I2C1_SDA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_N2HET1_27 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_nTZ1_2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B2_SHIFT ) ) + +#define PINMUX_BALL_C3_MIBSPI3NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_I2C1_SCL ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_N2HET1_29 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_nTZ1_1 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_C3_SHIFT ) ) + +#define PINMUX_BALL_W9_MIBSPI3NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_MIBSPI3NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_N2HET1_31 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_eQEP1B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W9_SHIFT ) ) + +#define PINMUX_BALL_W8_MIBSPI3SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_EXT_SEL_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_ECAP3 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W8_SHIFT ) ) + +#define PINMUX_BALL_V8_MIBSPI3SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_EXT_ENA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_ECAP2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V8_SHIFT ) ) + +#define PINMUX_BALL_H19_MIBSPI5CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_DMM_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_MII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_RMII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_H19_SHIFT ) ) + +#define PINMUX_BALL_E19_MIBSPI5NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_DMM_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_eTPWM4A \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E19_SHIFT ) ) + +#define PINMUX_BALL_B6_MIBSPI5NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B6_SHIFT ) ) +#define PINMUX_BALL_B6_DMM_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B6_SHIFT ) ) + +#define PINMUX_BALL_W6_MIBSPI5NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W6_SHIFT ) ) +#define PINMUX_BALL_W6_DMM_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W6_SHIFT ) ) + +#define PINMUX_BALL_T12_MIBSPI5NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_T12_DMM_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T12_SHIFT ) ) + +#define PINMUX_BALL_H18_MIBSPI5NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_DMM_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_MII_RXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_ECAP5 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H18_SHIFT ) ) + +#define PINMUX_BALL_J19_MIBSPI5SIMO_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_DMM_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_MII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_RMII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J19_SHIFT ) ) + +#define PINMUX_BALL_E16_MIBSPI5SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_E16_DMM_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_E16_EXT_SEL_00 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E16_SHIFT ) ) + +#define PINMUX_BALL_H17_MIBSPI5SIMO_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_H17_DMM_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_H17_EXT_SEL_01 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H17_SHIFT ) ) + +#define PINMUX_BALL_G17_MIBSPI5SIMO_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_DMM_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_I2C2_SDA \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_EXT_SEL_02 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G17_SHIFT ) ) + +#define PINMUX_BALL_J18_MIBSPI5SOMI_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_DMM_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_MII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_RMII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J18_SHIFT ) ) + +#define PINMUX_BALL_E17_MIBSPI5SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_E17_DMM_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_E17_EXT_SEL_03 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E17_SHIFT ) ) + +#define PINMUX_BALL_H16_MIBSPI5SOMI_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_H16_DMM_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_H16_EXT_SEL_04 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H16_SHIFT ) ) + +#define PINMUX_BALL_G16_MIBSPI5SOMI_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_DMM_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_I2C2_SCL \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_EXT_ENA \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G16_SHIFT ) ) + +#define PINMUX_BALL_K18_N2HET1_00 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_MIBSPI4CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_eTPWM2B \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_K18_SHIFT ) ) + +#define PINMUX_BALL_V2_N2HET1_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_MIBSPI4NENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_N2HET2_08 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_eQEP2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V2_SHIFT ) ) + +#define PINMUX_BALL_W5_N2HET1_02 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_MIBSPI4SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_eTPWM3A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W5_SHIFT ) ) + +#define PINMUX_BALL_U1_N2HET1_03 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_MIBSPI4NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_N2HET2_10 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_eQEP2B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_U1_SHIFT ) ) + +#define PINMUX_BALL_B12_N2HET1_04 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_MIBSPI4NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_eTPWM4B \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B12_SHIFT ) ) + +#define PINMUX_BALL_V6_N2HET1_05 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_MIBSPI4SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_N2HET2_12 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_eTPWM3B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V6_SHIFT ) ) + +#define PINMUX_BALL_W3_N2HET1_06 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_SCI3RX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_eTPWM5A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W3_SHIFT ) ) + +#define PINMUX_BALL_T1_N2HET1_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_MIBSPI4NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_N2HET2_14 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_eTPWM7B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_T1_SHIFT ) ) + +#define PINMUX_BALL_E18_N2HET1_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MIBSPI1SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MII_TXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E18_SHIFT ) ) + +#define PINMUX_BALL_V7_N2HET1_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_MIBSPI4NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_N2HET2_16 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_eTPWM7A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V7_SHIFT ) ) + +#define PINMUX_BALL_D19_N2HET1_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MIBSPI4NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_nTZ1_3 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_D19_SHIFT ) ) + +#define PINMUX_BALL_E3_N2HET1_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_MIBSPI3NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_N2HET2_18 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E3_SHIFT ) ) + +#define PINMUX_BALL_B4_N2HET1_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MIBSPI4NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MII_CRS ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_RMII_CRS_DV \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B4_SHIFT ) ) + +#define PINMUX_BALL_N2_N2HET1_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_SCI3TX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_N2HET2_20 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_eTPWM5B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N2_SHIFT ) ) + +#define PINMUX_BALL_N1_N2HET1_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_MIBSPI1NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_N2HET2_22 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_ECAP1 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N1_SHIFT ) ) + +#define PINMUX_BALL_A4_N2HET1_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCI \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_A4_SHIFT ) ) + +#define PINMUX_BALL_A13_N2HET1_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_A13_EMIF_nOE \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_A13_SCI4RX ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A13_SHIFT ) ) + +#define PINMUX_BALL_J1_N2HET1_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_EMIF_RNW ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_eTPWM6A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_J1_SHIFT ) ) + +#define PINMUX_BALL_B13_N2HET1_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_B13_EMIF_nDQM_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_B13_SCI4TX ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B13_SHIFT ) ) + +#define PINMUX_BALL_P2_N2HET1_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_EMIF_nDQM_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_eTPWM6B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_P2_SHIFT ) ) + +#define PINMUX_BALL_H4_N2HET1_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H4_SHIFT ) ) +#define PINMUX_BALL_H4_EMIF_nDQM_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H4_SHIFT ) ) + +#define PINMUX_BALL_B3_N2HET1_22 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_B3_EMIF_nDQM_3 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B3_SHIFT ) ) + +#define PINMUX_BALL_J4_N2HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J4_SHIFT ) ) +#define PINMUX_BALL_J4_EMIF_BA_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J4_SHIFT ) ) + +#define PINMUX_BALL_P1_N2HET1_24 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MIBSPI1NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_RMII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_P1_SHIFT ) ) + +#define PINMUX_BALL_A14_N2HET1_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_MII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_RMII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_A14_SHIFT ) ) + +#define PINMUX_BALL_K19_N2HET1_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_RMII_REFCLK \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_K19_SHIFT ) ) + +#define PINMUX_BALL_B11_N2HET1_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_MII_RX_DV \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_eQEP2S \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B11_SHIFT ) ) + +#define PINMUX_BALL_D8_N2HET2_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D8_SHIFT ) ) +#define PINMUX_BALL_D8_N2HET1_NDIS \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D8_SHIFT ) ) + +#define PINMUX_BALL_D7_N2HET2_02 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D7_SHIFT ) ) +#define PINMUX_BALL_D7_N2HET2_NDIS \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D7_SHIFT ) ) + +#define PINMUX_BALL_D3_N2HET2_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_MIBSPI2NENA \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_MIBSPI2NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_D3_SHIFT ) ) + +#define PINMUX_BALL_D2_N2HET2_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D2_SHIFT ) ) +#define PINMUX_BALL_D2_MIBSPI2SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D2_SHIFT ) ) + +#define PINMUX_BALL_D1_N2HET2_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D1_SHIFT ) ) +#define PINMUX_BALL_D1_MIBSPI2SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D1_SHIFT ) ) + +#define PINMUX_BALL_P4_N2HET2_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P4_SHIFT ) ) +#define PINMUX_BALL_P4_LIN2RX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P4_SHIFT ) ) + +#define PINMUX_BALL_T5_N2HET2_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T5_SHIFT ) ) +#define PINMUX_BALL_T5_LIN2TX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T5_SHIFT ) ) + +#define PINMUX_BALL_T4_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T4_SHIFT ) ) +#define PINMUX_BALL_T4_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_T4_SHIFT ) ) + +#define PINMUX_BALL_U7_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U7_SHIFT ) ) +#define PINMUX_BALL_U7_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_U7_SHIFT ) ) + +#define PINMUX_BALL_E2_N2HET2_03 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E2_SHIFT ) ) +#define PINMUX_BALL_E2_MIBSPI2CLK \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E2_SHIFT ) ) + +#define PINMUX_BALL_N3_N2HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N3_SHIFT ) ) +#define PINMUX_BALL_N3_MIBSPI2NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_N3_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_GATE_EMIF_CLK_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MII ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETHERNET_SHIFT ) ) +#define PINMUX_ETHERNET_RMII ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_ASYNC \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_SYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_FILTERED \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2S_FILTER_SHIFT ) ) + +#define PINMUX_ECAP1_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP1_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP6_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP6_FILTER_SHIFT ) ) + +#define PINMUX_GIOA0_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA0_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP3_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP3_ENABLE_SHIFT ) ) + +#define SIGNAL_AD2EVT_SHIFT 0U +#define SIGNAL_GIOA_0_SHIFT 24U +#define SIGNAL_GIOA_1_SHIFT 0U +#define SIGNAL_GIOA_2_SHIFT 8U +#define SIGNAL_GIOA_3_SHIFT 16U +#define SIGNAL_GIOA_4_SHIFT 24U +#define SIGNAL_GIOA_5_SHIFT 0U +#define SIGNAL_GIOA_6_SHIFT 8U +#define SIGNAL_GIOA_7_SHIFT 16U +#define SIGNAL_GIOB_0_SHIFT 24U +#define SIGNAL_GIOB_1_SHIFT 0U +#define SIGNAL_GIOB_2_SHIFT 8U +#define SIGNAL_GIOB_3_SHIFT 16U +#define SIGNAL_GIOB_4_SHIFT 24U +#define SIGNAL_GIOB_5_SHIFT 0U +#define SIGNAL_GIOB_6_SHIFT 8U +#define SIGNAL_GIOB_7_SHIFT 16U +#define SIGNAL_MDIO_SHIFT 24U +#define SIGNAL_MIBSPI1NCS_4_SHIFT 0U +#define SIGNAL_MIBSPI1NCS_5_SHIFT 8U +#define SIGNAL_MII_COL_SHIFT 16U +#define SIGNAL_MII_CRS_SHIFT 24U +#define SIGNAL_MII_RX_DV_SHIFT 0U +#define SIGNAL_MII_RX_ER_SHIFT 8U +#define SIGNAL_MII_RXCLK_SHIFT 16U +#define SIGNAL_MII_RXD_0_SHIFT 24U +#define SIGNAL_MII_RXD_1_SHIFT 0U +#define SIGNAL_MII_RXD_2_SHIFT 8U +#define SIGNAL_MII_RXD_3_SHIFT 16U +#define SIGNAL_MII_TX_CLK_SHIFT 24U +#define SIGNAL_N2HET1_17_SHIFT 0U +#define SIGNAL_N2HET1_19_SHIFT 8U +#define SIGNAL_N2HET1_21_SHIFT 16U +#define SIGNAL_N2HET1_23_SHIFT 24U +#define SIGNAL_N2HET1_25_SHIFT 0U +#define SIGNAL_N2HET1_27_SHIFT 8U +#define SIGNAL_N2HET1_29_SHIFT 16U +#define SIGNAL_N2HET1_31_SHIFT 24U +#define SIGNAL_N2HET2_00_SHIFT 0U +#define SIGNAL_N2HET2_01_SHIFT 8U +#define SIGNAL_N2HET2_02_SHIFT 16U +#define SIGNAL_N2HET2_03_SHIFT 24U +#define SIGNAL_N2HET2_04_SHIFT 0U +#define SIGNAL_N2HET2_05_SHIFT 8U +#define SIGNAL_N2HET2_06_SHIFT 16U +#define SIGNAL_N2HET2_07_SHIFT 24U +#define SIGNAL_N2HET2_08_SHIFT 0U +#define SIGNAL_N2HET2_09_SHIFT 8U +#define SIGNAL_N2HET2_10_SHIFT 16U +#define SIGNAL_N2HET2_11_SHIFT 24U +#define SIGNAL_N2HET2_12_SHIFT 0U +#define SIGNAL_N2HET2_13_SHIFT 8U +#define SIGNAL_N2HET2_14_SHIFT 16U +#define SIGNAL_N2HET2_15_SHIFT 24U +#define SIGNAL_N2HET2_16_SHIFT 0U +#define SIGNAL_N2HET2_18_SHIFT 8U +#define SIGNAL_N2HET2_20_SHIFT 16U +#define SIGNAL_N2HET2_22_SHIFT 24U +#define SIGNAL_nTZ1_1_SHIFT 0U +#define SIGNAL_nTZ1_2_SHIFT 8U +#define SIGNAL_nTZ1_3_SHIFT 16U + +#define SIGNAL_AD2EVT_T10 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_AD2EVT_SHIFT ) ) +#define SIGNAL_AD2EVT_V10 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_AD2EVT_SHIFT ) ) + +#define SIGNAL_GIOA_0_A5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_0_SHIFT ) ) +#define SIGNAL_GIOA_0_R5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_0_SHIFT ) ) + +#define SIGNAL_GIOA_1_C2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_1_SHIFT ) ) +#define SIGNAL_GIOA_1_R6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_1_SHIFT ) ) + +#define SIGNAL_GIOA_2_C1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_2_SHIFT ) ) +#define SIGNAL_GIOA_2_B15 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_2_SHIFT ) ) + +#define SIGNAL_GIOA_3_E1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_3_SHIFT ) ) +#define SIGNAL_GIOA_3_R7 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_3_SHIFT ) ) + +#define SIGNAL_GIOA_4_A6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_4_SHIFT ) ) +#define SIGNAL_GIOA_4_R8 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_4_SHIFT ) ) + +#define SIGNAL_GIOA_5_B5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_5_SHIFT ) ) +#define SIGNAL_GIOA_5_R9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_5_SHIFT ) ) + +#define SIGNAL_GIOA_6_H3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_6_SHIFT ) ) +#define SIGNAL_GIOA_6_R10 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_6_SHIFT ) ) + +#define SIGNAL_GIOA_7_M1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_7_SHIFT ) ) +#define SIGNAL_GIOA_7_R11 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_7_SHIFT ) ) + +#define SIGNAL_GIOB_0_M2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_0_SHIFT ) ) +#define SIGNAL_GIOB_0_B8 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_0_SHIFT ) ) + +#define SIGNAL_GIOB_1_K2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_1_SHIFT ) ) +#define SIGNAL_GIOB_1_B16 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_1_SHIFT ) ) + +#define SIGNAL_GIOB_2_F2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_2_SHIFT ) ) +#define SIGNAL_GIOB_2_B9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_2_SHIFT ) ) + +#define SIGNAL_GIOB_3_W10 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_3_SHIFT ) ) +#define SIGNAL_GIOB_3_R4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_3_SHIFT ) ) + +#define SIGNAL_GIOB_4_G1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_4_SHIFT ) ) +#define SIGNAL_GIOB_4_L17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_4_SHIFT ) ) + +#define SIGNAL_GIOB_5_G2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_5_SHIFT ) ) +#define SIGNAL_GIOB_5_M17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_5_SHIFT ) ) + +#define SIGNAL_GIOB_6_J2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_6_SHIFT ) ) +#define SIGNAL_GIOB_6_R3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_6_SHIFT ) ) + +#define SIGNAL_GIOB_7_F1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_7_SHIFT ) ) +#define SIGNAL_GIOB_7_P3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_7_SHIFT ) ) + +#define SIGNAL_MDIO_F4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MDIO_SHIFT ) ) +#define SIGNAL_MDIO_G3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MDIO_SHIFT ) ) + +#define SIGNAL_MIBSPI1NCS_4_U10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MIBSPI1NCS_4_SHIFT ) ) +#define SIGNAL_MIBSPI1NCS_4_N1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MIBSPI1NCS_4_SHIFT ) ) + +#define SIGNAL_MIBSPI1NCS_5_U9 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MIBSPI1NCS_5_SHIFT ) ) +#define SIGNAL_MIBSPI1NCS_5_P1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MIBSPI1NCS_5_SHIFT ) ) + +#define SIGNAL_MII_COL_W4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_COL_SHIFT ) ) +#define SIGNAL_MII_COL_F3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_COL_SHIFT ) ) + +#define SIGNAL_MII_CRS_V4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_CRS_SHIFT ) ) +#define SIGNAL_MII_CRS_B4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_CRS_SHIFT ) ) + +#define SIGNAL_MII_RX_DV_U6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RX_DV_SHIFT ) ) +#define SIGNAL_MII_RX_DV_B11 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RX_DV_SHIFT ) ) + +#define SIGNAL_MII_RX_ER_U5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RX_ER_SHIFT ) ) +#define SIGNAL_MII_RX_ER_N19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RX_ER_SHIFT ) ) + +#define SIGNAL_MII_RXCLK_T4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXCLK_SHIFT ) ) +#define SIGNAL_MII_RXCLK_K19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXCLK_SHIFT ) ) + +#define SIGNAL_MII_RXD_0_U4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_0_SHIFT ) ) +#define SIGNAL_MII_RXD_0_P1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_0_SHIFT ) ) + +#define SIGNAL_MII_RXD_1_T3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_1_SHIFT ) ) +#define SIGNAL_MII_RXD_1_A14 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_1_SHIFT ) ) + +#define SIGNAL_MII_RXD_2_U3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_2_SHIFT ) ) +#define SIGNAL_MII_RXD_2_G19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_2_SHIFT ) ) + +#define SIGNAL_MII_RXD_3_V3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_3_SHIFT ) ) +#define SIGNAL_MII_RXD_3_H18 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_3_SHIFT ) ) + +#define SIGNAL_MII_TX_CLK_U7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_TX_CLK_SHIFT ) ) +#define SIGNAL_MII_TX_CLK_D19 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_TX_CLK_SHIFT ) ) + +#define SIGNAL_N2HET1_17_A13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_17_SHIFT ) ) +#define SIGNAL_N2HET1_17_F3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_17_SHIFT ) ) + +#define SIGNAL_N2HET1_19_B13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_19_SHIFT ) ) +#define SIGNAL_N2HET1_19_G3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_19_SHIFT ) ) + +#define SIGNAL_N2HET1_21_H4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_21_SHIFT ) ) +#define SIGNAL_N2HET1_21_J3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_21_SHIFT ) ) + +#define SIGNAL_N2HET1_23_J4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_23_SHIFT ) ) +#define SIGNAL_N2HET1_23_G19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_23_SHIFT ) ) + +#define SIGNAL_N2HET1_25_M3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_25_SHIFT ) ) +#define SIGNAL_N2HET1_25_V5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_25_SHIFT ) ) + +#define SIGNAL_N2HET1_27_A9 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_27_SHIFT ) ) +#define SIGNAL_N2HET1_27_B2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_27_SHIFT ) ) + +#define SIGNAL_N2HET1_29_A3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_29_SHIFT ) ) +#define SIGNAL_N2HET1_29_C3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_29_SHIFT ) ) + +#define SIGNAL_N2HET1_31_J17 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_31_SHIFT ) ) +#define SIGNAL_N2HET1_31_W9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_31_SHIFT ) ) + +#define SIGNAL_N2HET2_00_D6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_00_SHIFT ) ) +#define SIGNAL_N2HET2_00_C1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_00_SHIFT ) ) + +#define SIGNAL_N2HET2_01_D8 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_01_SHIFT ) ) +#define SIGNAL_N2HET2_01_D4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_01_SHIFT ) ) + +#define SIGNAL_N2HET2_02_D7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_02_SHIFT ) ) +#define SIGNAL_N2HET2_02_E1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_02_SHIFT ) ) + +#define SIGNAL_N2HET2_03_E2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_03_SHIFT ) ) +#define SIGNAL_N2HET2_03_D5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_03_SHIFT ) ) + +#define SIGNAL_N2HET2_04_D13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_04_SHIFT ) ) +#define SIGNAL_N2HET2_04_H3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_04_SHIFT ) ) + +#define SIGNAL_N2HET2_05_D12 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_05_SHIFT ) ) +#define SIGNAL_N2HET2_05_D16 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_05_SHIFT ) ) + +#define SIGNAL_N2HET2_06_D11 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_06_SHIFT ) ) +#define SIGNAL_N2HET2_06_M1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_06_SHIFT ) ) + +#define SIGNAL_N2HET2_07_N3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_07_SHIFT ) ) +#define SIGNAL_N2HET2_07_N17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_07_SHIFT ) ) + +#define SIGNAL_N2HET2_08_K16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_08_SHIFT ) ) +#define SIGNAL_N2HET2_08_V2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_08_SHIFT ) ) + +#define SIGNAL_N2HET2_09_L16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_09_SHIFT ) ) +#define SIGNAL_N2HET2_09_K17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_09_SHIFT ) ) + +#define SIGNAL_N2HET2_10_M16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_10_SHIFT ) ) +#define SIGNAL_N2HET2_10_U1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_10_SHIFT ) ) + +#define SIGNAL_N2HET2_11_N16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_11_SHIFT ) ) +#define SIGNAL_N2HET2_11_C4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_11_SHIFT ) ) + +#define SIGNAL_N2HET2_12_D3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_12_SHIFT ) ) +#define SIGNAL_N2HET2_12_V6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_12_SHIFT ) ) + +#define SIGNAL_N2HET2_13_D2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_13_SHIFT ) ) +#define SIGNAL_N2HET2_13_C5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_13_SHIFT ) ) + +#define SIGNAL_N2HET2_14_D1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_14_SHIFT ) ) +#define SIGNAL_N2HET2_14_T1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_14_SHIFT ) ) + +#define SIGNAL_N2HET2_15_K4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_15_SHIFT ) ) +#define SIGNAL_N2HET2_15_C6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_15_SHIFT ) ) + +#define SIGNAL_N2HET2_16_L4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_16_SHIFT ) ) +#define SIGNAL_N2HET2_16_V7 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_16_SHIFT ) ) + +#define SIGNAL_N2HET2_18_N4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_18_SHIFT ) ) +#define SIGNAL_N2HET2_18_E3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_18_SHIFT ) ) + +#define SIGNAL_N2HET2_20_T5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_20_SHIFT ) ) +#define SIGNAL_N2HET2_20_N2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_20_SHIFT ) ) + +#define SIGNAL_N2HET2_22_T7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_22_SHIFT ) ) +#define SIGNAL_N2HET2_22_N1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_22_SHIFT ) ) + +#define SIGNAL_nTZ1_1_N19 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_1_SHIFT ) ) +#define SIGNAL_nTZ1_1_C3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_1_SHIFT ) ) + +#define SIGNAL_nTZ1_2_F1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_2_SHIFT ) ) +#define SIGNAL_nTZ1_2_B2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_2_SHIFT ) ) + +#define SIGNAL_nTZ1_3_J3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_3_SHIFT ) ) +#define SIGNAL_nTZ1_3_D19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_3_SHIFT ) ) + +/** @fn void muxInit(void) + * @brief Initializes the PINMUX Driver + * + * This function initializes the PINMUX module and configures the selected + * pinmux settings as per the user selection in the GUI + */ +void muxInit( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h new file mode 100644 index 00000000000..bedac83e298 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h @@ -0,0 +1,339 @@ +/** @file pom.h + * @brief POM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __POM_H__ +#define __POM_H__ + +#include "reg_pom.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pom_region_size + * @brief Alias names for pom region size + * This enumeration is used to provide alias names for POM region size: + */ +enum pom_region_size +{ + SIZE_32BYTES = 0U, + SIZE_64BYTES = 1U, + SIZE_128BYTES = 2U, + SIZE_256BYTES = 3U, + SIZE_512BYTES = 4U, + SIZE_1KB = 5U, + SIZE_2KB = 6U, + SIZE_4KB = 7U, + SIZE_8KB = 8U, + SIZE_16KB = 9U, + SIZE_32KB = 10U, + SIZE_64KB = 11U, + SIZE_128KB = 12U, + SIZE_256KB = 13U +}; + +/** @def INTERNAL_RAM + * @brief Alias name for Internal RAM + */ +#define INTERNAL_RAM 0x08000000U + +/** @def SDRAM + * @brief Alias name for SD RAM + */ +#define SDRAM 0x80000000U + +/** @def ASYNC_MEMORY + * @brief Alias name for Async RAM + */ +#define ASYNC_MEMORY 0x60000000U + +typedef uint32 REGION_t; + +/** @struct REGION_CONFIG_ST + * @brief POM region configuration + */ +typedef struct +{ + uint32 Prog_Reg_Sta_Addr; + uint32 Ovly_Reg_Sta_Addr; + uint32 Reg_Size; +} REGION_CONFIG_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct pom_config_reg +{ + uint32 CONFIG_POMGLBCTRL; + uint32 CONFIG_POMPROGSTART0; + uint32 CONFIG_POMOVLSTART0; + uint32 CONFIG_POMREGSIZE0; + uint32 CONFIG_POMPROGSTART1; + uint32 CONFIG_POMOVLSTART1; + uint32 CONFIG_POMREGSIZE1; + uint32 CONFIG_POMPROGSTART2; + uint32 CONFIG_POMOVLSTART2; + uint32 CONFIG_POMREGSIZE2; + uint32 CONFIG_POMPROGSTART3; + uint32 CONFIG_POMOVLSTART3; + uint32 CONFIG_POMREGSIZE3; + uint32 CONFIG_POMPROGSTART4; + uint32 CONFIG_POMOVLSTART4; + uint32 CONFIG_POMREGSIZE4; + uint32 CONFIG_POMPROGSTART5; + uint32 CONFIG_POMOVLSTART5; + uint32 CONFIG_POMREGSIZE5; + uint32 CONFIG_POMPROGSTART6; + uint32 CONFIG_POMOVLSTART6; + uint32 CONFIG_POMREGSIZE6; + uint32 CONFIG_POMPROGSTART7; + uint32 CONFIG_POMOVLSTART7; + uint32 CONFIG_POMREGSIZE7; + uint32 CONFIG_POMPROGSTART8; + uint32 CONFIG_POMOVLSTART8; + uint32 CONFIG_POMREGSIZE8; + uint32 CONFIG_POMPROGSTART9; + uint32 CONFIG_POMOVLSTART9; + uint32 CONFIG_POMREGSIZE9; + uint32 CONFIG_POMPROGSTART10; + uint32 CONFIG_POMOVLSTART10; + uint32 CONFIG_POMREGSIZE10; + uint32 CONFIG_POMPROGSTART11; + uint32 CONFIG_POMOVLSTART11; + uint32 CONFIG_POMREGSIZE11; + uint32 CONFIG_POMPROGSTART12; + uint32 CONFIG_POMOVLSTART12; + uint32 CONFIG_POMREGSIZE12; + uint32 CONFIG_POMPROGSTART13; + uint32 CONFIG_POMOVLSTART13; + uint32 CONFIG_POMREGSIZE13; + uint32 CONFIG_POMPROGSTART14; + uint32 CONFIG_POMOVLSTART14; + uint32 CONFIG_POMREGSIZE14; + uint32 CONFIG_POMPROGSTART15; + uint32 CONFIG_POMOVLSTART15; + uint32 CONFIG_POMREGSIZE15; + uint32 CONFIG_POMPROGSTART16; + uint32 CONFIG_POMOVLSTART16; + uint32 CONFIG_POMREGSIZE16; + uint32 CONFIG_POMPROGSTART17; + uint32 CONFIG_POMOVLSTART17; + uint32 CONFIG_POMREGSIZE17; + uint32 CONFIG_POMPROGSTART18; + uint32 CONFIG_POMOVLSTART18; + uint32 CONFIG_POMREGSIZE18; + uint32 CONFIG_POMPROGSTART19; + uint32 CONFIG_POMOVLSTART19; + uint32 CONFIG_POMREGSIZE19; + uint32 CONFIG_POMPROGSTART20; + uint32 CONFIG_POMOVLSTART20; + uint32 CONFIG_POMREGSIZE20; + uint32 CONFIG_POMPROGSTART21; + uint32 CONFIG_POMOVLSTART21; + uint32 CONFIG_POMREGSIZE21; + uint32 CONFIG_POMPROGSTART22; + uint32 CONFIG_POMOVLSTART22; + uint32 CONFIG_POMREGSIZE22; + uint32 CONFIG_POMPROGSTART23; + uint32 CONFIG_POMOVLSTART23; + uint32 CONFIG_POMREGSIZE23; + uint32 CONFIG_POMPROGSTART24; + uint32 CONFIG_POMOVLSTART24; + uint32 CONFIG_POMREGSIZE24; + uint32 CONFIG_POMPROGSTART25; + uint32 CONFIG_POMOVLSTART25; + uint32 CONFIG_POMREGSIZE25; + uint32 CONFIG_POMPROGSTART26; + uint32 CONFIG_POMOVLSTART26; + uint32 CONFIG_POMREGSIZE26; + uint32 CONFIG_POMPROGSTART27; + uint32 CONFIG_POMOVLSTART27; + uint32 CONFIG_POMREGSIZE27; + uint32 CONFIG_POMPROGSTART28; + uint32 CONFIG_POMOVLSTART28; + uint32 CONFIG_POMREGSIZE28; + uint32 CONFIG_POMPROGSTART29; + uint32 CONFIG_POMOVLSTART29; + uint32 CONFIG_POMREGSIZE29; + uint32 CONFIG_POMPROGSTART30; + uint32 CONFIG_POMOVLSTART30; + uint32 CONFIG_POMREGSIZE30; + uint32 CONFIG_POMPROGSTART31; + uint32 CONFIG_POMOVLSTART31; + uint32 CONFIG_POMREGSIZE31; +} pom_config_reg_t; + +/* Configuration registers initial value for POM*/ +#define POM_POMGLBCTRL_CONFIGVALUE ( ( uint32 ) INTERNAL_RAM | 0x00000005U ) +#define POM_POMPROGSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU ) +#define POM_POMOVLSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define POM_POMREGSIZE0_CONFIGVALUE ( ( uint32 ) SIZE_64BYTES ) +#define POM_POMPROGSTART1_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART1_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE1_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART2_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART2_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE2_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART3_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART3_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE3_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART4_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART4_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE4_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART5_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART5_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE5_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART6_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART6_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE6_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART7_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART7_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE7_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART8_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART8_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE8_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART9_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART9_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE9_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART10_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART10_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE10_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART11_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART11_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE11_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART12_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART12_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE12_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART13_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART13_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE13_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART14_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART14_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE14_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART15_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART15_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE15_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART16_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART16_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE16_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART17_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART17_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE17_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART18_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART18_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE18_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART19_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART19_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE19_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART20_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART20_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE20_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART21_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART21_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE21_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART22_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART22_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE22_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART23_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART23_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE23_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART24_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART24_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE24_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART25_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART25_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE25_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART26_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART26_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE26_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART27_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART27_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE27_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART28_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART28_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE28_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART29_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART29_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE29_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART30_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART30_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE30_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART31_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART31_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE31_CONFIGVALUE 0x00000000U + +/** + * @defgroup POM POM + * @brief Parameter Overlay Module. + * + * The POM provides a mechanism to redirect accesses to non-volatile memory into a + * volatile memory internal or external to the device. The data requested by the CPU will + * be fetched from the overlay memory instead of the main non-volatile memory. + * + * Related Files + * - reg_pom.h + * - pom.h + * - pom.c + * @addtogroup POM + * @{ + */ + +/* POM Interface Functions */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ); +void POM_Reset( void ); +void POM_Init( void ); +void POM_Enable( void ); +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* __POM_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h new file mode 100644 index 00000000000..1e8f755d94b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h @@ -0,0 +1,252 @@ +/** @file reg_adc.h + * @brief ADC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ADC_H__ +#define __REG_ADC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Adc Register Frame Definition */ +/** @struct adcBase + * @brief ADC Register Frame Definition + * + * This type is used to access the ADC Registers. + */ +/** @typedef adcBASE_t + * @brief ADC Register Frame Type Definition + * + * This type is used to access the ADC Registers. + */ +typedef volatile struct adcBase +{ + uint32 RSTCR; /**< 0x0000: Reset control register */ + uint32 OPMODECR; /**< 0x0004: Operating mode control register */ + uint32 CLOCKCR; /**< 0x0008: Clock control register */ + uint32 CALCR; /**< 0x000C: Calibration control register */ + uint32 GxMODECR[ 3U ]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */ + uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */ + uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */ + uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */ + uint32 GxINTENA[ 3U ]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register + */ + uint32 GxINTFLG[ 3U ]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */ + uint32 GxINTCR[ 3U ]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */ + uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */ + uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */ + uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */ + uint32 BNDCR; /**< 0x0058: Buffer boundary control register */ + uint32 BNDEND; /**< 0x005C: Buffer boundary end register */ + uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */ + uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */ + uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */ + uint32 EVSR; /**< 0x006C: Group 0 status register */ + uint32 G1SR; /**< 0x0070: Group 1 status register */ + uint32 G2SR; /**< 0x0074: Group 2 status register */ + uint32 GxSEL[ 3U ]; /**< 0x0078-0x007C: Group 0-2 channel select register */ + uint32 CALR; /**< 0x0084: Calibration register */ + uint32 SMSTATE; /**< 0x0088: State machine state register */ + uint32 LASTCONV; /**< 0x008C: Last conversion register */ + struct + { + uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */ + uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */ + uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */ + uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */ + uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */ + uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */ + uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */ + uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */ + } GxBUF[ 3U ]; + uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */ + uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */ + uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */ + uint32 EVTDIR; /**< 0x00FC: Event pin direction register */ + uint32 EVTOUT; /**< 0x0100: Event pin digital output register */ + uint32 EVTIN; /**< 0x0104: Event pin digital input register */ + uint32 EVTSET; /**< 0x0108: Event pin set register */ + uint32 EVTCLR; /**< 0x010C: Event pin clear register */ + uint32 EVTPDR; /**< 0x0110: Event pin open drain register */ + uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */ + uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */ + uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */ + uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */ + uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */ + uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */ + uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */ + uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */ + uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */ + uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */ + uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */ + uint32 rsvd1; /**< 0x0140: Reserved */ + uint32 rsvd2; /**< 0x0144: Reserved */ + uint32 rsvd3; /**< 0x0148: Reserved */ + uint32 rsvd4; /**< 0x014C: Reserved */ + uint32 rsvd5; /**< 0x0150: Reserved */ + uint32 rsvd6; /**< 0x0154: Reserved */ + uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */ + uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */ + uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */ + uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */ + uint32 GxFIFORESETCR[ 3U ]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register + */ + uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */ + uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */ + uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */ + uint32 PARCR; /**< 0x0180: Parity control register */ + uint32 PARADDR; /**< 0x0184: Parity error address register */ + uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */ + uint32 rsvd7; /**< 0x018C: Reserved */ + uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control + Register */ + uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register + */ + uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register + */ + uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */ + uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */ + uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */ + uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */ + uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */ + uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */ +} adcBASE_t; + +/** @struct adcLUTEntry + * @brief ADC Look-Up Table Entry + * + * This type is used to access ADC Look-Up Table Entry + */ +/** @typedef adcLUTEntry_t + * @brief ADC Look-Up Table Entry + * + * This type is used to access the Look-Up Table Entry. + */ +typedef struct adcLUTEntry +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 EV_INT_CHN_MUX_SEL; + uint8 EV_EXT_CHN_MUX_SEL; + uint16 rsvd; +#else + uint16 rsvd; + uint8 EV_EXT_CHN_MUX_SEL; + uint8 EV_INT_CHN_MUX_SEL; +#endif +} adcLUTEntry_t; + +/** @struct adcLUT + * @brief ADC Look-Up Table + * + * This type is used to access ADC Look-Up Table + */ +/** @typedef adcLUT_t + * @brief ADC Look-Up Table + * + * This type is used to access the ADC Look-Up Table. + */ +typedef volatile struct adcLUT +{ + adcLUTEntry_t eventGroup[ 32 ]; + adcLUTEntry_t Group1[ 32 ]; + adcLUTEntry_t Group2[ 32 ]; +} adcLUT_t; + +/** @def adcREG1 + * @brief ADC1 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC1 registers. + */ +#define adcREG1 ( ( adcBASE_t * ) 0xFFF7C000U ) + +/** @def adcREG2 + * @brief ADC2 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC2 registers. + */ +#define adcREG2 ( ( adcBASE_t * ) 0xFFF7C200U ) + +/** @def adcRAM1 + * @brief ADC1 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 RAM. + */ +#define adcRAM1 ( *( volatile uint32 * ) 0xFF3E0000U ) + +/** @def adcRAM2 + * @brief ADC2 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 RAM. + */ +#define adcRAM2 ( *( volatile uint32 * ) 0xFF3A0000U ) + +/** @def adcPARRAM1 + * @brief ADC1 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 Parity RAM. + */ +#define adcPARRAM1 ( *( volatile uint32 * ) ( 0xFF3E0000U + 0x1000U ) ) + +/** @def adcPARRAM2 + * @brief ADC2 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 Parity RAM. + */ +#define adcPARRAM2 ( *( volatile uint32 * ) ( 0xFF3A0000U + 0x1000U ) ) + +/** @def adcLUT1 + * @brief ADC1 Look-Up Table + * + * This pointer is used by the ADC driver to access the ADC1 Look-Up Table. + */ +#define adcLUT1 ( ( adcLUT_t * ) ( 0xFF3E0000U + 0x2000U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h new file mode 100644 index 00000000000..2bb705c66cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h @@ -0,0 +1,230 @@ +/** @file reg_can.h + * @brief CAN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CAN_H__ +#define __REG_CAN_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Can Register Frame Definition */ +/** @struct canBase + * @brief CAN Register Frame Definition + * + * This type is used to access the CAN Registers. + */ +/** @typedef canBASE_t + * @brief CAN Register Frame Type Definition + * + * This type is used to access the CAN Registers. + */ +typedef volatile struct canBase +{ + uint32 CTL; /**< 0x0000: Control Register */ + uint32 ES; /**< 0x0004: Error and Status Register */ + uint32 EERC; /**< 0x0008: Error Counter Register */ + uint32 BTR; /**< 0x000C: Bit Timing Register */ + uint32 INT; /**< 0x0010: Interrupt Register */ + uint32 TEST; /**< 0x0014: Test Register */ + uint32 rsvd1; /**< 0x0018: Reserved */ + uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */ + uint32 rsvd11; /**< 0x0020: Reserved */ + uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */ + uint32 ECCDIAG_STAT; /**< 0x0028: ECC Diagnostic Status Register */ + uint32 ECC_CS; /**< 0x002C: ECC Control and Status Register */ + uint32 ECC_SERR; /**< 0x0030: ECC Single Bit Error code register */ + uint32 rsvd2[ 19 ]; /**< 0x002C - 0x7C: Reserved */ + uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */ + uint32 TXRQX; /**< 0x0084: Transmission Request X Register */ + uint32 TXRQx[ 4U ]; /**< 0x0088-0x0094: Transmission Request Registers */ + uint32 NWDATX; /**< 0x0098: New Data X Register */ + uint32 NWDATx[ 4U ]; /**< 0x009C-0x00A8: New Data Registers */ + uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */ + uint32 INTPNDx[ 4U ]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */ + uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */ + uint32 MSGVALx[ 4U ]; /**< 0x00C4-0x00D0: Message Valid Registers */ + uint32 rsvd3; /**< 0x00D4: Reserved */ + uint32 INTMUXx[ 4U ]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */ + uint32 rsvd4[ 6 ]; /**< 0x00E8: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ +#else + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ +#endif + uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */ + uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */ + uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */ + uint8 IF1DATx[ 8U ]; /**< 0x0110-0x0114: IF1 Data A and B Registers */ + uint32 rsvd5[ 2 ]; /**< 0x0118: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ +#else + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */ +#endif + uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */ + uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */ + uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */ + uint8 IF2DATx[ 8U ]; /**< 0x0130-0x0134: IF2 Data A and B Registers */ + uint32 rsvd6[ 2 ]; /**< 0x0138: Reserved */ + uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */ + uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */ + uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */ + uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */ + uint8 IF3DATx[ 8U ]; /**< 0x0150-0x0154: IF3 Data A and B Registers */ + uint32 rsvd7[ 2 ]; /**< 0x0158: Reserved */ + uint32 IF3UEy[ 4U ]; /**< 0x0160-0x016C: IF3 Update Enable Registers */ + uint32 rsvd8[ 28 ]; /**< 0x0170: Reserved */ + uint32 TIOC; /**< 0x01E0: TX IO Control Register */ + uint32 RIOC; /**< 0x01E4: RX IO Control Register */ +} canBASE_t; + +/** @def canREG1 + * @brief CAN1 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN1 registers. + */ +#define canREG1 ( ( canBASE_t * ) 0xFFF7DC00U ) + +/** @def canREG2 + * @brief CAN2 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN2 registers. + */ +#define canREG2 ( ( canBASE_t * ) 0xFFF7DE00U ) + +/** @def canREG3 + * @brief CAN3 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN3 registers. + */ +#define canREG3 ( ( canBASE_t * ) 0xFFF7E000U ) + +/** @def canREG4 + * @brief CAN4 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN4 registers. + */ +#define canREG4 ( ( canBASE_t * ) 0xFFF7E200U ) + +/** @def canRAM1 + * @brief CAN1 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 RAM. + */ +#define canRAM1 ( *( volatile uint32 * ) 0xFF1E0000U ) + +/** @def canRAM2 + * @brief CAN2 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 RAM. + */ +#define canRAM2 ( *( volatile uint32 * ) 0xFF1C0000U ) + +/** @def canRAM3 + * @brief CAN3 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 RAM. + */ +#define canRAM3 ( *( volatile uint32 * ) 0xFF1A0000U ) + +/** @def canRAM4 + * @brief CAN4 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN4 RAM. + */ +#define canRAM4 ( *( volatile uint32 * ) 0xFF180000U ) + +/** @def canPARRAM1 + * @brief CAN1 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM1 ( *( volatile uint32 * ) ( 0xFF1E0000U + 0x10U ) ) + +/** @def canPARRAM2 + * @brief CAN2 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM2 ( *( volatile uint32 * ) ( 0xFF1C0000U + 0x10U ) ) + +/** @def canPARRAM3 + * @brief CAN3 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM3 ( *( volatile uint32 * ) ( 0xFF1A0000U + 0x10U ) ) + +/** @def canPARRAM4 + * @brief CAN4 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN4 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM4 ( *( volatile uint32 * ) ( 0xFF180000U + 0x10U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h new file mode 100644 index 00000000000..6a7b66a4ab5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h @@ -0,0 +1,84 @@ +/** @file reg_ccmr5.h + * @brief CCMR5 Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CCMR5_H__ +#define __REG_CCMR5_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ +/** @struct ccmr5Base + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ +/** @typedef ccmr5BASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct ccmr5Base +{ + uint32 CCMSR1; /* 0x00 Status Register 1 */ + uint32 CCMKEYR1; /* 0x04 Key Register 1 */ + uint32 CCMSR2; /* 0x08 Status Register 2 */ + uint32 CCMKEYR2; /* 0x0C Key Register 2 */ + uint32 CCMSR3; /* 0x10 Status Register 3 */ + uint32 CCMKEYR3; /* 0x14 Key Register 3 */ + uint32 CCMPOLCNTRL; /* 0x18 Polarity Control Register */ + uint32 CCMSR4; /* 0x1C Status Register 4 */ + uint32 CCMKEYR4; /* 0x20 Key Register 4 */ + uint32 CCMPDSTAT0; /* 0x24 Power Domain Status Register 0 */ +} ccmr5BASE_t; + +#define ccmr5REG ( ( ccmr5BASE_t * ) 0xFFFFF600U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h new file mode 100644 index 00000000000..fe70e50d066 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h @@ -0,0 +1,132 @@ +/** @file reg_crc.h + * @brief CRC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CRC_H__ +#define __REG_CRC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Crc Register Frame Definition */ +/** @struct crcBase + * @brief CRC Register Frame Definition + * + * This type is used to access the CRC Registers. + */ +/** @typedef crcBASE_t + * @brief CRC Register Frame Type Definition + * + * This type is used to access the CRC Registers. + */ +typedef volatile struct crcBase +{ + uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/ + uint32 rvd1; /**< 0x0004: reserved >**/ + uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/ + uint32 rvd2; /**< 0x000C: reserved >**/ + uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/ + uint32 rvd3; /**< 0x0014: reserved >**/ + uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/ + uint32 rvd4; /**< 0x001C: reserved >**/ + uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/ + uint32 rvd5; /**< 0x0024: reserved >**/ + uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/ + uint32 rvd6; /**< 0x002C: reserved >**/ + uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/ + uint32 rvd7; /**< 0x0034: reserved >**/ + uint32 BUSY; /**< 0x0038: CRC Busy Register >**/ + uint32 rvd8; /**< 0x003C: reserved >**/ + uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/ + uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/ + uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/ + uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/ + uint32 rvd9[ 3 ]; /**< 0x0054: reserved >**/ + uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/ + uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/ + uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/ + uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/ + uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/ + uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/ + uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/ + uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/ + uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/ + uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/ + uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/ + uint32 rvd10[ 3 ]; /**< 0x0094: reserved >**/ + uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/ + uint32 PSA_SIGREGH2; /**< 0x00A4: Channel 2 PSA signature high register >**/ + uint32 REGL2; /**< 0x00A8: Channel 2 CRC value low register >**/ + uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/ + uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/ + uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/ + uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/ +} crcBASE_t; + +/** @def crcREG1 + * @brief CRC1 Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC1 registers. + */ +#define crcREG1 ( ( crcBASE_t * ) 0xFE000000U ) + +/** @def crcREG2 + * @brief CRC2 Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC2 registers. + */ +#define crcREG2 ( ( crcBASE_t * ) 0xFB000000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h new file mode 100644 index 00000000000..f60eefcd29b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h @@ -0,0 +1,99 @@ +/** @file reg_dcc.h + * @brief DCC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DCC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DCC_H__ +#define __REG_DCC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dcc Register Frame Definition */ +/** @struct dccBase + * @brief DCC Base Register Definition + * + * This structure is used to access the DCC module registers. + */ +/** @typedef dccBASE_t + * @brief DCC Register Frame Type Definition + * + * This type is used to access the DCC Registers. + */ +typedef volatile struct dccBase +{ + uint32 GCTRL; /**< 0x0000: DCC Control Register */ + uint32 REV; /**< 0x0004: DCC Revision Id Register */ + uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */ + uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */ + uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */ + uint32 STAT; /**< 0x0014: DCC Status Register */ + uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */ + uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */ + uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */ + uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */ + uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */ +} dccBASE_t; + +/** @def dccREG1 + * @brief DCC1 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U ) + +/** @def dccREG2 + * @brief DCC2 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG2 ( ( dccBASE_t * ) 0xFFFFF400U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h new file mode 100644 index 00000000000..f0aa785319e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h @@ -0,0 +1,242 @@ +/** @file reg_dma.h + * @brief DMA Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMA_H__ +#define __REG_DMA_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DMA Register Frame Definition */ +/** @struct dmaBase + * @brief DMA Register Frame Definition + * + * This type is used to access the DMA Registers. + */ +/** @struct dmaBASE_t + * @brief DMA Register Definition + * + * This structure is used to access the DMA module egisters. + */ +typedef volatile struct dmaBase +{ + uint32 GCTRL; /**< 0x0000: Global Control Register */ + uint32 PEND; /**< 0x0004: Channel Pending Register */ + uint32 FBREG; /**< 0x0008: Fall Back Register */ + uint32 DMASTAT; /**< 0x000C: Status Register */ + uint32 rsvd1; /**< 0x0010: Reserved */ + uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */ + uint32 rsvd2; /**< 0x0018: Reserved */ + uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */ + uint32 rsvd3; /**< 0x0020: Reserved */ + uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */ + uint32 rsvd4; /**< 0x0028: Reserved */ + uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */ + uint32 rsvd5; /**< 0x0030: Reserved */ + uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */ + uint32 rsvd6; /**< 0x0038: Reserved */ + uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */ + uint32 rsvd7; /**< 0x0040: Reserved */ + uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */ + uint32 rsvd8; /**< 0x0048: Reserved */ + uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Reset */ + uint32 rsvd9; /**< 0x0050: Reserved */ + uint32 DREQASI[ 8U ]; /**< 0x0054 - 0x70: DMA Request Assignment Register */ + uint32 rsvd10[ 8U ]; /**< 0x0074 - 0x90: Reserved */ + uint32 PAR[ 4U ]; /**< 0x0094 - 0xA0: Port Assignment Register */ + uint32 rsvd11[ 4U ]; /**< 0x00A4 - 0xB0: Reserved */ + uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */ + uint32 rsvd12; /**< 0x00B8: Reserved */ + uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */ + uint32 rsvd13; /**< 0x00C0: Reserved */ + uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */ + uint32 rsvd14; /**< 0x00C8: Reserved */ + uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */ + uint32 rsvd15; /**< 0x00D0: Reserved */ + uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */ + uint32 rsvd16; /**< 0x00D8: Reserved */ + uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */ + uint32 rsvd17; /**< 0x00E0: Reserved */ + uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */ + uint32 rsvd18; /**< 0x00E8: Reserved */ + uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */ + uint32 rsvd19; /**< 0x00F0: Reserved */ + uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */ + uint32 rsvd20; /**< 0x00F8: Reserved */ + uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */ + uint32 rsvd21; /**< 0x0100: Reserved */ + uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */ + uint32 rsvd22; /**< 0x0108: Reserved */ + uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */ + uint32 rsvd23; /**< 0x0110: Reserved */ + uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */ + uint32 rsvd24; /**< 0x0118: Reserved */ + uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */ + uint32 rsvd25; /**< 0x0120: Reserved */ + uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */ + uint32 rsvd26; /**< 0x0128: Reserved */ + uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */ + uint32 rsvd27; /**< 0x0130: Reserved */ + uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */ + uint32 rsvd28; /**< 0x0138: Reserved */ + uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */ + uint32 rsvd29; /**< 0x0140: Reserved */ + uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */ + uint32 rsvd30; /**< 0x0148: Reserved */ + uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */ + uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */ + uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */ + uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */ + uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */ + uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */ + uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */ + uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */ + uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */ + uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */ + uint32 rsvd31; /**< 0x0174: Reserved */ + uint32 PTCRL; /**< 0x0178: Port Control Register */ + uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */ + uint32 DCTRL; /**< 0x0180: Debug Control */ + uint32 WPR; /**< 0x0184: Watch Point Register */ + uint32 WMR; /**< 0x0188: Watch Mask Register */ + uint32 FAACSADDR; /**< 0x018C: */ + uint32 FAACDADDR; /**< 0x0190: */ + uint32 FAACTC; /**< 0x0194: */ + uint32 FBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */ + uint32 FBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */ + uint32 FBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */ + uint32 rsvd32; /**< 0x01A4: Reserved */ + uint32 DMAPCR; /**< 0x01A8: Parity Control Register */ + uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */ + uint32 DMAMPCTRL1; /**< 0x01B0: DMA Memory Protection Control Register */ + uint32 DMAMPST1; /**< 0x01B4: DMA Memory Protection Status Register */ + + struct + { + uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + } DMAMPR_L[ 4U ]; + + uint32 DMAMPCTRL2; /**< 0x01D8: Memory Protection Control Register */ + uint32 DMAPST2; /**< 0x01DC: Memory Protection Status Register */ + + struct + { + uint32 STARTADD; /**< 0x01E0, 0x01E8, 0x01F0, 0x01F8: DMA Memory Protection + Region Start Address Register */ + uint32 ENDADD; /**< 0x01E4, 0x01EC, 0x01F4, 0x01FC: DMA Memory Protection Region + Start Address Register */ + } DMAMPR_H[ 4U ]; + + uint32 rsvd33[ 10U ]; /**< 0x0200 - 0x224: Reserved */ + uint32 DMASECCCTRL; /**< 0x0228: DMA Single bit ECC Control RegisteR */ + uint32 rsvd34; /**< 0x022C: Reserved */ + uint32 DMAECCSBE; /**< 0x0230: DMA ECC Single bit Error Address Register */ + uint32 rsvd35[ 3U ]; /**< 0x0234 - 0x023C: Reserved */ + uint32 FIFOASTATREG; /**< 0x0240: FIFO A Status Register */ + uint32 FIFOBSTATREG; /**< 0x0244: FIFO B Status Register */ + uint32 rsvd37[ 58U ]; /**< 0x0248 - 0x032C: Reserved */ + uint32 DMAREQPS1; /**< 0x0330: DMA Request Polarity Select Register 1 */ + uint32 DMAREQPS0; /**< 0x0334: DMA Request Polarity Select Register 0 */ + uint32 rsvd38[ 32 ]; /**< 0x0338 - 0x033C: Reserved */ + uint32 TERECTRL; /**< 0x0340: TER Event Control Register */ + uint32 TERFLAG; /**< 0x0344: TER Event Flag Register */ + uint32 TERROFFSET; /**< 0x0348: TER Event Channel Offset Register */ +} dmaBASE_t; + +typedef volatile struct +{ + struct /* 0x000-0x400 */ + { + uint32 ISADDR; + uint32 IDADDR; + uint32 ITCOUNT; + uint32 rsvd1; + uint32 CHCTRL; + uint32 EIOFF; + uint32 FIOFF; + uint32 rsvd2; + } PCP[ 32U ]; + + struct /* 0x400-0x800 */ + { + uint32 res[ 256U ]; + } RESERVED; + + struct /* 0x800-0xA00 */ + { + uint32 CSADDR; + uint32 CDADDR; + uint32 CTCOUNT; + uint32 rsvd3; + } WCP[ 32U ]; + +} dmaRAMBASE_t; + +#define dmaRAMREG ( ( dmaRAMBASE_t * ) 0xFFF80000U ) + +/** @def dmaREG + * @brief DMA1 Register Frame Pointer + * + * This pointer is used by the DMA driver to access the DMA module registers. + */ +#define dmaREG ( ( dmaBASE_t * ) 0xFFFFF000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* REG_DMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h new file mode 100644 index 00000000000..b53fab6355d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h @@ -0,0 +1,127 @@ +/** @file reg_dmm.h + * @brief DMM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DMM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMM_H__ +#define __REG_DMM_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dmm Register Frame Definition */ +/** @struct dmmBase + * @brief DMM Base Register Definition + * + * This structure is used to access the DMM module registers. + */ +/** @typedef dmmBASE_t + * @brief DMM Register Frame Type Definition + * + * This type is used to access the DMM Registers. + */ + +typedef volatile struct dmmBase +{ + uint32 GLBCTRL; /**< 0x0000: Global control register 0 */ + uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */ + uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */ + uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */ + uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */ + uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */ + uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */ + uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */ + uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */ + uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */ + uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */ + uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */ + uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */ + uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */ + uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */ + uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */ + uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */ + uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */ + uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */ + uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */ + uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */ + uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */ + uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */ + uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */ + uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */ + uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */ + uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */ + uint32 PC0; /**< 0x006C: DMM Pin Control 0 */ + uint32 PC1; /**< 0x0070: DMM Pin Control 1 */ + uint32 PC2; /**< 0x0074: DMM Pin Control 2 */ + uint32 PC3; /**< 0x0078: DMM Pin Control 3 */ + uint32 PC4; /**< 0x007C: DMM Pin Control 4 */ + uint32 PC5; /**< 0x0080: DMM Pin Control 5 */ + uint32 PC6; /**< 0x0084: DMM Pin Control 6 */ + uint32 PC7; /**< 0x0088: DMM Pin Control 7 */ + uint32 PC8; /**< 0x008C: DMM Pin Control 8 */ +} dmmBASE_t; + +/** @def dmmREG + * @brief DMM Register Frame Pointer + * + * This pointer is used by the DMM driver to access the DMM module registers. + */ +#define dmmREG ( ( dmmBASE_t * ) 0xFFFFF700U ) + +/** @def dmmPORT + * @brief DMM Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of DMM + * (use the GIO drivers to access the port pins). + */ +#define dmmPORT ( ( gioPORT_t * ) 0xFFFFF770U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h new file mode 100644 index 00000000000..962bc197e55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h @@ -0,0 +1,155 @@ +/** @file reg_ecap.h + * @brief ECAP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ECAP_H__ +#define __REG_ECAP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Ecap Register Frame Definition */ +/** @struct ecapBASE + * @brief ECAP Register Frame Definition + * + * This type is used to access the ECAP Registers. + */ +/** @typedef ecapBASE_t + * @brief ECAP Register Frame Type Definition + * + * This type is used to access the ECAP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ + +} ecapBASE_t; + +#else + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ + +} ecapBASE_t; + +#endif +/** @def ecapREG1 + * @brief ECAP1 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP1 registers. + */ +#define ecapREG1 ( ( ecapBASE_t * ) 0xFCF79300U ) + +/** @def ecapREG2 + * @brief ECAP2 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP2 registers. + */ +#define ecapREG2 ( ( ecapBASE_t * ) 0xFCF79400U ) + +/** @def ecapREG3 + * @brief ECAP3 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP3 registers. + */ +#define ecapREG3 ( ( ecapBASE_t * ) 0xFCF79500U ) + +/** @def ecapREG4 + * @brief ECAP4 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP4 registers. + */ +#define ecapREG4 ( ( ecapBASE_t * ) 0xFCF79600U ) + +/** @def ecapREG5 + * @brief ECAP5 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP5 registers. + */ +#define ecapREG5 ( ( ecapBASE_t * ) 0xFCF79700U ) + +/** @def ecapREG6 + * @brief ECAP6 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP6 registers. + */ +#define ecapREG6 ( ( ecapBASE_t * ) 0xFCF79800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h new file mode 100644 index 00000000000..f00eb93b75c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h @@ -0,0 +1,94 @@ +/** @file reg_efc.h + * @brief EFC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EFC_H__ +#define __REG_EFC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ +/** @struct efcBase + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ +/** @typedef efcBASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct efcBase +{ + uint32 rsvd1; /* 0x00 RESERVED */ + uint32 rsvd2; /* 0x04 RESERVED */ + uint32 rsvd3; /* 0x08 RESERVED */ + uint32 rsvd4; /* 0x0C RESERVED */ + uint32 rsvd5; /* 0x10 RESERVED */ + uint32 rsvd6; /* 0x14 RESERVED */ + uint32 rsvd7; /* 0x18 RESERVED */ + uint32 BOUND; /* 0x1C RESERVED */ + uint32 rsvd8; /* 0x20 RESERVED */ + uint32 rsvd9; /* 0x24 RESERVED */ + uint32 rsvd10; /* 0x28 RESERVED */ + uint32 PINS; /* 0x2C RESERVED */ + uint32 rsvd11; /* 0x30 RESERVED */ + uint32 rsvd12; /* 0x34 RESERVED */ + uint32 rsvd13; /* 0x38 RESERVED */ + uint32 ERR_STAT; /* 0x3C RESERVED */ + uint32 rsvd14; /* 0x40 RESERVED */ + uint32 rsvd15; /* 0x44 RESERVED */ + uint32 ST_CY; /* 0x48 RESERVED */ + uint32 ST_SIG; /* 0x4C RESERVED */ +} efcBASE_t; + +#define efcREG ( ( efcBASE_t * ) 0xFFF8C000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h new file mode 100644 index 00000000000..513ff89e67b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h @@ -0,0 +1,97 @@ +/** @file reg_emif.h + * @brief EMIF Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EMIF driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EMIF_H__ +#define __REG_EMIF_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Emif Register Frame Definition */ +/** @struct emifBASE_t + * @brief emifBASE Register Definition + * + * This structure is used to access the EMIF module registers. + */ +typedef volatile struct emifBase +{ + uint32 MIDR; /**< 0x0000 Module ID Register */ + uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/ + uint32 SDCR; /**< 0x0008 SDRAM configuration register */ + uint32 SDRCR; /**< 0x000C Set Interrupt Enable Register */ + uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */ + uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */ + uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */ + uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */ + uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */ + uint32 dummy1[ 6 ]; /** reserved **/ + uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */ + uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/ + uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */ + uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */ + uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */ + uint32 dummy2[ 6 ]; /** reserved **/ + uint32 PMCR; /**< 0x0068 Page Mode Control Register*/ + +} emifBASE_t; + +#define emifREG ( ( emifBASE_t * ) 0xFCFFE800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h new file mode 100644 index 00000000000..6c2612b51a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h @@ -0,0 +1,97 @@ +/** @file reg_epc.h + * @brief EPC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the EPC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EPC_H__ +#define __REG_EPC_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* EPC Register Frame Definition */ +/** @struct epcBase + * @brief EPC Base Register Definition + * + * This structure is used to access the EPC module registers. + */ +/** @typedef epcBASE_t + * @brief EPC Register Frame Type Definition + * + * This type is used to access the EPC Registers. + */ +typedef volatile struct epcBase +{ + uint32 EPCREVID; /**< 0x0000: EPC REVID Register */ + uint32 EPCCNTRL; /**< 0x0004: EPC Control Register */ + uint32 UERRSTAT; /**< 0x0008: Uncorrectable Error Status Register */ + uint32 EPCERRSTAT; /**< 0x000C: EPC Error Status Register */ + uint32 FIFOFULLSTAT; /**< 0x0010: FIFO Full Status Register */ + uint32 OVRFLWSTAT; /**< 0x0014: IP Interface FIFO Overflow Status Register */ + uint32 CAMAVAILSTAT; /**< 0x0018: CAM Index Available Status Register */ + uint32 rsvd1; /**< 0x001C: Reserved */ + uint32 UERRADDR[ 2 ]; /**< 0x0020 - 0x0024: Uncorrectable Error Address Registers */ + uint32 rsvd2[ 30 ]; /**< 0x0028 - 0x009C: Reserved */ + uint32 CAM_CONTENT[ 32 ]; /**< 0x00A0 - 0x011C: CAM Content Update Registers */ + uint32 rsvd3[ 56 ]; /**< 0x0120 - 0x01FC: Reserved */ + uint32 CAM_INDEX[ 8 ]; /**< 0x0200 - 0x021C: CAM Index Register 0 to 7 */ +} epcBASE_t; + +#define epcREG1 ( ( epcBASE_t * ) 0xFFFF0C00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h new file mode 100644 index 00000000000..26c50fe56f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h @@ -0,0 +1,148 @@ +/** @file reg_eqep.h + * @brief EQEP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EQEP_H__ +#define __REG_EQEP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Eqep Register Frame Definition */ +/** @struct eqepBASE + * @brief EQEP Register Frame Definition + * + * This type is used to access the EQEP Registers. + */ +/** @typedef eqepBASE_t + * @brief EQEP Register Frame Type Definition + * + * This type is used to access the EQEP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ +} eqepBASE_t; + +#else + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ +} eqepBASE_t; + +#endif + +/** @def eqepREG1 + * @brief eQEP1 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP1 registers. + */ +#define eqepREG1 ( ( eqepBASE_t * ) 0xFCF79900U ) + +/** @def eqepREG2 + * @brief eQEP2 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP2 registers. + */ +#define eqepREG2 ( ( eqepBASE_t * ) 0xFCF79A00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h new file mode 100644 index 00000000000..d5bef12ecd2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h @@ -0,0 +1,110 @@ +/** @file reg_esm.h + * @brief ESM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ESM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ESM_H__ +#define __REG_ESM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Esm Register Frame Definition */ +/** @struct esmBase + * @brief Esm Register Frame Definition + * + * This type is used to access the Esm Registers. + */ +/** @typedef esmBASE_t + * @brief Esm Register Frame Type Definition + * + * This type is used to access the Esm Registers. + */ +typedef volatile struct esmBase +{ + uint32 EEPAPR1; /* 0x0000 */ + uint32 DEPAPR1; /* 0x0004 */ + uint32 IESR1; /* 0x0008 */ + uint32 IECR1; /* 0x000C */ + uint32 ILSR1; /* 0x0010 */ + uint32 ILCR1; /* 0x0014 */ + uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */ + uint32 EPSR; /* 0x0024 */ + uint32 IOFFHR; /* 0x0028 */ + uint32 IOFFLR; /* 0x002C */ + uint32 LTCR; /* 0x0030 */ + uint32 LTCPR; /* 0x0034 */ + uint32 EKR; /* 0x0038 */ + uint32 SSR2; /* 0x003C */ + uint32 IEPSR4; /* 0x0040 */ + uint32 IEPCR4; /* 0x0044 */ + uint32 IESR4; /* 0x0048 */ + uint32 IECR4; /* 0x004C */ + uint32 ILSR4; /* 0x0050 */ + uint32 ILCR4; /* 0x0054 */ + uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */ + uint32 rsvd1[ 7U ]; /* 0x0064 - 0x007C */ + uint32 IEPSR7; /* 0x0080 */ + uint32 IEPCR7; /* 0x0084 */ + uint32 IESR7; /* 0x0088 */ + uint32 IECR7; /* 0x008C */ + uint32 ILSR7; /* 0x0090 */ + uint32 ILCR7; /* 0x0094 */ + uint32 SR7[ 3U ]; /* 0x0098, 0x009C, 0x00A0 */ +} esmBASE_t; + +/** @def esmREG + * @brief Esm Register Frame Pointer + * + * This pointer is used by the Esm driver to access the Esm registers. + */ +#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h new file mode 100644 index 00000000000..07d6382ab29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h @@ -0,0 +1,219 @@ +/** @file reg_etpwm.h + * @brief ETPWM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ETPWM_H__ +#define __REG_ETPWM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ETPWM Register Frame Definition */ +/** @struct etpwmBASE + * @brief ETPWM Register Frame Definition + * + * This type is used to access the ETPWM Registers. + */ +/** @typedef etpwmBASE_t + * @brief ETPWM Register Frame Type Definition + * + * This type is used to access the ETPWM Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct etpwmBASE +{ + uint16 TBCTL; /**< 0x0000 Time-Base Control Register*/ + uint16 TBSTS; /**< 0x0002 Time-Base Status Register*/ + uint16 rsvd1; /**< 0x0004 Reserved*/ + uint16 TBPHS; /**< 0x0006 Time-Base Phase Register*/ + uint16 TBCTR; /**< 0x0008 Time-Base Counter Register*/ + uint16 TBPRD; /**< 0x000A Time-Base Period Register*/ + uint16 rsvd2; /**< 0x000C Reserved*/ + uint16 CMPCTL; /**< 0x000E Counter-Compare Control Register*/ + uint16 rsvd3; /**< 0x0010 Reserved*/ + uint16 CMPA; /**< 0x0012 Counter-Compare A Register*/ + uint16 CMPB; /**< 0x0014 Counter-Compare B Register*/ + uint16 AQCTLA; /**< 0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 AQCTLB; /**< 0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 AQSFRC; /**< 0x001A Action-Qualifier Software Force Register*/ + uint16 AQCSFRC; /**< 0x001C Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBCTL; /**< 0x001E Dead-Band Generator Control Register*/ + uint16 DBRED; /**< 0x0020 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 DBFED; /**< 0x0022 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 TZSEL; /**< 0x0024 Trip-Zone Select Register*/ + uint16 TZDCSEL; /**< 0x0026 Trip Zone Digital Compare Select Register*/ + uint16 TZCTL; /**< 0x0028 Trip-Zone Control Register*/ + uint16 TZEINT; /**< 0x002A Trip-Zone Enable Interrupt Register*/ + uint16 TZFLG; /**< 0x002C Trip-Zone Flag Register*/ + uint16 TZCLR; /**< 0x002E Trip-Zone Clear Register*/ + uint16 TZFRC; /**< 0x0030 Trip-Zone Force Register*/ + uint16 ETSEL; /**< 0x0032 Event-Trigger Selection Register*/ + uint16 ETPS; /**< 0x0034 Event-Trigger Pre-Scale Register*/ + uint16 ETFLG; /**< 0x0036 Event-Trigger Flag Register*/ + uint16 ETCLR; /**< 0x0038 Event-Trigger Clear Register*/ + uint16 ETFRC; /**< 0x003A Event-Trigger Force Register*/ + uint16 PCCTL; /**< 0x003C PWM-Chopper Control Register*/ + uint16 rsvd4; /**< 0x003E Reserved*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCTRIPSEL; /**< 0x0060 Digital Compare Trip Select Register*/ + uint16 DCACTL; /**< 0x0062 Digital Compare A Control Register*/ + uint16 DCBCTL; /**< 0x0064 Digital Compare B Control Register*/ + uint16 DCFCTL; /**< 0x0066 Digital Compare Filter Control Register*/ + uint16 DCCAPCTL; /**< 0x0068 Digital Compare Capture Control Register*/ + uint16 DCFOFFSET; /**< 0x006A Digital Compare Filter Offset Register*/ + uint16 DCFOFFSETCNT; /**< 0x006C Digital Compare Filter Offset Counter Register*/ + uint16 DCFWINDOW; /**< 0x006E Digital Compare Filter Window Register*/ + uint16 DCFWINDOWCNT; /**< 0x0070 Digital Compare Filter Window Counter Register*/ + uint16 DCCAP; /**< 0x0072 Digital Compare Counter Capture Register*/ +} etpwmBASE_t; + +#else + +typedef volatile struct etpwmBASE +{ + uint16 TBSTS; /**< 0x0000 Time-Base Status Register*/ + uint16 TBCTL; /**< 0x0002 Time-Base Control Register*/ + uint16 TBPHS; /**< 0x0004 Time-Base Phase Register*/ + uint16 rsvd1; /**< 0x0006 Reserved*/ + uint16 TBPRD; /**< 0x0008 Time-Base Period Register*/ + uint16 TBCTR; /**< 0x000A Time-Base Counter Register*/ + uint16 CMPCTL; /**< 0x000C Counter-Compare Control Register*/ + uint16 rsvd2; /**< 0x000E Reserved*/ + uint16 CMPA; /**< 0x0010 Counter-Compare A Register*/ + uint16 rsvd3; /**< 0x0012 Reserved*/ + uint16 AQCTLA; /**< 0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 CMPB; /**< 0x0016 Counter-Compare B Register*/ + uint16 AQSFRC; /**< 0x0018 Action-Qualifier Software Force Register*/ + uint16 AQCTLB; /**< 0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 DBCTL; /**< 0x001C Dead-Band Generator Control Register*/ + uint16 AQCSFRC; /**< 0x001E Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBFED; /**< 0x0020 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 DBRED; /**< 0x0022 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 TZDCSEL; /**< 0x0024 Trip Zone Digital Compare Select Register*/ + uint16 TZSEL; /**< 0x0026 Trip-Zone Select Register*/ + uint16 TZEINT; /**< 0x0028 Trip-Zone Enable Interrupt Register*/ + uint16 TZCTL; /**< 0x002A Trip-Zone Control Register*/ + uint16 TZCLR; /**< 0x002C Trip-Zone Clear Register*/ + uint16 TZFLG; /**< 0x002E Trip-Zone Flag Register*/ + uint16 ETSEL; /**< 0x0030 Event-Trigger Selection Register*/ + uint16 TZFRC; /**< 0x0032 Trip-Zone Force Register*/ + uint16 ETFLG; /**< 0x0034 Event-Trigger Flag Register*/ + uint16 ETPS; /**< 0x0036 Event-Trigger Pre-Scale Register*/ + uint16 ETFRC; /**< 0x0038 Event-Trigger Force Register*/ + uint16 ETCLR; /**< 0x003A Event-Trigger Clear Register*/ + uint16 rsvd4; /**< 0x003C Reserved*/ + uint16 PCCTL; /**< 0x003E PWM-Chopper Control Register*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCACTL; /**< 0x0060 Digital Compare A Control Register*/ + uint16 DCTRIPSEL; /**< 0x0062 Digital Compare Trip Select Register*/ + uint16 DCFCTL; /**< 0x0064 Digital Compare Filter Control Register*/ + uint16 DCBCTL; /**< 0x0066 Digital Compare B Control Register*/ + uint16 DCFOFFSET; /**< 0x0068 Digital Compare Filter Offset Register*/ + uint16 DCCAPCTL; /**< 0x006A Digital Compare Capture Control Register*/ + uint16 DCFWINDOW; /**< 0x006C Digital Compare Filter Window Register*/ + uint16 DCFOFFSETCNT; /**< 0x006E Digital Compare Filter Offset Counter Register*/ + uint16 DCCAP; /**< 0x0070 Digital Compare Counter Capture Register*/ + uint16 DCFWINDOWCNT; /**< 0x0072 Digital Compare Filter Window Counter Register*/ +} etpwmBASE_t; + +#endif + +/** @def etpwmREG1 + * @brief ETPWM1 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM1 registers. + */ +#define etpwmREG1 ( ( etpwmBASE_t * ) 0xFCF78C00U ) + +/** @def etpwmREG2 + * @brief ETPWM2 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM2 registers. + */ +#define etpwmREG2 ( ( etpwmBASE_t * ) 0xFCF78D00U ) + +/** @def etpwmREG3 + * @brief ETPWM3 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM3 registers. + */ +#define etpwmREG3 ( ( etpwmBASE_t * ) 0xFCF78E00U ) + +/** @def etpwmREG4 + * @brief ETPWM4 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM4 registers. + */ +#define etpwmREG4 ( ( etpwmBASE_t * ) 0xFCF78F00U ) + +/** @def etpwmREG5 + * @brief ETPWM5 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM5 registers. + */ +#define etpwmREG5 ( ( etpwmBASE_t * ) 0xFCF79000U ) + +/** @def etpwmREG6 + * @brief ETPWM6 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM6 registers. + */ +#define etpwmREG6 ( ( etpwmBASE_t * ) 0xFCF79100U ) + +/** @def etpwmREG7 + * @brief ETPWM7 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM7 registers. + */ +#define etpwmREG7 ( ( etpwmBASE_t * ) 0xFCF79200U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h new file mode 100644 index 00000000000..262d45c66d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h @@ -0,0 +1,135 @@ +/** @file reg_flash.h + * @brief Flash Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_FLASH_H__ +#define __REG_FLASH_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Flash Register Frame Definition */ +/** @struct flashWBase + * @brief Flash Wrapper Register Frame Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +/** @typedef flashWBASE_t + * @brief Flash Wrapper Register Frame Type Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +typedef volatile struct flashWBase +{ + uint32 FRDCNTL; /* 0x0000 */ + uint32 rsvd1; /* 0x0004 */ + uint32 EE_FEDACCTRL1; /* 0x0008 */ + uint32 rsvd2; /* 0x000C */ + uint32 rsvd3; /* 0x0010 */ + uint32 FEDAC_PASTATUS; /* 0x0014 */ + uint32 FEDAC_PBSTATUS; /* 0x0018 */ + uint32 FEDAC_GBLSTATUS; /* 0x001C */ + uint32 rsvd4; /* 0x0020 */ + uint32 FEDACSDIS; /* 0x0024 */ + uint32 FPRIM_ADD_TAG; /* 0x0028 */ + uint32 FDUP_ADD_TAG; /* 0x002C */ + uint32 FBPROT; /* 0x0030 */ + uint32 FBSE; /* 0x0034 */ + uint32 FBBUSY; /* 0x0038 */ + uint32 FBAC; /* 0x003C */ + uint32 FBPWRMODE; /* 0x0040 */ + uint32 FBPRDY; /* 0x0044 */ + uint32 FPAC1; /* 0x0048 */ + uint32 rsvd5; /* 0x004C */ + uint32 FMAC; /* 0x0050 */ + uint32 FMSTAT; /* 0x0054 */ + uint32 FEMU_DMSW; /* 0x0058 */ + uint32 FEMU_DLSW; /* 0x005C */ + uint32 FEMU_ECC; /* 0x0060 */ + uint32 FLOCK; /* 0x0064 */ + uint32 rsvd6; /* 0x0068 */ + uint32 FDIAGCTRL; /* 0x006C */ + uint32 rsvd7; /* 0x0070 */ + uint32 FRAW_ADDR; /* 0x0074 */ + uint32 rsvd8; /* 0x0078 */ + uint32 FPAR_OVR; /* 0x007C */ + uint32 rsvd9[ 13U ]; /* 0x0080 - 0x00B0 */ + uint32 RCR_VALID; /* 0x00B4 */ + uint32 ACC_THRESHOLD; /* 0x00B8 */ + uint32 rsvd10; /* 0x00BC */ + uint32 FEDACSDIS2; /* 0x00C0 */ + uint32 rsvd11; /* 0x00C4 */ + uint32 rsvd12; /* 0x00C8 */ + uint32 rsvd13; /* 0x00CC */ + uint32 RCR_VALUE0; /* 0x00D0 */ + uint32 RCR_VALUE1; /* 0x00D4 */ + uint32 rsvd14[ 108U ]; /* 0x00D8 - 0x00284 */ + uint32 FSM_WR_ENA; /* 0x0288 */ + uint32 rsvd15[ 11U ]; /* 0x028C - 0x002B4 */ + uint32 EEPROM_CONFIG; /* 0x02B8 */ + uint32 rsvd16; /* 0x02BC */ + uint32 FSM_SECTOR1; /* 0x02C0 */ + uint32 FSM_SECTOR2; /* 0x02C4 */ + uint32 rsvd17[ 78U ]; /* 0x02A8 */ + uint32 FCFG_BANK; /* 0x02B8 */ + +} flashWBASE_t; + +/** @def flashWREG + * @brief Flash Wrapper Register Frame Pointer + * + * This pointer is used by the system driver to access the flash wrapper registers. + */ +#define flashWREG ( ( flashWBASE_t * ) ( 0xFFF87000U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h new file mode 100644 index 00000000000..694b0f4665a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h @@ -0,0 +1,128 @@ +/** @file reg_gio.h + * @brief GIO Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the GIO driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_GIO_H__ +#define __REG_GIO_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Gio Register Frame Definition */ +/** @struct gioBase + * @brief GIO Base Register Definition + * + * This structure is used to access the GIO module registers. + */ +/** @typedef gioBASE_t + * @brief GIO Register Frame Type Definition + * + * This type is used to access the GIO Registers. + */ +typedef volatile struct gioBase +{ + uint32 GCR0; /**< 0x0000: Global Control Register */ + uint32 rsvd; /**< 0x0004: Reserved*/ + uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/ + uint32 POL; /**< 0x000C: Interrupt Polarity Register */ + uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */ + uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */ + uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */ + uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */ + uint32 FLG; /**< 0x0020: Interrupt Flag Register */ + uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */ + uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */ + uint32 EMU1; /**< 0x002C: Emulation 1 Register */ + uint32 EMU2; /**< 0x0030: Emulation 2 Register */ +} gioBASE_t; + +/** @struct gioPort + * @brief GIO Port Register Definition + */ +/** @typedef gioPORT_t + * @brief GIO Port Register Type Definition + * + * This type is used to access the GIO Port Registers. + */ +typedef volatile struct gioPort +{ + uint32 DIR; /**< 0x0000: Data Direction Register */ + uint32 DIN; /**< 0x0004: Data Input Register */ + uint32 DOUT; /**< 0x0008: Data Output Register */ + uint32 DSET; /**< 0x000C: Data Output Set Register */ + uint32 DCLR; /**< 0x0010: Data Output Clear Register */ + uint32 PDR; /**< 0x0014: Open Drain Register */ + uint32 PULDIS; /**< 0x0018: Pullup Disable Register */ + uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */ +} gioPORT_t; + +/** @def gioREG + * @brief GIO Register Frame Pointer + * + * This pointer is used by the GIO driver to access the gio module registers. + */ +#define gioREG ( ( gioBASE_t * ) 0xFFF7BC00U ) + +/** @def gioPORTA + * @brief GIO Port (A) Register Pointer + * + * Pointer used by the GIO driver to access PORTA + */ +#define gioPORTA ( ( gioPORT_t * ) 0xFFF7BC34U ) + +/** @def gioPORTB + * @brief GIO Port (B) Register Pointer + * + * Pointer used by the GIO driver to access PORTB + */ +#define gioPORTB ( ( gioPORT_t * ) 0xFFF7BC54U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h new file mode 100644 index 00000000000..c5de03309e5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h @@ -0,0 +1,187 @@ +/** @file reg_het.h + * @brief HET Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HET driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HET_H__ +#define __REG_HET_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Het Register Frame Definition */ +/** @struct hetBase + * @brief HET Base Register Definition + * + * This structure is used to access the HET module registers. + */ +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +typedef volatile struct hetBase +{ + uint32 GCR; /**< 0x0000: Global control register */ + uint32 PFR; /**< 0x0004: Prescale factor register */ + uint32 ADDR; /**< 0x0008: Current address register */ + uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */ + uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */ + uint32 INTENAS; /**< 0x0014: Interrupt enable set register */ + uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */ + uint32 EXC1; /**< 0x001C: Exception control register 1 */ + uint32 EXC2; /**< 0x0020: Exception control register 2 */ + uint32 PRY; /**< 0x0024: Interrupt priority register */ + uint32 FLG; /**< 0x0028: Interrupt flag register */ + uint32 AND; /**< 0x002C: AND share control register */ + uint32 rsvd1; /**< 0x0030: Reserved */ + uint32 HRSH; /**< 0x0034: High resolution share register */ + uint32 XOR; /**< 0x0038: XOR share register */ + uint32 REQENS; /**< 0x003C: Request enable set register */ + uint32 REQENC; /**< 0x0040: Request enable clear register */ + uint32 REQDS; /**< 0x0044: Request destination select register */ + uint32 rsvd2; /**< 0x0048: Reserved */ + uint32 DIR; /**< 0x004C: Direction register */ + uint32 DIN; /**< 0x0050: Data input register */ + uint32 DOUT; /**< 0x0054: Data output register */ + uint32 DSET; /**< 0x0058: Data output set register */ + uint32 DCLR; /**< 0x005C: Data output clear register */ + uint32 PDR; /**< 0x0060: Open drain register */ + uint32 PULDIS; /**< 0x0064: Pull disable register */ + uint32 PSL; /**< 0x0068: Pull select register */ + uint32 rsvd3; /**< 0x006C: Reserved */ + uint32 rsvd4; /**< 0x0070: Reserved */ + uint32 PCR; /**< 0x0074: Parity control register */ + uint32 PAR; /**< 0x0078: Parity address register */ + uint32 PPR; /**< 0x007C: Parity pin select register */ + uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */ + uint32 SFENA; /**< 0x0084: Suppression filter enable register */ + uint32 rsvd5; /**< 0x0088: Reserved */ + uint32 LBPSEL; /**< 0x008C: Loop back pair select register */ + uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */ + uint32 PINDIS; /**< 0x0094: Pin disable register */ +} hetBASE_t; + +/** @struct hetInstructionBase + * @brief HET Instruction Definition + * + * This structure is used to access the HET RAM. + */ +/** @typedef hetINSTRUCTION_t + * @brief HET Instruction Type Definition + * + * This type is used to access a HET Instruction. + */ +typedef volatile struct hetInstructionBase +{ + uint32 Program; + uint32 Control; + uint32 Data; + uint32 rsvd1; +} hetINSTRUCTION_t; + +/** @struct hetRamBase + * @brief HET RAM Definition + * + * This structure is used to access the HET RAM. + */ +/** @typedef hetRAMBASE_t + * @brief HET RAM Type Definition + * + * This type is used to access the HET RAM. + */ +typedef volatile struct het1RamBase +{ + hetINSTRUCTION_t Instruction[ 160U ]; +} hetRAMBASE_t; + +/** @def hetREG1 + * @brief HET Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG1 ( ( hetBASE_t * ) 0xFFF7B800U ) + +/** @def hetPORT1 + * @brief HET GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET1 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT1 ( ( gioPORT_t * ) 0xFFF7B84CU ) + +/** @def hetREG2 + * @brief HET2 Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG2 ( ( hetBASE_t * ) 0xFFF7B900U ) + +/** @def hetPORT2 + * @brief HET2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET2 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT2 ( ( gioPORT_t * ) 0xFFF7B94CU ) + +#define hetRAM1 ( ( hetRAMBASE_t * ) 0xFF460000U ) + +#define hetRAM2 ( ( hetRAMBASE_t * ) 0xFF440000U ) + +#define NHET1RAMPARLOC ( *( volatile uint32 * ) 0xFF462000U ) +#define NHET1RAMLOC ( *( volatile uint32 * ) 0xFF460000U ) + +#define NHET2RAMPARLOC ( *( volatile uint32 * ) 0xFF442000U ) +#define NHET2RAMLOC ( *( volatile uint32 * ) 0xFF440000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h new file mode 100644 index 00000000000..d5760454f50 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h @@ -0,0 +1,130 @@ +/** @file reg_htu.h + * @brief HTU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HTU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HTU_H__ +#define __REG_HTU_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* htu Register Frame Definition */ +/** @struct htuBase + * @brief HTU Base Register Definition + * + * This structure is used to access the HTU module registers. + */ +/** @typedef htuBASE_t + * @brief HTU Register Frame Type Definition + * + * This type is used to access the HTU Registers. + */ +typedef volatile struct htuBase +{ + uint32 GC; /** 0x00 */ + uint32 CPENA; /** 0x04 */ + uint32 BUSY0; /** 0x08 */ + uint32 BUSY1; /** 0x0C */ + uint32 BUSY2; /** 0x10 */ + uint32 BUSY3; /** 0x14 */ + uint32 ACPE; /** 0x18 */ + uint32 rsvd1; /** 0x1C */ + uint32 RLBECTRL; /** 0x20 */ + uint32 BFINTS; /** 0x24 */ + uint32 BFINTC; /** 0x28 */ + uint32 INTMAP; /** 0x2C */ + uint32 rsvd2; /** 0x30 */ + uint32 INTOFF0; /** 0x34 */ + uint32 INTOFF1; /** 0x38 */ + uint32 BIM; /** 0x3C */ + uint32 RLOSTFL; /** 0x40 */ + uint32 BFINTFL; /** 0x44 */ + uint32 BERINTFL; /** 0x48 */ + uint32 MP1S; /** 0x4C */ + uint32 MP1E; /** 0x50 */ + uint32 DCTRL; /** 0x54 */ + uint32 WPR; /** 0x58 */ + uint32 WMR; /** 0x5C */ + uint32 ID; /** 0x60 */ + uint32 PCR; /** 0x64 */ + uint32 PAR; /** 0x68 */ + uint32 rsvd3; /** 0x6C */ + uint32 MPCS; /** 0x70 */ + uint32 MP0S; /** 0x74 */ + uint32 MP0E; /** 0x78 */ +} htuBASE_t; + +typedef volatile struct htudcp +{ + uint32 IFADDRA; + uint32 IFADDRB; + uint32 IHADDRCT; + uint32 ITCOUNT; +} htudcp_t; + +typedef volatile struct htucdcp +{ + uint32 CFADDRA; + uint32 CFADDRB; + uint32 CFCOUNT; + uint32 rsvd4; +} htucdcp_t; + +#define htuREG1 ( ( htuBASE_t * ) 0xFFF7A400U ) +#define htuREG2 ( ( htuBASE_t * ) 0xFFF7A500U ) + +#define htuDCP1 ( ( htudcp_t * ) 0xFF4E0000U ) +#define htuDCP2 ( ( htudcp_t * ) 0xFF4C0000U ) + +#define htuCDCP1 ( ( htucdcp_t * ) 0xFF4E0100U ) +#define htuCDCP2 ( ( htucdcp_t * ) 0xFF4C0100U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h new file mode 100644 index 00000000000..57331088e93 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h @@ -0,0 +1,136 @@ +/** @file reg_i2c.h + * @brief I2C Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the I2C driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* I2c Register Frame Definition */ +/** @struct i2cBase + * @brief I2C Base Register Definition + * + * This structure is used to access the I2C module registers. + */ +/** @typedef i2cBASE_t + * @brief I2C Register Frame Type Definition + * + * This type is used to access the I2C Registers. + */ +typedef volatile struct i2cBase +{ + uint32 OAR; /**< 0x0000 I2C Own Address register */ + uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */ + uint32 STR; /**< 0x0008 I2C Interrupt Status register */ + uint32 CKL; /**< 0x000C I2C Clock Divider Low register */ + uint32 CKH; /**< 0x0010 I2C Clock Divider High register */ + uint32 CNT; /**< 0x0014 I2C Data Count register */ + uint32 DRR; /**< 0x0018: I2C Data Receive register, */ + uint32 SAR; /**< 0x001C I2C Slave Address register */ + uint32 DXR; /**< 0x0020: I2C Data Transmit register, */ + uint32 MDR; /**< 0x0024 I2C Mode register */ + uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */ + uint32 EMDR; /**< 0x002C I2C Extended Mode register */ + uint32 PSC; /**< 0x0030 I2C Prescaler register */ + uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */ + uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */ + uint32 DMACR; /**< 0x003C I2C DMA Control Register */ + uint32 rsvd7; /**< 0x0040 Reserved */ + uint32 rsvd8; /**< 0x0044 Reserved */ + uint32 PFNC; /**< 0x0048 Pin Function Register */ + uint32 DIR; /**< 0x004C Pin Direction Register */ + uint32 DIN; /**< 0x0050 Pin Data In Register */ + uint32 DOUT; /**< 0x0054 Pin Data Out Register */ + uint32 SET; /**< 0x0058 Pin Data Set Register */ + uint32 CLR; /**< 0x005C Pin Data Clr Register */ + uint32 PDR; /**< 0x0060 Pin Open Drain Output Enable Register */ + uint32 PDIS; /**< 0x0064 Pin Pullup/Pulldown Disable Register */ + uint32 PSEL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */ + uint32 PSRS; /**< 0x006C Pin Slew Rate Select Register */ +} i2cBASE_t; + +/** @def i2cREG1 + * @brief I2C Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C module registers. + */ +#define i2cREG1 ( ( i2cBASE_t * ) 0xFFF7D400U ) + +/** @def i2cREG2 + * @brief I2C2 Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C2 module registers. + */ +#define i2cREG2 ( ( i2cBASE_t * ) 0xFFF7D500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @def i2cPORT1 + * @brief I2C1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C1 + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT1 ( ( gioPORT_t * ) 0xFFF7D44CU ) + +/** @def i2cPORT2 + * @brief I2C2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C2 + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT2 ( ( gioPORT_t * ) 0xFFF7D54CU ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h new file mode 100644 index 00000000000..61966cc2d03 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h @@ -0,0 +1,93 @@ +/** @file reg_l2ramw.h + * @brief L2RAMW Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_L2RAMW_H__ +#define __REG_L2RAMW_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* L2ram Register Frame Definition */ +/** @struct l2ramwBase + * @brief L2RAMW Wrapper Register Frame Definition + * + * This type is used to access the L2RAMW Wrapper Registers. + */ +/** @typedef l2ramwBASE_t + * @brief L2RAMW Wrapper Register Frame Type Definition + * + * This type is used to access the L2RAMW Wrapper Registers. + */ + +typedef volatile struct l2ramwBase +{ + uint32 RAMCTRL; /* 0x0000 */ + uint32 rsvd1[ 3 ]; /* 0x0004 */ + uint32 RAMERRSTATUS; /* 0x0010 */ + uint32 rsvd2[ 4 ]; /* 0x0014 */ + uint32 DIAGDATAVECTOR_H; /* 0x0024 */ + uint32 DIAGDATAVECTOR_L; /* 0x0028 */ + uint32 DIAG_ECC; /* 0x002C */ + uint32 RAMTEST; /* 0x0030 */ + uint32 rsvd3; /* 0x0034 */ + uint32 RAMADDRDECVECT; /* 0x0038 */ + uint32 MEMINITDOMAIN; /* 0x003C */ + uint32 rsvd4; /* 0x0040 */ + uint32 BANKDOMAINMAP0; /* 0x0044 */ + uint32 BANKDOMAINMAP1; /* 0x0048 */ +} l2ramwBASE_t; + +#define l2ramwREG ( ( l2ramwBASE_t * ) ( 0xFFFFF900U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h new file mode 100644 index 00000000000..31681e21ef8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h @@ -0,0 +1,138 @@ +/** @file reg_lin.h + * @brief LIN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the LIN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_LIN_H__ +#define __REG_LIN_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Lin Register Frame Definition */ +/** @struct linBase + * @brief LIN Base Register Definition + * + * This structure is used to access the LIN module registers. + */ +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +typedef volatile struct linBase +{ + uint32 GCR0; /**< 0x0000: Global control register 0 */ + uint32 GCR1; /**< 0x0004: Global control register 1 */ + uint32 GCR2; /**< 0x0008: Global control register 2 */ + uint32 SETINT; /**< 0x000C: Set interrupt enable register */ + uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */ + uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */ + uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */ + uint32 FLR; /**< 0x001C: interrupt flag register */ + uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */ + uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */ + uint32 FORMAT; /**< 0x0028: Format Control Register */ + uint32 BRS; /**< 0x002C: Baud rate selection register */ + uint32 ED; /**< 0x0030: Emulation register */ + uint32 RD; /**< 0x0034: Receive data register */ + uint32 TD; /**< 0x0038: Transmit data register */ + uint32 PIO0; /**< 0x003C: Pin function register */ + uint32 PIO1; /**< 0x0040: Pin direction register */ + uint32 PIO2; /**< 0x0044: Pin data in register */ + uint32 PIO3; /**< 0x0048: Pin data out register */ + uint32 PIO4; /**< 0x004C: Pin data set register */ + uint32 PIO5; /**< 0x0050: Pin data clr register */ + uint32 PIO6; /**< 0x0054: Pin open drain output enable register */ + uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */ + uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */ + uint32 COMP; /**< 0x0060: Compare register */ + uint8 RDx[ 8U ]; /**< 0x0064-0x0068: RX buffer register */ + uint32 MASK; /**< 0x006C: Mask register */ + uint32 ID; /**< 0x0070: Identification Register */ + uint8 TDx[ 8U ]; /**< 0x0074-0x0078: TX buffer register */ + uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */ + uint32 rsvd1[ 4U ]; /**< 0x0080 - 0x8C: Reserved */ + uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */ +} linBASE_t; + +/** @def linREG1 + * @brief LIN1 Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin1 module registers. + */ +#define linREG1 ( ( linBASE_t * ) 0xFFF7E400U ) + +/** @def linPORT1 + * @brief LIN1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN1 + * (use the GIO drivers to access the port pins). + */ +#define linPORT1 ( ( gioPORT_t * ) 0xFFF7E440U ) + +/** @def linREG2 + * @brief LIN2 Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin2 module registers. + */ +#define linREG2 ( ( linBASE_t * ) 0xFFF7E600U ) + +/** @def linPORT2 + * @brief LIN2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN2 + * (use the GIO drivers to access the port pins). + */ +#define linPORT2 ( ( gioPORT_t * ) 0xFFF7E640U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h new file mode 100644 index 00000000000..bb175ba4d0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h @@ -0,0 +1,311 @@ +/** @file reg_mibspi.h + * @brief MIBSPI Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the MIBSPI driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_MIBSPI_H__ +#define __REG_MIBSPI_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Mibspi Register Frame Definition */ +/** @struct mibspiBase + * @brief MIBSPI Register Definition + * + * This structure is used to access the MIBSPI module registers. + */ +/** @typedef mibspiBASE_t + * @brief MIBSPI Register Frame Type Definition + * + * This type is used to access the MIBSPI Registers. + */ +typedef volatile struct mibspiBase +{ + uint32 GCR0; /**< 0x0000: Global Control 0 */ + uint32 GCR1; /**< 0x0004: Global Control 1 */ + uint32 INT0; /**< 0x0008: Interrupt Register */ + uint32 LVL; /**< 0x000C: Interrupt Level */ + uint32 FLG; /**< 0x0010: Interrupt flags */ + uint32 PC0; /**< 0x0014: Function Pin Enable */ + uint32 PC1; /**< 0x0018: Pin Direction */ + uint32 PC2; /**< 0x001C: Pin Input Latch */ + uint32 PC3; /**< 0x0020: Pin Output Latch */ + uint32 PC4; /**< 0x0024: Output Pin Set */ + uint32 PC5; /**< 0x0028: Output Pin Clr */ + uint32 PC6; /**< 0x002C: Open Drain Output Enable */ + uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */ + uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */ + uint32 DAT0; /**< 0x0038: Transmit Data */ + uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ + uint32 BUF; /**< 0x0040: Receive Buffer */ + uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ + uint32 DELAY; /**< 0x0048: Delays */ + uint32 DEF; /**< 0x004C: Default Chip Select */ + uint32 FMT0; /**< 0x0050: Data Format 0 */ + uint32 FMT1; /**< 0x0054: Data Format 1 */ + uint32 FMT2; /**< 0x0058: Data Format 2 */ + uint32 FMT3; /**< 0x005C: Data Format 3 */ + uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ + uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ + uint32 rsvd3; /**< 0x0068: Slew Rate Select */ + uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */ + uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */ + uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */ + uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */ + uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */ + uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */ + uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */ + uint32 rsvd1[ 2U ]; /**< 0x0088: Reserved */ + uint32 TICKCNT; /**< 0x0090: Tick Counter */ + uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */ + uint32 TGCTRL[ 16U ]; /**< 0x0098 - 0x00D4: Transfer Group Control */ + uint32 DMACTRL[ 8U ]; /**< 0x00D8 - 0x00F4: DMA Control */ + uint32 DMACOUNT[ 8U ]; /**< 0x00F8 - 0x0114: DMA Count */ + uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */ + uint32 rsvd2; /**< 0x011C: Reserved */ + uint32 PAR_ECC_CTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control + */ + uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */ + uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */ + uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */ + uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */ + uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ + uint32 EXT_PRESCALE1; /**< 0x0138: SPI Extended Prescale Register 1*/ + uint32 EXT_PRESCALE2; /**< 0x013C: SPI Extended Prescale Register 2*/ + uint32 ECCDIAG_CTRL; /**< 0x0140: ECC Diagnostic Control register*/ + uint32 ECCDIAG_STAT; /**< 0x0144: ECC Diagnostic Status register*/ + uint32 SBERRADDR1; /**< 0x0148: */ + uint8 rsvd4[ 6 ]; /**< 0x014C-0x152: Single Bit Error Address Register - RXRAM*/ + uint32 SBERRADDR0; /**< 0x0152: Single Bit Error Address Register - TXRAM*/ + +} mibspiBASE_t; + +/** @def mibspiREG1 + * @brief MIBSPI1 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG1 ( ( mibspiBASE_t * ) 0xFFF7F400U ) + +/** @def mibspiPORT1 + * @brief MIBSPI1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI1 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U ) + +/** @def mibspiREG2 + * @brief MIBSPI2 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG2 ( ( mibspiBASE_t * ) 0xFFF7F600U ) + +/** @def mibspiPORT2 + * @brief MIBSPI2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI2 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT2 ( ( gioPORT_t * ) 0xFFF7F618U ) + +/** @def mibspiREG3 + * @brief MIBSPI3 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG3 ( ( mibspiBASE_t * ) 0xFFF7F800U ) + +/** @def mibspiPORT3 + * @brief MIBSPI3 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI3 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U ) + +/** @def mibspiREG4 + * @brief MIBSPI4 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG4 ( ( mibspiBASE_t * ) 0xFFF7FA00U ) + +/** @def mibspiPORT4 + * @brief MIBSPI4 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI4 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT4 ( ( gioPORT_t * ) 0xFFF7FA18U ) + +/** @def mibspiREG5 + * @brief MIBSPI5 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG5 ( ( mibspiBASE_t * ) 0xFFF7FC00U ) + +/** @def mibspiPORT5 + * @brief MIBSPI5 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI5 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U ) + +/** @struct mibspiRamBase + * @brief MIBSPI Buffer RAM Definition + * + * This structure is used to access the MIBSPI buffer memory. + */ +/** @typedef mibspiRAM_t + * @brief MIBSPI RAM Type Definition + * + * This type is used to access the MIBSPI RAM. + */ +typedef volatile struct mibspiRamBase +{ + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< tx buffer data */ + uint16 control; /**< tx buffer control */ +#else + uint16 control; /**< tx buffer control */ + uint16 data; /**< tx buffer data */ +#endif + } tx[ 128 ]; + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< rx buffer data */ + uint16 flags; /**< rx buffer flags */ +#else + uint16 flags; /**< rx buffer flags */ + uint16 data; /**< rx buffer data */ +#endif + } rx[ 128 ]; +} mibspiRAM_t; + +/** @def mibspiRAM1 + * @brief MIBSPI1 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM1 ( ( mibspiRAM_t * ) 0xFF0E0000U ) + +/** @def mibspiRAM2 + * @brief MIBSPI2 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM2 ( ( mibspiRAM_t * ) 0xFF080000U ) + +/** @def mibspiRAM3 + * @brief MIBSPI3 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM3 ( ( mibspiRAM_t * ) 0xFF0C0000U ) + +/** @def mibspiRAM4 + * @brief MIBSPI4 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM4 ( ( mibspiRAM_t * ) 0xFF060000U ) + +/** @def mibspiRAM5 + * @brief MIBSPI5 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM5 ( ( mibspiRAM_t * ) 0xFF0A0000U ) + +/** @def mibspiPARRAM1 + * @brief MIBSPI1 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM1 ( *( volatile uint32 * ) ( 0xFF0E0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM2 + * @brief MIBSPI2 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM2 ( *( volatile uint32 * ) ( 0xFF080000U + 0x00000400U ) ) + +/** @def mibspiPARRAM3 + * @brief MIBSPI3 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM3 ( *( volatile uint32 * ) ( 0xFF0C0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM4 + * @brief MIBSPI4 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM4 ( *( volatile uint32 * ) ( 0xFF060000U + 0x00000400U ) ) + +/** @def mibspiPARRAM5 + * @brief MIBSPI5 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM5 ( *( volatile uint32 * ) ( 0xFF0A0000U + 0x00000400U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h new file mode 100644 index 00000000000..6566787f24a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h @@ -0,0 +1,98 @@ +/** @file reg_nmpu.h + * @brief NMPU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_NMPU_H__ +#define __REG_NMPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* NMPU Register Frame Definition */ +/** @struct nmpuBASE_t + * @brief nmpuBASE Register Definition + * + * This structure is used to access the NMPU module registers. + */ +typedef volatile struct nmpuBase +{ + uint32 MPUREV; /**< 0x0000 MPU Revision ID Register */ + uint32 MPULOCK; /**< 0x0004 MPU Lock Register */ + uint32 MPUDIAGCTRL; /**< 0x0008 MPU Diagnostics Control Register */ + uint32 MPUDIAGADDR; /**< 0x000C MPU Diagnostic Address Register */ + uint32 MPUERRSTAT; /**< 0x0010 MPU Error Status Register */ + uint32 MPUERRADDR; /**< 0x0014 MPU Error Address Register */ + uint32 MPUIAM; /**< 0x0018 MPU Input Address Mask Register */ + uint32 rsvd1; /**< 0x001C Reserved */ + uint32 MPUCTRL1; /**< 0x0020 MPU Control Register 1 */ + uint32 MPUCTRL2; /**< 0x0024 MPU Control Register 2 */ + uint32 rsvd2; /**< 0x0028 Reserved */ + uint32 MPUTYPE; /**< 0x002C MPU Type Register */ + uint32 MPUREGBASE; /**< 0x0030 MPU Region Base Address Register */ + uint32 MPUREGSENA; /**< 0x0034 MPU Region Size and Enable Register */ + uint32 MPUREGACR; /**< 0x0038 MPU Region Access Control Register */ + uint32 MPUREGNUM; /**< 0x003C MPU Region Number Register */ +} nmpuBASE_t; + +#define nmpu_emacREG ( ( nmpuBASE_t * ) 0xFCFF1800U ) +#define nmpu_dmaREG ( ( nmpuBASE_t * ) 0xFFFF1A00U ) +#define nmpu_ps_scr_sREG ( ( nmpuBASE_t * ) 0xFFFF1800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h new file mode 100644 index 00000000000..d60aa405008 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h @@ -0,0 +1,96 @@ +/** @file reg_pbist.h + * @brief PBIST Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PBIST_H__ +#define __REG_PBIST_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* PBIST Register Frame Definition */ +/** @struct pbistBase + * @brief PBIST Base Register Definition + * + * This structure is used to access the PBIST module registers. + */ +/** @typedef pbistBASE_t + * @brief PBIST Register Frame Type Definition + * + * This type is used to access the PBIST Registers. + */ +typedef volatile struct pbistBase +{ + uint32 RAMT; /* 0x0160: RAM Configuration Register */ + uint32 DLR; /* 0x0164: Datalogger Register */ + uint32 rsvd1[ 6U ]; /* 0x0168 */ + uint32 PACT; /* 0x0180: PBIST Activate Register */ + uint32 PBISTID; /* 0x0184: PBIST ID Register */ + uint32 OVER; /* 0x0188: Override Register */ + uint32 rsvd2; /* 0x018C */ + uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */ + uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */ + uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */ + uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */ + uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */ + uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */ + uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */ + uint32 rsvd3; /* 0x01AC */ + uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */ + uint32 rsvd4[ 3U ]; /* 0x01B4 */ + uint32 ROM; /* 0x01C0: ROM Mask Register */ + uint32 ALGO; /* 0x01C4: Algorithm Mask Register */ + uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */ + uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */ +} pbistBASE_t; + +#define pbistREG ( ( pbistBASE_t * ) 0xFFFFE560U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h new file mode 100644 index 00000000000..c7454be31f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h @@ -0,0 +1,149 @@ +/** @file reg_pcr.h + * @brief PCR Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PCR_H__ +#define __REG_PCR_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Pcr Register Frame Definition */ +/** @struct pcrBase + * @brief Pcr Register Frame Definition + * + * This type is used to access the Pcr Registers. + */ +/** @typedef pcrBASE_t + * @brief PCR Register Frame Type Definition + * + * This type is used to access the PCR Registers. + */ +typedef volatile struct pcrBase +{ + uint32 PMPROTSET0; /* 0x0000 */ + uint32 PMPROTSET1; /* 0x0004 */ + uint32 rsvd1[ 2U ]; /* 0x0008 */ + uint32 PMPROTCLR0; /* 0x0010 */ + uint32 PMPROTCLR1; /* 0x0014 */ + uint32 rsvd2[ 2U ]; /* 0x0018 */ + uint32 PPROTSET0; /* 0x0020 */ + uint32 PPROTSET1; /* 0x0024 */ + uint32 PPROTSET2; /* 0x0028 */ + uint32 PPROTSET3; /* 0x002C */ + uint32 rsvd3[ 4U ]; /* 0x0030 */ + uint32 PPROTCLR0; /* 0x0040 */ + uint32 PPROTCLR1; /* 0x0044 */ + uint32 PPROTCLR2; /* 0x0048 */ + uint32 PPROTCLR3; /* 0x004C */ + uint32 rsvd4[ 4U ]; /* 0x0050 */ + uint32 PCSPWRDWNSET0; /* 0x0060 */ + uint32 PCSPWRDWNSET1; /* 0x0064 */ + uint32 rsvd5[ 2U ]; /* 0x0068 */ + uint32 PCSPWRDWNCLR0; /* 0x0070 */ + uint32 PCSPWRDWNCLR1; /* 0x0074 */ + uint32 rsvd6[ 2U ]; /* 0x0078 */ + uint32 PSPWRDWNSET0; /* 0x0080 */ + uint32 PSPWRDWNSET1; /* 0x0084 */ + uint32 PSPWRDWNSET2; /* 0x0088 */ + uint32 PSPWRDWNSET3; /* 0x008C */ + uint32 rsvd7[ 4U ]; /* 0x0090 */ + uint32 PSPWRDWNCLR0; /* 0x00A0 */ + uint32 PSPWRDWNCLR1; /* 0x00A4 */ + uint32 PSPWRDWNCLR2; /* 0x00A8 */ + uint32 PSPWRDWNCLR3; /* 0x00AC */ + uint32 rsvd8[ 4U ]; /* 0x00B0 */ + uint32 PDPWRDWNSET; /* 0x00C0 */ + uint32 PDPWRDWNCLR; /* 0x00C4 */ + uint32 rsvd9[ 78U ]; /* 0x00C8 */ + uint32 MSTIDWRENA; /* 0x0200 */ + uint32 MSTIDENA; /* 0x0204 */ + uint32 MSTIDDIAGCTRL; /* 0x0208 */ + uint32 rsvd10[ 61U ]; /* 0x020C */ + struct + { + uint32 PSxMSTID_L; + uint32 PSxMSTID_H; + } PSxMSTID[ 32 ]; /* 0x0300 */ + struct + { + uint32 PPSxMSTID_L; + uint32 PPSxMSTID_H; + } PPSxMSTID[ 8 ]; /* 0x0400 */ + struct + { + uint32 PPSExMSTID_L; + uint32 PPSExMSTID_H; + } PPSExMSTID[ 32 ]; /* 0x0440 */ + uint32 PCSxMSTID[ 32 ]; /* 0x0540 */ + uint32 PPCSxMSTID[ 8 ]; /* 0x05C0 */ +} pcrBASE_t; + +/** @def pcrREG1 + * @brief Pcr1 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr1 registers. + */ +#define pcrREG1 ( ( pcrBASE_t * ) 0xFFFF1000U ) + +/** @def pcrREG2 + * @brief Pcr2 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr2 registers. + */ +#define pcrREG2 ( ( pcrBASE_t * ) 0xFCFF1000U ) + +/** @def pcrREG3 + * @brief Pcr3 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr3 registers. + */ +#define pcrREG3 ( ( pcrBASE_t * ) 0xFFF78000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h new file mode 100644 index 00000000000..e26018aa2ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h @@ -0,0 +1,101 @@ +/** @file reg_pinmux.h + * @brief PINMUX Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PINMUX driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PINMUX_H__ +#define __REG_PINMUX_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @struct pinMuxBase + * @brief PINMUX Register Definition + * + * This structure is used to access the PINMUX module registers. + */ +/** @typedef pinMuxBASE_t + * @brief PINMUX Register Frame Type Definition + * + * This type is used to access the PINMUX Registers. + */ +typedef volatile struct pinMuxBase +{ + uint32 REVISION_REG; /**< 0x00: Revision Register */ + uint32 rsvd1[ 7 ]; /** address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [11]: + * - 0: Read + * - 1: Write + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetDataFault_( void ); + +/** @fn void _coreClearDataFault_(void) + * @brief Clear core data fault status register + */ +void _coreClearDataFault_( void ); + +/** @fn uint32 _coreGetInstructionFault_(void) + * @brief Get core instruction fault status register + * @return The function will return the instruction fault status register value: + * - bit [10,3..0]: + * - 0b00001: Alignment -> address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetInstructionFault_( void ); + +/** @fn void _coreClearInstructionFault_(void) + * @brief Clear core instruction fault status register + */ +void _coreClearInstructionFault_( void ); + +/** @fn uint32 _coreGetDataFaultAddress_(void) + * @brief Get core data fault address register + * @return The function will return the data fault address: + */ +uint32 _coreGetDataFaultAddress_( void ); + +/** @fn void _coreClearDataFaultAddress_(void) + * @brief Clear core data fault address register + */ +void _coreClearDataFaultAddress_( void ); + +/** @fn uint32 _coreGetInstructionFaultAddress_(void) + * @brief Get core instruction fault address register + * @return The function will return the instruction fault address: + */ +uint32 _coreGetInstructionFaultAddress_( void ); + +/** @fn void _coreClearInstructionFaultAddress_(void) + * @brief Clear core instruction fault address register + */ +void _coreClearInstructionFaultAddress_( void ); + +/** @fn uint32 _coreGetAuxiliaryDataFault_(void) + * @brief Get core auxiliary data fault status register + * @return The function will return the auxiliary data fault status register value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryDataFault_( void ); + +/** @fn void _coreClearAuxiliaryDataFault_(void) + * @brief Clear core auxiliary data fault status register + */ +void _coreClearAuxiliaryDataFault_( void ); + +/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void) + * @brief Get core auxiliary instruction fault status register + * @return The function will return the auxiliary instruction fault status register + * value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryInstructionFault_( void ); + +/** @fn void _coreClearAuxiliaryInstructionFault_(void) + * @brief Clear core auxiliary instruction fault status register + */ +void _coreClearAuxiliaryInstructionFault_( void ); + +/** @fn void _disable_IRQ_interrupt_(void) + * @brief Disable IRQ Interrupt mode in CPSR register + * + * This function disables IRQ Interrupt mode in CPSR register. + */ +void _disable_IRQ_interrupt_( void ); + +/** @fn void _enable_IRQ_interrupt_(void) + * @brief Enable IRQ Interrupt mode in CPSR register + * + * This function enables IRQ Interrupt mode in CPSR register. + */ +void _enable_IRQ_interrupt_( void ); + +/** @fn void _enable_interrupt_(void) + * @brief Enable IRQ and FIQ Interrupt mode in CPSR register + * + * This function Enables IRQ and FIQ Interrupt mode in CPSR register. + * User must call this function to enable Interrupts in non-OS environments. + */ +void _enable_interrupt_( void ); + +/** @fn void _esmCcmErrorsClear_(void) + * @brief Clears ESM Error caused due to CCM Errata in RevA Silicon + * + * This function Clears ESM Error caused due to CCM Errata + * in RevA Silicon immediately after powerup. + */ +void _esmCcmErrorsClear_( void ); + +/** @fn void _memInit_(void) + * @brief Initialize RAM + */ +void _memInit_( void ); + +/** @fn void _cacheEnable_(void) + * @brief Initialize RAM + */ +void _cacheEnable_( void ); + +/** @fn void _cacheDisable_(void) + * @brief Enable Cache + */ +void _cacheDisable_( void ); + +/** @fn void _dCacheInvalidate_(void) + * @brief Invalidate DCache. + */ +void _dCacheInvalidate_( void ); + +/** @fn void _iCacheInvalidate_(void) + * @brief Invalidate ICache. + */ +void _iCacheInvalidate_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h new file mode 100644 index 00000000000..79e5348c18e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h @@ -0,0 +1,300 @@ +/** @file sys_dma.h + * @brief DMA Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef DMA_H_ +#define DMA_H_ + +#include "reg_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef enum dmaChannel +{ + DMA_CH0 = 0U, + DMA_CH1, + DMA_CH2, + DMA_CH3, + DMA_CH4, + DMA_CH5, + DMA_CH6, + DMA_CH7, + DMA_CH8, + DMA_CH9, + DMA_CH10, + DMA_CH11, + DMA_CH12, + DMA_CH13, + DMA_CH14, + DMA_CH15, + DMA_CH16, + DMA_CH17, + DMA_CH18, + DMA_CH19, + DMA_CH20, + DMA_CH21, + DMA_CH22, + DMA_CH23, + DMA_CH24, + DMA_CH25, + DMA_CH26, + DMA_CH27, + DMA_CH28, + DMA_CH29, + DMA_CH30, + DMA_CH31 +} dmaChannel_t; + +typedef enum dmaRequest +{ + DMA_REQ0 = 0U, + DMA_REQ1, + DMA_REQ2, + DMA_REQ3, + DMA_REQ4, + DMA_REQ5, + DMA_REQ6, + DMA_REQ7, + DMA_REQ8, + DMA_REQ9, + DMA_REQ10, + DMA_REQ11, + DMA_REQ12, + DMA_REQ13, + DMA_REQ14, + DMA_REQ15, + DMA_REQ16, + DMA_REQ17, + DMA_REQ18, + DMA_REQ19, + DMA_REQ20, + DMA_REQ21, + DMA_REQ22, + DMA_REQ23, + DMA_REQ24, + DMA_REQ25, + DMA_REQ26, + DMA_REQ27, + DMA_REQ28, + DMA_REQ29, + DMA_REQ30, + DMA_REQ31, + DMA_REQ32, + DMA_REQ33, + DMA_REQ34, + DMA_REQ35, + DMA_REQ36, + DMA_REQ37, + DMA_REQ38, + DMA_REQ39, + DMA_REQ40, + DMA_REQ41, + DMA_REQ42, + DMA_REQ43, + DMA_REQ44, + DMA_REQ45, + DMA_REQ46, + DMA_REQ47 +} dmaRequest_t; + +typedef enum dmaTriggerType +{ + DMA_HW, + DMA_SW +} dmaTriggerType_t; + +typedef enum dmaPriorityQueue +{ + LOWPRIORITY, + HIGHPRIORITY +} dmaPriorityQueue_t; + +typedef enum dmaInterrupt +{ + FTC, /**< Frame transfer complete Interrupt */ + LFS, /**< Last frame transfer started Interrupt */ + HBC, /**< First half of block complete Interrupt */ + BTC /**< Block transfer complete Interrupt */ +} dmaInterrupt_t; + +typedef enum dmaIntGroup +{ + DMA_INTA = 0U, /**< Group A Interrupt */ + DMA_INTB = 1U /**< Group B Interrupt (Reserved for Lock-step devices) */ +} dmaIntGroup_t; + +typedef enum dmaMPURegion +{ + DMA_REGION0 = 0U, + DMA_REGION1 = 1U, + DMA_REGION2 = 2U, + DMA_REGION3 = 3U, + DMA_REGION4 = 4U, + DMA_REGION5 = 5U, + DMA_REGION6 = 6U, + DMA_REGION7 = 7U +} dmaMPURegion_t; + +typedef enum dmaRegionAccess +{ + FULLACCESS = 0U, + READONLY = 1U, + WRITEONLY = 2U, + NOACCESS = 3U +} dmaRegionAccess_t; + +typedef enum dmaMPUInt +{ + INTERRUPT_DISABLE = 0U, + INTERRUPTA_ENABLE = 1U, + INTERRUPTB_ENABLE = 3U +} dmaMPUInt_t; + +enum dmaPort +{ + PORTB_READ_PORTB_WRITE = 0x3U, + PORTA_READ_PORTA_WRITE = 0x2U, + PORTA_READ_PORTB_WRITE = 0x1U, + PORTB_READ_PORTA_WRITE = 0x0U +}; + +enum dmaElementSize +{ + ACCESS_8_BIT = 0U, + ACCESS_16_BIT = 1U, + ACCESS_32_BIT = 2U, + ACCESS_64_BIT = 3U +}; + +enum dmaTransferType +{ + FRAME_TRANSFER = 0U, + BLOCK_TRANSFER = 1U +}; + +enum dmaAddressMode +{ + ADDR_FIXED = 0U, + ADDR_INC1 = 1U, + ADDR_OFFSET = 3U +}; + +enum dmaAutoInitMode +{ + AUTOINIT_OFF = 0U, + AUTOINIT_ON = 1U +}; + +typedef struct dmaCTRLPKT +{ + uint32 SADD; /* Initial source address */ + uint32 DADD; /* Initial destination address */ + uint32 CHCTRL; /* Next channel to be triggered + 1 */ + uint32 FRCNT; /* Frame count */ + uint32 ELCNT; /* Element count */ + uint32 ELDOFFSET; /* Element destination offset */ + uint32 ELSOFFSET; /* Element source offset */ + uint32 FRDOFFSET; /* Frame destination offset */ + uint32 FRSOFFSET; /* Frame source offset */ + uint32 PORTASGN; /* DMA port */ + uint32 RDSIZE; /* Read element size */ + uint32 WRSIZE; /* Write element size */ + uint32 TTYPE; /* Trigger type - frame/block */ + uint32 ADDMODERD; /* Addressing mode for source */ + uint32 ADDMODEWR; /* Addressing mode for destination */ + uint32 AUTOINIT; /* Auto-init mode */ +} g_dmaCTRL; + +void dmaEnable( void ); +void dmaDisable( void ); +void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT ); +void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type ); +void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline ); +void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority ); +void dmaEnableInterrupt( dmaChannel_t channel, + dmaInterrupt_t inttype, + dmaIntGroup_t group ); +void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype ); +void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add ); +void dmaEnableRegion( dmaMPURegion_t region, + dmaRegionAccess_t access, + dmaMPUInt_t intenable ); +void dmaDisableRegion( dmaMPURegion_t region ); +void dmaEnableECC( void ); +void dmaDisableECC( void ); + +uint32 dmaGetReq( dmaChannel_t channel ); +boolean dmaIsBusy( void ); +boolean dmaIsChannelActive( dmaChannel_t channel ); +boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype ); + +/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) + * @brief Interrupt callback + * @param[in] inttype Interrupt type + * - FTC + * - LFS + * - HBC + * - BTC + * @param[in] channel channel number 0..15 + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* DMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h new file mode 100644 index 00000000000..312c6265444 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h @@ -0,0 +1,612 @@ +/** @file sys_mpu.h + * @brief System Mpu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Mpu Interface Functions + * . + * which are relevant for the memory protection unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_MPU_H__ +#define __SYS_MPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def mpuREGION1 + * @brief Mpu region 1 + * + * Alias for Mpu region 1 + */ +#define mpuREGION1 0U + +/** @def mpuREGION2 + * @brief Mpu region 2 + * + * Alias for Mpu region 1 + */ +#define mpuREGION2 1U + +/** @def mpuREGION3 + * @brief Mpu region 3 + * + * Alias for Mpu region 3 + */ +#define mpuREGION3 2U + +/** @def mpuREGION4 + * @brief Mpu region 4 + * + * Alias for Mpu region 4 + */ +#define mpuREGION4 3U + +/** @def mpuREGION5 + * @brief Mpu region 5 + * + * Alias for Mpu region 5 + */ +#define mpuREGION5 4U + +/** @def mpuREGION6 + * @brief Mpu region 6 + * + * Alias for Mpu region 6 + */ +#define mpuREGION6 5U + +/** @def mpuREGION7 + * @brief Mpu region 7 + * + * Alias for Mpu region 7 + */ +#define mpuREGION7 6U + +/** @def mpuREGION8 + * @brief Mpu region 8 + * + * Alias for Mpu region 8 + */ +#define mpuREGION8 7U + +/** @def mpuREGION9 + * @brief Mpu region 9 + * + * Alias for Mpu region 9 + */ +#define mpuREGION9 8U + +/** @def mpuREGION10 + * @brief Mpu region 10 + * + * Alias for Mpu region 10 + */ +#define mpuREGION10 9U + +/** @def mpuREGION11 + * @brief Mpu region 11 + * + * Alias for Mpu region 11 + */ +#define mpuREGION11 10U + +/** @def mpuREGION12 + * @brief Mpu region 12 + * + * Alias for Mpu region 12 + */ +#define mpuREGION12 11U + +/** @def mpuREGION13 + * @brief Mpu region 13 + * + * Alias for Mpu region 13 + */ +#define mpuREGION13 12U + +/** @def mpuREGION14 + * @brief Mpu region 14 + * + * Alias for Mpu region 14 + */ +#define mpuREGION14 13U + +/** @def mpuREGION15 + * @brief Mpu region 15 + * + * Alias for Mpu region 15 + */ +#define mpuREGION15 14U + +/** @def mpuREGION16 + * @brief Mpu region 16 + * + * Alias for Mpu region 16 + */ +#define mpuREGION16 15U + +/** @def mpuREGION_ENABLE + * @brief Enable MPU Region + * + * Alias for MPU region enable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_ENABLE 1U + +/** @def mpuREGION_DISABLE + * @brief Disable MPU Region + * + * Alias for MPU region disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_DISABLE 0U + +/** @def mpuSUBREGION0_DISABLE + * @brief Disable MPU Sub Region0 + * + * Alias for MPU subregion0 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION0_DISABLE 0x100U + +/** @def mpuSUBREGION1_DISABLE + * @brief Disable MPU Sub Region1 + * + * Alias for MPU subregion1 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION1_DISABLE 0x200U + +/** @def mpuSUBREGION2_DISABLE + * @brief Disable MPU Sub Region2 + * + * Alias for MPU subregion2 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION2_DISABLE 0x400U + +/** @def mpuSUBREGION3_DISABLE + * @brief Disable MPU Sub Region3 + * + * Alias for MPU subregion3 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION3_DISABLE 0x800U + +/** @def mpuSUBREGION4_DISABLE + * @brief Disable MPU Sub Region4 + * + * Alias for MPU subregion4 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION4_DISABLE 0x1000U + +/** @def mpuSUBREGION5_DISABLE + * @brief Disable MPU Sub Region5 + * + * Alias for MPU subregion5 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION5_DISABLE 0x2000U + +/** @def mpuSUBREGION6_DISABLE + * @brief Disable MPU Sub Region6 + * + * Alias for MPU subregion6 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION6_DISABLE 0x4000U + +/** @def mpuSUBREGION7_DISABLE + * @brief Disable MPU Sub Region7 + * + * Alias for MPU subregion7 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION7_DISABLE 0x8000U + +/** @enum mpuRegionAccessPermission + * @brief Alias names for mpu region access permissions + * + * This enumeration is used to provide alias names for the mpu region access permission: + * - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode + * and execute + * - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode + * and execute + * - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode + * and execute + * - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and + * execute + * - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode + * and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode + * and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode + * and no execution + * + */ +enum mpuRegionAccessPermission +{ + MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access + in user mode and execute */ + MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias no read/write in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias no read/write in privileged mode, read + only in user mode and execute */ + MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias no read/write in privileged mode, + read/write in user mode and execute */ + MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias no read only in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias no read only in privileged mode, read + only in user mode and execute */ + MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, + read only in user mode and no execution */ + MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, + read/write in user mode and no execution */ + MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias no read only in privileged mode, read + only in user mode and no execution */ +}; + +/** @enum mpuRegionType + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_DEVICE_SHAREABLE Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, + * no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, + * no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no + * write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no + * write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cacheable + * and non shared + * - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cacheable + * and shared + * - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, + * write allocate and non shared + * - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, + * write allocate and shared + * - MPU_DEVICE_NONSHAREABLE Memory type device and non sharable + */ +enum mpuRegionType +{ + MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and + sharable */ + MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */ + MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner + write-through, no write allocate and non + shared */ + MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner + write-back, no write allocate and non + shared */ + MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner + write-through, no write allocate and shared + */ + MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner + write-back, no write allocate and shared */ + MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner + non-cacheable and non shared */ + MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner + write-back, write allocate and non shared */ + MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner + non-cacheable and shared */ + MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner + write-back, write allocate and shared */ + MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */ +}; + +/** @enum mpuRegionSize + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_32_BYTES Memory size in bytes + * - MPU_64_BYTES Memory size in bytes + * - MPU_128_BYTES Memory size in bytes + * - MPU_256_BYTES Memory size in bytes + * - MPU_512_BYTES Memory size in bytes + * - MPU_1_KB Memory size in kB + * - MPU_2_KB Memory size in kB + * - MPU_4_KB Memory size in kB + * - MPU_8_KB Memory size in kB + * - MPU_16_KB Memory size in kB + * - MPU_32_KB Memory size in kB + * - MPU_64_KB Memory size in kB + * - MPU_128_KB Memory size in kB + * - MPU_256_KB Memory size in kB + * - MPU_512_KB Memory size in kB + * - MPU_1_MB Memory size in MB + * - MPU_2_MB Memory size in MB + * - MPU_4_MB Memory size in MB + * - MPU_8_MBv Memory size in MB + * - MPU_16_MB Memory size in MB + * - MPU_32_MB Memory size in MB + * - MPU_64_MB Memory size in MB + * - MPU_128_MB Memory size in MB + * - MPU_256_MB Memory size in MB + * - MPU_512_MB Memory size in MB + * - MPU_1_GB Memory size in GB + * - MPU_2_GB Memory size in GB + * - MPU_4_GB Memory size in GB + */ +enum mpuRegionSize +{ + MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */ + MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */ + MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */ + MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */ + MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */ + MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */ + MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */ + MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */ + MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */ + MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */ + MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */ + MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */ + MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */ + MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */ + MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */ + MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */ + MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */ + MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */ + MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */ + MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */ + MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */ + MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */ + MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */ + MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */ + MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */ + MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */ + MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */ + MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */ +}; + +/** @fn void _mpuInit_(void) + * @brief Initialize Mpu + * + * This function initializes memory protection unit. + */ +void _mpuInit_( void ); + +/** @fn void _mpuEnable_(void) + * @brief Enable Mpu + * + * This function enables memory protection unit. + */ +void _mpuEnable_( void ); + +/** @fn void _mpuDisable_(void) + * @brief Disable Mpu + * + * This function disables memory protection unit. + */ +void _mpuDisable_( void ); + +/** @fn void _mpuEnableBackgroundRegion_(void) + * @brief Enable Mpu background region + * + * This function enables background region of the memory protection unit. + */ +void _mpuEnableBackgroundRegion_( void ); + +/** @fn void _mpuDisableBackgroundRegion_(void) + * @brief Disable Mpu background region + * + * This function disables background region of the memory protection unit. + */ +void _mpuDisableBackgroundRegion_( void ); + +/** @fn uint32 _mpuGetNumberOfRegions_(void) + * @brief Returns number of implemented Mpu regions + * @return Number of implemented mpu regions + * + * This function returns the number of implemented mpu regions. + */ +uint32 _mpuGetNumberOfRegions_( void ); + +/** @fn uint32 _mpuAreRegionsSeparate_(void) + * @brief Returns the type of the implemented mpu regions + * @return Mpu type of regions + * + * This function returns 0 when mpu regions are of type unified otherwise regions are of + * type separate. + */ +uint32 _mpuAreRegionsSeparate_( void ); + +/** @fn void _mpuSetRegion_(uint32 region) + * @brief Set mpu region number + * @param[in] region Region number: mpuREGION1..mpuREGION12 + * + * This function selects one of the implemented mpu regions. + */ +void _mpuSetRegion_( uint32 region ); + +/** @fn uint32 _mpuGetRegion_(void) + * @brief Returns the currently selected mpu region + * @return Mpu region number + * + * This function returns currently selected mpu region number. + */ +uint32 _mpuGetRegion_( void ); + +/** @fn void _mpuSetRegionBaseAddress_(uint32 address) + * @brief Set base address of currently selected mpu region + * @param[in] address Base address of the MPU region + * @note The base address must always aligned with region size + * + * This function sets the base address of currently selected mpu region. + */ +void _mpuSetRegionBaseAddress_( uint32 address ); + +/** @fn uint32 _mpuGetRegionBaseAddress_(void) + * @brief Returns base address of currently selected mpu region + * @return Current base address of selected mpu region + * + * This function returns the base address of currently selected mpu region. + */ +uint32 _mpuGetRegionBaseAddress_( void ); + +/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission) + * @brief Set type of currently selected mpu region + * @param[in] type Region Type + * - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and + * sharable + * - MPU_DEVICE_SHAREABLE : Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and + * inner write-through, no write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and + * inner write-back, no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and + * inner write-through, no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and + * inner write-back, no write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and + * inner non-cacheable and non shared + * - MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and + * inner write-back, write allocate and non shared + * - MPU_NORMAL_OINC_SHARED : Memory type normal outer and + * inner non-cacheable and shared + * - MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and + * inner write-back, write allocate and shared + * - MPU_DEVICE_NONSHAREABLE : Memory type device and non + * sharable + * + * @param[in] permission Region Access permission + * - MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged + * mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_NA_EXEC : Alias no read/write in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_RO_EXEC : Alias no read/write in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_RW_USER_RW_EXEC : Alias no read/write in + * privileged mode, read/write in user mode and execute + * - MPU_PRIV_RO_USER_NA_EXEC : Alias no read only in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RO_USER_RO_EXEC : Alias no read only in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged + * mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in + * privileged mode, read only in user mode and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in + * privileged mode, read/write in user mode and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in + * privileged mode, read only in user mode and no execution + * + * This function sets the type of currently selected mpu region. + */ +void _mpuSetRegionTypeAndPermission_( uint32 type, uint32 permission ); + +/** @fn uint32 _mpuGetRegionType_(void) + * @brief Returns the type of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns the type of currently selected mpu region. + */ +uint32 _mpuGetRegionType_( void ); + +/** @fn uint32 _mpuGetRegionPermission_(void) + * @brief Returns permission of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns permission of currently selected mpu region. + */ +uint32 _mpuGetRegionPermission_( void ); + +/** @fn void _mpuSetRegionSizeRegister_(uint32 value) + * @brief Set mpu region size register value + * @param[in] value Value to be written in the MPU Region Size and Enable register + * + * This function sets mpu region size register value. + * + * Sample usuage: + * _mpuSetRegion_(mpuREGION5); + * _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE | + * mpuSUBREGION4_DISABLE); + */ +void _mpuSetRegionSizeRegister_( uint32 value ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h new file mode 100644 index 00000000000..b8dc1fb4feb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h @@ -0,0 +1,331 @@ +/** @file pcr.h + * @brief PCR Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PCR driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PCR_H_ +#define PCR_H_ + +#include "reg_pcr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define QUADRANT0 1U +#define QUADRANT1 2U +#define QUADRANT2 4U +#define QUADRANT3 8U + +typedef enum +{ + PS0 = 0U, + PS1, + PS2, + PS3, + PS4, + PS5, + PS6, + PS7, + PS8, + PS9, + PS10, + PS11, + PS12, + PS13, + PS14, + PS15, + PS16, + PS17, + PS18, + PS19, + PS20, + PS21, + PS22, + PS23, + PS24, + PS25, + PS26, + PS27, + PS28, + PS29, + PS30, + PS31 +} peripheral_Frame_t; + +typedef enum +{ + PPS0 = 0U, + PPS1, + PPS2, + PPS3, + PPS4, + PPS5, + PPS6, + PPS7 +} privileged_Peripheral_Frame_t; + +typedef enum +{ + PPSE0 = 0U, + PPSE1, + PPSE2, + PPSE3, + PPSE4, + PPSE5, + PPSE6, + PPSE7, + PPSE8, + PPSE9, + PPSE10, + PPSE11, + PPSE12, + PPSE13, + PPSE14, + PPSE15, + PPSE16, + PPSE17, + PPSE18, + PPSE19, + PPSE20, + PPSE21, + PPSE22, + PPSE23, + PPSE24, + PPSE25, + PPSE26, + PPSE27, + PPSE28, + PPSE29, + PPSE30, + PPSE31 +} privileged_Peripheral_Extended_Frame_t; + +typedef enum +{ + PCS0 = 0U, + PCS1, + PCS2, + PCS3, + PCS4, + PCS5, + PCS6, + PCS7, + PCS8, + PCS9, + PCS10, + PCS11, + PCS12, + PCS13, + PCS14, + PCS15, + PCS16, + PCS17, + PCS18, + PCS19, + PCS20, + PCS21, + PCS22, + PCS23, + PCS24, + PCS25, + PCS26, + PCS27, + PCS28, + PCS29, + PCS30, + PCS31, + PCS32, + PCS33, + PCS34, + PCS35, + PCS36, + PCS37, + PCS38, + PCS39, + PCS40, + PCS41, + PCS42, + PCS43, + PCS44, + PCS45, + PCS46, + PCS47, + PCS48, + PCS49, + PCS50, + PCS51, + PCS52, + PCS53, + PCS54, + PCS55, + PCS56, + PCS57, + PCS58, + PCS59, + PCS60, + PCS61, + PCS62, + PCS63 +} peripheral_Memory_t; + +typedef enum +{ + PPCS0 = 0U, + PPCS1, + PPCS2, + PPCS3, + PPCS4, + PPCS5, + PPCS6, + PPCS7, + PPCS8, + PPCS9, + PPCS10, + PPCS11, + PPCS12, + PPCS13, + PPCS14, + PPCS15 +} privileged_Peripheral_Memory_t; + +typedef enum +{ + Master_CPU0 = 0U, + Master_CPU1 = 1U, /* Reserved for Lock-Step device */ + Master_DMA = 2U, + Master_HTU1 = 3U, + Master_HTU2 = 4U, + Master_FTU = 5U, + Master_DMM = 7U, + Master_DAP = 9U, + Master_EMAC = 10U +} master_ID_t; + +/** + * @defgroup PCR PCR + * @brief PPeripheral Central Resource Module + * + * Related files: + * - reg_pcr.h + * - sys_pcr.h + * - sys_pcr.c + * + * @addtogroup PCR + * @{ + */ + +void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Frame_Protection_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); +void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); + +void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); +void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); + +void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ); +void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ); + +void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ); +void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ); +void privileged_Peripheral_Memory_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ); +void privileged_Peripheral_Memory_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ); + +void pcrEnableMasterIDCheck( pcrBASE_t * pcr ); +void pcrDisableMasterIDCheck( pcrBASE_t * pcr ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* PCR_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h new file mode 100644 index 00000000000..0365d796e13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h @@ -0,0 +1,119 @@ +/** @file sys_pmm.h + * @brief PMM Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMM_H__ +#define __SYS_PMM_H__ + +#include "reg_pmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pmmLogicPDTag + * @brief PMM Logic Power Domain + * + * Used to define PMM Logic Power Domain + */ +typedef enum pmmLogicPDTag +{ + PMM_LOGICPD1 = 5U, /*-- NOT USED*/ + PMM_LOGICPD2 = 0U, + PMM_LOGICPD3 = 1U, + PMM_LOGICPD4 = 2U, + PMM_LOGICPD5 = 3U, + PMM_LOGICPD6 = 4U +} pmm_LogicPD_t; + +/** @enum pmmModeTag + * @brief PSCON operating mode + * + * Used to define the operating mode of PSCON Compare Block + */ +typedef enum pmmModeTag +{ + LockStep = 0x0U, + SelfTest = 0x6U, + ErrorForcing = 0x9U, + SelfTestErrorForcing = 0xFU +} pmm_Mode_t; + +/** + * @defgroup PMM PMM + * @brief Power Management Module + * + * The PMM provides memory-mapped registers that control the states of the supported power + * domains. The PMM includes interfaces to the Power Mode Controller (PMC) and the Power + * State Controller (PSCON). The PMC and PSCON control the power up/down sequence of each + * power domain. + * + * Related files: + * - reg_pmm.h + * - sys_pmm.h + * - sys_pmm.c + * + * @addtogroup PMM + * @{ + */ + +/* Pmm Interface Functions */ +boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ); +boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ); +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h new file mode 100644 index 00000000000..f60d1f47c55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h @@ -0,0 +1,240 @@ +/** @file sys_pmu.h + * @brief System Pmu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Pmu Interface Functions + * . + * which are relevant for the performance monitor unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMU_H__ +#define __SYS_PMU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def pmuCOUNTER0 + * @brief pmu event counter 0 + * + * Alias for pmu event counter 0 + */ +#define pmuCOUNTER0 0x00000001U + +/** @def pmuCOUNTER1 + * @brief pmu event counter 1 + * + * Alias for pmu event counter 1 + */ +#define pmuCOUNTER1 0x00000002U + +/** @def pmuCOUNTER2 + * @brief pmu event counter 2 + * + * Alias for pmu event counter 2 + */ +#define pmuCOUNTER2 0x00000004U + +/** @def pmuCYCLE_COUNTER + * @brief pmu cycle counter + * + * Alias for pmu event counter + */ +#define pmuCYCLE_COUNTER 0x80000000U + +/** @enum pmuEvent + * @brief pmu event + * + * Alias for pmu event counter increment source + */ +enum pmuEvent +{ + PMU_INST_CACHE_MISS = 0x01U, + PMU_DATA_CACHE_MISS = 0x03U, + PMU_DATA_CACHE_ACCESS = 0x04U, + PMU_DATA_READ_ARCH_EXECUTED = 0x06U, + PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U, + PMU_INST_ARCH_EXECUTED = 0x08U, + PMU_EXCEPTION_TAKEN = 0x09U, + PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU, + PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU, + PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU, + PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU, + PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU, + PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU, + PMU_BRANCH_MISSPREDICTED = 0x10U, + PMU_CYCLE_COUNT = 0x11U, + PMU_PREDICTABLE_BRANCHES = 0x12U, + PMU_INST_BUFFER_STALL = 0x40U, + PMU_DATA_DEPENDENCY_INST_STALL = 0x41U, + PMU_DATA_CACHE_WRITE_BACK = 0x42U, + PMU_EXT_MEMORY_REQUEST = 0x43U, + PMU_LSU_BUSY_STALL = 0x44U, + PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U, + PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U, + PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U, + PMU_ETMEXTOUT_0 = 0x48U, + PMU_ETMEXTOUT_1 = 0x49U, + PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU, + PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU, + PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU, + PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU, + PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU, + PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU, + PMU_STORE_BUFFER_MERGE = 0x50U, + PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U, + PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U, + PMU_INTEGER_DIV_EXECUTED = 0x53U, + PMU_STALL_INTEGER_DIV = 0x54U, + PMU_PLD_INST_LINE_FILL = 0x55U, + PMU_PLD_INST_NO_LINE_FILL = 0x56U, + PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U, + PMU_INST_CACHE_ACCESS = 0x58U, + PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U, + PMU_DUAL_ISSUE_CASE_A = 0x5AU, + PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU, + PMU_DUAL_ISSUE_OTHER = 0x5CU, + PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU, + PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU, + PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U, + PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U, + PMU_PROCESSOR_LIVE_LOCK = 0x62U, + PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U, + PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U, + PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U, + PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U, + PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U, + PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U, + PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU, + PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU, + PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU, + PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU, + PMU_ALL_CORRECTABLE_EVENTS = 0x6EU, + PMU_ALL_FATAL_EVENTS = 0x6FU, + PMU_ALL_CORRECTABLE_FAULTS = 0x70U, + PMU_ALL_FATAL_FAULTS = 0x71U, + PMU_ACP_DCACHE_ACCESS_LOOKUP_INVALIDATE = 0x72U, + PMU_ACP_DCACHE_INVALIDATE = 0x73U +}; + +/** @fn void _pmuInit_(void) + * @brief Initialize Performance Monitor Unit + */ +void _pmuInit_( void ); + +/** @fn void _pmuEnableCountersGlobal_(void) + * @brief Enable and reset cycle counter and all 3 event counters + */ +void _pmuEnableCountersGlobal_( void ); + +/** @fn void _pmuDisableCountersGlobal_(void) + * @brief Disable cycle counter and all 3 event counters + */ +void _pmuDisableCountersGlobal_( void ); + +/** @fn void _pmuResetCycleCounter_(void) + * @brief Reset cycle counter + */ +void _pmuResetCycleCounter_( void ); + +/** @fn void _pmuResetEventCounters_(void) + * @brief Reset event counters 0-2 + */ +void _pmuResetEventCounters_( void ); + +/** @fn void _pmuResetCounters_(void) + * @brief Reset cycle counter and event counters 0-2 + */ +void _pmuResetCounters_( void ); + +/** @fn void _pmuStartCounters_(uint32 counters) + * @brief Starts selected counters + * @param[in] counters - Counter mask + */ +void _pmuStartCounters_( uint32 counters ); + +/** @fn void _pmuStopCounters_(uint32 counters) + * @brief Stops selected counters + * @param[in] counters - Counter mask + */ +void _pmuStopCounters_( uint32 counters ); + +/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event) + * @brief Set event counter count event + * @param[in] counter - Counter select 0..2 + * @param[in] event - Count event + */ +void _pmuSetCountEvent_( uint32 counter, uint32 event ); + +/** @fn uint32 _pmuGetCycleCount_(void) + * @brief Returns current cycle counter value + * + * @return cycle count. + */ +uint32 _pmuGetCycleCount_( void ); + +/** @fn uint32 _pmuGetEventCount_(uint32 counter) + * @brief Returns current event counter value + * @param[in] counter - Counter select 0..2 + * + * @return event counter count. + */ +uint32 _pmuGetEventCount_( uint32 counter ); + +/** @fn uint32 _pmuGetOverflow_(void) + * @brief Returns current overflow register and clear flags + * + * @return overflow flags. + */ +uint32 _pmuGetOverflow_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h new file mode 100644 index 00000000000..3d989cf9acb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h @@ -0,0 +1,386 @@ +/** @file sys_vim.h + * @brief Vectored Interrupt Module Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - VIM Type Definitions + * - VIM General Definitions + * . + * which are relevant for Vectored Interrupt Controller. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_VIM_H__ +#define __SYS_VIM_H__ + +#include "reg_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* VIM Type Definitions */ + +/** @typedef t_isrFuncPTR + * @brief ISR Function Pointer Type Definition + * + * This type is used to access the ISR handler. + */ +typedef void ( *t_isrFuncPTR )( void ); + +/** @enum systemInterrupt + * @brief Alias names for clock sources + * + * This enumeration is used to provide alias names for the clock sources: + * - IRQ + * - FIQ + */ +typedef enum systemInterrupt +{ + SYS_IRQ = 0U, /**< Alias for IRQ interrupt */ + SYS_FIQ = 1U /**< Alias for FIQ interrupt */ +} systemInterrupt_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* VIM General Configuration */ + +#define VIM_CHANNELS 128U + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* Interrupt Handlers */ +extern void custom_dabort( void ); +extern void esmHighInterrupt( void ) __attribute__( ( weak, interrupt( "FIQ" ) ) ); +extern void phantomInterrupt( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void FreeRTOS_Tick_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void vPortYieldWithinAPI( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void FreeRTOS_IRQ_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +#define VIM_ECCSTAT ( *( volatile uint32 * ) 0xFFFFFDECU ) +#define VIM_ECCCTL ( *( volatile uint32 * ) 0xFFFFFDF0U ) +#define VIM_UERRADDR ( *( volatile uint32 * ) 0xFFFFFDF4U ) +#define VIM_FBVECADDR ( *( volatile uint32 * ) 0xFFFFFDF8U ) +#define VIM_SBERRADDR ( *( volatile uint32 * ) 0xFFFFFDFCU ) + +#define VIMRAMECCLOC ( *( volatile uint32 * ) 0xFFF82400U ) +#define VIMRAMLOC ( *( volatile uint32 * ) 0xFFF82000U ) + +/* Configuration registers */ +typedef struct vim_config_reg +{ + uint32 CONFIG_FIRQPR0; + uint32 CONFIG_FIRQPR1; + uint32 CONFIG_FIRQPR2; + uint32 CONFIG_FIRQPR3; + uint32 CONFIG_REQMASKSET0; + uint32 CONFIG_REQMASKSET1; + uint32 CONFIG_REQMASKSET2; + uint32 CONFIG_REQMASKSET3; + uint32 CONFIG_WAKEMASKSET0; + uint32 CONFIG_WAKEMASKSET1; + uint32 CONFIG_WAKEMASKSET2; + uint32 CONFIG_WAKEMASKSET3; + uint32 CONFIG_CAPEVT; + uint32 CONFIG_CHANCTRL[ 24U ]; +} vim_config_reg_t; + +/* Configuration registers initial value */ +#define VIM_FIRQPR0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_REQMASKSET0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 1U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_WAKEMASKSET0_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET1_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET2_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET3_CONFIGVALUE 0xFFFFFFFFU +#define VIM_CAPEVT_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +#define VIM_CHANCTRL0_CONFIGVALUE 0x00010203U +#define VIM_CHANCTRL1_CONFIGVALUE 0x04050607U +#define VIM_CHANCTRL2_CONFIGVALUE 0x08090A0BU +#define VIM_CHANCTRL3_CONFIGVALUE 0x0C0D0E0FU +#define VIM_CHANCTRL4_CONFIGVALUE 0x10111213U +#define VIM_CHANCTRL5_CONFIGVALUE 0x14151617U +#define VIM_CHANCTRL6_CONFIGVALUE 0x18191A1BU +#define VIM_CHANCTRL7_CONFIGVALUE 0x1C1D1E1FU +#define VIM_CHANCTRL8_CONFIGVALUE 0x20212223U +#define VIM_CHANCTRL9_CONFIGVALUE 0x24252627U +#define VIM_CHANCTRL10_CONFIGVALUE 0x28292A2BU +#define VIM_CHANCTRL11_CONFIGVALUE 0x2C2D2E2FU +#define VIM_CHANCTRL12_CONFIGVALUE 0x30313233U +#define VIM_CHANCTRL13_CONFIGVALUE 0x34353637U +#define VIM_CHANCTRL14_CONFIGVALUE 0x38393A3BU +#define VIM_CHANCTRL15_CONFIGVALUE 0x3C3D3E3FU +#define VIM_CHANCTRL16_CONFIGVALUE 0x40414243U +#define VIM_CHANCTRL17_CONFIGVALUE 0x44454647U +#define VIM_CHANCTRL18_CONFIGVALUE 0x48494A4BU +#define VIM_CHANCTRL19_CONFIGVALUE 0x4C4D4E4FU +#define VIM_CHANCTRL20_CONFIGVALUE 0x50515253U +#define VIM_CHANCTRL21_CONFIGVALUE 0x54555657U +#define VIM_CHANCTRL22_CONFIGVALUE 0x58595A5BU +#define VIM_CHANCTRL23_CONFIGVALUE 0x5C5D5E5FU + +/** + * @defgroup VIM VIM + * @brief Vectored Interrupt Manager + * + * The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and + * controlling the many interrupt sources present on a device. Interrupts are caused by + * events outside of the normal flow of program execution. + * + * Related files: + * - reg_vim.h + * - sys_vim.h + * - sys_vim.c + * + * @addtogroup VIM + * @{ + */ +/*VIM Interface functions*/ +void vimInit( void ); +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ); +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ); +void vimDisableInterrupt( uint32 channel ); +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ); +/*@}*/ +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h new file mode 100644 index 00000000000..a80f461245f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h @@ -0,0 +1,477 @@ +/** @file system.h + * @brief System Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_SYSTEM_H__ +#define __SYS_SYSTEM_H__ + +#include "reg_system.h" +#include "reg_flash.h" +#include "reg_l2ramw.h" +#include "reg_ccmr5.h" +#include "sys_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* System General Definitions */ + +/** @enum systemClockSource + * @brief Alias names for clock sources + * + * This enumeration is used to provide alias names for the clock sources: + * - Oscillator + * - Pll1 + * - External1 + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - PLL2 + * - External2 + * - Synchronous VCLK1 + */ +enum systemClockSource +{ + SYS_OSC = 0x0U, /**< Alias for oscillator clock Source */ + SYS_PLL1 = 0x1U, /**< Alias for Pll1 clock Source */ + SYS_EXTERNAL1 = 0x3U, /**< Alias for external clock Source */ + SYS_LPO_LOW = 0x4U, /**< Alias for low power oscillator low clock Source */ + SYS_LPO_HIGH = 0x5U, /**< Alias for low power oscillator high clock Source */ + SYS_PLL2 = 0x6U, /**< Alias for Pll2 clock Source */ + SYS_EXTERNAL2 = 0x7U, /**< Alias for external 2 clock Source */ + SYS_VCLK = 0x9U, /**< Alias for synchronous VCLK1 clock Source */ + SYS_PLL2_ODCLK_8 = 0xEU, /**< Alias for PLL2_post_ODCLK/8 */ + SYS_PLL2_ODCLK_16 = 0xFU /**< Alias for PLL2_post_ODCLK/8 */ +}; + +/** @enum resetSource + * @brief Alias names for reset sources + * + * This enumeration is used to provide alias names for the reset sources: + * - Power On Reset + * - Osc Failure Reset + * - Watch Dog Reset + * - Icepick Reset + * - CPU Reset + * - Software Reset + * - External Reset + * + */ +typedef enum +{ + POWERON_RESET = 0x8000U, /**< Alias for Power On Reset */ + OSC_FAILURE_RESET = 0x4000U, /**< Alias for Osc Failure Reset */ + WATCHDOG_RESET = 0x2000U, /**< Alias for Watch Dog Reset */ + WATCHDOG2_RESET = 0x1000U, /**< Alias for Watch Dog 2 Reset */ + DEBUG_RESET = 0x0800U, /**< Alias for Debug Reset */ + INTERCONNECT_RESET = 0x0080U, /**< Alias for Interconnect Reset */ + CPU0_RESET = 0x0020U, /**< Alias for CPU 0 Reset */ + SW_RESET = 0x0010U, /**< Alias for Software Reset */ + EXT_RESET = 0x0008U, /**< Alias for External Reset */ + NO_RESET = 0x0000U /**< Alias for No Reset */ +} resetSource_t; + +#define SYS_DOZE_MODE 0x000F3F02U +#define SYS_SNOOZE_MODE 0x000F3F03U +#define SYS_SLEEP_MODE 0x000FFFFFU +#define LPO_TRIM_VALUE ( ( ( *( volatile uint32 * ) 0xF00801B4U ) & 0xFFFF0000U ) >> 16U ) +#define SYS_EXCEPTION ( *( volatile uint32 * ) 0xFFFFFFE4U ) + +#define WATCHDOG_STATUS ( *( volatile uint32 * ) 0xFFFFFC98U ) +#define DEVICE_ID_REV ( *( volatile uint32 * ) 0xFFFFFFF0U ) + +/** @def OSC_FREQ + * @brief Oscillator clock source exported from HALCoGen GUI + * + * Oscillator clock source exported from HALCoGen GUI + */ +#define OSC_FREQ 16.0F + +/** @def PLL1_FREQ + * @brief PLL 1 clock source exported from HALCoGen GUI + * + * PLL 1 clock source exported from HALCoGen GUI + */ +#define PLL1_FREQ 300.00F + +/** @def LPO_LF_FREQ + * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI + * + * LPO Low Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_LF_FREQ 0.080F + +/** @def LPO_HF_FREQ + * @brief LPO High Freq Oscillator source exported from HALCoGen GUI + * + * LPO High Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_HF_FREQ 10.000F + +/** @def PLL1_FREQ + * @brief PLL 2 clock source exported from HALCoGen GUI + * + * PLL 2 clock source exported from HALCoGen GUI + */ +#define PLL2_FREQ 300.00F + +/** @def GCLK_FREQ + * @brief GCLK domain frequency exported from HALCoGen GUI + * + * GCLK domain frequency exported from HALCoGen GUI + */ +#define GCLK_FREQ 300.000F + +/** @def HCLK_FREQ + * @brief HCLK domain frequency exported from HALCoGen GUI + * + * HCLK domain frequency exported from HALCoGen GUI + */ +#define HCLK_FREQ 150.000F + +/** @def RTI_FREQ + * @brief RTI Clock frequency exported from HALCoGen GUI + * + * RTI Clock frequency exported from HALCoGen GUI + */ +#define RTI_FREQ 75.000F + +/** @def AVCLK1_FREQ + * @brief AVCLK1 Domain frequency exported from HALCoGen GUI + * + * AVCLK Domain frequency exported from HALCoGen GUI + */ +#define AVCLK1_FREQ 75.000F + +/** @def AVCLK2_FREQ + * @brief AVCLK2 Domain frequency exported from HALCoGen GUI + * + * AVCLK2 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK2_FREQ 0.000F + +/** @def AVCLK3_FREQ + * @brief AVCLK3 Domain frequency exported from HALCoGen GUI + * + * AVCLK3 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK3_FREQ 75.000F + +/** @def AVCLK4_FREQ + * @brief AVCLK4 Domain frequency exported from HALCoGen GUI + * + * AVCLK4 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK4_FREQ 75.000F + +/** @def VCLK1_FREQ + * @brief VCLK1 Domain frequency exported from HALCoGen GUI + * + * VCLK1 Domain frequency exported from HALCoGen GUI + */ +#define VCLK1_FREQ 75.000F + +/** @def VCLK2_FREQ + * @brief VCLK2 Domain frequency exported from HALCoGen GUI + * + * VCLK2 Domain frequency exported from HALCoGen GUI + */ +#define VCLK2_FREQ 75.000F + +/** @def VCLK3_FREQ + * @brief VCLK3 Domain frequency exported from HALCoGen GUI + * + * VCLK3 Domain frequency exported from HALCoGen GUI + */ +#define VCLK3_FREQ 75.000F + +/** @def VCLK4_FREQ + * @brief VCLK4 Domain frequency exported from HALCoGen GUI + * + * VCLK4 Domain frequency exported from HALCoGen GUI + */ +#define VCLK4_FREQ 75.0F + +/** @def SYS_PRE1 + * @brief Alias name for RTI1CLK PRE clock source + * + * This is an alias name for the RTI1CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 "Macro filled using GUI parameter cannot be avoided" + */ +#define SYS_PRE1 ( SYS_PLL1 ) + +/** @def SYS_PRE2 + * @brief Alias name for RTI2CLK pre clock source + * + * This is an alias name for the RTI2CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 "Macro filled using GUI parameter cannot be avoided" + */ +#define SYS_PRE2 ( SYS_PLL1 ) + +/* Configuration registers */ +typedef struct system_config_reg +{ + uint32 CONFIG_SYSPC1; + uint32 CONFIG_SYSPC2; + uint32 CONFIG_SYSPC7; + uint32 CONFIG_SYSPC8; + uint32 CONFIG_SYSPC9; + uint32 CONFIG_CSDIS; + uint32 CONFIG_CDDIS; + uint32 CONFIG_GHVSRC; + uint32 CONFIG_VCLKASRC; + uint32 CONFIG_RCLKSRC; + uint32 CONFIG_MSTGCR; + uint32 CONFIG_MINITGCR; + uint32 CONFIG_MSINENA; + uint32 CONFIG_PLLCTL1; + uint32 CONFIG_PLLCTL2; + uint32 CONFIG_SYSPC10; + uint32 CONFIG_LPOMONCTL; + uint32 CONFIG_CLKTEST; + uint32 CONFIG_DFTCTRLREG1; + uint32 CONFIG_DFTCTRLREG2; + uint32 CONFIG_GPREG1; + uint32 CONFIG_RAMGCR; + uint32 CONFIG_BMMCR1; + uint32 CONFIG_CLKCNTL; + uint32 CONFIG_ECPCNTL; + uint32 CONFIG_DEVCR1; + uint32 CONFIG_SYSECR; + uint32 CONFIG_PLLCTL3; + uint32 CONFIG_STCCLKDIV; + uint32 CONFIG_ECPCNTL1; + uint32 CONFIG_CLK2CNTRL; + uint32 CONFIG_VCLKACON1; + uint32 CONFIG_HCLKCNTL; + uint32 CONFIG_CLKSLIP; + uint32 CONFIG_EFC_CTLEN; +} system_config_reg_t; + +/* Configuration registers initial value */ +#define SYS_SYSPC1_CONFIGVALUE 0U + +#define SYS_SYSPC2_CONFIGVALUE 1U + +#define SYS_SYSPC7_CONFIGVALUE 0U + +#define SYS_SYSPC8_CONFIGVALUE 0U + +#define SYS_SYSPC9_CONFIGVALUE 1U + +#define SYS_CSDIS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x4U ) + +#define SYS_CDDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) ) + +#define SYS_GHVSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ) ) + +#define SYS_VCLKASRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_RCLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_MSTGCR_CONFIGVALUE 0x00000105U + +#define SYS_MINITGCR_CONFIGVALUE 0x5U + +#define SYS_MSINENA_CONFIGVALUE 0U + +#define SYS_PLLCTL1_CONFIGVALUE_1 \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) ) + +#define SYS_PLLCTL1_CONFIGVALUE_2 \ + ( ( ( SYS_PLLCTL1_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) + +#define SYS_PLLCTL2_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 255U << 22U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U ) + +#define SYS_SYSPC10_CONFIGVALUE 0U + +#define SYS_LPOMONCTL_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | LPO_TRIM_VALUE ) +#define SYS_LPOMONCTL_CONFIGVALUE_2 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 16U << 8U ) | 16U ) + +#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U + +#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U + +#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U + +#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU + +#define SYS_RAMGCR_CONFIGVALUE 0x00050000U + +#define SYS_BMMCR1_CONFIGVALUE 0xAU + +#define SYS_CLKCNTL_CONFIGVALUE \ + ( 0x00000100U | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define SYS_ECPCNTL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ) ) + +#define SYS_DEVCR1_CONFIGVALUE 0xAU + +#define SYS_SYSECR_CONFIGVALUE 0x00004000U +#define SYS2_PLLCTL3_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) ) + +#define SYS2_PLLCTL3_CONFIGVALUE_2 \ + ( ( ( SYS2_PLLCTL3_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) +#define SYS2_STCCLKDIV_CONFIGVALUE 0U +#define SYS2_ECPCNTL1_CONFIGVALUE 0x50000000U +#define SYS2_CLK2CNTRL_CONFIGVALUE ( 1U | 0x00000100U ) +#define SYS2_HCLKCNTL_CONFIGVALUE 1U +#define SYS2_VCLKACON1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 1U << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) +#define SYS2_CLKSLIP_CONFIGVALUE 0x5U +#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U + +#define L2FLASH_FBPWRMODE_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) | ( uint32 ) ( ( uint32 ) 3U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 10U ) | ( uint32 ) ( ( uint32 ) 3U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 6U ) | ( uint32 ) ( ( uint32 ) 3U << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ) ) +#define L2FLASH_FRDCNTL_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U ) + +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* FlashW General Definitions */ + +/** @enum flashWPowerModes + * @brief Alias names for flash bank power modes + * + * This enumeration is used to provide alias names for the flash bank power modes: + * - sleep + * - standby + * - active + */ +enum flashWPowerModes +{ + SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ + SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ + SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ +}; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define FSM_WR_ENA_HL ( *( volatile uint32 * ) 0xFFF87288U ) +#define EEPROM_CONFIG_HL ( *( volatile uint32 * ) 0xFFF872B8U ) +#define FSM_SECTOR1 ( *( volatile uint32 * ) 0xFFF872C0U ) +#define FSM_SECTOR2 ( *( volatile uint32 * ) 0xFFF872C4U ) +#define FCFG_BANK ( *( volatile uint32 * ) 0xFFF87400U ) + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/* System Interface Functions */ +void setupPLL( void ); +void trimLPO( void ); +void customTrimLPO( void ); +void setupFlash( void ); +void periphInit( void ); +void mapClocks( void ); +void systemInit( void ); +void systemPowerDown( uint32 mode ); +resetSource_t getResetSource( void ); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h new file mode 100644 index 00000000000..d38f913546f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h @@ -0,0 +1,625 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * + ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.01 29Oct2012 Vishwanath Reddy 0000000000000 Changes for + implementing Error Recovery + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + segmentation changes. + * 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested + by Vector. + * 00.01.04 12Feb2012 Vishwanath Reddy SDOCM00099152 Integration issues + fix. + * 00.01.05 04Mar2013 Vishwanath Reddy SDOCM00099152 Added Deleting a + block feature, bug fixes. + * 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : + copying of unconfigured blocks. + * 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : + Number of 8 bytes writes, fixed issue with copy blocks. + * 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature : CRC + check for unconfigured blocks, Main function modified to complete writes as fast as + possible, Added Non polling mode support. + * 00.01.09 19Apr2013 Vishwanath Reddy SDOCM00099152 Warning removal, + Added feature comparision of data during write. + * 00.01.10 11Jun2013 Vishwanath Reddy SDOCM00101845 Updated version + information. + * 00.01.11 05Jul2013 Vishwanath Reddy SDOCM00101643 Updated version + information. + * 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags + added. + * MISRA C fixes. + Version info corrected. + * 01.13.00 30Dec2013 Vishwanath Reddy 0000000000000 Undated version info + for SDOCM00107976 + * and SDOCM00105795. + * 01.13.01 19May2014 Vishwanath Reddy 0000000000000 Updated version info + for SDOCM00107913 + * and SDOCM00107622. + * 01.13.02 12Jun2014 Vishwanath Reddy 0000000000000 Updated version info + for SDOCM00108238 + * 01.14.00 26Mar2014 Vishwanath Reddy Update version info + for SDOCM00107161. + * 01.15.00 06Jun2014 Vishwanath Reddy Support for + Conqueror. + * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA + warnings. + * 01.16.01 12Sep2014 Vishwanath Reddy SDOCM00112930 Prototype for + TI_Fee_SuspendResumeErase added. + * TI_Fee_EraseCommandType enum added. + * extern added for + TI_Fee_bEraseSuspended. + * 01.17.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization + changes. + * 01.17.01 30Oct2014 Vishwanath Reddy SDOCM00113536 Support for + TMS570LS07xx,TMS570LS09xx, + * TMS570LS05xx, RM44Lx. + * 01.17.02 26Dec2014 Vishwanath Reddy SDOCM00114102 FLEE Errata Fix. + * SDOCM00114104 Change ALL 1's OK + check condition. + * Updated version info. + Added new macros. + * SDOCM00114423 Add new enum + TI_Fee_DeviceType. + * Add new variable + TI_Fee_MaxSectors and + * prototype + TI_FeeInternal_PopulateStructures. + * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version + history. + * Update ti_fee_util.c + file for the + * bugfix "If morethan + one data set is config- + * ured, then a valid + block may get invalidated if + * multiple valid blocks + are present in FEE memory. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + history. + * In + TI_FeeInternal_FeeManager, do not change the + * state to IDLE,after + completing the copy operation. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + history. + * Add a call of + TI_FeeInternal_PollFlashStatus() + * before reading data + from FEE bank in + * TI_FeeInternal_UpdateBlockOffsetArray(), + * TI_Fee_WriteAsync(),TI_Fee_WriteSync(), + * TI_Fee_ReadSync(), + TI_Fee_Read() + * 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update patch version + TI_FEE_SW_PATCH_VERSION. + * TI_FEE_FLASH_CRC_ENABLE is renamed to + * TI_FEE_FLASH_CHECKSUM_ENABLE. + * SDOCM00122429 In ti_fee_types.h, + add error when endianess + * is not defined. + * 01.19.00 08Augu2016 Vishwanath Reddy SDOCM00122592 Update patch version + TI_FEE_MINOR_VERSION. + * Code for using + partially ersed sector is now + * removed. + * Bugfix for FEE + reading from unimplemented memory + * space. + * 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update patch version + TI_FEE_MINOR_VERSION. + * Synchronous write API + modified to avoid copy of + * already copied block. + * 01.19.02 25Janu2017 Vishwanath Reddy SDOCM00122832 Update patch version + TI_FEE_MINOR_VERSION. + * Format API modified + to erase all configured VS. + * SDOCM00122833 In API + TI_Fee_ErrorRecovery, added polling for + * flash status before + calling TI_Fee_Init. + * 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Added + TI_Fee_bIsMainFunctionCalled Global Variable. + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_H + #define TI_FEE_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "hal_stdtypes.h" + #include "fee_interface.h" + #include "ti_fee_types.h" + #include "ti_fee_cfg.h" + /********************************************************************************************************************** + * GLOBAL CONSTANT MACROS + *********************************************************************************************************************/ + /* Fee Published Information */ + #define TI_FEE_MAJOR_VERSION 3U + #define TI_FEE_MINOR_VERSION 0U + #define TI_FEE_PATCH_VERSION 2U + #define TI_FEE_SW_MAJOR_VERSION 1U + #define TI_FEE_SW_MINOR_VERSION 19U + #define TI_FEE_SW_PATCH_VERSION 4U + + #define TI_FEE_VIRTUAL_SECTOR_VERSION 1U + + /* Virtual sector states */ + #define ActiveVSHi 0x0000FFFFU + #define ActiveVSLo 0x00000000U + #define CopyVSHi 0xFFFFFFFFU + #define CopyVSLo 0x00000000U + #define EmptyVSHi 0xFFFFFFFFU + #define EmptyVSLo 0x0000FFFFU + #define InvalidVSHi 0xFFFFFFFFU + #define InvalidVSLo 0xFFFFFFFFU + #define ReadyforEraseVSHi 0x00000000U + #define ReadyforEraseVSLo 0x00000000U + + /* Data Block states*/ + #define EmptyBlockHi 0xFFFFFFFFU + #define EmptyBlockLo 0xFFFFFFFFU + #define StartProgramBlockHi 0xFFFF0000U + #define StartProgramBlockLo 0xFFFFFFFFU + #define ValidBlockHi 0x00000000U + #define ValidBlockLo 0xFFFFFFFFU + #define InvalidBlockHi 0x00000000U + #define InvalidBlockLo 0xFFFF0000U + #define CorruptBlockHi 0x00000000U + #define CorruptBlockLo 0x00000000U + + #define FEE_BANK 0U + + /* Enable/Disable FEE sectors */ + #define FEE_DISABLE_SECTORS_31_00 0x00000000U + #define FEE_DISABLE_SECTORS_63_32 0x00000000U + #define FEE_ENABLE_SECTORS_31_00 0xFFFFFFFFU + #define FEE_ENABLE_SECTORS_63_32 0xFFFFFFFFU + +/********************************************************************************************************************** + * GLOBAL DATA TYPES AND STRUCTURES + *********************************************************************************************************************/ +/* Structures used */ +/* Enum to describe the Fee Status types */ +typedef enum +{ + TI_FEE_OK = 0U, /* Function returned no error */ + TI_FEE_ERROR = 1U /* Function returned an error */ +} TI_Fee_StatusType; + +/* Enum to describe the Virtual Sector State */ +typedef enum +{ + VsState_Invalid = 1U, + VsState_Empty = 2U, + VsState_Copy = 3U, + VsState_Active = 4U, + VsState_ReadyForErase = 5U +} VirtualSectorStatesType; + +/* Enum to describe the Block State */ +typedef enum +{ + Block_StartProg = 1U, + Block_Valid = 2U, + Block_Invalid = 3U +} BlockStatesType; + +/* Enum for error trpes */ +typedef enum +{ + Error_Nil = 0U, + Error_TwoActiveVS = 1U, + Error_TwoCopyVS = 2U, + Error_SetupStateMachine = 3U, + Error_CopyButNoActiveVS = 4U, + Error_NoActiveVS = 5U, + Error_BlockInvalid = 6U, + Error_NullDataPtr = 7U, + Error_NoFreeVS = 8U, + Error_InvalidVirtualSectorParameter = 9U, + Error_ExceedSectorOnBank = 10U, + Error_EraseVS = 11U, + Error_BlockOffsetGtBlockSize = 12U, + Error_LengthParam = 13U, + Error_FeeUninit = 14U, + Error_Suspend = 15U, + Error_InvalidBlockIndex = 16U, + Error_NoErase = 17U, + Error_CurrentAddress = 18U, + Error_Exceed_No_Of_DataSets = 19U +} TI_Fee_ErrorCodeType; + +typedef enum +{ + Suspend_Erase = 0U, + Resume_Erase +} TI_Fee_EraseCommandType; + +/* Enum to describe the Device types */ +typedef enum +{ + CHAMPION = 0U, /* Function returned no error */ + ARCHER = 1U /* Function returned an error */ +} TI_Fee_DeviceType; + +typedef uint32 TI_Fee_AddressType; /* Used for defining variables to indicate number of + bytes for address offset */ +typedef uint32 TI_Fee_LengthType; /* Used for defining variables to indicate number of + bytes per read/write/erase */ +typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType; + +/* Structure used when defining virtual sectors */ +/* The following error checks need to be performed: */ +/* Virtual Sector definitions are not allowed to overlap */ +/* Virtual Sector definition is at least twice the size in bytes of the total size of all + * defined blocks */ +/* We will need to define a formula to indicate if the number of write cycles indicated in + * the block definitions */ +/* is possible in the defined Virtual Sector. */ +/* Ending sector cannot be less than Starting sector */ +typedef struct +{ + uint16 FeeVirtualSectorNumber; /* Virtual Sector's Number - 0 and 0xFFFF values are + not allowed*/ + /* Minimum 1, Maximum 4 */ + uint16 FeeFlashBank; /* Flash Bank to use for virtual sector. */ + /* As we do not allow Flash EEPROM Emulation in Bank 0, + 0 is not a valid option */ + /* Defaultvalue 1, Minimum 1, Maxiumum 7 */ + Fapi_FlashSectorType FeeStartSector; /* Defines the Starting Sector inthe Bank for + this VirtualSector*/ + Fapi_FlashSectorType FeeEndSector; /* Defines the Ending Sector inthe Bank for this + Virtual Sector */ + /* Start and End sectors can be the same, which indicates only + one sector */ + /* is the entire virtual sector. */ + /* Values are based on the FLASH_SECT enum */ + /* Defaultvalue and Min is the same sector defined as the starting + sector */ + /* Max values are based onthe device definition file being used.*/ +} Fee_VirtualSectorConfigType; + +/* Structure used when defining blocks */ +typedef struct +{ + uint16 FeeBlockNumber; /* Block's Number - 0 and 0xFFFF values are not allowed */ + /* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */ + uint16 FeeBlockSize; /* Block's Size - Actual number of bits used is reduced */ + /* by number of bits used for dataset. */ + /* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */ + boolean FeeImmediateData; /* Indicates if the block is used for immediate data */ + /* Default: False */ + uint32 FeeNumberOfWriteCycles; /* Number of write cycles this block requires */ + /* Default: 0, but this will not be a valid number. + Force customer to select a value */ + /* Min 1, Max (2^32)-1 */ + uint8 FeeDeviceIndex; /* Device Index - This will always be 0 */ + /* Fixed value: 0 */ + uint8 FeeNumberOfDataSets; /* Number of DataSets for the Block */ + /* Default value: 1 */ + uint8 FeeEEPNumber; +} Fee_BlockConfigType; + +/* Structure used for Global variables */ +typedef struct +{ + TI_Fee_AddressType Fee_oFlashNextAddress; /* The next Flash Address to write to */ + TI_Fee_AddressType Fee_oCopyCurrentAddress; /* Indicates the Address within the Active + VS which will be copied to Copy VS */ + TI_Fee_AddressType Fee_oCopyNextAddress; /* Indicates the Address within the Copy VS + to which the data from Active VS will be + copied to */ + TI_Fee_AddressType Fee_u32nextwriteaddress; /* Indicates the next free Address within + the curent VS to which the data will be + written */ + TI_Fee_AddressType Fee_oVirtualSectorStartAddress; /* Start Address of the current + Virtual Sector */ + TI_Fee_AddressType Fee_oVirtualSectorEndAddress; /* End Address of the current Virtual + Sector */ + TI_Fee_AddressType Fee_oCopyVirtualSectorAddress; /* Start Address of the Copy Virtual + Address */ + TI_Fee_AddressType Fee_oCurrentStartAddress; /* Start Address of the Previous Block */ + TI_Fee_AddressType Fee_oCurrentBlockHeader; /* Start Address of the Block which is + being currently written*/ + TI_Fee_AddressType Fee_oWriteAddress; /* Address within the VS where data is to be + written */ + TI_Fee_AddressType Fee_oCopyWriteAddress; /* Address within the VS where data is to be + copied */ + TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; /* Start Address of the Active VS + */ + TI_Fee_AddressType Fee_oBlankFailAddress; /* Address of first non-blank location */ + TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress; /* Start Address of the + active VS */ + TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress; /* End Address of the active VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress; /* Start Address of the Copy VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress; /* End Address of the Copy VS */ + TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress; /* Next write address in Active VS + */ + TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress; /* Next write address in Copy VS */ + uint16 Fee_u16CopyBlockSize; /* Indicates the size of current block in bytes which is + been copied from Active to Copy VS */ + uint8 Fee_u8VirtualSectorStart; /* Index of the Start Sector of the VS */ + uint8 Fee_u8VirtualSectorEnd; /* Index of the End Sector of the VS */ + uint32 Fee_au32VirtualSectorStateValue[ TI_FEE_VIRTUAL_SECTOR_OVERHEAD + >> 2U ]; /* Array to store the Virtual + Sector Header and + Information record */ + uint8 Fee_au8VirtualSectorState[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Stores the + state of each + Virtual sector + */ + uint32 Fee_au32VirtualSectorEraseCount[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Array + to + store + the + erase + count + of each + Virtual + Sector*/ + uint16 Fee_au16BlockOffset[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to store within + the VS */ + uint32 Fee_au32BlockHeader[ TI_FEE_BLOCK_OVERHEAD >> 2U ]; /* Array to store the Block + Header value */ + uint8 Fee_au8BlockCopyStatus[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to storeblock + copy status */ + uint8 Fee_u8InternalVirtualSectorStart; /* Indicates internal VS start index */ + uint8 Fee_u8InternalVirtualSectorEnd; /* Indicates internal VS end index */ + TI_FeeModuleStatusType Fee_ModuleState; /* Indicates the state of the FEE module */ + TI_FeeJobResultType Fee_u16JobResult; /* Stores the Job Result of the current command + */ + TI_Fee_StatusType Fee_oStatus; /* Indicates the status of FEE */ + TI_Fee_ErrorCodeType Fee_Error; /* Indicates the Error code */ + uint16 Fee_u16CopyBlockNumber; /* Block number which is currently being copied */ + uint16 Fee_u16BlockIndex; /* Index of the Current Block */ + uint16 Fee_u16BlockCopyIndex; /* Index of the Block being copied from Copy to Active + VS */ + uint16 Fee_u16DataSetIndex; /* Index of the Current DataSet */ + uint16 Fee_u16ArrayIndex; /* Index of the Current DataSet */ + uint16 Fee_u16BlockSize; /* Size of the current block in bytes */ + uint16 Fee_u16BlockSizeinBlockHeader; /* Size of the current block. Used to write into + Block Header */ + uint16 Fee_u16BlockNumberinBlockHeader; /* Number of the current block. Used to write + into Block Header */ + uint8 Fee_u8ActiveVirtualSector; /* Indicates the FeeVirtualSectorNumber for the + Active VS */ + uint8 Fee_u8CopyVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Copy VS + */ + uint32 Fee_u32InternalEraseQueue; /* Indicates which VS can be erased when the FEE is + in BusyInternal State*/ + uint8 Fee_u8WriteCopyVSHeader; /* Indicates the number of bytes of the Copy VS Header + being written */ + uint8 Fee_u8WriteCount; /* Indicates the number of bytes of the Block Header being + written */ + uint8 * Fee_pu8ReadDataBuffer; /* Pointer to read data */ + uint8 * Fee_pu8ReadAddress; /* Pointer to read address */ + uint8 * Fee_pu8Data; /* Pointer to the next data to be written to the VS */ + uint8 * Fee_pu8CopyData; /* Pointer to the next data to be copied to the VS */ + uint8 * Fee_pu8DataStart; /* Pointer to the first data to be written to the VS */ + boolean Fee_bInvalidWriteBit; /* Indicates whether the block is + written/invalidated/erased for the first time */ + boolean Fee_bWriteData; /* Indicates that there is data which is pending to be written + to the Block */ + boolean Fee_bWriteBlockHeader; /* Indicates whether the Block Header has been written + or not */ + boolean bWriteFirstTime; /* Indicates if the block is being written first time */ + boolean Fee_bFindNextVirtualSector; /* Indicates if there is aneed to find next free + VS */ + boolean Fee_bWriteVSHeader; /* Indicates if block header needs to be written */ + boolean Fee_bWriteStartProgram; /* Indicates if start program block header needs to be + written */ + boolean Fee_bWritePartialBlockHeader; /* Indicates if start program block header needs + to be written */ + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) + uint16 Fee_au16UnConfiguredBlockAddress + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Indicates + number of unconfigured blocks to copy */ + uint8 Fee_au8UnConfiguredBlockCopyStatus + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Array to store block + copy status */ + #endif +} TI_Fee_GlobalVarsType; + +/********************************************************************************************************************** + * EXTERN Declarations + *********************************************************************************************************************/ +/* Fee Global Variables */ +extern const Fee_BlockConfigType Fee_BlockConfiguration[ TI_FEE_NUMBER_OF_BLOCKS ]; + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF ) +extern const Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern const Device_FlashType Device_FlashDevice; + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +extern Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern Device_FlashType Device_FlashDevice; +extern uint8 TI_Fee_MaxSectors; + #endif +extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[ TI_FEE_NUMBER_OF_EEPS ]; +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[ TI_FEE_NUMBER_OF_EEPS ]; + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +extern uint32 TI_Fee_u32FletcherChecksum; + #endif +extern uint32 TI_Fee_u32BlockEraseCount; +extern uint8 TI_Fee_u8DataSets; +extern uint8 TI_Fee_u8DeviceIndex; +extern uint32 TI_Fee_u32ActCpyVS; +extern uint8 TI_Fee_u8ErrEraseVS; + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) +extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[ TI_FEE_NUMBER_OF_EEPS ]; + #endif + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern boolean Fee_bDoubleBitError; +extern boolean Fee_bSingleBitError; + #endif + #if( TI_FEE_NUMBER_OF_EEPS == 2U ) +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global; + #endif +extern boolean TI_Fee_FapiInitCalled; +extern boolean TI_Fee_bEraseSuspended; +extern boolean TI_Fee_bIsMainFunctionCalled; + +/********************************************************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + *********************************************************************************************************************/ +/* Interface Functions */ +extern void TI_Fee_Cancel( uint8 u8EEPIndex ); +extern Std_ReturnType TI_Fee_EraseImmediateBlock( uint16 BlockNumber ); +extern TI_FeeModuleStatusType TI_Fee_GetStatus( uint8 u8EEPIndex ); +extern void TI_Fee_GetVersionInfo( Std_VersionInfoType * VersionInfoPtr ); +extern void TI_Fee_Init( void ); +extern Std_ReturnType TI_Fee_InvalidateBlock( uint16 BlockNumber ); +extern Std_ReturnType TI_Fee_Read( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); +extern Std_ReturnType TI_Fee_WriteAsync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern void TI_Fee_MainFunction( void ); +extern TI_Fee_ErrorCodeType TI_FeeErrorCode( uint8 u8EEPIndex ); +extern void TI_Fee_ErrorRecovery( TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector ); +extern TI_FeeJobResultType TI_Fee_GetJobResult( uint8 u8EEPIndex ); +extern void TI_Fee_SuspendResumeErase( TI_Fee_EraseCommandType Command ); + + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern void TI_Fee_ErrorHookSingleBitError( void ); +extern void TI_Fee_ErrorHookDoubleBitError( void ); + #endif + + #if( TI_FEE_DRIVER == 1U ) +extern Std_ReturnType TI_Fee_WriteSync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern Std_ReturnType TI_Fee_Shutdown( void ); +extern boolean TI_Fee_Format( uint32 u32FormatKey ); +extern Std_ReturnType TI_Fee_ReadSync( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); + #endif + +/* TI Fee Internal Functions */ +TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress( uint8 u8EEPIndex ); +TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC( TI_Fee_AddressType oAddress ); +TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - + * TI_FeeInternal_GetVirtualSectorParameter name is required here."*/ +uint32 TI_FeeInternal_GetVirtualSectorParameter( Fapi_FlashSectorType oSector, + uint16 u16Bank, + boolean VirtualSectorInfo, + uint8 u8EEPIndex ); +uint32 TI_FeeInternal_PollFlashStatus( void ); +uint16 TI_FeeInternal_GetBlockSize( uint16 BlockIndex ); +uint16 TI_FeeInternal_GetBlockIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetDataSetIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetBlockNumber( uint16 BlockNumber ); +uint8 TI_FeeInternal_FindNextVirtualSector( uint8 u8EEPIndex ); +uint8 TI_FeeInternal_WriteDataF021( boolean bCopy, + uint16 u16WriteSize, + uint8 u8EEPIndex ); +boolean TI_FeeInternal_BlankCheck( uint32 u32StartAddress, + uint32 u32EndAddress, + uint16 u16Bank, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckReadParameters( uint32 u32BlockSize, + uint16 BlockOffset, + const uint8 * DataBufferPtr, + uint16 Length, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckModuleState( uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_InvalidateErase( uint16 BlockNumber ); +TI_Fee_StatusType TI_FeeInternal_FeeManager( uint8 u8EEPIndex ); +void TI_FeeInternal_WriteVirtualSectorHeader( uint8 FeeVirtualSectorNumber, + VirtualSectorStatesType VsState, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - TI_FeeInternal_GetVirtualSectorIndex + * name is required here."*/ +void TI_FeeInternal_GetVirtualSectorIndex( Fapi_FlashSectorType oSectorStart, + Fapi_FlashSectorType oSectorEnd, + uint16 u16Bank, + boolean bOperation, + uint8 u8EEPIndex ); +void TI_FeeInternal_WritePreviousBlockHeader( boolean bWrite, uint8 u8EEPIndex ); +void TI_FeeInternal_WriteBlockHeader( boolean bWrite, + uint8 u8EEPIndex, + uint16 Fee_BlockSize_u16, + uint16 u16BlockNumber ); +void TI_FeeInternal_SetClearCopyBlockState( uint8 u8EEPIndex, boolean bSetClear ); +void TI_FeeInternal_SanityCheck( uint16 BlockSize, uint8 u8EEPIndex ); +void TI_FeeInternal_StartProgramBlock( uint8 u8EEPIndex ); +void TI_FeeInternal_UpdateBlockOffsetArray( uint8 u8EEPIndex, + boolean bActCpyVS, + uint8 u8VirtualSector ); +void TI_FeeInternal_WriteInitialize( TI_Fee_AddressType oFlashNextAddress, + uint8 * DataBufferPtr, + uint8 u8EEPIndex ); +void TI_FeeInternal_CheckForError( uint8 u8EEPIndex ); +void TI_FeeInternal_EnableRequiredFlashSector( uint32 u32VirtualSectorStartAddress ); +uint16 TI_FeeInternal_GetArrayIndex( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex, + boolean bCallContext ); + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +uint32 TI_FeeInternal_Fletcher16( uint8 const * pu8data, uint16 u16Length ); + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +void TI_FeeInternal_PopulateStructures( TI_Fee_DeviceType DeviceType ); + #endif +#endif /* TI_FEE_H */ +/********************************************************************************************************************** + * END OF FILE: ti_fee.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h new file mode 100644 index 00000000000..60e8117e6c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h @@ -0,0 +1,55 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_cfg.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: HALCoGen + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.00.01 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + *history. + * + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h new file mode 100644 index 00000000000..7dea8d67c26 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h @@ -0,0 +1,260 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 03.00.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + *segmentation changes. 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 + *MISRA C fixes. + * 01.15.00 06Jun2014 Vishwanath Reddy Support for LC + *Varients. 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove + *MISRA warnings. + * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version + *history. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + *history. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + *history. 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update + *version history. SDOCM00122429 Added error when endianess is not defined. 01.19.00 + *08Augu2016 Vishwanath Reddy SDOCM00122592 Update version history. 01.19.01 + *12Augu2016 Vishwanath Reddy SDOCM00122543 Update version history. 01.19.03 + *15May2017 Prathap Srinivasan SDOCM00122917 Update version history. 01.19.04 + *05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_TYPES_H + #define TI_FEE_TYPES_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "Device_header.h" + + #ifndef TI_Fee_None + #define TI_Fee_None \ + 0x00U /*Take no action on single bit errors, (respond with corrected data), \ + */ + /*return error for uncorrectable error reads (multibit errors for ECC or parity + * failures)*/ + /*For devices with no ECC (they may have parity or not) the only valid option is none. + */ + #endif + + #ifndef TI_Fee_Fix + #define TI_Fee_Fix 0x01U /* single bit error will be fixed by reprogramming */ + /* return previous valid data for uncorrectable error reads (multi bit errors for ECC + or parity failures). */ + #endif + + #if !defined( _LITTLE_ENDIAN ) && !defined( _BIG_ENDIAN ) + #error "Target Endianess is not defined. Include F021 header files and library." + #endif + +/*SAFETYMCUSW 74 S MR:18.4 "Reason - union declaration is necessary here."*/ +typedef union +{ + uint16 Fee_u16StatusWord; + #ifdef _BIG_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + } Fee_StatusWordType_ST; + #endif + #ifdef _LITTLE_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + } Fee_StatusWordType_ST; + #endif +} TI_Fee_StatusWordType_UN; + +typedef enum +{ + UNINIT, + IDLE, + /*SAFETYMCUSW 91 S MR:5.2,5.6,5.7 "Reason - BUSY in F021 is a member of + * structure."*/ + BUSY, + BUSY_INTERNAL +} TI_FeeModuleStatusType; + +typedef enum +{ + JOB_OK, + JOB_FAILED, + JOB_PENDING, + JOB_CANCELLED, + BLOCK_INCONSISTENT, + BLOCK_INVALID +} TI_FeeJobResultType; + +#endif /* TI_FEE_TYPES_H */ + +/********************************************************************************************************************** + * END OF FILE: ti_fee_types.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c new file mode 100644 index 00000000000..c9b4ed5f955 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c @@ -0,0 +1,1052 @@ +/** @file adc.c + * @brief ADC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void adcInit(void) + * @brief Initializes ADC Driver + * + * This function initializes the ADC driver. + * + */ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ADC_SourceId_001 */ +/* DesignId : ADC_DesignId_001 */ +/* Requirements : CONQ_ADC_SR2 */ +void adcInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b Initialize @b ADC1: */ + + /** - Reset ADC module */ + adcREG1->RSTCR = 1U; + adcREG1->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG1->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG1->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG1->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG1->BNDEND = ( adcREG1->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup event group sample window */ + adcREG1->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 1 sample window */ + adcREG1->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 2 sample window */ + adcREG1->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC1 EVT pin output value */ + adcREG1->EVTOUT = 0U; + + /** - ADC1 EVT pin direction */ + adcREG1->EVTDIR = 0U; + + /** - ADC1 EVT pin open drain enable */ + adcREG1->EVTPDR = 0U; + + /** - ADC1 EVT pin pullup / pulldown selection */ + adcREG1->EVTPSEL = 1U; + + /** - ADC1 EVT pin pullup / pulldown enable*/ + adcREG1->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG1->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG1->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG1->PARCR = 0x00000005U; + + /** @b Initialize @b ADC2: */ + + /** - Reset ADC module */ + adcREG2->RSTCR = 1U; + adcREG2->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG2->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG2->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG2->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG2->BNDEND = ( adcREG2->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup event group sample window */ + adcREG2->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 1 sample window */ + adcREG2->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 2 sample window */ + adcREG2->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC2 EVT pin output value */ + adcREG2->EVTOUT = 0U; + + /** - ADC2 EVT pin direction */ + adcREG2->EVTDIR = 0U; + + /** - ADC2 EVT pin open drain enable */ + adcREG2->EVTPDR = 0U; + + /** - ADC2 EVT pin pullup / pulldown selection */ + adcREG2->EVTPSEL = 1U; + + /** - ADC2 EVT pin pullup / pulldown enable*/ + adcREG2->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG2->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG2->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG2->PARCR = 0x00000005U; + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** - s_adcSelect is used as constant table for channel selection */ +static const uint32 s_adcSelect[ 2U ][ 3U ] = { + { 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U }, + { + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + } +}; + +/** - s_adcFiFoSize is used as constant table for channel selection */ +static const uint32 s_adcFiFoSize[ 2U ][ 3U ] = { { 16U, 16U, 16U }, { 16U, 16U, 16U } }; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) + * @brief Starts an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function starts a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_002 */ +/* DesignId : ADC_DesignId_002 */ +/* Requirements : CONQ_ADC_SR3 */ +void adcStartConversion( adcBASE_t * adc, uint32 group ) +{ + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Setup FiFo size */ + adc->GxINTCR[ group ] = s_adcFiFoSize[ index ][ group ]; + + /** - Start Conversion */ + adc->GxSEL[ group ] = s_adcSelect[ index ][ group ]; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) + * @brief Stops an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function stops a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_003 */ +/* DesignId : ADC_DesignId_003 */ +/* Requirements : CONQ_ADC_SR4 */ +void adcStopConversion( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Stop Conversion */ + adc->GxSEL[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) + * @brief Resets FiFo read and write pointer. + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function resets the FiFo read and write pointers. + * + */ +/* SourceId : ADC_SourceId_004 */ +/* DesignId : ADC_DesignId_004 */ +/* Requirements : CONQ_ADC_SR5 */ +void adcResetFiFo( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Reset FiFo */ + adc->GxFIFORESETCR[ group ] = 1U; + + /** @note The function adcInit has to be called before this function can be used.\n + * the conversion should be stopped before calling this function. + */ + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) + * @brief Gets converted a ADC values + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @param[out] data Pointer to store ADC converted data + * @return The function will return the number of converted values copied into data + * buffer: + * + * This function writes a ADC message into a ADC message box. + * + */ +/* SourceId : ADC_SourceId_005 */ +/* DesignId : ADC_DesignId_005 */ +/* Requirements : CONQ_ADC_SR6 */ +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ) +{ + uint32 i; + uint32 buf; + uint32 mode; + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + uint32 intcr_reg = adc->GxINTCR[ group ]; + uint32 count = ( intcr_reg >= 256U ) ? s_adcFiFoSize[ index ][ group ] + : ( s_adcFiFoSize[ index ][ group ] + - ( uint32 ) ( intcr_reg & 0xFFU ) ); + adcData_t * ptr = data; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mode = ( adc->OPMODECR & ADC_12_BIT_MODE ); + + if( mode == ADC_12_BIT_MODE ) + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0xFFFU ); + ptr->id = ( uint32 ) ( ( buf >> 16U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + else + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0x3FFU ); + ptr->id = ( uint32 ) ( ( buf >> 10U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + + adc->GxINTFLG[ group ] = 9U; + + /** @note The function adcInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return count; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) + * @brief Checks if FiFo buffer is full + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When FiFo buffer is not full + * - 1: When FiFo buffer is full + * - 3: When FiFo buffer overflow occurred + * + * This function checks FiFo buffer status. + * + */ +/* SourceId : ADC_SourceId_006 */ +/* DesignId : ADC_DesignId_006 */ +/* Requirements : CONQ_ADC_SR7 */ +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read FiFo flags */ + flags = adc->GxINTFLG[ group ] & 3U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) + * @brief Checks if Conversion is complete + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When is not finished + * - 8: When conversion is complete + * + * This function checks if conversion is complete. + * + */ +/* SourceId : ADC_SourceId_007 */ +/* DesignId : ADC_DesignId_007 */ +/* Requirements : CONQ_ADC_SR8 */ +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Read conversion flags */ + flags = adc->GxINTFLG[ group ] & 8U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn void adcCalibration(adcBASE_t *adc) + * @brief Computes offset error using Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * This function computes offset error using Calibration mode + * + */ +/* SourceId : ADC_SourceId_008 */ +/* DesignId : ADC_DesignId_010 */ +/* Requirements : CONQ_ADC_SR11 */ +void adcCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + uint32 conv_val[ 5U ] = { 0U, 0U, 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 4U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + case 2U: /* Test 1 : Bride En = 1 , HiLo =0 */ + adc->CALCR = 0x0200U; + break; + + case 3U: /* Test 1 : Bride En = 1 , HiLo =1 */ + adc->CALCR = 0x0300U; + break; + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 4U ] = conv_val[ 0U ] + conv_val[ 1U ] + conv_val[ 2U ] + conv_val[ 3U ]; + + conv_val[ 4U ] = ( conv_val[ 4U ] / 4U ); + + offset_error = conv_val[ 4U ] - 0x7FFU; + + /*Write the offset error to the Calibration register */ + /* Load 2;s complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error & 0xFFFU; + offset_error = offset_error + 1U; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + /** @note The function adcInit has to be called before using this function. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/** @fn void adcMidPointCalibration(adcBASE_t *adc) + * @brief Computes offset error using Mid Point Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @return This function will return offset error using Mid Point Calibration mode + * + * This function computes offset error using Mid Point Calibration mode + * + */ +/* SourceId : ADC_SourceId_009 */ +/* DesignId : ADC_DesignId_011 */ +/* Requirements : CONQ_ADC_SR12 */ +uint32 adcMidPointCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + uint32 conv_val[ 3U ] = { 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 2U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 2U ] = ( conv_val[ 0U ] ) + ( conv_val[ 1U ] ); + + conv_val[ 2U ] = ( conv_val[ 2U ] / 2U ); + + offset_error = conv_val[ 2U ] - 0x7FFU; + + /* Write the offset error to the Calibration register */ + /* Load 2's complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error + 1U; + offset_error = offset_error & 0xFFFU; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + return ( offset_error ); + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) + * @brief Enable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will enable the notification of a conversion. + * In single conversion mode for conversion complete and + * in continuous conversion mode when the FiFo buffer is full. + * + */ +/* SourceId : ADC_SourceId_010 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : CONQ_ADC_SR9 */ +void adcEnableNotification( adcBASE_t * adc, uint32 group ) +{ + uint32 notif = ( ( ( uint32 ) ( adc->GxMODECR[ group ] ) & 2U ) == 2U ) ? 1U : 8U; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = notif; + + /** @note The function adcInit has to be called before this function can be used.\n + * This function should be called before the conversion is started + */ + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + +/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) + * @brief Disable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will disable the notification of a conversion. + */ +/* SourceId : ADC_SourceId_011 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : CONQ_ADC_SR9 */ +void adcDisableNotification( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} + +/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @param[in] value Value to be set: 0 or 1 + * + * This function will set the ADC EVT pin if configured as an output pin. + */ +/* SourceId : ADC_SourceId_012 */ +/* DesignId : ADC_DesignId_014 */ +/* Requirements : CONQ_ADC_SR13 */ +void adcSetEVTPin( adcBASE_t * adc, uint32 value ) +{ + adc->EVTOUT = value; +} + +/** @fn uint32 adcGetEVTPin(adcBASE_t *adc) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @return Value of the ADC EVT pin: 0 or 1 + * + * This function will return the value of ADC EVT pin. + */ +/* SourceId : ADC_SourceId_013 */ +/* DesignId : ADC_DesignId_015 */ +/* Requirements : CONQ_ADC_SR14 */ +uint32 adcGetEVTPin( adcBASE_t * adc ) +{ + return adc->EVTIN; +} + +/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_014 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : CONQ_ADC_SR15 */ +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC1_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC1_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC1_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; + } + else + { + config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG1->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG1->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG1->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG1->EVSRC; + config_reg->CONFIG_G1SRC = adcREG1->G1SRC; + config_reg->CONFIG_G2SRC = adcREG1->G2SRC; + config_reg->CONFIG_BNDCR = adcREG1->BNDCR; + config_reg->CONFIG_BNDEND = adcREG1->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG1->PARCR; + } +} + +/** @fn void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_015 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : CONQ_ADC_SR15 */ +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC2_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC2_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC2_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC2_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC2_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC2_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC2_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC2_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC2_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC2_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC2_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC2_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC2_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC2_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC2_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC2_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC2_PARCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_OPMODECR = adcREG2->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG2->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG2->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG2->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG2->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG2->EVSRC; + config_reg->CONFIG_G1SRC = adcREG2->G1SRC; + config_reg->CONFIG_G2SRC = adcREG2->G2SRC; + config_reg->CONFIG_BNDCR = adcREG2->BNDCR; + config_reg->CONFIG_BNDEND = adcREG2->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG2->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG2->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG2->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG2->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG2->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG2->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG2->PARCR; + } +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c new file mode 100644 index 00000000000..2dbf833636c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c @@ -0,0 +1,1690 @@ +/** @file can.c + * @brief CAN Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "can.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Global and Static Variables */ + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) +#else +static const uint32 s_canByteOrder[ 8U ] = { 3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U }; +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void canInit(void) + * @brief Initializes CAN Driver + * + * This function initializes the CAN driver. + * + */ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +/* SourceId : CAN_SourceId_001 */ +/* DesignId : CAN_DesignId_001 */ +/* Requirements : CONQ_CAN_SR4 */ +void canInit( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG1->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG1->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG1->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG1->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG1->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG1->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG1->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN1 Port output values */ + canREG1->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG1->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG1->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN2: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG2->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG2->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG2->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG2->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG2->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG2->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG2->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG2->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN2 Port output values */ + canREG2->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG2->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG2->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN3: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG3->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG3->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG3->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + canREG3->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG3->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG3->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG3->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG3->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) ( uint32 ) 9U; + + /** - CAN3 Port output values */ + canREG3->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG3->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG3->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG4->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG4->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG4->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG4->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG4->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG4->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG4->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG4->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG4->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG4->BTR = ( ( uint32 ) 0U << 16U ) | ( ( ( uint32 ) 4U - 1U ) << 12U ) + | ( ( ( ( uint32 ) 6U + ( uint32 ) 4U ) - 1U ) << 8U ) + | ( ( ( uint32 ) 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN4 Port output values */ + canREG4->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG4->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + /** - Leave configuration and initialization mode */ + canREG4->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data) + * @brief Transmits a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of the TX message box wasn't successful + * - 1: When the setup of the TX message box was successful + * + * This function writes a CAN message into a CAN message box. + * + */ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_002 */ +/* DesignId : CAN_DesignId_002 */ +/* Requirements : CONQ_CAN_SR5 */ +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + * - Start Transmission + */ + node->IF1CMD = 0x87U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return: + * - 0: When RX message box hasn't received new data + * - 1: When RX data are stored in the data buffer + * - 3: When RX data are stored in the data buffer and a message was lost + * + * This function writes a CAN message into a CAN message box. + * + */ + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_003 */ +/* DesignId : CAN_DesignId_003 */ +/* Requirements : CONQ_CAN_SR6 */ +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ) +{ + uint32 i; + uint32 size; + uint8 * pData = data; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Check if new data have been arrived: + * - no new data, return 0 + * - new data, get received message + */ + if( ( node->NWDATx[ regIndex ] & bitIndex ) == 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF2 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x17U; + + /** - Copy data into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Get number of received bytes */ + size = node->IF2MCTL & 0xFU; + if( size > 0x8U ) + { + size = 0x8U; + } + /** - Copy RX data into destination buffer */ + for( i = 0U; i < size; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + pData++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ s_canByteOrder[ i ] ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + pData++; +#endif + } + + success = 1U; + } + /** - Check if data have been lost: + * - no data lost, return 1 + * - data lost, return 3 + */ + if( ( node->IF2MCTL & 0x4000U ) == 0x4000U ) + { + success = 3U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetID(canBASE_t *node, uint32 messageBox) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return the ID of the message box. + * + * This function gets the identifier of a CAN message box. + * + */ +/* SourceId : CAN_SourceId_026 */ +/* DesignId : CAN_DesignId_020 */ +/* Requirements : CONQ_CAN_SR39 */ +uint32 canGetID( canBASE_t * node, uint32 messageBox ) +{ + uint32 msgBoxID = 0U; + + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x20U; + + /** - Copy message box number into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /* Read Message Box ID from Arbitration register. */ + msgBoxID = ( node->IF2ARB & 0x1FFFFFFFU ); + + return msgBoxID; +} + +/** @fn uint32 canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal) +* @brief Gets received a CAN message +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* - canREG4: CAN4 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[in] msgBoxArbitVal (32 bit value): +* Bit 31 - Not used. +* Bit 30 - 0 - The 11-bit ("standard") identifier is used for this message +object. * 1 - The 29-bit ("extended") identifier is used for this +message object. * Bit 29 - 0 - Direction = Receive +* 1 - Direction = Transmit +* Bit 28:0 - Message Identifier. +* @return + +* +* This function changes the Identifier and other arbitration parameters of a CAN Message +Box. +* +*/ +/* SourceId : CAN_SourceId_027 */ +/* DesignId : CAN_DesignId_021 */ +/* Requirements : CONQ_CAN_SR40 */ +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ) +{ + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0xA0U; + /* Copy passed value into the arbitration register. */ + node->IF2ARB &= 0x80000000U; + node->IF2ARB |= ( msgBoxArbitVal & 0x7FFFFFFFU ); + + /** - Update message box number. */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ +} + +/** @fn uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox) + * @brief Transmits a CAN Remote Frame. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of Send Remote Frame from message box wasn't successful + * - 1: When the setup of Send Remote Frame from message box was successful + * + * This function triggers Remote Frame Transmission from CAN message box. + * Note : Enable RTR must be set in the Message x Configuration in the GUI( x: 1 - 64) + * + */ +/* SourceId : CAN_SourceId_028 */ +/* DesignId : CAN_DesignId_022 */ +/* Requirements : CONQ_CAN_SR23 */ +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ) +{ + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Request Transmission by setting TxRqst in message box */ + node->IF1CMD = ( uint8 ) 0x84U; + + /** - Trigger Remote Frame Transmit from message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + return success; +} + +/** @fn uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * + * data) + * @brief Fills the Message Object with the data but does not initiate transmission. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return: + * - 0: When the Fill up of the TX message box wasn't successful + * - 1: When the Fill up of the TX message box was successful + * + * This function fills the Message Object with the data but does not initiate + * transmission. + * + */ +/* SourceId : CAN_SourceId_029 */ +/* DesignId : CAN_DesignId_023 */ +/* Requirements : CONQ_CAN_SR24 */ +uint32 canFillMessageObjectData( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + */ + node->IF1CMD = 0x83U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + + return success; +} + +/** @fn uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox) + * @brief Gets Tx message box transmission status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the tx request flag + * + * Checks to see if the Tx message box has a pending Tx request, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_004 */ +/* DesignId : CAN_DesignId_004 */ +/* Requirements : CONQ_CAN_SR7 */ +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->TXRQx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox) + * @brief Gets Rx message box reception status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the Rx message box has pending Rx data, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_005 */ +/* DesignId : CAN_DesignId_005 */ +/* Requirements : CONQ_CAN_SR8 */ +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->NWDATx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox) + * @brief Checks if message box is valid + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the message box is valid for operation, returns + * 0 is flag not set otherwise will return the validation flag itself. + */ + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_006 */ +/* DesignId : CAN_DesignId_006 */ +/* Requirements : CONQ_CAN_SR9 */ +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->MSGVALx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canGetLastError(canBASE_t *node) + * @brief Gets last RX/TX-Error of CAN message traffic + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @return The function will return: + * - canERROR_OK (0): When no CAN error occurred + * - canERROR_STUFF (1): When a stuff error occurred on RX message + * - canERROR_FORMAT (2): When a form/format error occurred on RX message + * - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged + * - canERROR_BIT1 (4): When a TX message monitored dominant level where + * recessive is expected + * - canERROR_BIT0 (5): When a TX message monitored recessive level where + * dominant is expected + * - canERROR_CRC (6): When a RX message has wrong CRC value + * - canERROR_NO (7): When no error occurred since last call of this function + * + * This function returns the last occurred error code of an RX or TX message, + * since the last call of this function. + * + */ + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_007 */ +/* DesignId : CAN_DesignId_007 */ +/* Requirements : CONQ_CAN_SR10 */ +uint32 canGetLastError( canBASE_t * node ) +{ + uint32 errorCode; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Get last error code */ + errorCode = node->ES & 7U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return errorCode; +} + +/** @fn uint32 canGetErrorLevel(canBASE_t *node) + * @brief Gets error level of a CAN node + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @return The function will return: + * - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and + * 255 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * + * This function returns the current error level of a CAN node. + * + */ + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_008 */ +/* DesignId : CAN_DesignId_008 */ +/* Requirements : CONQ_CAN_SR11 */ +uint32 canGetErrorLevel( canBASE_t * node ) +{ + uint32 errorLevel; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + /** - Get error level */ + errorLevel = node->ES & 0xE0U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + return errorLevel; +} + +/** @fn void canEnableErrorNotification(canBASE_t *node) + * @brief Enable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will enable the notification for the reaching the error levels warning, + * passive and bus off. + */ + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_009 */ +/* DesignId : CAN_DesignId_009 */ +/* Requirements : CONQ_CAN_SR12 */ +void canEnableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + node->CTL |= 8U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + +/** @fn void canEnableStatusChangeNotification(canBASE_t *node) + * @brief Enable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will enable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_030 */ +/* DesignId : CAN_DesignId_024 */ +/* Requirements : CONQ_CAN_SR25 */ +void canEnableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL |= 4U; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableStatusChangeNotification(canBASE_t *node) + * @brief Disable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_031 */ +/* DesignId : CAN_DesignId_025 */ +/* Requirements : CONQ_CAN_SR26 */ +void canDisableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL &= ~( uint32 ) ( 4U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableErrorNotification(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable the notification for the reaching the error levels + * warning, passive and bus off. + */ + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_010 */ +/* DesignId : CAN_DesignId_010 */ +/* Requirements : CONQ_CAN_SR13 */ +void canDisableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + node->CTL &= ~( uint32 ) ( 8U ); + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] Loopbacktype Type of Loopback: + * - Internal_Lbk: Internal Loop Back + * - External_Lbk: External Loop Back + * - Internal_Silent_Lbk: Internal Loop Back with Silent mode. + * + * This function will enable can loopback mode + */ +/* SourceId : CAN_SourceId_011 */ +/* DesignId : CAN_DesignId_011 */ +/* Requirements : CONQ_CAN_SR21 */ +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ) +{ + /* Enter Test Mode */ + node->CTL |= ( uint32 ) ( ( uint32 ) 1U << 7U ); + + /* Configure Loopback */ + node->TEST |= ( uint32 ) Loopbacktype; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableloopback(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable can loopback mode + */ +/* SourceId : CAN_SourceId_012 */ +/* DesignId : CAN_DesignId_012 */ +/* Requirements : CONQ_CAN_SR22 */ +void canDisableloopback( canBASE_t * node ) +{ + node->TEST &= ~( uint32 ) ( 0x00000118U ); + + /* Exit Test Mode */ + node->CTL &= ~( uint32 ) ( ( uint32 ) 1U << 7U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir) + * @brief Set Port Direction + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] TxDir - TX Pin direction + * @param[in] RxDir - RX Pin direction + * + * Set the direction of CAN pins at runtime when configured as IO pins. + */ +/* SourceId : CAN_SourceId_013 */ +/* DesignId : CAN_DesignId_013 */ +/* Requirements : CONQ_CAN_SR14 */ +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ) +{ + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFBU ) | ( TxDir << 2U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFBU ) | ( RxDir << 2U ) ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue) + * @brief Write Port Value + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] TxValue - TX Pin value 0 or 1 + * @param[in] RxValue - RX Pin value 0 or 1 + * + * Writes a value to TX and RX pin of a given CAN module when configured as IO pins. + */ +/* SourceId : CAN_SourceId_014 */ +/* DesignId : CAN_DesignId_014 */ +/* Requirements : CONQ_CAN_SR15 */ +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFDU ) | ( TxValue << 1U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFDU ) | ( RxValue << 1U ) ); + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn uint32 canIoTxGetBit(canBASE_t *node) + * @brief Read TX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the TX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_015 */ +/* DesignId : CAN_DesignId_015 */ +/* Requirements : CONQ_CAN_SR16 */ +uint32 canIoTxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + return ( node->TIOC & 1U ); +} + +/** @fn uint32 canIoRxGetBit(canBASE_t *node) + * @brief Read RX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the RX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_016 */ +/* DesignId : CAN_DesignId_016 */ +/* Requirements : CONQ_CAN_SR17 */ +uint32 canIoRxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + + return ( node->RIOC & 1U ); +} + +/** @fn void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_017 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR27 */ +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN1_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN1_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN1_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN1_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN1_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN1_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN1_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN1_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN1_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG1->CTL; + config_reg->CONFIG_ES = canREG1->ES; + config_reg->CONFIG_BTR = canREG1->BTR; + config_reg->CONFIG_TEST = canREG1->TEST; + config_reg->CONFIG_ABOTR = canREG1->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG1->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG1->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG1->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG1->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG1->TIOC; + config_reg->CONFIG_RIOC = canREG1->RIOC; + } +} +/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_018 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR28 */ +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG2->CTL; + config_reg->CONFIG_ES = canREG2->ES; + config_reg->CONFIG_BTR = canREG2->BTR; + config_reg->CONFIG_TEST = canREG2->TEST; + config_reg->CONFIG_ABOTR = canREG2->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG2->TIOC; + config_reg->CONFIG_RIOC = canREG2->RIOC; + } +} +/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_019 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR29 */ +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG3->CTL; + config_reg->CONFIG_ES = canREG3->ES; + config_reg->CONFIG_BTR = canREG3->BTR; + config_reg->CONFIG_TEST = canREG3->TEST; + config_reg->CONFIG_ABOTR = canREG3->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG3->TIOC; + config_reg->CONFIG_RIOC = canREG3->RIOC; + } +} + +/** @fn void can4GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN4 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_032 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR30 */ +void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN4_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN4_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN4_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN4_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN4_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN4_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN4_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN4_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN4_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN4_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN4_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG4->CTL; + config_reg->CONFIG_ES = canREG4->ES; + config_reg->CONFIG_BTR = canREG4->BTR; + config_reg->CONFIG_TEST = canREG4->TEST; + config_reg->CONFIG_ABOTR = canREG4->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG4->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG4->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG4->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG4->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG4->TIOC; + config_reg->CONFIG_RIOC = canREG4->RIOC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c new file mode 100644 index 00000000000..b8ebcd958af --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c @@ -0,0 +1,652 @@ +/** @file crc.c + * @brief CRC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "crc.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void crcInit(void) + * @brief Initializes the crc Driver + * + * This function initializes the crc module. + */ +/* SourceId : CRC_SourceId_001 */ +/* DesignId : CRC_DesignId_001 */ +/* Requirements : CONQ_CRC_SR2 */ +void crcInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b CRC1 */ + /** - Reset PSA*/ + crcREG1->CTRL0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ); + + /** - Pulling PSA out of reset */ + crcREG1->CTRL0 = 0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG1->CTRL2 |= ( uint32 ) 0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG1->INTS = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG1->PCOUNT_REG1 = 0x00000000U; + crcREG1->PCOUNT_REG2 = 0x00000000U; + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG1->SCOUNT_REG1 = 0x00000000U; + crcREG1->SCOUNT_REG2 = 0x00000000U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG1->WDTOPLD1 = 0x00000000U; + crcREG1->WDTOPLD2 = 0x00000000U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG1->BCTOPLD1 = 0x00000000U; + crcREG1->BCTOPLD2 = 0x00000000U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG1->REGL1 = 0x00000000U; + crcREG1->REGL2 = 0x00000000U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG1->REGH1 = 0x00000000U; + crcREG1->REGH2 = 0x00000000U; + + /** - Setup the Channel mode */ + crcREG1->CTRL2 |= ( uint32 ) ( CRC_FULL_CPU ) + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ); + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b CRC2 */ + + /** - Reset PSA*/ + crcREG2->CTRL0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ); + + /** - Pulling PSA out of reset */ + crcREG2->CTRL0 = 0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG2->CTRL2 |= ( uint32 ) 0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG2->INTS = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG2->PCOUNT_REG1 = 0U; + crcREG2->PCOUNT_REG2 = 0U; + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG2->SCOUNT_REG1 = 0U; + crcREG2->SCOUNT_REG2 = 0U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG2->WDTOPLD1 = 0U; + crcREG2->WDTOPLD2 = 0U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG2->BCTOPLD1 = 0U; + crcREG2->BCTOPLD2 = 0U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG2->REGL1 = 0U; + crcREG2->REGL2 = 0U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG2->REGH1 = 0U; + crcREG2->REGH2 = 0U; + + /** - Setup the Channel mode */ + crcREG2->CTRL2 |= ( uint32 ) ( CRC_FULL_CPU ) + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void crcSendPowerDown(crcBASE_t *crc) + * @brief Send crc power down + * @param[in] crc - crc module base address + * + * Send crc power down signal to enter into sleep mode + */ +/* SourceId : CRC_SourceId_002 */ +/* DesignId : CRC_DesignId_002 */ +/* Requirements : CONQ_CRC_SR3 */ +void crcSendPowerDown( crcBASE_t * crc ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + crc->CTRL1 |= 0x00000001U; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/** @fn void crcSignGen(crcBASE_t *crc,crcModConfig_t *param) + * @brief set the mode specific parameters for signature generation + * @param[in] crc - crc module base address + * @param[in] param - structure holding mode specific parameters + * Generate CRC signature + */ +/* SourceId : CRC_SourceId_003 */ +/* DesignId : CRC_DesignId_003 */ +/* Requirements : CONQ_CRC_SR4 */ +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + uint32 i = 0U, psaSigx; + volatile uint64 *ptr64, *psaSigx_ptr64; + ptr64 = param->src_data_pat; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 439 S MR:11.3 "Pointer Manupulation required to find offset" + */ + psaSigx = ( uint32 ) ( &crc->PSA_SIGREGL1 ) + + ( ( uint32 ) ( param->crc_channel ) * 0x40U ); + psaSigx_ptr64 = ( uint64 * ) ( psaSigx ); + + if( param->mode == CRC_AUTO ) + { + /** -do a channel reset + * -clear all interrupts by reading offset register + * -set CRC FAIL interrupt + * -set the pattern count and sector count + * -HW trigger in AUTO mode for CRC register update + * -copy from memory location to CRC register using DMA + * -copy from memory to PSA signature register using DMA + * -frame or block transfer,auto init + * -compare with crc reference + * -do a channel reset + */ + } + else if( param->mode == CRC_SEMI_CPU ) + { + /* after DMA does the transfer,CPU is invoked by CC interrupt to do signature + * verification */ + } + else if( param->mode == CRC_FULL_CPU ) + { + for( i = 0U; i < param->data_length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *psaSigx_ptr64 = *ptr64; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr64++; + } + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + } + else + { + /* Empty */ + } +} + +/** @fn void crcSetConfig(crcBASE_t *crc,crcConfig_t *param) + * @brief Set crc configurations + * @param[in] crc - crc module base address + * @param[in] param - structure for channel configuration + * Set Channel parameters + */ +/* SourceId : CRC_SourceId_004 */ +/* DesignId : CRC_DesignId_004 */ +/* Requirements : CONQ_CRC_SR5 */ +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + switch( param->crc_channel ) + { + case 0U: + crc->CTRL2 &= 0xFFFFFFFCU; + crc->CTRL0 |= 0x00000001U; + crc->CTRL0 &= 0xFFFFFFFEU; + crc->PCOUNT_REG1 = param->pcount; + crc->SCOUNT_REG1 = param->scount; + crc->WDTOPLD1 = param->wdg_preload; + crc->BCTOPLD1 = param->block_preload; + crc->CTRL2 |= param->mode; + break; + case 1U: + crc->CTRL2 &= 0xFFFFFCFFU; + crc->CTRL0 |= 0x00000100U; + crc->CTRL0 &= 0xFFFFFEFFU; + crc->PCOUNT_REG2 = param->pcount; + crc->SCOUNT_REG2 = param->scount; + crc->WDTOPLD2 = param->wdg_preload; + crc->BCTOPLD2 = param->block_preload; + crc->CTRL2 |= ( uint32 ) ( ( uint32 ) param->mode << 8U ); + break; + default: + break; + } + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/** @fn uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel) + * @brief get genearted sector signature + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get Sector signature value of selected channel + */ +/* SourceId : CRC_SourceId_005 */ +/* DesignId : CRC_DesignId_006 */ +/* Requirements : CONQ_CRC_SR7 */ +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ) +{ + uint64 status = 0U; + uint32 CRC_PSA_SECSIGREGH1 = crc->PSA_SECSIGREGH1; + uint32 CRC_PSA_SECSIGREGL1 = crc->PSA_SECSIGREGL1; + uint32 CRC_PSA_SECSIGREGH2 = crc->PSA_SECSIGREGH2; + uint32 CRC_PSA_SECSIGREGL2 = crc->PSA_SECSIGREGL2; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + switch( channel ) + { + case 0U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SECSIGREGL1 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SECSIGREGH1 ) ); + break; + case 1U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SECSIGREGL2 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SECSIGREGH2 ) ); + break; + default: + break; + } + return status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel) + * @brief get failed sector details + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get Failed Sector value of selected channel + */ +/* SourceId : CRC_SourceId_006 */ +/* DesignId : CRC_DesignId_007 */ +/* Requirements : CONQ_CRC_SR8 */ +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ) +{ + uint32 sector = 0U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + switch( channel ) + { + case 0U: + sector = crc->CURSEC_REG1; + break; + case 1U: + sector = crc->CURSEC_REG2; + break; + default: + break; + } + return sector; + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel) + * @brief get highest priority interrupt pending + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * + * Get pending Interrupts of selected channel + */ +/* SourceId : CRC_SourceId_007 */ +/* DesignId : CRC_DesignId_008 */ +/* Requirements : CONQ_CRC_SR9 */ +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + return crc->INT_OFFSET_REG; + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void crcChannelReset(crcBASE_t *crc,uint32 channel) + * @brief Reset the channel configurations + * @param[in] crc - crc module base address + * @param[in] channel-crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Reset configurations of the selected channels. + */ +/* SourceId : CRC_SourceId_008 */ +/* DesignId : CRC_DesignId_009 */ +/* Requirements : CONQ_CRC_SR10 */ +void crcChannelReset( crcBASE_t * crc, uint32 channel ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( channel == 0U ) + { + crc->CTRL0 |= ( uint32 ) ( ( uint32 ) 1U << 0U ); /** Reset the CRC channel */ + crc->CTRL0 &= ~( uint32 ) ( ( uint32 ) 1U << 0U ); /** Exit the reset */ + } + else if( channel == 1U ) + { + crc->CTRL0 |= ( uint32 ) ( ( uint32 ) 1U << 8U ); /** Reset the CRC channel */ + crc->CTRL0 &= ~( uint32 ) ( ( uint32 ) 1U << 8U ); /** Exit the reset */ + } + else + { + /** Empty */ + } + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn crcEnableNotification(crcBASE_t *crc, uint32 flags) + * @brief Enable interrupts + * @param[in] crc - crc module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * CRC_CH2_TO - channel3 timeout error, + * CRC_CH2_UR - channel3 underrun error, + * CRC_CH2_OR - channel3 overrun error, + * CRC_CH2_FAIL - channel3 crc error, + * CRC_CH2_CC - channel3 compression complete interrupt , + * CRC_CH1_TO - channel4 timeout error, + * CRC_CH1_UR - channel4 underrun error, + * CRC_CH1_OR - channel4 overrun error, + * CRC_CH1_FAIL - channel4 crc error, + * CRC_CH1_CC - channel4 compression complete interrupt + * + * Enable Notifications / Interrupts + */ +/* SourceId : CRC_SourceId_009 */ +/* DesignId : CRC_DesignId_010 */ +/* Requirements : CONQ_CRC_SR11 */ +void crcEnableNotification( crcBASE_t * crc, uint32 flags ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + crc->INTS = flags; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn crcDisableNotification(crcBASE_t *crc, uint32 flags) + * @brief Disable interrupts + * @param[in] crc - crc module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * CRC_CH2_TO - channel3 timeout error, + * CRC_CH2_UR - channel3 underrun error, + * CRC_CH2_OR - channel3 overrun error, + * CRC_CH2_FAIL - channel3 crc error, + * CRC_CH2_CC - channel3 compression complete interrupt , + * CRC_CH1_TO - channel4 timeout error, + * CRC_CH1_UR - channel4 underrun error, + * CRC_CH1_OR - channel4 overrun error, + * CRC_CH1_FAIL - channel4 crc error, + * CRC_CH1_CC - channel4 compression complete interrupt + * + * Disable Notifications / Interrupts + */ +/* SourceId : CRC_SourceId_010 */ +/* DesignId : CRC_DesignId_011 */ +/* Requirements : CONQ_CRC_SR12 */ +void crcDisableNotification( crcBASE_t * crc, uint32 flags ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + crc->INTR = flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetPSASig(crcBASE_t *crc,uint32 channel) + * @brief get genearted PSA signature used for FULL CPU mode + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get PSA signature used for FULL CPU mode of selected channel + */ +/* SourceId : CRC_SourceId_011 */ +/* DesignId : CRC_DesignId_005 */ +/* Requirements : CONQ_CRC_SR6 */ +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ) +{ + uint64 status = 0U; + uint32 CRC_PSA_SIGREGH1 = crc->PSA_SIGREGH1; + uint32 CRC_PSA_SIGREGL1 = crc->PSA_SIGREGL1; + uint32 CRC_PSA_SIGREGH2 = crc->PSA_SIGREGH2; + uint32 CRC_PSA_SIGREGL2 = crc->PSA_SIGREGL2; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + switch( channel ) + { + case 0U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SIGREGL1 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SIGREGH1 ) ); + break; + case 1U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SIGREGL2 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SIGREGH2 ) ); + break; + default: + break; + } + return status; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void crc1GetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CRC1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CRC_SourceId_012 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements : CONQ_CRC_SR15 */ +void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRL0 = CRC1_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC1_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC1_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC1_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC1_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC1_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC1_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC1_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC1_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC1_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC1_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC1_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTRL0 = crcREG1->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG1->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG1->CTRL2; + config_reg->CONFIG_INTS = crcREG1->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG1->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG1->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG1->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG1->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG1->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG1->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG1->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG1->BCTOPLD2; + } +} + +/** @fn void crc2GetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CRC2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CRC_SourceId_013 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements : CONQ_CRC_SR15 */ +void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRL0 = CRC2_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC2_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC2_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC2_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC2_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC2_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC2_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC2_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC2_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC2_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC2_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC2_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTRL0 = crcREG2->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG2->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG2->CTRL2; + config_reg->CONFIG_INTS = crcREG2->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG2->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG2->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG2->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG2->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG2->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG2->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG2->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG2->BCTOPLD2; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S new file mode 100644 index 00000000000..03969b31d23 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S @@ -0,0 +1,164 @@ +/*-------------------------------------------------------------------------- + dabort.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +--------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + + +/*-------------------------------------------------------------------------------*/ +@ Run Memory Test + + .extern custom_dabort + .extern vHandleMemoryFault + .weak _dabort + .type _dabort, %function + +_dabort: + stmfd r13!, {r0 - r12, lr}@ push registers and link register on to stack + ldr r12, esmsr3 @ ESM Group3 status register + ldr r0, [r12] + tst r0, #0x8 @ check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM + bne ramErrorFound + tst r0, #0x20 @ check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM + bne ramErrorFound2 + +noRAMerror: + tst r0, #0x80 @ check if bit 7 is set, this indicates uncorrectable ECC error on ATCM + bne flashErrorFound + +/* Create a Exception Fault Stack similiar to the way it is created by the ARMvM + * architecture. The auto-pushed exception stack will contain: + * +-------+-----+----------+----------+------+ + * | R0-R3 | R12 | LR (R14) | PC (R15) | CPSR | + * +-------+-----+----------+----------+------+ + * + * <-------><----><---------><---------><-----> + * 4 1 1 1 1 +*/ +MemManage_Handler: + /* Pop the pushed values so we can re-do the stack the way we need it to be */ + LDMFD R13!, {R0 - R12, LR} + /* Abort exceptions increment the LR 0x8 after the fault-inducing instruction */ + SUB LR, #0x8 + + SRSDB SP!, #0x17 /* Save the pre-exception PC and CPSR */ + STMDB SP, { R0-R3, R12, LR }^ /* Save the user R0-R3, R12, and LR */ + SUB SP, SP, #0x18 /* Can't auto-increment SP with ^ operator */ + /* Need the SP in R0 */ + MOV R0, SP + + POP { R0-R3, R12, LR } /* Pop the original values off the stack */ + /* Return to the next instruction after the fault was generated */ + RFEIA SP! + +ramErrorFound: + ldr r1, ramctrl @ RAM control register for B0TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x08 + str r2, [r12] @ clear ESM group3 channel3 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + +ramErrorFound2: + ldr r1, ram2ctrl @ RAM control register for B1TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x20 + str r2, [r12] @ clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +ramErrorReal: + b ramErrorReal @ branch here forever as continuing operation is not recommended + +flashErrorFound: + ldr r1, flashbase + ldr r2, [r1, #0x6C] @ read FDIAGCTRL register + + mov r2, r2, lsr #16 + tst r2, #5 @ check if bits 19:16 are 5, this indicates diagnostic mode is enabled + beq flashErrorReal + mov r2, #1 + mov r2, r2, lsl #8 + + str r2, [r1, #0x1C] @ clear FEDACSTATUS error flag + + mov r2, #0x80 + str r2, [r12] @ clear ESM group3 flag for uncorrectable flash ECC error + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +flashErrorReal: + b flashErrorReal @ branch here forever as continuing operation is not recommended + +esmsr3: .word 0xFFFFF520 +ramctrl: .word 0xFFFFF800 +ram2ctrl: .word 0xFFFFF900 +ram1errstat: .word 0xFFFFF810 +ram2errstat: .word 0xFFFFF910 +flashbase: .word 0xFFF87000 + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c new file mode 100644 index 00000000000..4498fab0615 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c @@ -0,0 +1,455 @@ +/** @file dcc.c + * @brief DCC Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "dcc.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : DCC_SourceId_001 */ +/* DesignId : DCC_DesignId_001 */ +/* Requirements : CONQ_DCC_SR4 */ +/** @fn void dccInit(void) + * @brief Initializes the DCC Driver + * + * This function initializes the DCC module. + */ +void dccInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b DCC1 */ + + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 39204U; + + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 792U; + + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 742500U; + + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) DCC1_CNT1_PLL1; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable / Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0xAU << 4U ) | /** Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0xAU << 12U ); /** Done Interrupt */ + + /** @b initialize @b DCC2 */ + + /** DCC2 Clock0 Counter Seed value configuration */ + dccREG2->CNT0SEED = 0U; + + /** DCC2 Clock0 Valid Counter Seed value configuration */ + dccREG2->VALID0SEED = 0U; + + /** DCC2 Clock1 Counter Seed value configuration */ + dccREG2->CNT1SEED = 0U; + + /** DCC2 Clock1 Source 1 Select */ + dccREG2->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | /** DCC Enable Key */ + ( uint32 ) DCC2_CNT1_VCLK; /** DCC2 Clock Source 1 */ + + dccREG2->CNT0CLKSRC = ( uint32 ) DCC2_CNT0_OSCIN; /** DCC2 Clock Source 0 */ + + /** DCC2 Global Control register configuration */ + dccREG2->GCTRL = ( uint32 ) 0xAU | /** Enable DCC2 */ + ( uint32 ) ( ( uint32 ) 0xAU << 4U ) | /** Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0xAU << 12U ); /** Done Interrupt */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_002 */ +/* DesignId : DCC_DesignId_002 */ +/* Requirements : CONQ_DCC_SR5 */ +/** @fn void dccSetCounter0Seed(dccBASE_t *dcc, uint32 cnt0seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0seed - Clock Source 0 Counter seed value + * + * This function sets the seed value for Clock source 0 counter. + * + */ +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + dcc->CNT0SEED = cnt0seed; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_003 */ +/* DesignId : DCC_DesignId_003 */ +/* Requirements : CONQ_DCC_SR6 */ +/** @fn void dccSetTolerance(dccBASE_t *dcc, uint32 valid0seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] valid0seed - Clock Source 0 Counter tolerance value + * + * This function sets the seed value for Clock source 0 tolerance or + * valid counter. + * + */ +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + dcc->VALID0SEED = valid0seed; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_004 */ +/* DesignId : DCC_DesignId_004 */ +/* Requirements : CONQ_DCC_SR7 */ +/** @fn void dccSetCounter1Seed(dccBASE_t *dcc, uint32 cnt1seed) + * @brief Set dcc Clock source 1 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt1seed - Clock Source 1 Counter seed value + * + * This function sets the seed value for Clock source 1 counter. + * + */ +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + dcc->CNT1SEED = cnt1seed; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_005 */ +/* DesignId : DCC_DesignId_005 */ +/* Requirements : CONQ_DCC_SR8 */ +/** @fn void dccSetSeed(dccBASE_t *dcc, uint32 cnt0seed, uint32 valid0seed, uint32 + * cnt1seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0seed - Clock Source 0 Counter seed value. + * @param[in] valid0seed - Clock Source 0 Counter tolerance value. + * @param[in] cnt1seed - Clock Source 1 Counter seed value. + * + * This function sets the seed value for clock source 0, clock source 1 + * and tolerance counter. + * + */ +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + dcc->CNT0SEED = cnt0seed; + dcc->VALID0SEED = valid0seed; + dcc->CNT1SEED = cnt1seed; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_006 */ +/* DesignId : DCC_DesignId_006 */ +/* Requirements : CONQ_DCC_SR9 */ +/** @fn void dccSelectClockSource(dccBASE_t *dcc, uint32 cnt0_Clock_Source, uint32 + * cnt1_Clock_Source) + * @brief Set dcc counter Clock sources + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0_Clock_Source - Clock source for counter 0. + * @param[in] cnt1_Clock_Source - Clock source for counter 1. + * + * This function sets the dcc counter 0 and counter 1 clock sources. + * DCC must be disabled using dccDisable API before calling this + * function. + */ +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + dcc->CNT1CLKSRC = ( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | /** DCC Enable Key */ + ( uint32 ) ( cnt1_Clock_Source + & 0x0000000FU ) ); /* Configure Clock source 1 */ + dcc->CNT0CLKSRC = cnt0_Clock_Source; /* Configure Clock source 0 */ + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_007 */ +/* DesignId : DCC_DesignId_007 */ +/* Requirements : CONQ_DCC_SR10 */ +/** @fn void dccEnable(dccBASE_t *dcc) + * @brief Enable dcc module to begin counting + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * This function enables the dcc counters to begin counting. + * + */ +void dccEnable( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( dcc->GCTRL & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_008 */ +/* DesignId : DCC_DesignId_008 */ +/* Requirements : CONQ_DCC_SR21 */ +/** @fn void dccDisable(dccBASE_t *dcc) + * @brief Make selected dcc module to stop counting + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * This function stops the dcc counters from counting. + * + */ +void dccDisable( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( dcc->GCTRL & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_009 */ +/* DesignId : DCC_DesignId_009 */ +/* Requirements : CONQ_DCC_SR12 */ +/** @fn uint32 dccGetErrStatus(dccBASE_t *dcc) + * @brief Get error status from selected dcc module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * @return The Error status of selected dcc module + * + * Returns the error status of selected dcc module. + * + */ +uint32 dccGetErrStatus( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + return ( dcc->STAT & 0x00000001U ); +} + +/* SourceId : DCC_SourceId_010 */ +/* DesignId : DCC_DesignId_010 */ +/* Requirements : CONQ_DCC_SR13 */ +/** @fn void dccEnableNotification(dccBASE_t *dcc, uint32 notification) + * @brief Enable notification of selected DCC module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] notification Select notification of DCC module: + * - dccNOTIFICATION_DONE: DCC DONE notification + * - dccNOTIFICATION_ERROR: DCC ERROR notification + * + * This function will enable the selected notification of a DCC module. + * It is possible to enable multiple notifications masked. + */ + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( ( dcc->GCTRL & 0xFFFF0F0FU ) | notification ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_011 */ +/* DesignId : DCC_DesignId_011 */ +/* Requirements : CONQ_DCC_SR14 */ +/** @fn void dccDisableNotification(dccBASE_t *dcc, uint32 notification) + * @brief Disable notification of selected DCC module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] notification Select notification of DCC module: + * - dccNOTIFICATION_DONE: DCC DONE notification + * - dccNOTIFICATION_ERROR: DCC ERROR notification + * + * This function will enable the selected notification of a DCC module. + * It is possible to enable multiple notifications masked. + */ + +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( ( dcc->GCTRL & 0xFFFF0F0FU ) | ( ( ~notification ) & 0x0000F0F0U ) ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_012 */ +/* DesignId : DCC_DesignId_012 */ +/* Requirements : CONQ_DCC_SR18 */ +/** @fn void dcc1GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCTRL = DCC1_GCTRL_CONFIGVALUE; + config_reg->CONFIG_CNT0SEED = DCC1_CNT0SEED_CONFIGVALUE; + config_reg->CONFIG_VALID0SEED = DCC1_VALID0SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1SEED = DCC1_CNT1SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1CLKSRC = DCC1_CNT1CLKSRC_CONFIGVALUE; + config_reg->CONFIG_CNT0CLKSRC = DCC1_CNT0CLKSRC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + config_reg->CONFIG_GCTRL = dccREG1->GCTRL; + config_reg->CONFIG_CNT0SEED = dccREG1->CNT0SEED; + config_reg->CONFIG_VALID0SEED = dccREG1->VALID0SEED; + config_reg->CONFIG_CNT1SEED = dccREG1->CNT1SEED; + config_reg->CONFIG_CNT1CLKSRC = dccREG1->CNT1CLKSRC; + config_reg->CONFIG_CNT0CLKSRC = dccREG1->CNT0CLKSRC; + } +} + +/* SourceId : DCC_SourceId_013 */ +/* DesignId : DCC_DesignId_012 */ +/* Requirements : CONQ_DCC_SR19 */ +/** @fn void dcc2GetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCTRL = DCC2_GCTRL_CONFIGVALUE; + config_reg->CONFIG_CNT0SEED = DCC2_CNT0SEED_CONFIGVALUE; + config_reg->CONFIG_VALID0SEED = DCC2_VALID0SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1SEED = DCC2_CNT1SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1CLKSRC = DCC2_CNT1CLKSRC_CONFIGVALUE; + config_reg->CONFIG_CNT0CLKSRC = DCC2_CNT0CLKSRC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + config_reg->CONFIG_GCTRL = dccREG2->GCTRL; + config_reg->CONFIG_CNT0SEED = dccREG2->CNT0SEED; + config_reg->CONFIG_VALID0SEED = dccREG2->VALID0SEED; + config_reg->CONFIG_CNT1SEED = dccREG2->CNT1SEED; + config_reg->CONFIG_CNT1CLKSRC = dccREG2->CNT1CLKSRC; + config_reg->CONFIG_CNT0CLKSRC = dccREG2->CNT0CLKSRC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c new file mode 100644 index 00000000000..b5507af5a21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c @@ -0,0 +1,1062 @@ +/** @file ecap.c + * @brief ECAP Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "ecap.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void ecapInit(void) + * @brief Initializes the eCAP Driver + * + * This function initializes the eCAP module. + */ +/* SourceId : ECAP_SourceId_001 */ +/* DesignId : ECAP_DesignId_001 */ +/* Requirements : CONQ_ECAP_SR2 */ +void ecapInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** @b initialize @b ECAP1 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG1 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG1->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG1->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP2 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG2 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG2->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG2->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP3 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG3 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG3->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG3->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP4 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG4 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG4->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG4->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP5 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG5 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG5->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG5->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP6 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG6 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG6->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG6->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ +} + +/** @fn void ecapSetCounter(ecapBASE_t *ecap, uint32 value) + * @brief Set Time-Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] value 16-bit Counter value + * + * This function sets the Time-Stamp Counter register + */ +/* SourceId : ECAP_SourceId_002 */ +/* DesignId : ECAP_DesignId_002 */ +/* Requirements : CONQ_ECAP_SR3 */ +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ) +{ + ecap->TSCTR = value; +} + +/** @fn void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase) + * @brief Enable counter register load from phase register when a sync event occurs + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] phase Counter value to be loaded when a sync event occurs + * + * This function enables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_003 */ +/* DesignId : ECAP_DesignId_003 */ +/* Requirements : CONQ_ECAP_SR6 */ +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ) +{ + ecap->ECCTL2 |= 0x0020U; + ecap->CTRPHS = phase; +} + +/** @fn void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap) + * @brief Disable counter register load from phase register when a sync event occurs + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_004 */ +/* DesignId : ECAP_DesignId_004 */ +/* Requirements : CONQ_ECAP_SR7 */ +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0020U; +} + +/** @fn void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale) + * @brief Set Event prescaler + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] prescale Event Filter prescale select + * (ecapPrescale_By_1..ecapPrescale_By_62) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_005 */ +/* DesignId : ECAP_DesignId_005 */ +/* Requirements : CONQ_ECAP_SR8 */ +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) 0x3E00U; + ecap->ECCTL1 |= ( uint16 ) prescale; +} + +/** @fn void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 1 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 1 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 1 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 1 + */ +/* SourceId : ECAP_SourceId_006 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 0U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 0U ); +} + +/** @fn void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 2 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 2 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 2 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 2 + */ +/* SourceId : ECAP_SourceId_007 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 2U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 2U ); +} + +/** @fn void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 3 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 3 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 3 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 3 + */ +/* SourceId : ECAP_SourceId_008 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 4U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 4U ); +} + +/** @fn void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 4 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 4 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 4 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 4 + */ +/* SourceId : ECAP_SourceId_009 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 6U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 6U ); +} + +/** @fn void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t mode, ecapEvent_t event) + * @brief Set Capture mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] capMode Capture mode + * - CONTINUOUS + * - ONE_SHOT + * @param[in] event Stop/Wrap value + * - CAPTURE_EVENT1: Stop after Capture Event 1 in one-shot mode / + * Wrap after Capture Event 1 in continuous mode + * - CAPTURE_EVENT2: Stop after Capture Event 2 in one-shot mode / + * Wrap after Capture Event 2 in continuous mode. + * - CAPTURE_EVENT3: Stop after Capture Event 3 in one-shot mode / + * Wrap after Capture Event 3 in continuous mode. + * - CAPTURE_EVENT4: Stop after Capture Event 4 in one-shot mode / + * Wrap after Capture Event 4 in continuous mode. + * + * This function sets the capture mode and stop/wrap value + */ +/* SourceId : ECAP_SourceId_010 */ +/* DesignId : ECAP_DesignId_007 */ +/* Requirements : CONQ_ECAP_SR10 */ +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ) +{ + ecap->ECCTL2 &= 0xFFF8U; + ecap->ECCTL2 |= ( ( uint16 ) ( ( uint16 ) event << 1U ) | ( uint16 ) capMode ); +} + +/** @fn void ecapEnableCapture(ecapBASE_t *ecap) + * @brief Enable Capture + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function enable loading of CAP1-4 registers on a capture event + */ +/* SourceId : ECAP_SourceId_011 */ +/* DesignId : ECAP_DesignId_008 */ +/* Requirements : CONQ_ECAP_SR11 */ +void ecapEnableCapture( ecapBASE_t * ecap ) +{ + ecap->ECCTL1 |= 0x0100U; +} + +/** @fn void ecapDisableCapture(ecapBASE_t *ecap) + * @brief Disable Capture + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disable loading of CAP1-4 registers on a capture event + */ +/* SourceId : ECAP_SourceId_012 */ +/* DesignId : ECAP_DesignId_009 */ +/* Requirements : CONQ_ECAP_SR12 */ +void ecapDisableCapture( ecapBASE_t * ecap ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) 0x0100U; +} + +/** @fn void ecapStartCounter(ecapBASE_t *ecap) + * @brief Start Time Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function starts Time Stamp Counter + */ +/* SourceId : ECAP_SourceId_013 */ +/* DesignId : ECAP_DesignId_010 */ +/* Requirements : CONQ_ECAP_SR4 */ +void ecapStartCounter( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 |= 0x0010U; +} + +/** @fn void ecapStopCounter(ecapBASE_t *ecap)) + * @brief Stop Time Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function stops Time Stamp Counter + */ +/* SourceId : ECAP_SourceId_014 */ +/* DesignId : ECAP_DesignId_011 */ +/* Requirements : CONQ_ECAP_SR5 */ +void ecapStopCounter( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0010U; +} + +/** @fn void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc) + * @brief Set the source of Sync-out signal + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] syncOutSrc Sync-Out Select + * - SyncOut_SyncIn: Sync In used for Sync Out + * - SyncOut_CTRPRD: CTR = PRD used for Sync Out + * - SyncOut_None : Disables Sync Out + * + * This function sets the source of Sync-out signal + */ +/* SourceId : ECAP_SourceId_015 */ +/* DesignId : ECAP_DesignId_012 */ +/* Requirements : CONQ_ECAP_SR13 */ +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x00C0U; + ecap->ECCTL2 |= syncOutSrc; +} + +/** @fn void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint16 + * period, uint16 duty) + * @brief Enable APWM mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] pwmPolarity APWM output polarity select + * - ACTIVE_HIGH + * - ACTIVE_LOW + * @param[in] period APWM period (in terms of ticks) + * @param[in] duty APWM duty (in terms of ticks) + * + * This function enables and sets APWM mode + */ +/* SourceId : ECAP_SourceId_016 */ +/* DesignId : ECAP_DesignId_013 */ +/* Requirements : CONQ_ECAP_SR14 */ +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0400U; + ecap->ECCTL2 |= ( uint16 ) ( ( uint16 ) pwmPolarity << 10U ) + | ( uint16 ) ( ( uint16 ) 1U << 9U ); + ecap->CAP1 = period - 1U; + ecap->CAP2 = duty; +} + +/** @fn void ecapDisableAPWMMode(ecapBASE_t *ecap) + * @brief Disable APWM mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disables APWM mode + */ +/* SourceId : ECAP_SourceId_017 */ +/* DesignId : ECAP_DesignId_014 */ +/* Requirements : CONQ_ECAP_SR15 */ +void ecapDisableAPWMMode( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0200U; +} + +/** @fn void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) + * @brief Enable eCAP interrupt sources + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] interrupts eCAP interrupt sources + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function enables eCAP interrupt sources + */ +/* SourceId : ECAP_SourceId_018 */ +/* DesignId : ECAP_DesignId_015 */ +/* Requirements : CONQ_ECAP_SR16 */ +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ) +{ + ecap->ECEINT |= interrupts; +} + +/** @fn void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) + * @brief Disables eCAP interrupt sources + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] interrupts eCAP interrupt sources + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function disables eCAP interrupt sources + */ +/* SourceId : ECAP_SourceId_019 */ +/* DesignId : ECAP_DesignId_016 */ +/* Requirements : CONQ_ECAP_SR17 */ +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ) +{ + ecap->ECEINT &= ( uint16 ) ~( uint16 ) interrupts; +} + +/** @fn uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events) + * @brief Return Event status + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] events eCAP events + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_Global : Denotes Capture global interrupt + * - ecapInt_All : Denotes All interrupts + * @return Event status + * + * This function returns the event status + */ +/* SourceId : ECAP_SourceId_020 */ +/* DesignId : ECAP_DesignId_017 */ +/* Requirements : CONQ_ECAP_SR18 */ +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ) +{ + return ( ecap->ECFLG & events ); +} + +/** @fn void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events) + * @brief Clear Event status + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] events eCAP events + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_Global : Denotes Capture global interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function clears the event status + */ +/* SourceId : ECAP_SourceId_021 */ +/* DesignId : ECAP_DesignId_018 */ +/* Requirements : CONQ_ECAP_SR19 */ +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ) +{ + ecap->ECCLR = events; +} + +/** @fn void uint32 ecapGetCAP1(ecapBASE_t *ecap) + * @brief Get CAP1 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 1 value + */ +/* SourceId : ECAP_SourceId_022 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP1( ecapBASE_t * ecap ) +{ + return ecap->CAP1; +} + +/** @fn void uint32 ecapGetCAP2(ecapBASE_t *ecap) + * @brief Get CAP2 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 2 value + */ +/* SourceId : ECAP_SourceId_023 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP2( ecapBASE_t * ecap ) +{ + return ecap->CAP2; +} + +/** @fn void uint32 ecapGetCAP3(ecapBASE_t *ecap) + * @brief Get CAP3 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 3 value + */ +/* SourceId : ECAP_SourceId_024 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP3( ecapBASE_t * ecap ) +{ + return ecap->CAP3; +} + +/** @fn void uint32 ecapGetCAP4(ecapBASE_t *ecap) + * @brief Get CAP4 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 4 value + */ +/* SourceId : ECAP_SourceId_025 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP4( ecapBASE_t * ecap ) +{ + return ecap->CAP4; +} + +/** @fn void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_026 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP1_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP1_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP1_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP1_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG1->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG1->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG1->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG1->ECEINT; + } +} + +/** @fn void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_027 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP2_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP2_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP2_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP2_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG2->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG2->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG2->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG2->ECEINT; + } +} + +/** @fn void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_028 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP3_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP3_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP3_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP3_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG3->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG3->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG3->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG3->ECEINT; + } +} + +/** @fn void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_029 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP4_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP4_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP4_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP4_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG4->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG4->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG4->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG4->ECEINT; + } +} + +/** @fn void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_030 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP5_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP5_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP5_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP5_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG5->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG5->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG5->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG5->ECEINT; + } +} + +/** @fn void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_031 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP6_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP6_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP6_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP6_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG6->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG6->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG6->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG6->ECEINT; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c new file mode 100644 index 00000000000..fb35e4511fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c @@ -0,0 +1,1965 @@ +/** + * \file emac.c + * + * \brief EMAC APIs. + * + * This file contains the device abstraction layer APIs for EMAC. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emac.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Defining interface for all the emac instances */ +hdkif_t hdkif_data[ MAX_EMAC_INSTANCE ]; +/*SAFETYMCUSW 25 D MR:8.7 "Statically allocated memory needs to be available to + * entire application." */ +static uint8_t pbuf_array[ MAX_RX_PBUF_ALLOC ][ MAX_TRANSFER_UNIT ]; +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define EMAC_CONTROL_RESET ( 0x01U ) +#define EMAC_SOFT_RESET ( 0x01U ) +#define EMAC_MAX_HEADER_DESC ( 8U ) +#define EMAC_UNICAST_DISABLE ( 0xFFU ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Enables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_001 */ +/* DesignId : ETH_DesignId_001*/ +/* Requirements : CONQ_EMAC_SR9 */ +void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_TXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnTXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_002 */ +/* DesignId : ETH_DesignId_002*/ +/* Requirements : CONQ_EMAC_SR10 */ +void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnTXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Enables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be enabled. + * \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_003 */ +/* DesignId : ETH_DesignId_003*/ +/* Requirements : CONQ_EMAC_SR11 */ +void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnRXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be disabled. + * \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_004 */ +/* DesignId : ETH_DesignId_004*/ +/* Requirements : CONQ_EMAC_SR12 */ +void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnRXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} +/** + * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or + * 100 Mbps + * + * \param emacBase Base address of the EMAC Module registers. + * \param speed speed for setting. + * speed can take the following values. \n + * EMAC_RMIISPEED_10MBPS - 10 Mbps \n + * EMAC_RMIISPEED_100MBPS - 100 Mbps. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_005 */ +/* DesignId : ETH_DesignId_005*/ +/* Requirements : CONQ_EMAC_SR23 */ +void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RMIISPEED ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= speed; +} +/* SourceId : ETH_SourceId_006 */ +/* DesignId : ETH_DesignId_006*/ +/* Requirements : CONQ_EMAC_SR21 */ +/** + * \brief This API set the GMII bit, RX and TX are enabled for receive and transmit. + * Note: This is not the API to enable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +void EMACMIIEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_GMIIEN; +} + +/** + * \brief This API clears the GMII bit, Rx and Tx are held in reset. + * Note: This is not the API to disable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_007 */ +/* DesignId : ETH_DesignId_007*/ +/* Requirements : CONQ_EMAC_SR22 */ +void EMACMIIDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); +} + +/** + * \brief This API sets the duplex mode of operation(full/half) for MAC. + * + * \param emacBase Base address of the EMAC Module registers. + * \param duplexMode duplex mode of operation. + * duplexMode can take the following values. \n + * EMAC_DUPLEX_FULL - Full Duplex \n + * EMAC_DUPLEX_HALF - Half Duplex. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_008 */ +/* DesignId : ETH_DesignId_008*/ +/* Requirements : CONQ_EMAC_SR29 */ +void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_FULLDUPLEX ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= duplexMode; +} + +/** + * \brief API to enable the transmit in the TX Control Register + * After the transmit is enabled, any write to TXHDP of + * a channel will start transmission + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_009 */ +/* DesignId : ETH_DesignId_009*/ +/* Requirements : CONQ_EMAC_SR30 */ +void EMACTxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXEN; +} + +/** + * \brief API to disable the transmit in the TX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_010 */ +/* DesignId : ETH_DesignId_010*/ +/* Requirements : CONQ_EMAC_SR31 */ +void EMACTxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXDIS; +} + +/** + * \brief API to enable the receive in the RX Control Register + * After the receive is enabled, and write to RXHDP of + * a channel, the data can be received in the destination + * specified by the corresponding RX buffer descriptor. + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_011*/ +/* DesignId : ETH_DesignId_011*/ +/* Requirements : CONQ_EMAC_SR32 */ +void EMACRxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXEN; +} + +/** + * \brief API to disable the receive in the RX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_012*/ +/* DesignId : ETH_DesignId_012*/ +/* Requirements : CONQ_EMAC_SR33 */ +void EMACRxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXDIS; +} + +/** + * \brief API to write the TX HDP register. If transmit is enabled, + * write to the TX HDP will immediately start transmission. + * The data will be taken from the buffer pointer of the TX buffer + * descriptor written to the TX HDP + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the TX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_013*/ +/* DesignId : ETH_DesignId_013*/ +/* Requirements : CONQ_EMAC_SR17 */ +void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXHDP( channel ) ) = descHdr; +} + +/** + * \brief API to write the RX HDP register. If receive is enabled, + * write to the RX HDP will enable data reception to point to + * the corresponding RX buffer descriptor's buffer pointer. + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the RX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_014 */ +/* DesignId : ETH_DesignId_014*/ +/* Requirements : CONQ_EMAC_SR18 */ +void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXHDP( channel ) ) = descHdr; +} + +/** + * \brief This API Initializes the EMAC and EMAC Control modules. The + * EMAC Control module is reset, the CPPI RAM is cleared. also, + * all the interrupts are disabled. This API does not enable any + * interrupt or operation of the EMAC. + * + * \param emacCtrlBase Base Address of the EMAC Control module + * registers.\n + * \param emacBase Base address of the EMAC module registers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_015 */ +/* DesignId : ETH_DesignId_015*/ +/* Requirements : CONQ_EMAC_SR1 */ +void EMACInit( uint32 emacCtrlBase, uint32 emacBase ) +{ + uint32 cnt; + + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + } /* Wait */ + + /* Reset the EMAC Module. This clears the CPPI RAM also */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + } /* Wait */ + + HWREG( emacBase + EMAC_MACCONTROL ) = 0U; + HWREG( emacBase + EMAC_RXCONTROL ) = 0U; + HWREG( emacBase + EMAC_TXCONTROL ) = 0U; + + /* Initialize all the header descriptor pointer registers */ + for( cnt = 0U; cnt < EMAC_MAX_HEADER_DESC; cnt++ ) + { + HWREG( emacBase + EMAC_RXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXFREEBUFFER( cnt ) ) = 0xFFU; + } + /* Clear the interrupt enable for all the channels */ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) = 0xFFU; + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) = 0xFFU; + + HWREG( emacBase + EMAC_MACHASH1 ) = 0U; + HWREG( emacBase + EMAC_MACHASH2 ) = 0U; + + HWREG( emacBase + EMAC_RXBUFFEROFFSET ) = 0U; +} + +/** + * \brief Sets the MAC Address in MACSRCADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_016 */ +/* DesignId : ETH_DesignId_016*/ +/* Requirements : CONQ_EMAC_SR5 */ +void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ) +{ + HWREG( emacBase + EMAC_MACSRCADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACSRCADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) ); +} + +/** + * \brief Sets the MAC Address in MACADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param matchFilt Match or Filter + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * matchFilt can take the following values \n + * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match + * or filter incoming packet. \n + * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n + * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_017 */ +/* DesignId : ETH_DesignId_017*/ +/* Requirements : CONQ_EMAC_SR6 */ +void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ) +{ + HWREG( emacBase + EMAC_MACINDEX ) = channel; + + HWREG( emacBase + EMAC_MACADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) + | matchFilt | ( channel << 16U ) ); +} + +/** + * \brief Acknowledges an interrupt processed to the EMAC Control Core. + * + * \param emacBase Base Address of the EMAC module registers. + * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control + * module. + * eoiFlag can take the following values \n + * EMAC_INT_CORE0_TX - Core 0 TX Interrupt + * EMAC_INT_CORE1_TX - Core 1 TX Interrupt + * EMAC_INT_CORE2_TX - Core 2 TX Interrupt + * EMAC_INT_CORE0_RX - Core 0 RX Interrupt + * EMAC_INT_CORE1_RX - Core 1 RX Interrupt + * EMAC_INT_CORE2_RX - Core 2 RX Interrupt + * \return None + * + **/ +/* SourceId : ETH_SourceId_018 */ +/* DesignId : ETH_DesignId_018*/ +/* Requirements : CONQ_EMAC_SR16 */ +void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ) +{ + /* Acknowledge the EMAC Control Core */ + HWREG( emacBase + EMAC_MACEOIVECTOR ) = eoiFlag; +} + +/** + * \brief Writes the the TX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_019 */ +/* DesignId : ETH_DesignId_019*/ +/* Requirements : CONQ_EMAC_SR41 */ +void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_TXCP( channel ) ) = comPtr; +} + +/** + * \brief Writes the the RX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_020 */ +/* DesignId : ETH_DesignId_020*/ +/* Requirements : CONQ_EMAC_SR42 */ +void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_RXCP( channel ) ) = comPtr; +} + +/** + * \brief Enables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_021 */ +/* DesignId : ETH_DesignId_021*/ +/* Requirements : CONQ_EMAC_SR43 */ +void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + + HWREG( + emacBase + + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXBROADEN + | ( ( uint32 ) channel + << ( uint32 ) EMAC_RXMBPENABLE_RXBROADCH_SHIFT ) ); +} + +/** + * \brief Disables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_022 */ +/* DesignId : ETH_DesignId_022*/ +/* Requirements : CONQ_EMAC_SR44 */ +void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + /* Broadcast Frames are filtered. */ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADEN ); +} + +/** + * \brief Enables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_023 */ +/* DesignId : ETH_DesignId_023*/ +/* Requirements : CONQ_EMAC_SR45 */ +void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXMULTEN + | ( channel ) ); +} + +/** + * \brief Disables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_024 */ +/* DesignId : ETH_DesignId_024*/ +/* Requirements : CONQ_EMAC_SR46 */ +void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTEN ); +} + +/** + * \brief Enables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_025 */ +/* DesignId : ETH_DesignId_025*/ +/* Requirements : CONQ_EMAC_SR7 */ +void EMACRxUnicastSet( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXUNICASTSET ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_026 */ +/* DesignId : ETH_DesignId_026*/ +/* Requirements : CONQ_EMAC_SR8 */ +void EMACRxUnicastClear( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXUNICASTCLEAR ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Set the free buffers for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param nBuf Number of free buffers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_027 */ +/* DesignId : ETH_DesignId_027*/ +/* Requirements : CONQ_EMAC_SR15 */ +void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ) +{ + HWREG( emacBase + EMAC_RXFREEBUFFER( channel ) ) = nBuf; +} + +/** + * \brief Gets the interrupt vectors of EMAC, which are pending + * + * \param emacBase Base Address of the EMAC module registers. + * + * \return Vectors + * + **/ +/* SourceId : ETH_SourceId_028 */ +/* DesignId : ETH_DesignId_028*/ +/* Requirements : CONQ_EMAC_SR14 */ +uint32 EMACIntVectorGet( uint32 emacBase ) +{ + return ( HWREG( emacBase + EMAC_MACINVECTOR ) ); +} + +/** + * Function to setup the instance parameters inside the interface + * @param hdkif Network interface structure + * @return none. + */ +/* SourceId : ETH_SourceId_029 */ +/* DesignId : ETH_DesignId_029*/ +/* Requirements : CONQ_EMAC_SR3 */ +void EMACInstConfig( hdkif_t * hdkif ) +{ + hdkif->emac_base = EMAC_0_BASE; + hdkif->emac_ctrl_base = EMAC_CTRL_0_BASE; + hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE; + hdkif->mdio_base = MDIO_BASE; + hdkif->phy_addr = 1U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker. + */ + hdkif->phy_autoneg = &PhyAutoNegotiate; + hdkif->phy_partnerability = &PhyPartnerAbilityGet; +} + +/** + * Function to setup the link. AutoNegotiates with the phy for link + * setup and set the EMAC with the result of autonegotiation. + * @param hdkif Network interface structure. + * @return ERR_OK if everything passed + * others if not passed + */ +/* SourceId : ETH_SourceId_030 */ +/* DesignId : ETH_DesignId_030*/ +/* Requirements : CONQ_EMAC_SR4 */ +uint32 EMACLinkSetup( hdkif_t * hdkif ) +{ + uint32 linkstat = EMAC_ERR_CONNECT; + uint16 partnr_ablty = 0U; + uint32 phyduplex = EMAC_DUPLEX_HALF; + volatile uint32 delay = 0xFFFFFU; + + if( PhyAutoNegotiate( ( uint32 ) hdkif->mdio_base, + ( uint32 ) hdkif->phy_addr, + ( uint16 ) ( ( uint16 ) DP83640_100BTX + | ( uint16 ) DP83640_100BTX_FD + | ( uint16 ) DP83640_10BT + | ( uint16 ) DP83640_10BT_FD ) ) + == TRUE ) + { + linkstat = EMAC_ERR_OK; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA + * checker (due to use of & ?) */ + ( void ) PhyPartnerAbilityGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_ablty ); + + /* Check for 100 Mbps and duplex capability */ + if( ( partnr_ablty & DP83640_100BTX_FD ) != 0U ) + { + phyduplex = EMAC_DUPLEX_FULL; + } + } + + else + { + linkstat = EMAC_ERR_CONNECT; + } + + /* Set the EMAC with the negotiation results if it is successful */ + if( linkstat == EMAC_ERR_OK ) + { + EMACDuplexSet( hdkif->emac_base, phyduplex ); + } + + /* Wait for the MII to settle down */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + delay--; + } + + return linkstat; +} + +/** + * \brief Perform a transmit queue teardown, that is, transmission is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_031 */ +/* DesignId : ETH_DesignId_031*/ +/* Requirements : CONQ_EMAC_SR34 */ +void EMACTxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform a receive queue teardown, that is, reception is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_032 */ +/* DesignId : ETH_DesignId_032*/ +/* Requirements : CONQ_EMAC_SR35 */ +void EMACRxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform multicast frame filtering using the MAC Hash Registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param hashTable The hash table which specifies which bits are to be accepted. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_033 */ +/* DesignId : ETH_DesignId_033*/ +/* Requirements : CONQ_EMAC_SR38 */ +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ) +{ + HWREG( emacBase + EMAC_MACHASH1 ) = ( uint32 ) ( hashTable & 0xFFFFFFFFU ); + HWREG( emacBase + EMAC_MACHASH2 ) = ( uint32 ) ( hashTable >> 32U ); +} + +/** + * \brief Sets the Transmit Queue Priority type in the MACCONTROL Register + * + * \param emacBase Base Address of the EMAC module registers. + * \param txPType The Transmit Queue Priority Type. + * 0 results in a round-robin scheme being used to select the next + *channel, while 1 results in a fixed-priority scheme( channel 7 highest priority). + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_034 */ +/* DesignId : ETH_DesignId_034*/ +/* Requirements : CONQ_EMAC_SR39 */ +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ) +{ + /* 1- The queue uses a fixed-priority (channel 7 highest priority) scheme */ + if( txPType == 1U ) + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXPTYPE; + } + else + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + } +} + +/** + * \brief Performs a soft reset of the EMAC and EMAC Control Modules. + * + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_035 */ +/* DesignId : ETH_DesignId_035*/ +/* Requirements : CONQ_EMAC_SR40 */ +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ) +{ + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + /* Wait for the reset to complete */ + } + + /* Reset the EMAC Module. */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + /* Wait for the Reset to complete */ + } +} + +/** + * \brief Enable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_036 */ +/* DesignId : ETH_DesignId_036*/ +/* Requirements : CONQ_EMAC_SR51 */ +void EMACEnableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_CMDIDLE; +} + +/** + * \brief Disable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_037 */ +/* DesignId : ETH_DesignId_037*/ +/* Requirements : CONQ_EMAC_SR52 */ +void EMACDisableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_CMDIDLE ) ); +} + +/** + * \brief Enables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_038 */ +/* DesignId : ETH_DesignId_038*/ +/* Requirements : CONQ_EMAC_SR70 */ +void EMACEnableLoopback( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + uint32 GMIIENval = 0U; + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Enable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_LOOPBACK; + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Disables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_039 */ +/* DesignId : ETH_DesignId_039*/ +/* Requirements : CONQ_EMAC_SR71 */ +void EMACDisableLoopback( uint32 emacBase ) +{ + uint32 GMIIENval = 0U; + + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Disable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_LOOPBACK ); + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Enable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_040 */ +/* DesignId : ETH_DesignId_040*/ +/* Requirements : CONQ_EMAC_SR24 */ +void EMACTxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXFLOWEN; +} + +/** + * \brief Disable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_041 */ +/* DesignId : ETH_DesignId_041*/ +/* Requirements : CONQ_EMAC_SR25 */ +void EMACTxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_TXFLOWEN ); +} + +/** + * \brief Enable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_042 */ +/* DesignId : ETH_DesignId_042*/ +/* Requirements : CONQ_EMAC_SR26 */ +void EMACRxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_RXBUFFERFLOWEN; +} + +/** + * \brief Disable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_043 */ +/* DesignId : ETH_DesignId_043*/ +/* Requirements : CONQ_EMAC_SR27 */ +void EMACRxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RXBUFFERFLOWEN ); +} + +/** + * \brief Performs byte inversion of 32-bit data to counteract swizzling performed by + *CPU during reads of CPPI RAM.(Due to BE8 format) + * + * \param word The 32-bit word to be swizzled. + * \return uint32 + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : CONQ_EMAC_SR73 */ +uint32 EMACSwizzleData( uint32 word ) +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + return word; +#else + return ( ( ( word << 24U ) & 0xFF000000U ) | ( ( word << 8U ) & 0x00FF0000U ) + | ( ( word >> 8U ) & 0x0000FF00U ) | ( ( word >> 24U ) & 0x000000FFU ) ); +#endif +} + +/** + * \brief Receive flow threshold. These bits contain the threshold value for issuing + *flow control on incoming frames for channel n (when enabled). + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param threshold threshold value for issuing flow control on incoming frames for + *the given channel \return None + * + **/ +/* SourceId : ETH_SourceId_044 */ +/* DesignId : ETH_DesignId_044*/ +/* Requirements : CONQ_EMAC_SR28 */ +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ) +{ + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) &= ( 0x0U ); + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) |= threshold; +} + +/** + * \brief This function reads the contents of the 36 network statistics + *registers that are present in the module. \param emacBase Base Address of the EMAC + *module registers. \param statRegNo The number of the register with RXGOODFRAMES + *(Offset= 0x200) being 0. Refer the Technical Reference Manual for the list of registers + *and their contents. \return uint32 + **/ +/* SourceId : ETH_SourceId_045 */ +/* DesignId : ETH_DesignId_045*/ +/* Requirements : CONQ_EMAC_SR47 */ +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ) +{ + return HWREG( emacBase + EMAC_NETSTATREGS( statRegNo ) ); +} + +/** + * \brief Function to read values of Transmit Interrupt Status registers + *(TXINTSTATMASKED and TXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param txintstat pointer to the emac_tx_int_status Structure that will store the + *register values that have been read \return None + * + **/ +/* SourceId : ETH_SourceId_046 */ +/* DesignId : ETH_DesignId_046*/ +/* Requirements : CONQ_EMAC_SR36 */ +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ) +{ + txintstat->intstatmasked = ( HWREG( emacBase + EMAC_TXINTSTATMASKED ) + & ( ( uint32 ) 1U << channel ) ); + txintstat->intstatraw = ( HWREG( emacBase + EMAC_TXINTSTATRAW ) + & ( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Function to read values of Receive Interrupt Status registers + *(RXINTSTATMASKED, RXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param rxintstat pointer to the emac_rx_int_status Structure that will store the + *register values that have been read. \return None + **/ +/* SourceId : ETH_SourceId_047 */ +/* DesignId : ETH_DesignId_047*/ +/* Requirements : CONQ_EMAC_SR37 */ +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ) +{ + rxintstat->intstatmasked_pend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatmasked_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); + + rxintstat->intstatraw_pend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatraw_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); +} + +/** + * \brief Tx and Rx Buffer Descriptors are initialized. Buffer pointers are allocated to + *the Rx Descriptors. + * + * \param hdkif network interface structure + * \return None + * + **/ +/* SourceId : ETH_SourceId_048 */ +/* DesignId : ETH_DesignId_048*/ +/* Requirements : CONQ_EMAC_SR19,CONQ_EMAC_SR20 */ +void EMACDMAInit( hdkif_t * hdkif ) +{ + uint32 num_bd, pbuf_cnt = 0U; + volatile emac_tx_bd_t *curr_txbd, *last_txbd; + volatile emac_rx_bd_t *curr_bd, *last_bd; + txch_t * txch_dma; + rxch_t * rxch_dma; + uint8_t * p; + + txch_dma = &( hdkif->txchptr ); + + /** + * Initialize the Descriptor Memory For TX and RX + * Only single channel is supported for both TX and RX + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + txch_dma->free_head = ( volatile emac_tx_bd_t * ) ( hdkif->emac_ctrl_ram ); + txch_dma->next_bd_to_process = txch_dma->free_head; + txch_dma->active_tail = NULL; + + /* Set the number of descriptors for the channel */ + num_bd = ( SIZE_EMAC_CTRL_RAM >> 1U ) / sizeof( emac_tx_bd_t ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_txbd = txch_dma->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd = curr_txbd; + + /* Initialize all the TX buffer Descriptors */ + while( num_bd != 0U ) + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list + * is incremented." */ + curr_txbd->next = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) ( curr_txbd + 1U ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd->flags_pktlen = 0U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_txbd = curr_txbd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_txbd->next ); + num_bd--; + } + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd->next = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) txch_dma->free_head ); + + /* Initialize the descriptors for the RX channel */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma = &( hdkif->rxchptr ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is + * incremented." */ + curr_txbd++; + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "Linked List pointer needs to be + * assigned." */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "Linked List pointer needs to be assigned." + */ + /*SAFETYMCUSW 344 S MR:11.5 "Linked List pointer needs to be assigned to a + * different structure." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_head = ( volatile emac_rx_bd_t * ) curr_txbd; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->free_head = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_dma->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = curr_bd; + + /* + ** Static allocation of a specific number of packet buffers as specified by + *MAX_RX_PBUF_ALLOC, whose value is entered by the user in HALCoGen GUI. + */ + + /*Commented part of allocation of pbufs need to check whether its true*/ + + for( pbuf_cnt = 0U; pbuf_cnt < MAX_RX_PBUF_ALLOC; pbuf_cnt++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + p = pbuf_array[ pbuf_cnt ]; + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = EMACSwizzleData( ( uint32 ) p ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( EMAC_BUF_DESC_OWNER ); + if( pbuf_cnt == ( MAX_RX_PBUF_ALLOC - 1U ) ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + else + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd->next = ( emac_rx_bd_t * ) EMACSwizzleData( + ( uint32 ) ( curr_bd + 1U ) ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd++; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_tail = last_bd; +} + +/** + * \brief Initializes the EMAC module for transmission and reception. + * + * \param macaddr MAC Address of the Module. + * \param channel Channel Number. + * + * \return EMAC_ERR_OK if everything gets initialized + * EMAC_ERR_CONN in case of an error in connecting. + * + **/ +/* SourceId : ETH_SourceId_049 */ +/* DesignId : ETH_DesignId_049*/ +/* Requirements : CONQ_EMAC_SR2 */ +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ) +{ + uint32 temp, channel; + volatile uint32 phyID = 0U; + volatile uint32 delay = 0xFFFU; + uint32 phyIdReadCount = 0xFFFFU; + volatile uint32 phyLinkRetries = 0xFFFFU; + hdkif_t * hdkif; + rxch_t * rxch; + uint32 retVal = EMAC_ERR_OK; + uint32 emacBase = 0U; +#if( EMAC_MII_ENABLE == 0U ) + uint16 partnr_spd; +#endif + + hdkif = &hdkif_data[ 0U ]; + EMACInstConfig( hdkif ); + /* set MAC hardware address */ + for( temp = 0U; temp < EMAC_HWADDR_LEN; temp++ ) + { + hdkif->mac_addr[ temp ] = macaddr[ ( EMAC_HWADDR_LEN - 1U ) - temp ]; + } + /*Initialize the EMAC, EMAC Control and MDIO modules. */ + EMACInit( hdkif->emac_ctrl_base, hdkif->emac_base ); + MDIOInit( hdkif->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + delay--; + } + + /* Set the MAC Addresses in EMAC hardware */ + emacBase = hdkif->emac_base; /* MISRA Code Fix (12.2) */ + EMACMACSrcAddrSet( emacBase, hdkif->mac_addr ); + for( channel = 0U; channel < 8U; channel++ ) + { + emacBase = hdkif->emac_base; + EMACMACAddrSet( emacBase, channel, hdkif->mac_addr, EMAC_MACADDR_MATCH ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( phyID == 0U ) && ( phyIdReadCount > 0U ) ) + { + phyID = PhyIDGet( hdkif->mdio_base, hdkif->phy_addr ); + phyIdReadCount--; + } + + if( 0U == phyID ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( ( uint32 ) 0U + == ( ( MDIOPhyAliveStatusGet( hdkif->mdio_base ) >> hdkif->phy_addr ) + & ( uint32 ) 0x01U ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + +#if( EMAC_MII_ENABLE == 0U ) + PhyPartnerSpdGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_spd ); + if( ( partnr_spd & 2U ) == 0U ) + { + EMACRMIISpeedSet( hdkif->emac_base, EMAC_MACCONTROL_RMIISPEED ); + } +#endif + + if( !PhyLinkStatusGet( hdkif->mdio_base, + ( uint32 ) EMAC_PHYADDRESS, + ( uint32 ) phyLinkRetries ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( EMACLinkSetup( hdkif ) != EMAC_ERR_OK ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + /* The transmit and receive buffer descriptors are initialized here. + * Also, packet buffers are allocated to the receive buffer descriptors. + */ + + EMACDMAInit( hdkif ); + + /* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/ + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_RX ); + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_TX ); + + /* Enable GMII bit in the MACCONTROL Rgister*/ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ + EMACMIIEnable( hdkif->emac_base ); + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_BROADCAST_ENABLE ) + EMACRxBroadCastEnable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxBroadCastDisable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_UNICAST_ENABLE ) + EMACRxUnicastSet( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxUnicastClear( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /*Enable Full Duplex or Half-Duplex mode based on GUI Input. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_FULL_DUPLEX_ENABLE ) + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_FULL ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition arameter is taken as input from + * GUI." */ + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_HALF ); +#endif + + /* Enable Loopback based on GUI Input */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_LOOPBACK_ENABLE ) + EMACEnableLoopback( hdkif->emac_base ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACDisableLoopback( hdkif->emac_base ); +#endif + + /* Enable Transmit and Transmit Interrupt */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_TX_ENABLE ) + EMACTxEnable( hdkif->emac_base ); + EMACTxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACTxDisable( hdkif->emac_base ); + EMACTxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /* Enable Receive and Receive Interrupt. Then start receiving by writing to the HDP + * register. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_RX_ENABLE ) + EMACNumFreeBufSet( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) MAX_RX_PBUF_ALLOC ); + EMACRxEnable( hdkif->emac_base ); + EMACRxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); + rxch = &( hdkif->rxchptr ); + /* Write to the RX HDP for channel 0 */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) rxch->active_head, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxDisable( hdkif->emac_base ); + EMACRxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + return retVal; +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf might be + * chained. That is, one pbuf can span more than one tx buffer descriptors + * + * @param hdkif network interface structure + * @param pbuf the pbuf structure which contains the data to be sent using EMAC + * @return boolean. + * -Returns FALSE if a Null pointer was passed for transmission + * -Returns TRUE if valid data is sent and is transmitted. + */ +/* SourceId : ETH_SourceId_050 */ +/* DesignId : ETH_DesignId_050*/ +/* Requirements : CONQ_EMAC_SR49 */ +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ) +{ + txch_t * txch; + pbuf_t * q; + uint32 flags_pktlen; + uint16 totLen; + uint16 qLen; + volatile emac_tx_bd_t *curr_bd, *active_head, *bd_end; + boolean retValue = FALSE; + if( ( pbuf != NULL ) && ( hdkif != NULL ) ) + { + txch = &( hdkif->txchptr ); + + /* Get the buffer descriptor which is free to transmit */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + active_head = curr_bd; + + /* Update the total packet length */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + totLen = pbuf->tot_len; + + curr_bd->flags_pktlen = 0U; + flags_pktlen = ( ( uint32 ) ( totLen ) + | ( EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER ) ); + /* Indicate the start of the packet */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( flags_pktlen ); + + /* Copy pbuf information into TX buffer descriptors */ + q = pbuf; + while( q != NULL ) + { + /* Initialize the buffer pointer and length */ + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = EMACSwizzleData( ( uint32 ) ( q->payload ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + qLen = ( uint16 ) ( q->len ); + curr_bd->bufoff_len = ( uint32 ) EMACSwizzleData( + ( ( uint32 ) ( qLen ) & 0xFFFFU ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + q = q->next; + } + + /* Indicate the start and end of the packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end->next = NULL; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + bd_end->flags_pktlen |= EMACSwizzleData( EMAC_BUF_DESC_EOP ); + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." + */ + txch->free_head = curr_bd; + + /* For the first time, write the HDP with the filled bd */ + if( txch->active_tail == NULL ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /* + * Chain the bd's. If the DMA engine, already reached the end of the chain, + * the EOQ will be set. In that case, the HDP shall be written again. + */ + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->active_tail; + /* Wait for the EOQ bit is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( EMAC_BUF_DESC_EOQ + != ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) ) + { + } + /* Don't write to TXHDP0 until it turns to zero */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( ( uint32 ) 0U != *( ( uint32 * ) 0xFCF78600U ) ) ) + { + } + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) active_head ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( EMAC_BUF_DESC_EOQ + == ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) ) + { + /* Write the Header Descriptor Pointer and start DMA */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch->active_tail = bd_end; + retValue = TRUE; + } + else + { + retValue = FALSE; + } + return retValue; +} + +/** + * Function for processing Tx buffer descriptors. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_051 */ +/* DesignId : ETH_DesignId_051*/ +/* Requirements : CONQ_EMAC_SR13 */ +void EMACTxIntHandler( hdkif_t * hdkif ) +{ + txch_t * txch_int; + volatile emac_tx_bd_t *curr_bd, *next_bd_to_process; + + txch_int = &( hdkif->txchptr ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = next_bd_to_process; + + /* Check for correct start of packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_SOP ) + == EMAC_BUF_DESC_SOP ) + { + /* Make sure that the transmission is over */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_OWNER ) + == EMAC_BUF_DESC_OWNER ) + { + } + + /* Traverse till the end of packet is reached */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_EOP ) + != EMAC_BUF_DESC_EOP ) + { + curr_bd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process->flags_pktlen &= ~( EMACSwizzleData( EMAC_BUF_DESC_SOP ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen &= ~( EMACSwizzleData( EMAC_BUF_DESC_EOP ) ); + + /** + * If there are no more data transmitted, the next interrupt + * shall happen with the pbuf associated with the free_head + */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( curr_bd->next == NULL ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = txch_int->free_head; + } + + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) curr_bd->next ); + } + + /* Acknowledge the EMAC and free the corresponding pbuf */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as + * an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 344 S MR:11.5 "Address stored in pointer is passed as as + * an int parameter." */ + EMACTxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) curr_bd ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = next_bd_to_process; + } +} + +/** + * Function for processing received packets. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_052 */ +/* DesignId : ETH_DesignId_052*/ +/* Requirements : CONQ_EMAC_SR50 */ +void EMACReceive( hdkif_t * hdkif ) +{ + rxch_t * rxch_int; + volatile emac_rx_bd_t *curr_bd, *curr_tail, *last_bd; + + /* The receive structure that holds data about a particular receive channel */ + rxch_int = &( hdkif->rxchptr ); + + /* Get the buffer descriptors which contain the earliest filled data */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_int->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = rxch_int->active_tail; + + /** + * Process the descriptors as long as data is available + * when the DMA is receiving data, SOP flag will be set + */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_SOP ) + == EMAC_BUF_DESC_SOP ) + { + /* Start processing once the packet is loaded */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_OWNER ) + != EMAC_BUF_DESC_OWNER ) + { + /* this bd chain will be freed after processing */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + + /* Get the total length of the packet. curr_bd points to the start + * of the packet. + */ + + /* + * The loop runs till it reaches the end of the packet. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOP ) + != EMAC_BUF_DESC_EOP ) + { + /*Update the flags for the descriptor again and the length of the buffer*/ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( ( uint32 ) EMAC_BUF_DESC_OWNER ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( ( uint32 ) MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_rx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + } + + /* Updating the last descriptor (which contained the EOP flag) */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( ( uint32 ) EMAC_BUF_DESC_OWNER ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( ( uint32 ) MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_rx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + + /* Acknowledge that this packet is processed */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) last_bd ); + + /* The next buffer descriptor is the new head of the linked list. */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->active_head = curr_bd; + + /* The processed descriptor is now the tail of the linked list. */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail = rxch_int->active_tail; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail->next = ( emac_rx_bd_t * ) EMACSwizzleData( + ( uint32 ) rxch_int->free_head ); + + /* The last element in the already processed Rx descriptor chain is now the + * end of list. */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd->next = NULL; + + /** + * Check if the reception has ended. If the EOQ flag is set, the NULL + * Pointer is taken by the DMA engine. So we need to write the RX HDP + * with the next descriptor. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( EMACSwizzleData( curr_tail->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) + == EMAC_BUF_DESC_EOQ ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( rxch_int->free_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + rxch_int->active_tail = last_bd; + } + } +} + +/** @fn void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETH_SourceId_053 */ +/* DesignId : ETH_DesignId_053*/ +/* Requirements : CONQ_EMAC_SR74 */ +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->TXCONTROL = EMAC_TXCONTROL_CONFIGVALUE; + config_reg->RXCONTROL = EMAC_RXCONTROL_CONFIGVALUE; + config_reg->TXINTMASKSET = EMAC_TXINTMASKSET_CONFIGVALUE; + config_reg->TXINTMASKCLEAR = EMAC_TXINTMASKCLEAR_CONFIGVALUE; + config_reg->RXINTMASKSET = EMAC_RXINTMASKSET_CONFIGVALUE; + config_reg->RXINTMASKCLEAR = EMAC_RXINTMASKCLEAR_CONFIGVALUE; + config_reg->MACSRCADDRHI = EMAC_MACSRCADDRHI_CONFIGVALUE; + config_reg->MACSRCADDRLO = EMAC_MACSRCADDRLO_CONFIGVALUE; + config_reg->MDIOCONTROL = EMAC_MDIOCONTROL_CONFIGVALUE; + config_reg->C0RXEN = EMAC_C0RXEN_CONFIGVALUE; + config_reg->C0TXEN = EMAC_C0TXEN_CONFIGVALUE; + } + else + { + config_reg->TXCONTROL = HWREG( EMAC_0_BASE + EMAC_TXCONTROL ); + config_reg->RXCONTROL = HWREG( EMAC_0_BASE + EMAC_RXCONTROL ); + config_reg->TXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_TXINTMASKSET ); + config_reg->TXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_TXINTMASKCLEAR ); + config_reg->RXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_RXINTMASKSET ); + config_reg->RXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_RXINTMASKCLEAR ); + config_reg->MACSRCADDRHI = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRHI ); + config_reg->MACSRCADDRLO = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRLO ); + config_reg->MDIOCONTROL = HWREG( MDIO_0_BASE + MDIO_CONTROL ); + config_reg->C0RXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnRXEN( 0U ) ); + config_reg->C0TXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnTXEN( 0U ) ); + } +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c new file mode 100644 index 00000000000..1274b7d517c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c @@ -0,0 +1,320 @@ +/** @file emif.c + * @brief emif Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void emif_SDRAMInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function has been deprecated. + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF clock + * below 40MHz. Hence the init function needs to be called from the startup before the PLL + * is configured. A new function emif_SDRAM_StartupInit has been added and is called from + * the startup. This function need not be called from the main, and is preserved for + * compatibilty. + */ + +/* SourceId : EMIF_SourceId_001 */ +/* DesignId : EMIF_DesignId_001 */ +/* Requirements : CONQ_EMIF_SR2 */ +void emif_SDRAMInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC1Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_002 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR3 */ +void emif_ASYNC1Init( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + emifREG->CE2CFG = 0x00000000U; + emifREG->CE2CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFFFF00U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) + | ( uint32 ) ( ( uint32 ) 0U ); + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC2Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_003 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR4 */ +void emif_ASYNC2Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + emifREG->CE3CFG = 0x00000000U; + emifREG->CE3CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFF00FFU ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ); + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC3Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_004 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR5 */ +void emif_ASYNC3Init( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + emifREG->CE4CFG = 0x00000000U; + emifREG->CE4CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFF00FFFFU ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void emifGetConfigValue(emif_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the EMIF configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EMIF_SourceId_005 */ +/* DesignId : EMIF_DesignId_003 */ +/* Requirements : CONQ_EMIF_SR6 */ +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_AWCC = EMIF_AWCC_CONFIGVALUE; + config_reg->CONFIG_SDCR = EMIF_SDCR_CONFIGVALUE; + config_reg->CONFIG_SDRCR = EMIF_SDRCR_CONFIGVALUE; + config_reg->CONFIG_CE2CFG = EMIF_CE2CFG_CONFIGVALUE; + config_reg->CONFIG_CE3CFG = EMIF_CE3CFG_CONFIGVALUE; + config_reg->CONFIG_CE4CFG = EMIF_CE4CFG_CONFIGVALUE; + config_reg->CONFIG_CE5CFG = EMIF_CE5CFG_CONFIGVALUE; + config_reg->CONFIG_SDTIMR = EMIF_SDTIMR_CONFIGVALUE; + config_reg->CONFIG_SDSRETR = EMIF_SDSRETR_CONFIGVALUE; + config_reg->CONFIG_INTMSK = EMIF_INTMSK_CONFIGVALUE; + config_reg->CONFIG_PMCR = EMIF_PMCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_AWCC = emifREG->AWCC; + config_reg->CONFIG_SDCR = emifREG->SDCR; + config_reg->CONFIG_SDRCR = emifREG->SDRCR; + config_reg->CONFIG_CE2CFG = emifREG->CE2CFG; + config_reg->CONFIG_CE3CFG = emifREG->CE3CFG; + config_reg->CONFIG_CE4CFG = emifREG->CE4CFG; + config_reg->CONFIG_CE5CFG = emifREG->CE5CFG; + config_reg->CONFIG_SDTIMR = emifREG->SDTIMR; + config_reg->CONFIG_SDSRETR = emifREG->SDSRETR; + config_reg->CONFIG_INTMSK = emifREG->INTMSK; + config_reg->CONFIG_PMCR = emifREG->PMCR; + } +} + +/** @fn void emif_SDRAM_StartupInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function initializes the emif driver for SDRAM (SDRAM initialization function). + * SDRAM Configuration Procedure B as documented in the TRM is implemented. + * + * Note: This function is called in the startup. Do not call the function inside main. + */ + +/* SourceId : EMIF_SourceId_006 */ +/* DesignId : EMIF_DesignId_004 */ +/* Requirements : CONQ_EMIF_SR2 */ +void emif_SDRAM_StartupInit( void ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + volatile uint32 buffer; + + /* Procedure B Step 1: EMIF Clock Frequency is assumed to be configured in the + * startup */ + + /* Procedure B Step 2: Program SDTIMR and SDSRETR to satisfy requirements of SDRAM + * Device */ + emifREG->SDTIMR = ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ); + + emifREG->SDSRETR = ( uint32 ) 0U; + + /* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of + * initialization time */ + emifREG->SDRCR = 1605U; + + /* Procedure B Step 4: Program SDRCR to Trigger Initialization Sequence */ + /** -general clearing of register + * -for NM for setting 16 bit data bus + * -cas latency + * -BIT11_9CLOCK to allow the cl field to be written + * -selecting the banks + * -setting the pagesize + */ + emifREG->SDCR = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 1U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) elements_256 ); + + /* Procedure B Step 5: Read of SDRAM memory location causes processor to wait until + * SDRAM Initialization completes */ + buffer = *PTR; + /* prevents optimization */ + buffer = buffer; + + /* Procedure B Step 6: Program the RR field to the default Refresh Interval of the + * SDRAM*/ + emifREG->SDRCR = 0U; + + /* Place the EMIF in Self Refresh Mode For Clock Change */ + /* Must only write to the upper byte of the SDCR to avoid */ + /* a second intiialization sequence */ + /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */ + *( ( unsigned char * ) ( &emifREG->SDCR ) + 0x3U ) = 0x80U; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c new file mode 100644 index 00000000000..1a16ccee63b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c @@ -0,0 +1,369 @@ +/** @file epc.c + * @brief EPC Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * This file contains APIs for the Error Profiling Controller Module. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "epc.h" +#include "system.h" +#include "reg_esm.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void epcEnableIP1ErrorGen(void) + * @brief Enable ECC error generation for ECC errors on DMA Port A + * + * Enable ECC error generation for ECC errors detected on DMA Port A master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_001 */ +/* DesignId : EPC_DesignId_001 */ +/* Requirements : CONQ_EPC_SR1 */ +void epcEnableIP1ErrorGen( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void epcDisableIP1ErrorGen(void) + * @brief Disable ECC error generation for ECC errors on DMA Port A + * + * Disable ECC error generation for ECC errors detected on DMA Port A master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_002 */ +/* DesignId : EPC_DesignId_002 */ +/* Requirements : CONQ_EPC_SR2 */ +void epcDisableIP1ErrorGen( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void epcEnableIP2ErrorGen(void) + * @brief Enable ECC error generation for ECC errors on PS_SCR_M + * + * Enable ECC error generation for ECC errors detected on PS_SCR_M master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_003 */ +/* DesignId : EPC_DesignId_003 */ +/* Requirements : CONQ_EPC_SR3 */ +void epcEnableIP2ErrorGen( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFF0FFU ) | 0xA00U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void epcDisableIP2ErrorGen(void) + * @brief Disable ECC error generation for ECC errors on PS_SCR_M + * + * Disable ECC error generation for ECC errors detected on PS_SCR_M master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_004 */ +/* DesignId : EPC_DesignId_004 */ +/* Requirements : CONQ_EPC_SR4 */ +void epcDisableIP2ErrorGen( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFF0FFU ) | 0x500U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void epcEnableSERREvent(void) + * @brief Single (correctable) bit error event enable. + * + * These bits (when enabled) cause EPC to + * generate the serr_event if there is a correctable ECC fault address arrives from one + * of the EPC-IP interface and the CAM has an empty entry. + */ +/* SourceId : EPC_SourceId_005 */ +/* DesignId : EPC_DesignId_005 */ +/* Requirements : CONQ_EPC_SR5 */ +void epcEnableSERREvent( void ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void epcDisableSERREvent(void) + * @brief Single (correctable) bit error event disable. + * + * These bits (when enabled) cause EPC to + * disable the serr_event generation. + */ +/* SourceId : EPC_SourceId_006 */ +/* DesignId : EPC_DesignId_006 */ +/* Requirements : CONQ_EPC_SR6 */ +void epcDisableSERREvent( void ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn void epcEnableInterrupt(void) + * @brief CAM or FIFO full interrupt enable. + * + * If this bit is set and CAM is full, CAM Full Interrupt + * is generated. + */ +/* SourceId : EPC_SourceId_007 */ +/* DesignId : EPC_DesignId_007 */ +/* Requirements : CONQ_EPC_SR7 */ +void epcEnableInterrupt( void ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL |= ( uint32 ) ( ( uint32 ) 1U << 24U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void epcDisableInterrupt(void) + * @brief CAM or FIFO full interrupt disable. + * + * Disables interrupt generation in case CAM is full. + */ +/* SourceId : EPC_SourceId_008 */ +/* DesignId : EPC_DesignId_008 */ +/* Requirements : CONQ_EPC_SR8 */ +void epcDisableInterrupt( void ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL &= ~( uint32 ) ( ( uint32 ) 1U << 24U ); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void epcCAMInit(void) + * @brief Initializes CAM. + * + * CAM entries are cleared and available for future CAM usage. + */ +/* SourceId : EPC_SourceId_009 */ +/* DesignId : EPC_DesignId_009 */ +/* Requirements : CONQ_EPC_SR9 */ +void epcCAMInit( void ) +{ + uint8 i; + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + for( i = 0U; i < 8U; i++ ) + { + epcREG1->CAM_INDEX[ i ] = 0x05050505U; + } + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void epcDiagnosticTest(void) + * @brief CAM diagnostic test. + * @return TRUE if diagnostic test passed, FALSE otherwise + * + * This function executes a diagnostic test on EPC and returns the result + */ +/* SourceId : EPC_SourceId_010 */ +/* DesignId : EPC_DesignId_010 */ +/* Requirements : CONQ_EPC_SR14 */ +boolean epcDiagnosticTest( void ) +{ + uint32 epccntrl_bk, camCont_bk, camIndex_bk; + uint32 camAvailable; + boolean status = true; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* Back up EPCCNTRL register */ + epccntrl_bk = epcREG1->EPCCNTRL; + + /* Back up CAM_CONTENT[0] and CAM_INDEX[0] registers */ + camCont_bk = epcREG1->CAM_CONTENT[ 0U ]; + camIndex_bk = epcREG1->CAM_INDEX[ 0U ]; + + /* Enter CAM diagnostic mode and and enable Single (correctable) bit error event + * generation */ + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFF0F0U ) | 0x0A0AU; + + /* Clear first CAM entry */ + epcREG1->CAM_INDEX[ 0U ] = ( epcREG1->CAM_INDEX[ 0U ] & 0xFFFFFFF0U ) | 0x5U; + + /* Identify the number of CAM entries available */ + camAvailable = epcREG1->CAMAVAILSTAT; + + /* New CAM Entry */ + epcREG1->CAM_CONTENT[ 0U ] = 0x1000U; + + /* The number of CAM entries must reduce by 1 */ + if( ( ( esmREG->SR1[ 0U ] & 0x10U ) != 0x10U ) + || ( epcREG1->CAMAVAILSTAT != ( camAvailable - 1U ) ) + || ( epcCheckCAMEntry( 0U ) == true ) ) + { + status = false; + } + + /* Restore CAM_CONTENT and CAM_INDEX[0] registers */ + epcREG1->CAM_CONTENT[ 0U ] = camCont_bk; + epcREG1->CAM_INDEX[ 0U ] = camIndex_bk; + + /* Disable CAM diagnostic mode and restore EPCCNTRL register */ + epcREG1->EPCCNTRL = epccntrl_bk; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + return status; +} + +/** @fn void epcAddCAMEEntry(uint32 address) + * @brief Add a new CAM Entry + * + * Allows you to write a new CAM entry, after checking if there are any available + * entries. + */ +/* SourceId : EPC_SourceId_011 */ +/* DesignId : EPC_DesignId_011 */ +/* Requirements : CONQ_EPC_SR10 */ +boolean epcAddCAMEEntry( uint32 address ) +{ + uint8 i = 0U; + boolean status = false; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + if( epcREG1->CAMAVAILSTAT != 0U ) + { + for( i = 0U; i < 32U; i++ ) + { + if( epcCheckCAMEntry( i ) == true ) + { + epcREG1->CAM_CONTENT[ i ] = address; + status = true; + break; + } + } + } + else + { + status = false; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return status; +} + +/** @fn void epcCheckCAMEntry(uint32 CAMIndex) + * @brief Checks if CAM entry is available. + * + * Checks if the CAM Entry is available and ready for future usage. + */ +/* SourceId : EPC_SourceId_012 */ +/* DesignId : EPC_DesignId_012 */ +/* Requirements : CONQ_EPC_SR11 */ +boolean epcCheckCAMEntry( uint32 index ) +{ + uint32 i, j; + boolean status = false; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + i = index / 4U; + j = ( index % 4U ) * 8U; + + /* Check for availability of CAM Entry for future CAM usage. */ + if( ( epcREG1->CAM_INDEX[ i ] & ( uint32 ) ( ( uint32 ) 0xFU << j ) ) + == ( uint32 ) ( ( uint32 ) 0x5U << j ) ) + { + status = true; + } + else + { + status = false; + } + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + return status; +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c new file mode 100644 index 00000000000..fec49834f0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c @@ -0,0 +1,1273 @@ +/** @file eqep.c + * @brief EQEP Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "eqep.h" +#include "sys_vim.h" + +/*the functions + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void QEPInit(void) + * @brief Initializes the eQEP Driver + * + * This function initializes the eQEP module. + */ +/* SourceId : EQEP_SourceId_001 */ +/* DesignId : EQEP_DesignId_001 */ +/* Requirements : CONQ_QEP_SR1 */ +void QEPInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG1->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG1->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG1->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG1->QPOSCMP = 0x00000000U; + + /** - Clear the time base */ + eqepREG1->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG1->QUPRD = ( uint32 ) 0x00000000U; + + /** - Clear Watchdog Timer register */ + eqepREG1->QWDTMR = ( uint16 ) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG1->QWDPRD = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG1->QDECCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) + | ( uint16 ) ( ( uint16 ) 0U << 13U ) + | ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) + | ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Stobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG1 + ->QEPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) + | ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) + | ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ + << 2U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG1->QPOSCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) + | ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP + << 14U ) + | ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) + | ( uint16 ) ( ( uint16 ) 0x000U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG1->QCAPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) + | ( uint16 ) 0x0000U ); + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG1->QCLR = ( uint16 ) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG1->QEINT = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) ( ( uint16 ) 0U << 4U ) + | ( uint16 ) ( ( uint16 ) 0U << 3U ) + | ( uint16 ) ( ( uint16 ) 0U << 2U ) + | ( uint16 ) ( ( uint16 ) 0U << 1U ) ); + + /** - Clear Capture Timer register */ + eqepREG1->QCTMR = ( uint16 ) 0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG1->QCPRD = ( uint16 ) 0x0000U; + + /** - Clear Period Latch register */ + eqepREG1->QCPRDLAT = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG2->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG2->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG2->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG2->QPOSCMP = 0U; + + /** - Clear the time base */ + eqepREG2->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG2->QUPRD = ( uint32 ) 0U; + + /** - Clear Watchdog Timer register */ + eqepREG2->QWDTMR = ( uint16 ) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG2->QWDPRD = ( uint16 ) 0U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG2->QDECCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) + | ( uint16 ) ( ( uint16 ) 0U << 13U ) + | ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) + | ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Strobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG2 + ->QEPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) + | ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) + | ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ + << 2U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG2->QPOSCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) + | ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP + << 14U ) + | ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) + | ( uint16 ) ( ( uint16 ) 0U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG2->QCAPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) + | ( uint16 ) 0x0000U ); + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG2->QCLR = ( uint16 ) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG2->QEINT = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) ( ( uint16 ) 0U << 4U ) + | ( uint16 ) ( ( uint16 ) 0U << 3U ) + | ( uint16 ) ( ( uint16 ) 0U << 2U ) + | ( uint16 ) ( ( uint16 ) 0U << 1U ) ); + + /** - Clear Capture Timer register */ + eqepREG2->QCTMR = ( uint16 ) 0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG2->QCPRD = ( uint16 ) 0x0000U; + + /** - Clear Period Latch register */ + eqepREG2->QCPRDLAT = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @brief Clears all QEP interrupt flags + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_002 */ +/* DesignId : EQEP_DesignId_002 */ +/* Requirements : CONQ_QEP_SR2 */ +void eqepClearAllInterruptFlags( eqepBASE_t * eqep ) +{ + eqep->QCLR = 0xfffU; + + return; +} /*end of eQEP_clear_all_interrupt_flags() function */ + +/** @brief Clears a single interrupt flag + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Interrupt flag + */ +/* SourceId : EQEP_SourceId_003 */ +/* DesignId : EQEP_DesignId_003 */ +/* Requirements : CONQ_QEP_SR3 */ +void eqepClearInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QCLR |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_clear_interrupt_flag() function */ + +/** @brief Clears the position counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_004 */ +/* DesignId : EQEP_DesignId_004 */ +/* Requirements : CONQ_QEP_SR4 */ +void eqepClearPosnCounter( eqepBASE_t * eqep ) +{ + eqep->QPOSCNT = 0U; + + return; +} /*end of eQEP_clear_posn_counter() function */ + +/** @brief Disables all interrupts + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_005 */ +/* DesignId : EQEP_DesignId_005 */ +/* Requirements : CONQ_QEP_SR5 */ +void eqepDisableAllInterrupts( eqepBASE_t * eqep ) +{ + eqep->QEINT = 0U; + + return; +} /*end of eQEP_disable_all_interrupts () function */ + +/** @brief Disable capture + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_006 */ +/* DesignId : EQEP_DesignId_006 */ +/* Requirements : CONQ_QEP_SR6 */ +void eqepDisableCapture( eqepBASE_t * eqep ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_disable_capture () function */ + +/** @brief Disable gating of index pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_007 */ +/* DesignId : EQEP_DesignId_007 */ +/* Requirements : CONQ_QEP_SR7 */ +void eqepDisableGateIndex( eqepBASE_t * eqep ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_IGATE; + + return; +} /*end of eQEP_disable_gate_index () function */ + +/** @brief Disable individual interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Individual interrupts + */ +/* SourceId : EQEP_SourceId_008 */ +/* DesignId : EQEP_DesignId_008 */ +/* Requirements : CONQ_QEP_SR8 */ +void eqepDisableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QEINT &= ( uint16 ) ~( uint16 ) QEINT_type; + + return; +} /*end of eQEP_disable_interrupt */ + +/** @brief Disable position compare + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_009 */ +/* DesignId : EQEP_DesignId_009 */ +/* Requirements : CONQ_QEP_SR9 */ +void eqepDisablePosnCompare( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_disable_posn_compare () function */ + +/** @brief Disable position compare shadowing + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_010 */ +/* DesignId : EQEP_DesignId_010 */ +/* Requirements : CONQ_QEP_SR10 */ +void eqepDisablePosnCompareShadow( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_disable_posn_compare_shadow () function */ + +/** @brief Disable output sync pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_011 */ +/* DesignId : EQEP_DesignId_011 */ +/* Requirements : CONQ_QEP_SR11 */ +void eqepDisableSyncOut( eqepBASE_t * eqep ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_disable_sync_out () function */ + +/** @brief Disable unit timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_012 */ +/* DesignId : EQEP_DesignId_012 */ +/* Requirements : CONQ_QEP_SR12 */ +void eqepDisableUnitTimer( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_disable_unit_timer () function */ + +/** @brief Disable watchdog timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_013 */ +/* DesignId : EQEP_DesignId_013 */ +/* Requirements : CONQ_QEP_SR13 */ +void eqepDisableWatchdog( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_disable_watchdog () function */ + +/** @brief Enable capture + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_014 */ +/* DesignId : EQEP_DesignId_014 */ +/* Requirements : CONQ_QEP_SR14 */ +void eqepEnableCapture( eqepBASE_t * eqep ) +{ + eqep->QCAPCTL |= eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_enable_capture () function */ + +/** @brief Enable counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_015 */ +/* DesignId : EQEP_DesignId_015 */ +/* Requirements : CONQ_QEP_SR15 */ +void eqepEnableCounter( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_QPEN; + + return; +} /*end of eQEP_enable_counter () function */ + +/** @brief Enable gating of index pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_016 */ +/* DesignId : EQEP_DesignId_016 */ +/* Requirements : CONQ_QEP_SR16 */ +void eqepEnableGateIndex( eqepBASE_t * eqep ) +{ + eqep->QDECCTL |= ( uint16 ) eQEP_Igate_Enable; + + return; +} /*end of eQEP_enable_gate_index () function */ + +/** @brief Enable individual interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT_type Individual interrupts + */ +/* SourceId : EQEP_SourceId_017 */ +/* DesignId : EQEP_DesignId_017 */ +/* Requirements : CONQ_QEP_SR17 */ +void eqepEnableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QEINT |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_enable_interrupt () function */ + +/** @brief Enable position compare + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_018 */ +/* DesignId : EQEP_DesignId_018 */ +/* Requirements : CONQ_QEP_SR18 */ +void eqepEnablePosnCompare( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL |= eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_enable_posn_compare () function */ + +/** @brief Enable position compare shadowing + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_019 */ +/* DesignId : EQEP_DesignId_019 */ +/* Requirements : CONQ_QEP_SR19 */ +void eqepEnablePosnCompareShadow( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL |= eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_enable_posn_compare_shadow () function */ + +/** @brief Enable output sync pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_020 */ +/* DesignId : EQEP_DesignId_020 */ +/* Requirements : CONQ_QEP_SR46 */ +void eqepEnableSyncOut( eqepBASE_t * eqep ) +{ + eqep->QDECCTL |= eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_enable_sync_out () function */ + +/** @brief Enable unit timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_021 */ +/* DesignId : EQEP_DesignId_021 */ +/* Requirements : CONQ_QEP_SR20 */ +void eqepEnableUnitTimer( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_enable_unit_timer () function */ + +/** @brief Enable watchdog timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_022 */ +/* DesignId : EQEP_DesignId_022 */ +/* Requirements : CONQ_QEP_SR21 */ +void eqepEnableWatchdog( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_enable_watchdog () function */ + +/** @brief Manually force QEP interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Individual interrupt + */ +/* SourceId : EQEP_SourceId_023 */ +/* DesignId : EQEP_DesignId_023 */ +/* Requirements : CONQ_QEP_SR22 */ +void eqepForceInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QFRC |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_force_interrupt () function */ + +/** @brief Reads capture period latch + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_024 */ +/* DesignId : EQEP_DesignId_024 */ +/* Requirements : CONQ_QEP_SR23 */ +uint16 eqepReadCapturePeriodLatch( eqepBASE_t * eqep ) +{ + return eqep->QCPRDLAT; +} /*end of eQEP_read_capture_period_latch () function */ + +/** @brief Reads timer latch + * @param[in] eqep Handle to QEP object + * @return Timer value + */ +/* SourceId : EQEP_SourceId_025 */ +/* DesignId : EQEP_DesignId_025 */ +/* Requirements : CONQ_QEP_SR24 */ +uint16 eqepReadCaptureTimerLatch( eqepBASE_t * eqep ) +{ + return eqep->QCTMRLAT; +} /*end of eQEP_read_capture_timer_latch () function */ + +/** @brief Reads interrupt flag value + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Which interrupt to interrogate + * @return Interrupt flag value + */ +/* SourceId : EQEP_SourceId_064 */ +/* DesignId : EQEP_DesignId_064 */ +/* Requirements : CONQ_QEP_SR25 */ +uint16 eqepReadInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + return ( uint16 ) ( eqep->QFLG & ( uint16 ) QEINT_type ); +} /*end of eQEP_read_interrupt_flag () function */ + +/** @brief Reads position compare register + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_026 */ +/* DesignId : EQEP_DesignId_026 */ +/* Requirements : CONQ_QEP_SR26 */ +uint32 eqepReadPosnCompare( eqepBASE_t * eqep ) +{ + return eqep->QPOSCMP; +} /*end of eQEP_read_posn_compare () function */ + +/** @brief Reads position counter + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_027 */ +/* DesignId : EQEP_DesignId_027 */ +/* Requirements : CONQ_QEP_SR27 */ +uint32 eqepReadPosnCount( eqepBASE_t * eqep ) +{ + return eqep->QPOSCNT; +} /*end of eQEP_read_posn_count () function */ + +/** @brief Reads position counter value index pulse latch register + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_028 */ +/* DesignId : EQEP_DesignId_028 */ +/* Requirements : CONQ_QEP_SR28 */ +uint32 eqepReadPosnIndexLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSILAT; +} /*end of eQEP_read_posn_index_latch () function */ + +/** @brief Reads position counter value + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_029 */ +/* DesignId : EQEP_DesignId_029 */ +/* Requirements : CONQ_QEP_SR29 */ +uint32 eqepReadPosnLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSLAT; +} /*end of eQEP_read_posn_latch () function */ + +/** @brief Reads position strobe latch + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_030 */ +/* DesignId : EQEP_DesignId_030 */ +/* Requirements : CONQ_QEP_SR30 */ +uint32 eqepReadPosnStrobeLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSSLAT; +} /*end of eQEP_read_posn_strobe_latch () function */ + +/** @brief Reads status register + * @param[in] eqep Handle to QEP object + * @return Status register value + */ +/* SourceId : EQEP_SourceId_031 */ +/* DesignId : EQEP_DesignId_031 */ +/* Requirements : CONQ_QEP_SR31 */ +uint16 eqepReadStatus( eqepBASE_t * eqep ) +{ + return eqep->QEPSTS; +} /*end of eqepReadStatus () function */ + +/** @brief Resets counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_032 */ +/* DesignId : EQEP_DesignId_032 */ +/* Requirements : CONQ_QEP_SR32 */ +void eqepResetCounter( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_QPEN; + + return; +} /*end of eqepResetCounter () function */ + +/** @brief Sets capture latch mode + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Qclm capture latch mode + */ +/* SourceId : EQEP_SourceId_033 */ +/* DesignId : EQEP_DesignId_033 */ +/* Requirements : CONQ_QEP_SR33 */ +void eqepSetCaptureLatchMode( eqepBASE_t * eqep, QEPCTL_Qclm_t QEPCTL_Qclm ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_QCLM; + eqep->QEPCTL |= QEPCTL_Qclm; + + return; +} /*end of eqepSetCaptureLatchMode () function */ + +/** @brief Sets capture period + * @param[in] eqep Handle to QEP object + * @param[in] period Capture period + */ +/* SourceId : EQEP_SourceId_034 */ +/* DesignId : EQEP_DesignId_034 */ +/* Requirements : CONQ_QEP_SR34 */ +void eqepSetCapturePeriod( eqepBASE_t * eqep, uint16 period ) +{ + eqep->QCPRD = period; + + return; +} /*end of eqepSetCapturePeriod () function */ + +/** @brief Sets capture pre-scaler + * @param[in] eqep Handle to QEP object + * @param[in] QCAPCTL_Ccps Capture pre-scaler + */ +/* SourceId : EQEP_SourceId_035 */ +/* DesignId : EQEP_DesignId_035 */ +/* Requirements : CONQ_QEP_SR35 */ +void eqepSetCapturePrescale( eqepBASE_t * eqep, QCAPCTL_Ccps_t QCAPCTL_Ccps ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_CCPS; + eqep->QCAPCTL |= QCAPCTL_Ccps; +} /*end of eqepSetCapturePrescale () function */ + +/** @brief Sets emulation control + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Freesoft Emulation control bits + */ +/* SourceId : EQEP_SourceId_036 */ +/* DesignId : EQEP_DesignId_036 */ +/* Requirements : CONQ_QEP_SR36 */ +void eqepSetEmuControl( eqepBASE_t * eqep, QEPCTL_Freesoft_t QEPCTL_Freesoft ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_FREESOFT; + eqep->QEPCTL |= QEPCTL_Freesoft; + + return; +} /*end of eqepSetEmuControl () function */ + +/** @brief Sets external clock rate + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Xcr External clock rate + */ +/* SourceId : EQEP_SourceId_037 */ +/* DesignId : EQEP_DesignId_037 */ +/* Requirements : CONQ_QEP_SR37 */ +void eqepSetExtClockRate( eqepBASE_t * eqep, eQEP_Xcr_t eQEP_Xcr ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_XCR; + eqep->QDECCTL |= ( uint16 ) eQEP_Xcr; + + return; +} /*end of eqepSetExtClockRate () function */ + +/** @brief Sets the event which initializes the counter register + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Iei Index event + */ +/* SourceId : EQEP_SourceId_038 */ +/* DesignId : EQEP_DesignId_038 */ +/* Requirements : CONQ_QEP_SR38 */ +void eqepSetIndexEventInit( eqepBASE_t * eqep, QEPCTL_Iei_t QEPCTL_Iei ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_IEI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Iei; + + return; +} /*end of eqepSetIndexEventInit () function */ + +/** @brief Sets the index event which latches the position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Iel Latch event + */ +/* SourceId : EQEP_SourceId_039 */ +/* DesignId : EQEP_DesignId_039 */ +/* Requirements : CONQ_QEP_SR39 */ +void eqepSetIndexEventLatch( eqepBASE_t * eqep, QEPCTL_Iel_t QEPCTL_Iel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_IEL; + eqep->QEPCTL |= QEPCTL_Iel; + + return; +} /*end of eqepSetIndexEventLatch */ + +/** @brief Sets index polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qip Index polarity + */ +/* SourceId : EQEP_SourceId_040 */ +/* DesignId : EQEP_DesignId_040 */ +/* Requirements : CONQ_QEP_SR40 */ +void eqepSetIndexPolarity( eqepBASE_t * eqep, eQEP_Qip_t eQEP_Qip ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QIP; + eqep->QDECCTL |= eQEP_Qip; + + return; +} /*end of eqepSetIndexPolarity () function */ + +/** @brief Sets max position count + * @param[in] eqep Handle to QEP object + * @param[in] max_count Maximum counter value + */ +/* SourceId : EQEP_SourceId_041 */ +/* DesignId : EQEP_DesignId_041 */ +/* Requirements : CONQ_QEP_SR41 */ +void eqepSetMaxPosnCount( eqepBASE_t * eqep, uint32 max_count ) +{ + eqep->QPOSMAX = max_count; + + return; +} /*end of eqepSetMaxPosnCount () function */ + +/** @brief Sets output pulse width when a match occur + * @param[in] eqep Handle to QEP object + * @param[in] pulse_width Pulse width value + */ +/* SourceId : EQEP_SourceId_042 */ +/* DesignId : EQEP_DesignId_042 */ +/* Requirements : CONQ_QEP_SR42 */ +void eqepSetPosnComparePulseWidth( eqepBASE_t * eqep, uint16 pulse_width ) +{ + uint16 pulse_width_masked; + + pulse_width_masked = pulse_width & 4095U; + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCSPW; + eqep->QPOSCTL |= pulse_width_masked; + + return; +} /*end of eqepSetPosnComparePulseWidth () function */ + +/** @brief Sets position compare shadow load mode + * @param[in] eqep Handle to QEP object + * @param[in] QPOSCTL_Pcload PC load event + */ +/* SourceId : EQEP_SourceId_043 */ +/* DesignId : EQEP_DesignId_043 */ +/* Requirements : CONQ_QEP_SR43 */ +void eqepSetPosnCompareShadowLoad( eqepBASE_t * eqep, QPOSCTL_Pcload_t QPOSCTL_Pcload ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCLOAD; + eqep->QPOSCTL |= ( uint16 ) QPOSCTL_Pcload; + + return; +} /*end of eqepSetPosnCompareShadowLoad () function */ + +/** @brief Sets position counter reset mode + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Pcrm Position counter reset mode + */ +/* SourceId : EQEP_SourceId_044 */ +/* DesignId : EQEP_DesignId_044 */ +/* Requirements : CONQ_QEP_SR44 */ +void eqepSetPosnCountResetMode( eqepBASE_t * eqep, QEPCTL_Pcrm_t QEPCTL_Pcrm ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_PCRM; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Pcrm; + + return; +} /*end of eqepSetPosnCountResetMode () function */ + +/** @brief Sets initial position counter value + * @param[in] eqep Handle to QEP object + * @param[in] init_count initial counter value + */ +/* SourceId : EQEP_SourceId_045 */ +/* DesignId : EQEP_DesignId_045 */ +/* Requirements : CONQ_QEP_SR45 */ +void eqepSetPosnInitCount( eqepBASE_t * eqep, uint32 init_count ) +{ + eqep->QPOSINIT = init_count; + + return; +} /*end of eqepSetPosnInitCount () function */ + +/** @brief Selects whether index or strobe pin is used for sync output + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_SPsel Selected pin + */ +/* SourceId : EQEP_SourceId_046 */ +/* DesignId : EQEP_DesignId_046 */ +/* Requirements : CONQ_QEP_SR47 */ +void eqepSetSelectSyncPin( eqepBASE_t * eqep, eQEP_Spsel_t eQEP_SPsel ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SPSEL; + eqep->QDECCTL |= ( uint16 ) eQEP_SPsel; + + return; +} /*end of eQEP_set_select_sync_pin () function */ + +/** @brief Determines if software initialization of position counter enabled + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Swi Enable/disable position counter initialization + */ +/* SourceId : EQEP_SourceId_047 */ +/* DesignId : EQEP_DesignId_047 */ +/* Requirements : CONQ_QEP_SR48 */ +void eqepSetSoftInit( eqepBASE_t * eqep, QEPCTL_Swi_t QEPCTL_Swi ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SWI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Swi; + + return; +} /*end of eQEP_set_soft_init () function */ + +/** @brief Determines strobe initialization of position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sei Strobe initialization of position counter (disabled, + * rising edge of QEPI) or rising/falling depending on direction + */ +/* SourceId : EQEP_SourceId_048 */ +/* DesignId : EQEP_DesignId_048 */ +/* Requirements : CONQ_QEP_SR49 */ +void eqepSetStrobeEventInit( eqepBASE_t * eqep, QEPCTL_Sei_t QEPCTL_Sei ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Sei; + + return; +} /*end of eQEP_set_strobe_event_init () function */ + +/** @brief Sets up strobe latch of position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sel Sets strobe latch of position counter + */ +/* SourceId : EQEP_SourceId_049 */ +/* DesignId : EQEP_DesignId_049 */ +/* Requirements : CONQ_QEP_SR50 */ +void eqepSetStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= QEPCTL_Sel; + + return; +} /*end of eQEP_set_strobe_event_latch () function */ + +/** @brief Sets up strobe polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qsp Strobe polarity + */ +/* SourceId : EQEP_SourceId_050 */ +/* DesignId : EQEP_DesignId_050 */ +/* Requirements : CONQ_QEP_SR51 */ +void eqepSetStrobePolarity( eqepBASE_t * eqep, eQEP_Qsp_t eQEP_Qsp ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QSP; + eqep->QDECCTL |= eQEP_Qsp; + + return; +} /*end of eqepSetStrobePolarity () function */ + +/** @brief Sets up swapping of A/B channels + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Swap Swap/don't swap A/B channels + */ +/* SourceId : EQEP_SourceId_051 */ +/* DesignId : EQEP_DesignId_051 */ +/* Requirements : CONQ_QEP_SR52 */ +void eqepSetSwapQuadInputs( eqepBASE_t * eqep, eQEP_Swap_t eQEP_Swap ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SWAP; + eqep->QDECCTL |= ( uint16 ) eQEP_Swap; + + return; +} /*end of eqepSetSwapQuadInputs () function */ + +/** @brief Sets sync output compare polarity + * @param[in] eqep Handle to QEP object + * @param[in] QPOSCTL_Pcpol Polarity of sync output + */ +/* SourceId : EQEP_SourceId_052 */ +/* DesignId : EQEP_DesignId_052 */ +/* Requirements : CONQ_QEP_SR53 */ +void eqepSetSynchOutputComparePolarity( eqepBASE_t * eqep, QPOSCTL_Pcpol_t QPOSCTL_Pcpol ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCPOL; + eqep->QPOSCTL |= ( uint16 ) QPOSCTL_Pcpol; + + return; +} /*end of eqepSetSynchOutputComparePolarity () function */ + +/** @brief Sets unit timer period + * @param[in] eqep Handle to QEP object + * @param[in] unit_period Unit period + */ +/* SourceId : EQEP_SourceId_053 */ +/* DesignId : EQEP_DesignId_053 */ +/* Requirements : CONQ_QEP_SR54 */ +void eqepSetUnitPeriod( eqepBASE_t * eqep, uint32 unit_period ) +{ + eqep->QUPRD = unit_period; + + return; +} /*end of eqepSetUnitPeriod () function */ + +/** @brief Sets unit timer prescaling + * @param[in] eqep Handle to QEP object + * @param[in] QCAPCTL_Upps Unit timer prescaling + */ +/* SourceId : EQEP_SourceId_054 */ +/* DesignId : EQEP_DesignId_054 */ +/* Requirements : CONQ_QEP_SR55 */ +void eqepSetUnitPosnPrescale( eqepBASE_t * eqep, QCAPCTL_Upps_t QCAPCTL_Upps ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_UPPS; + eqep->QCAPCTL |= ( uint16 ) QCAPCTL_Upps; + + return; +} /*end of eqepSetUnitPosnPrescale () function */ + +/** @brief Sets watchdog period + * @param[in] eqep Handle to QEP object + * @param[in] watchdog_period Watchdog period + */ +/* SourceId : EQEP_SourceId_055 */ +/* DesignId : EQEP_DesignId_055 */ +/* Requirements : CONQ_QEP_SR56 */ +void eqepSetWatchdogPeriod( eqepBASE_t * eqep, uint16 watchdog_period ) +{ + eqep->QWDPRD = watchdog_period; + + return; +} /*end of eqepSetWatchdogPeriod () function */ + +/** @brief Sets strobe event latch + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sel Sets strobe latch of position counter + */ +/* SourceId : EQEP_SourceId_056 */ +/* DesignId : EQEP_DesignId_056 */ +/* Requirements : CONQ_QEP_SR57 */ +void eqepSetupStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Sel; + + return; +} /*end of eqepSetupStrobeEventLatch () function */ + +/** @brief Sets A polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qap Channel A polarity + */ +/* SourceId : EQEP_SourceId_057 */ +/* DesignId : EQEP_DesignId_057 */ +/* Requirements : CONQ_QEP_SR58 */ +void eqepSetAPolarity( eqepBASE_t * eqep, eQEP_Qap_t eQEP_Qap ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QAP; + eqep->QDECCTL |= ( uint16 ) eQEP_Qap; + + return; +} /*end of eqepSetAPolarity () function */ + +/** @brief Sets B polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qbp Channel B polarity + */ +/* SourceId : EQEP_SourceId_058 */ +/* DesignId : EQEP_DesignId_058 */ +/* Requirements : CONQ_QEP_SR59 */ +void eqepSetBPolarity( eqepBASE_t * eqep, eQEP_Qbp_t eQEP_Qbp ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QBP; + eqep->QDECCTL |= ( uint16 ) eQEP_Qbp; + + return; +} /*end of eQEP_set_B_polarity () function */ + +/** @brief Set QEP counting mode + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qsrc Sets QEP counting mode + */ +/* SourceId : EQEP_SourceId_059 */ +/* DesignId : EQEP_DesignId_059 */ +/* Requirements : CONQ_QEP_SR60 */ +void eqepSetQEPSource( eqepBASE_t * eqep, eQEP_Qsrc_t eQEP_Qsrc ) +{ + /* set the value */ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QSRC; + eqep->QDECCTL |= ( uint16 ) eQEP_Qsrc; + + return; +} /*end of eQEP_set_eQEP_source () function */ + +/** @brief Writes a value to the position compare register + * @param[in] eqep Handle to QEP object + * @param[in] posn Position compare register value + */ +/* SourceId : EQEP_SourceId_060 */ +/* DesignId : EQEP_DesignId_060 */ +/* Requirements : CONQ_QEP_SR61 */ +void eqepWritePosnCompare( eqepBASE_t * eqep, uint32 posn ) +{ + eqep->QPOSCMP = posn; + + return; +} /*end of eQEP_write_posn_compare () function */ + +/** @fn void eqep1GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EQEP_SourceId_061 */ +/* DesignId : EQEP_DesignId_061 */ +/* Requirements : CONQ_QEP_SR64 */ +void eqep1GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_QPOSINIT = EQEP1_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP1_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP1_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP1_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP1_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP1_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP1_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP1_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP1_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP1_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG1->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG1->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG1->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG1->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG1->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG1->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG1->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG1->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG1->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG1->QEINT; + } +} + +/** @fn void eqep2GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EQEP_SourceId_062 */ +/* DesignId : EQEP_DesignId_062 */ +/* Requirements : CONQ_QEP_SR65 */ +void eqep2GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_QPOSINIT = EQEP2_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP2_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP2_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP2_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP2_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP2_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP2_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP2_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP2_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP2_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG2->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG2->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG2->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG2->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG2->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG2->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG2->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG2->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG2->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG2->QEINT; + } +} + +/*end of file*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c new file mode 100644 index 00000000000..b5bb5023b4d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c @@ -0,0 +1,273 @@ +/** @file errata.c + * @brief Errata workaround Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Errata workaround API's + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "errata.h" +#include "sys_core.h" +#include "sys_pmu.h" + +/** @fn void errataFailNotification(uint32 flag) + * @brief Errata fail service routine + * + * This function is called if there is a errata workaround fail with appropriate flag + */ +void errataFailNotification( uint32 flag ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/** @fn void errata_PBIST_4(void) + * @brief Workaround for the Errata PBIST#4. + * + * This function is workaround for Errata PBIST#4. + * This function is designed to initialize the ROMs using the PBIST controller. + * The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM. + * This function should be called at startup after system init before using the ROMs. + * + * @note : This Function uses register's which are not exposed to users through + * TRM , to run custom algorithm. User can use this function as Black box. + * + */ +void errata_PBIST_4( void ) +{ + volatile uint32 i = 0U; + uint8 ROM_count; + sint32 PBIST_wait_done_loop; + uint32 pmuCalibration, pmuCount; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* PMU calibration */ + _pmuInit_(); + _pmuEnableCountersGlobal_(); + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + _pmuStopCounters_( pmuCYCLE_COUNTER ); + pmuCalibration = _pmuGetCycleCount_(); + + /* ROM_init Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + *( volatile uint32 * ) 0xFFFF0400U = 0x0000000AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000EE0AU; + + /* Loop for Executing PBIST ROM and STC ROM */ + for( ROM_count = 0U; ROM_count < 4U; ROM_count++ ) + { + PBIST_wait_done_loop = 0; + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST Clocks did not disable */ + if( pbistREG->PACT != 0x0U ) + { + errataFailNotification( PBISTERRATA_FAIL3 ); + } + else + { + /* PBIST ROM clock frequency = GCLK frequency /4 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000205U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000020AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /* wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + for( i = 0U; i < ( 64U + ( 64U * 1U ) ); i++ ) + { /* Wait */ + } + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Load PBIST ALGO to initialize the ROMs */ + *( volatile uint32 * ) 0xFFFFE400U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE440U = 0x00000025U; + *( volatile uint32 * ) 0xFFFFE404U = 0x62400001U; + *( volatile uint32 * ) 0xFFFFE444U = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE408U = 0x00068003U; + *( volatile uint32 * ) 0xFFFFE448U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE40CU = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE44CU = 0x00006860U; + *( volatile uint32 * ) 0xFFFFE410U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE450U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE540U = 0x000003E8U; + *( volatile uint32 * ) 0xFFFFE550U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE530U = 0x00000000U; + + /* SELECT ROM */ + if( ROM_count == 0U ) + { + /* SELECT STC1 ROM1 */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x07B3FFFFU; + pbistREG->RAMT = 0x0E01200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else if( ROM_count == 1U ) + { + /* SELECT STC1 ROM2 */ + *( volatile uint32 * ) 0xFFFFE520U = 0xA88FA473U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00BD719DU; + pbistREG->RAMT = 0x0E02200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 2U; /* CSR */ + } + else if( ROM_count == 2U ) + { + /* SELECT STC2 ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x06E3FFFFU; + pbistREG->RAMT = 0x0F01200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else if( ROM_count == 3U ) + { + /* SELECT PBIST ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0x00000002U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00000000U; + pbistREG->RAMT = 0x0101200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else + { + /* Empty */ + } + + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 0U ] = 8U; /* CMS */ + + /* Start PMU counter */ + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + + /* PBIST_RUN */ + pbistREG->rsvd1[ 1U ] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->MSTCGSTAT & 0x1U ) != 0x1U ) + { + } /* Wait */ + + /* Stop PMU counter */ + _pmuStopCounters_( pmuCYCLE_COUNTER ); + + /* Get CPU cycle count */ + pmuCount = _pmuGetCycleCount_(); + + /* Calculate PBIST test complete time in ROM Clock */ + /* 4 - Divide value ( Default is 4 in HALCoGen) */ + /* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */ + pmuCount = pmuCount - pmuCalibration; + PBIST_wait_done_loop = ( ( sint32 ) pmuCount / 4 ) - 1000; + + /* Check PBIST status results (Address, Status, Count, etc...) */ + if( ( pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 + | pbistREG->FSRDL1 | pbistREG->rsvd4[ 0U ] | pbistREG->rsvd4[ 1U ] ) + != 0U ) + { + /* PBIST Failure for the Algorithm chosen above */ + errataFailNotification( PBISTERRATA_FAIL1 ); + } + + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected */ + if( ( PBIST_wait_done_loop <= 20 ) || ( PBIST_wait_done_loop >= 200 ) ) + { + errataFailNotification( PBISTERRATA_FAIL2 ); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + } + } /* ROM Loop */ + + /* ROM restore default setup */ + /* (must be completed before continuing) */ + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA0AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA05U; + *( volatile uint32 * ) 0xFFFF0400U = 0x00000005U; + + _pmuDisableCountersGlobal_(); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c new file mode 100644 index 00000000000..3fada34da53 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c @@ -0,0 +1,374 @@ +/** @file errata_SSWF021_45.c + * @brief errata for PLLs + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "errata_SSWF021_45_defs.h" +#include "errata_SSWF021_45.h" + +static uint32 check_frequency( uint32 cnt1_clksrc ); +static uint32 disable_plls( uint32 plls ); + +/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count) +* @brief This handles the errata for PLL1 and PLL2. This function is called in device +startup +* +* @param[in] count : Number of retries until both PLLs are locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_both_plls( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while( ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + || ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) == 0U ) ) ) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count) +* @brief This handles the errata for PLL1. This function is called in device startup +* +* @param[in] count : Number of retries until both PLL1 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll1( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1; + /* Check for PLL1 valid or PLL1 slip*/ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count) +* @brief This handles the errata for PLL2. This function is called in device startup +* +* @param[in] count : Number of retries until PLL2 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll2( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL2; + /* Check for PLL2 valid or PLL2 slip */ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0 ] & ESM_SR4_PLL2SLIP ) == 0U ) ) + { + /* Wait */ + } + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 check_frequency(uint32 cnt1_clksrc) + * @brief This function checks for the PLL frequency. + * + * @param[in] cnt1_clksrc : Clock source for Counter1 + * 0U - PLL1 (clock source 0) + * 1U - PLL2 (clock source 1) + * + * @return DCC Error status + * 0 - DCC error has not occurred + * 1 - DCC error has occurred + */ +static uint32 check_frequency( uint32 cnt1_clksrc ) +{ + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0x5U | /** Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + dccREG1->STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) cnt1_clksrc; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + while( dccREG1->STAT == 0U ) + { + /* Wait */ + } + return ( dccREG1->STAT & 0x01U ); +} +/** @fn uint32 disable_plls(uint32 plls) + * @brief This function disables plls and clears the respective ESM flags. + * + * @param[in] plls : Clock source for Counter1 + * 2U - PLL1 + * 40U - PLL2 + * + * @return failCode + * 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 4 = The workaround function was not able to disable at least one of the PLLs. + * The most likely reason is that a PLL is already being used as a clock source. This can + * be caused by the workaround function being called from the wrong place in the code. + */ +static uint32 disable_plls( uint32 plls ) +{ + uint32 timeout, failCode; + + systemREG1->CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout--; + while( ( ( systemREG1->CSVSTAT & ( plls ) ) != 0U ) && ( timeout != 0U ) ) + { + /* Clear ESM and GLBSTAT PLL slip flags */ + systemREG1->GBLSTAT = 0x00000300U; + + if( ( plls & SYS_CLKSRC_PLL1 ) == SYS_CLKSRC_PLL1 ) + { + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + } + if( ( plls & SYS_CLKSRC_PLL2 ) == SYS_CLKSRC_PLL2 ) + { + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + } + timeout--; + /* Wait */ + } + if( timeout == 0U ) + { + failCode = 4U; + } + else + { + failCode = 0U; + } + return failCode; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c new file mode 100644 index 00000000000..8cf11f1fcda --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c @@ -0,0 +1,1068 @@ +/** @file esm.c + * @brief Esm Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the Esm driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "esm.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void esmInit(void) + * @brief Initializes Esm Driver + * + * This function initializes the Esm driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : ESM_SourceId_001 */ +/* DesignId : ESM_DesignId_001 */ +/* Requirements : CONQ_ESM_SR2 */ +void esmInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Disable error pin channels */ + esmREG->DEPAPR1 = 0xFFFFFFFFU; + esmREG->IEPCR4 = 0xFFFFFFFFU; + esmREG->IEPCR7 = 0xFFFFFFFFU; + + /** - Disable interrupts */ + esmREG->IECR1 = 0xFFFFFFFFU; + esmREG->IECR4 = 0xFFFFFFFFU; + esmREG->IECR7 = 0xFFFFFFFFU; + + /** - Clear error status flags */ + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SSR2 = 0xFFFFFFFFU; + esmREG->SR1[ 2U ] = 0xFFFFFFFFU; + + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + + /** - Setup LPC preload */ + esmREG->LTCPR = 16384U - 1U; + + /** - Reset error pin */ + if( esmREG->EPSR == 0U ) + { + esmREG->EKR = 0x00000005U; + } + else + { + esmREG->EKR = 0x00000000U; + } + + /** - Clear interrupt level */ + esmREG->ILCR1 = 0xFFFFFFFFU; + esmREG->ILCR4 = 0xFFFFFFFFU; + esmREG->ILCR7 = 0xFFFFFFFFU; + + /** - Set interrupt level */ + esmREG->ILSR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable error pin channels */ + esmREG->EEPAPR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable interrupts */ + esmREG->IESR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn uint32 esmError(void) + * @brief Return Error status + * + * @return The error status + * + * Returns the error status. + */ +/* SourceId : ESM_SourceId_002 */ +/* DesignId : ESM_DesignId_002 */ +/* Requirements : CONQ_ESM_SR3 */ +uint32 esmError( void ) +{ + uint32 status; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + status = esmREG->EPSR; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_003 */ +/* DesignId : ESM_DesignId_003 */ +/* Requirements : CONQ_ESM_SR4 */ +void esmEnableError( uint64 channels ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + esmREG->IEPSR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->EEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_004 */ +/* DesignId : ESM_DesignId_004 */ +/* Requirements : CONQ_ESM_SR4 */ +void esmEnableErrorUpper( uint64 channels ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + esmREG->IEPSR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_005 */ +/* DesignId : ESM_DesignId_005 */ +/* Requirements : CONQ_ESM_SR5 */ +void esmDisableError( uint64 channels ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + esmREG->IEPCR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->DEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_006 */ +/* DesignId : ESM_DesignId_006 */ +/* Requirements : CONQ_ESM_SR5 */ +void esmDisableErrorUpper( uint64 channels ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + esmREG->IEPCR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} +/** @fn void esmTriggerErrorPinReset(void) + * @brief Trigger error pin reset and switch back to normal operation + * + * Trigger error pin reset and switch back to normal operation. + */ +/* SourceId : ESM_SourceId_007 */ +/* DesignId : ESM_DesignId_007 */ +/* Requirements : CONQ_ESM_SR6 */ +void esmTriggerErrorPinReset( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + esmREG->EKR = 5U; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void esmActivateNormalOperation(void) + * @brief Activate normal operation + * + * Activates normal operation mode. + */ +/* SourceId : ESM_SourceId_008 */ +/* DesignId : ESM_DesignId_008 */ +/* Requirements : CONQ_ESM_SR7 */ +void esmActivateNormalOperation( void ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + esmREG->EKR = 0U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_009 */ +/* DesignId : ESM_DesignId_009 */ +/* Requirements : CONQ_ESM_SR8 */ +void esmEnableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + esmREG->IESR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IESR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_010 */ +/* DesignId : ESM_DesignId_010 */ +/* Requirements : CONQ_ESM_SR8 */ +void esmEnableInterruptUpper( uint64 channels ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + esmREG->IESR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} +/** @fn void esmDisableInterrupt(uint32 channels) + * @brief Disable Group 1 Channels Interrupts for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_011 */ +/* DesignId : ESM_DesignId_011 */ +/* Requirements : CONQ_ESM_SR9 */ +void esmDisableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + esmREG->IECR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IECR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void esmDisableInterrupt(uint64 channels) + * @brief Disable Group 1 Channels Interrupts for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_012 */ +/* DesignId : ESM_DesignId_012 */ +/* Requirements : CONQ_ESM_SR9 */ +void esmDisableInterruptUpper( uint64 channels ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + esmREG->IECR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels for channels 0-63 + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_013 */ +/* DesignId : ESM_DesignId_013 */ +/* Requirements : CONQ_ESM_SR10 */ +void esmSetInterruptLevel( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + esmREG->ILCR4 = ( uint32 ) ( ( ( channels & ( ~flags ) ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILSR4 = ( uint32 ) ( ( ( channels & flags ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILCR1 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR1 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels for channels 64-95 + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_014 */ +/* DesignId : ESM_DesignId_014 */ +/* Requirements : CONQ_ESM_SR10 */ +void esmSetInterruptLevelUpper( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + esmREG->ILCR7 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR7 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatus(uint32 group, uint32 channels) + * @brief Clear Group error status + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_015 */ +/* DesignId : ESM_DesignId_015 */ +/* Requirements : CONQ_ESM_SR14 */ +void esmClearStatus( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + esmREG->SR1[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + if( group == 0U ) + { + esmREG->SR4[ group ] = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatusUpper(uint32 group, uint64 channels) + * @brief Clear Group error status for channels 64-95 + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_016 */ +/* DesignId : ESM_DesignId_016 */ +/* Requirements : CONQ_ESM_SR14 */ +void esmClearStatusUpper( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + esmREG->SR7[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} +/** @fn void esmClearStatusBuffer(uint32 channels) + * @brief Clear Group 2 error status buffer + * + * @param[in] channels - Channel mask + * + * Clear Group 2 error status buffer. + */ +/* SourceId : ESM_SourceId_017 */ +/* DesignId : ESM_DesignId_017 */ +/* Requirements : CONQ_ESM_SR15 */ +void esmClearStatusBuffer( uint32 channels ) +{ + /* USER CODE BEGIN (35) */ + /* USER CODE END */ + + esmREG->SSR2 = channels; + + /* USER CODE BEGIN (36) */ + /* USER CODE END */ +} + +/** @fn void esmSetCounterPreloadValue(uint32 value) + * @brief Set counter preload value + * + * @param[in] value - Counter preload value + * + * Set counter preload value. + */ +/* SourceId : ESM_SourceId_018 */ +/* DesignId : ESM_DesignId_018 */ +/* Requirements : CONQ_ESM_SR11 */ +void esmSetCounterPreloadValue( uint32 value ) +{ + /* USER CODE BEGIN (37) */ + /* USER CODE END */ + + esmREG->LTCPR = value & 0xC000U; + + /* USER CODE BEGIN (38) */ + /* USER CODE END */ +} + +/** @fn uint64 esmGetStatus(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group (Channels from 0-63) + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_019 */ +/* DesignId : ESM_DesignId_019 */ +/* Requirements : CONQ_ESM_SR12 */ +uint64 esmGetStatus( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + if( group == 0U ) + { + ESM_ESTATUS4 = esmREG->SR4[ group ]; + } + else + { + ESM_ESTATUS4 = 0U; + } + ESM_ESTATUS1 = esmREG->SR1[ group ]; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( ( uint64 ) ESM_ESTATUS4 ) << 32U ) | ( uint64 ) ESM_ESTATUS1 ) + & channels; + + /* USER CODE BEGIN (40) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusUpper(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group (Channels from 64-95) + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_020 */ +/* DesignId : ESM_DesignId_020 */ +/* Requirements : CONQ_ESM_SR12 */ +uint64 esmGetStatusUpper( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS7 = esmREG->SR7[ group ]; + + /* USER CODE BEGIN (41) */ + /* USER CODE END */ + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( uint64 ) ESM_ESTATUS7 ) & channels; + + /* USER CODE BEGIN (42) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusBuffer(uint64 channels) + * @brief Return Group 2 channel x Error status buffer + * + * @param[in] channels - Error Channels + * + * @return The channels status + * + * Returns the group 2 buffered status of selected channels. + */ +/* SourceId : ESM_SourceId_021 */ +/* DesignId : ESM_DesignId_021 */ +/* Requirements : CONQ_ESM_SR17 */ +uint32 esmGetStatusBuffer( uint32 channels ) +{ + uint32 status; + + /* USER CODE BEGIN (43) */ + /* USER CODE END */ + status = esmREG->SSR2 & channels; + + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmEnterSelfTest(void) + * @brief Return ESM Self test status + * + * @return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_022 */ +/* DesignId : ESM_DesignId_022 */ +/* Requirements : CONQ_ESM_SR16 */ +esmSelfTestFlag_t esmEnterSelfTest( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (45) */ + /* USER CODE END */ + + uint32 errPinStat = esmREG->EPSR & 0x1U; + uint32 esmKeyReg = esmREG->EKR; + if( ( errPinStat == 0x0U ) && ( esmKeyReg == 0x0U ) ) + { + status = esmSelfTest_NotStarted; + } + else + { + esmREG->EKR = 0xAU; + status = esmSelfTest_Active; + if( ( esmREG->EPSR & 0x1U ) != 0x0U ) + { + status = esmSelfTest_Failed; + } + esmREG->EKR = 0x5U; + } + + /* USER CODE BEGIN (46) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmSelfTestStatus(void) + * @brief Return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_023 */ +/* DesignId : ESM_DesignId_023 */ +/* Requirements : CONQ_ESM_SR17 */ +esmSelfTestFlag_t esmSelfTestStatus( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (47) */ + /* USER CODE END */ + + if( ( esmREG->EPSR & 0x1U ) == 0x0U ) + { + if( esmREG->EKR == 0x5U ) + { + status = esmSelfTest_Active; + } + else + { + status = esmSelfTest_Failed; + } + } + else + { + status = esmSelfTest_Passed; + } + + /* USER CODE BEGIN (48) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +/* SourceId : ESM_SourceId_024 */ +/* DesignId : ESM_DesignId_024 */ +/* Requirements : CONQ_ESM_SR18 */ +void esmGetConfigValue( esm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE; + config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE; + config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE; + config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE; + config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE; + config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE; + config_reg->CONFIG_IEPSR7 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR7 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR7 = ESM_ILSR4_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1; + config_reg->CONFIG_IESR1 = esmREG->IESR1; + config_reg->CONFIG_ILSR1 = esmREG->ILSR1; + config_reg->CONFIG_LTCPR = esmREG->LTCPR; + config_reg->CONFIG_EKR = esmREG->EKR; + config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4; + config_reg->CONFIG_IESR4 = esmREG->IESR4; + config_reg->CONFIG_ILSR4 = esmREG->ILSR4; + config_reg->CONFIG_IEPSR7 = esmREG->IEPSR7; + config_reg->CONFIG_IESR7 = esmREG->IESR7; + config_reg->CONFIG_ILSR7 = esmREG->ILSR7; + } +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/** @fn void esmHighInterrupt(void) + * @brief High Level Interrupt for ESM + */ + +/* SourceId : ESM_SourceId_025 */ +/* DesignId : ESM_DesignId_025 */ +/* Requirements : CONQ_ESM_SR19 */ +void esmHighInterrupt( void ) +{ + /* Note : Group 1 Error */ + /* 1 to 32 -> channel 0 to 31 */ + /* 65 to 96 -> channel 32 to 63 */ + /* 129 to 160 -> channel 64 to 95 */ + /* Note : Group 2 Error */ + /* 33 to 64 -> channel 0 to 31 */ + + uint32 vec = esmREG->IOFFHR - 1U; + + /* USER CODE BEGIN (50) */ + /* USER CODE END */ + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( esmREG, ( vec ) ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( esmREG, ( vec - 32U ) ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( esmREG, ( vec - 32U ) ); + } + else if( ( vec >= 128U ) && ( vec < 160U ) ) + { + esmREG->SR7[ 0U ] = ( uint32 ) 1U << ( vec - 128U ); + esmGroup1Notification( esmREG, ( vec - 96U ) ); + } + else + { + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c new file mode 100644 index 00000000000..9acbe119a7d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c @@ -0,0 +1,2393 @@ +/** @file etpwm.c + * @brief ETPWM Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "etpwm.h" +#include "pinmux.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void etpwmInit(void) + * @brief Initializes the eTPWM Driver + * + * This function initializes the eTPWM module. + * + * @note This function sets the time-base counters in up-count mode. + * Application can configure the module in a different mode using other functions in + * this driver.(Sample code provided in the examples folder) In that case, application + * need not call etpwmInit function. pinmuxInit needs to be called before this function. + * + */ +/* SourceId : ETPWM_SourceId_001 */ +/* DesignId : ETPWM_DesignId_001 */ +/* Requirements : CONQ_EPWM_SR2 */ +void etpwmInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** @b initialize @b ETPWM1 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG1->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG1->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG1->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG1->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG1->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG1->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG1->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG1->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0u << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG1->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG1->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG1->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG1->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG1 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG1->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG1->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG1->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG1->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG1->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG1->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM2 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG2->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG2->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG2->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG2->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG2->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG2->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG2->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG2->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG2->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG2->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG2->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG2->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG2 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG2->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG2->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG2->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG2->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG2->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG2->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM3 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG3->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG3->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG3->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG3->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG3->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG3->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG3->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG3->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG3->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG3->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG3->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG3->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG3 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG3->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG3->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG3->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG3->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG3->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG3->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM4 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG4->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG4->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG4->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG4->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG4->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG4->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG4->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG4->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG4->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG4->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG4->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG4 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG4->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG4->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG4->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG4->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG4->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG4->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM5 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG5->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG5->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG5->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG5->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG5->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG5->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG5->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG5->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG5->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG5->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG5->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG5->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG5 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG5->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG5->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG5->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG5->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG5->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG5->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM6 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG6->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG6->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG6->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG6->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG6->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG6->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG6->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG6->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG6->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG6->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG6->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG6->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG6 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG6->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG6->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG6->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG6->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG6->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG6->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM7 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG7->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG7->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG7->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG7->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG7->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG7->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG7->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG7->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG7->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG7->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG7->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG7 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG7->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG7->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG7->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG7->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG7->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG7->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/** @fn void etpwmStartTBCLK() + * @brief Start the time-base clocks of all eTPWMx modules + * + * This function starts the time-base clocks of all eTPWMx modules. + */ +/* SourceId : ETPWM_SourceId_002 */ +/* DesignId : ETPWM_DesignId_002 */ +/* Requirements : CONQ_EPWM_SR45 */ +void etpwmStartTBCLK( void ) +{ + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMUX[ 166U ] = ( pinMuxReg->PINMUX[ 166U ] + & PINMUX_ETPWM_TBCLK_SYNC_MASK ) + | ( PINMUX_ETPWM_TBCLK_SYNC_ON ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmStopTBCLK() + * @brief Stop the time-base clocks of all eTPWMx modules + * + * This function stops the time-base clocks of all eTPWMx modules. + */ +/* SourceId : ETPWM_SourceId_003 */ +/* DesignId : ETPWM_DesignId_003 */ +/* Requirements : CONQ_EPWM_SR46 */ +void etpwmStopTBCLK( void ) +{ + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMUX[ 166U ] = ( pinMuxReg->PINMUX[ 166U ] + & PINMUX_ETPWM_TBCLK_SYNC_MASK ) + | ( PINMUX_ETPWM_TBCLK_SYNC_OFF ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t + * hspclkdiv) + * @brief Sets the Time-base Clock divider + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param clkdiv Time-base clock divider + * - ClkDiv_by_1 + * - ClkDiv_by_2 + * - ClkDiv_by_4 + * - ClkDiv_by_8 + * - ClkDiv_by_16 + * - ClkDiv_by_32 + * - ClkDiv_by_64 + * - ClkDiv_by_128 + * @param hspclkdiv High Speed Time-base clock divider + * - HspClkDiv_by_1 + * - HspClkDiv_by_2 + * - HspClkDiv_by_4 + * - HspClkDiv_by_6 + * - HspClkDiv_by_8 + * - HspClkDiv_by_10 + * - HspClkDiv_by_12 + * - HspClkDiv_by_14 + * + * This function sets the TimeBase Clock and the High Speed time base clock divider + * TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV) + */ +/* SourceId : ETPWM_SourceId_004 */ +/* DesignId : ETPWM_DesignId_004 */ +/* Requirements : CONQ_EPWM_SR3 */ +void etpwmSetClkDiv( etpwmBASE_t * etpwm, + etpwmClkDiv_t clkdiv, + etpwmHspClkDiv_t hspclkdiv ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x1F80U; + etpwm->TBCTL |= ( uint16 ) clkdiv | ( uint16 ) hspclkdiv; +} + +/** @fn void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) + * @brief Sets period of timebase counter + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param period 16-bit Time-base period + * + * This function sets period of timebase counter + */ +/* SourceId : ETPWM_SourceId_005 */ +/* DesignId : ETPWM_DesignId_005 */ +/* Requirements : CONQ_EPWM_SR4 */ +void etpwmSetTimebasePeriod( etpwmBASE_t * etpwm, uint16 period ) +{ + etpwm->TBPRD = period; +} + +/** @fn void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) + * @brief Sets timebase counter + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param count 16-bit Counter value + * + * This function sets the timebase counter + */ +/* SourceId : ETPWM_SourceId_006 */ +/* DesignId : ETPWM_DesignId_006 */ +/* Requirements : CONQ_EPWM_SR5 */ +void etpwmSetCount( etpwmBASE_t * etpwm, uint16 count ) +{ + etpwm->TBCTR = count; +} + +/** @fn void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for time-base period register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for time-base period register + */ +/* SourceId : ETPWM_SourceId_007 */ +/* DesignId : ETPWM_DesignId_007 */ +/* Requirements : CONQ_EPWM_SR6 */ +void etpwmDisableTimebasePeriodShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL |= 0x0008U; +} + +/** @fn void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) + * @brief Enable shadow mode for time-base period register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function enables shadow mode for time-base period register + */ +/* SourceId : ETPWM_SourceId_008 */ +/* DesignId : ETPWM_DesignId_008 */ +/* Requirements : CONQ_EPWM_SR7 */ +void etpwmEnableTimebasePeriodShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0008U; +} + +/** @fn void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 + * direction) + * @brief Enable counter register load from phase register when a sync event occurs + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param phase Counter value to be loaded when a sync event occurs + * @param direction Direction of the counter after the sync event (Applied only if + * counter is in updown-count mode, ignores otherwise) + * - COUNT_UP + * - COUNT_DOWN + * - Pass 0 if not applied + * + * This function enables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ETPWM_SourceId_009 */ +/* DesignId : ETPWM_DesignId_009 */ +/* Requirements : CONQ_EPWM_SR8 */ +void etpwmEnableCounterLoadOnSync( etpwmBASE_t * etpwm, uint16 phase, uint16 direction ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x2000U; + etpwm->TBCTL |= 0x0004U | direction; + etpwm->TBPHS = phase; +} + +/** @fn void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) + * @brief Disable counter register load from phase register when a sync event occurs + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ETPWM_SourceId_010 */ +/* DesignId : ETPWM_DesignId_010 */ +/* Requirements : CONQ_EPWM_SR9 */ +void etpwmDisableCounterLoadOnSync( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0004U; +} + +/** @fn void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncMode_t syncmode) + * @brief Set the source of EPWMxSYNCO signal + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param syncOutSrc Synchronization Output Select + * - SyncOut_EPWMxSYNCI + * - SyncOut_CtrEqZero + * - SyncOut_CtrEqCmpB + * - SyncOut_Disable + * + * This function sets the source of synchronization output signal + */ +/* SourceId : ETPWM_SourceId_011 */ +/* DesignId : ETPWM_DesignId_011 */ +/* Requirements : CONQ_EPWM_SR10 */ +void etpwmSetSyncOut( etpwmBASE_t * etpwm, etpwmSyncOut_t syncOutSrc ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0030U; + etpwm->TBCTL |= syncOutSrc; +} + +/** @fn void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) + * @brief Set the time-base counter mode + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param countermode Counter Mode + * - CounterMode_Up + * - Countermode_Down + * - CounterMode_UpDown + * - CounterMode_Stop + * + * This function sets the time-base counter mode of operation. + */ +/* SourceId : ETPWM_SourceId_012 */ +/* DesignId : ETPWM_DesignId_012 */ +/* Requirements : CONQ_EPWM_SR11 */ +void etpwmSetCounterMode( etpwmBASE_t * etpwm, etpwmCounterMode_t countermode ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0003U; + etpwm->TBCTL |= countermode; +} + +/** @fn void etpwmTriggerSWSync(etpwmBASE_t *etpwm) + * @brief Trigger a software synchronization pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function triggers a software synchronization pulse. SWFSYNC is valid (operates) + * only when EPWMxSYNCI as SyncOut + */ +/* SourceId : ETPWM_SourceId_013 */ +/* DesignId : ETPWM_DesignId_013 */ +/* Requirements : CONQ_EPWM_SR12 */ +void etpwmTriggerSWSync( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL |= 0x0040U; +} + +/** @fn void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) + * @brief Set the pulse width modulation (ETPWM) run mode + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param runmode Run mode + * - RunMode_SoftStopAfterIncr : Stop after the next time-base + * counter increment + * - RunMode_SoftStopAfterDecr : Stop after the next time-base + * counter decrement + * - RunMode_SoftStopAfterCycle : Stop when counter completes a whole + * cycle + * - RunMode_FreeRun : Free-run + * + * This function select the behaviour of the ePWM time-base counter during emulation + * events + */ +/* SourceId : ETPWM_SourceId_014 */ +/* DesignId : ETPWM_DesignId_014 */ +/* Requirements : CONQ_EPWM_SR13 */ +void etpwmSetRunMode( etpwmBASE_t * etpwm, etpwmRunMode_t runmode ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0xC000U; + etpwm->TBCTL |= runmode; +} + +/** @fn void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) + * @brief Set the Compare A value + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param value 16-bit Compare A value + * + * This function sets the compare A value + */ +/* SourceId : ETPWM_SourceId_015 */ +/* DesignId : ETPWM_DesignId_015 */ +/* Requirements : CONQ_EPWM_SR14 */ +void etpwmSetCmpA( etpwmBASE_t * etpwm, uint16 value ) +{ + etpwm->CMPA = value; +} + +/** @fn void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) + * @brief Set the Compare B value + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param value 16-bit Compare B value + * + * This function sets the compare B register + */ +/* SourceId : ETPWM_SourceId_016 */ +/* DesignId : ETPWM_DesignId_016 */ +/* Requirements : CONQ_EPWM_SR15 */ +void etpwmSetCmpB( etpwmBASE_t * etpwm, uint16 value ) +{ + etpwm->CMPB = value; +} + +/** @fn void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) + * @brief Enable shadow mode for Compare A register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param loadmode Active Counter-Compare A (CMPA) Load From Shadow Select Mode + * - LoadMode_CtrEqZero : Load on CTR = Zero + * - LoadMode_CtrEqPeriod : Load on CTR = PRD + * - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD + * - LoadMode_Freeze : Freeze (no loads possible) + * + * This function enables shadow mode for Compare A register + */ +/* SourceId : ETPWM_SourceId_017 */ +/* DesignId : ETPWM_DesignId_017 */ +/* Requirements : CONQ_EPWM_SR16 */ +void etpwmEnableCmpAShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode ) +{ + etpwm->CMPCTL &= ( uint16 ) ~( uint16 ) 0x0013U; + etpwm->CMPCTL |= loadmode; +} + +/** @fn void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for Compare A register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for Compare A register + */ +/* SourceId : ETPWM_SourceId_018 */ +/* DesignId : ETPWM_DesignId_018 */ +/* Requirements : CONQ_EPWM_SR17 */ +void etpwmDisableCmpAShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->CMPCTL |= 0x0010U; +} + +/** @fn void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) + * @brief Enable shadow mode for Compare B register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param loadmode Active Counter-Compare B (CMPB) Load From Shadow Select Mode + * - LoadMode_CtrEqZero : Load on CTR = Zero + * - LoadMode_CtrEqPeriod : Load on CTR = PRD + * - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD + * - LoadMode_Freeze : Freeze (no loads possible) + * + * This function enables shadow mode for Compare B register + */ +/* SourceId : ETPWM_SourceId_019 */ +/* DesignId : ETPWM_DesignId_019 */ +/* Requirements : CONQ_EPWM_SR18 */ +void etpwmEnableCmpBShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode ) +{ + etpwm->CMPCTL &= ( uint16 ) ~( uint16 ) 0x004CU; + etpwm->CMPCTL |= ( uint16 ) ( ( uint16 ) loadmode << 2U ); +} + +/** @fn void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for Compare B register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for Compare B register + */ +/* SourceId : ETPWM_SourceId_020 */ +/* DesignId : ETPWM_DesignId_020 */ +/* Requirements : CONQ_EPWM_SR19 */ +void etpwmDisableCmpBShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->CMPCTL |= 0x0040U; +} + +/** @fn void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t + * actionqualconfig) + * @brief Configure Action Qualifier submodule to generate PWMA + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param actionqualconfig Action Qualifier configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmActionQualConfig_t configA + * configA.CtrEqZero_Action = ActionQual_Set + * configA.CtrEqPeriod_Action = ActionQual_Disabled + * configA.CtrEqCmpAUp_Action = ActionQual_Clear + * configA.CtrEqCmpADown_Action = ActionQual_Disabled + * configA.CtrEqCmpBUp_Action = ActionQual_Disabled + * configA.CtrEqCmpBDown_Action = ActionQual_Disabled + * void etpwmSetActionQualPwmA(etpwmREG1, configA) + * + * This function configures Action Qualifier submodule to generate PWMA + */ +/* SourceId : ETPWM_SourceId_021 */ +/* DesignId : ETPWM_DesignId_021 */ +/* Requirements : CONQ_EPWM_SR20 */ +void etpwmSetActionQualPwmA( etpwmBASE_t * etpwm, + etpwmActionQualConfig_t actionqualconfig ) +{ + etpwm + ->AQCTLA = ( ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqZero_Action << 0U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqPeriod_Action << 2U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpAUp_Action << 4U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpADown_Action + << 6U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBUp_Action << 8U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBDown_Action + << 10U ) ); +} + +/** @fn void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t + * actionqualconfig) + * @brief Configure Action Qualifier submodule to generate PWMB + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param actionqualconfig Action Qualifier configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmActionQualConfig_t configB + * configB.CtrEqZero_Action = ActionQual_Set + * configB.CtrEqPeriod_Action = ActionQual_Disabled + * configB.CtrEqCmpAUp_Action = ActionQual_Disabled + * configB.CtrEqCmpADown_Action = ActionQual_Disabled + * configB.CtrEqCmpBUp_Action = ActionQual_Clear + * configB.CtrEqCmpBDown_Action = ActionQual_Disabled + * void etpwmSetActionQualPwmB(etpwmREG1, configB) + * + * This function configures Action Qualifier submodule to generate PWMB + */ +/* SourceId : ETPWM_SourceId_022 */ +/* DesignId : ETPWM_DesignId_022 */ +/* Requirements : CONQ_EPWM_SR21 */ +void etpwmSetActionQualPwmB( etpwmBASE_t * etpwm, + etpwmActionQualConfig_t actionqualconfig ) +{ + etpwm + ->AQCTLB = ( ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqZero_Action << 0U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqPeriod_Action << 2U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpAUp_Action << 4U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpADown_Action + << 6U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBUp_Action << 8U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBDown_Action + << 10U ) ); +} + +/** @fn void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) + * @brief Enable DeadBand module + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param deadbandconfig DeadBand configuration + * + * This function configures Action Qualifier submodule to generate PWMB + */ +/* SourceId : ETPWM_SourceId_023 */ +/* DesignId : ETPWM_DesignId_023 */ +/* Requirements : CONQ_EPWM_SR22 */ +void etpwmEnableDeadBand( etpwmBASE_t * etpwm, etpwmDeadBandConfig_t deadbandconfig ) +{ + uint16 halfCycleMask = ( uint16 ) ( ( deadbandconfig.halfCycleEnable ) ? 0x8000U + : 0U ); + etpwm->DBCTL = ( ( uint16 ) deadbandconfig.inputmode + | ( uint16 ) deadbandconfig.outputmode + | ( uint16 ) deadbandconfig.polarity | halfCycleMask ); +} + +/** @fn void etpwmDisableDeadband(etpwmBASE_t *etpwm) + * @brief Disable DeadBand module + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * + * This function bypasses the Deadband submodule + */ +/* SourceId : ETPWM_SourceId_024 */ +/* DesignId : ETPWM_DesignId_024 */ +/* Requirements : CONQ_EPWM_SR23 */ +void etpwmDisableDeadband( etpwmBASE_t * etpwm ) +{ + etpwm->DBCTL = 0U; +} + +/** @fn void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) + * @brief Sets the rising and falling edge delay + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param Rdelay 16-bit rising edge delay in terms of TCLK ticks + * @param Fdelay 16-bit falling edge delay in terms of TCLK ticks + * + * This function sets the rising and falling edge delays in the DeadBand submodule + */ +/* SourceId : ETPWM_SourceId_025 */ +/* DesignId : ETPWM_DesignId_025 */ +/* Requirements : CONQ_EPWM_SR24 */ +void etpwmSetDeadBandDelay( etpwmBASE_t * etpwm, uint16 Rdelay, uint16 Fdelay ) +{ + etpwm->DBRED = Rdelay; + etpwm->DBFED = Fdelay; +} + +/** @fn void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) + * @brief Enable chopping + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param choppingconfig Chopper submodule configuration + * + * This function enables the chopper submodule with the given configuration + */ +/* SourceId : ETPWM_SourceId_026 */ +/* DesignId : ETPWM_DesignId_026 */ +/* Requirements : CONQ_EPWM_SR25 */ +void etpwmEnableChopping( etpwmBASE_t * etpwm, etpwmChoppingConfig_t choppingconfig ) +{ + etpwm->PCCTL = ( ( uint16 ) 0x0001U | ( uint16 ) choppingconfig.oswdth + | ( uint16 ) choppingconfig.freq | ( uint16 ) choppingconfig.duty ); +} + +/** @fn void etpwmDisableChopping(etpwmBASE_t *etpwm) + * @brief Disable chopping + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables the chopper submodule + */ +/* SourceId : ETPWM_SourceId_027 */ +/* DesignId : ETPWM_DesignId_027 */ +/* Requirements : CONQ_EPWM_SR26 */ +void etpwmDisableChopping( etpwmBASE_t * etpwm ) +{ + etpwm->PCCTL = 0U; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) + * @brief Select the tripzone zources + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param sources Trip zone sources (sources can be ORed) + * - CycleByCycle_TZ1 : Enable TZ1 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ2 : Enable TZ2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ3 : Enable TZ3 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ4 : Enable TZ4 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ5 : Enable TZ5 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ6 : Enable TZ6 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCAEVT2 : Enable DCAEVT2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCBEVT2 : Enable DCBEVT2 as a Cycle-by-cycle trip + * source + * - OneShot_TZ1 : Enable TZ1 as a One-shot trip source + * - OneShot_TZ2 : Enable TZ2 as a One-shot trip source + * - OneShot_TZ3 : Enable TZ3 as a One-shot trip source + * - OneShot_TZ4 : Enable TZ4 as a One-shot trip source + * - OneShot_TZ5 : Enable TZ5 as a One-shot trip source + * - OneShot_TZ6 : Enable TZ6 as a One-shot trip source + * - OneShot_DCAEVT1 : Enable DCAEVT1 as a One-shot trip source + * - OneShot_DCBEVT1 : Enable DCBEVT1 as a One-shot trip source + * + * This function selects the tripzone sources for cycle-by-cycle and one-shot trip + */ +/* SourceId : ETPWM_SourceId_028 */ +/* DesignId : ETPWM_DesignId_028 */ +/* Requirements : CONQ_EPWM_SR27 */ +void etpwmEnableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources ) +{ + etpwm->TZSEL |= sources; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) + * @brief Disable the tripzone zources + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param sources Trip zone sources (sources can be ORed) + * - CycleByCycle_TZ1 : Disable TZ1 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ2 : Disable TZ2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ3 : Disable TZ3 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ4 : Disable TZ4 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ5 : Disable TZ5 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ6 : Disable TZ6 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCAEVT2 : Disable DCAEVT2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCBEVT2 : Disable DCBEVT2 as a Cycle-by-cycle trip + * source + * - OneShot_TZ1 : Disable TZ1 as a One-shot trip source + * - OneShot_TZ2 : Disable TZ2 as a One-shot trip source + * - OneShot_TZ3 : Disable TZ3 as a One-shot trip source + * - OneShot_TZ4 : Disable TZ4 as a One-shot trip source + * - OneShot_TZ5 : Disable TZ5 as a One-shot trip source + * - OneShot_TZ6 : Disable TZ6 as a One-shot trip source + * - OneShot_DCAEVT1 : Disable DCAEVT1 as a One-shot trip source + * - OneShot_DCBEVT1 : Disable DCBEVT1 as a One-shot trip source + * + * This function disables the tripzone sources for cycle-by-cycle or one-shot trip + */ +/* SourceId : ETPWM_SourceId_029 */ +/* DesignId : ETPWM_DesignId_029 */ +/* Requirements : CONQ_EPWM_SR28 */ +void etpwmDisableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources ) +{ + etpwm->TZSEL &= ( uint16 ) ~( uint16 ) sources; +} + +/** @fn void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t + * tripactionconfig) + * @brief Set the action for each trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param tripactionconfig Trip action configuration + * + * This function sets the action for each trip event + */ +/* SourceId : ETPWM_SourceId_030 */ +/* DesignId : ETPWM_DesignId_030 */ +/* Requirements : CONQ_EPWM_SR29 */ +void etpwmSetTripAction( etpwmBASE_t * etpwm, etpwmTripActionConfig_t tripactionconfig ) +{ + etpwm->TZCTL = ( ( uint16 ) ( ( uint16 ) tripactionconfig.TripEvent_ActionOnPWMA + << 0U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.TripEvent_ActionOnPWMB + << 2U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCAEVT1_ActionOnPWMA + << 4U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCAEVT2_ActionOnPWMA + << 6U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCBEVT1_ActionOnPWMB + << 8U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCBEVT2_ActionOnPWMB + << 10U ) ); +} + +/** @fn void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) + * @brief Enables interrupt(EPWMx_TZINT) for the trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param interrupts Interrupts to be enabled (Interrupts can be ORed) + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function enables interrupt(EPWMx_TZINT) for the trip event + */ +/* SourceId : ETPWM_SourceId_031 */ +/* DesignId : ETPWM_DesignId_031 */ +/* Requirements : CONQ_EPWM_SR30 */ +void etpwmEnableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts ) +{ + etpwm->TZEINT |= interrupts; +} + +/** @fn void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) + * @brief Disables interrupt(EPWMx_TZINT) for the trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param interrupts Trip Interrupts to be disabled (Interrupts can be ORed) + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function disables interrupt(EPWMx_TZINT) for the trip event + */ +/* SourceId : ETPWM_SourceId_032 */ +/* DesignId : ETPWM_DesignId_032 */ +/* Requirements : CONQ_EPWM_SR31 */ +void etpwmDisableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts ) +{ + etpwm->TZEINT &= ( uint16 ) ~( uint16 ) interrupts; +} + +/** @fn void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) + * @brief Clears the trip event flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param trips Trip events + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function clears the trip event / Digital Compare output event flag + */ +/* SourceId : ETPWM_SourceId_033 */ +/* DesignId : ETPWM_DesignId_033 */ +/* Requirements : CONQ_EPWM_SR32 */ +void etpwmClearTripCondition( etpwmBASE_t * etpwm, etpwmTrip_t trips ) +{ + etpwm->TZCLR = trips; +} + +/** @fn void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) + * @brief Clears the trip interrupt flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function clears the trip interrupt flag + */ +/* SourceId : ETPWM_SourceId_034 */ +/* DesignId : ETPWM_DesignId_034 */ +/* Requirements : CONQ_EPWM_SR33 */ +void etpwmClearTripInterruptFlag( etpwmBASE_t * etpwm ) +{ + etpwm->TZCLR = 1U; +} + +/** @fn void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) + * @brief Force a trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param trip Trip events + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function forces a trip event / Digital Compare trip event via software + */ +/* SourceId : ETPWM_SourceId_035 */ +/* DesignId : ETPWM_DesignId_035 */ +/* Requirements : CONQ_EPWM_SR34 */ +void etpwmForceTripEvent( etpwmBASE_t * etpwm, etpwmTrip_t trip ) +{ + etpwm->TZFRC = trip; +} + +/** @fn void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ADC Start of Conversion A pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMxSOCA Selection Options + * - DCAEVT1 : DCAEVT1.soc event + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMxSOCA Period Select + * - EventPeriod_FirstEvent : Generate SOCA pulse on the first + * event + * - EventPeriod_SecondEvent : Generate SOCA pulse on the second + * event + * - EventPeriod_ThirdEvent : Generate SOCA pulse on the third + * event + * + * This function enables ADC Start of Conversion A pulse + */ +/* SourceId : ETPWM_SourceId_036 */ +/* DesignId : ETPWM_DesignId_036 */ +/* Requirements : CONQ_EPWM_SR35 */ +void etpwmEnableSOCA( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0xF0FFU; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 11U ) + | ( uint16 ) ( ( uint16 ) eventsource << 8U ); + + etpwm->ETPS &= 0xF0FFU; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 8U ); +} + +/** @fn void etpwmDisableSOCA(etpwmBASE_t *etpwm) + * @brief Disable ADC Start of Conversion A pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables ADC Start of Conversion A pulse + */ +/* SourceId : ETPWM_SourceId_037 */ +/* DesignId : ETPWM_DesignId_037 */ +/* Requirements : CONQ_EPWM_SR36 */ +void etpwmDisableSOCA( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0xF0FFU; +} + +/** @fn void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ADC Start of Conversion B pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMxSOCB Selection Options + * - DCBEVT1 : DCBEVT1.soc event + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMxSOCB Period Select + * - EventPeriod_FirstEvent : Generate SOCB pulse on the first + * event + * - EventPeriod_SecondEvent : Generate SOCB pulse on the second + * event + * - EventPeriod_ThirdEvent : Generate SOCB pulse on the third + * event + * + * This function enables ADC Start of Conversion B pulse + */ +/* SourceId : ETPWM_SourceId_038 */ +/* DesignId : ETPWM_DesignId_038 */ +/* Requirements : CONQ_EPWM_SR37 */ +void etpwmEnableSOCB( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0x0FFFU; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 15U ) + | ( uint16 ) ( ( uint16 ) eventsource << 12U ); + + etpwm->ETPS &= 0x0FFFU; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 12U ); +} + +/** @fn void etpwmDisableSOCB(etpwmBASE_t *etpwm) + * @brief Disable ADC Start of Conversion B pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables ADC Start of Conversion B pulse + */ +/* SourceId : ETPWM_SourceId_039 */ +/* DesignId : ETPWM_DesignId_039 */ +/* Requirements : CONQ_EPWM_SR38 */ +void etpwmDisableSOCB( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0x0FFFU; +} + +/** @fn void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ePWM Interrupt + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMx_INT Selection Options + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMx_INT Period Select + * - EventPeriod_FirstEvent : Generate interrupt on the first + * event + * - EventPeriod_SecondEvent : Generate interrupt on the second + * event + * - EventPeriod_ThirdEvent : Generate interrupt on the third + * event + * + * This function enables EPWMx_INT generation + */ +/* SourceId : ETPWM_SourceId_040 */ +/* DesignId : ETPWM_DesignId_040 */ +/* Requirements : CONQ_EPWM_SR39 */ +void etpwmEnableInterrupt( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0xFFF0U; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 3U ) + | ( uint16 ) ( ( uint16 ) eventsource << 0U ); + + etpwm->ETPS &= 0xFFF0U; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 0U ); +} + +/** @fn void etpwmDisableInterrupt(etpwmBASE_t *etpwm) + * @brief Disable ePWM Interrupt + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables EPWMx_INT generation + */ +/* SourceId : ETPWM_SourceId_041 */ +/* DesignId : ETPWM_DesignId_041 */ +/* Requirements : CONQ_EPWM_SR40 */ +void etpwmDisableInterrupt( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0xFFF0U; +} + +/** @fn uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) + * @brief Return event status flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @return event status flag + * Bit 0: ePWM Interrupt(EPWMx_INT) Status Flag + * Bit 2: ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag + * Bit 3: ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag + * + * This function returns the event status flags + */ +/* SourceId : ETPWM_SourceId_042 */ +/* DesignId : ETPWM_DesignId_042 */ +/* Requirements : CONQ_EPWM_SR47 */ +uint16 etpwmGetEventStatus( etpwmBASE_t * etpwm ) +{ + return etpwm->ETFLG; +} + +/** @fn void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) + * @brief Clear event status flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param events status flag (flags can be ORed) + * - Event_Interrupt + * - Event_SOCA + * - Event_SOCB + * + * This function clears the event status flags + */ +/* SourceId : ETPWM_SourceId_043 */ +/* DesignId : ETPWM_DesignId_043 */ +/* Requirements : CONQ_EPWM_SR48 */ +void etpwmClearEventFlag( etpwmBASE_t * etpwm, etpwmEvent_t events ) +{ + etpwm->ETCLR = events; +} + +/** @fn void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) + * @brief Force an event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @return events (events can be ORed) + * - Event_Interrupt + * - Event_SOCA + * - Event_SOCB + * + * This function forces an event + */ +/* SourceId : ETPWM_SourceId_044 */ +/* DesignId : ETPWM_DesignId_044 */ +/* Requirements : CONQ_EPWM_SR49 */ +void etpwmTriggerEvent( etpwmBASE_t * etpwm, etpwmEvent_t events ) +{ + etpwm->ETFRC = events; +} + +/** @fn void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, + * etpwmDigitalCompareConfig_t digitalcompareconfig) + * @brief Enable and configure digital compare events + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param digitalcompareconfig Digital Compare modue configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmDigitalCompareConfig_t config1 + * config1.DCAH_src = TZ1 + * config1.DCAL_src = TZ2 + * config1.DCBH_src = TZ1 + * config1.DCBL_src = TZ3 + * config1.DCAEVT1_event = DCAH_High + * config1.DCAEVT2_event = DCAL_High + * config1.DCBEVT1_event = DCBL_High + * config1.DCBEVT2_event = DCBL_High_DCBH_low + * etpwmEnableDigitalCompareEvents(etpwmREG1, config1) + * + * This function enbales and configures the digital compare events. HTis function can + * also be used to disable digital compare events + */ +/* SourceId : ETPWM_SourceId_045 */ +/* DesignId : ETPWM_DesignId_045 */ +/* Requirements : CONQ_EPWM_SR41 */ +void etpwmEnableDigitalCompareEvents( etpwmBASE_t * etpwm, + etpwmDigitalCompareConfig_t digitalcompareconfig ) +{ + etpwm->DCTRIPSEL = ( ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAH_src << 0U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAL_src << 4U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBH_src << 8U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBL_src + << 12U ) ); + + etpwm->TZDCSEL = ( ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAEVT1_event << 0U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAEVT2_event + << 3U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBEVT1_event + << 6U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBEVT2_event + << 9U ) ); +} + +/** @fn void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_046 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm1GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM1_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM1_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM1_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM1_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM1_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM1_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM1_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM1_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM1_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM1_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM1_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM1_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM1_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM1_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM1_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM1_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM1_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM1_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM1_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM1_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM1_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM1_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM1_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM1_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG1->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG1->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG1->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG1->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG1->CMPA; + config_reg->CONFIG_CMPB = etpwmREG1->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG1->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG1->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG1->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG1->DBRED; + config_reg->CONFIG_DBFED = etpwmREG1->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG1->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG1->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG1->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG1->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG1->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG1->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG1->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG1->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG1->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG1->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG1->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG1->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG1->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG1->DCFWINDOWCNT; + } +} + +/** @fn void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_47 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm2GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM2_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM2_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM2_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM2_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM2_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM2_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM2_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM2_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM2_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM2_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM2_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM2_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM2_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM2_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM2_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM2_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM2_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM2_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM2_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM2_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM2_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM2_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM2_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM2_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM2_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG2->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG2->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG2->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG2->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG2->CMPA; + config_reg->CONFIG_CMPB = etpwmREG2->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG2->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG2->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG2->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG2->DBRED; + config_reg->CONFIG_DBFED = etpwmREG2->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG2->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG2->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG2->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG2->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG2->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG2->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG2->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG2->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG2->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG2->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG2->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG2->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG2->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG2->DCFWINDOWCNT; + } +} + +/** @fn void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_048 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm3GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM3_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM3_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM3_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM3_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM3_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM3_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM3_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM3_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM3_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM3_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM3_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM3_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM3_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM3_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM3_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM3_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM3_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM3_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM3_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM3_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM3_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM3_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM3_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM3_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM3_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG3->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG3->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG3->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG3->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG3->CMPA; + config_reg->CONFIG_CMPB = etpwmREG3->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG3->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG3->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG3->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG3->DBRED; + config_reg->CONFIG_DBFED = etpwmREG3->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG3->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG3->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG3->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG3->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG3->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG3->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG3->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG3->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG3->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG3->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG3->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG3->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG3->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG3->DCFWINDOWCNT; + } +} + +/** @fn void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_049 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm4GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM4_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM4_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM4_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM4_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM4_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM4_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM4_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM4_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM4_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM4_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM4_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM4_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM4_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM4_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM4_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM4_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM4_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM4_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM4_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM4_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM4_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM4_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM4_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM4_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM4_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG4->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG4->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG4->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG4->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG4->CMPA; + config_reg->CONFIG_CMPB = etpwmREG4->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG4->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG4->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG4->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG4->DBRED; + config_reg->CONFIG_DBFED = etpwmREG4->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG4->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG4->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG4->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG4->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG4->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG4->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG4->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG4->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG4->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG4->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG4->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG4->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG4->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG4->DCFWINDOWCNT; + } +} + +/** @fn void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_050 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm5GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM5_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM5_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM5_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM5_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM5_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM5_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM5_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM5_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM5_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM5_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM5_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM5_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM5_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM5_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM5_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM5_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM5_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM5_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM5_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM5_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM5_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM5_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM5_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM5_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM5_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG5->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG5->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG5->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG5->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG5->CMPA; + config_reg->CONFIG_CMPB = etpwmREG5->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG5->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG5->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG5->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG5->DBRED; + config_reg->CONFIG_DBFED = etpwmREG5->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG5->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG5->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG5->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG5->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG5->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG5->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG5->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG5->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG5->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG5->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG5->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG5->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG5->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG5->DCFWINDOWCNT; + } +} + +/** @fn void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_051 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm6GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM6_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM6_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM6_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM6_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM6_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM6_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM6_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM6_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM6_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM6_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM6_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM6_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM6_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM6_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM6_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM6_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM6_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM6_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM6_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM6_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM6_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM6_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM6_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM6_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM6_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG6->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG6->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG6->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG6->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG6->CMPA; + config_reg->CONFIG_CMPB = etpwmREG6->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG6->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG6->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG6->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG6->DBRED; + config_reg->CONFIG_DBFED = etpwmREG6->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG6->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG6->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG6->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG6->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG6->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG6->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG6->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG6->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG6->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG6->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG6->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG6->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG6->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG6->DCFWINDOWCNT; + } +} + +/** @fn void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_052 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm7GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM7_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM7_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM7_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM7_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM7_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM7_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM7_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM7_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM7_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM7_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM7_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM7_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM7_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM7_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM7_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM7_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM7_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM7_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM7_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM7_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM7_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM7_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM7_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM7_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG7->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG7->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG7->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG7->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG7->CMPA; + config_reg->CONFIG_CMPB = etpwmREG7->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG7->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG7->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG7->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG7->DBRED; + config_reg->CONFIG_DBFED = etpwmREG7->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG7->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG7->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG7->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG7->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG7->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG7->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG7->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG7->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG7->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG7->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG7->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG7->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG7->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG7->DCFWINDOWCNT; + } +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c new file mode 100644 index 00000000000..1ba9c6cabb9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c @@ -0,0 +1,505 @@ +/** @file gio.c + * @brief GIO Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "gio.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void gioInit(void) + * @brief Initializes the GIO Driver + * + * This function initializes the GIO module and set the GIO ports + * to the initial values. + */ +/* SourceId : GIO_SourceId_001 */ +/* DesignId : GIO_DesignId_001 */ +/* Requirements : CONQ_GIO_SR2 */ +void gioInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** bring GIO module out of reset */ + gioREG->GCR0 = 1U; + gioREG->ENACLR = 0xFFU; + gioREG->LVLCLR = 0xFFU; + + /** @b initialize @b Port @b A */ + + /** - Port A output values */ + gioPORTA->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A direction */ + gioPORTA->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A open drain enable */ + gioPORTA->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown selection */ + gioPORTA->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown enable*/ + gioPORTA->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** @b initialize @b Port @b B */ + + /** - Port B output values */ + gioPORTB->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B direction */ + gioPORTB->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B open drain enable */ + gioPORTB->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown selection */ + gioPORTB->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown enable*/ + gioPORTB->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b interrupts */ + + /** - interrupt polarity */ + gioREG->POL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - interrupt level */ + gioREG->LVLSET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - clear all pending interrupts */ + gioREG->FLG = 0xFFU; + + /** - enable interrupts */ + gioREG->ENASET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir) + * @brief Set Port Direction + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] dir value to write to DIR register + * + * Set the direction of GIO pins at runtime. + */ +/* SourceId : GIO_SourceId_002 */ +/* DesignId : GIO_DesignId_002 */ +/* Requirements : CONQ_GIO_SR3 */ +void gioSetDirection( gioPORT_t * port, uint32 dir ) +{ + port->DIR = dir; +} + +/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * @param[in] value binary value to write to bit + * + * Writes a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_003 */ +/* DesignId : GIO_DesignId_003 */ +/* Requirements : CONQ_GIO_SR4 */ +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( value != 0U ) + { + port->DSET = ( uint32 ) 1U << bit; + } + else + { + port->DCLR = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioSetPort(gioPORT_t *port, uint32 value) + * @brief Write Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] value value to write to port + * + * Writes a value to all pin of a given GIO port + */ +/* SourceId : GIO_SourceId_004 */ +/* DesignId : GIO_DesignId_004 */ +/* Requirements : CONQ_GIO_SR5 */ +void gioSetPort( gioPORT_t * port, uint32 value ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + port->DOUT = value; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit) + * @brief Read Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Reads a the current value from the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_005 */ +/* DesignId : GIO_DesignId_005 */ +/* Requirements : CONQ_GIO_SR8 */ +uint32 gioGetBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return ( port->DIN >> bit ) & 1U; +} + +/** @fn uint32 gioGetPort(gioPORT_t *port) + * @brief Read Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * + * Reads a the current value of a given GIO port + */ +/* SourceId : GIO_SourceId_006 */ +/* DesignId : GIO_DesignId_006 */ +/* Requirements : CONQ_GIO_SR7 */ +uint32 gioGetPort( gioPORT_t * port ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return port->DIN; +} + +/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Toggle a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_007 */ +/* DesignId : GIO_DesignId_007 */ +/* Requirements : CONQ_GIO_SR6 */ +void gioToggleBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( port->DIN & ( uint32 ) ( ( uint32 ) 1U << bit ) ) != 0U ) + { + port->DCLR = ( uint32 ) 1U << bit; + } + else + { + port->DSET = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioEnableNotification(uint32 bit) + * @brief Enable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Enables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_008 */ +/* DesignId : GIO_DesignId_008 */ +/* Requirements : CONQ_GIO_SR9 */ +void gioEnableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENASET = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENASET = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioDisableNotification(uint32 bit) + * @brief Disable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Disables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_009 */ +/* DesignId : GIO_DesignId_009 */ +/* Requirements : CONQ_GIO_SR10 */ +void gioDisableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENACLR = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENACLR = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : GIO_SourceId_010 */ +/* DesignId : GIO_DesignId_010 */ +/* Requirements : CONQ_GIO_SR11 */ +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_INTDET = GIO_INTDET_CONFIGVALUE; + config_reg->CONFIG_POL = GIO_POL_CONFIGVALUE; + config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE; + config_reg->CONFIG_LVLSET = GIO_LVLSET_CONFIGVALUE; + + config_reg->CONFIG_PORTADIR = GIO_PORTADIR_CONFIGVALUE; + config_reg->CONFIG_PORTAPDR = GIO_PORTAPDR_CONFIGVALUE; + config_reg->CONFIG_PORTAPSL = GIO_PORTAPSL_CONFIGVALUE; + config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE; + + config_reg->CONFIG_PORTBDIR = GIO_PORTBDIR_CONFIGVALUE; + config_reg->CONFIG_PORTBPDR = GIO_PORTBPDR_CONFIGVALUE; + config_reg->CONFIG_PORTBPSL = GIO_PORTBPSL_CONFIGVALUE; + config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_INTDET = gioREG->INTDET; + config_reg->CONFIG_POL = gioREG->POL; + config_reg->CONFIG_INTENASET = gioREG->ENASET; + config_reg->CONFIG_LVLSET = gioREG->LVLSET; + + config_reg->CONFIG_PORTADIR = gioPORTA->DIR; + config_reg->CONFIG_PORTAPDR = gioPORTA->PDR; + config_reg->CONFIG_PORTAPSL = gioPORTA->PSL; + config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PORTBDIR = gioPORTB->DIR; + config_reg->CONFIG_PORTBPDR = gioPORTB->PDR; + config_reg->CONFIG_PORTBPSL = gioPORTB->PSL; + config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS; + } +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c new file mode 100644 index 00000000000..8e835f9acf5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c @@ -0,0 +1,2921 @@ +/** @file het.c + * @brief HET Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "het.h" +#include "sys_vim.h" +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Global variables */ + +static const uint32 s_het1pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +static const uint32 s_het2pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het1PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het1PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het2PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het2PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/** @fn void hetInit(void) + * @brief Initializes the het Driver + * + * This function initializes the het 1 module. + */ +/* SourceId : HET_SourceId_001 */ +/* DesignId : HET_DesignId_001 */ +/* Requirements : CONQ_HET_SR10 */ +void hetInit( void ) +{ + /** @b initialize @b HET */ + + /** - Set HET pins default output value */ + hetREG1 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG1->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG1->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG1->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG1->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG1->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG1->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG1->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG1->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG1->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM1, + ( const void * ) het1PROGRAM, + sizeof( het1PROGRAM ) ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG1->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG1->INTENAC = 0xFFFFFFFFU; + hetREG1->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG1->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @b initialize @b HET 2 */ + + /** - Set HET pins default output value */ + hetREG2 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG2->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG2->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG2->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG2->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG2->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG2->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG2->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG2->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Release from reset */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM2, + ( const void * ) het2PROGRAM, + sizeof( het2PROGRAM ) ); + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG2->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG2->INTENAC = 0xFFFFFFFFU; + hetREG2->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG2->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Start pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Start the given pwm signal + */ +/* SourceId : HET_SourceId_002 */ +/* DesignId : HET_DesignId_002 */ +/* Requirements : CONQ_HET_SR11 */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control |= 0x00400000U; +} + +/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Stop pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Stop the given pwm signal + */ +/* SourceId : HET_SourceId_003 */ +/* DesignId : HET_DesignId_003 */ +/* Requirements : CONQ_HET_SR12 */ +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control &= ~( uint32 ) 0x00400000U; +} + +/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty) + * @brief Set duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] pwmDuty duty cycle in %. + * + * Sets a new duty cycle on the given pwm signal + */ +/* SourceId : HET_SourceId_004 */ +/* DesignId : HET_DesignId_004 */ +/* Requirements : CONQ_HET_SR13 */ +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + uint32 pwmPeriod = hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U; + pwmPeriod = pwmPeriod >> 7U; + + if( hetRAM == hetRAM1 ) + { + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + if( pwmDuty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( pwmDuty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data = ( ( ( pwmPeriod * pwmDuty ) / 100U ) + << 7U ) + + 128U; +} + +/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) +* @brief Set period +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] signal signal + - duty cycle in %. +* - period period in us. +* +* Sets a new pwm signal +*/ +/* SourceId : HET_SourceId_005 */ +/* DesignId : HET_DesignId_005 */ +/* Requirements : CONQ_HET_SR14 */ +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + float64 pwmPeriod = 0.0F; + + if( hetRAM == hetRAM1 ) + { + pwmPeriod = ( signal.period * 1000.0F ) / 853.333F; + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPeriod = ( signal.period * 1000.0F ) / 853.333F; + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + if( signal.duty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( signal.duty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Data = ( ( ( ( uint32 ) pwmPeriod * signal.duty ) / 100U ) << 7U ) + 128U; + hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data = ( ( uint32 ) pwmPeriod << 7U ) + - 128U; +} + +/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) + * @brief Get duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given pwm signal. + */ +/* SourceId : HET_SourceId_006 */ +/* DesignId : HET_DesignId_006 */ +/* Requirements : CONQ_HET_SR15 */ +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data - 128U ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } +} + +/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_007 */ +/* DesignId : HET_DesignId_007 */ +/* Requirements : CONQ_HET_SR16 */ +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->FLG = notification << ( pwm << 1U ); + hetREG->INTENAS = notification << ( pwm << 1U ); +} + +/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_008 */ +/* DesignId : HET_DesignId_008 */ +/* Requirements : CONQ_HET_SR17 */ +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->INTENAC = notification << ( pwm << 1U ); +} + +/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Resets edge counter to 0 + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Reset edge counter to 0. + */ +/* SourceId : HET_SourceId_009 */ +/* DesignId : HET_DesignId_009 */ +/* Requirements : CONQ_HET_SR19 */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + hetRAM->Instruction[ edge + 17U ].Data = 0U; +} + +/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Get current edge counter value + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Gets current edge counter value. + */ +/* SourceId : HET_SourceId_010 */ +/* DesignId : HET_DesignId_010 */ +/* Requirements : CONQ_HET_SR20 */ +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + return hetRAM->Instruction[ edge + 17U ].Data >> 7U; +} + +/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_011 */ +/* DesignId : HET_DesignId_011 */ +/* Requirements : CONQ_HET_SR21 */ +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->FLG = ( uint32 ) 0x20000U << edge; + hetREG->INTENAS = ( uint32 ) 0x20000U << edge; +} + +/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_012 */ +/* DesignId : HET_DesignId_012 */ +/* Requirements : CONQ_HET_SR22 */ +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->INTENAC = ( uint32 ) 0x20000U << edge; +} + +/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal) + * @brief Get capture signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] cap captured signal: + * - cap0: Captured signal 0 + * - cap1: Captured signal 1 + * - cap2: Captured signal 2 + * - cap3: Captured signal 3 + * - cap4: Captured signal 4 + * - cap5: Captured signal 5 + * - cap6: Captured signal 6 + * - cap7: Captured signal 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given capture signal. + */ +/* SourceId : HET_SourceId_013 */ +/* DesignId : HET_DesignId_013 */ +/* Requirements : CONQ_HET_SR24 */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( cap << 1U ) + 25U ].Data ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( cap << 1U ) + 26U ].Data ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } +} + +/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Resets timestamp + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * + * Resets loop count based timestamp. + */ +/* SourceId : HET_SourceId_014 */ +/* DesignId : HET_DesignId_014 */ +/* Requirements : CONQ_HET_SR25 */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ) +{ + hetRAM->Instruction[ 0U ].Data = 0U; +} + +/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Returns timestamp + * + * Returns loop count based timestamp. + */ +/* SourceId : HET_SourceId_015 */ +/* DesignId : HET_DesignId_015 */ +/* Requirements : CONQ_HET_SR26 */ +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ) +{ + return hetRAM->Instruction[ 57U ].Data; +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_016 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : CONQ_HET_SR29 */ +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET1_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET1_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET1_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET1_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET1_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET1_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET1_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET1_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET1_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET1_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET1_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG1->GCR; + config_reg->CONFIG_PFR = hetREG1->PFR; + config_reg->CONFIG_INTENAS = hetREG1->INTENAS; + config_reg->CONFIG_INTENAC = hetREG1->INTENAC; + config_reg->CONFIG_PRY = hetREG1->PRY; + config_reg->CONFIG_AND = hetREG1->AND; + config_reg->CONFIG_HRSH = hetREG1->HRSH; + config_reg->CONFIG_XOR = hetREG1->XOR; + config_reg->CONFIG_DIR = hetREG1->DIR; + config_reg->CONFIG_PDR = hetREG1->PDR; + config_reg->CONFIG_PULDIS = hetREG1->PULDIS; + config_reg->CONFIG_PSL = hetREG1->PSL; + config_reg->CONFIG_PCR = hetREG1->PCR; + } +} + +/** @fn void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_017 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : CONQ_HET_SR29 */ +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET2_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET2_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET2_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET2_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET2_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET2_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET2_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET2_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET2_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET2_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET2_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET2_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET2_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG2->GCR; + config_reg->CONFIG_PFR = hetREG2->PFR; + config_reg->CONFIG_INTENAS = hetREG2->INTENAS; + config_reg->CONFIG_INTENAC = hetREG2->INTENAC; + config_reg->CONFIG_PRY = hetREG2->PRY; + config_reg->CONFIG_AND = hetREG2->AND; + config_reg->CONFIG_HRSH = hetREG2->HRSH; + config_reg->CONFIG_XOR = hetREG2->XOR; + config_reg->CONFIG_DIR = hetREG2->DIR; + config_reg->CONFIG_PDR = hetREG2->PDR; + config_reg->CONFIG_PULDIS = hetREG2->PULDIS; + config_reg->CONFIG_PSL = hetREG2->PSL; + config_reg->CONFIG_PCR = hetREG2->PCR; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c new file mode 100644 index 00000000000..fb2de140c7b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c @@ -0,0 +1,1005 @@ +/** @file i2c.c + * @brief I2C Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "i2c.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_i2CTransfer + * @brief Interrupt mode globals + * + */ +static struct g_i2cTransfer +{ + uint32 mode; + uint32 length; + uint8 * data; +} g_i2cTransfer_t[ 2U ]; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : I2C_SourceId_001 */ +/* DesignId : I2C_DesignId_001 */ +/* Requirements : CONQ_I2C_SR5 */ +/** @fn void i2cInit(void) + * @brief Initializes the i2c Driver + * + * This function initializes the i2c module. + */ +void i2cInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + /** @b initialize @b I2C1 */ + + /** - i2c Enter reset */ + i2cREG1->MDR = ( uint32 ) ( ( uint32 ) 0U << 5U ); + + /** - set i2c mode */ + i2cREG1->MDR = ( uint32 ) ( ( uint32 ) 0U << 15U ) /* nack mode */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* free running */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* start condition - master mode + only */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* stop condition */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* Master/Slave mode */ + | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) /* Transmitter/receiver */ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) /* xpanded address */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* repeat mode */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* digital loopback */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* start byte - master only */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* free data format */ + | ( uint32 ) ( ( uint32 ) I2C_8_BIT ); /* bit count */ + + /** - set i2c extended mode */ + i2cREG1->EMDR = ( uint32 ) 0U << 1U; /* Ignore Nack Enable/Disable */ + + /** - set i2c Backward Compatibility mode */ + i2cREG1->EMDR |= 0U; + + /** - Disable DMA */ + i2cREG1->DMACR = 0x00U; + + /** - set i2c data count */ + i2cREG1->CNT = 8U; + + /** - disable all interrupts */ + i2cREG1->IMR = 0x00U; + + /** - set prescale */ + i2cREG1->PSC = 8U; + + /** - set clock rate */ + i2cREG1->CKH = 37U; + i2cREG1->CKL = 37U; + + /** - set i2c pins functional mode */ + i2cREG1->PFNC = ( 0U ); + + /** - set i2c pins default output value */ + i2cREG1->DOUT = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG1->DIR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG1->PDR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG1->PDIS = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG1->PSEL = ( uint32 ) ( ( uint32 ) 1U << 1U ) /* sda pin */ + | ( uint32 ) ( 1U ); /* scl pin */ + + /** - set interrupt enable */ + i2cREG1->IMR = ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Address as slave interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Stop Condition detect interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Transmit data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Receive data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Register Access ready interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* No Acknowledgment interrupt */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Arbitration Lost interrupt */ + + i2cREG1->MDR |= ( uint32 ) I2C_RESET_OUT; /* i2c out of reset */ + + /** - initialize global transfer variables */ + g_i2cTransfer_t[ 0U ].mode = ( uint32 ) 0U << 4U; + g_i2cTransfer_t[ 0U ].length = 0U; + + /** @b initialize @b I2C2 */ + + /** - i2c Enter reset */ + i2cREG2->MDR = ( uint32 ) ( ( uint32 ) 0U << 5U ); + + /** - set i2c mode */ + i2cREG2->MDR = ( uint32 ) ( ( uint32 ) 0U << 15U ) /* nack mode */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* free running */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* start condition - master mode + only */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* stop condition */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* Master/Slave mode */ + | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) /* Transmitter/receiver */ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) /* Expanded address */ + | ( uint32 ) ( ( uint32 ) 0 << 7U ) /* repeat mode */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* digital loopback */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* start byte - master only */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* free data format */ + | ( uint32 ) ( I2C_2_BIT ); /* bit count */ + + /** - set i2c extended mode */ + i2cREG2->EMDR = ( uint32 ) 0U << 1U; /* Ignore Nack Enable/Disable */ + + /** - set i2c Backward Compatibility mode */ + i2cREG2->EMDR |= 0U; + + /** - Disable DMA */ + i2cREG2->DMACR = 0x00U; + + /** - set i2c data count */ + i2cREG2->CNT = 8U; + + /** - disable all interrupts */ + i2cREG2->IMR = 0x00U; + + /** - set prescale */ + i2cREG2->PSC = 8U; + + /** - set clock rate */ + i2cREG2->CKH = 37U; + i2cREG2->CKL = 37U; + + /** - set i2c pins functional mode */ + i2cREG2->PFNC = ( 0U ); + + /** - set i2c pins default output value */ + i2cREG2->DOUT = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG2->DIR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG2->PDR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG2->PDIS = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG2->PSEL = ( uint32 ) ( ( uint32 ) 1U << 1U ) /* sda pin */ + | ( uint32 ) ( 1U ); /* scl pin */ + + /** - set interrupt enable */ + i2cREG2->IMR = ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Address as slave interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Stop Condition detect interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Transmit data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Receive data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Register Access ready interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* No Acknowledgment interrupt */ + | ( uint32 ) ( 0U ); /* Arbitration Lost interrupt */ + + i2cREG2->MDR |= ( uint32 ) I2C_RESET_OUT; /* i2c out of reset */ + + /** - initialize global transfer variables */ + g_i2cTransfer_t[ 1U ].mode = ( uint32 ) 0U << 4U; + g_i2cTransfer_t[ 1U ].length = 0U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_002 */ +/* DesignId : I2C_DesignId_002 */ +/* Requirements : CONQ_I2C_SR6 */ +/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd) + * @brief Set I2C Own Address + * @param[in] oadd - I2C Own address (7-bit or 10 -bit address) + * @param[in] i2c - i2c module base address + * Set the Own address of the I2C module. + */ +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ) +{ + i2c->OAR = oadd; /* set own address */ +} + +/* SourceId : I2C_SourceId_003 */ +/* DesignId : I2C_DesignId_003 */ +/* Requirements : CONQ_I2C_SR7 */ +/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd) + * @brief Set Port Direction + * @param[in] sadd - I2C Slave address + * @param[in] i2c - i2c module base address + * Set the Slave address to communicate which is must in Master mode. + */ +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ) +{ + i2c->SAR = sadd; /* set slave address */ +} + +/* SourceId : I2C_SourceId_004 */ +/* DesignId : I2C_DesignId_004 */ +/* Requirements : CONQ_I2C_SR8 */ +/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] i2c - i2c module base address + * @param[in] baud - baudrate in KHz + * + * Change the i2c baudrate at runtime. The I2C module needs to be taken to reset( nIRS=0 + * in I2CMDR) in order to change baud rate. + */ +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ) +{ + uint32 prescale; + uint32 d; + uint32 ck; + float64 vclk = 75.000F * 1000000.0F; + float64 divider = 0.0F; + uint32 temp = 0U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + divider = vclk / 8000000.0F; + prescale = ( uint32 ) divider - 1U; + + if( prescale >= 2U ) + { + d = 5U; + } + else + { + d = ( prescale != 0U ) ? 6U : 7U; + } + + temp = 2U * baud * 1000U * ( prescale + 1U ); + divider = vclk / ( ( float64 ) temp ); + ck = ( uint32 ) divider - d; + + i2c->PSC = prescale; + i2c->CKH = ck; + i2c->CKL = ck; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_005 */ +/* DesignId : I2C_DesignId_015 */ +/* Requirements : CONQ_I2C_SR20 */ +/** @fn void i2cSetStart(i2cBASE_t *i2c) + * @brief Set i2c start condition + * @param[in] i2c - i2c module base address + * Set i2c to generate a start bit (Only in Master mode) + */ +void i2cSetStart( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + i2c->MDR |= ( uint32 ) I2C_START_COND; /* set start condition */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_006 */ +/* DesignId : I2C_DesignId_016 */ +/* Requirements : CONQ_I2C_SR21 */ +/** @fn void i2cSetStop(i2cBASE_t *i2c) + * @brief Set i2c stop condition + * @param[in] i2c - i2c module base address + * Set i2c to generate a stop bit (Only in Master mode) + */ +void i2cSetStop( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + i2c->MDR |= ( uint32 ) I2C_STOP_COND; /* generate stop condition */ + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_007 */ +/* DesignId : I2C_DesignId_017 */ +/* Requirements : CONQ_I2C_SR22 */ +/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32 cnt) + * @brief Set i2c data count + * @param[in] i2c - i2c module base address + * @param[in] cnt - data count + * Set i2c count to a transfer value after which the stop condition needs to be + * generated. (Only in Master Mode) + */ +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + i2c->CNT = cnt; /* set i2c count */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_008 */ +/* DesignId : I2C_DesignId_005 */ +/* Requirements : CONQ_I2C_SR9 */ +/** @fn uint32 i2cIsTxReady(i2cBASE_t *i2c) + * @brief Check if Tx buffer empty + * @param[in] i2c - i2c module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 i2cIsTxReady( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return i2c->STR & ( uint32 ) I2C_TX_INT; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_009 */ +/* DesignId : I2C_DesignId_006 */ +/* Requirements : CONQ_I2C_SR10 */ +/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8 byte) + * @brief Send Byte + * @param[in] i2c - i2c module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use i2cIsTxReady to check for Tx buffer empty + * before calling i2cSendByte to avoid waiting. + */ +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_TX_INT ) == 0U ) + { + } /* Wait */ + i2c->DXR = ( uint32 ) byte; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_010 */ +/* DesignId : I2C_DesignId_007 */ +/* Requirements : CONQ_I2C_SR11 */ +/** @fn void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] i2c - i2c module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, i2cSend must not be called again until the + * transfer is complete, when the i2cNotification callback will + * be called. In polling mode, i2cSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( g_i2cTransfer_t[ index ].mode & ( uint32 ) I2C_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + i2c->DXR = ( uint32 ) *g_i2cTransfer_t[ index ].data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data++; + /* Length -1 since one data is written already */ + g_i2cTransfer_t[ index ].length = ( length - 1U ); + /* Enable Transmit Interrupt */ + i2c->IMR |= ( uint32 ) I2C_TX_INT; + } + else + { + /* send the data */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in + * Transmit/Receive polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_TX_INT ) == 0U ) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + i2c->DXR = ( uint32 ) *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; + length--; + } + } + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_011 */ +/* DesignId : I2C_DesignId_008 */ +/* Requirements : CONQ_I2C_SR12 */ +/** @fn uint32 i2cIsRxReady(i2cBASE_t *i2c) + * @brief Check if Rx buffer full + * @param[in] i2c - i2c module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 i2cIsRxReady( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return i2c->STR & ( uint32 ) I2C_RX_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_012 */ +/* DesignId : I2C_DesignId_023 */ +/* Requirements : CONQ_I2C_SR13 */ +/** @fn uint32 i2cIsStopDetected(i2cBASE_t *i2c) + * @brief Check if Stop Condition Detected + * @param[in] i2c - i2c module base address + * + * @return The Stop Condition Detected flag + * + * Checks to see if the Stop Condition Detected flag is set, + * returns 0 if flags not set otherwise will return the Stop + * Condition Detected flag itself. + */ +uint32 i2cIsStopDetected( i2cBASE_t * i2c ) +{ + return i2c->STR & ( uint32 ) I2C_SCD_INT; +} + +/* SourceId : I2C_SourceId_013 */ +/* DesignId : I2C_DesignId_010 */ +/* Requirements : CONQ_I2C_SR15 */ +/** @fn uint32 i2cRxError(i2cBASE_t *i2c) + * @brief Return Rx Error flags + * @param[in] i2c - i2c module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +uint32 i2cRxError( i2cBASE_t * i2c ) +{ + uint32 status = i2c->STR & ( ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + i2c->STR = ( uint32 ) ( ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : I2C_SourceId_014 */ +/* DesignId : I2C_DesignId_009 */ +/* Requirements : CONQ_I2C_SR14 */ +/** @fn void i2cClearSCD(i2cBASE_t *i2c) + * @brief Clears the Stop condition detect flags. + * @param[in] i2c - i2c module base address + * + * This function is called to clear the Stop condition detect(SCD) flag + */ +void i2cClearSCD( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + i2c->STR = ( uint32 ) I2C_SCD_INT; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_015 */ +/* DesignId : I2C_DesignId_011 */ +/* Requirements : CONQ_I2C_SR16 */ +/** @fn uint8 i2cReceiveByte(i2cBASE_t *i2c) + * @brief Receive Byte + * @param[in] i2c - i2c module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use i2cIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +uint8 i2cReceiveByte( i2cBASE_t * i2c ) +{ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_RX_INT ) == 0U ) + { + } /* Wait */ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + return ( ( uint8 ) i2c->DRR ); +} + +/* SourceId : I2C_SourceId_016 */ +/* DesignId : I2C_DesignId_012 */ +/* Requirements : CONQ_I2C_SR17 */ +/** @fn void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] i2c - i2c module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, i2cReceive must not be called + * again until the transfer is complete, when the i2cNotification + * callback will be called. In polling mode, i2cReceive will not + * return until the transfer is complete. + */ +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + if( ( i2c->IMR & ( uint32 ) I2C_RX_INT ) != 0U ) + { + /* we are in interrupt mode */ + /* clear error flags */ + i2c->STR = ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT; + + g_i2cTransfer_t[ index ].length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data = data; + } + else + { /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive + polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_RX_INT ) == 0U ) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( ( uint8 ) i2c->DRR ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_017 */ +/* DesignId : I2C_DesignId_018 */ +/* Requirements : CONQ_I2C_SR24 */ +/** @fn void i2cEnableLoopback(i2cBASE_t *i2c) + * @brief Enable Loopback mode for self test + * @param[in] i2c - i2c module base address + * + * This function enables the Loopback mode for self test. + */ +void i2cEnableLoopback( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + /* enable digital loopback */ + i2c->MDR |= ( ( uint32 ) 1U << 6U ); + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_018 */ +/* DesignId : I2C_DesignId_019 */ +/* Requirements : CONQ_I2C_SR25 */ +/** @fn void i2cDisableLoopback(i2cBASE_t *i2c) + * @brief Enable Loopback mode for self test + * @param[in] i2c - i2c module base address + * + * This function disable the Loopback mode. + */ +void i2cDisableLoopback( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + i2c->MDR &= 0xFFFFFFBFU; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_019 */ +/* DesignId : I2C_DesignId_013 */ +/* Requirements : CONQ_I2C_SR18 */ +/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Enable interrupts + * @param[in] i2c - i2c module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * i2c_FE_INT - framing error, + * i2c_OE_INT - overrun error, + * i2c_PE_INT - parity error, + * i2c_RX_INT - receive buffer ready, + * i2c_TX_INT - transmit buffer ready, + * i2c_WAKE_INT - wakeup, + * i2c_BREAK_INT - break detect + */ +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + g_i2cTransfer_t[ index ].mode |= ( flags & ( uint32 ) I2C_TX_INT ); + i2c->IMR = ( flags & ( uint32 ) ( ~( uint32 ) I2C_TX_INT ) ); +} + +/* SourceId : I2C_SourceId_020 */ +/* DesignId : I2C_DesignId_014 */ +/* Requirements : CONQ_I2C_SR19 */ +/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Disable interrupts + * @param[in] i2c - i2c module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * i2c_FE_INT - framing error, + * i2c_OE_INT - overrun error, + * i2c_PE_INT - parity error, + * i2c_RX_INT - receive buffer ready, + * i2c_TX_INT - transmit buffer ready, + * i2c_WAKE_INT - wakeup, + * i2c_BREAK_INT - break detect + */ +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + uint32 int_mask; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + g_i2cTransfer_t[ index ].mode &= ( uint32 ) ~( flags & ( uint32 ) I2C_TX_INT ); + int_mask = i2c->IMR & ( uint32 ) ( ~( uint32 ) ( flags | ( uint32 ) I2C_TX_INT ) ); + i2c->IMR = int_mask; +} + +/* SourceId : I2C_SourceId_021 */ +/* DesignId : I2C_DesignId_020 */ +/* Requirements : CONQ_I2C_SR23 */ +/** @fn i2cSetMode(i2cBASE_t *i2c, uint32 mode) + * @brief Sets Master or Slave mode. + * @param[in] i2c - i2c module base address + * @param[in] mode - Mode can be either: + * I2C_MASTER - Master Mode, + * I2C_SLAVE - Slave Mode + */ +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ) +{ + uint32 temp_mdr; + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* set Master or Slave Mode */ + temp_mdr = ( i2c->MDR & ( ~I2C_MASTER ) ); + i2c->MDR = ( temp_mdr | mode ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_022 */ +/* DesignId : I2C_DesignId_021 */ +/* Requirements : CONQ_I2C_SR28 */ +/** @fn void i2c1GetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the I2C1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OAR = I2C1_OAR_CONFIGVALUE; + config_reg->CONFIG_IMR = I2C1_IMR_CONFIGVALUE; + config_reg->CONFIG_CLKL = I2C1_CLKL_CONFIGVALUE; + config_reg->CONFIG_CLKH = I2C1_CLKH_CONFIGVALUE; + config_reg->CONFIG_CNT = I2C1_CNT_CONFIGVALUE; + config_reg->CONFIG_SAR = I2C1_SAR_CONFIGVALUE; + config_reg->CONFIG_MDR = I2C1_MDR_CONFIGVALUE; + config_reg->CONFIG_EMDR = I2C1_EMDR_CONFIGVALUE; + config_reg->CONFIG_PSC = I2C1_PSC_CONFIGVALUE; + config_reg->CONFIG_DMAC = I2C1_DMAC_CONFIGVALUE; + config_reg->CONFIG_FUN = I2C1_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = I2C1_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = I2C1_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = I2C1_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = I2C1_PSL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_OAR = i2cREG1->OAR; + config_reg->CONFIG_IMR = i2cREG1->IMR; + config_reg->CONFIG_CLKL = i2cREG1->CKL; + config_reg->CONFIG_CLKH = i2cREG1->CKH; + config_reg->CONFIG_CNT = i2cREG1->CNT; + config_reg->CONFIG_SAR = i2cREG1->SAR; + config_reg->CONFIG_MDR = i2cREG1->MDR; + config_reg->CONFIG_EMDR = i2cREG1->EMDR; + config_reg->CONFIG_PSC = i2cREG1->PSC; + config_reg->CONFIG_DMAC = i2cREG1->DMACR; + config_reg->CONFIG_FUN = i2cREG1->PFNC; + config_reg->CONFIG_DIR = i2cREG1->DIR; + config_reg->CONFIG_ODR = i2cREG1->PDR; + config_reg->CONFIG_PD = i2cREG1->PDIS; + config_reg->CONFIG_PSL = i2cREG1->PSEL; + } +} + +/* SourceId : I2C_SourceId_023 */ +/* DesignId : I2C_DesignId_021 */ +/* Requirements : CONQ_I2C_SR29 */ +/** @fn void i2c2GetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the I2C1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OAR = I2C2_OAR_CONFIGVALUE; + config_reg->CONFIG_IMR = I2C2_IMR_CONFIGVALUE; + config_reg->CONFIG_CLKL = I2C2_CLKL_CONFIGVALUE; + config_reg->CONFIG_CLKH = I2C2_CLKH_CONFIGVALUE; + config_reg->CONFIG_CNT = I2C2_CNT_CONFIGVALUE; + config_reg->CONFIG_SAR = I2C2_SAR_CONFIGVALUE; + config_reg->CONFIG_MDR = I2C2_MDR_CONFIGVALUE; + config_reg->CONFIG_EMDR = I2C2_EMDR_CONFIGVALUE; + config_reg->CONFIG_PSC = I2C2_PSC_CONFIGVALUE; + config_reg->CONFIG_DMAC = I2C2_DMAC_CONFIGVALUE; + config_reg->CONFIG_FUN = I2C2_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = I2C2_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = I2C2_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = I2C2_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = I2C2_PSL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_OAR = i2cREG2->OAR; + config_reg->CONFIG_IMR = i2cREG2->IMR; + config_reg->CONFIG_CLKL = i2cREG2->CKL; + config_reg->CONFIG_CLKH = i2cREG2->CKH; + config_reg->CONFIG_CNT = i2cREG2->CNT; + config_reg->CONFIG_SAR = i2cREG2->SAR; + config_reg->CONFIG_MDR = i2cREG2->MDR; + config_reg->CONFIG_EMDR = i2cREG2->EMDR; + config_reg->CONFIG_PSC = i2cREG2->PSC; + config_reg->CONFIG_DMAC = i2cREG2->DMACR; + config_reg->CONFIG_FUN = i2cREG2->PFNC; + config_reg->CONFIG_DIR = i2cREG2->DIR; + config_reg->CONFIG_ODR = i2cREG2->PDR; + config_reg->CONFIG_PD = i2cREG2->PDIS; + config_reg->CONFIG_PSL = i2cREG2->PSEL; + } +} + +/** @fn i2cSetDirection(i2cBASE_t *i2c, uint32 dir) + * @brief Sets I2C as transmitter or receiver. + * @param[in] i2c - i2c module base address + * @param[in] dir - This can be one of the following: + * I2C_TRANSMITTER - Transmit Mode, + * I2C_RECEIVER - Receive Mode + */ +/* SourceId : I2C_SourceId_026 */ +/* DesignId : */ +/* Requirements : */ +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ) +{ + /* USER CODE BEGIN (58) */ + /* USER CODE END */ + + /* set Transmit/Receive mode */ + i2c->MDR &= ~I2C_TRANSMITTER; + i2c->MDR |= dir; + + /* USER CODE BEGIN (59) */ + /* USER CODE END */ +} + +/** @fn i2cIsMasterReady(i2cBASE_t *i2c) + * @brief Indicates whether MST bit is set or cleared to indicate that stop + * condition was generated. This API should be called after Master Tx or Rx + * to check if the transaction is complete. + * @param[in] i2c - i2c module base address + * @return boolean value to indicate whether MST bit is cleared after STOP bit is + * generated. + * - TRUE, if MST bit is cleared. + * - FALSE, if MST bit is set. + */ +/* SourceId : I2C_SourceId_027 */ +/* DesignId : */ +/* Requirements : */ +bool i2cIsMasterReady( i2cBASE_t * i2c ) +{ + bool retVal = 0U; + /* USER CODE BEGIN (60) */ + /* USER CODE END */ + + /* check if MST bit is cleared. */ + if( ( i2c->MDR & I2C_MASTER ) == 0 ) + { + retVal = true; + } + else + { + retVal = false; + } + return retVal; + + /* USER CODE BEGIN (61) */ + /* USER CODE END */ +} + +/** @fn i2cIsBusBusy(i2cBASE_t *i2c) + * @brief Returns the state of the bus busy flag. True if it is set and false otherwise. + * @param[in] i2c - i2c module base address + * @return boolean value to indicate whether BB bit is set in the status register. + * - TRUE, if BB bit is set. + * - FALSE, if BB bit is cleared. + */ +/* SourceId : I2C_SourceId_028 */ +/* DesignId : */ +/* Requirements : */ +bool i2cIsBusBusy( i2cBASE_t * i2c ) +{ + bool retVal = 0U; + /* USER CODE BEGIN (62) */ + /* USER CODE END */ + + /* check if BB bit is set. */ + if( ( i2c->STR & I2C_BUSBUSY ) == I2C_BUSBUSY ) + { + retVal = true; + } + else + { + retVal = false; + } + return retVal; + + /* USER CODE BEGIN (63) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c new file mode 100644 index 00000000000..265d2415ba0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c @@ -0,0 +1,943 @@ +/** @file lin.c + * @brief LIN Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "lin.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : LIN_SourceId_001 */ +/* DesignId : LIN_DesignId_001 */ +/* Requirements : CONQ_LIN_SR5 */ +/** @fn void linInit(void) + * @brief Initializes the lin Driver + * + * This function initializes the lin module. + */ +void linInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG1->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG1->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG1->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module either as master/salve + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG1->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG1->MBRSR = ( uint32 ) 3370U; + + /** - Setup baud rate prescaler */ + linREG1->BRS = ( uint32 ) 233U; + + /** - Setup RX and TX reception masks */ + linREG1->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG1->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG1->FORMAT = ( ( linREG1->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG1->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG1->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG1->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG1->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG1->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG1->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG1->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG1->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG1->GCR1 |= 0x00000080U; + + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG2->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG2->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG2->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module either as master/salve + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG2->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG2->MBRSR = ( uint32 ) 3370U; + + /** - Setup baud rate prescaler */ + linREG2->BRS = ( uint32 ) 233U; + + /** - Setup RX and TX reception masks */ + linREG2->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG2->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG2->FORMAT = ( ( linREG2->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG2->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG2->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG2->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG2->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG2->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG2->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG2->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG2->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG2->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_002 */ +/* DesignId : LIN_DesignId_002 */ +/* Requirements : CONQ_LIN_SR6 */ +/** @fn void linSetFunctional(linBASE_t *lin, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] lin - lin module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCFUN register at runtime, this allows to + * dynamically change the functionality of the LIN pins between functional + * and GIO mode. + */ +void linSetFunctional( linBASE_t * lin, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + lin->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_003 */ +/* DesignId : LIN_DesignId_003 */ +/* Requirements : CONQ_LIN_SR7 */ +/** @fn void linSendHeader(linBASE_t *lin, uint8 identifier) + * @brief Send lin header. + * @param[in] lin - lin module base address + * @param[in] identifier - lin header id + * + * Send lin header including sync break field, sync field and identifier. + */ +void linSendHeader( linBASE_t * lin, uint8 identifier ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + lin->ID = ( ( lin->ID & 0xFFFFFF00U ) | ( uint32 ) identifier ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_004 */ +/* DesignId : LIN_DesignId_004 */ +/* Requirements : CONQ_LIN_SR8 */ +/** @fn void linSendWakupSignal(linBASE_t *lin) + * @brief Send lin wakeup signal. + * @param[in] lin - lin module base address + * + * Send lin wakeup signal to terminate the sleep mode of any lin node connected to the + * BUS. + */ +void linSendWakupSignal( linBASE_t * lin ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + lin->TDx[ 0U ] = 0xF0U; + lin->GCR2 |= 0x00000100U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_005 */ +/* DesignId : LIN_DesignId_005 */ +/* Requirements : CONQ_LIN_SR9 */ +/** @fn void linEnterSleep(linBASE_t *lin) + * @brief Take Module to Sleep. + * @param[in] lin - lin module base address + * + * Application must call this function to take Module to Sleep when Sleep command is + * received. This function can also be called to forcefully enter Sleep when no activity + * on BUS. + */ +void linEnterSleep( linBASE_t * lin ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + lin->GCR2 |= 0x00000001U; + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_006 */ +/* DesignId : LIN_DesignId_006 */ +/* Requirements : CONQ_LIN_SR10 */ +/** @fn void linSoftwareReset(linBASE_t *lin) + * @brief Perform software reset. + * @param[in] lin - lin module base address + * + * Perform software reset of lin module. + * This function will reset the lin state machine and clear all pending flags. + * It is required to call this function after a wakeup signal has been sent. + */ +void linSoftwareReset( linBASE_t * lin ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + lin->GCR1 &= ~( uint32 ) ( 0x00000080U ); + lin->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_007 */ +/* DesignId : LIN_DesignId_007 */ +/* Requirements : CONQ_LIN_SR11 */ +/** @fn uint32 linIsTxReady(linBASE_t *lin) + * @brief Check if Tx buffer empty + * @param[in] lin - lin module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 linIsTxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return lin->FLR & LIN_TX_READY; +} + +/* SourceId : LIN_SourceId_008 */ +/* DesignId : LIN_DesignId_008 */ +/* Requirements : CONQ_LIN_SR12 */ +/** @fn void linSetLength(linBASE_t *lin, uint32 length) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] length - number of data words in bytes. Range: 1-8. + * + * Send data response length in bytes. + */ +void linSetLength( linBASE_t * lin, uint32 length ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + lin->FORMAT = ( ( lin->FORMAT & 0xFFF8FFFFU ) | ( ( length - 1U ) << 16U ) ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_009 */ +/* DesignId : LIN_DesignId_009 */ +/* Requirements : CONQ_LIN_SR13 */ +/** @fn void linSend(linBASE_t *lin, uint8 * data) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data'. + * The number of data to transmit must be set with 'linSetLength' before. + */ +void linSend( linBASE_t * lin, uint8 * data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + uint8 * pData = data + length; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + lin->TDx[ length - i ] = *pData; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData--; + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_010 */ +/* DesignId : LIN_DesignId_010 */ +/* Requirements : CONQ_LIN_SR14 */ +/** @fn uint32 linIsRxReady(linBASE_t *lin) + * @brief Check if Rx buffer full + * @param[in] lin - lin module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 linIsRxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return lin->FLR & LIN_RX_INT; +} + +/* SourceId : LIN_SourceId_011 */ +/* DesignId : LIN_DesignId_011 */ +/* Requirements : CONQ_LIN_SR15 */ +/** @fn uint32 linTxRxError(linBASE_t *lin) + * @brief Return Tx and Rx Error flags + * @param[in] lin - lin module base address + * + * @return The Tx and Rx error flags + * + * Returns the bit, physical bus, checksum, inconsistent sync field, + * no response, framing, overrun, parity and timeout error flags. + * It also clears the error flags before returning. + */ +uint32 linTxRxError( linBASE_t * lin ) +{ + uint32 status = lin->FLR + & ( LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT + | LIN_TOAWUS_INT | LIN_TO_INT ); + + lin->FLR = LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT | LIN_TOAWUS_INT + | LIN_TO_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : LIN_SourceId_012 */ +/* DesignId : LIN_DesignId_012 */ +/* Requirements : CONQ_LIN_SR16 */ +/** @fn uint32 linGetIdentifier(linBASE_t *lin) + * @brief Get last received identifier + * @param[in] lin - lin module base address + * + * @return Identifier + * + * Read last received identifier. + */ +uint32 linGetIdentifier( linBASE_t * lin ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + return ( uint32 ) ( ( uint32 ) ( lin->ID & 0x00FF0000U ) >> 16U ); +} + +/* SourceId : LIN_SourceId_013 */ +/* DesignId : LIN_DesignId_013 */ +/* Requirements : CONQ_LIN_SR17 */ +/** @fn void linGetData(linBASE_t *lin, uint8 * const data) + * @brief Read received data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data buffer + * + * Read a block of bytes and place it into the data buffer pointed to by 'data'. + */ +void linGetData( linBASE_t * lin, uint8 * const data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + uint8 * pData = data; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *pData = lin->RDx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + pData++; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_014 */ +/* DesignId : LIN_DesignId_016 */ +/* Requirements : CONQ_LIN_SR20 */ +/** @fn void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + lin->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + lin->IODFTCTRL = ( ( uint32 ) ( 0x00000A00U ) + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_015 */ +/* DesignId : LIN_DesignId_017 */ +/* Requirements : CONQ_LIN_SR21 */ +/** @fn void linDisableLoopback(linBASE_t *lin) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * + * This function disable the Loopback mode. + */ +void linDisableLoopback( linBASE_t * lin ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + lin->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_016 */ +/* DesignId : LIN_DesignId_014 */ +/* Requirements : CONQ_LIN_SR18 */ +/** @fn linEnableNotification(linBASE_t *lin, uint32 flags) + * @brief Enable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +void linEnableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + lin->SETINT = flags; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_017 */ +/* DesignId : LIN_DesignId_015 */ +/* Requirements : CONQ_LIN_SR19 */ +/** @fn linDisableNotification(linBASE_t *lin, uint32 flags) + * @brief Disable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +void linDisableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + lin->CLEARINT = flags; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_018 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : CONQ_LIN_SR25 */ +/** @fn void lin1GetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN1_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN1_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN1_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN1_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN1_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN1_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN1_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN1_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN1_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN1_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN1_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN1_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN1_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN1_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN1_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = linREG1->GCR0; + config_reg->CONFIG_GCR1 = linREG1->GCR1; + config_reg->CONFIG_GCR2 = linREG1->GCR2; + config_reg->CONFIG_SETINT = linREG1->SETINT; + config_reg->CONFIG_SETINTLVL = linREG1->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG1->FORMAT; + config_reg->CONFIG_BRSR = linREG1->BRS; + config_reg->CONFIG_FUN = linREG1->PIO0; + config_reg->CONFIG_DIR = linREG1->PIO1; + config_reg->CONFIG_ODR = linREG1->PIO6; + config_reg->CONFIG_PD = linREG1->PIO7; + config_reg->CONFIG_PSL = linREG1->PIO8; + config_reg->CONFIG_COMP = linREG1->COMP; + config_reg->CONFIG_MASK = linREG1->MASK; + config_reg->CONFIG_MBRSR = linREG1->MBRSR; + } +} + +/* SourceId : LIN_SourceId_019 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : CONQ_LIN_SR26 */ +/** @fn void lin2GetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN2_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN2_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN2_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN2_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN2_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN2_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN2_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN2_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN2_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN2_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN2_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN2_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN2_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN2_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN2_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = linREG2->GCR0; + config_reg->CONFIG_GCR1 = linREG2->GCR1; + config_reg->CONFIG_GCR2 = linREG2->GCR2; + config_reg->CONFIG_SETINT = linREG2->SETINT; + config_reg->CONFIG_SETINTLVL = linREG2->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG2->FORMAT; + config_reg->CONFIG_BRSR = linREG2->BRS; + config_reg->CONFIG_FUN = linREG2->PIO0; + config_reg->CONFIG_DIR = linREG2->PIO1; + config_reg->CONFIG_ODR = linREG2->PIO6; + config_reg->CONFIG_PD = linREG2->PIO7; + config_reg->CONFIG_PSL = linREG2->PIO8; + config_reg->CONFIG_COMP = linREG2->COMP; + config_reg->CONFIG_MASK = linREG2->MASK; + config_reg->CONFIG_MBRSR = linREG2->MBRSR; + } +} + +/* SourceId : LIN_SourceId_024 */ +/* DesignId : */ +/* Requirements : */ +/** @fn uint32 linGetStatusFlag(linBASE_t *lin) + * @brief Get LIN status register value + * @param[in] lin - lin module base address + * + * @return Status Flag register content + * + * Read current Status Flag register. + */ +uint32 linGetStatusFlag( linBASE_t * lin ) +{ + return lin->FLR; +} + +/* SourceId : LIN_SourceId_025 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void linClearStatusFlag(linBASE_t *lin, uint32 flags) + * @brief Clear LIN status register + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be or'ed value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect, + * LIN_BUSY_FLAG - Bus Busy Flag, + * LIN_TXEMPTY_INT - Transmit Empty Flag + * + * Clear Status Flags passed as parameter. + */ +void linClearStatusFlag( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + lin->FLR = flags; + /* USER CODE BEGIN (45) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c new file mode 100644 index 00000000000..958a14a5cad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c @@ -0,0 +1,251 @@ +/** + * \file mdio.c + * + * \brief MDIO APIs. + * + * This file contains the device abstraction layer APIs for MDIO. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "hw_reg_access.h" +#include "mdio.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define PHY_REG_MASK ( 0x1FU ) +#define PHY_ADDR_MASK ( 0x1FU ) +#define PHY_DATA_MASK ( 0xFFFFU ) +#define PHY_REG_SHIFT ( 21U ) +#define PHY_ADDR_SHIFT ( 16U ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ + +/** + * \brief Reads a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param dataPtr Pointer where the read value shall be written. + * + * \return status of the read \n + * TRUE - read is successful.\n + * FALSE - read is not acknowledged properly. + * + **/ +/* SourceId : ETH_SourceId_059 */ +/* DesignId : ETH_DesignId_059*/ +/* Requirements : CONQ_EMAC_SR62 */ +boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ) +{ + boolean retVal = FALSE; + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( ( ( uint32 ) MDIO_USERACCESS0_READ ) + | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) ); + + /* wait for command completion */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + /* Store the data if the read is acknowledged */ + if( ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) & MDIO_USERACCESS0_ACK ) + == MDIO_USERACCESS0_ACK ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Output is a 16 bit Value to be stored - + * Advisory as per MISRA" */ + *dataPtr = ( uint16 ) ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) + & PHY_DATA_MASK ); + retVal = TRUE; + } + + return retVal; +} + +/** + * \brief Writes a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param RegVal Value to be written. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_058 */ +/* DesignId : ETH_DesignId_058*/ +/* Requirements : CONQ_EMAC_SR63 */ +void MDIOPhyRegWrite( uint32 baseAddr, uint32 phyAddr, uint32 regNum, uint16 RegVal ) +{ + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( MDIO_USERACCESS0_WRITE | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) + | RegVal ); + + /* wait for command completion*/ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ +} +/** + * \brief Reads the alive status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * is alive. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO alive register state + * + **/ +/* SourceId : ETH_SourceId_062 */ +/* DesignId : ETH_DesignId_062*/ +/* Requirements : CONQ_EMAC_SR64 */ +uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_ALIVE ) ); +} + +/** + * \brief Reads the link status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * link is active. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO link register state + * + **/ +/* SourceId : ETH_SourceId_061 */ +/* DesignId : ETH_DesignId_061*/ +/* Requirements : CONQ_EMAC_SR67 */ +uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_LINK ) ); +} + +/** + * \brief Initializes the MDIO peripheral. This enables the MDIO state + * machine, uses standard pre-amble and set the clock divider value. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param mdioInputFreq The clock input to the MDIO module + * \param mdioOutputFreq The clock output required on the MDIO bus + * \return None + * + **/ +/* SourceId : ETH_SourceId_060 */ +/* DesignId : ETH_DesignId_060*/ +/* Requirements : CONQ_EMAC_SR59 */ +void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ) +{ + uint32 clkDiv = ( mdioInputFreq / mdioOutputFreq ) - 1U; + HWREG( baseAddr + MDIO_CONTROL ) = ( ( clkDiv & MDIO_CONTROL_CLKDIV ) + | MDIO_CONTROL_ENABLE | MDIO_CONTROL_PREAMBLE + | MDIO_CONTROL_FAULTENB ); +} + +/** + * \brief Function to enable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : CONQ_EMAC_SR60 */ +void MDIOEnable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + | MDIO_CONTROL_ENABLE; +} + +/** + * \brief Function to disable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_057 */ +/* DesignId : ETH_DesignId_057*/ +/* Requirements : CONQ_EMAC_SR61 */ +void MDIODisable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + & ( ~MDIO_CONTROL_ENABLE ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c new file mode 100644 index 00000000000..cca2730f813 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c @@ -0,0 +1,3408 @@ +/** @file mibspi.c + * @brief MIBSPI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "mibspi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : MIBSPI_SourceId_001 */ +/* DesignId : MIBSPI_DesignId_001 */ +/* Requirements : CONQ_MIBSPI_SR9 */ +/** @fn void mibspiInit(void) + * @brief Initializes the MIBSPI Driver + * + * This function initializes the MIBSPI module. + */ +void mibspiInit( void ) +{ + uint32 i; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b MIBSPI1 */ + + /** bring MIBSPI out of reset */ + mibspiREG1->GCR0 = 0U; + mibspiREG1->GCR0 = 1U; + + /** enable MIBSPI1 multibuffered mode and enable buffer RAM */ + mibspiREG1->MIBSPIE = ( mibspiREG1->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI1 master mode and clock configuration */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI1 enable pin configuration */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG1->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG1->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG1->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG1->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG1->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG1->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG1->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG1->PAR_ECC_CTRL = ( mibspiREG1->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG1->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG1->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG1->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG1->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG1->LTGPEND = ( mibspiREG1->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG1->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG1->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI1 @b Port */ + + /** - MIBSPI1 Port output values */ + mibspiREG1->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port direction */ + mibspiREG1->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port open drain enable */ + mibspiREG1->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown selection */ + mibspiREG1->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown enable*/ + mibspiREG1->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /* MIBSPI1 set all pins to functional */ + mibspiREG1->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - Finally start MIBSPI1 */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI2 */ + + /** bring MIBSPI out of reset */ + mibspiREG2->GCR0 = 0U; + mibspiREG2->GCR0 = 1U; + + /** enable MIBSPI2 multibuffered mode and enable buffer RAM */ + mibspiREG2->MIBSPIE = ( mibspiREG2->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI2 master mode and clock configuration */ + mibspiREG2->GCR1 = ( mibspiREG2->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI2 enable pin configuration */ + mibspiREG2->INT0 = ( mibspiREG2->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG2->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG2->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG2->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG2->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG2->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG2->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG2->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG2->PAR_ECC_CTRL = ( mibspiREG2->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG2->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG2->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG2->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG2->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG2->LTGPEND = ( mibspiREG2->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG2->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG2->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG2->INT0 = ( mibspiREG2->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI2 @b Port */ + + /** - MIBSPI2 Port output values */ + mibspiREG2->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port direction */ + mibspiREG2->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port open drain enable */ + mibspiREG2->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port pullup / pulldown selection */ + mibspiREG2->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port pullup / pulldown enable*/ + mibspiREG2->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI2 set all pins to functional */ + mibspiREG2->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI2 */ + mibspiREG2->GCR1 = ( mibspiREG2->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI3 */ + + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = ( mibspiREG3->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG3->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG3->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->PAR_ECC_CTRL = ( mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG3->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG3->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG3->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG3->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI4 */ + + /** bring MIBSPI out of reset */ + mibspiREG4->GCR0 = 0U; + mibspiREG4->GCR0 = 1U; + + /** enable MIBSPI4 multibuffered mode and enable buffer RAM */ + mibspiREG4->MIBSPIE = ( mibspiREG4->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI4 master mode and clock configuration */ + mibspiREG4->GCR1 = ( mibspiREG4->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI4 enable pin configuration */ + mibspiREG4->INT0 = ( mibspiREG4->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG4->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG4->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG4->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG4->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG4->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG4->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG4->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG4->PAR_ECC_CTRL = ( mibspiREG4->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG4->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG4->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG4->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG4->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG4->LTGPEND = ( mibspiREG4->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG4->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG4->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG4->INT0 = ( mibspiREG4->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI4 @b Port */ + + /** - MIBSPI4 Port output values */ + mibspiREG4->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port direction */ + mibspiREG4->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port open drain enable */ + mibspiREG4->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port pullup / pulldown selection */ + mibspiREG4->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port pullup / pulldown enable*/ + mibspiREG4->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI4 set all pins to functional */ + mibspiREG4->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI4 */ + mibspiREG4->GCR1 = ( mibspiREG4->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI5 */ + + /** bring MIBSPI out of reset */ + mibspiREG5->GCR0 = 0U; + mibspiREG5->GCR0 = 1U; + + /** enable MIBSPI5 multibuffered mode and enable buffer RAM */ + mibspiREG5->MIBSPIE = ( mibspiREG5->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI5 master mode and clock configuration */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI5 enable pin configuration */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG5->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG5->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG5->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG5->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG5->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG5->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG5->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG5->PAR_ECC_CTRL = ( mibspiREG5->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG5->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG5->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG5->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG5->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG5->LTGPEND = ( mibspiREG5->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG5->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG5->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI5 @b Port */ + + /** - MIBSPI5 Port output values */ + mibspiREG5->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port direction */ + mibspiREG5->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port open drain enable */ + mibspiREG5->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown selection */ + mibspiREG5->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown enable*/ + mibspiREG5->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /* MIBSPI5 set all pins to functional */ + mibspiREG5->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - Finally start MIBSPI5 */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_002 */ +/* DesignId : */ +/* Requirements : */ +/** @fn boolean mibspiIsBuffInitialized(mibspiBASE_t *mibspi) + * @brief Checks if Mibspi buffer is initialized. + * @param[in] mibspi - Mibspi module base address + * + * This function brings Mibspi module out of reset. + */ +boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi ) +{ + volatile boolean status; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + if( ( mibspi->FLG & 0x01000000U ) != 0x01000000U ) + { + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + return ( status ); +} + +/* SourceId : MIBSPI_SourceId_003 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void mibspiOutofReset(mibspiBASE_t *mibspi) + * @brief Bring Mibspi Module Out of Reset + * @param[in] mibspi - Mibspi module base address + * + * This function brings Mibspi module out of reset. + */ +void mibspiOutofReset( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + mibspi->GCR0 |= 0x1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_004 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void mibspiReset(mibspiBASE_t *mibspi) + * @brief Take Mibspi Module to Reset + * @param[in] mibspi - Mibspi module base address + * + * This function takes Mibspi module to reset. + */ +void mibspiReset( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + mibspi->GCR0 = 0x0U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_005 */ +/* DesignId : MIBSPI_DesignId_002 */ +/* Requirements : CONQ_MIBSPI_SR10 */ +/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] mibspi - mibspi module base address + * @param[in] port - Value to write to PC0 register + * + * Change the value of the PC0 register at runtime, this allows to + * dynamically change the functionality of the MIBSPI pins between functional + * and GIO mode. + */ +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + mibspi->PC0 = port; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_006 */ +/* DesignId : MIBSPI_DesignId_003 */ +/* Requirements : CONQ_MIBSPI_SR11 */ +/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Set Buffer Data + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] data - new data for transfer group + * + * This function updates the data for the specified transfer group, + * the length of the data must match the length of the transfer group. + */ +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + mibspiRAM_t * ram = mibspi == mibspiREG1 + ? mibspiRAM1 + : ( mibspi == mibspiREG2 + ? mibspiRAM2 + : ( mibspi == mibspiREG3 + ? mibspiRAM3 + : ( mibspi == mibspiREG4 ? mibspiRAM4 + : mibspiRAM5 ) ) ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + ram->tx[ start ].data = *data; + data++; + start++; + } + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_007 */ +/* DesignId : MIBSPI_DesignId_004 */ +/* Requirements : CONQ_MIBSPI_SR12 */ +/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Retrieves Buffer Data from receive buffer + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[out] data - pointer to data array + * + * @return error flags from data buffer, if there was a receive error on + * one of the buffers this will be reflected in the return value. + * + * This function transfers the data from the specified transfer group receive + * buffers to the data array, the length of the data must match the length + * of the transfer group. + */ +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + mibspiRAM_t * ram = mibspi == mibspiREG1 + ? mibspiRAM1 + : ( mibspi == mibspiREG2 + ? mibspiRAM2 + : ( mibspi == mibspiREG3 + ? mibspiRAM3 + : ( mibspi == mibspiREG4 ? mibspiRAM4 + : mibspiRAM5 ) ) ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + uint16 mibspiFlags = 0U; + uint32 ret; + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + mibspiFlags |= ram->rx[ start ].flags; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *data = ram->rx[ start ].data; + data++; + start++; + } + + ret = ( ( uint32 ) mibspiFlags >> 8U ) & 0x5FU; + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + return ret; +} + +/* SourceId : MIBSPI_SourceId_008 */ +/* DesignId : MIBSPI_DesignId_005 */ +/* Requirements : CONQ_MIBSPI_SR13 */ +/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) + * @brief Transmit Transfer Group + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * Initiates a transfer for the specified transfer group. + */ +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mibspi->TGCTRL[ group ] |= 0x80000000U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_009 */ +/* DesignId : MIBSPI_DesignId_006 */ +/* Requirements : CONQ_MIBSPI_SR14 */ +/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) + * @brief Check for Transfer Group Ready + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * @return TRUE is transfer complete, otherwise FALSE. + * + * Checks to see if the transfer for the specified transfer group + * has finished. + */ +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ) +{ + boolean status; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( ( ( ( ( mibspi->TGINTFLG & 0xFFFF0000U ) >> 16U ) >> group ) & 1U ) == 1U ) + { + mibspi->TGINTFLG = ( mibspi->TGINTFLG & 0x0000FFFFU ) + | ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return ( status ); +} + +/* SourceId : MIBSPI_SourceId_010 */ +/* DesignId : MIBSPI_DesignId_009 */ +/* Requirements : CONQ_MIBSPI_SR17 */ +/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + mibspi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + mibspi->IOLPKTSTCR = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_011 */ +/* DesignId : MIBSPI_DesignId_010 */ +/* Requirements : CONQ_MIBSPI_SR18 */ +/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * + * This function disable the Loopback mode. + */ +void mibspiDisableLoopback( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + mibspi->IOLPKTSTCR = 0x00000500U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_012 */ +/* DesignId : MIBSPI_DesignId_011 */ +/* Requirements : CONQ_MIBSPI_SR21 */ +/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) + * @brief Set the Pmode for the selected Data Format register + * @param[in] mibspi - Mibspi module base address + * @param[in] Pmode - Mibspi Parellel mode + * PMODE_NORMAL + * PMODE_2_DATALINE + * PMODE_4_DATALINE + * PMODE_8_DATALINE + * @param[in] DFMT - Mibspi Data Format register + * DATA_FORMAT0 + * DATA_FORMAT1 + * DATA_FORMAT2 + * DATA_FORMAT3 + * + * This function sets the Pmode for the selected Data Format register. + */ +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ) +{ + uint32 pmctrl_reg; + /* Set the Pmode for the selected Data Format register */ + pmctrl_reg = ( mibspi->PMCTRL + & ( ~( uint32 ) ( ( uint32 ) 0xFFU << ( 8U * DFMT ) ) ) ); + mibspi->PMCTRL = ( pmctrl_reg + | ( uint32 ) ( ( uint32 ) Pmode << ( ( 8U * DFMT ) ) ) ); +} + +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_007 */ +/* Requirements : CONQ_MIBSPI_SR15 */ +/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 + * level) + * @brief Enable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] level - Interrupt level + * + * This function enables the transfer group finished interrupt. + */ +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + if( level != 0U ) + { + mibspi->TGITLVST = ( mibspi->TGITLVST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + else + { + mibspi->TGITLVCR = ( mibspi->TGITLVCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + mibspi->TGITENST = ( mibspi->TGITENST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_014 */ +/* DesignId : MIBSPI_DesignId_008 */ +/* Requirements : CONQ_MIBSPI_SR16 */ +/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Disable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * This function disables the transfer group finished interrupt. + */ +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + mibspi->TGITENCR = ( mibspi->TGITENCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_015 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR22 */ +/** @fn void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI1_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI1_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI1_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI1_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI1_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI1_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI1_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI1_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI1_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI1_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI1_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI1_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI1_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI1_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI1_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI1_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI1_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI1_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI1_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI1_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI1_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI1_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI1_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG1->GCR1; + config_reg->CONFIG_INT0 = mibspiREG1->INT0; + config_reg->CONFIG_LVL = mibspiREG1->LVL; + config_reg->CONFIG_PCFUN = mibspiREG1->PC0; + config_reg->CONFIG_PCDIR = mibspiREG1->PC1; + config_reg->CONFIG_PCPDR = mibspiREG1->PC6; + config_reg->CONFIG_PCDIS = mibspiREG1->PC7; + config_reg->CONFIG_PCPSL = mibspiREG1->PC8; + config_reg->CONFIG_DELAY = mibspiREG1->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG1->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG1->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG1->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG1->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG1->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG1->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG1->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG1->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG1->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG1->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG1->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG1->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG1->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG1->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG1->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_016 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR23 */ +/** @fn void mibspi2GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI2_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI2_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI2_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI2_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI2_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI2_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI2_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI2_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI2_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI2_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI2_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI2_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI2_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI2_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI2_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI2_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI2_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI2_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI2_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI2_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI2_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI2_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI2_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG2->GCR1; + config_reg->CONFIG_INT0 = mibspiREG2->INT0; + config_reg->CONFIG_LVL = mibspiREG2->LVL; + config_reg->CONFIG_PCFUN = mibspiREG2->PC0; + config_reg->CONFIG_PCDIR = mibspiREG2->PC1; + config_reg->CONFIG_PCPDR = mibspiREG2->PC6; + config_reg->CONFIG_PCDIS = mibspiREG2->PC7; + config_reg->CONFIG_PCPSL = mibspiREG2->PC8; + config_reg->CONFIG_DELAY = mibspiREG2->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG2->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG2->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG2->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG2->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG2->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG2->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG2->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG2->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG2->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG2->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG2->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG2->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG2->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG2->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG2->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_017 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR24 */ +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG3->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG3->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG3->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG3->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG3->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG3->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG3->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG3->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG3->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_018 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR25 */ +/** @fn void mibspi4GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI4_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI4_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI4_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI4_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI4_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI4_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI4_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI4_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI4_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI4_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI4_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI4_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI4_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI4_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI4_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI4_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI4_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI4_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI4_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI4_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI4_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI4_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG4->GCR1; + config_reg->CONFIG_INT0 = mibspiREG4->INT0; + config_reg->CONFIG_LVL = mibspiREG4->LVL; + config_reg->CONFIG_PCFUN = mibspiREG4->PC0; + config_reg->CONFIG_PCDIR = mibspiREG4->PC1; + config_reg->CONFIG_PCPDR = mibspiREG4->PC6; + config_reg->CONFIG_PCDIS = mibspiREG4->PC7; + config_reg->CONFIG_PCPSL = mibspiREG4->PC8; + config_reg->CONFIG_DELAY = mibspiREG4->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG4->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG4->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG4->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG4->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG4->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG4->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG4->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG4->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG4->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG4->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG4->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG4->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG4->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG4->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG4->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_019 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR26 */ +/** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI5_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI5_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI5_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI5_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI5_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI5_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI5_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI5_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI5_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI5_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI5_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI5_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI5_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI5_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI5_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI5_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI5_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI5_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI5_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI5_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI5_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI5_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI5_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG5->GCR1; + config_reg->CONFIG_INT0 = mibspiREG5->INT0; + config_reg->CONFIG_LVL = mibspiREG5->LVL; + config_reg->CONFIG_PCFUN = mibspiREG5->PC0; + config_reg->CONFIG_PCDIR = mibspiREG5->PC1; + config_reg->CONFIG_PCPDR = mibspiREG5->PC6; + config_reg->CONFIG_PCDIS = mibspiREG5->PC7; + config_reg->CONFIG_PCPSL = mibspiREG5->PC8; + config_reg->CONFIG_DELAY = mibspiREG5->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG5->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG5->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG5->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG5->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG5->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG5->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG5->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG5->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG5->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG5->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG5->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG5->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG5->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG5->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG5->PAR_ECC_CTRL; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c new file mode 100644 index 00000000000..786f8d6871a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c @@ -0,0 +1,403 @@ +/** @file nmpu.c + * @brief NMPU Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "nmpu.h" + +/** @fn void nmpuEnable(nmpuBASE_t * nmpu) + * @brief Enable memory protection + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function enables memory protection + */ +/* SourceId : NMPU_SourceId_001 */ +/* DesignId : NMPU_DesignId_001 */ +/* Requirements : CONQ_NMPU_SR1 */ +void nmpuEnable( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL1 = 0xAU; /* Enable Memory Protection */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void nmpuDisable(nmpuBASE_t * nmpu) + * @brief Disable memory protection + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function disables memory protection + */ +/* SourceId : NMPU_SourceId_002 */ +/* DesignId : NMPU_DesignId_002 */ +/* Requirements : CONQ_NMPU_SR2 */ +void nmpuDisable( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL1 = 0x5U; /* Disable Memory Protection */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void nmpuEnableErrorGen(nmpuBASE_t * nmpu) + * @brief Enable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function enables error pulse output to ESM + */ +/* SourceId : NMPU_SourceId_003 */ +/* DesignId : NMPU_DesignId_003 */ +/* Requirements : CONQ_NMPU_SR3 */ +void nmpuEnableErrorGen( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL2 = 0xAU; /* Enable Error pulse output to ESM */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void nmpuDisableErrorGen(nmpuBASE_t * nmpu) + * @brief Disable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function disables error pulse output to ESM + */ +/* SourceId : NMPU_SourceId_004 */ +/* DesignId : NMPU_DesignId_004 */ +/* Requirements : CONQ_NMPU_SR4 */ +void nmpuDisableErrorGen( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL2 = 0x5U; /* Disable Error pulse output to ESM */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn boolean nmpuEnableRegion(nmpuBASE_t * nmpu, uint32 region, nmpuRegionAttributes_t +config) +* @brief Enable NMPU region +* +* @param[in] nmpu NMPU module instance +* - nmpu_emacREG : EMAC-NMPU (2 regions) +* - nmpu_dmaREG : DMA-NMPU (8 regions) +* - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 +regions) +* @param[in] region region number (NMPU_REGION0..NMPU_REGION7) +* @param[in] config struct containing the following elements: + - baseaddr : 32-bit vase address (must be multiple of +region size) + - regionsize : Region size (Refer enum nmpuRegionSize) + - accesspermission : Access Permission (Refer enum +nmpuAccessPermission) +* @return Returns TRUE if the input parameters are valid. +* +* This function enables an NMPU region. This function will not enable the NMPU module. +Application must call the routine nmpuEnable to so the same. +*/ +/* SourceId : NMPU_SourceId_005 */ +/* DesignId : NMPU_DesignId_005 */ +/* Requirements : CONQ_NMPU_SR5 */ +boolean nmpuEnableRegion( nmpuBASE_t * nmpu, + nmpuReg_t region, + nmpuRegionAttributes_t config ) +{ + boolean status = TRUE; + uint32 addrMask; + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + if( ( uint32 ) region >= ( nmpu->MPUTYPE >> 8U ) ) + { + /* Invalid region */ + status = FALSE; + } + + addrMask = ( uint32 ) 2U << ( config.regionsize ); + addrMask = addrMask - 1U; + if( ( config.baseaddr & addrMask ) != 0U ) + { + /* Invalid Baseaddress - Not a multiple of region size */ + status = FALSE; + } + + if( status == TRUE ) + { + /* Set the region attributes */ + nmpu->MPULOCK = 0xAU; + nmpu->MPUREGNUM = region; + nmpu->MPUREGBASE = ( ( uint32 ) ( config.baseaddr ) ); + nmpu->MPUREGSENA = ( ( uint32 ) ( config.regionsize ) << 1U ) | 1U; + nmpu->MPUREGACR = ( ( uint32 ) ( config.accesspermission ) << 8U ); + nmpu->MPULOCK = 0x5U; + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuDisableRegion(nmpuBASE_t * nmpu, uint32 region) + * @brief Disable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @param[in] region region number (NMPU_REGION0..NMPU_REGION7) + * @return Returns TRUE if the input parameters are valid. + * + * This function disables an NMPU region. + */ +/* SourceId : NMPU_SourceId_006 */ +/* DesignId : NMPU_DesignId_006 */ +/* Requirements : CONQ_NMPU_SR6 */ +boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region ) +{ + boolean status; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( uint32 ) region >= ( nmpu->MPUTYPE >> 8U ) ) + { + /* Invalid region */ + status = FALSE; + } + else + { + nmpu->MPULOCK = 0xAU; + nmpu->MPUREGNUM = region; + nmpu->MPUREGSENA = 0U; + nmpu->MPULOCK = 0x5U; + status = TRUE; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuErr_t nmpuGetErrorStatus(nmpuBASE_t * nmpu) + * @brief Get the error status + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Returns any of the following: + * - NMPU_ERROR_NONE : No error + * - NMPU_ERROR_AP_READ : Access permission Read Error + * - NMPU_ERROR_AP_WRITE : Access permission Write Error + * - NMPU_ERROR_BG_READ : Backgroung Read Error + * - NMPU_ERROR_BG_WRITE : Backgroung Write Error + * + * This function returns the status of NMPU error + */ +/* SourceId : NMPU_SourceId_007 */ +/* DesignId : NMPU_DesignId_007 */ +/* Requirements : CONQ_NMPU_SR7 */ +nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu ) +{ + nmpuErr_t status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( ( nmpu->MPUERRSTAT & 0x1U ) == 0x1U ) + { + if( ( nmpu->MPUERRSTAT & 0x02000000U ) == 0x02000000U ) + { + if( ( nmpu->MPUERRSTAT & 0x10000000U ) == 0x10000000U ) + { + status = NMPU_ERROR_AP_READ; + } + else + { + status = NMPU_ERROR_AP_WRITE; + } + } + else + { + if( ( nmpu->MPUERRSTAT & 0x10000000U ) == 0x10000000U ) + { + status = NMPU_ERROR_BG_READ; + } + else + { + status = NMPU_ERROR_BG_WRITE; + } + } + } + else + { + status = NMPU_ERROR_NONE; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuReg_t nmpuGetErrorRegion(nmpuBASE_t * nmpu) + * @brief Get the region for which an access permission error was detected + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Region where access permission error was detected + * + * This function returns the region for which an access permission error was detected + */ +/* SourceId : NMPU_SourceId_008 */ +/* DesignId : NMPU_DesignId_008 */ +/* Requirements : CONQ_NMPU_SR9 */ +nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return ( nmpuReg_t ) ( ( nmpu->MPUERRSTAT & 0x70000U ) >> 16U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn uint32 nmpuGetErrorAddress(nmpuBASE_t * nmpu) + * @brief Get the address for MPU compare fail + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Address for MPU compare fail + * + * This function returns the address for MPU compare fail + */ +/* SourceId : NMPU_SourceId_009 */ +/* DesignId : NMPU_DesignId_009 */ +/* Requirements : CONQ_NMPU_SR8 */ +uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + return ( nmpu->MPUERRADDR ); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void nmpuClearErrorStatus(nmpuBASE_t * nmpu) + * @brief Clear error status + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function clears the error status flags + */ +/* SourceId : NMPU_SourceId_010 */ +/* DesignId : NMPU_DesignId_010 */ +/* Requirements : CONQ_NMPU_SR10 */ +void nmpuClearErrorStatus( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + nmpu->MPUERRSTAT = 1U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c new file mode 100644 index 00000000000..ea9e93c4b16 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c @@ -0,0 +1,330 @@ +/** @file notification.c + * @brief User Notification Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file defines empty notification routines to avoid + * linker errors, Driver expects user to define the notification. + * The user needs to either remove this file and use their custom + * notification function or place their code sequence in this file + * between the provided USER CODE BEGIN and USER CODE END. + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include +#include "esm.h" +#include "can.h" +#include "gio.h" +#include "lin.h" +#include "mibspi.h" +#include "sci.h" +#include "het.h" +#include "dcc.h" +#include "i2c.h" +#include "crc.h" +#include "etpwm.h" +#include "eqep.h" +#include "ecap.h" +#include "epc.h" +#include "emac.h" +#include "sys_dma.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ +void esmGroup1Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +void esmGroup2Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +void esmGroup3Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + for( ;; ) + { + } /* Wait */ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +void adcNotification( adcBASE_t * adc, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +void canErrorNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +void canStatusChangeNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +void canMessageNotification( canBASE_t * node, uint32 messageBox ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +void dccNotification( dccBASE_t * dcc, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +void gioNotification( gioPORT_t * port, uint32 bit ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ +void linNotification( linBASE_t * lin, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +void sciNotification( sciBASE_t * sci, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ +void edgeNotification( hetBASE_t * hetREG, uint32 edge ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (40) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ +void hetNotification( hetBASE_t * het, uint32 offset ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +void crcNotification( crcBASE_t * crc, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (45) */ +/* USER CODE END */ + +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + +void etpwmNotification( etpwmBASE_t * node ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (47) */ + /* USER CODE END */ +} +void etpwmTripNotification( etpwmBASE_t * node, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (48) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + +void eqepNotification( eqepBASE_t * eqep, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (52) */ +/* USER CODE END */ + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + +void ecapNotification( ecapBASE_t * ecap, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (54) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + +void epcCAMFullNotification( void ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (57) */ + /* USER CODE END */ +} +void epcFIFOFullNotification( uint32 epcFIFOStatus ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (58) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + +void emacTxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (60) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ +void emacRxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (62) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (63) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c new file mode 100644 index 00000000000..e5a51eee03b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c @@ -0,0 +1,433 @@ +/** + * \file phy_dp83640.c + * + * \brief APIs for configuring DP83640. + * + * This file contains the device abstraction APIs for PHY DP83640. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : CONQ_EMAC_SR69 */ +uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : CONQ_EMAC_SR67 */ +boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * DP83640_100BTX - 100BaseTX + * DP83640_100BTX_FD - Full duplex capabilty for 100BaseTX + * DP83640_10BT - 10BaseT + * DP83640_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : CONQ_EMAC_SR66 */ +boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : CONQ_EMAC_SR68 */ +boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : CONQ_EMAC_SR65 */ +void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint16 regVal = 0U; + uint16 * regPtr = ®Val; + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET ); + + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, regPtr ); + /* : This bit is self-clearing and returns 1 until the reset process is complete. */ + while( ( regVal & PHY_SOFTRESET ) != 0U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, regPtr ); + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : CONQ_EMAC_SR72 */ +void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + uint16 * regPtr = ®Val; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regPtr ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : CONQ_EMAC_SR73 */ +void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + uint16 * regPtr = ®Val; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regPtr ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : CONQ_EMAC_SR75 */ +uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c new file mode 100644 index 00000000000..d6954591150 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c @@ -0,0 +1,401 @@ +/** + * \file phy_Tlk111.c + * + * \brief APIs for configuring Tlk111. + * + * This file contains the device abstraction APIs for PHY Tlk111. + */ + +/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com + * ALL RIGHTS RESERVED + */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_tlk111.h" + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : ETH_SR49 */ +uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR1, Tlk111_SWSCR1_Val ); + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR2, Tlk111_SWSCR2_Val ); + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR3, Tlk111_SWSCR3_Val ); + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_SWSCR1, + ( Tlk111_SWSCR1_Val | Tlk111_SWStrapDone ) ); +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : ETH_SR47 */ +boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * Tlk111_100BTX - 100BaseTX + * Tlk111_100BTX_FD - Full duplex capabilty for 100BaseTX + * Tlk111_10BT - 10BaseT + * Tlk111_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : ETH_SR46 */ +boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : ETH_SR48 */ +boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : ETH_SR44 */ +void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_LPBK_ENABLE ); + /* A wait of 3us is required before allowing further operation. */ + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : ETH_SR51 */ +void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : ETH_SR51 */ +void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : ETH_SR53 */ +uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} + +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c new file mode 100644 index 00000000000..a8bca743bfa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c @@ -0,0 +1,559 @@ +/** @file pinmux.c + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include "pinmux.h" + +#define PINMUX_GIOB_DISABLE_HET2_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 179 ] = ( pinMuxReg->PINMUX[ 179 ] \ + & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +#define PINMUX_GIOA_DISABLE_HET1_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 179 ] = ( pinMuxReg->PINMUX[ 179 ] \ + & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +#define PINMUX_ETHERNET_SELECT( interface ) \ + ( pinMuxReg->PINMUX[ 160 ] = ( pinMuxReg->PINMUX[ 160 ] & PINMUX_ETHERNET_MASK ) \ + | ( PINMUX_ETHERNET_##interface ) ) + +#define PINMUX_ETPWM1_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM1_MASK ) \ + | ( PINMUX_ETPWM1_##interface ) ) + +#define PINMUX_ETPWM2_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM2_MASK ) \ + | ( PINMUX_ETPWM2_##interface ) ) + +#define PINMUX_ETPWM3_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM3_MASK ) \ + | ( PINMUX_ETPWM3_##interface ) ) + +#define PINMUX_ETPWM4_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM4_MASK ) \ + | ( PINMUX_ETPWM4_##interface ) ) + +#define PINMUX_ETPWM5_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM5_MASK ) \ + | ( PINMUX_ETPWM5_##interface ) ) + +#define PINMUX_ETPWM6_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM6_MASK ) \ + | ( PINMUX_ETPWM6_##interface ) ) + +#define PINMUX_ETPWM7_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM7_MASK ) \ + | ( PINMUX_ETPWM7_##interface ) ) + +#define PINMUX_ETPWM_TZ1_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] & PINMUX_TZ1_MASK ) \ + | ( PINMUX_TZ1_##interface ) ) + +#define PINMUX_ETPWM_TZ2_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] & PINMUX_TZ2_MASK ) \ + | ( PINMUX_TZ2_##interface ) ) + +#define PINMUX_ETPWM_TZ3_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TZ3_MASK ) \ + | ( PINMUX_TZ3_##interface ) ) + +#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_EPWM1SYNCI_MASK ) \ + | ( PINMUX_EPWM1SYNCI_##interface ) ) + +#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 165 ] \ + & PINMUX_ETPWM_TIME_BASE_SYNC_MASK ) \ + | ( PINMUX_ETPWM_TIME_BASE_SYNC_##state ) ) + +#define PINMUX_ETPWM_SOC1A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC1A_MASK ) \ + | ( PINMUX_ETPWM_SOC1A_##state ) ) + +#define PINMUX_ETPWM_SOC2A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC2A_MASK ) \ + | ( PINMUX_ETPWM_SOC2A_##state ) ) + +#define PINMUX_ETPWM_SOC3A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC3A_MASK ) \ + | ( PINMUX_ETPWM_SOC3A_##state ) ) + +#define PINMUX_ETPWM_SOC4A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC4A_MASK ) \ + | ( PINMUX_ETPWM_SOC4A_##state ) ) + +#define PINMUX_ETPWM_SOC5A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC5A_MASK ) \ + | ( PINMUX_ETPWM_SOC5A_##state ) ) + +#define PINMUX_ETPWM_SOC6A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC6A_MASK ) \ + | ( PINMUX_ETPWM_SOC6A_##state ) ) + +#define PINMUX_ETPWM_SOC7A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC7A_MASK ) \ + | ( PINMUX_ETPWM_SOC7A_##state ) ) + +#define PINMUX_GATE_EMIF_CLK_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 9 ] = ( pinMuxReg->PINMUX[ 9 ] & PINMUX_GATE_EMIF_CLK_MASK ) \ + | ( PINMUX_GATE_EMIF_CLK_##state ) ) + +#define PINMUX_ALT_ADC_TRIGGER_SELECT( num ) \ + ( pinMuxReg->PINMUX[ 161 ] = ( pinMuxReg->PINMUX[ 161 ] \ + & PINMUX_ALT_ADC_TRIGGER_MASK ) \ + | ( PINMUX_ALT_ADC_TRIGGER_##num ) ) + +#define PINMUX_EMIF_OUTPUT_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 174 ] = ( pinMuxReg->PINMUX[ 174 ] \ + & PINMUX_EMIF_OUTPUT_ENABLE_MASK ) \ + | ( PINMUX_EMIF_OUTPUT_ENABLE_##state ) ) + +#define PINMUX_EQEP1A_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] \ + & PINMUX_EQEP1A_FILTER_MASK ) \ + | ( PINMUX_EQEP1A_FILTER_##state ) ) + +#define PINMUX_EQEP1B_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] \ + & PINMUX_EQEP1B_FILTER_MASK ) \ + | ( PINMUX_EQEP1B_FILTER_##state ) ) + +#define PINMUX_EQEP1I_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP1I_FILTER_MASK ) \ + | ( PINMUX_EQEP1I_FILTER_##state ) ) + +#define PINMUX_EQEP1S_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP1S_FILTER_MASK ) \ + | ( PINMUX_EQEP1S_FILTER_##state ) ) + +#define PINMUX_EQEP2A_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP2A_FILTER_MASK ) \ + | ( PINMUX_EQEP2A_FILTER_##state ) ) + +#define PINMUX_EQEP2B_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP2B_FILTER_MASK ) \ + | ( PINMUX_EQEP2B_FILTER_##state ) ) + +#define PINMUX_EQEP2I_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] \ + & PINMUX_EQEP2I_FILTER_MASK ) \ + | ( PINMUX_EQEP2I_FILTER_##state ) ) + +#define PINMUX_EQEP2S_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] \ + & PINMUX_EQEP2S_FILTER_MASK ) \ + | ( PINMUX_EQEP2S_FILTER_##state ) ) + +#define PINMUX_ECAP1_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP1_FILTER_MASK ) \ + | ( PINMUX_ECAP1_FILTER_##state ) ) + +#define PINMUX_ECAP2_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP2_FILTER_MASK ) \ + | ( PINMUX_ECAP2_FILTER_##state ) ) + +#define PINMUX_ECAP3_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP3_FILTER_MASK ) \ + | ( PINMUX_ECAP3_FILTER_##state ) ) + +#define PINMUX_ECAP4_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP4_FILTER_MASK ) \ + | ( PINMUX_ECAP4_FILTER_##state ) ) + +#define PINMUX_ECAP5_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] & PINMUX_ECAP5_FILTER_MASK ) \ + | ( PINMUX_ECAP5_FILTER_##state ) ) + +#define PINMUX_ECAP6_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] & PINMUX_ECAP6_FILTER_MASK ) \ + | ( PINMUX_ECAP6_FILTER_##state ) ) + +#define PINMUX_GIOA0_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA0_DMA_MASK ) \ + | ( PINMUX_GIOA0_DMA_##state ) ) + +#define PINMUX_GIOA1_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA1_DMA_MASK ) \ + | ( PINMUX_GIOA1_DMA_##state ) ) + +#define PINMUX_GIOA2_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA2_DMA_MASK ) \ + | ( PINMUX_GIOA2_DMA_##state ) ) + +#define PINMUX_GIOA3_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA3_DMA_MASK ) \ + | ( PINMUX_GIOA3_DMA_##state ) ) + +#define PINMUX_GIOA4_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA4_DMA_MASK ) \ + | ( PINMUX_GIOA4_DMA_##state ) ) + +#define PINMUX_GIOA5_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA5_DMA_MASK ) \ + | ( PINMUX_GIOA5_DMA_##state ) ) + +#define PINMUX_GIOA6_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA6_DMA_MASK ) \ + | ( PINMUX_GIOA6_DMA_##state ) ) + +#define PINMUX_GIOA7_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA7_DMA_MASK ) \ + | ( PINMUX_GIOA7_DMA_##state ) ) + +#define PINMUX_GIOB0_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB0_DMA_MASK ) \ + | ( PINMUX_GIOB0_DMA_##state ) ) + +#define PINMUX_GIOB1_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB1_DMA_MASK ) \ + | ( PINMUX_GIOB1_DMA_##state ) ) + +#define PINMUX_GIOB2_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB2_DMA_MASK ) \ + | ( PINMUX_GIOB2_DMA_##state ) ) + +#define PINMUX_GIOB3_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB3_DMA_MASK ) \ + | ( PINMUX_GIOB3_DMA_##state ) ) + +#define PINMUX_GIOB4_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB4_DMA_MASK ) \ + | ( PINMUX_GIOB4_DMA_##state ) ) + +#define PINMUX_GIOB5_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB5_DMA_MASK ) \ + | ( PINMUX_GIOB5_DMA_##state ) ) + +#define PINMUX_GIOB6_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB6_DMA_MASK ) \ + | ( PINMUX_GIOB6_DMA_##state ) ) + +#define PINMUX_GIOB7_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB7_DMA_MASK ) \ + | ( PINMUX_GIOB7_DMA_##state ) ) + +#define PINMUX_TEMP1_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TEMP1_ENABLE_MASK ) \ + | ( PINMUX_TEMP1_ENABLE_##state ) ) + +#define PINMUX_TEMP2_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TEMP2_ENABLE_MASK ) \ + | ( PINMUX_TEMP2_ENABLE_##state ) ) + +#define PINMUX_TEMP3_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 174 ] = ( pinMuxReg->PINMUX[ 174 ] & PINMUX_TEMP3_ENABLE_MASK ) \ + | ( PINMUX_TEMP3_ENABLE_##state ) ) + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +void muxInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + pinMuxReg->PINMUX[ 0 ] = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_D4_EMIF_ADDR_00 + | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06; + + pinMuxReg->PINMUX[ 1 ] = PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 + | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10; + + pinMuxReg->PINMUX[ 2 ] = PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 + | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14; + + pinMuxReg->PINMUX[ 3 ] = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 + | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18; + + pinMuxReg->PINMUX[ 4 ] = PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 + | PINMUX_BALL_C17_EMIF_ADDR_21; + + pinMuxReg->PINMUX[ 5 ] = 0U; + + pinMuxReg->PINMUX[ 6 ] = 0U; + + pinMuxReg->PINMUX[ 7 ] = 0U; + + pinMuxReg->PINMUX[ 8 ] = PINMUX_BALL_D16_EMIF_BA_1; + + pinMuxReg->PINMUX[ 9 ] = PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 + | PINMUX_BALL_L17_EMIF_nCS_2; + + pinMuxReg->PINMUX[ 10 ] = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 + | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT; + + pinMuxReg->PINMUX[ 11 ] = PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_ETMDATA_08 + | PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_E7_ETMDATA_10; + + pinMuxReg->PINMUX[ 12 ] = PINMUX_BALL_E6_ETMDATA_11 | PINMUX_BALL_E13_ETMDATA_12 + | PINMUX_BALL_E12_ETMDATA_13 | PINMUX_BALL_E11_ETMDATA_14; + + pinMuxReg->PINMUX[ 13 ] = PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_K15_ETMDATA_16 + | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_M15_ETMDATA_18; + + pinMuxReg->PINMUX[ 14 ] = PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_E5_ETMDATA_20 + | PINMUX_BALL_F5_ETMDATA_21 | PINMUX_BALL_G5_ETMDATA_22; + + pinMuxReg->PINMUX[ 15 ] = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_L5_ETMDATA_24 + | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_N5_ETMDATA_26; + + pinMuxReg->PINMUX[ 16 ] = PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_R5_ETMDATA_28 + | PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_R7_ETMDATA_30; + + pinMuxReg->PINMUX[ 17 ] = PINMUX_BALL_R8_ETMDATA_31 | PINMUX_BALL_R9_ETMTRACECLKIN + | PINMUX_BALL_R10_ETMTRACECLKOUT + | PINMUX_BALL_R11_ETMTRACECTL; + + pinMuxReg->PINMUX[ 18 ] = PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 + | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2; + + pinMuxReg->PINMUX[ 19 ] = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 + | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6; + + pinMuxReg->PINMUX[ 20 ] = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 + | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6; + + pinMuxReg->PINMUX[ 21 ] = PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MIBSPI1NCS_0 + | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_MIBSPI1NCS_2; + + pinMuxReg->PINMUX[ 22 ] = PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MIBSPI1NENA + | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0; + + pinMuxReg->PINMUX[ 23 ] = PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_B2_MIBSPI3NCS_2 + | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA; + + pinMuxReg->PINMUX[ 24 ] = PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI + | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_E19_MIBSPI5NCS_0; + + pinMuxReg->PINMUX[ 25 ] = PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 + | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MIBSPI5NENA; + + pinMuxReg->PINMUX[ 26 ] = PINMUX_BALL_J19_MIBSPI5SIMO_0 + | PINMUX_BALL_E16_MIBSPI5SIMO_1 + | PINMUX_BALL_H17_MIBSPI5SIMO_2 + | PINMUX_BALL_G17_MIBSPI5SIMO_3; + + pinMuxReg->PINMUX[ 27 ] = PINMUX_BALL_J18_MIBSPI5SOMI_0 + | PINMUX_BALL_E17_MIBSPI5SOMI_1 + | PINMUX_BALL_H16_MIBSPI5SOMI_2 + | PINMUX_BALL_G16_MIBSPI5SOMI_3; + + pinMuxReg->PINMUX[ 28 ] = PINMUX_BALL_K18_N2HET1_00 | PINMUX_BALL_V2_N2HET1_01 + | PINMUX_BALL_W5_N2HET1_02 | PINMUX_BALL_U1_N2HET1_03; + + pinMuxReg->PINMUX[ 29 ] = PINMUX_BALL_B12_N2HET1_04 | PINMUX_BALL_V6_N2HET1_05 + | PINMUX_BALL_W3_N2HET1_06 | PINMUX_BALL_T1_N2HET1_07; + + pinMuxReg->PINMUX[ 30 ] = PINMUX_BALL_E18_N2HET1_08 | PINMUX_BALL_V7_N2HET1_09 + | PINMUX_BALL_D19_N2HET1_10 | PINMUX_BALL_E3_N2HET1_11; + + pinMuxReg->PINMUX[ 31 ] = PINMUX_BALL_B4_N2HET1_12 | PINMUX_BALL_N2_N2HET1_13 + | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16; + + pinMuxReg->PINMUX[ 32 ] = PINMUX_BALL_A13_N2HET1_17 | PINMUX_BALL_J1_N2HET1_18 + | PINMUX_BALL_B13_N2HET1_19 | PINMUX_BALL_P2_N2HET1_20; + + pinMuxReg->PINMUX[ 33 ] = PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 + | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_N2HET1_24; + + pinMuxReg->PINMUX[ 34 ] = PINMUX_BALL_A14_N2HET1_26 | PINMUX_BALL_K19_N2HET1_28 + | PINMUX_BALL_B11_N2HET1_30 | PINMUX_BALL_D8_N2HET2_01; + + pinMuxReg->PINMUX[ 35 ] = PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_N2HET2_12 + | PINMUX_BALL_D2_N2HET2_13 | PINMUX_BALL_D1_N2HET2_14; + + pinMuxReg->PINMUX[ 36 ] = PINMUX_BALL_P4_N2HET2_19 | PINMUX_BALL_T5_N2HET2_20 + | PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK; + + pinMuxReg->PINMUX[ 37 ] = PINMUX_BALL_E2_N2HET2_03 | PINMUX_BALL_N3_N2HET2_07; + + pinMuxReg->PINMUX[ 80 ] = ( SIGNAL_AD2EVT_T10 | 0x02020200U ); + + pinMuxReg->PINMUX[ 81 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 82 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 83 ] = ( SIGNAL_GIOA_0_A5 | 0x00020202U ); + + pinMuxReg->PINMUX[ 84 ] = SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 + | SIGNAL_GIOA_4_A6; + + pinMuxReg->PINMUX[ 85 ] = SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 + | SIGNAL_GIOB_0_M2; + + pinMuxReg->PINMUX[ 86 ] = SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_F2 | SIGNAL_GIOB_3_W10 + | SIGNAL_GIOB_4_G1; + + pinMuxReg->PINMUX[ 87 ] = SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 + | SIGNAL_MDIO_F4; + + pinMuxReg->PINMUX[ 88 ] = ( SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9 + | 0x00020000U ); + + pinMuxReg->PINMUX[ 89 ] = SIGNAL_MII_COL_W4 | SIGNAL_MII_CRS_V4; + + pinMuxReg->PINMUX[ 90 ] = SIGNAL_MII_RX_DV_U6 | SIGNAL_MII_RX_ER_U5 + | SIGNAL_MII_RXCLK_T4 | SIGNAL_MII_RXD_0_U4; + + pinMuxReg->PINMUX[ 91 ] = SIGNAL_MII_RXD_1_T3 | SIGNAL_MII_RXD_2_U3 + | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_U7; + + pinMuxReg->PINMUX[ 92 ] = SIGNAL_N2HET1_17_A13 | SIGNAL_N2HET1_19_B13 + | SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4; + + pinMuxReg->PINMUX[ 93 ] = SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 + | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17; + + pinMuxReg->PINMUX[ 94 ] = SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 + | SIGNAL_N2HET2_02_D7 | SIGNAL_N2HET2_03_E2; + + pinMuxReg->PINMUX[ 95 ] = SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 + | SIGNAL_N2HET2_06_D11 | SIGNAL_N2HET2_07_N3; + + pinMuxReg->PINMUX[ 96 ] = SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 + | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16; + + pinMuxReg->PINMUX[ 97 ] = SIGNAL_N2HET2_12_D3 | SIGNAL_N2HET2_13_D2 + | SIGNAL_N2HET2_14_D1 | SIGNAL_N2HET2_15_K4; + + pinMuxReg->PINMUX[ 98 ] = SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 + | SIGNAL_N2HET2_20_T5 | SIGNAL_N2HET2_22_T7; + + pinMuxReg->PINMUX[ 99 ] = SIGNAL_nTZ1_1_N19 | SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3; + + pinMuxReg->PINMUX[ 161 ] = 0x02020200U; + + pinMuxReg->PINMUX[ 162 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 163 ] = 0x00020202U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + PINMUX_GATE_EMIF_CLK_ENABLE( OFF ); + PINMUX_EMIF_OUTPUT_ENABLE( OFF ); + PINMUX_GIOA_DISABLE_HET1_ENABLE( OFF ); + PINMUX_GIOB_DISABLE_HET2_ENABLE( OFF ); + PINMUX_ETHERNET_SELECT( MII ); + PINMUX_ALT_ADC_TRIGGER_SELECT( 1 ); + + PINMUX_ETPWM1_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM2_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM3_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM4_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM5_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM6_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM7_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( OFF ); + PINMUX_ETPWM_TZ1_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ2_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ3_ENABLE( ASYNC ); + PINMUX_ETPWM_EPWM1SYNCI_ENABLE( ASYNC ); + + PINMUX_ETPWM_SOC1A_ENABLE( ON ); + PINMUX_ETPWM_SOC2A_ENABLE( ON ); + PINMUX_ETPWM_SOC3A_ENABLE( ON ); + PINMUX_ETPWM_SOC4A_ENABLE( ON ); + PINMUX_ETPWM_SOC5A_ENABLE( ON ); + PINMUX_ETPWM_SOC6A_ENABLE( ON ); + PINMUX_ETPWM_SOC7A_ENABLE( ON ); + + PINMUX_EQEP1A_FILTER_ENABLE( OFF ); + PINMUX_EQEP1B_FILTER_ENABLE( OFF ); + PINMUX_EQEP1I_FILTER_ENABLE( OFF ); + PINMUX_EQEP1S_FILTER_ENABLE( OFF ); + PINMUX_EQEP2A_FILTER_ENABLE( OFF ); + PINMUX_EQEP2B_FILTER_ENABLE( OFF ); + PINMUX_EQEP2I_FILTER_ENABLE( OFF ); + PINMUX_EQEP2S_FILTER_ENABLE( OFF ); + + PINMUX_ECAP1_FILTER_ENABLE( OFF ); + PINMUX_ECAP2_FILTER_ENABLE( OFF ); + PINMUX_ECAP3_FILTER_ENABLE( OFF ); + PINMUX_ECAP4_FILTER_ENABLE( OFF ); + PINMUX_ECAP5_FILTER_ENABLE( OFF ); + PINMUX_ECAP6_FILTER_ENABLE( OFF ); + + PINMUX_GIOA0_DMA_ENABLE( OFF ); + PINMUX_GIOA1_DMA_ENABLE( OFF ); + PINMUX_GIOA2_DMA_ENABLE( OFF ); + PINMUX_GIOA3_DMA_ENABLE( OFF ); + PINMUX_GIOA4_DMA_ENABLE( OFF ); + PINMUX_GIOA5_DMA_ENABLE( OFF ); + PINMUX_GIOA6_DMA_ENABLE( OFF ); + PINMUX_GIOA7_DMA_ENABLE( OFF ); + PINMUX_GIOB0_DMA_ENABLE( OFF ); + PINMUX_GIOB1_DMA_ENABLE( OFF ); + PINMUX_GIOB2_DMA_ENABLE( OFF ); + PINMUX_GIOB3_DMA_ENABLE( OFF ); + PINMUX_GIOB4_DMA_ENABLE( OFF ); + PINMUX_GIOB5_DMA_ENABLE( OFF ); + PINMUX_GIOB6_DMA_ENABLE( OFF ); + PINMUX_GIOB7_DMA_ENABLE( OFF ); + + pinMuxReg->PINMUX[ 174 ] |= ( uint32 ) ( ~( 0XFEFFFFFFU ) ); + + PINMUX_TEMP1_ENABLE( OFF ); + PINMUX_TEMP2_ENABLE( OFF ); + PINMUX_TEMP3_ENABLE( OFF ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c new file mode 100644 index 00000000000..3813fc4b809 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c @@ -0,0 +1,354 @@ +/** @file pom.c + * @brief POM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "pom.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num) + * @brief set the prog start address,overlay address,and size in the respective register + * for specified region number. + * @param[in] Reg_Config_Ptr - this will have the prog start address and overlay + * addresses and size which have to be set in the registers + * @param[in] Region_Num - Region number is used to access registers(for the specified + * region number) + * + */ +/* SourceId : POM_SourceId_001 */ +/* DesignId : POM_DesignId_001 */ +/* Requirements : CONQ_POM_SR3 */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + pomREG->POMRGNCONF_ST[ Region_Num ].POMPROGSTART = Reg_Config_Ptr->Prog_Reg_Sta_Addr; + pomREG->POMRGNCONF_ST[ Region_Num ].POMOVLSTART = Reg_Config_Ptr->Ovly_Reg_Sta_Addr; + pomREG->POMRGNCONF_ST[ Region_Num ].POMREGSIZE = Reg_Config_Ptr->Reg_Size; + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void POM_Reset(void) + * @brief Reset POM module. + */ +/* SourceId : POM_SourceId_002 */ +/* DesignId : POM_DesignId_002 */ +/* Requirements : CONQ_POM_SR4 */ +void POM_Reset( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = 0x5U; + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void void POM_Init(void) + * @brief Initializes the POM driver + * + * This function initializes the POM driver single function handles all the + * regions,timeouts are also handled. POM_Enable() function must be called after + * POM_Init() function. + */ +/* SourceId : POM_SourceId_003 */ +/* DesignId : POM_DesignId_003 */ +/* Requirements : CONQ_POM_SR2 */ +void POM_Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = INTERNAL_RAM | 0x00000005U; + + /* Configure region 1 */ + pomREG->POMRGNCONF_ST[ 0U ].POMPROGSTART = 0x00000000U; + pomREG->POMRGNCONF_ST[ 0U ].POMOVLSTART = 0x00000000U; + pomREG->POMRGNCONF_ST[ 0U ].POMREGSIZE = ( uint32 ) SIZE_64BYTES; + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void POM_Enable(void) + * @brief Enable POM module. + */ +/* SourceId : POM_SourceId_004 */ +/* DesignId : POM_DesignId_004 */ +/* Requirements : CONQ_POM_SR5 */ +void POM_Enable( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = ( ( pomREG->POMGLBCTRL & 0xFFFFFFF0U ) + | ( uint32 ) 0x0000000AU ); + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void pomGetConfigValue(pom_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the POM configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +/* SourceId : POM_SourceId_005 */ +/* DesignId : POM_DesignId_005 */ +/* Requirements : CONQ_POM_SR6 */ +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_POMGLBCTRL = POM_POMGLBCTRL_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART0 = POM_POMPROGSTART0_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART0 = POM_POMOVLSTART0_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE0 = POM_POMREGSIZE0_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART1 = POM_POMPROGSTART1_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART1 = POM_POMOVLSTART1_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE1 = POM_POMREGSIZE1_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART2 = POM_POMPROGSTART2_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART2 = POM_POMOVLSTART2_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE2 = POM_POMREGSIZE2_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART3 = POM_POMPROGSTART3_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART3 = POM_POMOVLSTART3_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE3 = POM_POMREGSIZE3_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART4 = POM_POMPROGSTART4_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART4 = POM_POMOVLSTART4_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE4 = POM_POMREGSIZE4_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART5 = POM_POMPROGSTART5_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART5 = POM_POMOVLSTART5_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE5 = POM_POMREGSIZE5_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART6 = POM_POMPROGSTART6_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART6 = POM_POMOVLSTART6_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE6 = POM_POMREGSIZE6_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART7 = POM_POMPROGSTART7_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART7 = POM_POMOVLSTART7_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE7 = POM_POMREGSIZE7_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART8 = POM_POMPROGSTART8_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART8 = POM_POMOVLSTART8_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE8 = POM_POMREGSIZE8_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART9 = POM_POMPROGSTART9_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART9 = POM_POMOVLSTART9_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE9 = POM_POMREGSIZE9_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART10 = POM_POMPROGSTART10_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART10 = POM_POMOVLSTART10_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE10 = POM_POMREGSIZE10_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART11 = POM_POMPROGSTART11_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART11 = POM_POMOVLSTART11_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE11 = POM_POMREGSIZE11_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART12 = POM_POMPROGSTART12_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART12 = POM_POMOVLSTART12_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE12 = POM_POMREGSIZE12_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART13 = POM_POMPROGSTART13_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART13 = POM_POMOVLSTART13_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE13 = POM_POMREGSIZE13_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART14 = POM_POMPROGSTART14_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART14 = POM_POMOVLSTART14_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE14 = POM_POMREGSIZE14_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART15 = POM_POMPROGSTART15_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART15 = POM_POMOVLSTART15_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE15 = POM_POMREGSIZE15_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART16 = POM_POMPROGSTART16_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART16 = POM_POMOVLSTART16_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE16 = POM_POMREGSIZE16_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART17 = POM_POMPROGSTART17_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART17 = POM_POMOVLSTART17_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE17 = POM_POMREGSIZE17_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART18 = POM_POMPROGSTART18_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART18 = POM_POMOVLSTART18_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE18 = POM_POMREGSIZE18_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART19 = POM_POMPROGSTART19_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART19 = POM_POMOVLSTART19_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE19 = POM_POMREGSIZE19_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART20 = POM_POMPROGSTART20_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART20 = POM_POMOVLSTART20_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE20 = POM_POMREGSIZE20_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART21 = POM_POMPROGSTART21_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART21 = POM_POMOVLSTART21_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE21 = POM_POMREGSIZE21_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART22 = POM_POMPROGSTART22_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART22 = POM_POMOVLSTART22_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE22 = POM_POMREGSIZE22_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART23 = POM_POMPROGSTART23_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART23 = POM_POMOVLSTART23_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE23 = POM_POMREGSIZE23_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART24 = POM_POMPROGSTART24_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART24 = POM_POMOVLSTART24_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE24 = POM_POMREGSIZE24_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART25 = POM_POMPROGSTART25_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART25 = POM_POMOVLSTART25_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE25 = POM_POMREGSIZE25_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART26 = POM_POMPROGSTART26_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART26 = POM_POMOVLSTART26_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE26 = POM_POMREGSIZE26_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART27 = POM_POMPROGSTART27_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART27 = POM_POMOVLSTART27_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE27 = POM_POMREGSIZE27_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART28 = POM_POMPROGSTART28_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART28 = POM_POMOVLSTART28_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE28 = POM_POMREGSIZE28_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART29 = POM_POMPROGSTART29_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART29 = POM_POMOVLSTART29_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE29 = POM_POMREGSIZE29_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART30 = POM_POMPROGSTART30_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART30 = POM_POMOVLSTART30_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE30 = POM_POMREGSIZE30_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART31 = POM_POMPROGSTART31_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART31 = POM_POMOVLSTART31_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE31 = POM_POMREGSIZE31_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_POMGLBCTRL = pomREG->POMGLBCTRL; + config_reg->CONFIG_POMPROGSTART0 = pomREG->POMRGNCONF_ST[ 0 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART0 = pomREG->POMRGNCONF_ST[ 0 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE0 = pomREG->POMRGNCONF_ST[ 0 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART1 = pomREG->POMRGNCONF_ST[ 1 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART1 = pomREG->POMRGNCONF_ST[ 1 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE1 = pomREG->POMRGNCONF_ST[ 1 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART2 = pomREG->POMRGNCONF_ST[ 2 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART2 = pomREG->POMRGNCONF_ST[ 2 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE2 = pomREG->POMRGNCONF_ST[ 2 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART3 = pomREG->POMRGNCONF_ST[ 3 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART3 = pomREG->POMRGNCONF_ST[ 3 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE3 = pomREG->POMRGNCONF_ST[ 3 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART4 = pomREG->POMRGNCONF_ST[ 4 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART4 = pomREG->POMRGNCONF_ST[ 4 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE4 = pomREG->POMRGNCONF_ST[ 4 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART5 = pomREG->POMRGNCONF_ST[ 5 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART5 = pomREG->POMRGNCONF_ST[ 5 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE5 = pomREG->POMRGNCONF_ST[ 5 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART6 = pomREG->POMRGNCONF_ST[ 6 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART6 = pomREG->POMRGNCONF_ST[ 6 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE6 = pomREG->POMRGNCONF_ST[ 6 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART7 = pomREG->POMRGNCONF_ST[ 7 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART7 = pomREG->POMRGNCONF_ST[ 7 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE7 = pomREG->POMRGNCONF_ST[ 7 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART8 = pomREG->POMRGNCONF_ST[ 8 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART8 = pomREG->POMRGNCONF_ST[ 8 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE8 = pomREG->POMRGNCONF_ST[ 8 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART9 = pomREG->POMRGNCONF_ST[ 9 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART9 = pomREG->POMRGNCONF_ST[ 9 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE9 = pomREG->POMRGNCONF_ST[ 9 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART10 = pomREG->POMRGNCONF_ST[ 10 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART10 = pomREG->POMRGNCONF_ST[ 10 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE10 = pomREG->POMRGNCONF_ST[ 10 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART11 = pomREG->POMRGNCONF_ST[ 11 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART11 = pomREG->POMRGNCONF_ST[ 11 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE11 = pomREG->POMRGNCONF_ST[ 11 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART12 = pomREG->POMRGNCONF_ST[ 12 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART12 = pomREG->POMRGNCONF_ST[ 12 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE12 = pomREG->POMRGNCONF_ST[ 12 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART13 = pomREG->POMRGNCONF_ST[ 13 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART13 = pomREG->POMRGNCONF_ST[ 13 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE13 = pomREG->POMRGNCONF_ST[ 13 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART14 = pomREG->POMRGNCONF_ST[ 14 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART14 = pomREG->POMRGNCONF_ST[ 14 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE14 = pomREG->POMRGNCONF_ST[ 14 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART15 = pomREG->POMRGNCONF_ST[ 15 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART15 = pomREG->POMRGNCONF_ST[ 15 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE15 = pomREG->POMRGNCONF_ST[ 15 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART16 = pomREG->POMRGNCONF_ST[ 16 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART16 = pomREG->POMRGNCONF_ST[ 16 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE16 = pomREG->POMRGNCONF_ST[ 16 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART17 = pomREG->POMRGNCONF_ST[ 17 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART17 = pomREG->POMRGNCONF_ST[ 17 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE17 = pomREG->POMRGNCONF_ST[ 17 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART18 = pomREG->POMRGNCONF_ST[ 18 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART18 = pomREG->POMRGNCONF_ST[ 18 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE18 = pomREG->POMRGNCONF_ST[ 18 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART19 = pomREG->POMRGNCONF_ST[ 19 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART19 = pomREG->POMRGNCONF_ST[ 19 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE19 = pomREG->POMRGNCONF_ST[ 19 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART20 = pomREG->POMRGNCONF_ST[ 20 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART20 = pomREG->POMRGNCONF_ST[ 20 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE20 = pomREG->POMRGNCONF_ST[ 20 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART21 = pomREG->POMRGNCONF_ST[ 20 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART21 = pomREG->POMRGNCONF_ST[ 21 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE21 = pomREG->POMRGNCONF_ST[ 21 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART22 = pomREG->POMRGNCONF_ST[ 21 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART22 = pomREG->POMRGNCONF_ST[ 22 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE22 = pomREG->POMRGNCONF_ST[ 22 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART23 = pomREG->POMRGNCONF_ST[ 22 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART23 = pomREG->POMRGNCONF_ST[ 23 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE23 = pomREG->POMRGNCONF_ST[ 23 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART24 = pomREG->POMRGNCONF_ST[ 23 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART24 = pomREG->POMRGNCONF_ST[ 24 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE24 = pomREG->POMRGNCONF_ST[ 24 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART25 = pomREG->POMRGNCONF_ST[ 24 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART25 = pomREG->POMRGNCONF_ST[ 25 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE25 = pomREG->POMRGNCONF_ST[ 25 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART26 = pomREG->POMRGNCONF_ST[ 25 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART26 = pomREG->POMRGNCONF_ST[ 26 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE26 = pomREG->POMRGNCONF_ST[ 26 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART27 = pomREG->POMRGNCONF_ST[ 26 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART27 = pomREG->POMRGNCONF_ST[ 27 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE27 = pomREG->POMRGNCONF_ST[ 27 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART28 = pomREG->POMRGNCONF_ST[ 27 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART28 = pomREG->POMRGNCONF_ST[ 28 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE28 = pomREG->POMRGNCONF_ST[ 28 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART29 = pomREG->POMRGNCONF_ST[ 28 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART29 = pomREG->POMRGNCONF_ST[ 29 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE29 = pomREG->POMRGNCONF_ST[ 29 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART30 = pomREG->POMRGNCONF_ST[ 30 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART30 = pomREG->POMRGNCONF_ST[ 30 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE30 = pomREG->POMRGNCONF_ST[ 30 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART31 = pomREG->POMRGNCONF_ST[ 31 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART31 = pomREG->POMRGNCONF_ST[ 31 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE31 = pomREG->POMRGNCONF_ST[ 31 ].POMREGSIZE; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c new file mode 100644 index 00000000000..12377f8e060 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c @@ -0,0 +1,994 @@ +/** @file sci.c + * @brief SCI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +#include +/* USER CODE END */ + +#include "sci.h" +#include "sys_vim.h" +#include "math.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_sciTransfer + * @brief Interrupt mode globals + * + */ +static volatile struct g_sciTransfer +{ + uint32 mode; /* Used to check for TX interrupt Enable */ + uint32 tx_length; /* Transmit data length in number of Bytes */ + uint32 rx_length; /* Receive data length in number of Bytes */ + uint8 * tx_data; /* Transmit data pointer */ + uint8 * rx_data; /* Receive data pointer */ +} g_sciTransfer_t[ 4U ]; + +/* SourceId : SCI_SourceId_001 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : CONQ_SCI_SR5 */ + +/** @fn void sciInit(void) + * @brief Initializes the SCI Driver + * + * This function initializes the SCI module. + */ +void sciInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b SCI3 */ + + /** - bring SCI3 out of reset */ + sciREG3->GCR0 = 0U; + sciREG3->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG3->CLEARINT = 0xFFFFFFFFU; + sciREG3->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG3->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG3->BRS = 40U; /* baudrate */ + + /** - transmission length */ + sciREG3->FORMAT = 8U - 1U; /* length */ + + /** - set SCI3 pins functional mode */ + sciREG3->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI3 pins default output value */ + sciREG3->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins output direction */ + sciREG3->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins open drain enable */ + sciREG3->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins pullup/pulldown enable */ + sciREG3->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins pullup/pulldown select */ + sciREG3->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG3->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG3->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 2U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 2U ].tx_length = 0U; + g_sciTransfer_t[ 2U ].rx_length = 0U; + + /** - Finaly start SCI3 */ + sciREG3->GCR1 |= 0x80U; + + /** @b initialize @b SCI4 */ + + /** - bring SCI4 out of reset */ + sciREG4->GCR0 = 0U; + sciREG4->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG4->CLEARINT = 0xFFFFFFFFU; + sciREG4->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG4->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG4->BRS = 40U; /* baudrate */ + + /** - transmission length */ + sciREG4->FORMAT = 8U - 1U; /* length */ + + /** - set SCI4 pins functional mode */ + sciREG4->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI4 pins default output value */ + sciREG4->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins output direction */ + sciREG4->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins open drain enable */ + sciREG4->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins pullup/pulldown enable */ + sciREG4->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins pullup/pulldown select */ + sciREG4->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG4->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG4->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 3U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 3U ].tx_length = 0U; + g_sciTransfer_t[ 3U ].rx_length = 0U; + + /** - Finaly start SCI4 */ + sciREG4->GCR1 |= 0x80U; + + /* USER CODE BEGIN (3) */ + /** @b initialize @b SCILIN */ + + /** - bring SCI out of reset */ + scilinREG->GCR0 = 0U; + scilinREG->GCR0 = 1U; + + /** - Disable all interrupts */ + scilinREG->CLEARINT = 0xFFFFFFFFU; + scilinREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + scilinREG->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has + no clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits + */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + scilinREG->BRS = 40U; /* baudrate */ + + /** - transmission length */ + scilinREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + scilinREG->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI pins default output value */ + scilinREG->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins output direction */ + scilinREG->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins open drain enable */ + scilinREG->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown enable */ + scilinREG->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown select */ + scilinREG->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + scilinREG->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - set interrupt enable */ + scilinREG->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 1U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 1U ].tx_length = 0U; + g_sciTransfer_t[ 1U ].rx_length = 0U; + + /** - Finaly start SCILIN */ + scilinREG->GCR1 |= 0x80U; + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_002 */ +/* DesignId : SCI_DesignId_002 */ +/* Requirements : CONQ_SCI_SR6 */ + +/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] sci - sci module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCPIO0 register at runtime, this allows to + * dynamically change the functionality of the SCI pins between functional + * and GIO mode. + */ +void sciSetFunctional( sciBASE_t * sci, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + sci->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_003 */ +/* DesignId : SCI_DesignId_003 */ +/* Requirements : CONQ_SCI_SR7 */ + +/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] sci - sci module base address + * @param[in] baud - baudrate in Hz + * + * Change the SCI baudrate at runtime. + */ +void sciSetBaudrate( sciBASE_t * sci, uint32 baud ) +{ + float64 vclk = 75.000 * 1000000.0; + uint32 f = ( ( sci->GCR1 & 2U ) == 2U ) ? 16U : 1U; + uint32 temp; + float64 temp2; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /*SAFETYMCUSW 96 S MR:6.1 "Calculations including int and float cannot be + * avoided" */ + temp = ( f * ( baud ) ); + temp2 = ( ( vclk ) / ( ( float64 ) temp ) ) - 1U; + temp2 = temp2 + 0.5; + sci->BRS = ( uint32 ) ( ( uint32 ) temp2 & 0x00FFFFFFU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_004 */ +/* DesignId : SCI_DesignId_004 */ +/* Requirements : CONQ_SCI_SR8 */ + +/** @fn uint32 sciIsTxReady(sciBASE_t *sci) + * @brief Check if Tx buffer empty + * @param[in] sci - sci module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 sciIsTxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_TX_INT; +} + +/* SourceId : SCI_SourceId_005 */ +/* DesignId : SCI_DesignId_005 */ +/* Requirements : CONQ_SCI_SR9 */ + +/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) + * @brief Send Byte + * @param[in] sci - sci module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use sciIsTxReady to check for Tx buffer empty + * before calling sciSendByte to avoid waiting. + */ +void sciSendByte( sciBASE_t * sci, uint8 byte ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + sci->TD = byte; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_006 */ +/* DesignId : SCI_DesignId_006 */ +/* Requirements : CONQ_SCI_SR10 */ + +/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, sciSend must not be called again until the + * transfer is complete, when the sciNotification callback will + * be called. In polling mode, sciSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +void sciSend( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + uint8 txdata; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + /*SAFETYMCUSW 139 S MR:13.7 "Mode variable is configured in + * sciEnableNotification()" */ + if( ( g_sciTransfer_t[ index ].mode & ( uint32 ) SCI_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + + g_sciTransfer_t[ index ].tx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].tx_data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + txdata = *g_sciTransfer_t[ index ].tx_data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[ index ].tx_data++; + sci->SETINT = ( uint32 ) SCI_TX_INT; + } + else + { + /* send the data */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in + * Transmit/Receive polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + txdata = *data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_007 */ +/* DesignId : SCI_DesignId_007 */ +/* Requirements : CONQ_SCI_SR11 */ + +/** @fn uint32 sciIsRxReady(sciBASE_t *sci) + * @brief Check if Rx buffer full + * @param[in] sci - sci module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 sciIsRxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_RX_INT; +} + +/* SourceId : SCI_SourceId_008 */ +/* DesignId : SCI_DesignId_008 */ +/* Requirements : CONQ_SCI_SR12 */ + +/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) + * @brief Check if Idle Period is Detected + * @param[in] sci - sci module base address + * + * @return The Idle flag + * + * Checks to see if the SCI Idle flag is set, returns 0 is flags + * not set otherwise will return the Ilde flag itself. + */ +uint32 sciIsIdleDetected( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_IDLE; +} + +/* SourceId : SCI_SourceId_009 */ +/* DesignId : SCI_DesignId_009 */ +/* Requirements : CONQ_SCI_SR13 */ + +/** @fn uint32 sciRxError(sciBASE_t *sci) + * @brief Return Rx Error flags + * @param[in] sci - sci module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +uint32 sciRxError( sciBASE_t * sci ) +{ + uint32 status = ( sci->FLR + & ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ) ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT | ( uint32 ) SCI_PE_INT ); + return status; +} + +/* SourceId : SCI_SourceId_010 */ +/* DesignId : SCI_DesignId_010 */ +/* Requirements : CONQ_SCI_SR14 */ + +/** @fn uint32 sciReceiveByte(sciBASE_t *sci) + * @brief Receive Byte + * @param[in] sci - sci module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use sciIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +uint32 sciReceiveByte( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + return ( sci->RD & ( uint32 ) 0x000000FFU ); +} + +/* SourceId : SCI_SourceId_011 */ +/* DesignId : SCI_DesignId_011 */ +/* Requirements : CONQ_SCI_SR15 */ + +/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer to receive data + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, sciReceive must not be called + * again until the transfer is complete, when the sciNotification + * callback will be called. In polling mode, sciReceive will not + * return until the transfer is complete. + */ +void sciReceive( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( sci->SETINT & ( uint32 ) SCI_RX_INT ) == ( uint32 ) SCI_RX_INT ) + { + /* we are in interrupt mode */ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* clear error flags */ + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ); + + g_sciTransfer_t[ index ].rx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].rx_data = data; + } + else + { + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( uint8 ) ( sci->RD & 0x000000FFU ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_012 */ +/* DesignId : SCI_DesignId_014 */ +/* Requirements : CONQ_SCI_SR18 */ + +/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void sciEnableLoopback( sciBASE_t * sci, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + sci->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + sci->IODFTCTRL = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_013 */ +/* DesignId : SCI_DesignId_015 */ +/* Requirements : CONQ_SCI_SR19 */ + +/** @fn void sciDisableLoopback(sciBASE_t *sci) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * + * This function disable the Loopback mode. + */ +void sciDisableLoopback( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + sci->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_014 */ +/* DesignId : SCI_DesignId_012 */ +/* Requirements : CONQ_SCI_SR16 */ + +/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) + * @brief Enable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +void sciEnableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode |= ( flags & ( uint32 ) SCI_TX_INT ); + sci->SETINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_015 */ +/* DesignId : SCI_DesignId_013 */ +/* Requirements : CONQ_SCI_SR17 */ + +/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) + * @brief Disable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +void sciDisableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode &= ( uint32 ) ( ~( flags & ( uint32 ) SCI_TX_INT ) ); + sci->CLEARINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_016 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : */ + +/** @fn sciEnterResetState(sciBASE_t *sci) + * @brief Enter reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +void sciEnterResetState( sciBASE_t * sci ) +{ + sci->GCR1 &= 0xFFFFFF7FU; +} + +/* SourceId : SCI_SourceId_017 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : */ + +/** @fn scixitResetState(sciBASE_t *sci) + * @brief Exit reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +void sciExitResetState( sciBASE_t * sci ) +{ + sci->GCR1 |= 0x00000080U; +} + +/* SourceId : SCI_SourceId_020 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : CONQ_SCI_SR25 */ + +/** @fn void sci3GetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void sci3GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI3_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI3_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI3_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI3_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI3_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI3_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI3_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI3_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI3_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI3_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = sciREG3->GCR0; + config_reg->CONFIG_GCR1 = sciREG3->GCR1; + config_reg->CONFIG_SETINT = sciREG3->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG3->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG3->FORMAT; + config_reg->CONFIG_BRS = sciREG3->BRS; + config_reg->CONFIG_PIO0 = sciREG3->PIO0; + config_reg->CONFIG_PIO1 = sciREG3->PIO1; + config_reg->CONFIG_PIO6 = sciREG3->PIO6; + config_reg->CONFIG_PIO7 = sciREG3->PIO7; + config_reg->CONFIG_PIO8 = sciREG3->PIO8; + } +} + +/* SourceId : SCI_SourceId_021 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : CONQ_SCI_SR26 */ + +/** @fn void sci4GetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI4 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void sci4GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI4_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI4_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI4_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI4_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI4_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI4_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI4_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI4_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI4_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI4_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = sciREG4->GCR0; + config_reg->CONFIG_GCR1 = sciREG4->GCR1; + config_reg->CONFIG_SETINT = sciREG4->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG4->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG4->FORMAT; + config_reg->CONFIG_BRS = sciREG4->BRS; + config_reg->CONFIG_PIO0 = sciREG4->PIO0; + config_reg->CONFIG_PIO1 = sciREG4->PIO1; + config_reg->CONFIG_PIO6 = sciREG4->PIO6; + config_reg->CONFIG_PIO7 = sciREG4->PIO7; + config_reg->CONFIG_PIO8 = sciREG4->PIO8; + } +} + +void sci_print( char * str ) +{ + sciDisplayText( scilinREG, str, strlen( str ) ); +} + +void sciDisplayText( sciBASE_t * sci, char * text, uint32_t length ) +{ + while( length-- ) + { + /* Wait until we hit an idle state */ + while( ( sci->FLR & ( uint32_t ) SCI_IDLE ) == 4U ) + { + /* Wait */ + } + + /* Send out text */ + sciSendByte( sci, *text++ ); + } +} + +void sciDisplayData( sciBASE_t * sci, uint8_t * text, uint32_t length ) +{ + uint8_t txt = 0; + uint8_t txt1 = 0; + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + text = text + ( length - 1 ); +#endif + + while( length-- ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + txt = *text--; +#else + txt = *text++; +#endif + + txt1 = txt; + + txt &= ~( 0xF0 ); + txt1 &= ~( 0x0F ); + txt1 = txt1 >> 4; + + if( txt <= 0x9 ) + { + txt += 0x30; + } + else if( ( txt > 0x9 ) && ( txt < 0xF ) ) + { + txt += 0x37; + } + else + { + txt = 0x30; + } + + if( txt1 <= 0x9 ) + { + txt1 += 0x30; + } + else if( ( txt1 > 0x9 ) && ( txt1 <= 0xF ) ) + { + txt1 += 0x37; + } + else + { + txt1 = 0x30; + } + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt1 ); /* send out text */ + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt ); /* send out text */ + } +} + +/* USER CODE BEGIN (45) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S new file mode 100644 index 00000000000..af42adc0a01 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S @@ -0,0 +1,574 @@ +/*------------------------------------------------------------------------------- + sys_core.asm + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +-------------------------------------------------------------------------*/ + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize CPU Registers + + .weak _coreInitRegisters_ + .type _coreInitRegisters_, %function + +_coreInitRegisters_: + + @ After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, lr + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to FIQ mode (M = 10001) + cps #17 + mov lr, r0 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to IRQ mode (M = 10010) + cps #18 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Abort mode (M = 10111) + cps #23 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Undefined Instruction Mode (M = 11011) + cps #27 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to System Mode ( Shares User Mode registers ) (M = 11111) + cps #31 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + mov r2, #0x40000000 + fmxr fpexc, r2 + + fmdrr d0, r1, r1 + fmdrr d1, r1, r1 + fmdrr d2, r1, r1 + fmdrr d3, r1, r1 + fmdrr d4, r1, r1 + fmdrr d5, r1, r1 + fmdrr d6, r1, r1 + fmdrr d7, r1, r1 + fmdrr d8, r1, r1 + fmdrr d9, r1, r1 + fmdrr d10, r1, r1 + fmdrr d11, r1, r1 + fmdrr d12, r1, r1 + fmdrr d13, r1, r1 + fmdrr d14, r1, r1 + fmdrr d15, r1, r1 + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + bx r0 + +/*-------------------------------------------------------------------------------*/ +@ Initialize Stack Pointers + + .weak _coreInitStackPointer_ + .type _coreInitStackPointer_, %function + +_coreInitStackPointer_: + + cps #17 + ldr sp, fiqSp + cps #18 + ldr sp, irqSp + cps #19 + ldr sp, svcSp + cps #23 + ldr sp, abortSp + cps #27 + ldr sp, undefSp + cps #31 + ldr sp, userSp + bx lr + + +undefSp: .word 0x08000000+0x00000200 +svcSp: .word 0x08000000+0x00000800 +fiqSp: .word 0x08000000+0x00000A00 +abortSp: .word 0x08000000+0x00000C00 +irqSp: .word 0x08000000+0x00001000 +userSp: .word 0x08000000+0x00001000 + +/*-------------------------------------------------------------------------------*/ +@ Get CPSR Value + + .weak _getCPSRValue_ + .type _getCPSRValue_, %function + +_getCPSRValue_: + + mrs r0, CPSR + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Take CPU to IDLE state + + .weak _gotoCPUIdle_ + .type _gotoCPUIdle_, %function + +_gotoCPUIdle_: + + WFI + nop + nop + nop + nop + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable VFP Unit + + .weak _coreEnableVfp_ + .type _coreEnableVfp_, %function + +_coreEnableVfp_: + + mrc p15, #0x00, r0, c1, c0, #0x02 + orr r0, r0, #0xF00000 + mcr p15, #0x00, r0, c1, c0, #0x02 + mov r0, #0x40000000 + fmxr fpexc, r0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Event Bus Export + + .weak _coreEnableEventBusExport_ + .type _coreEnableEventBusExport_, %function + +_coreEnableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + orr r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Event Bus Export + + .weak _coreDisableEventBusExport_ + .type _coreDisableEventBusExport_, %function + +_coreDisableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + bic r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Offset via Vic controller + + .weak _coreEnableIrqVicOffset_ + .type _coreEnableIrqVicOffset_, %function + +_coreEnableIrqVicOffset_: + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x01000000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault status register + + .weak _coreGetDataFault_ + .type _coreGetDataFault_, %function + +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault status register + + .weak _coreClearDataFault_ + .type _coreClearDataFault_, %function + +_coreClearDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault status register + + .weak _coreGetInstructionFault_ + .type _coreGetInstructionFault_, %function + +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault status register + + .weak _coreClearInstructionFault_ + .type _coreClearInstructionFault_, %function + +_coreClearInstructionFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault address register + + .weak _coreGetDataFaultAddress_ + .type _coreGetDataFaultAddress_, %function + +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault address register + + .weak _coreClearDataFaultAddress_ + .type _coreClearDataFaultAddress_, %function + +_coreClearDataFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault address register + + .weak _coreGetInstructionFaultAddress_ + .type _coreGetInstructionFaultAddress_, %function + +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault address register + + .weak _coreClearInstructionFaultAddress_ + .type _coreClearInstructionFaultAddress_, %function + +_coreClearInstructionFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary data fault status register + + .weak _coreGetAuxiliaryDataFault_ + .type _coreGetAuxiliaryDataFault_, %function + +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary data fault status register + + .weak _coreClearAuxiliaryDataFault_ + .type _coreClearAuxiliaryDataFault_, %function + +_coreClearAuxiliaryDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary instruction fault status register + + .weak _coreGetAuxiliaryInstructionFault_ + .type _coreGetAuxiliaryInstructionFault_, %function + +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary instruction fault status register + + .weak _coreClearAuxiliaryInstructionFault_ + .type _coreClearAuxiliaryInstructionFault_, %function + +_coreClearAuxiliaryInstructionFault_: + + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable IRQ interrupt + + .weak _disable_IRQ_interrupt_ + .type _disable_IRQ_interrupt_, %function + +_disable_IRQ_interrupt_: + + cpsid i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - CPU IRQ + + .weak _enable_IRQ_interrupt_ + .type _enable_IRQ_interrupt_, %function + +_enable_IRQ_interrupt_: + + cpsie i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - CPU IRQ & FIQ + + .weak _enable_interrupt_ + .type _enable_interrupt_, %function + +_enable_interrupt_: + + cpsie if + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear ESM CCM errorss + + .weak _esmCcmErrorsClear_ + .type _esmCcmErrorsClear_, %function + +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + +/*-------------------------------------------------------------------------------*/ +@Initialize RAM memory + + .weak _memInit_ + .type _memInit_, %function + +_memInit_: + ldr r12, MINITGCR @Load MINITGCR register address + mov r4, #0xA + str r4, [r12] @Enable global memory hardware initialization + + ldr r11, MSIENA @Load MSIENA register address + mov r4, #0x1 @Bit position 0 of MSIENA corresponds to SRAM + str r4, [r11] @Enable auto hardware initalisation for SRAM +mloop: @Loop till memory hardware initialization comletes + ldr r5, MSTCGSTAT + ldr r4, [r5] + tst r4, #0x100 + beq mloop + + mov r4, #5 + str r4, [r12] @Disable global memory hardware initialization + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Check Initialize RAM memory + + .weak _checkMemInitOn_ + .type _checkMemInitOn_, %function + +_checkMemInitOn_: + ldr r12, MINITGCR @Load MINITGCR register address +mloop5: ldr r4, [r12] + teq r4, #0xA + beq mloop5 + bx lr + + +MINITGCR: .word 0xFFFFFF5C +MSIENA: .word 0xFFFFFF60 +MSTCGSTAT: .word 0xFFFFFF68 + +/*-------------------------------------------------------------------------------*/ +@ Enable caches + + .weak _cacheEnable_ + .type _cacheEnable_, %function + +_cacheEnable_: + + stmfd sp!, {r0-r1} + mov r0,#0 + + MRC p15, #0, r1, c1, c0, #1 @ Read auxiliary control register + BIC r1, r1, #0x1 << 5 @ bit is default set to disable ECC. Clearing bit 5 + MCR p15, #0, r1, c1, c0, #1 @ enable ECC, generate abort on ECC errors, enable + @ hardware recovery + + MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data + ORR R1, R1, #0x1 <<12 @ instruction cache enable + ORR R1, R1, #0x1 <<2 @ data cache enable + DSB + MCR p15, #0, r0, c15, c5, #0 @ Invalidate entire data cache + DSB @ delay is required, manually added + MCR p15, #0, r0, c7, c5, #0 @ Invalidate entire instruction cache + DSB @ delay is required, manually added + MCR p15, #0, R1, c1, c0, #0 @ enabled cache RAMs + ISB + + ldmfd sp!, {r0-r1} + + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable caches + + .weak _cacheDisable_ + .type _cacheDisable_, %function + +_cacheDisable_: + + stmfd sp!, {r1} + + MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data + BIC R1, R1, #0x1 <<12 @ instruction cache disable + BIC R1, R1, #0x1 <<2 @ data cache disable + DSB + MCR p15, #0, R1, c1, c0, #0 @ disabled cache RAMs + ISB + + ldmfd sp!, {r1} + + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Invalidate Data Cache + + .weak _dCacheInvalidate_ + .type _dCacheInvalidate_, %function + +_dCacheInvalidate_: + MOV R0,#0 + DSB + MCR P15, #0, R0, C15, C5, #0 + DSB + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Invalidate Instruction Cache + + .weak _iCacheInvalidate_ + .type _iCacheInvalidate_, %function + +_iCacheInvalidate_: + MOV R0,#0 + DSB + MCR p15, #0, r0, c7, c5, #0 + DSB + bx lr +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c new file mode 100644 index 00000000000..bca5ac8d98b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c @@ -0,0 +1,654 @@ +/** @file sys_dma.c + * @brief DMA Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_dma.h" +#include "sys_vim.h" + +/** @fn void dmaEnable(void) + * @brief enables DMA module + * + * This function brings DMA out of reset + */ +/* SourceId : DMA_SourceId_001 */ +/* DesignId : DMA_DesignId_001 */ +/* Requirements : CONQ_DMA_SR1 */ +void dmaEnable( void ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + dmaREG->GCTRL = 0x00010000U; /* enable dma */ + dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */ + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void dmaDisable(void) + * @brief disables DMA module + * + * This function disables DMA module + */ +/* SourceId : DMA_SourceId_002 */ +/* DesignId : DMA_DesignId_002 */ +/* Requirements : CONQ_DMA_SR2 */ +void dmaDisable( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + while( ( dmaREG->GCTRL & 0x00004000U ) != 0U ) + { + } /* Wait */ + + /* Disable DMA module */ + dmaREG->GCTRL = 0U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void dmaSetCtrlPacket(uint32 channel) + * @brief Set control packet + * + * This function sets control packet + */ +/* SourceId : DMA_SourceId_003 */ +/* DesignId : DMA_DesignId_003 */ +/* Requirements : CONQ_DMA_SR4 */ +void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT ) +{ + uint8 i, j; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + dmaRAMREG->PCP[ channel ].ISADDR = g_dmaCTRLPKT.SADD; + + dmaRAMREG->PCP[ channel ].IDADDR = g_dmaCTRLPKT.DADD; + + dmaRAMREG->PCP[ channel ].ITCOUNT = ( g_dmaCTRLPKT.FRCNT << 16U ) + | g_dmaCTRLPKT.ELCNT; + + dmaRAMREG->PCP[ channel ].CHCTRL = ( g_dmaCTRLPKT.RDSIZE << 14U ) + | ( g_dmaCTRLPKT.WRSIZE << 12U ) + | ( g_dmaCTRLPKT.TTYPE << 8U ) + | ( g_dmaCTRLPKT.ADDMODERD << 3U ) + | ( g_dmaCTRLPKT.ADDMODEWR << 1U ) + | ( g_dmaCTRLPKT.AUTOINIT ); + + dmaRAMREG->PCP[ channel ].CHCTRL |= ( g_dmaCTRLPKT.CHCTRL << 16U ); + + dmaRAMREG->PCP[ channel ].EIOFF = ( g_dmaCTRLPKT.ELDOFFSET << 16U ) + | ( g_dmaCTRLPKT.ELSOFFSET ); + + dmaRAMREG->PCP[ channel ].FIOFF = ( g_dmaCTRLPKT.FRDOFFSET << 16U ) + | ( g_dmaCTRLPKT.FRSOFFSET ); + + i = channel / 8U; /* Find the register to write */ + j = channel % 8U; /* Find the offset */ + j = ( uint8 ) 7U - j; /* Reverse the order */ + j = j * 4U; /* Find the bit position */ + + dmaREG->PAR[ i ] &= ~( ( uint32 ) 0xFU << j ); + dmaREG->PAR[ i ] |= ( g_dmaCTRLPKT.PORTASGN << j ); + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void dmaSetChEnable(uint32 channel,uint32 type) + * @brief Enable channel + * @param[in] channel DMA channel + * @param[in] type Type of triggering + * - DMA_HW: Enables the selected DMA channel for hardware triggering + * - DMA_SW: Enables the selected DMA channel for software triggering + * + * This function enables the DMA channel for hardware or software triggering + */ +/* SourceId : DMA_SourceId_004 */ +/* DesignId : DMA_DesignId_004 */ +/* Requirements : CONQ_DMA_SR5 */ +void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + if( type == DMA_HW ) + { + dmaREG->HWCHENAS = ( uint32 ) 1U << channel; + } + else + { + dmaREG->SWCHENAS = ( uint32 ) 1U << channel; + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void dmaReqAssign(uint32 channel,uint32 reqline) + * @brief Assign DMA request lines to channels + * @param[in] channel DMA channel + * @param[in] reqline DMA request line + * + * This function assigns DMA request lines to channels + */ +/* SourceId : DMA_SourceId_005 */ +/* DesignId : DMA_DesignId_005 */ +/* Requirements : CONQ_DMA_SR3 */ +void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline ) +{ + uint8 i, j; + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + i = channel / 4U; /* Find the register to configure */ + j = channel % 4U; /* Find the offset */ + j = ( uint8 ) 3U - j; /* reverse the byte order */ + j = j * 8U; /* find the bit location */ + + /* Mapping channel 'i' to request line 'j' */ + dmaREG->DREQASI[ i ] &= ~( ( uint32 ) 0xFFU << j ); + dmaREG->DREQASI[ i ] |= ( ( uint32 ) reqline << j ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) + * @brief Assign Priority to the channel + * @param[in] channel DMA channel + * @param[in] priority Priority queue to which channel needs to be assigned + * - LOWPRIORITY : The selected channel will be assigned to low + * priority queue + * - HIGHPRIORITY: The selected channel will be assigned to high + * priority queue + * + * This function assigns the selected priority to the selected channel + */ +/* SourceId : DMA_SourceId_006 */ +/* DesignId : DMA_DesignId_006 */ +/* Requirements : CONQ_DMA_SR6 */ +void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( priority == LOWPRIORITY ) + { + dmaREG->CHPRIOR = ( uint32 ) 1U << channel; + } + else + { + dmaREG->CHPRIOS = ( uint32 ) 1U << channel; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableInterrupt(dmaChannel_t channel, dmaInterrupt_t inttype, + *dmaIntGroup_t group) + * @brief Enable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be enabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for + *the selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled + *for the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + *for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for + *the selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + *channel + * @param[in] group Group to which the interrupt is routed to. + * - DMA_INTA : Group A + * - DMA_INTB : Group B (Do not use this in case of Lock-step + *device) + * + * This function enables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_007 */ +/* DesignId : DMA_DesignId_007 */ +/* Requirements : CONQ_DMA_SR8 */ +void dmaEnableInterrupt( dmaChannel_t channel, + dmaInterrupt_t inttype, + dmaIntGroup_t group ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + dmaREG->GCHIENAS = ( uint32 ) 1U << channel; + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAS = ( uint32 ) 1U << channel; + dmaREG->FTCMAP = ( dmaREG->FTCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case LFS: + dmaREG->LFSINTENAS = ( uint32 ) 1U << channel; + dmaREG->LFSMAP = ( dmaREG->LFSMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case HBC: + dmaREG->HBCINTENAS = ( uint32 ) 1U << channel; + dmaREG->HBCMAP = ( dmaREG->HBCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case BTC: + dmaREG->BTCINTENAS = ( uint32 ) 1U << channel; + dmaREG->BTCMAP = ( dmaREG->BTCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + default: + break; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} +/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) + * @brief Disable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be disabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for the + * selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled for + * the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + * for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for the + * selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + * channel + * + * This function disables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_008 */ +/* DesignId : DMA_DesignId_008 */ +/* Requirements : CONQ_DMA_SR9 */ +void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAR = ( uint32 ) 1U << channel; + break; + case LFS: + dmaREG->LFSINTENAR = ( uint32 ) 1U << channel; + break; + case HBC: + dmaREG->HBCINTENAR = ( uint32 ) 1U << channel; + break; + case BTC: + dmaREG->BTCINTENAR = ( uint32 ) 1U << channel; + break; + default: + break; + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} +/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) + * @brief Configure start and end address of the region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * @param[in] start_add Start address of the the region + * @param[in] end_add End address of the region + * + * This function configure start and end address of the selected region + */ +/* SourceId : DMA_SourceId_009 */ +/* DesignId : DMA_DesignId_009 */ +/* Requirements : CONQ_DMA_SR10 */ +void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + if( region < 4U ) + { + dmaREG->DMAMPR_L[ region ].STARTADD = start_add; + dmaREG->DMAMPR_L[ region ].ENDADD = end_add; + } + else + { + dmaREG->DMAMPR_H[ region - 4U ].STARTADD = start_add; + dmaREG->DMAMPR_H[ region - 4U ].ENDADD = end_add; + } + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, dmaMPUInt_t + * intenable) + * @brief Enable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * @param[in] access Access permission of the selected region + * - FULLACCESS + * - READONLY + * - WRITEONLY + * - NOACCESS + * @param[in] intenable Interrupt to be enabled or not + * - INTERRUPTA_ENABLE : Enable Group A interrupt for the selected + * region + * - INTERRUPTB_ENABLE : Enable Group B interrupt for the selected + * region (Do not use this in case of Lock-step device) + * - INTERRUPT_DISABLE : Disable interrupt for the selected region + * + * This function enables the selected region with selected access permission with or + * without interrupt enable + */ +/* SourceId : DMA_SourceId_010 */ +/* DesignId : DMA_DesignId_010 */ +/* Requirements : CONQ_DMA_SR11 */ +void dmaEnableRegion( dmaMPURegion_t region, + dmaRegionAccess_t access, + dmaMPUInt_t intenable ) +{ + uint8 bitpos = 0U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( region < 4U ) + { + bitpos = region * 8U; + dmaREG->DMAMPCTRL1 &= ~( uint32 ) ( ( uint32 ) 0xFFU << bitpos ); + + dmaREG->DMAMPCTRL1 |= ( ( uint32 ) 1U << bitpos ) /* Enable the region */ + | ( ( uint32 ) access << ( bitpos + 1U ) ) /* Set access + permission for + the region */ + | ( ( uint32 ) intenable + << ( bitpos + 3U ) ); /* Enable or Disable interrupt + */ + } + else + { + bitpos = ( region - 4U ) * 8U; + dmaREG->DMAMPCTRL2 &= ~( ( uint32 ) 0xFFU << bitpos ); + + dmaREG->DMAMPCTRL2 |= ( ( uint32 ) 1U << bitpos ) /* Enable the region */ + | ( ( uint32 ) access << ( bitpos + 1U ) ) /* Set access + permission for + the region */ + | ( ( uint32 ) intenable + << ( bitpos + 3U ) ); /* Enable or Disable interrupt + */ + } + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void dmaDisableRegion(dmaREGION_t region) + * @brief Disable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * + * This function disables the selected region(no address checking done). + */ +/* SourceId : DMA_SourceId_011 */ +/* DesignId : DMA_DesignId_011 */ +/* Requirements : CONQ_DMA_SR12 */ +void dmaDisableRegion( dmaMPURegion_t region ) +{ + uint8 bitpos = 0U; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + if( region < 4U ) + { + bitpos = region * 8U; + dmaREG->DMAMPCTRL1 &= ~( ( uint32 ) 1U << bitpos ); + } + else + { + bitpos = ( region - 4U ) * 8U; + dmaREG->DMAMPCTRL2 &= ~( ( uint32 ) 1U << bitpos ); + } + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableECC(void) + * @brief Enable ECC + * + * This function enables ECC check + */ +/* SourceId : DMA_SourceId_012 */ +/* DesignId : DMA_DesignId_012 */ +/* Requirements : CONQ_DMA_SR13 */ +void dmaEnableECC( void ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + dmaREG->DMAPCR = 0xAU; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void dmaDisableECC(void) + * @brief Disable ECC + * + * This function disables ECC check + */ +/* SourceId : DMA_SourceId_013 */ +/* DesignId : DMA_DesignId_013 */ +/* Requirements : CONQ_DMA_SR14 */ +void dmaDisableECC( void ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + dmaREG->DMAPCR = 0x5U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn uint32 dmaGetReq(uint32 channel) + * @brief Gets the request line number mapped to the selected channel + * @param[in] channel DMA channel + * + * This function returns the request line number mapped to the selected channel + */ +/* SourceId : DMA_SourceId_014 */ +/* DesignId : DMA_DesignId_014 */ +/* Requirements : CONQ_DMA_SR3 */ +uint32 dmaGetReq( dmaChannel_t channel ) +{ + uint8 i, j; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + i = channel / 4U; /* Find the register to configure */ + j = channel % 4U; /* Find the offset */ + j = ( uint8 ) 3U - j; /* reverse the byte order */ + j = j * 8U; /* find the bit location */ + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + return ( ( dmaREG->DREQASI[ i ] >> j ) & 0xFFU ); +} + +/** @fn boolean dmaIsChannelActive(dmaChannel_t channel) + * @brief Gets the status of the DMA channel + * @param[in] channel DMA channel + * + * This function returns TRUE if the channel is currently being processed using one of + * the FIFOs. + */ +/* SourceId : DMA_SourceId_015 */ +/* DesignId : DMA_DesignId_016 */ +/* Requirements : CONQ_DMA_SR21 */ +boolean dmaIsChannelActive( dmaChannel_t channel ) +{ + boolean status; + uint32 bitmask = ( uint32 ) 1U << channel; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + if( ( dmaREG->DMASTAT & bitmask ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + return status; +} + +/** @fn boolean dmaIsBusy(void) + * @brief Gets the status of the DMA bus + * + * This function returns TRUE if DMA's external bus is busy in data transfers + */ +/* SourceId : DMA_SourceId_016 */ +/* DesignId : DMA_DesignId_015 */ +/* Requirements : CONQ_DMA_SR20 */ +boolean dmaIsBusy( void ) +{ + boolean status; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + if( ( dmaREG->GCTRL & 0x4000U ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : DMA_SourceId_017 */ +/* DesignId : DMA_DesignId_017 */ +/* Requirements : CONQ_DMA_SR22 */ +boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype ) +{ + boolean status; + uint32 mask = ( uint32 ) 1U << channel; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + switch( inttype ) + { + case FTC: + status = ( ( dmaREG->FTCFLAG & mask ) != 0U ); + break; + case LFS: + status = ( ( dmaREG->LFSFLAG & mask ) != 0U ); + break; + case HBC: + status = ( ( dmaREG->HBCFLAG & mask ) != 0U ); + break; + case BTC: + status = ( ( dmaREG->BTCFLAG & mask ) != 0U ); + break; + default: + status = FALSE; + break; + } + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S new file mode 100644 index 00000000000..881537438ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S @@ -0,0 +1,75 @@ +/*--------------------------------------------------------------------------- + sys_intvecs.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +----------------------------------------------------------------------------*/ + + .syntax unified + .cpu cortex-r5 + .arm + + .section .intvecs,"a",%progbits + .type resetEntry, %object + .size resetEntry, .-resetEntry + +/*-------------------------------------------------------------------------------*/ +@ import reference for interrupt routines + + .extern _c_int00 + .extern FreeRTOS_SVC_Handler + .extern _dabort + .extern phantomInterrupt + .weak resetEntry + +/*-------------------------------------------------------------------------------*/ +@ interrupt vectors + +resetEntry: + b _c_int00 +undefEntry: + b undefEntry +svcEntry: + b FreeRTOS_SVC_Handler +prefetchEntry: + b prefetchEntry +dataAbortEntry: + b _dabort + b phantomInterrupt + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * IRQVECREG: 0x18 - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * FIQVECREG: 0x1C - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld new file mode 100644 index 00000000000..958b5541d33 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld @@ -0,0 +1,186 @@ +/*----------------------------------------------------------------------------*/ +/* sys_link.ld */ +/* */ +/* (c) Texas Instruments 2009-2014, All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Entry Point */ +ENTRY(_c_int00) + +/* Highest address of the stack */ +_estack = 0x8080000; /* end of 512K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 4M + RAM (xrw) : ORIGIN = 0x08000000, LENGTH = 512K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/** Common sizes + * 0x0000 0001 == 1B + * 0x0000 0002 == 2B + * 0x0000 0004 == 4B + * 0x0000 0008 == 8B + * 0x0000 0010 == 16B + * 0x0000 0020 == 32B + * 0x0000 0040 == 64B + * 0x0000 0080 == 128B + * 0x0000 0100 == 256B + * 0x0000 0200 == 512B + * 0x0000 0400 == 1K + * 0x0000 0800 == 2K + * 0x0000 1000 == 4K + * 0x0000 2000 == 8K + * 0x0000 4000 == 16K + * 0x0000 8000 == 32K + * 0x0001 0000 == 64K + * 0x0002 0000 == 128K + * 0x0003 0000 == 192K + * 0x0004 0000 == 256K + * 0x0008 0000 == 512K + * 0x0010 0000 == 1024K/1MB + * 0x0014 0000 == 1280KB/1.25 MB + * 0x0020 0000 == 2048K/2MB + * 0x0040 0000 == 4096K/4MB + * 0x0080 0000 == 8192K/8MB + * 0x0100 0000 == 16MB + * 0x0200 0000 == 32MB + * 0x0400 0000 == 64MB + * 0x0800 0000 == 128MB +*/ + +/* The first 2K of space in RAM is used for different processor mode stacks */ +__interrupt_stack_region_size = 0x1000; + +/* Define output sections */ +SECTIONS +{ + /* The ISR vector goes first into RAM */ + .intvecs : + { + . = ALIGN(4); + KEEP(*(.intvecs)) + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into RAM */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by sys_startup.c to initialize data */ + _sidata = LOADADDR(.data); + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + . = __interrupt_stack_region_size; + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c new file mode 100644 index 00000000000..2a4ece6cb9c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c @@ -0,0 +1,1081 @@ +/** @file sys_pcr.c + * @brief PCR Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the PCR driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pcr.h" + +/** @fn void peripheral_Memory_Protection_Set(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Set Peripheral Memory Protection + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function enables peripheral memory protection (write in privileged mode only) + * for the selected frame + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_001 */ +/* DesignId : PCR_DesignId_001 */ +/* Requirements : CONQ_PCR_SR1 */ +void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PMPROTSET0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PMPROTSET1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_Protection_Clr(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Clear Peripheral Memory Protection + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function disables peripheral memory protection (write in privileged mode only) + * for the selected frame + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_002 */ +/* DesignId : PCR_DesignId_002 */ +/* Requirements : CONQ_PCR_SR2 */ +void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PMPROTCLR0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PMPROTCLR1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_Protection_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Protection + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function enables peripheral frame protection (write in privileged mode only) for + *the selected frame + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_003 */ +/* DesignId : PCR_DesignId_003 */ +/* Requirements : CONQ_PCR_SR3 */ +void peripheral_Frame_Protection_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PPROTSET0 = quadrant << PS * 4U; + } + else if( PS < 16U ) + { + pcr->PPROTSET1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PPROTSET2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PPROTSET3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_Protection_Clr(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Clear Peripheral Frame Protection + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function disables peripheral frame protection (write in privileged mode only) + *for the selected frame + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_004 */ +/* DesignId : PCR_DesignId_004 */ +/* Requirements : CONQ_PCR_SR4 */ +void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PPROTCLR0 = quadrant << PS * 4U; + } + else if( PS < 16U ) + { + pcr->PPROTCLR1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PPROTCLR2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PPROTCLR3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_PowerDown_Set(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Set Peripheral Memory Power Down + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function disables the clocks to the selected peripheral memory + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_005 */ +/* DesignId : PCR_DesignId_005 */ +/* Requirements : CONQ_PCR_SR5 */ +void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PCSPWRDWNSET0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PCSPWRDWNSET1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_PowerDown_Clr(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Clear Peripheral Memory Power Down + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function enables the clocks to the selected peripheral memory + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_006 */ +/* DesignId : PCR_DesignId_006 */ +/* Requirements : CONQ_PCR_SR6 */ +void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PCSPWRDWNCLR0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PCSPWRDWNCLR1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_PowerDown_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Power Down + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function disables the clocks to the selected quadrant(s) + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_007 */ +/* DesignId : PCR_DesignId_007 */ +/* Requirements : CONQ_PCR_SR7 */ +void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PSPWRDWNSET0 = quadrant << ( PS * 4U ); + } + else if( PS < 16U ) + { + pcr->PSPWRDWNSET1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PSPWRDWNSET2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PSPWRDWNSET3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_PowerDown_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Power Down + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function enables the clocks to the selected quadrant(s) + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_008*/ +/* DesignId : PCR_DesignId_008 */ +/* Requirements : CONQ_PCR_SR8 */ +void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PSPWRDWNCLR0 = quadrant << ( PS * 4U ); + } + else if( PS < 16U ) + { + pcr->PSPWRDWNCLR1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PSPWRDWNCLR2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PSPWRDWNCLR3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, peripheral_Frame_t PS, + *uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_009 */ +/* DesignId : PCR_DesignId_010 */ +/* Requirements : CONQ_PCR_SR14 */ +void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, peripheral_Frame_t + *PS, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_010 */ +/* DesignId : PCR_DesignId_009 */ +/* Requirements : CONQ_PCR_SR13 */ +void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Frame_t PPS, uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPS Privileged Peripheral chip select (PPS0..PPS7) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_011 */ +/* DesignId : PCR_DesignId_012 */ +/* Requirements : CONQ_PCR_SR16 */ +void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Frame_t PPS, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPS Privileged Peripheral chip select (PPS0..PPS7) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_012 */ +/* DesignId : PCR_DesignId_011 */ +/* Requirements : CONQ_PCR_SR15 */ +void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Extended_Frame_t PPSE, uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPSE Privileged Peripheral Extended chip select (PPSE0..PPSE31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSEx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_013 */ +/* DesignId : PCR_DesignId_014 */ +/* Requirements : CONQ_PCR_SR18 */ +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Extended_Frame_t PPSE, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPSE Privileged Peripheral Extended chip select (PPSE0..PPSE31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSEx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_014 */ +/* DesignId : PCR_DesignId_013 */ +/* Requirements : CONQ_PCR_SR17 */ +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_MasterIDFilter_Enable(pcrBASE_t *pcr, peripheral_Memory_t + *PCS, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_015 */ +/* DesignId : PCR_DesignId_016 */ +/* Requirements : CONQ_PCR_SR20 */ +void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PCS / 2U; + j = PCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PCSxMSTID[ i ] |= ( uint32 ) 1U << ( master + j ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_MasterIDFilter_Disable(pcrBASE_t *pcr, peripheral_Memory_t + *PCS, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_016 */ +/* DesignId : PCR_DesignId_015 */ +/* Requirements : CONQ_PCR_SR19 */ +void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PCS / 2U; + j = PCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PCSxMSTID[ i ] &= ~( ( uint32 ) 1U << ( master + j ) ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Memory_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Memory_t PPCS, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PPCS Privileged Peripheral memory chip select (PPCS0..PPCS15) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_017 */ +/* DesignId : PCR_DesignId_018 */ +/* Requirements : CONQ_PCR_SR22 */ +void privileged_Peripheral_Memory_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PPCS / 2U; + j = PPCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PPCSxMSTID[ i ] |= ( uint32 ) 1U << ( master + j ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Memory_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Memory_t PPCS, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PPCS Privileged Peripheral memory chip select (PPCS0..PPCS15) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_018 */ +/* DesignId : PCR_DesignId_017 */ +/* Requirements : CONQ_PCR_SR21 */ +void privileged_Peripheral_Memory_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PPCS / 2U; /* Find the index of the register to be written */ + j = PPCS % 2U; /* Find the bit position */ + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PPCSxMSTID[ i ] &= ~( ( uint32 ) 1U << ( master + j ) ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void pcrEnableMasterIDCheck(pcrBASE_t *pcr) + * @brief Enable Master-ID check + * + * @param[in] pcr PCR segment (pcrREG1..pcrREG3) + * + * This function enables master-id check for the selected PCR. + */ +/* SourceId : PCR_SourceId_019 */ +/* DesignId : PCR_DesignId_019 */ +/* Requirements : CONQ_PCR_SR11 */ +void pcrEnableMasterIDCheck( pcrBASE_t * pcr ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + pcr->MSTIDENA = 0xAU; + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn void pcrDisableMasterIDCheck(pcrBASE_t *pcr) + * @brief Disable Master-ID check + * + * @param[in] pcr PCR segment (pcrREG1..pcrREG3) + * + * This function disables master-id check for the selected PCR. + */ +/* SourceId : PCR_SourceId_020 */ +/* DesignId : PCR_DesignId_020*/ +/* Requirements : CONQ_PCR_SR12 */ +void pcrDisableMasterIDCheck( pcrBASE_t * pcr ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + pcr->MSTIDENA = 0x5U; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c new file mode 100644 index 00000000000..ab428fddc7f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c @@ -0,0 +1,77 @@ +/** @file sys_phantom.c + * @brief Phantom Interrupt Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Phantom Interrupt Handler + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_common.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Phantom Interrupt Handler */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +void phantomInterrupt( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/** @fn void custom_dabort(void) + * @brief Custom Data abort routine for the application. + * + * Custom Data abort routine for the application. + */ +void custom_dabort( void ) +{ + /* Need custom data abort handler here. + * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC + * logic. + */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c new file mode 100644 index 00000000000..a6339001706 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c @@ -0,0 +1,229 @@ +/** @file sys_pmm.c + * @brief PCR Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pmm.h" + +#define PMM_LODICPWRSTAT 0x3U +#define PMM_DOMAINON 0x100U +#define PMM_AUTOCLKWAKEENA 0x1U + +/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns on Logic Power Domain + * @param[in] logicPD - Power Domain to be turned on + * - PMM_LOGICPD2: Power domain PD2 will be turned on + * - PMM_LOGICPD3: Power domain PD3 will be turned on + * - PMM_LOGICPD4: Power domain PD4 will be turned on + * - PMM_LOGICPD5: Power domain PD5 will be turned on + * - PMM_LOGICPD6: Power domain PD6 will be turned on + * + * This function turns on the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_001 */ +/* DesignId : PMM_DesignId_001 */ +/* Requirements : CONQ_PMM_SR3 */ +boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + boolean status = TRUE; + + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + /* Power On the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x05000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x00050000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000500U; + } + else if( logicPD == PMM_LOGICPD5 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) | 0x00000005U; + } + else if( logicPD == PMM_LOGICPD6 ) + { + pmmREG->LOGICPDPWRCTRL1 = 0x05000000U; + } + else + { + /* Invalid input */ + status = FALSE; + } + + if( status == TRUE ) + { + if( ( pmmREG->GLOBALCTRL1 & PMM_AUTOCLKWAKEENA ) == 0U ) + { + /* Enable clocks to the power domain */ + pmmREG->PDCLKDISCLR = ( uint32 ) 1U << logicPD; + } + + /* Wait until the domain is powered on */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_DOMAINON ) == 0U ) + { + /* Add timeout code here */ + } + } + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + return status; +} + +/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns off Logic Power Domain + * @param[in] logicPD - Power Domain to be tured off + * - PMM_LOGICPD2: Power domain PD2 will be turned off + * - PMM_LOGICPD3: Power domain PD3 will be turned off + * - PMM_LOGICPD4: Power domain PD4 will be turned off + * - PMM_LOGICPD5: Power doamin PD5 will be turned off + * - PMM_LOGICPD6: Power doamin PD5 will be turned off + * + * This function turns off the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_002 */ +/* DesignId : PMM_DesignId_002 */ +/* Requirements : CONQ_PMM_SR4 */ +boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + boolean status = TRUE; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* Disable clocks to the power domain */ + pmmREG->PDCLKDISSET = ( uint32 ) 1U << logicPD; + + /* Power Down the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x0A000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x000A0000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000A00U; + } + else if( logicPD == PMM_LOGICPD5 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) | 0x0000000AU; + } + else if( logicPD == PMM_LOGICPD6 ) + { + pmmREG->LOGICPDPWRCTRL1 = 0x0A000000U; + } + else + { + /* Invalid input */ + status = FALSE; + } + + if( status == TRUE ) + { + /* Wait until the domain is powered down */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LODICPWRSTAT ) != 0U ) + { + /* Add timeout code here */ + } + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + return status; +} + +/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) + * @brief Check if the power domain is active or not + * @param[in] logicPD - Power Domain to be be checked + * - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not + * - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not + * - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not + * - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not + * - PMM_LOGICPD6: Checks whether Power domain PD6 is active or not + * @return The function will return: + * - TRUE : When the selected power domain is in Active state. + * - FALSE: When the selected power domain is in OFF state. + * + * This function checks whether the selected power domain is active or not. + * + */ +/* SourceId : PMM_SourceId_003 */ +/* DesignId : PMM_DesignId_003 */ +/* Requirements : CONQ_PMM_SR5 */ +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ) +{ + boolean status; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + if( logicPD == PMM_LOGICPD1 ) + { + status = TRUE; + } + else + { + if( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LODICPWRSTAT ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S new file mode 100644 index 00000000000..cf54214b1ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S @@ -0,0 +1,215 @@ +/*------------------------------------------------------------------------------ + sys_pmu.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +---------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize Pmu +@ Note: It will reset all counters + + .weak _pmuInit_ + .type _pmuInit_, %function + +_pmuInit_: + + @ set control register + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #(1 << 4) + 6 + 1 + mcr p15, #0, r0, c9, c12, #0 + @ clear flags + mov r0, #0 + sub r0, r0, #1 + mcr p15, #0, r0, c9, c12, #3 + @ select counter 0 event + mov r0, #0 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 1 event + mov r0, #1 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 2 event + mov r0, #2 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Counters Global [Cycle, Event [0..2]] +@ Note: It will reset all counters + + .weak _pmuEnableCountersGlobal_ + .type _pmuEnableCountersGlobal_, %function + +_pmuEnableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #7 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Counters Global [Cycle, Event [0..2]] + + .weak _pmuDisableCountersGlobal_ + .type _pmuDisableCountersGlobal_, %function + +_pmuDisableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter + + .weak _pmuResetCycleCounter_ + .type _pmuResetCycleCounter_, %function + +_pmuResetCycleCounter_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #4 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Event Counters [0..2] + + .weak _pmuResetEventCounters_ + .type _pmuResetEventCounters_, %function + +_pmuResetEventCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #2 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter abd Event Counters [0..2] + + .weak _pmuResetCounters_ + .type _pmuResetCounters_, %function + +_pmuResetCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #6 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Start Counters [Cycle, 0..2] + + .weak _pmuStartCounters_ + .type _pmuStartCounters_, %function + +_pmuStartCounters_: + + mcr p15, #0, r0, c9, c12, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Stop Counters [Cycle, 0..2] + + .weak _pmuStopCounters_ + .type _pmuStopCounters_, %function + +_pmuStopCounters_: + + mcr p15, #0, r0, c9, c12, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Set Count event + + .weak _pmuSetCountEvent_ + .type _pmuSetCountEvent_, %function + +_pmuSetCountEvent_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mcr p15, #0, r1, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Cycle Count + + .weak _pmuGetCycleCount_ + .type _pmuGetCycleCount_, %function + +_pmuGetCycleCount_: + + mrc p15, #0, r0, c9, c13, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Event Counter Count Value + + .weak _pmuGetEventCount_ + .type _pmuGetEventCount_, %function + +_pmuGetEventCount_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mrc p15, #0, r0, c9, c13, #2 @ read event counter + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Overflow Flags + + .weak _pmuGetOverflow_ + .type _pmuGetOverflow_, %function + +_pmuGetOverflow_: + + mrc p15, #0, r0, c9, c12, #3 @ read overflow + mov r1, #0 + sub r1, r1, #1 + mcr p15, #0, r1, c9, c12, #3 @ clear flags + bx lr + +/*-------------------------------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c new file mode 100644 index 00000000000..e62403f53fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c @@ -0,0 +1,290 @@ +/** @file sys_startup.c + * @brief Startup Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Include Files + * - Type Definitions + * - External Functions + * - VIM RAM Setup + * - Startup Routine + * . + * which are relevant for the Startup. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "sys_common.h" +#include "system.h" +#include "sys_vim.h" +#include "sys_core.h" +#include "esm.h" +#include "sys_mpu.h" +#include "errata_SSWF021_45.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* External Functions */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(main should be declared by the user)" + */ +extern void main( void ); +/*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be present)" + */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(Extern declaration present in the + * library)" */ +extern void exit( int _status ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +void handlePLLLockFail( void ); +/* Startup Routine */ +void _c_int00( void ) __attribute__( ( noreturn ) ); +#define PLL_RETRIES 5U +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +__attribute__( ( naked ) ) + +/* SourceId : STARTUP_SourceId_001 */ +/* DesignId : STARTUP_DesignId_001 */ +/* Requirements : CONQ_STARTUP_SR1 */ +void _c_int00( void ) +{ + register resetSource_t rstSrc; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /* Initialize Core Registers to avoid CCM Error */ + _coreInitRegisters_(); + + /* Initialize Stack Pointers */ + _coreInitStackPointer_(); + + /* Reset handler: the following instructions read from the system exception status + * register to identify the cause of the CPU reset. + */ + rstSrc = getResetSource(); + + switch( rstSrc ) + { + case POWERON_RESET: + /* Initialize L2RAM to avoid ECC errors right after power on */ + _memInit_(); + + /* Add condition to check whether PLL can be started successfully */ + if( _errata_SSWF021_45_both_plls( PLL_RETRIES ) != 0U ) + { + /* Put system in a safe state */ + handlePLLLockFail(); + } + break; + + /*SAFETYMCUSW 62 S MR:15.2, 15.5 "Need to continue to handle + * POWERON Reset" */ + case DEBUG_RESET: + case EXT_RESET: + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /* Initialize L2RAM to avoid ECC errors right after power on */ + if( rstSrc != POWERON_RESET ) + { + _memInit_(); + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /* Check if there were ESM group3 errors during power-up. + * These could occur during eFuse auto-load or during reads from flash OTP + * during power-up. Device operation is not reliable and not recommended + * in this case. */ + if( ( esmREG->SR1[ 2 ] ) != 0U ) + { + esmGroup3Notification( esmREG, esmREG->SR1[ 2 ] ); + } + + /* Initialize System - Clock, Flash settings with Efuse self check */ + systemInit(); + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Enable IRQ offset via Vic controller */ + _coreEnableIrqVicOffset_(); + + /* Initialize VIM table */ + vimInit(); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + /* Configure system response to error conditions signaled to the ESM group1 */ + /* This function can be configured from the ESM tab of HALCoGen */ + esmInit(); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + break; + + case OSC_FAILURE_RESET: + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + break; + + case WATCHDOG_RESET: + case WATCHDOG2_RESET: + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + break; + + case CPU0_RESET: + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + break; + + case SW_RESET: + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + break; + + default: + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + break; + } + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + { + extern uint32 _sidata, _sdata, _edata; + uint32 *src, *dst; + + src = &_sidata; + dst = &_sdata; + + while( dst < &_edata ) + { + *dst++ = *src++; + } + + } + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* call the application */ + /*SAFETYMCUSW 296 S MR:8.6 "Startup code(library functions at block scope)" + */ + /*SAFETYMCUSW 326 S MR:8.2 "Startup code(Declaration for main in library)" + */ + /*SAFETYMCUSW 60 D MR:8.8 "Startup code(Declaration for main in + * library;Only doing an extern for the same)" */ + main(); + + /*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be + * present)" */ + exit( 0 ); + /* USER CODE BEGIN (77) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void handlePLLLockFail(void) + * @brief This function handles PLL lock fail. + */ +/* USER CODE BEGIN (30) */ +/* USER CODE END */ +void handlePLLLockFail( void ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + while( 1 ) + { + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (33) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c new file mode 100644 index 00000000000..fd3b1c86be6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c @@ -0,0 +1,855 @@ +/** @file sys_vim.c + * @brief VIM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_vim.h" +#include "system.h" +#include "esm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Vim Ram Definition */ +/** @struct vimRam + * @brief Vim Ram Definition + * + * This type is used to access the Vim Ram. + */ +/** @typedef vimRAM_t + * @brief Vim Ram Type Definition + * + * This type is used to access the Vim Ram. + */ +typedef volatile struct vimRam +{ + t_isrFuncPTR ISR[ VIM_CHANNELS ]; +} vimRAM_t; + +#define vimRAM ( ( vimRAM_t * ) 0xFFF82000U ) + +static const t_isrFuncPTR s_vim_init[ 128U ] = { + &phantomInterrupt, &esmHighInterrupt, /* Channel 0 */ + &phantomInterrupt, /* Channel 1 */ + &FreeRTOS_IRQ_Handler, /* Channel 2 */ + &phantomInterrupt, /* Channel 3 */ + &phantomInterrupt, /* Channel 4 */ + &phantomInterrupt, /* Channel 5 */ + &phantomInterrupt, /* Channel 6 */ + &phantomInterrupt, /* Channel 7 */ + &phantomInterrupt, /* Channel 8 */ + &phantomInterrupt, /* Channel 9 */ + &phantomInterrupt, /* Channel 10 */ + &phantomInterrupt, /* Channel 11 */ + &phantomInterrupt, /* Channel 12 */ + &phantomInterrupt, /* Channel 13 */ + &phantomInterrupt, /* Channel 14 */ + &phantomInterrupt, /* Channel 15 */ + &phantomInterrupt, /* Channel 16 */ + &phantomInterrupt, /* Channel 17 */ + &phantomInterrupt, /* Channel 18 */ + &phantomInterrupt, /* Channel 19 */ + &phantomInterrupt, /* Channel 20 */ + &FreeRTOS_IRQ_Handler, /* Channel 21 */ + &phantomInterrupt, /* Channel 22 */ + &phantomInterrupt, /* Channel 23 */ + &phantomInterrupt, /* Channel 24 */ + &phantomInterrupt, /* Channel 25 */ + &phantomInterrupt, /* Channel 26 */ + &phantomInterrupt, /* Channel 27 */ + &phantomInterrupt, /* Channel 28 */ + &phantomInterrupt, /* Channel 29 */ + &phantomInterrupt, /* Channel 30 */ + &phantomInterrupt, /* Channel 31 */ + &phantomInterrupt, /* Channel 32 */ + &phantomInterrupt, /* Channel 33 */ + &phantomInterrupt, /* Channel 34 */ + &phantomInterrupt, /* Channel 35 */ + &phantomInterrupt, /* Channel 36 */ + &phantomInterrupt, /* Channel 37 */ + &phantomInterrupt, /* Channel 38 */ + &phantomInterrupt, /* Channel 39 */ + &phantomInterrupt, /* Channel 40 */ + &phantomInterrupt, /* Channel 41 */ + &phantomInterrupt, /* Channel 42 */ + &phantomInterrupt, /* Channel 43 */ + &phantomInterrupt, /* Channel 44 */ + &phantomInterrupt, /* Channel 45 */ + &phantomInterrupt, /* Channel 46 */ + &phantomInterrupt, /* Channel 47 */ + &phantomInterrupt, /* Channel 48 */ + &phantomInterrupt, /* Channel 49 */ + &phantomInterrupt, /* Channel 50 */ + &phantomInterrupt, /* Channel 51 */ + &phantomInterrupt, /* Channel 52 */ + &phantomInterrupt, /* Channel 53 */ + &phantomInterrupt, /* Channel 54 */ + &phantomInterrupt, /* Channel 55 */ + &phantomInterrupt, /* Channel 56 */ + &phantomInterrupt, /* Channel 57 */ + &phantomInterrupt, /* Channel 58 */ + &phantomInterrupt, /* Channel 59 */ + &phantomInterrupt, /* Channel 60 */ + &phantomInterrupt, /* Channel 61 */ + &phantomInterrupt, /* Channel 62 */ + &phantomInterrupt, /* Channel 63 */ + &phantomInterrupt, /* Channel 64 */ + &phantomInterrupt, /* Channel 65 */ + &phantomInterrupt, /* Channel 66 */ + &phantomInterrupt, /* Channel 67 */ + &phantomInterrupt, /* Channel 68 */ + &phantomInterrupt, /* Channel 69 */ + &phantomInterrupt, /* Channel 70 */ + &phantomInterrupt, /* Channel 71 */ + &phantomInterrupt, /* Channel 72 */ + &phantomInterrupt, /* Channel 73 */ + &phantomInterrupt, /* Channel 74 */ + &phantomInterrupt, /* Channel 75 */ + &phantomInterrupt, /* Channel 76 */ + &phantomInterrupt, /* Channel 77 */ + &phantomInterrupt, /* Channel 78 */ + &phantomInterrupt, /* Channel 79 */ + &phantomInterrupt, /* Channel 80 */ + &phantomInterrupt, /* Channel 81 */ + &phantomInterrupt, /* Channel 82 */ + &phantomInterrupt, /* Channel 83 */ + &phantomInterrupt, /* Channel 84 */ + &phantomInterrupt, /* Channel 85 */ + &phantomInterrupt, /* Channel 86 */ + &phantomInterrupt, /* Channel 87 */ + &phantomInterrupt, /* Channel 88 */ + &phantomInterrupt, /* Channel 89 */ + &phantomInterrupt, /* Channel 90 */ + &phantomInterrupt, /* Channel 91 */ + &phantomInterrupt, /* Channel 92 */ + &phantomInterrupt, /* Channel 93 */ + &phantomInterrupt, /* Channel 94 */ + &phantomInterrupt, /* Channel 95 */ + &phantomInterrupt, /* Channel 96 */ + &phantomInterrupt, /* Channel 97 */ + &phantomInterrupt, /* Channel 98 */ + &phantomInterrupt, /* Channel 99 */ + &phantomInterrupt, /* Channel 100 */ + &phantomInterrupt, /* Channel 101 */ + &phantomInterrupt, /* Channel 102 */ + &phantomInterrupt, /* Channel 103 */ + &phantomInterrupt, /* Channel 104 */ + &phantomInterrupt, /* Channel 105 */ + &phantomInterrupt, /* Channel 106 */ + &phantomInterrupt, /* Channel 107 */ + &phantomInterrupt, /* Channel 108 */ + &phantomInterrupt, /* Channel 109 */ + &phantomInterrupt, /* Channel 110 */ + &phantomInterrupt, /* Channel 111 */ + &phantomInterrupt, /* Channel 112 */ + &phantomInterrupt, /* Channel 113 */ + &phantomInterrupt, /* Channel 114 */ + &phantomInterrupt, /* Channel 115 */ + &phantomInterrupt, /* Channel 116 */ + &phantomInterrupt, /* Channel 117 */ + &phantomInterrupt, /* Channel 118 */ + &phantomInterrupt, /* Channel 119 */ + &phantomInterrupt, /* Channel 120 */ + &phantomInterrupt, /* Channel 121 */ + &phantomInterrupt, /* Channel 122 */ + &phantomInterrupt, /* Channel 123 */ + &phantomInterrupt, /* Channel 124 */ + &phantomInterrupt, /* Channel 125 */ + &phantomInterrupt, /* Channel 126 */ +}; +void vimECCErrorHandler( void ); + +/* SourceId : VIM_SourceId_001 */ +/* DesignId : VIM_DesignId_001 */ +/* Requirements : CONQ_VIM_SR2 */ +/** @fn void vimInit(void) + * @brief Initializes VIM module + * + * This function initializes VIM RAM and registers + */ + +void vimInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable ECC for VIM RAM */ + /* Errata VIM#28 Workaround: Disable Single Bit error correction */ + vimREG->ECCCTL = ( uint32 ) ( ( uint32 ) 0xAU << 0U ) + | ( uint32 ) ( ( uint32 ) 0x5U << 16U ); + + /* Initialize VIM table */ + { + uint32 i; + + for( i = 0U; i < VIM_CHANNELS; i++ ) + { + vimRAM->ISR[ i ] = s_vim_init[ i ]; + } + } + vimREG->FBVECADDR = ( uint32 ) &vimECCErrorHandler; + + /* set IRQ/FIQ priorities */ + vimREG->FIRQPR0 = ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR1 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR2 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR3 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + /* enable interrupts */ + vimREG->REQMASKSET0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 1U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 1U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET1 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET2 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET3 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + /* Set Capture event sources */ + vimREG->CAPEVT = ( ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ); + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_002 */ +/* DesignId : VIM_DesignId_002 */ +/* Requirements : CONQ_VIM_SR5 */ +/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler) + * @brief Map selected interrupt request to the selected channel + * + * @param[in] request: Interrupt request number 2..95 + * @param[in] channel: VIM Channel number 2..95 + * @param[in] handler: Address of the interrupt handler + * + * This function will map selected interrupt request to the selected channel. + * + */ +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ) +{ + uint32 i, j; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + i = channel >> 2U; /* Find the register to configure */ + j = channel - ( i << 2U ); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /*Mapping the required interrupt request to the required channel*/ + vimREG->CHANCTRL[ i ] &= ~( uint32 ) ( ( uint32 ) 0xFFU << j ); + vimREG->CHANCTRL[ i ] |= ( request << j ); + + /*Updating VIMRAM*/ + vimRAM->ISR[ channel + 1U ] = handler; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_003 */ +/* DesignId : VIM_DesignId_003 */ +/* Requirements : CONQ_VIM_SR3 */ +/** @fn void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype) + * @brief Enable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..95 + * @param[in] inttype: Interrupt type + * - SYS_IRQ: Selected channel will be enabled as IRQ + * - SYS_FIQ: Selected channel will be enabled as FIQ + * + * This function will enable interrupt for the selected channel. + * + */ +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( channel >= 96U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR3 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 96U ) ); + } + else + { + vimREG->FIRQPR3 |= ( ( uint32 ) 1U << ( channel - 96U ) ); + } + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR2 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 64U ) ); + } + else + { + vimREG->FIRQPR2 |= ( ( uint32 ) 1U << ( channel - 64U ) ); + } + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR1 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 32U ) ); + } + else + { + vimREG->FIRQPR1 |= ( ( uint32 ) 1U << ( channel - 32U ) ); + } + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR0 &= ~( uint32 ) ( ( uint32 ) 1U << channel ); + } + else + { + vimREG->FIRQPR0 |= ( ( uint32 ) 1U << channel ); + } + vimREG->REQMASKSET0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_004 */ +/* DesignId : VIM_DesignId_004 */ +/* Requirements : CONQ_VIM_SR5 */ +/** @fn void vimDisableInterrupt(uint32 channel) + * @brief Disable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..95 + * + * This function will disable interrupt for the selected channel. + * + */ +void vimDisableInterrupt( uint32 channel ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + if( channel >= 96U ) + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* SourceId : VIM_SourceId_005 */ +/* DesignId : VIM_DesignId_005 */ +/* Requirements : CONQ_VIM_SR7 */ +/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE; + config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE; + config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE; + config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE; + config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 0U ] = VIM_CHANCTRL0_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 1U ] = VIM_CHANCTRL1_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 2U ] = VIM_CHANCTRL2_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 3U ] = VIM_CHANCTRL3_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 4U ] = VIM_CHANCTRL4_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 5U ] = VIM_CHANCTRL5_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 6U ] = VIM_CHANCTRL6_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 7U ] = VIM_CHANCTRL7_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 8U ] = VIM_CHANCTRL8_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 9U ] = VIM_CHANCTRL9_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 10U ] = VIM_CHANCTRL10_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 11U ] = VIM_CHANCTRL11_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 12U ] = VIM_CHANCTRL12_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 13U ] = VIM_CHANCTRL13_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 14U ] = VIM_CHANCTRL14_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 15U ] = VIM_CHANCTRL15_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 16U ] = VIM_CHANCTRL16_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 17U ] = VIM_CHANCTRL17_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 18U ] = VIM_CHANCTRL18_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 19U ] = VIM_CHANCTRL19_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 20U ] = VIM_CHANCTRL20_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 21U ] = VIM_CHANCTRL21_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 22U ] = VIM_CHANCTRL22_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 23U ] = VIM_CHANCTRL23_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0; + config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1; + config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2; + config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3; + config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0; + config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1; + config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2; + config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3; + config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0; + config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1; + config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2; + config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3; + config_reg->CONFIG_CAPEVT = vimREG->CAPEVT; + config_reg->CONFIG_CHANCTRL[ 0U ] = vimREG->CHANCTRL[ 0U ]; + config_reg->CONFIG_CHANCTRL[ 1U ] = vimREG->CHANCTRL[ 1U ]; + config_reg->CONFIG_CHANCTRL[ 2U ] = vimREG->CHANCTRL[ 2U ]; + config_reg->CONFIG_CHANCTRL[ 3U ] = vimREG->CHANCTRL[ 3U ]; + config_reg->CONFIG_CHANCTRL[ 4U ] = vimREG->CHANCTRL[ 4U ]; + config_reg->CONFIG_CHANCTRL[ 5U ] = vimREG->CHANCTRL[ 5U ]; + config_reg->CONFIG_CHANCTRL[ 6U ] = vimREG->CHANCTRL[ 6U ]; + config_reg->CONFIG_CHANCTRL[ 7U ] = vimREG->CHANCTRL[ 7U ]; + config_reg->CONFIG_CHANCTRL[ 8U ] = vimREG->CHANCTRL[ 8U ]; + config_reg->CONFIG_CHANCTRL[ 9U ] = vimREG->CHANCTRL[ 9U ]; + config_reg->CONFIG_CHANCTRL[ 10U ] = vimREG->CHANCTRL[ 10U ]; + config_reg->CONFIG_CHANCTRL[ 11U ] = vimREG->CHANCTRL[ 11U ]; + config_reg->CONFIG_CHANCTRL[ 12U ] = vimREG->CHANCTRL[ 12U ]; + config_reg->CONFIG_CHANCTRL[ 13U ] = vimREG->CHANCTRL[ 13U ]; + config_reg->CONFIG_CHANCTRL[ 14U ] = vimREG->CHANCTRL[ 14U ]; + config_reg->CONFIG_CHANCTRL[ 15U ] = vimREG->CHANCTRL[ 15U ]; + config_reg->CONFIG_CHANCTRL[ 16U ] = vimREG->CHANCTRL[ 16U ]; + config_reg->CONFIG_CHANCTRL[ 17U ] = vimREG->CHANCTRL[ 17U ]; + config_reg->CONFIG_CHANCTRL[ 18U ] = vimREG->CHANCTRL[ 18U ]; + config_reg->CONFIG_CHANCTRL[ 19U ] = vimREG->CHANCTRL[ 19U ]; + config_reg->CONFIG_CHANCTRL[ 20U ] = vimREG->CHANCTRL[ 20U ]; + config_reg->CONFIG_CHANCTRL[ 21U ] = vimREG->CHANCTRL[ 21U ]; + config_reg->CONFIG_CHANCTRL[ 22U ] = vimREG->CHANCTRL[ 22U ]; + config_reg->CONFIG_CHANCTRL[ 23U ] = vimREG->CHANCTRL[ 23U ]; + } +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/* SourceId : VIM_SourceId_006 */ +/* DesignId : VIM_DesignId_006 */ +/* Requirements : CONQ_VIM_SR6 */ +void vimECCErrorHandler( void ) +{ + uint32 vec; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Identify the corrupted address */ + uint32 error_addr = vimREG->UERRADDR; + + /* Identify the channel number */ + uint32 error_channel = ( ( error_addr & 0x3FFU ) >> 2U ); + + /* Correct the corrupted location */ + vimRAM->ISR[ error_channel ] = s_vim_init[ error_channel ]; + + /* Clear Parity Error Flag */ + vimREG->ECCSTAT = 1U; + + /* Disable and enable the highest priority pending channel */ + if( vimREG->FIQINDEX != 0U ) + { + vec = vimREG->FIQINDEX - 1U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Read 32 bit volatile register" */ + vec = vimREG->IRQINDEX - 1U; + } + if( vec == 0U ) + { + vimREG->INTREQ0 = 1U; + vec = esmREG->IOFFHR - 1U; + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( esmREG, vec ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( esmREG, ( vec - 32U ) ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( esmREG, ( vec - 32U ) ); + } + else if( ( vec >= 128U ) && ( vec < 160U ) ) + { + esmREG->SR7[ 0U ] = ( uint32 ) 1U << ( vec - 128U ); + esmGroup2Notification( esmREG, ( vec - 96U ) ); + } + else + { + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + esmREG->SR4[ 1U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + } + else if( vec < 32U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << vec; + vimREG->REQMASKSET0 = ( uint32 ) 1U << vec; + } + else if( vec < 64U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( vec - 32U ); + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( vec - 32U ); + } + else if( vec < 96U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( vec - 64U ); + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( vec - 64U ); + } + else + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( vec - 96U ); + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( vec - 96U ); + } + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c new file mode 100644 index 00000000000..c12435362e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c @@ -0,0 +1,652 @@ +/** @file system.c + * @brief System Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "system.h" +#include "reg_pcr.h" +#include "pinmux.h" + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void systemInit(void) + * @brief Initializes System Driver + * + * This function initializes the System driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : SYSTEM_SourceId_001 */ +/* DesignId : SYSTEM_DesignId_001 */ +/* Requirements : CONQ_SYSTEM_SR3 */ +void setupPLL( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* Disable PLL1 and PLL2 */ + systemREG1->CSDISSET = 0x00000002U | 0x00000040U; + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x42U ) != 0x42U ) + { + /* Wait */ + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x301U; + + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /** - Setup pll control register 1: + * - Setup reset on oscillator slip + * - Setup bypass on pll slip + * - setup Pll output clock divider to max before Lock + * - Setup reset on oscillator fail + * - Setup reference clock divider + * - Setup Pll multiplier + */ + systemREG1->PLLCTL1 = ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) + | ( uint32 ) ( 0x9500U ); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider + * - Setup spreading amount + */ + systemREG1->PLLCTL2 = ( uint32 ) ( ( uint32 ) 255U << 22U ) + | ( uint32 ) ( ( uint32 ) 7U << 12U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U; + + /** @b Initialize @b Pll2: */ + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + systemREG2->PLLCTL3 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) + | ( uint32 ) ( 0x9500U ); + + /** - Enable PLL(s) to start up or Lock */ + systemREG1->CSDIS = 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000004U; +} + +/** @fn void trimLPO(void) + * @brief Initialize LPO trim values + * + * Load TRIM values from OTP if present else call customTrimLPO() function + * + */ +/* SourceId : SYSTEM_SourceId_002 */ +/* DesignId : SYSTEM_DesignId_002 */ +/* Requirements : CONQ_SYSTEM_SR6 */ +void trimLPO( void ) +{ + uint32 u32clocktestConfig; + /* Save user clocktest register configuration */ + u32clocktestConfig = systemREG1->CLKTEST; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO + * clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify + * what the maximum step is so there is no metric to use for the SW implementation - + * the routine can temporarily disable the LPOCLKMON range check so the sudden change + * will not cause a fault.*/ + /* Disable clock range detection*/ + + systemREG1->CLKTEST = ( systemREG1->CLKTEST | ( uint32 ) ( ( uint32 ) 0x1U << 24U ) ) + & ( uint32 ) ( ~( ( uint32 ) 0x1U << 25U ) ); + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) LPO_TRIM_VALUE ); + } + else + { + customTrimLPO(); + } + + /* Restore the user clocktest register value configuration */ + systemREG1->CLKTEST = u32clocktestConfig; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_003 */ +/* DesignId : SYSTEM_DesignId_003 */ +/* Requirements : CONQ_SYSTEM_SR5 */ +void setupFlash( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Setup flash read mode, address wait states and data wait states */ + flashWREG->FRDCNTL = 0x00000000U | ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U; + + /** - Setup flash access wait states for bank 7 */ + FSM_WR_ENA_HL = 0x5U; + EEPROM_CONFIG_HL = 0x00000002U | ( uint32 ) ( ( uint32 ) 9U << 16U ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Disable write access to flash state machine registers */ + FSM_WR_ENA_HL = 0x2U; + + /** - Setup flash bank power modes */ + flashWREG->FBPWRMODE = 0x00000000U + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) /* BANK 7 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) /* BANK 1 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ); /* BANK 0 */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_004 */ +/* DesignId : SYSTEM_DesignId_004 */ +/* Requirements : CONQ_SYSTEM_SR4 */ +void periphInit( void ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /** - Disable Peripherals before peripheral powerup*/ + systemREG1->CLKCNTL &= 0xFFFFFEFFU; + + /** - Release peripherals from reset and enable clocks to all peripherals */ + /** - Power-up all peripherals */ + pcrREG1->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + pcrREG2->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + pcrREG3->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + /** - Enable Peripherals */ + systemREG1->CLKCNTL |= 0x00000100U; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : CONQ_SYSTEM_SR7 */ +void mapClocks( void ) +{ + uint32 SYS_CSVSTAT, SYS_CSDIS; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /** @b Initialize @b Clock @b Tree: */ + /** - Setup system clock divider for HCLK */ + systemREG2->HCLKCNTL = 1U; + + /** - Disable / Enable clock domain */ + systemREG1->CDDIS = ( uint32 ) ( ( uint32 ) 0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* AVCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* AVCLK4 , 1 - OFF, 0 - ON + */ + + /* Always check the CSDIS register to make sure the clock source is turned on and + * check the CSVSTAT register to make sure the clock source is valid. Then write to + * GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + while( ( SYS_CSVSTAT & ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + != ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + { + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + } /* Wait */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and + * after wakeup */ + systemREG1->GHVSRC = ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + systemREG1->RCLKSRC = ( uint32 ) ( ( uint32 ) 1U << 24U ) /* RTI2 divider (Not + applicable for lock-step + device) */ + | ( uint32 ) ( ( uint32 ) SYS_VCLK + << 16U ) /* RTI2 clock source (Not applicable + for lock-step device) */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* RTI1 divider */ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); /* RTI1 clock source + */ + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + systemREG1->VCLKASRC = ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xF0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 24U ); + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xFFF0FFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ); + + systemREG2->CLK2CNTRL = ( systemREG2->CLK2CNTRL & 0xFFFFFFF0U ) + | ( uint32 ) ( ( uint32 ) 1U << 0U ); + + systemREG2->VCLKACON1 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed + * value */ + systemREG1->PLLCTL1 = ( systemREG1->PLLCTL1 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + /*SAFETYMCUSW 134 S MR:12.2 " Clear and write to the volatile register " */ + systemREG2->PLLCTL3 = ( systemREG2->PLLCTL3 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + + /* Enable/Disable Frequency modulation */ + systemREG1->PLLCTL2 |= 0x00000000U; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_006 */ +/* DesignId : SYSTEM_DesignId_006 */ +/* Requirements : CONQ_SYSTEM_SR2 */ +void systemInit( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /* Configure PLL control registers and enable PLLs. + * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock. + * This initialization sequence performs all the tasks that are not + * required to be done at full application speed while the PLL locks. + */ + setupPLL(); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* Enable clocks to peripherals and release peripheral reset */ + periphInit(); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* Configure device-level multiplexing and I/O multiplexing */ + muxInit(); + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /** - Set up flash address and data wait states based on the target CPU clock + * frequency The number of address and data wait states for the target CPU clock + * frequency are specified in the specific part's datasheet. + */ + setupFlash(); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */ + trimLPO(); + + /* + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF + * clock below 40MHz. Hence the init function needs to be called from the startup + * before the PLL is configured. + */ + emif_SDRAM_StartupInit(); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /** - Wait for PLLs to start up and map clock domains to desired clock sources */ + mapClocks(); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /** - set ECLK pins functional mode */ + systemREG1->SYSPC1 = 0U; + + /** - set ECLK pins default output value */ + systemREG1->SYSPC4 = 0U; + + /** - set ECLK pins output direction */ + systemREG1->SYSPC2 = 1U; + + /** - set ECLK pins open drain enable */ + systemREG1->SYSPC7 = 0U; + + /** - set ECLK pins pullup/pulldown enable */ + systemREG1->SYSPC8 = 0U; + + /** - set ECLK pins pullup/pulldown select */ + systemREG1->SYSPC9 = 1U; + + /** - Setup ECLK */ + systemREG1->ECPCNTL = ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_007 */ +/* DesignId : SYSTEM_DesignId_007 */ +/* Requirements : CONQ_SYSTEM_SR8 */ +void systemPowerDown( uint32 mode ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + /* Disable clock sources */ + systemREG1->CSDISSET = mode & 0x000000FFU; + + /* Disable clock domains */ + systemREG1->CDDIS = ( mode >> 8U ) & 0x00000FFFU; + + /* Idle CPU */ + /*SAFETYMCUSW 88 S MR:2.1 "Assembly in C needed" */ + _gotoCPUIdle_(); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_008 */ +/* DesignId : SYSTEM_DesignId_008 */ +/* Requirements : CONQ_SYSTEM_SR9 */ +resetSource_t getResetSource( void ) +{ + register resetSource_t rst_source; + + if( ( SYS_EXCEPTION & ( uint32 ) POWERON_RESET ) != 0U ) + { + /* power-on reset condition */ + rst_source = POWERON_RESET; + /* Clear all exception status Flag and proceed since it's power up */ + SYS_EXCEPTION = 0x0000FFFFU; + } + + else if( ( SYS_EXCEPTION & ( uint32 ) EXT_RESET ) != 0U ) + { + SYS_EXCEPTION = ( uint32 ) EXT_RESET; + /*** Check for other causes of EXT_RESET that would take precedence **/ + if( ( SYS_EXCEPTION & ( uint32 ) OSC_FAILURE_RESET ) != 0U ) + { + /* Reset caused due to oscillator failure. Add user code here to handle + * oscillator failure */ + rst_source = OSC_FAILURE_RESET; + SYS_EXCEPTION = ( uint32 ) OSC_FAILURE_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) WATCHDOG_RESET ) != 0U ) + { + /* Reset caused due watchdog violation */ + rst_source = WATCHDOG_RESET; + SYS_EXCEPTION = ( uint32 ) WATCHDOG_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) WATCHDOG2_RESET ) != 0U ) + { + /* Reset caused due watchdog violation */ + rst_source = WATCHDOG2_RESET; + SYS_EXCEPTION = ( uint32 ) WATCHDOG2_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) SW_RESET ) != 0U ) + { + /* Reset caused due to software reset. */ + rst_source = SW_RESET; + SYS_EXCEPTION = ( uint32 ) SW_RESET; + } + else + { + /* Reset caused due to External reset. */ + rst_source = EXT_RESET; + } + } + else if( ( SYS_EXCEPTION & ( uint32 ) DEBUG_RESET ) != 0U ) + { + /* Reset caused due Debug reset request */ + rst_source = DEBUG_RESET; + SYS_EXCEPTION = ( uint32 ) DEBUG_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) CPU0_RESET ) != 0U ) + { + /* Reset caused due to CPU0 reset. CPU reset can be caused by CPU self-test + * completion, or by toggling the "CPU RESET" bit of the CPU Reset Control + * Register. */ + rst_source = CPU0_RESET; + SYS_EXCEPTION = ( uint32 ) CPU0_RESET; + } + else + { + /* No_reset occured. */ + rst_source = NO_RESET; + } + return rst_source; +} + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_009 */ +/* DesignId : SYSTEM_DesignId_009 */ +/* Requirements : CONQ_SYSTEM_SR10 */ +/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + */ +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE; + config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE; + config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE; + config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE; + config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE; + config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE; + config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE; + config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE; + config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE; + config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE; + config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE; + config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE; + config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE; + config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2; + config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE; + config_reg->CONFIG_SYSPC10 = SYS_SYSPC10_CONFIGVALUE; + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1; + } + else + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2; + } + config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE; + config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE; + config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE; + config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE; + config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE; + config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE; + config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE; + config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2; + config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL1 = SYS2_ECPCNTL1_CONFIGVALUE; + config_reg->CONFIG_CLK2CNTRL = SYS2_CLK2CNTRL_CONFIGVALUE; + config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE; + config_reg->CONFIG_HCLKCNTL = SYS2_HCLKCNTL_CONFIGVALUE; + config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE; + config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE; + } + else + { + config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1; + config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2; + config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7; + config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8; + config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9; + config_reg->CONFIG_CSDIS = systemREG1->CSDIS; + config_reg->CONFIG_CDDIS = systemREG1->CDDIS; + config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC; + config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC; + config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC; + config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR; + config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR; + config_reg->CONFIG_MSINENA = systemREG1->MSINENA; + config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1; + config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2; + config_reg->CONFIG_SYSPC10 = systemREG1->SYSPC10; + config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL; + config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST; + config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1; + config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2; + config_reg->CONFIG_GPREG1 = systemREG1->GPREG1; + config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR; + config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1; + config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL; + config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL; + config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1; + config_reg->CONFIG_SYSECR = systemREG1->SYSECR; + config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3; + config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV; + config_reg->CONFIG_ECPCNTL1 = systemREG2->ECPCNTL1; + config_reg->CONFIG_CLK2CNTRL = systemREG2->CLK2CNTRL; + config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1; + config_reg->CONFIG_HCLKCNTL = systemREG2->HCLKCNTL; + config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP; + config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN; + } +} + +/** @fn customTrimLPO(void) + * @brief custom function to initilize LPO trim values + * + * This function initializes default LPO trim values if OTP value is 0XFFFF, + * user can also write their own code to handle this case . + * + */ +void customTrimLPO( void ) +{ + /* User can write logic to handle the case where LPO trim is set to 0xFFFFu */ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + /* Load default trimLPO value */ + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 16U ); + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt new file mode 100644 index 00000000000..6cc77d74ad2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt @@ -0,0 +1,204 @@ +cmake_minimum_required(VERSION 3.22) + +SET(CMAKE_CROSSCOMPILING "TRUE" CACHE STRING "Set Cross Compiling to true" FORCE) + +# Strip the default MacOSX flags that cause cross-compilations to fail. +SET(CMAKE_OSX_DEPLOYMENT_TARGET "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) +SET(CMAKE_OSX_SYSROOT "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) + +# Set the compiler before declaring the project for the test build +SET(CMAKE_C_COMPILER "arm-none-eabi-gcc") +SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") + +# Set the system processor and name before declaring the project +# Needs to be set here otherwise it will fail the test compilation +SET(CMAKE_SYSTEM_NAME "Generic" CACHE STRING "Target system is a generic ARM Processor") +SET(CMAKE_SYSTEM_PROCESSOR "armv7-r" CACHE STRING "Target system is an ARM7r Processor") + +# Set the ASM and C compilation flags +SET(CMAKE_ASM_FLAGS "-mcpu=cortex-r5 -mfpu=vfpv3-d16 -Og -g -ggdb -Wall -MMD -MP") +SET(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -specs=\"nosys.specs\" -specs=\"nano.specs\"") +SET(CMAKE_C_FLAGS "${CMAKE_ASM_FLAGS} -marm -mfloat-abi=hard") + +project(RM57_FreeRTOS C ASM) + +SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR} CACHE STRING "") + +# Increase the debug level of the CMAKE build +SET(CMAKE_VERBOSE_MAKEFILE ON) + +# Get the absolute path to the Demo Directory +SET(DEMO_DIR_REL "${CMAKE_CURRENT_SOURCE_DIR}") +GET_FILENAME_COMPONENT(DEMO_DIR ${DEMO_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Board Files +SET(BOARD_FILES_DIR_REL "${DEMO_DIR}/BoardFiles") +GET_FILENAME_COMPONENT(BOARD_FILES_DIR ${BOARD_FILES_DIR_REL} ABSOLUTE) + +SET(FREERTOS_CONFIG_FILE_DIRECTORY "${DEMO_DIR}/include" CACHE STRING "Config File Path") +SET(FREERTOS_PORT "GCC_ARM_CRx_No_GIC" CACHE STRING "FreeRTOS Port to Use") + +ADD_LIBRARY(freertos_config INTERFACE) +TARGET_INCLUDE_DIRECTORIES(freertos_config SYSTEM + INTERFACE + INCLUDE ${FREERTOS_CONFIG_FILE_DIRECTORY} +) + +# Clone the tag of the FreeRTOS-Kernel last tested with this project. +INCLUDE(FetchContent) + +FetchContent_Declare( + FreeRTOS-Kernel + GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git + # Last tested FreeRTOS-Kernel Commit + GIT_TAG main + SOURCE_DIR "${DEMO_DIR}/../../Source" + USES_TERMINAL_DOWNLOAD YES + USES_TERMINAL_UPDATE YES + BUILD_COMMAND "" +) + +# Uncomment the following lines to use Fetch-Content to clone Kernel. +# FetchContent_GetProperties(FreeRTOS-Kernel) +# if(NOT FreeRTOS-Kernel_POPULATED) +# FetchContent_Populate(FreeRTOS-Kernel) +# endif() + + +# Get the absolute path to the FreeRTOS-Kernel Directory +SET(FREERTOS_KERNEL_DIR_REL "${DEMO_DIR}/../../Source") +GET_FILENAME_COMPONENT(FREERTOS_KERNEL_DIR ${FREERTOS_KERNEL_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Port Directory +SET(PORT_DIR_REL "${FREERTOS_KERNEL_DIR}/portable/GCC/ARM_CRx_No_GIC") +GET_FILENAME_COMPONENT(PORT_DIR ${PORT_DIR_REL} ABSOLUTE) + +# Debug +MESSAGE("Project: ${PROJECT_NAME}") +MESSAGE("Demo Directory: ${DEMO_DIR}") +MESSAGE("FREERTOS_KERNEL_DIR: ${FREERTOS_KERNEL_DIR}") +MESSAGE("PORT_DIR: ${PORT_DIR}") + +INCLUDE_DIRECTORIES( + ${DEMO_DIR} + ${DEMO_DIR}/include + ${BOARD_FILES_DIR}/include + ${FREERTOS_KERNEL_DIR}/include + ${PORT_DIR} +) + +# Source files used for the FreeRTOS Demos +SET(FREERTOS_DEMO_SOURCES + ${DEMO_DIR}/source/main.c + ${DEMO_DIR}/source/irq_demo.c + ${DEMO_DIR}/source/notification_demo.c + ${DEMO_DIR}/source/queue_demo.c + ${DEMO_DIR}/source/reg_test.c + ${DEMO_DIR}/source/reg_test_GCC.S +) + +# Source files used for the Board Support Package +ADD_LIBRARY(TI_BOARD_SUPPORT_PACKAGE OBJECT + ${BOARD_FILES_DIR}/source/adc.c + ${BOARD_FILES_DIR}/source/can.c + ${BOARD_FILES_DIR}/source/crc.c + ${BOARD_FILES_DIR}/source/dabort.S + ${BOARD_FILES_DIR}/source/dcc.c + ${BOARD_FILES_DIR}/source/ecap.c + ${BOARD_FILES_DIR}/source/emac.c + ${BOARD_FILES_DIR}/source/emif.c + ${BOARD_FILES_DIR}/source/epc.c + ${BOARD_FILES_DIR}/source/eqep.c + ${BOARD_FILES_DIR}/source/errata.c + ${BOARD_FILES_DIR}/source/errata_SSWF021_45.c + ${BOARD_FILES_DIR}/source/esm.c + ${BOARD_FILES_DIR}/source/etpwm.c + ${BOARD_FILES_DIR}/source/gio.c + ${BOARD_FILES_DIR}/source/het.c + ${BOARD_FILES_DIR}/source/i2c.c + ${BOARD_FILES_DIR}/source/lin.c + ${BOARD_FILES_DIR}/source/mdio.c + ${BOARD_FILES_DIR}/source/mibspi.c + ${BOARD_FILES_DIR}/source/nmpu.c + ${BOARD_FILES_DIR}/source/notification.c + ${BOARD_FILES_DIR}/source/phy_dp83640.c + ${BOARD_FILES_DIR}/source/phy_tlk111.c + ${BOARD_FILES_DIR}/source/pinmux.c + ${BOARD_FILES_DIR}/source/pom.c + ${BOARD_FILES_DIR}/source/sci.c + ${BOARD_FILES_DIR}/source/sys_core.S + ${BOARD_FILES_DIR}/source/sys_dma.c + ${BOARD_FILES_DIR}/source/sys_intvecs.S + ${BOARD_FILES_DIR}/source/sys_link.ld + ${BOARD_FILES_DIR}/source/sys_pcr.c + ${BOARD_FILES_DIR}/source/sys_phantom.c + ${BOARD_FILES_DIR}/source/sys_pmm.c + ${BOARD_FILES_DIR}/source/sys_pmu.S + ${BOARD_FILES_DIR}/source/sys_startup.c + ${BOARD_FILES_DIR}/source/system.c + ${BOARD_FILES_DIR}/source/sys_vim.c +) + +# FreeRTOS Kernel Files +ADD_LIBRARY(FREERTOS_KERNEL OBJECT + ${FREERTOS_KERNEL_DIR}/croutine.c + ${FREERTOS_KERNEL_DIR}/event_groups.c + ${FREERTOS_KERNEL_DIR}/list.c + ${FREERTOS_KERNEL_DIR}/queue.c + ${FREERTOS_KERNEL_DIR}/stream_buffer.c + ${FREERTOS_KERNEL_DIR}/tasks.c + ${FREERTOS_KERNEL_DIR}/timers.c +) + +ADD_LIBRARY(FREERTOS_PORT OBJECT + ${PORT_DIR}/portASM.S + ${PORT_DIR}/port.c +) + +# On Mac the C_LINK flags by default adds "-Wl,-search_paths_first -Wl,-headerpad_max_install_names" which +# Causes the executable that gets built to strip the symbols, so force set it to empty here. +SET(CMAKE_C_LINK_FLAGS "") +SET(CMAKE_EXE_LINKER_FLAGS "-Wl,-Map,\"RTOSDemo.map\" -Wl,-T\"${BOARD_FILES_DIR}/source/sys_link.ld\"") + +# Debug +MESSAGE("Demo Sources: ${FREERTOS_DEMO_SOURCES}") +MESSAGE("FreeRTOS Sources: ${FREERTOS_KERNEL_SOURCES}") +MESSAGE("Port Sources: ${FREERTOS_PORT_SOURCES}") + +# Create Full Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Full.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Register Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Register_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Queue Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Queue_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create IRQ Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_IRQ_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Notification Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Notification_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# These options are explained in the demo_tasks.h file +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Full.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x0F") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Register_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x1") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Queue_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x2") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_IRQ_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x4") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Notification_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x8") + +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Full.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Register_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Queue_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_IRQ_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Notification_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/README.md b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/README.md new file mode 100644 index 00000000000..b4e6919ffd9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/README.md @@ -0,0 +1,67 @@ +# Intro + +This directory contains a FreeRTOS project to build a set of demos for the +[RM57L843](https://www.ti.com/product/RM57L843) board. The demos to build are +selected using the macro `mainDEMO_TYPE` in the `include/demo_tasks.h` file. + +It is set up to blink LEDs on the Texas Instruments +[LAUNCHXL2-RM57L](https://www.ti.com/tool/LAUNCHXL2-RM57L) +and the [TMDXRM57LHDK](https://www.ti.com/tool/TMDXRM57LHDK) Development Kits. + +The code related to the Main Demo Files can be found in the +[source](./source) directory. +The code related to the board setup can be found in the +[BoardFiles](./BoardFiles) directory. + +## Building + +This demo can either be loaded into Texas Instrument's +[Code Composer Studio (CCS)](https://www.ti.com/tool/CCSTUDIO). +or built using [CMake](https://cmake.org/). + +### CCS Build + +If building with CCS you need to install CCS, and then install the +[ARM Compiler Tools](https://software-dl.ti.com/ccs/esd/documents/ccs_compiler-installation-selection.html#compiler-installation) +as well as the Hercules Safety MCUs +[device support targets](https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_installation.html#device-support). + +After doing this, you can then open this directory in CCS, which will load up the +project. If everything installed correctly you should then be able to build and flash +to the board. + +Please be aware there is a filter on [CMakeLists.txt](./CMakeLists.txt) and the *build* +directory in the CCS project. + +This is to keep CCS from attempting to use resources generated with a CMAKE build. +If a directory other than "build" is selected when building using CMAKE, CCS will +attempt to use the the files in that directory, leading to build issues in CCS. +At time of writing this can be fixed by right clicking the folder in CCS +and selecting "Exclude from build". + +### CMake build + +When using CMake you will need to install a compatible version of the +[Arm GNU Toolchain](https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain) +and add this to your `PATH`. + +After doing this inspect the [demo_task.h](./include/demo_tasks.h#L30) file to see +what the possible demo configurations are, and select your desired demo config. + +The `all` options builds all combinations of these. +Example Usage: + +```sh +cmake -S . -B build; +make -C build all; +``` + +The generated binaries can then be found in the `build` directory. +These binaries can then be flashed to the board by using +[Uniflash](https://www.ti.com/tool/UNIFLASH) or by using CCS. + +## UART Output + +Rudimentary UART output is available by opening a Serial Connection +to the board. The settings for the UART are a BAUD rate of 115200, 1 stopbit, +and None Parity. diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h new file mode 100644 index 00000000000..acef1b15ed2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h @@ -0,0 +1,170 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Section of the file that can't be included in ASM Pre-processor */ +#ifndef FREERTOS_ASSEMBLY + #include + #ifndef configASSERT + +/* debug ASSERT The first option calls a function that prints to UART + * The second one loops for when using a debugger. */ +extern void vAssertCalled( const char * pcFileName, uint32_t ulLine ); + #define configASSERT( x ) \ + if( ( x ) == pdFALSE ) \ + { \ + vAssertCalled( __func__, __LINE__ ); \ + } + +extern void vMainSetupTimerInterrupt( void ); + #define configCLEAR_TICK_INTERRUPT() + #define configSETUP_TICK_INTERRUPT() vMainSetupTimerInterrupt() + #endif /* configASSERT */ +#endif /* FREERTOS_ASSEMBLY */ + +#ifndef FREERTOS_CONFIG_H + #define FREERTOS_CONFIG_H + + /*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + + /** Code Composer Studio will throw errors about NULL not being defined. + * as such wrap a define for NULL to 0 to remove the errors. + */ + #ifndef NULL + #define NULL 0x0 + #endif + + #define configNUMBER_OF_CORES 1U + #define configUSE_PREEMPTION 1U + #define configUSE_IDLE_HOOK 1U + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + #define configUSE_TICK_HOOK 0 + #define configMAX_PRIORITIES ( 30UL ) + #define configQUEUE_REGISTRY_SIZE 10U + #define configSUPPORT_STATIC_ALLOCATION 1U + #define configSUPPORT_DYNAMIC_ALLOCATION 0U + #define configUSE_TASK_FPU_SUPPORT 2U + + #define configCPU_CLOCK_HZ ( 110000000U ) + #define configTICK_RATE_HZ ( 1000U ) + #define configMINIMAL_STACK_SIZE ( 0x80 ) + #define configSYSTEM_CALL_STACK_SIZE configMINIMAL_STACK_SIZE + #define configTOTAL_HEAP_SIZE ( ( 80 * 512 ) ) + #define configMAX_TASK_NAME_LEN ( 0x20U ) + #define configUSE_TRACE_FACILITY 0U + #define configUSE_16_BIT_TICKS 0 + #define configIDLE_SHOULD_YIELD 0 + #define configUSE_CO_ROUTINES 0 + #define configUSE_MUTEXES 1U + #define configUSE_RECURSIVE_MUTEXES 1U + #define configUSE_EVENT_GROUPS 0U + #define configCHECK_FOR_STACK_OVERFLOW 0 + #define configUSE_QUEUE_SETS 1U + #define configUSE_COUNTING_SEMAPHORES 1U + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1U + #define configUSE_POSIX_ERRNO 0 + #define configUSE_TIME_SLICING 0 + #define configUSE_C_RUNTIME_TLS_SUPPORT 0 + #define configUSE_NEWLIB_REENTRANT 0 + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 + #define configUSE_MALLOC_FAILED_HOOK 0 + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + #define configAPPLICATION_ALLOCATED_HEAP 0 + #define configUSE_SB_COMPLETED_CALLBACK 0 + #define configRUN_MULTIPLE_PRIORITIES 0 + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING 0 + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + #define configUSE_MINI_LIST_ITEM 0 + #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 0x20UL + + /* Timer related defines. */ + #define configUSE_TIMERS 1 + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 6UL ) + #define configTIMER_QUEUE_LENGTH 20 + #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + #define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 + #define INCLUDE_xTimerPendFunctionCall 1 + + /* Task Notification defines. */ + #define configUSE_TASK_NOTIFICATIONS 1 + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 3 + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. */ + + #define INCLUDE_vTaskPrioritySet 1 + #define INCLUDE_uxTaskPriorityGet 1 + #define INCLUDE_vTaskDelete 1 + #define INCLUDE_vTaskCleanUpResources 0 + #define INCLUDE_vTaskSuspend 1 + #define INCLUDE_xTaskDelayUntil 1 + #define INCLUDE_vTaskDelay 1 + #define INCLUDE_uxTaskGetStackHighWaterMark 1 + #define INCLUDE_xTaskGetSchedulerState 1 + #define INCLUDE_xTaskGetIdleTaskHandle 1 + #define INCLUDE_xSemaphoreGetMutexHolder 1 + #define INCLUDE_eTaskGetState 1 + #define INCLUDE_xTaskAbortDelay 1 + #define INCLUDE_xTaskGetHandle 1 + + /** Note: These value come from the Board Support Package. They are pulled directly + * from sys_vim.h, and reg_vim.h. These values correspond to hardware registers + * and keys exclusive to the board that this demo was written for. + */ + + /** @brief Address of MCU Register used to mark the end of an IRQ */ + #define configEOI_ADDRESS 0xFFFFFE70UL + + /** @brief Address of Real Time Interrupt (RTI) used for the system clock */ + #define configRTI_ADDRESS 0xFFFFFC88UL + + /** @brief Value used to clear a RTI Interrupt */ + #define configRTI_CLEAR_VALUE 0x1 + + /** @brief Address of Register used to trigger Software Interrupts (SWI) */ + #define configSWI_ADDRESS 0xFFFFFFB0UL + + /** @brief Key value that is written to the SWI Interrupt Register */ + #define configSWI_KEY_VAL 0x7500UL + + /** @brief Address of Register used to clear SWI Interrupts */ + #define configSWI_CLEAR_ADDRESS 0xFFFFFFF4UL + + /** @brief Value to write to clear a Software Interrupt (SWI) */ + #define configSWI_CLEAR_VAL 0x0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h new file mode 100644 index 00000000000..abf24267bab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h @@ -0,0 +1,181 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEMO_TASKS_H +#define DEMO_TASKS_H + +/* ----------------------------------- Demo Option ----------------------------------- */ + +/** @brief Create Tasks that are written in assembly to test context swaps */ +#define REGISTER_DEMO 0x1 + +/** @brief Demo that uses timers, timer callbacks, and Queues */ +#define QUEUE_DEMO 0x2 + +/** @brief Demo that causes and unwinds a Nested IRQ */ +#define IRQ_DEMO 0x4 + +/** @brief Demo that uses the Task Notification APIs */ +#define NOTIFICATION_DEMO 0x8 + +/** @brief Build Register, Queue, IRQ, and Notification demos */ +#define FULL_DEMO ( REGISTER_DEMO | QUEUE_DEMO | IRQ_DEMO | NOTIFICATION_DEMO ) + +/** @brief Bitfield used to select the Demo Tasks to build and run + * + * @note This project contains multiple demo and test tasks. A bitfield is used + * to select which demos and tests are built and run as part of the executable. + * More information about what these demos and tests do can be found in their + * corresponding files. + * + * Bit 1 Set: Include the Register Test Tasks + * + * Bit 2 Set: Include the Queue Send and Receive Test Tasks + * + * Bit 3 Set: Include the Nested IRQ Test Tasks + * + * Bit 4 Set: Include the Notification Test Tasks + * + */ +#ifndef mainDEMO_TYPE + #define mainDEMO_TYPE ( FULL_DEMO ) +#endif /* mainDEMO_TYPE */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "portmacro.h" + +/* These tasks have been given pseudo random priority values for testing. + * Except for the queue send and receive task any of these tasks priorities + * should be able to be set to any valid priority without issue. */ + +/** @brief Priority at which the Register Task 1 is created. */ +#define demoREG_TASK_1_PRIORITY ( configMAX_PRIORITIES - 2UL ) + +/** @brief Priority at which the Register Task 2 is created. */ +#define demoREG_TASK_2_PRIORITY ( configMAX_PRIORITIES - 1UL ) + +/** @brief Priority at which the prvQueueSendTask is created. */ +#define demoQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL ) + +/** @brief Priority at which the prvQueueReceiveTask is created. */ +#define demoQUEUE_RECEIVE_TASK_PRIORITY ( demoQUEUE_SEND_TASK_PRIORITY + 1UL ) + +/** @brief Priority at which the Nested IRQ Test Task is created. */ +#define demoIRQ_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 2UL ) + +/** @brief Priority at which the Notification Demo Task is created. */ +#define demoNOTIFICATION_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 1UL ) + +/* ------------------------------- Register Test Tasks ------------------------------- */ + +/* @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest1Implementation( void ); + +/** @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest2Implementation( void ); + +/** @brief Creates the Register Test Tasks implemented in reg_test_GCC.S + * @return pdPASS if all tasks are created, pdFAIL if they are not. + */ +BaseType_t xCreateRegisterTestTasks( void ); + +/* ----------------------------- Demo Tasks Declarations ----------------------------- */ + +/** + * @brief Create two tasks, a queue, and a timer, which are used to blink an LED. + * + * @return + * pdPASS if all objects are created. + * pdFAIL if any object cannot be created. + */ +BaseType_t xCreateQueueTasks( void ); + +/** @brief Create a task that waits for a response from a nested IRQ + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateIRQTestTask( void ); + +/** + * @brief Create tasks that send task notifications back and forth. + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateNotificationTestTask( void ); + +/** @brief Interrupt Handler used for Software Raised Interrupts */ +PRIVILEGED_FUNCTION void vIRQDemoHandler( void ); + +/* Registers required to configure the Real Time Interrupt (RTI). */ +#define portRTI_GCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC00UL ) ) +#define portRTI_TBCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC04UL ) ) +#define portRTI_COMPCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC0CUL ) ) +#define portRTI_CNT0_FRC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC10UL ) ) +#define portRTI_CNT0_UC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC14UL ) ) +#define portRTI_CNT0_CPUC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC18UL ) ) +#define portRTI_CNT0_COMP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC50UL ) ) +#define portRTI_CNT0_UDCP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC54UL ) ) +#define portRTI_SETINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC80UL ) ) +#define portRTI_CLEARINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC84UL ) ) +#define portRTI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFC88UL ) ) +#define portEND_OF_INTERRUPT_REG ( ( ( volatile uint32_t * ) configEOI_ADDRESS ) ) + + +/* Registers used by the Vectored Interrupt Manager */ +typedef void ( * ISRFunction_t )( void ); +#define portVIM_IRQ_INDEX ( *( ( volatile uint32_t * ) 0xFFFFFE00 ) ) +#define portVIM_IRQ_VEC_REG ( *( ( volatile ISRFunction_t * ) 0xFFFFFE70 ) ) + +#define portSSI_INT_REG_BASE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) + +#define portSSI_INT_REG_ONE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) +#define portSSI_ONE_KEY 0x7500UL + +#define portSSI_INT_REG_TWO ( ( ( volatile uint32_t * ) 0xFFFFFFB4 ) ) +#define portSSI_TWO_KEY 0x8400UL + +#define portSSI_INT_REG_THREE ( ( ( volatile uint32_t * ) 0xFFFFFFB8 ) ) +#define portSSI_THREE_KEY 0x9300UL + +#define portSSI_INT_REG_FOUR ( ( ( volatile uint32_t * ) 0xFFFFFFBC ) ) +#define portSSI_FOUR_KEY 0xA200UL + +#define portSSI_VEC_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF4 ) ) +#define portSSI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF8 ) ) + +/* --------------------------- Shared Function Deceleration --------------------------- */ + +/** @brief Function to toggle LEDs on the RM57-XL2 Launchpad + * @param ulLED Which LED to flicker + */ +void vToggleLED( uint32_t ulLED ); + +/* ----------------------------------------------------------------------------------- */ + +#endif /* DEMO_TASKS_H */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c new file mode 100644 index 00000000000..f097d9f8574 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c @@ -0,0 +1,244 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if ( mainDEMO_TYPE &IRQ_DEMO ) + +/** @brief TCB used by the IRQ Test Task. */ + static StaticTask_t xIRQTestTaskTCB; + +/** @brief Stack used by the IRQ Test Task. */ + + static StackType_t uxIRQTestTaskStack[ configMINIMAL_STACK_SIZE ]; + +/** @brief Parameters that are passed into the IRQ test task solely for + * the purpose of ensuring parameters are passed into tasks correctly. */ + #define irqTASK_PARAMETER ( 0xFEEDBEEFUL ) + +/** @brief Statically allocated task handle for the IRQ Test task. */ + static TaskHandle_t xIRQTaskHandle; + + volatile static uint32_t ulIntNestTestVal; +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the IRQ Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task raises Software Interrupts (SWI) in the form of IRQs using the + * Vectored Interrupt Manager (VIM) built into the RM57 by Texas Instrument (TI). + * It does this through use of the Software Interrupt Registers (SSIRs). + * More information about these can be found in the following document: + * https://www.ti.com/document-viewer/RM57L843/datasheet#system_information_and_electrical_specifications/SPNS1607150 + */ + static void prvIRQTestTask( void * pvParameters ) + { + /* Ensure that the correct parameter was passed to the task. */ + configASSERT( ( uint32_t ) pvParameters == irqTASK_PARAMETER ); + volatile uint32_t * xSoftwareInterruptRegister; + volatile TickType_t ulLoopCount; + volatile TickType_t xPreIRQTickCount; + + for( ; ; ) + { + sci_print( "IRQ Test Task Starting IRQ Nesting Test!\r\n" ); + ulIntNestTestVal = 0xFFFFUL; + + /* Get the tick count before raising the SWI */ + xPreIRQTickCount = xTaskGetTickCount(); + + /* Trigger an IRQ by writing to the SSI Register with a data value */ + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + *xSoftwareInterruptRegister = portSSI_FOUR_KEY | 0x44UL; + + /* When using a debugger IRQs can be paused/delayed. + * This loop exists to keep the compiler from optimizing it out + * while also giving the debugger time to trigger the IRQ. */ + ulLoopCount = xPreIRQTickCount; + + while( ( ulLoopCount + xPreIRQTickCount ) < ( xPreIRQTickCount + 0x20UL ) ) + { + if( 0xFFFFUL != ulIntNestTestVal ) + { + ulLoopCount++; + } + else + { + ulLoopCount = 0xFFFF0000UL; + } + } + + if( 0x4UL == ulIntNestTestVal ) + { + sci_print( "IRQ Test Task reported correct unwinding!\r\n" ); + vToggleLED( 0x1 ); + } + else + { + sci_print( "IRQ Test Task did not receive the correct nesting value!\r\n" ); + configASSERT( 0x0 ); + } + + sci_print( "IRQ Test Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times. */ + vTaskDelay( pdMS_TO_TICKS( 3150UL ) ); + } + } + +/* ----------------------------------------------------------------------------------- */ + + void vIRQDemoHandler( void ) + { + sci_print( "\tSWI Based IRQ was raised!\r\n" ); + volatile uint32_t ulSSIRegisterValue; + volatile uint32_t ulSSIIntFlagValue; + volatile uint32_t * xSoftwareInterruptRegister; + /* The 4 different SWI Registers use a bitfield to mark that they where raised. */ + { + /* Determine what channel raised the IRQ without clearing the interrupt. */ + ulSSIIntFlagValue = portSSI_INTFLAG_REG; + + if( 0x1UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x11UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #1 Raised with Data Value 0x11, clearing the " + "IRQs...\r\n" ); + /* Read to mark this IRQ as cleared. */ + /* Mark the Nested Channel 1 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x1101UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 2 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x2202UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 3 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x3303UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 4 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x4404UL == ulSSIIntFlagValue ); + + /* Should be no other IRQs raised, mask out the data. */ + ulSSIIntFlagValue = ( portSSI_VEC_REG ) & 0XFFUL; + configASSERT( 0x0UL == ulSSIIntFlagValue ); + } + } + + else if( 0x2UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x22UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #2 triggering nested Channel #1 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + *xSoftwareInterruptRegister = portSSI_ONE_KEY | 0x11UL; + __asm volatile ( "CPSIE I" ); + } + } + + else if( 0x4UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x33UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #3 triggering nested Channel #2 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + *xSoftwareInterruptRegister = portSSI_TWO_KEY | 0x22UL; + __asm volatile ( "CPSIE I" ); + } + } + + else /* if( 0x8UL & ulSSIIntFlagValue ) */ + { + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x44UL ) + { + ulIntNestTestVal = 0x1UL; + sci_print( "\t\tSWI Channel #4 triggering nested Channel #3 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + *xSoftwareInterruptRegister = portSSI_THREE_KEY | 0x33UL; + __asm volatile ( "CPSIE I" ); + } + } + } + } + +/* ----------------------------------------------------------------------------------- */ + + BaseType_t xCreateIRQTestTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* Create the IRQ check tasks, as described at the top of this file. */ + xIRQTaskHandle = xTaskCreateStatic( prvIRQTestTask, + "IRQTestTask", + configMINIMAL_STACK_SIZE, + ( void * ) irqTASK_PARAMETER, + ( configTIMER_TASK_PRIORITY + 0x2UL ), + uxIRQTestTaskStack, + &xIRQTestTaskTCB ); + + if( xIRQTaskHandle != NULL ) + { + sci_print( "Created the IRQ Test Task\r\n" ); + xReturn = pdPASS; + } + else + { + sci_print( "Failed to create the IRQ Test Task\r\n" ); + } + + ulIntNestTestVal = 0xFEEDBEEFUL; + return xReturn; + } +#endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/main.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/main.c new file mode 100644 index 00000000000..fcd4380cd38 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/main.c @@ -0,0 +1,466 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* ------------------------------------------------------------------------- */ + +/** + * @file main.c + * @brief File implementing RM57L843 specific functions + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "portmacro.h" +#include "task.h" +#include "timers.h" + +/* Standard includes. */ +#include +#include + +/* HalCoGen includes. */ +#include "system.h" +#include "gio.h" +#include "het.h" +#include "reg_vim.h" +#include "sci.h" +#include "sys_vim.h" +#include "system.h" + +/* Demo Tasks include */ +#include "demo_tasks.h" + +/* ----------------------- Microcontroller Registers ----------------------- */ + +/** @brief Configure the hardware to start the scheduler timer. */ +void vMainSetupTimerInterrupt( void ); + +/** @brief Set up necessary hardware registers. */ +static void prvSetupHardware( void ); + +/** @brief Landing point function for any failed configASSERT() check. + * @param pcFuncName The function that raised the assert. + * @param ulLine The line that the assert was called from. */ +void vAssertCalled( const char * pcFileName, + uint32_t ulLine ); + +void vApplicationIRQHandler( void ); +/* --------------------- Static Task Memory Allocation --------------------- */ + +/** @brief Statically declared TCB Used by the Idle Task. */ +static StaticTask_t xTimerTaskTCB; + +/** @brief Statically declared stack used by the timer task. */ +static StackType_t uxTimerTaskStack[ configMINIMAL_STACK_SIZE ]; + +/** @brief Statically declared TCB Used by the Idle Task. */ +static StaticTask_t xIdleTaskTCB; + +/** @brief Statically declared stack used by the idle task. */ +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + +/** @brief Simple variable to show how the idle tick hook can be used. */ +static volatile TickType_t ulIdleTickHookCount = 0x0; + +extern volatile uint32_t ulPortYieldRequired; + +/* ------------------------------------------------------------------------- */ + +int main( void ) +{ + UBaseType_t xReturn = pdPASS; + + ulIdleTickHookCount = 0x0; + prvSetupHardware(); + + sci_print( "\r\n---------------------------- Create FreeRTOS Tasks" + "----------------------------\r\n\r\n" ); + + #if ( mainDEMO_TYPE & REGISTER_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Register test tasks\r\n" ); + xReturn = xCreateRegisterTestTasks(); + } + } + #endif /* ( mainDEMO_TYPE & REGISTER_DEMO ) */ + + #if ( mainDEMO_TYPE & QUEUE_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Queue Demo Tasks\r\n" ); + xReturn = xCreateQueueTasks(); + } + } + #endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ + + #if ( mainDEMO_TYPE & IRQ_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the IRQ Demo Tasks\r\n" ); + xReturn = xCreateIRQTestTask(); + } + } + #endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ + + #if ( mainDEMO_TYPE & NOTIFICATION_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Notification Demo Tasks\r\n" ); + xReturn = xCreateNotificationTestTask(); + } + } + #endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ + + if( pdPASS == xReturn ) + { + sci_print( "\r\n--------------------------- Start of FreeRTOS Demo Tasks" + "---------------------------\r\n\r\n" ); + vTaskStartScheduler(); + } + else + { + sci_print( "Failed to create the Demo Tasks\r\n" ); + configASSERT( pdFAIL ); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was an error when creating the necessary FreeRTOS objects. */ + configASSERT( 0x0 ); + return 0; +} +/*---------------------------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + systemInit(); + gioInit(); + hetInit(); + sciInit(); + + /* Setup gioPORTB for when using the RM57 Launchpad. */ + gioPORTB->DIR |= ( 0x01 << 6 ); /*configure GIOB[6] as output. */ + gioPORTB->DIR |= ( 0x01 << 7 ); /*configure GIOB[7] as output. */ + + /* Configure HET as master, pull functionality, and switch on. */ + hetREG1->GCR = 0x01000001; + hetREG1->PULDIS = 0x00000000; + + /* Configure pins connected to LEDs NHET[0,2,4,5,25,16,17,18,20,27,29,31] + * as output. */ + hetREG1->DIR = 0xAA178035; + hetREG1->DOUT = 0x0; + + /* Enable notifications for the SCI register. */ + /* Use a BAUD rate of 115200, 1 stop bit, and None Parity. */ + sciEnableNotification( scilinREG, SCI_RX_INT ); +} + +/*---------------------------------------------------------------------------*/ + +void vToggleLED( uint32_t ulLEDNum ) +{ + uint32_t ulLEDVal; + uint32_t ulGIOVal; + + if( 0x0 == ulLEDNum ) + { + /* RM57 TMDX Dev Kit LED1 use NHET[27], Launchpad LED2 uses GIOB[6]. */ + ulLEDVal = 1UL << 27UL; + ulGIOVal = 1UL << 6UL; + } + else + { + /* RM57 TMDX Dev Kit LED2 use NHET[5], Launchpad LED3 uses GIOB[7]. */ + ulLEDVal = 1UL << 5UL; + ulGIOVal = 1UL << 7UL; + } + + if( ( hetREG1->DOUT & ulLEDVal ) == 0 ) + { + hetREG1->DOUT |= ulLEDVal; + gioPORTB->DOUT |= ulGIOVal; + } + else + { + hetREG1->DOUT &= ~ulLEDVal; + gioPORTB->DOUT &= ~ulGIOVal; + } +} + +/*---------------------------------------------------------------------------*/ + +void vMainSetupTimerInterrupt( void ) +{ + /* Disable timer 0. */ + portRTI_GCTRL_REG &= 0xFFFFFFFEUL; + + /* Use the internal counter. */ + portRTI_TBCTRL_REG = 0x00000000U; + + /* COMPSEL0 will use the RTIFRC0 counter. */ + portRTI_COMPCTRL_REG = 0x00000000U; + + /* Initialise the counter and the prescale counter registers. */ + portRTI_CNT0_UC0_REG = 0x00000000U; + portRTI_CNT0_FRC0_REG = 0x00000000U; + + /* Set Prescalar for RTI clock. */ + portRTI_CNT0_CPUC0_REG = 0x00000001U; + portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + + /* Clear interrupts. */ + portRTI_INTFLAG_REG = 0x0007000FU; + portRTI_CLEARINTENA_REG = 0x00070F0FU; + + /* Enable the compare 0 interrupt. */ + portRTI_SETINTENA_REG = 0x00000001U; + portRTI_GCTRL_REG |= 0x00000001U; +} + +/*---------------------------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the + * idle task. It is essential that code added to this hook function never + * attempts to block in any way (for example, call xQueueReceive() with a + * block time specified, or call vTaskDelay()). If application tasks make + * use of the vTaskDelete() API function to delete themselves then it is + * also important that vApplicationIdleHook() is permitted to return to its + * calling function, because it is the responsibility of the idle task to + * clean up memory allocated by the kernel to any task that has since + * deleted itself. */ + ulIdleTickHookCount++; + + if( ( TickType_t ) 0xF00000 == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xF0 0000 times!\r\n" ); + } + + else if( ( TickType_t ) 0xFFFFFFFF == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xFFFFFFFF times! " + "Setting it to 0x0!\r\n" ); + ulIdleTickHookCount = 0x0; + } +} + +/*---------------------------------------------------------------------------*/ + +void vAssertCalled( const char * pcFuncName, + uint32_t ulLine ) +{ + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + volatile const char * callingFunc = pcFuncName; + volatile uint32_t callingLine = ulLine; + + /* These variables can be inspected in a debugger. */ + if( callingFunc != ( char * ) callingLine ) + { + __asm volatile ( "NOP" ); + } + + taskENTER_CRITICAL(); + { + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + } + } + taskEXIT_CRITICAL(); +} + +/*---------------------------------------------------------------------------*/ + +/** @brief Default IRQ Handler used in the ARM_Cortex_RX ports. + * @note This Handler is directly tied to the Texas Instrument's Hercules + * Vectored Interrupt Manager (VIM). For more information about what + * this is and how it operates please refer to their document: + * https://www.ti.com/lit/pdf/spna218 + */ +void vApplicationIRQHandler( void ) +{ + /* Load the IRQ Channel Number and Function PTR from the VIM. */ + volatile uint32_t ulIRQChannelIndex = portVIM_IRQ_INDEX; + volatile ISRFunction_t xIRQFncPtr = portVIM_IRQ_VEC_REG; + + /* Setup Bit Mask Clear Values. */ + volatile uint32_t ulPendingIRQMask; + + volatile uint32_t ulPendISRReg0 = vimREG->REQMASKCLR0; + volatile uint32_t ulPendISRReg1 = vimREG->REQMASKCLR1; + volatile uint32_t ulPendISRReg2 = vimREG->REQMASKCLR2; + volatile uint32_t ulPendISRReg3 = vimREG->REQMASKCLR3; + + if( NULL == xIRQFncPtr ) + { + sci_print( "Received a NULL Function Pointer from the IRQ VIM\r\n" ); + configASSERT( pdFALSE ); + } + else + { + if( 0U != ulIRQChannelIndex ) + { + ulIRQChannelIndex--; + } + + if( ulIRQChannelIndex <= 31U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ulIRQChannelIndex; + vimREG->REQMASKCLR0 = ulPendingIRQMask; + vimREG->REQMASKCLR1 = 0xFFFFFFFFU; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 63U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 32U ); + vimREG->REQMASKCLR1 = ulPendingIRQMask; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 95U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 64U ); + vimREG->REQMASKCLR2 = ulPendingIRQMask; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 96U ); + vimREG->REQMASKCLR3 = ulPendingIRQMask; + } + } + + /* + * Channel 0 is the ESM handler, treat this as a special case. + * phantomInterrupt() + * Keep interrupts disabled, this function does not return. + */ + + if( 0UL == ulIRQChannelIndex ) + { + sci_print( "Phantom interrupt?\r\n" ); + configASSERT( pdFALSE ); + ( *xIRQFncPtr )(); + } + else if( ( phantomInterrupt == xIRQFncPtr ) ) + { + sci_print( "IRQ With no registered function in sys_vim.c has been raised\r\n" ); + configASSERT( pdFALSE ); + } + else + { + /* Information about the mapping of Interrupts in the VIM to their + * causes can be found in the RM57L843 Data Sheet: + * https://www.ti.com/document-viewer/RM57L843/datasheet#system_information_and_electrical_specifications/SPNS1607150 */ + /* An IRQ Raised by Channel Two of the VIM is RTI Compare Interrupt 0. */ + if( 2UL == ulIRQChannelIndex ) + { + /* This is the System Tick Timer Interrupt. */ + ulPortYieldRequired = xTaskIncrementTick(); + /* Acknowledge the System Tick Timer Interrupt. */ + portRTI_INTFLAG_REG = 0x1UL; + } + /* An IRQ Raised by Channel 21 of the VIM is a Software Interrupt (SSI). */ + else if( 21UL == ulIRQChannelIndex ) + { + #if ( mainDEMO_TYPE &IRQ_DEMO ) + /* This is an interrupt raised by Software. */ + vIRQDemoHandler(); + #else + sci_print( "SWI of unknown cause was raised!\r\n" ); + configASSERT( 0x0 ); + #endif + + /* Register read is needed to mark the end of the IRQ. */ + volatile uint32_t ulEndOfIntRegVal = *portEND_OF_INTERRUPT_REG; + *portEND_OF_INTERRUPT_REG = ulEndOfIntRegVal; + } + else + { + sci_print( "Unmapped IRQ Channel Number Raised\r\n" ); + } + } + + vimREG->REQMASKSET0 = ulPendISRReg0; + vimREG->REQMASKSET1 = ulPendISRReg1; + vimREG->REQMASKSET2 = ulPendISRReg2; + vimREG->REQMASKSET3 = ulPendISRReg3; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c new file mode 100644 index 00000000000..43f2070615d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c @@ -0,0 +1,203 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if ( mainDEMO_TYPE & NOTIFICATION_DEMO ) + + /** @brief Parameters that are passed into the notification test task solely + * for the purpose of ensuring parameters are passed into tasks correctly. */ + #define notificationTASK_PARAMETER ( 0xFEEDBEEFUL ) + + /** @brief Value sent back and forth between the tasks. */ + #define notificationTEST_VALUE 0x1234UL + + /** @brief TCB used by the Notification Test Task. */ + static StaticTask_t xNotificationTestTaskTCB; + + /** @brief Stack used by the Notification Test Task. */ + static StackType_t uxNotificationTestTaskStack[ configMINIMAL_STACK_SIZE ]; + + /** @brief Statically allocated task handle for the Notification Test task. */ + static TaskHandle_t xNotificationTaskOneHandle; + +/* ----------------------------------------------------------------------------------- */ + + static void prvNotifyCheck( BaseType_t ulRetVal ) + { + if( pdPASS == ulRetVal ) + { + sci_print( "Notification API Returned a passing value!\r\n" ); + } + else + { + sci_print( "Notification API did not return pdPASS.\r\n" ); + configASSERT( ulRetVal ); + } + } + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Notification Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly + * set. + * @note This task sends itself and another task notifications using the + * cross-task notification APIs. + */ + static void prvNotificationTestTask( void * pvParameters ) + { + BaseType_t xReturned; + UBaseType_t ulNotificationValue; + + /* Ensure that the correct parameter was passed to the task. */ + configASSERT( ( uint32_t ) pvParameters == notificationTEST_VALUE ); + + for( ; ; ) + { + /* Clear the notification value each loop. */ + ulNotificationValue = 0x0UL; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0x0UL, 0x0UL, + &ulNotificationValue, 0x0UL ); + configASSERT( pdFAIL == xReturned ); + configASSERT( 0x0UL == ulNotificationValue ); + + /* Tell the task to notify itself twice. */ + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + /* Perform a non-blocking notification read, should see two "gives". */ + ulNotificationValue = ulTaskNotifyTake( pdTRUE, 0x0 ); + + /* Two notifications have been sent to this task by itself. */ + configASSERT( 0x2UL == ulNotificationValue ); + sci_print( "Notification Task correctly sent itself two" + "notifications!\r\n" ); + + /* Now make the task send itself a notification with a value. */ + xReturned = xTaskNotify( xTaskGetCurrentTaskHandle(), + notificationTEST_VALUE, + eSetValueWithOverwrite ); + prvNotifyCheck( xReturned ); + + /* Clear ulNotificationValue before using it. */ + ulNotificationValue = 0x0UL; + + /* Receive the value sent using xTaskNotify. */ + xReturned = xTaskNotifyWait( 0, + ( uint32_t ) 0xFFFFFFFFUL, + &ulNotificationValue, + ( TickType_t ) 0x50UL ); + prvNotifyCheck( xReturned ); + + if( notificationTEST_VALUE == ulNotificationValue ) + { + sci_print( "Notification Task got the expected value!\r\n" ); + } + else + { + sci_print( "Notification Task did NOT get the expected" + "value!\r\n" ); + configASSERT( 0x0UL ); + } + + /* Reset the variable before using it. */ + ulNotificationValue = 0x0UL; + + /* There should be no value to receive this time. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, + ( TickType_t ) 0x0UL ); + + if( ( pdPASS == xReturned ) || ( 0x0 != ulNotificationValue ) ) + { + sci_print( "Notification Task received a value when there" + "should have been none" ); + configASSERT( 0x0UL ); + } + + xTaskNotify( xTaskGetCurrentTaskHandle(), + ulNotificationValue, + eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* First time a notification was pending. */ + configASSERT( xReturned == pdTRUE ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* Second time the notification was already clear. */ + configASSERT( xReturned == pdFALSE ); + + sci_print( "Notification Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times. */ + vTaskDelay( pdMS_TO_TICKS( 2750UL ) ); + } + } + +/* ----------------------------------------------------------------------------------- */ + + BaseType_t xCreateNotificationTestTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* Create the notification test task. */ + xNotificationTaskOneHandle = xTaskCreateStatic( prvNotificationTestTask, + "NotificationTestTask", + configMINIMAL_STACK_SIZE, + ( void * ) notificationTEST_VALUE, + demoNOTIFICATION_TASK_PRIORITY, + uxNotificationTestTaskStack, + &xNotificationTestTaskTCB ); + + if( xNotificationTaskOneHandle != NULL ) + { + sci_print( "Created the Notification Test Task\r\n" ); + xReturn = pdPASS; + } + else + { + sci_print( "Failed to create the Notification Test Task\r\n" ); + } + + return xReturn; + } +#endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c new file mode 100644 index 00000000000..00233d01ab1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c @@ -0,0 +1,355 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file queue_demo.c + * @brief Use the Queue APIs to send data from a sender task to a receiver task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" + +/* Board Support Package Includes. */ +#include "sci.h" +#include "reg_system.h" + +/* Demo Specific Includes. */ +#include "demo_tasks.h" + +#if ( mainDEMO_TYPE & QUEUE_DEMO ) + + /* ------------------------------ Demo Task Configs --------------------*/ + + /** @brief The rate at which data is sent to the queue from the send task. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) + + /** @brief The rate at which data is sent to the queue from the timer. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + + /** @brief The number of items the queue can hold at once. */ + #define queueQUEUE_LENGTH ( 2 ) + + /** @brief Value sent from the send task to the receive task. */ + #define queueVALUE_SENT_FROM_TASK ( 0x1234UL ) + + /** @brief Value sent from the timer to the receive task. */ + #define queueVALUE_SENT_FROM_TIMER ( 0x4321UL ) + +/* --------------------- Task Function Declaration --------------------- */ + +/** @brief Function run by the task that receives data from the queue. + * @note + * The queue receive task is implemented by the prvQueueReceiveTask() + * function in this file. prvQueueReceiveTask() waits for data to arrive on + * the queue. When data is received, the task checks the value of the data, + * then outputs a message to indicate if the data came from the queue send + * task or the queue send software timer. */ + static void prvQueueReceiveTask( void * pvParameters ); + +/** @brief Function run by the task that sends data to a queue. + * @note + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It uses vTaskDelayUntil() to create a periodic task that + * sends queueVALUE_SENT_FROM_TASK to the queue every 200 milliseconds. */ + static void prvQueueSendTask( void * pvParameters ); + +/** @brief The callback function executed when the timer expires. + * @note + * The timer is an auto-reload timer with a period of two seconds. Its + * callback function sends the value queueVALUE_SENT_FROM_TIMER to the + * queue. The callback function is implemented by prvQueueSendTimerCallback(). + */ + static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); + +/*-------------------- Static Task Memory Allocation ------------------- */ + +/** @brief Statically allocated Queue object. */ + static StaticQueue_t xStaticQueue; + +/** @brief Statically allocated Storage for the Queue. */ + static uint8_t xQueueStorage[ 0x20 ]; + +/** @brief Statically allocated QueueHandle. */ + static QueueHandle_t xQueue; + +/* Each task needs to know the other tasks' handle so they can send signals to + * each other. The handle is obtained from the task's name. */ + +/** @brief Task name for the queue send task. */ + static const char * pcSendTaskName = "SendTaskName"; + +/** @brief Task name for the queue receive task. */ + static const char * pcReceiveTaskName = "ReceiveTaskName"; + +/** @brief Statically allocated stack used by the Queue Send Task. */ + static StackType_t xQueueSendTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/** @brief Static TCB Used by the Queue Send Task. */ + static StaticTask_t xQueueSendTaskTCB; + +/** @brief Statically allocated stack used by the Queue Receive Task. */ + static StackType_t xQueueReceiveTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/** @brief Static TCB Used by the Queue Receive Task. */ + static StaticTask_t xQueueReceiveTaskTCB; + +/** @brief A software timer that is started from the tick hook. */ + static TimerHandle_t xTimer = NULL; + +/** @brief Statically allocated timer object. */ + static StaticTimer_t xStaticTimer; + +/** @brief Statically allocated task handle for the queue receive task. */ + static TaskHandle_t xReceiveTaskHandle; + +/** @brief Statically allocated task handle for the queue send task. */ + static TaskHandle_t xSendTaskHandle; + +/* ------------------------------------------------------------------------------------ */ + + BaseType_t prvCreateQueueTasks( void ) + { + BaseType_t xReturn = pdPASS; + + xReceiveTaskHandle = xTaskCreateStatic( prvQueueReceiveTask, + pcReceiveTaskName, + configMINIMAL_STACK_SIZE / 2U, + NULL, + demoQUEUE_RECEIVE_TASK_PRIORITY, + xQueueReceiveTaskStack, + &xQueueReceiveTaskTCB ); + + if( xReceiveTaskHandle != NULL ) + { + sci_print( "Created the Queue Receive Task\r\n" ); + + xSendTaskHandle = xTaskCreateStatic( prvQueueSendTask, + pcSendTaskName, + configMINIMAL_STACK_SIZE / 2U, + NULL, + demoQUEUE_SEND_TASK_PRIORITY, + xQueueSendTaskStack, + &xQueueSendTaskTCB ); + + if( xSendTaskHandle != NULL ) + { + sci_print( "Created the Queue Send Task\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + + return xReturn; + } + +/* ------------------------------------------------------------------------------------ */ + + BaseType_t xCreateQueueTasks( void ) + { + BaseType_t xReturn = pdPASS; + + /* The Receive Task MUST be a higher priority than the send task. */ + configASSERT( demoQUEUE_RECEIVE_TASK_PRIORITY > demoQUEUE_SEND_TASK_PRIORITY ); + + /* Create the queue used by the queue tasks . */ + xQueue = xQueueCreateStatic( queueQUEUE_LENGTH, + sizeof( uint32_t ), + xQueueStorage, + &xStaticQueue ); + + if( xQueue != NULL ) + { + sci_print( "Created the Queue for the tasks\r\n" ); + + /** @brief The debugging text name for the timer. */ + const char * pcTimerName = "Timer"; + /** @brief Mark that this is an auto-reload timer. */ + const BaseType_t xAutoReload = ( BaseType_t ) pdTRUE; + /** @brief Timer ID that is not used in this demo. */ + void * const pvTimerID = NULL; + /** @brief Callback function for the timer. */ + TimerCallbackFunction_t pxCallbackFunction = prvQueueSendTimerCallback; + + /* Create a statically allocated timer. */ + xTimer = xTimerCreateStatic( pcTimerName, + ( const TickType_t ) queueTIMER_SEND_FREQUENCY_MS, + xAutoReload, + pvTimerID, + pxCallbackFunction, + &( xStaticTimer ) ); + } + else + { + sci_print( "Failed to create the Queue for the tasks\r\n" ); + xReturn = pdFAIL; + } + + if( NULL != xTimer ) + { + sci_print( "Created the Queue Timer\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Timer\r\n" ); + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + xReturn = prvCreateQueueTasks(); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + /* The scheduler has not started so use a block time of 0. */ + xReturn = xTimerStart( xTimer, 0 ); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + sci_print( "Started the Timer\r\n" ); + } + else + { + sci_print( "Failed to start the Queue Timer\r\n" ); + } + + return xReturn; + } + +/*-----------------------------------------------------------------------*/ + + static void prvQueueSendTask( void * pvParameters ) + { + TickType_t xNextWakeTime; + const TickType_t xBlockTime = queueTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TASK; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Move this task to the blocked state for xBlockTime milliseconds. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in + * ticks. While in the Blocked state this task will not consume any + * CPU time. */ + xTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock + * and write to the console. 0 is used as the block time so the send + * operation will not block. It shouldn't need to block as the queue + * should always have at least one space at this point in the code. + */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } + } + +/*-----------------------------------------------------------------------*/ + + static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) + { + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TIMER; + + /* This is the software timer callback function. The software timer has + * a period of two seconds. This callback function will execute if the + * timer expires, which will happen every two seconds. */ + + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; + + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon + * task, so must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } + +/*-----------------------------------------------------------------------*/ + + static void prvQueueReceiveTask( void * pvParameters ) + { + uint32_t ulReceivedValue = 0; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, + * but is it an expected value? */ + if( ulReceivedValue == queueVALUE_SENT_FROM_TASK ) + { + vToggleLED( 0x0 ); + } + else if( ulReceivedValue == queueVALUE_SENT_FROM_TIMER ) + { + vToggleLED( 0x1 ); + } + else + { + /* Invalid value received. Force an assert. */ + configASSERT( ulReceivedValue == !ulReceivedValue ); + } + } + } +/* --------------------------------------------------------------------- */ + +#endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c new file mode 100644 index 00000000000..e8735978cfa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c @@ -0,0 +1,176 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +/* ----------------------------------------------------------------------------------- */ + +/** @brief TCB used by Register Test Task One. */ +static StaticTask_t xRegTestOneTaskTCB; + +/** @brief Stack used by Register Test Task One. */ +static StackType_t uxRegTestOneTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/** @brief TCB used by Register Test Two Task. */ +static StaticTask_t xRegTestTwoTaskTCB; + +/** @brief Stack used by Register Test Task Two. */ +static StackType_t uxRegTestTwoTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/* Parameters that are passed into the register check tasks solely for the + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Array to track the number of loops the register test tasks have run. + * + * Register Test One will use loopCount[0]; + * Register Test Two Will use loopCount[1]; + */ +uint32_t loopCounter[ 0x8 ]; + +/** @brief Statically allocated task handle for the first register task. */ +static TaskHandle_t xRegisterTaskOneHandle; + +/** @brief Statically allocated task handle for the second register task. */ +static TaskHandle_t xRegisterTaskTwoHandle; + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Register Test 1 Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry1( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + else + { + /** The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Register Test 2 Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry2( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + else + { + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateRegisterTestTasks( void ) +{ + BaseType_t xReturn = pdFAIL; + + /* Create the register check tasks, as described at the top of this file. */ + + /* Create the first register test task. */ + xRegisterTaskOneHandle = xTaskCreateStatic( prvRegTestTaskEntry1, + "RegTestOne", + configMINIMAL_STACK_SIZE / 0x2, + mainREG_TEST_TASK_1_PARAMETER, + demoREG_TASK_1_PRIORITY, + uxRegTestOneTaskStack, + &xRegTestOneTaskTCB ); + + if( xRegisterTaskOneHandle != NULL ) + { + sci_print( "Created the Register Test 1 Task\r\n" ); + + /* Create the second register test task. */ + xRegisterTaskTwoHandle = xTaskCreateStatic( prvRegTestTaskEntry2, + "RegTestTwo", + configMINIMAL_STACK_SIZE / 0x2, + mainREG_TEST_TASK_2_PARAMETER, + demoREG_TASK_2_PRIORITY, + uxRegTestTwoTaskStack, + &xRegTestTwoTaskTCB ); + + if( xRegisterTaskTwoHandle != NULL ) + { + sci_print( "Created the Register Test 2 Task\r\n" ); + xReturn = pdPASS; + } + else + { + sci_print( "Failed to create the Register Test 2 Task\r\n" ); + } + } + else + { + sci_print( "Failed to create the Register Test 1 Task\r\n" ); + } + + return xReturn; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S new file mode 100644 index 00000000000..56684d893e0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S @@ -0,0 +1,443 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#define FREERTOS_ASSEMBLY + #include "FreeRTOSConfig.h" +#undef FREERTOS_ASSEMBLY + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern vPortYield + .extern + .extern loopCounter + .text + .arm + +/*-----------------------------------------------------------*/ + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + MOV R0, #0xFF + MOV R1, #0x11 + MOV R2, #0x22 + MOV R3, #0x33 + MOV R4, #0x44 + MOV R5, #0x55 + MOV R6, #0x66 + MOV R7, #0x77 + MOV R8, #0x88 + MOV R9, #0x99 + MOV R10, #0xAA + MOV R11, #0xBB + MOV R12, #0xCC + MOV R14, #0xEE + + /* Fill each FPU register with a known value. */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg1_loop: + /* Perform a yield to increase test coverage */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B reg1_error_loopf + B 0xDEACFC + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + CMP R0, #0xFF + BLNE reg1_error_loop + CMP R1, #0x11 + BLNE reg1_error_loop + CMP R2, #0x22 + BLNE reg1_error_loop + CMP R3, #0x33 + BLNE reg1_error_loop + CMP R4, #0x44 + BLNE reg1_error_loop + CMP R5, #0x55 + BLNE reg1_error_loop + CMP R6, #0x66 + BLNE reg1_error_loop + CMP R7, #0x77 + BLNE reg1_error_loop + CMP R8, #0x88 + BLNE reg1_error_loop + CMP R9, #0x99 + BLNE reg1_error_loop + CMP R10, #0xAA + BLNE reg1_error_loop + CMP R11, #0xBB + BLNE reg1_error_loop + CMP R12, #0xCC + BLNE reg1_error_loop + CMP R14, #0xEE + BLNE reg1_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0] + ADD R1, R1, #1 + STR R1, [R0] + POP { R0-R1 } + + /* Delay for 0x100 ticks before running again */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x100 + LDR R1, =vTaskDelay + BLX R1 + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B reg1_error_loop + NOP + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + MOV R0, #0xFF000000 + MOV R1, #0x11000000 + MOV R2, #0x22000000 + MOV R3, #0x33000000 + MOV R4, #0x44000000 + MOV R5, #0x55000000 + MOV R6, #0x66000000 + MOV R7, #0x77000000 + MOV R8, #0x88000000 + MOV R9, #0x99000000 + MOV R10, #0xAA000000 + MOV R11, #0xBB000000 + MOV R12, #0xCC000000 + MOV R14, #0xEE000000 + + /* Likewise the floating point registers. */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg2_loop: + + /* Yield to increase test coverage. */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B reg2_error_loopf + +reg2_loopf_pass: + + CMP R0, #0xFF000000 + BLNE reg2_error_loop + CMP R1, #0x11000000 + BLNE reg2_error_loop + CMP R2, #0x22000000 + BLNE reg2_error_loop + CMP R3, #0x33000000 + BLNE reg2_error_loop + CMP R4, #0x44000000 + BLNE reg2_error_loop + CMP R5, #0x55000000 + BLNE reg2_error_loop + CMP R6, #0x66000000 + BLNE reg2_error_loop + CMP R7, #0x77000000 + BLNE reg2_error_loop + CMP R8, #0x88000000 + BLNE reg2_error_loop + CMP R9, #0x99000000 + BLNE reg2_error_loop + CMP R10, #0xAA000000 + BLNE reg2_error_loop + CMP R11, #0xBB000000 + BLNE reg2_error_loop + CMP R12, #0xCC000000 + BLNE reg2_error_loop + CMP R14, #0xEE000000 + BLNE reg2_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0, #+0x4] + ADD R1, R1, #1 + STR R1, [R0, #+0x4] + POP { R0-R1 } + + /* Delay for 0x200 ticks before running again. */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x200 + BLX vTaskDelay + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B reg2_error_loop + NOP + +/* End of file. */ +.end + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml new file mode 100644 index 00000000000..6b3299f439d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt new file mode 100644 index 00000000000..d783fef4d6a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c index ecf1e4199a2..80b165448bb 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h index 92833b4c55f..3ae14056162 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c index d7bf163d60a..32aaa3b755a 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c index 22bfce1d69c..518692f630e 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c index c96fbd6aaff..d0200529d1e 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c index 556af543e00..5bbb7d4f436 100644 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject index 893e3e02fd4..18814d8ff8c 100644 --- a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject +++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject @@ -1,13 +1,13 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject index 006536a7071..e16a858aad6 100644 --- a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject +++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject @@ -15,74 +15,78 @@ - - - - - @@ -103,73 +107,77 @@ - - - - - @@ -190,73 +198,77 @@ - - - - - - + diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h index 75ccb0ca822..6089c6f552a 100644 --- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c index 4ccc982f989..75355fa541f 100644 --- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c index 55a85f37161..886b48d3148 100644 --- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c +++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c index 42cf825cdaa..8fe59d4cb81 100644 --- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c +++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h index e44cc1c825d..21a2938648c 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile index e4d8ca95800..25dc920b6a1 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile @@ -9,9 +9,19 @@ LD = riscv64-unknown-elf-gcc SIZE = riscv64-unknown-elf-size MAKE = make -CFLAGS += $(INCLUDE_DIRS) -DportasmHANDLE_INTERRUPT=handle_trap -fmessage-length=0 \ - -march=rv32imac_zicsr -mabi=ilp32 -mcmodel=medlow -ffunction-sections -fdata-sections \ +# Generate GCC_VERSION in number format +GCC_VERSION = $(shell $(CC) --version | grep ^$(CC) | sed 's/^.* //g' | awk -F. '{ printf("%d%02d%02d"), $$1, $$2, $$3 }') +GCC_VERSION_NEED_ZICSR = "110100" + +CFLAGS += $(INCLUDE_DIRS) -fmessage-length=0 \ + -mabi=ilp32 -mcmodel=medlow -ffunction-sections -fdata-sections \ -Wno-unused-parameter -nostartfiles -g3 -Os + +ifeq ($(shell test $(GCC_VERSION) -ge $(GCC_VERSION_NEED_ZICSR) && echo true),true) + CFLAGS += -march=rv32imac_zicsr +else + CFLAGS += -march=rv32imac +endif ifeq ($(PICOLIBC),1) CFLAGS += --specs=picolibc.specs -DPICOLIBC_INTEGER_PRINTF_SCANF diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c index fdfb58efb0c..1eac0409575 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -56,40 +56,40 @@ #include /* This project provides two demo applications. A simple blinky style demo -application, and a more comprehensive test and demo application. The -mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. - -If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built. -The blinky demo is implemented and described in main_blinky.c. - -If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and -demo application will be built. The comprehensive test and demo application is -implemented and described in main_full.c. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * application, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. + * + * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built. + * The blinky demo is implemented and described in main_blinky.c. + * + * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and + * demo application will be built. The comprehensive test and demo application is + * implemented and described in main_full.c. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /* Set to 1 to use direct mode and set to 0 to use vectored mode. -VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the -vector base address (BASE) in the mtvec register. -VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the -pc to be set to the BASE, whereas interrupts cause the pc to be set to the -address BASE plus four times the interrupt cause number. -*/ -#define mainVECTOR_MODE_DIRECT 0 + * VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the + * vector base address (BASE) in the mtvec register. + * VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the + * pc to be set to the BASE, whereas interrupts cause the pc to be set to the + * address BASE plus four times the interrupt cause number. + */ +#define mainVECTOR_MODE_DIRECT 0 /* printf() output uses the UART. These constants define the addresses of the -required UART registers. */ -#define UART0_ADDRESS ( 0x40004000UL ) -#define UART0_DATA ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 0UL ) ) ) ) -#define UART0_STATE ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 4UL ) ) ) ) -#define UART0_CTRL ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 8UL ) ) ) ) -#define UART0_BAUDDIV ( * ( ( ( volatile uint32_t * )( UART0_ADDRESS + 16UL ) ) ) ) -#define TX_BUFFER_MASK ( 1UL ) + * required UART registers. */ +#define UART0_ADDRESS ( 0x40004000UL ) +#define UART0_DATA ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 0UL ) ) ) ) +#define UART0_STATE ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 4UL ) ) ) ) +#define UART0_CTRL ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 8UL ) ) ) ) +#define UART0_BAUDDIV ( *( ( ( volatile uint32_t * ) ( UART0_ADDRESS + 16UL ) ) ) ) +#define TX_BUFFER_MASK ( 1UL ) /* Registers used to initialise the PLIC. */ -#define mainPLIC_PENDING_0 ( * ( ( volatile uint32_t * ) 0x0C001000UL ) ) -#define mainPLIC_PENDING_1 ( * ( ( volatile uint32_t * ) 0x0C001004UL ) ) -#define mainPLIC_ENABLE_0 ( * ( ( volatile uint32_t * ) 0x0C002000UL ) ) -#define mainPLIC_ENABLE_1 ( * ( ( volatile uint32_t * ) 0x0C002004UL ) ) +#define mainPLIC_PENDING_0 ( *( ( volatile uint32_t * ) 0x0C001000UL ) ) +#define mainPLIC_PENDING_1 ( *( ( volatile uint32_t * ) 0x0C001004UL ) ) +#define mainPLIC_ENABLE_0 ( *( ( volatile uint32_t * ) 0x0C002000UL ) ) +#define mainPLIC_ENABLE_1 ( *( ( volatile uint32_t * ) 0x0C002004UL ) ) extern void freertos_risc_v_trap_handler( void ); extern void freertos_vector_table( void ); @@ -112,213 +112,231 @@ void vFullDemoIdleFunction( void ); void main( void ) { - /* See https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html for - instructions. */ - - #if( mainVECTOR_MODE_DIRECT == 1 ) - { - __asm__ volatile( "csrw mtvec, %0" :: "r"( freertos_risc_v_trap_handler ) ); - } - #else - { - __asm__ volatile( "csrw mtvec, %0" :: "r"( ( uintptr_t )freertos_vector_table | 0x1 ) ); - } - #endif - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif + /* See https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html for + * instructions. */ + + #if ( mainVECTOR_MODE_DIRECT == 1 ) + { + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( freertos_risc_v_trap_handler ) ); + } + #else + { + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( ( uintptr_t ) freertos_vector_table | 0x1 ) ); + } + #endif + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created using the dynamic allocation (as opposed to - static allocation) option. It is also called by various parts of the - demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the - size of the heap available to pvPortMalloc() is defined by - configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() - API function can be used to query the size of free heap space that remains - (although it does not provide information on how the remaining heap might be - fragmented). See http://www.freertos.org/a00111.html for more - information. */ - printf( "\r\n\r\nMalloc failed\r\n" ); - portDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created using the dynamic allocation (as opposed to + * static allocation) option. It is also called by various parts of the + * demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the + * size of the heap available to pvPortMalloc() is defined by + * configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() + * API function can be used to query the size of free heap space that remains + * (although it does not provide information on how the remaining heap might be + * fragmented). See http://www.freertos.org/a00111.html for more + * information. */ + printf( "\r\n\r\nMalloc failed\r\n" ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If application tasks make use of the - vTaskDelete() API function to delete themselves then it is also important - that vApplicationIdleHook() is permitted to return to its calling function, - because it is the responsibility of the idle task to clean up memory - allocated by the kernel to any task that has since deleted itself. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If application tasks make use of the + * vTaskDelete() API function to delete themselves then it is also important + * that vApplicationIdleHook() is permitted to return to its calling function, + * because it is the responsibility of the idle task to clean up memory + * allocated by the kernel to any task that has since deleted itself. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - printf( "\r\n\r\nStack overflow in %s\r\n", pcTaskName ); - portDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + printf( "\r\n\r\nStack overflow in %s\r\n", pcTaskName ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - extern void vFullDemoTickHookFunction( void ); - - vFullDemoTickHookFunction(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ + + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + { + extern void vFullDemoTickHookFunction( void ); + + vFullDemoTickHookFunction(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ } /*-----------------------------------------------------------*/ void vApplicationDaemonTaskStartupHook( void ) { - /* This function will be called once only, when the daemon task starts to - execute (sometimes called the timer task). This is useful if the - application includes initialisation code that would benefit from executing - after the scheduler has been started. */ + /* This function will be called once only, when the daemon task starts to + * execute (sometimes called the timer task). This is useful if the + * application includes initialisation code that would benefit from executing + * after the scheduler has been started. */ } /*-----------------------------------------------------------*/ -void vAssertCalled( const char *pcFileName, uint32_t ulLine ) +void vAssertCalled( const char * pcFileName, + uint32_t ulLine ) { -volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; - - /* Called if an assertion passed to configASSERT() fails. See - http://www.freertos.org/a00110.html#configASSERT for more information. */ - - printf( "ASSERT! Line %d, file %s\r\n", ( int ) ulLine, pcFileName ); - - taskENTER_CRITICAL(); - { - /* You can step out of this function to debug the assertion by using - the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero - value. */ - while( ulSetToNonZeroInDebuggerToContinue == 0 ) - { - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - } - } - taskEXIT_CRITICAL(); + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + + printf( "ASSERT! Line %d, file %s\r\n", ( int ) ulLine, pcFileName ); + + taskENTER_CRITICAL(); + { + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + } + } + taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; } /*-----------------------------------------------------------*/ /* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) { /* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ -int __write( int iFile, char *pcString, int iStringLength ) +int __write( int iFile, + char * pcString, + int iStringLength ) { - int iNextChar; + int iNextChar; + + /* Avoid compiler warnings about unused parameters. */ + ( void ) iFile; - /* Avoid compiler warnings about unused parameters. */ - ( void ) iFile; + /* Output the formatted string to the UART. */ + for( iNextChar = 0; iNextChar < iStringLength; iNextChar++ ) + { + while( ( UART0_STATE & TX_BUFFER_MASK ) != 0 ) + { + } - /* Output the formatted string to the UART. */ - for( iNextChar = 0; iNextChar < iStringLength; iNextChar++ ) - { - while( ( UART0_STATE & TX_BUFFER_MASK ) != 0 ); - UART0_DATA = *pcString; - pcString++; - } + UART0_DATA = *pcString; + pcString++; + } - return iStringLength; + return iStringLength; } /*-----------------------------------------------------------*/ -void *malloc( size_t size ) +void * malloc( size_t size ) { - ( void ) size; + ( void ) size; - /* This project uses heap_4 so doesn't set up a heap for use by the C - library - but something is calling the C library malloc(). See - https://freertos.org/a00111.html for more information. */ - printf( "\r\n\r\nUnexpected call to malloc() - should be using pvPortMalloc()\r\n" ); - portDISABLE_INTERRUPTS(); - for( ;; ); + /* This project uses heap_4 so doesn't set up a heap for use by the C + * library - but something is calling the C library malloc(). See + * https://freertos.org/a00111.html for more information. */ + printf( "\r\n\r\nUnexpected call to malloc() - should be using pvPortMalloc()\r\n" ); + portDISABLE_INTERRUPTS(); + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_blinky.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_blinky.c index 27d0d2a293d..7fcc3b8050c 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_blinky.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -66,29 +66,29 @@ #include "queue.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The times are converted from -milliseconds to ticks using the pdMS_TO_TICKS() macro. */ -#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) -#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + * milliseconds to ticks using the pdMS_TO_TICKS() macro. */ +#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) +#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) /* The number of items the queue can hold at once. */ -#define mainQUEUE_LENGTH ( 2 ) +#define mainQUEUE_LENGTH ( 2 ) /* The values sent to the queue receive task from the queue send task and the -queue send software timer respectively. */ -#define mainVALUE_SENT_FROM_TASK ( 100UL ) -#define mainVALUE_SENT_FROM_TIMER ( 200UL ) + * queue send software timer respectively. */ +#define mainVALUE_SENT_FROM_TASK ( 100UL ) +#define mainVALUE_SENT_FROM_TIMER ( 200UL ) /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * The callback function executed when the software timer expires. @@ -108,128 +108,128 @@ static TimerHandle_t xTimer = NULL; /*** SEE THE COMMENTS AT THE TOP OF THIS FILE ***/ void main_blinky( void ) { -const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this simple case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer, but don't start it yet. */ - xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ - xTimerPeriod, /* The period of the software timer in ticks. */ - pdTRUE, /* xAutoReload is set to pdTRUE, so this is an auto-reload timer. */ - NULL, /* The timer's ID is not used. */ - prvQueueSendTimerCallback );/* The function executed when the timer expires. */ - - xTimerStart( xTimer, 0 ); /* The scheduler has not started so use a block time of 0. */ - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. NOTE: This demo uses static allocation - for the idle and timer tasks so this line should never execute. */ - for( ;; ); + const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this simple case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer, but don't start it yet. */ + xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ + xTimerPeriod, /* The period of the software timer in ticks. */ + pdTRUE, /* xAutoReload is set to pdTRUE, so this is an auto-reload timer. */ + NULL, /* The timer's ID is not used. */ + prvQueueSendTimerCallback ); /* The function executed when the timer expires. */ + + xTimerStart( xTimer, 0 ); /* The scheduler has not started so use a block time of 0. */ + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. NOTE: This demo uses static allocation + * for the idle and timer tasks so this line should never execute. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, pdMS_TO_TICKS() was used to - convert a time specified in milliseconds into a time specified in ticks. - While in the Blocked state this task will not consume any CPU time. */ - vTaskDelayUntil( &xNextWakeTime, xBlockTime ); - - /* Send to the queue - causing the queue receive task to unblock and - write to the console. 0 is used as the block time so the send operation - will not block - it shouldn't need to block as the queue should always - have at least one space at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } + TickType_t xNextWakeTime; + const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in ticks. + * While in the Blocked state this task will not consume any CPU time. */ + vTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock and + * write to the console. 0 is used as the block time so the send operation + * will not block - it shouldn't need to block as the queue should always + * have at least one space at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } } /*-----------------------------------------------------------*/ static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) { -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; + const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; - /* This is the software timer callback function. The software timer has a - period of two seconds and is reset each time a key is pressed. This - callback function will execute if the timer expires, which will only happen - if a key is not pressed for two seconds. */ + /* This is the software timer callback function. The software timer has a + * period of two seconds and is reset each time a key is pressed. This + * callback function will execute if the timer expires, which will only happen + * if a key is not pressed for two seconds. */ - /* Avoid compiler warnings resulting from the unused parameter. */ - ( void ) xTimerHandle; + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; - /* Send to the queue - causing the queue receive task to unblock and - write out a message. This function is called from the timer/daemon task, so - must not block. Hence the block time is set to 0. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon task, so + * must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -uint32_t ulReceivedValue; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. It will not use any CPU time while it is in the - Blocked state. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it an expected value? */ - if( ulReceivedValue == mainVALUE_SENT_FROM_TASK ) - { - /* It is normally not good to call printf() from an embedded system, - although it is ok in this simulated case. */ - printf( "Message received from task\r\n" ); - } - else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER ) - { - printf( "Message received from software timer\r\n" ); - } - else - { - printf( "Unexpected message\r\n" ); - } - } + uint32_t ulReceivedValue; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + * is it an expected value? */ + if( ulReceivedValue == mainVALUE_SENT_FROM_TASK ) + { + /* It is normally not good to call printf() from an embedded system, + * although it is ok in this simulated case. */ + printf( "Message received from task\r\n" ); + } + else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER ) + { + printf( "Message received from software timer\r\n" ); + } + else + { + printf( "Unexpected message\r\n" ); + } + } } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c index 5120ef1ca66..974507ee64f 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -97,23 +97,23 @@ /*-----------------------------------------------------------*/ /* Task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) /* Stack sizes are defined relative to configMINIMAL_STACK_SIZE so they scale -across projects that have that constant set differently - in this case the -constant is different depending on the compiler in use. */ -#define mainMESSAGE_BUFFER_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) -#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) -#define mainREG_TEST_STACK_SIZE_WORDS 90 + * across projects that have that constant set differently - in this case the + * constant is different depending on the compiler in use. */ +#define mainMESSAGE_BUFFER_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) +#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) +#define mainREG_TEST_STACK_SIZE_WORDS 90 /* Parameters that are passed into the register check tasks solely for the -purpose of ensuring parameters are passed into tasks correctly. */ -#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) -#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) /*-----------------------------------------------------------*/ @@ -123,279 +123,282 @@ purpose of ensuring parameters are passed into tasks correctly. */ * entry points are kept in the C file for the convenience of checking the task * parameter. */ -static void prvRegTestTaskEntry1( void *pvParameters ); +static void prvRegTestTaskEntry1( void * pvParameters ); extern void vRegTest1Implementation( void ); -static void prvRegTestTaskEntry2( void *pvParameters ); +static void prvRegTestTaskEntry2( void * pvParameters ); extern void vRegTest2Implementation( void ); /* The task that checks the operation of all the other standard demo tasks, as * described at the top of this file. */ -static void prvCheckTask( void *pvParameters ); +static void prvCheckTask( void * pvParameters ); /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the -register check tasks to the check task. If the variables keep incrementing, -then the register check tasks have not discovered any errors. If a variable -stops incrementing, then an error has been found. */ + * register check tasks to the check task. If the variables keep incrementing, + * then the register check tasks have not discovered any errors. If a variable + * stops incrementing, then an error has been found. */ uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; -volatile uint32_t *pulRegTest1LoopCounter = &ulRegTest1LoopCounter; -volatile uint32_t *pulRegTest2LoopCounter = &ulRegTest2LoopCounter; +volatile uint32_t * pulRegTest1LoopCounter = &ulRegTest1LoopCounter; +volatile uint32_t * pulRegTest2LoopCounter = &ulRegTest2LoopCounter; /*-----------------------------------------------------------*/ void main_full( void ) { - /* Start the standard demo tasks. */ - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartRecursiveMutexTasks(); - vCreateBlockTimeTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartQueuePeekTasks(); - vStartQueueSetTasks(); - vStartEventGroupTasks(); - vStartMessageBufferTasks( mainMESSAGE_BUFFER_STACK_SIZE ); - vStartStreamBufferTasks(); - vCreateAbortDelayTasks(); - vStartCountingSemaphoreTasks(); - vStartDynamicPriorityTasks(); - vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE ); - vStartQueueOverwriteTask( tskIDLE_PRIORITY ); - vStartQueueSetPollingTask(); - vStartStaticallyAllocatedTasks(); - vStartTaskNotifyTask(); - vStartTaskNotifyArrayTask(); - vStartTimerDemoTask( 50 ); - vStartStreamBufferInterruptDemo(); - vStartInterruptSemaphoreTasks(); - - /* Create the register check tasks, as described at the top of this file. - Use xTaskCreateStatic() to create a task using only statically allocated - memory. */ - xTaskCreate( prvRegTestTaskEntry1, /* The function that implements the task. */ - "Reg1", /* The name of the task. */ - mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */ - mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */ - tskIDLE_PRIORITY, /* Priority of the task. */ - NULL ); /* Can be used to pass out a handle to the created task. */ - xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If configSUPPORT_STATIC_ALLOCATION was false then execution would only - get here if there was insufficient heap memory to create either the idle or - timer tasks. As static allocation is used execution should never be able - to reach here. */ - for( ;; ); + /* Start the standard demo tasks. */ + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartRecursiveMutexTasks(); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartQueuePeekTasks(); + vStartQueueSetTasks(); + vStartEventGroupTasks(); + vStartMessageBufferTasks( mainMESSAGE_BUFFER_STACK_SIZE ); + vStartStreamBufferTasks(); + vCreateAbortDelayTasks(); + vStartCountingSemaphoreTasks(); + vStartDynamicPriorityTasks(); + vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE ); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); + vStartQueueSetPollingTask(); + vStartStaticallyAllocatedTasks(); + vStartTaskNotifyTask(); + vStartTaskNotifyArrayTask(); + vStartTimerDemoTask( 50 ); + vStartStreamBufferInterruptDemo(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file. + * Use xTaskCreateStatic() to create a task using only statically allocated + * memory. */ + xTaskCreate( prvRegTestTaskEntry1, /* The function that implements the task. */ + "Reg1", /* The name of the task. */ + mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */ + mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */ + tskIDLE_PRIORITY, /* Priority of the task. */ + NULL ); /* Can be used to pass out a handle to the created task. */ + xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + * tasks were running prior to their creation in order to ascertain whether + * or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If configSUPPORT_STATIC_ALLOCATION was false then execution would only + * get here if there was insufficient heap memory to create either the idle or + * timer tasks. As static allocation is used execution should never be able + * to reach here. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvRegTestTaskEntry1( void *pvParameters ) +static void prvRegTestTaskEntry1( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest1Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ -static void prvRegTestTaskEntry2( void *pvParameters ) +static void prvRegTestTaskEntry2( void * pvParameters ) { - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest2Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); + /* Although the regtest task is written in assembler, its entry point is + * written in C for convenience of checking the task parameter is being passed + * in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter is + * not being incremented and flag an error. */ + vTaskDelete( NULL ); } /*-----------------------------------------------------------*/ /* See the comments at the top of this file. */ -static void prvCheckTask( void *pvParameters ) +static void prvCheckTask( void * pvParameters ) { -static const char * pcMessage = "FreeRTOS Demo SUCCESS:"; -const TickType_t xTaskPeriod = pdMS_TO_TICKS( 5000UL ); -TickType_t xPreviousWakeTime; -uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; + static const char * pcMessage = "FreeRTOS Demo SUCCESS:"; + const TickType_t xTaskPeriod = pdMS_TO_TICKS( 5000UL ); + TickType_t xPreviousWakeTime; + uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; /* Avoid warning about unused parameter. */ ( void ) pvParameters; - /* Demo start marker. */ - printf( "FreeRTOS Demo Start\r\n" ); - - xPreviousWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - vTaskDelayUntil( &xPreviousWakeTime, xTaskPeriod ); - - /* Has an error been found in any task? */ - if( xAreStreamBufferTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreStreamBufferTasksStillRunning() returned false"; - } - else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreMessageBufferTasksStillRunning() returned false"; - } - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreGenericQueueTasksStillRunning() returned false"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xIsCreateTaskStillRunning() returned false"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreBlockTimeTestTasksStillRunning() returned false"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreSemaphoreTasksStillRunning() returned false"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xArePollingQueuesStillRunning() returned false"; - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreQueuePeekTasksStillRunning() returned false"; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreRecursiveMutexTasksStillRunning() returned false"; - } - else if( xAreQueueSetTasksStillRunning() != pdPASS ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreQueueSetTasksStillRunning() returned false"; - } - else if( xAreEventGroupTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreEventGroupTasksStillRunning() returned false"; - } - else if( xAreAbortDelayTestTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreAbortDelayTestTasksStillRunning() returned false"; - } - else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreCountingSemaphoreTasksStillRunning() returned false"; - } - else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreDynamicPriorityTasksStillRunning() returned false"; - } - else if( xAreMessageBufferAMPTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreMessageBufferAMPTasksStillRunning() returned false"; - } - else if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xIsQueueOverwriteTaskStillRunning() returned false"; - } - else if( xAreQueueSetPollTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreQueueSetPollTasksStillRunning() returned false"; - } - else if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreStaticAllocationTasksStillRunning() returned false"; - } - else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreTaskNotificationTasksStillRunning() returned false"; - } - else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreTaskNotificationArrayTasksStillRunning() returned false"; - } - else if( xAreTimerDemoTasksStillRunning( xTaskPeriod ) != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreTimerDemoTasksStillRunning() returned false"; - } - else if( xIsInterruptStreamBufferDemoStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xIsInterruptStreamBufferDemoStillRunning() returned false"; - } - else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) - { - pcMessage = "FreeRTOS Demo ERROR: xAreInterruptSemaphoreTasksStillRunning() returned false"; - } - else if( ulLastRegTest1Value == ulRegTest1LoopCounter ) /* Check that the register test 1 task is still running. */ - { - pcMessage = "FreeRTOS Demo ERROR: Register test 1.\r\n"; - } - else if( ulLastRegTest2Value == ulRegTest2LoopCounter ) /* Check that the register test 2 task is still running. */ - { - pcMessage = "FreeRTOS Demo ERROR: Register test 2.\r\n"; - } - - ulLastRegTest1Value = ulRegTest1LoopCounter; - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* It is normally not good to call printf() from an embedded system, - although it is ok in this simulated case. */ - printf( "%s : %d\r\n", pcMessage, (int) xTaskGetTickCount() ); - } + /* Demo start marker. */ + printf( "FreeRTOS Demo Start\r\n" ); + + xPreviousWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + vTaskDelayUntil( &xPreviousWakeTime, xTaskPeriod ); + + /* Has an error been found in any task? */ + if( xAreStreamBufferTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreStreamBufferTasksStillRunning() returned false"; + } + else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreMessageBufferTasksStillRunning() returned false"; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreGenericQueueTasksStillRunning() returned false"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xIsCreateTaskStillRunning() returned false"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreBlockTimeTestTasksStillRunning() returned false"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreSemaphoreTasksStillRunning() returned false"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xArePollingQueuesStillRunning() returned false"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreQueuePeekTasksStillRunning() returned false"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreRecursiveMutexTasksStillRunning() returned false"; + } + else if( xAreQueueSetTasksStillRunning() != pdPASS ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreQueueSetTasksStillRunning() returned false"; + } + else if( xAreEventGroupTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreEventGroupTasksStillRunning() returned false"; + } + else if( xAreAbortDelayTestTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreAbortDelayTestTasksStillRunning() returned false"; + } + else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreCountingSemaphoreTasksStillRunning() returned false"; + } + else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreDynamicPriorityTasksStillRunning() returned false"; + } + else if( xAreMessageBufferAMPTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreMessageBufferAMPTasksStillRunning() returned false"; + } + else if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xIsQueueOverwriteTaskStillRunning() returned false"; + } + else if( xAreQueueSetPollTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreQueueSetPollTasksStillRunning() returned false"; + } + else if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreStaticAllocationTasksStillRunning() returned false"; + } + else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreTaskNotificationTasksStillRunning() returned false"; + } + else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreTaskNotificationArrayTasksStillRunning() returned false"; + } + else if( xAreTimerDemoTasksStillRunning( xTaskPeriod ) != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreTimerDemoTasksStillRunning() returned false"; + } + else if( xIsInterruptStreamBufferDemoStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xIsInterruptStreamBufferDemoStillRunning() returned false"; + } + else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + pcMessage = "FreeRTOS Demo ERROR: xAreInterruptSemaphoreTasksStillRunning() returned false"; + } + else if( ulLastRegTest1Value == ulRegTest1LoopCounter ) /* Check that the register test 1 task is still running. */ + { + pcMessage = "FreeRTOS Demo ERROR: Register test 1.\r\n"; + } + else if( ulLastRegTest2Value == ulRegTest2LoopCounter ) /* Check that the register test 2 task is still running. */ + { + pcMessage = "FreeRTOS Demo ERROR: Register test 2.\r\n"; + } + + ulLastRegTest1Value = ulRegTest1LoopCounter; + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* It is normally not good to call printf() from an embedded system, + * although it is ok in this simulated case. */ + printf( "%s : %d\r\n", pcMessage, ( int ) xTaskGetTickCount() ); + } } /*-----------------------------------------------------------*/ void vFullDemoTickHookFunction( void ) { - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); - /* Call the event group ISR tests. */ - vPeriodicEventGroupsProcessing(); + /* Call the event group ISR tests. */ + vPeriodicEventGroupsProcessing(); - /* Exercise stream buffers from interrupts. */ - vPeriodicStreamBufferProcessing(); + /* Exercise stream buffers from interrupts. */ + vPeriodicStreamBufferProcessing(); - /* Exercise using queue overwrites from interrupts. */ - vQueueOverwritePeriodicISRDemo(); + /* Exercise using queue overwrites from interrupts. */ + vQueueOverwritePeriodicISRDemo(); - /* Exercise using Queue Sets from interrupts. */ - vQueueSetPollingInterruptAccess(); + /* Exercise using Queue Sets from interrupts. */ + vQueueSetPollingInterruptAccess(); - /* Exercise using task notifications from interrupts. */ - xNotifyTaskFromISR(); - xNotifyArrayTaskFromISR(); + /* Exercise using task notifications from interrupts. */ + xNotifyTaskFromISR(); + xNotifyArrayTaskFromISR(); - /* Exercise software timers from interrupts. */ - vTimerPeriodicISRTests(); + /* Exercise software timers from interrupts. */ + vTimerPeriodicISRTests(); - /* Exercise stream buffers from interrupts. */ - vBasicStreamBufferSendFromISR(); + /* Exercise stream buffers from interrupts. */ + vBasicStreamBufferSendFromISR(); - /* Exercise semaphores from interrupts. */ - vInterruptSemaphorePeriodicTest(); + /* Exercise semaphores from interrupts. */ + vInterruptSemaphorePeriodicTest(); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.c index 627413ad536..e6518627262 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.h b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.h index 7495bcb233c..28cfc713dda 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.h +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/ns16550.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-reg.h b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-reg.h index fd5723d37aa..a5372311aae 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-reg.h +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-reg.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.c index f5eb568823f..fa5c535c8cc 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -56,9 +56,3 @@ size_t i; portEXIT_CRITICAL(); } - -void handle_trap(void) -{ - while (1) - ; -} diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.h b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.h index 36e5b23f475..09b451108c1 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.h +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/riscv-virt.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject index 5e22068fdb3..689047934c5 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject @@ -66,7 +66,7 @@ - + diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h index 16b1f169778..ffb41d0ce91 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c index e91f7783ab7..be9881e2765 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/main_full.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/main_full.c index 2c9f0c0279c..ec7e57b0b4a 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/main_full.c +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/main.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/main.c index 7c51650265d..2892a75be29 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/main.c +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -56,28 +56,28 @@ #include /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /* Set to 1 to use direct mode and set to 0 to use vectored mode. - -VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the -vector base address (BASE) in the mtvec register. - -VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the -pc to be set to the BASE, whereas interrupts cause the pc to be set to the -address BASE plus four times the interrupt cause number. -*/ -#define mainVECTOR_MODE_DIRECT 0 + * + * VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the + * vector base address (BASE) in the mtvec register. + * + * VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the + * pc to be set to the BASE, whereas interrupts cause the pc to be set to the + * address BASE plus four times the interrupt cause number. + */ +#define mainVECTOR_MODE_DIRECT 0 /* Index to first HART (there is only one). */ -#define mainHART_0 0 +#define mainHART_0 0 /* Registers used to initialise the PLIC. */ -#define mainPLIC_PENDING_0 ( * ( ( volatile uint32_t * ) 0x0C001000UL ) ) -#define mainPLIC_PENDING_1 ( * ( ( volatile uint32_t * ) 0x0C001004UL ) ) -#define mainPLIC_ENABLE_0 ( * ( ( volatile uint32_t * ) 0x0C002000UL ) ) -#define mainPLIC_ENABLE_1 ( * ( ( volatile uint32_t * ) 0x0C002004UL ) ) +#define mainPLIC_PENDING_0 ( *( ( volatile uint32_t * ) 0x0C001000UL ) ) +#define mainPLIC_PENDING_1 ( *( ( volatile uint32_t * ) 0x0C001004UL ) ) +#define mainPLIC_ENABLE_0 ( *( ( volatile uint32_t * ) 0x0C002000UL ) ) +#define mainPLIC_ENABLE_1 ( *( ( volatile uint32_t * ) 0x0C002004UL ) ) /*-----------------------------------------------------------*/ @@ -89,9 +89,9 @@ extern void freertos_vector_table( void ); * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* @@ -100,7 +100,8 @@ extern void freertos_vector_table( void ); */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* @@ -111,199 +112,206 @@ static void prvSetupHardware( void ); /* * Used by the Freedom Metal drivers. */ -static struct metal_led *pxBlueLED = NULL; +static struct metal_led * pxBlueLED = NULL; /*-----------------------------------------------------------*/ int main( void ) { - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { -struct metal_cpu *pxCPU; -struct metal_interrupt *pxInterruptController; - - /* Initialise the blue LED. */ - pxBlueLED = metal_led_get_rgb( "LD0", "blue" ); - configASSERT( pxBlueLED ); - metal_led_enable( pxBlueLED ); - metal_led_off( pxBlueLED ); - - /* Initialise the interrupt controller. */ - pxCPU = metal_cpu_get( mainHART_0 ); - configASSERT( pxCPU ); - pxInterruptController = metal_cpu_interrupt_controller( pxCPU ); - configASSERT( pxInterruptController ); - metal_interrupt_init( pxInterruptController ); - - #if( mainVECTOR_MODE_DIRECT == 1 ) - { - __asm__ volatile( "csrw mtvec, %0" :: "r"( freertos_risc_v_trap_handler ) ); - } - #else - { - __asm__ volatile( "csrw mtvec, %0" :: "r"( ( uintptr_t )freertos_vector_table | 0x1 ) ); - } - #endif - - /* Set all interrupt enable bits to 0. */ - mainPLIC_ENABLE_0 = 0UL; - mainPLIC_ENABLE_1 = 0UL; + struct metal_cpu * pxCPU; + struct metal_interrupt * pxInterruptController; + + /* Initialise the blue LED. */ + pxBlueLED = metal_led_get_rgb( "LD0", "blue" ); + configASSERT( pxBlueLED ); + metal_led_enable( pxBlueLED ); + metal_led_off( pxBlueLED ); + + /* Initialise the interrupt controller. */ + pxCPU = metal_cpu_get( mainHART_0 ); + configASSERT( pxCPU ); + pxInterruptController = metal_cpu_interrupt_controller( pxCPU ); + configASSERT( pxInterruptController ); + metal_interrupt_init( pxInterruptController ); + + #if ( mainVECTOR_MODE_DIRECT == 1 ) + { + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( freertos_risc_v_trap_handler ) ); + } + #else + { + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( ( uintptr_t ) freertos_vector_table | 0x1 ) ); + } + #endif + + /* Set all interrupt enable bits to 0. */ + mainPLIC_ENABLE_0 = 0UL; + mainPLIC_ENABLE_1 = 0UL; } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* The tests in the full demo expect some interaction with interrupts. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - extern void vFullDemoTickHook( void ); - vFullDemoTickHook(); - } - #endif + /* The tests in the full demo expect some interaction with interrupts. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + { + extern void vFullDemoTickHook( void ); + vFullDemoTickHook(); + } + #endif } /*-----------------------------------------------------------*/ void vAssertCalled( void ) { -static struct metal_led *pxRedLED = NULL; -volatile uint32_t ul; -const uint32_t ulNullLoopDelay = 0x1ffffUL; - - taskDISABLE_INTERRUPTS(); - - /* Initialise the red LED. */ - pxRedLED = metal_led_get_rgb( "LD0", "red" ); - configASSERT( pxRedLED ); - metal_led_enable( pxRedLED ); - metal_led_off( pxRedLED ); - - /* Flash the red LED to indicate that assert was hit - interrupts are off - here to prevent any further tick interrupts or context switches, so the - delay is implemented as a crude loop instead of a peripheral timer. */ - for( ;; ) - { - for( ul = 0; ul < ulNullLoopDelay; ul++ ) - { - __asm volatile( "nop" ); - } - metal_led_toggle( pxRedLED ); - } + static struct metal_led * pxRedLED = NULL; + volatile uint32_t ul; + const uint32_t ulNullLoopDelay = 0x1ffffUL; + + taskDISABLE_INTERRUPTS(); + + /* Initialise the red LED. */ + pxRedLED = metal_led_get_rgb( "LD0", "red" ); + configASSERT( pxRedLED ); + metal_led_enable( pxRedLED ); + metal_led_off( pxRedLED ); + + /* Flash the red LED to indicate that assert was hit - interrupts are off + * here to prevent any further tick interrupts or context switches, so the + * delay is implemented as a crude loop instead of a peripheral timer. */ + for( ; ; ) + { + for( ul = 0; ul < ulNullLoopDelay; ul++ ) + { + __asm volatile ( "nop" ); + } + + metal_led_toggle( pxRedLED ); + } } /*-----------------------------------------------------------*/ void handle_trap( void ) { -volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL, ulPLICPending0Register = 0UL, ulPLICPending1Register = 0UL; - - /* Store a few register values that might be useful when determining why this - function was called. */ - __asm volatile( "csrr %0, mepc" : "=r"( ulMEPC ) ); - __asm volatile( "csrr %0, mcause" : "=r"( ulMCAUSE ) ); - ulPLICPending0Register = mainPLIC_PENDING_0; - ulPLICPending1Register = mainPLIC_PENDING_1; - - /* Prevent compiler warnings about unused variables. */ - ( void ) ulPLICPending0Register; - ( void ) ulPLICPending1Register; - - /* Force an assert as this function has not been implemented as the demo - does not use external interrupts. */ - configASSERT( metal_cpu_get( mainHART_0 ) == 0x00 ); + volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL, ulPLICPending0Register = 0UL, ulPLICPending1Register = 0UL; + + /* Store a few register values that might be useful when determining why this + * function was called. */ + __asm volatile ( "csrr %0, mepc" : "=r" ( ulMEPC ) ); + __asm volatile ( "csrr %0, mcause" : "=r" ( ulMCAUSE ) ); + + ulPLICPending0Register = mainPLIC_PENDING_0; + ulPLICPending1Register = mainPLIC_PENDING_1; + + /* Prevent compiler warnings about unused variables. */ + ( void ) ulPLICPending0Register; + ( void ) ulPLICPending1Register; + + /* Force an assert as this function has not been implemented as the demo + * does not use external interrupts. */ + configASSERT( metal_cpu_get( mainHART_0 ) == 0x00 ); } /*-----------------------------------------------------------*/ void freertos_risc_v_application_interrupt_handler( uint32_t ulMcause ) { - ( void )ulMcause; + ( void ) ulMcause; - handle_trap(); + handle_trap(); } /*-----------------------------------------------------------*/ void freertos_risc_v_application_exception_handler( uint32_t ulMcause ) { - ( void )ulMcause; + ( void ) ulMcause; - handle_trap(); + handle_trap(); } /*-----------------------------------------------------------*/ void vToggleLED( void ) { - metal_led_toggle( pxBlueLED ); + metal_led_toggle( pxBlueLED ); } /*-----------------------------------------------------------*/ -void *malloc( size_t xSize ) +void * malloc( size_t xSize ) { - /* The linker script does not define a heap so artificially force an assert() - if something unexpectedly uses the C library heap. See - https://www.freertos.org/a00111.html for more information. */ - configASSERT( metal_cpu_get( mainHART_0 ) == 0x00 ); - - /* Remove warnings about unused parameter. */ - ( void ) xSize; - return NULL; + /* The linker script does not define a heap so artificially force an assert() + * if something unexpectedly uses the C library heap. See + * https://www.freertos.org/a00111.html for more information. */ + configASSERT( metal_cpu_get( mainHART_0 ) == 0x00 ); + + /* Remove warnings about unused parameter. */ + ( void ) xSize; + return NULL; } /*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h index de3dbc8f240..80ea71207f5 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/blinky_demo/main_blinky.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/blinky_demo/main_blinky.c index 719f149c62e..b1044bdf8ec 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/main_full.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/main_full.c index 574d66fe4e3..b85d31775ab 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/main_full.c +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c index 8a8a52bb393..f0dd2d650f9 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c +++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -55,8 +55,8 @@ #include /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /* Set to 1 to use direct mode and set to 0 to use vectored mode. * @@ -66,47 +66,47 @@ or 0 to run the more comprehensive test and demo application. */ * VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the * pc to be set to the BASE, whereas interrupts cause the pc to be set to the * address BASE plus four times the interrupt cause number. -*/ -#define mainVECTOR_MODE_DIRECT 0 + */ +#define mainVECTOR_MODE_DIRECT 0 /* UART hardware constants. */ -#define mainUART_BASE_ADDRESS ( *( volatile uint32_t * ) 0x20000000UL ) -#define mainUART_TX_DATA 0x00 -#define mainUART_TX_CTRL 0x08 -#define mainUART_RX_CTRL 0x0c -#define mainUART_CLOCK_DIV 0x18 -#define mainUART_TX_ENABLE_BIT (1UL << 0UL) -#define mainUART_RX_ENABLE_BIT (1UL << 0UL) -#define mainUART_TX_FULL_BIT (1UL << 31UL) +#define mainUART_BASE_ADDRESS ( *( volatile uint32_t * ) 0x20000000UL ) +#define mainUART_TX_DATA 0x00 +#define mainUART_TX_CTRL 0x08 +#define mainUART_RX_CTRL 0x0c +#define mainUART_CLOCK_DIV 0x18 +#define mainUART_TX_ENABLE_BIT ( 1UL << 0UL ) +#define mainUART_RX_ENABLE_BIT ( 1UL << 0UL ) +#define mainUART_TX_FULL_BIT ( 1UL << 31UL ) #define mainUART_REGISTER( offset ) ( ( mainUART_BASE_ADDRESS + offset ) ) #define mainUART_REGISTER_WORD( offset ) ( *( ( uint32_t * ) mainUART_REGISTER( offset ) ) ) /* Hardware LED specifics. */ -#define mainRED_LED_PIN ( 1UL << 0x16UL ) -#define mainLED_IO_BASE_ADDRESS ( 0x10012000UL ) -#define mainRED_LED_INPUT_ENABLE_REG ( * ( uint32_t * ) ( mainLED_IO_BASE_ADDRESS + 4UL ) ) -#define mainRED_LED_OUTPUT_ENABLE_REG ( * ( uint32_t * ) ( mainLED_IO_BASE_ADDRESS + 8UL ) ) +#define mainRED_LED_PIN ( 1UL << 0x16UL ) +#define mainLED_IO_BASE_ADDRESS ( 0x10012000UL ) +#define mainRED_LED_INPUT_ENABLE_REG ( *( uint32_t * ) ( mainLED_IO_BASE_ADDRESS + 4UL ) ) +#define mainRED_LED_OUTPUT_ENABLE_REG ( *( uint32_t * ) ( mainLED_IO_BASE_ADDRESS + 8UL ) ) /* Hardware LED specifics. */ -#define mainUART_PINMUX_BASE_ADDRESS ( 0x10012000 ) -#define mainUART0_BASE_ADDRESS 0x10013000UL -#define mainUART_CLOCK_RATE 16000000UL -#define mainUART_BAUD_RATE 115200UL -#define mainUART0_TX_DATA_REG ( * ( uint32_t * ) ( mainUART0_BASE_ADDRESS + 0UL ) ) -#define mainUART0_TX_DATA_BYTE_REG ( * ( uint8_t * ) ( mainUART0_BASE_ADDRESS + 0UL ) ) -#define mainUART0_DIV_REG ( * ( uint32_t * ) ( mainUART0_BASE_ADDRESS + 24UL ) ) -#define mainUART0_TXCTRL_REG ( * ( uint32_t * ) ( mainUART0_BASE_ADDRESS + 8UL ) ) -#define mainUART0_RXCTRL_REG ( * ( uint32_t * ) ( mainUART0_BASE_ADDRESS + 12UL ) ) -#define mainUART0_GPIO_SEL_REG ( * ( uint32_t * ) ( mainUART_PINMUX_BASE_ADDRESS + 60UL ) ) -#define mainUART0_GPIO_SEL_EN ( * ( uint32_t * ) ( mainUART_PINMUX_BASE_ADDRESS + 56UL ) ) -#define mainUART_TXEN_BIT ( 1UL ) -#define mainUART0_PIN ( 0x30000UL ) +#define mainUART_PINMUX_BASE_ADDRESS ( 0x10012000 ) +#define mainUART0_BASE_ADDRESS 0x10013000UL +#define mainUART_CLOCK_RATE 16000000UL +#define mainUART_BAUD_RATE 115200UL +#define mainUART0_TX_DATA_REG ( *( uint32_t * ) ( mainUART0_BASE_ADDRESS + 0UL ) ) +#define mainUART0_TX_DATA_BYTE_REG ( *( uint8_t * ) ( mainUART0_BASE_ADDRESS + 0UL ) ) +#define mainUART0_DIV_REG ( *( uint32_t * ) ( mainUART0_BASE_ADDRESS + 24UL ) ) +#define mainUART0_TXCTRL_REG ( *( uint32_t * ) ( mainUART0_BASE_ADDRESS + 8UL ) ) +#define mainUART0_RXCTRL_REG ( *( uint32_t * ) ( mainUART0_BASE_ADDRESS + 12UL ) ) +#define mainUART0_GPIO_SEL_REG ( *( uint32_t * ) ( mainUART_PINMUX_BASE_ADDRESS + 60UL ) ) +#define mainUART0_GPIO_SEL_EN ( *( uint32_t * ) ( mainUART_PINMUX_BASE_ADDRESS + 56UL ) ) +#define mainUART_TXEN_BIT ( 1UL ) +#define mainUART0_PIN ( 0x30000UL ) /* Registers used to initialise the PLIC. */ -#define mainPLIC_PENDING_0 ( * ( ( volatile uint32_t * ) 0x0C001000UL ) ) -#define mainPLIC_PENDING_1 ( * ( ( volatile uint32_t * ) 0x0C001004UL ) ) -#define mainPLIC_ENABLE_0 ( * ( ( volatile uint32_t * ) 0x0C002000UL ) ) -#define mainPLIC_ENABLE_1 ( * ( ( volatile uint32_t * ) 0x0C002004UL ) ) +#define mainPLIC_PENDING_0 ( *( ( volatile uint32_t * ) 0x0C001000UL ) ) +#define mainPLIC_PENDING_1 ( *( ( volatile uint32_t * ) 0x0C001004UL ) ) +#define mainPLIC_ENABLE_0 ( *( ( volatile uint32_t * ) 0x0C002000UL ) ) +#define mainPLIC_ENABLE_1 ( *( ( volatile uint32_t * ) 0x0C002004UL ) ) /*-----------------------------------------------------------*/ @@ -129,7 +129,8 @@ extern void freertos_vector_table( void ); */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* @@ -151,7 +152,7 @@ int main( void ) /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top * of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) { main_blinky(); } @@ -187,13 +188,13 @@ static void prvSetupHardware( void ) mainUART0_GPIO_SEL_REG &= mainUART0_PIN; mainUART0_GPIO_SEL_EN |= mainUART0_PIN; - #if( mainVECTOR_MODE_DIRECT == 1 ) + #if ( mainVECTOR_MODE_DIRECT == 1 ) { - __asm__ volatile( "csrw mtvec, %0" :: "r"( freertos_risc_v_trap_handler ) ); + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( freertos_risc_v_trap_handler ) ); } #else { - __asm__ volatile( "csrw mtvec, %0" :: "r"( ( uintptr_t )freertos_vector_table | 0x1 ) ); + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( ( uintptr_t ) freertos_vector_table | 0x1 ) ); } #endif } @@ -201,7 +202,7 @@ static void prvSetupHardware( void ) void vToggleLED( void ) { -static uint32_t ulLEDState = 0; + static uint32_t ulLEDState = 0; if( ulLEDState == 0 ) { @@ -211,18 +212,22 @@ static uint32_t ulLEDState = 0; { mainRED_LED_OUTPUT_ENABLE_REG &= ~mainRED_LED_PIN; } + ulLEDState = !ulLEDState; } /*-----------------------------------------------------------*/ void vSendString( const char * const pcString ) { -uint32_t ulIndex = 0; + uint32_t ulIndex = 0; /* Crude polling UART Tx. */ while( pcString[ ulIndex ] != 0x00 ) { - while( ( mainUART0_TX_DATA_REG & mainUART_TX_FULL_BIT ) != 0UL ); + while( ( mainUART0_TX_DATA_REG & mainUART_TX_FULL_BIT ) != 0UL ) + { + } + mainUART0_TX_DATA_BYTE_REG = pcString[ ulIndex ]; ulIndex++; } @@ -242,7 +247,10 @@ void vApplicationMallocFailedHook( void ) * to query the size of free heap space that remains (although it does not * provide information on how the remaining heap might be fragmented). */ taskDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ @@ -260,7 +268,8 @@ void vApplicationIdleHook( void ) } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { ( void ) pcTaskName; ( void ) pxTask; @@ -269,14 +278,17 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook * function is called if a stack overflow is detected. */ taskDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { /* The tests in the full demo expect some interaction with interrupts. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) { extern void vFullDemoTickHook( void ); vFullDemoTickHook(); @@ -287,7 +299,7 @@ void vApplicationTickHook( void ) void freertos_risc_v_application_interrupt_handler( uint32_t ulMcause ) { -char pcCause[ 20 ]; + char pcCause[ 20 ]; /* Not implemented yet! */ sprintf( pcCause, "%u", ulMcause ); @@ -298,7 +310,7 @@ char pcCause[ 20 ]; void freertos_risc_v_application_exception_handler( uint32_t ulMcause ) { -char pcCause[ 20 ]; + char pcCause[ 20 ]; /* Not implemented yet! */ sprintf( pcCause, "%u", ulMcause ); @@ -307,7 +319,7 @@ char pcCause[ 20 ]; } /*-----------------------------------------------------------*/ -void *malloc( size_t xSize ) +void * malloc( size_t xSize ) { /* The linker script does not define a heap so artificially force an assert() * if something unexpectedly uses the C library heap. See diff --git a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.cproject b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.cproject index 7d369fbc4ae..bb2d1a1673c 100644 --- a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.cproject +++ b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.cproject @@ -229,7 +229,7 @@ - + diff --git a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/main.c b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/main.c index 94536f24345..17a401d4e45 100644 --- a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/main.c +++ b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,19 +57,19 @@ #include "drivers/mss/mss_mmuart/mss_uart.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /* Set to 1 to use direct mode and set to 0 to use vectored mode. - -VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the -vector base address (BASE) in the mtvec register. - -VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the -pc to be set to the BASE, whereas interrupts cause the pc to be set to the -address BASE plus four times the interrupt cause number. -*/ -#define mainVECTOR_MODE_DIRECT 0 + * + * VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the + * vector base address (BASE) in the mtvec register. + * + * VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the + * pc to be set to the BASE, whereas interrupts cause the pc to be set to the + * address BASE plus four times the interrupt cause number. + */ +#define mainVECTOR_MODE_DIRECT 0 /*-----------------------------------------------------------*/ @@ -92,7 +92,8 @@ extern void freertos_vector_table( void ); */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* @@ -110,7 +111,7 @@ void e51( void ) /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top * of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) { main_blinky(); } @@ -126,25 +127,25 @@ static void prvSetupHardware( void ) { /* Configure UART0. */ SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_MMUART0_MASK; - SYSREG->SOFT_RESET_CR &= ~SOFT_RESET_CR_MMUART0_MASK; + SYSREG->SOFT_RESET_CR &= ~SOFT_RESET_CR_MMUART0_MASK; MSS_UART_init( &( g_mss_uart0_lo ), MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT ); /* Configure the LED. */ - mss_config_clk_rst( MSS_PERIPH_GPIO2, ( uint8_t )MPFS_HAL_FIRST_HART, PERIPHERAL_ON ); + mss_config_clk_rst( MSS_PERIPH_GPIO2, ( uint8_t ) MPFS_HAL_FIRST_HART, PERIPHERAL_ON ); MSS_GPIO_config( GPIO2_LO, MSS_GPIO_16, MSS_GPIO_OUTPUT_MODE ); /* Red Led (LED1). */ MSS_GPIO_config( GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE ); /* Yellow Led (LED3). */ - #if( mainVECTOR_MODE_DIRECT == 1 ) - { - __asm__ volatile( "csrw mtvec, %0" :: "r"( freertos_risc_v_trap_handler ) ); - } - #else - { - __asm__ volatile( "csrw mtvec, %0" :: "r"( ( uintptr_t )freertos_vector_table | 0x1 ) ); - } - #endif + #if ( mainVECTOR_MODE_DIRECT == 1 ) + { + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( freertos_risc_v_trap_handler ) ); + } + #else + { + __asm__ volatile ( "csrw mtvec, %0" : : "r" ( ( uintptr_t ) freertos_vector_table | 0x1 ) ); + } + #endif } /*-----------------------------------------------------------*/ @@ -161,7 +162,10 @@ void vApplicationMallocFailedHook( void ) * to query the size of free heap space that remains (although it does not * provide information on how the remaining heap might be fragmented). */ taskDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ @@ -179,7 +183,8 @@ void vApplicationIdleHook( void ) } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { ( void ) pcTaskName; ( void ) pxTask; @@ -188,14 +193,17 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook * function is called if a stack overflow is detected. */ taskDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { /* The tests in the full demo expect some interaction with interrupts. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) { extern void vFullDemoTickHook( void ); vFullDemoTickHook(); @@ -206,7 +214,7 @@ void vApplicationTickHook( void ) void vToggleLED( void ) { -static volatile uint8_t value = 0u; + static volatile uint8_t value = 0u; value = ( value == 0u ) ? 1u : 0u; MSS_GPIO_set_output( GPIO2_LO, MSS_GPIO_18, value ); @@ -215,20 +223,20 @@ static volatile uint8_t value = 0u; void vAssertCalled( void ) { -volatile uint32_t ul; -const uint32_t ulNullLoopDelay = 0x1ffffUL; -static volatile uint8_t value = 0u; + volatile uint32_t ul; + const uint32_t ulNullLoopDelay = 0x1ffffUL; + static volatile uint8_t value = 0u; taskDISABLE_INTERRUPTS(); /* Flash the red LED to indicate that assert was hit - interrupts are off * here to prevent any further tick interrupts or context switches, so the * delay is implemented as a crude loop instead of a peripheral timer. */ - for( ;; ) + for( ; ; ) { for( ul = 0; ul < ulNullLoopDelay; ul++ ) { - __asm volatile( "nop" ); + __asm volatile ( "nop" ); } value = ( value == 0u ) ? 1u : 0u; diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h index 80021cfcc67..e7385f64464 100644 --- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch index 3a67cbcc160..d9e54f81a77 100644 --- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch +++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch @@ -10,7 +10,7 @@ - + diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c index 3858cfbc8f3..a2b68a62fc2 100644 --- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c +++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c index 48835d20664..ff940ad59d0 100644 --- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c +++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c index c2f8f693c81..5c3d7be2591 100644 --- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c +++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -50,24 +50,25 @@ */ /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + * or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /* * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - extern void main_blinky( void ); + extern void main_blinky( void ); #else - extern void main_full( void ); + extern void main_full( void ); #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. See https://www.freertos.org/a00016.html */ + * within this file. See https://www.freertos.org/a00016.html */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* Prepare hardware to run the demo. */ @@ -86,105 +87,111 @@ static gpio_instance_t g_gpio_out; int main( void ) { - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif } /*-----------------------------------------------------------*/ static void prvSetupHardware( void ) { - PLIC_init(); - UART_init( &g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, ( DATA_8_BITS | NO_PARITY ) ); + PLIC_init(); + UART_init( &g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, ( DATA_8_BITS | NO_PARITY ) ); } /*-----------------------------------------------------------*/ void vToggleLED( void ) { -static uint32_t ulLEDState = 0; + static uint32_t ulLEDState = 0; - GPIO_set_outputs( &g_gpio_out, ulLEDState ); - ulLEDState = !ulLEDState; + GPIO_set_outputs( &g_gpio_out, ulLEDState ); + ulLEDState = !ulLEDState; } /*-----------------------------------------------------------*/ void vSendString( const char * const pcString ) { - UART_polled_tx_string( &g_uart, ( const uint8_t * ) pcString ); + UART_polled_tx_string( &g_uart, ( const uint8_t * ) pcString ); } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c or heap_2.c are used, then the size of the + * heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + * FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* The tests in the full demo expect some interaction with interrupts. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - extern void vFullDemoTickHook( void ); - vFullDemoTickHook(); - } - #endif + /* The tests in the full demo expect some interaction with interrupts. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + { + extern void vFullDemoTickHook( void ); + vFullDemoTickHook(); + } + #endif } /*-----------------------------------------------------------*/ -void *_sbrk( ptrdiff_t incr ) +void * _sbrk( ptrdiff_t incr ) { - /* Required to link, but force an assert to ensure it is never actually - called. */ - configASSERT( ( void * ) incr == NULL ); - return NULL; + /* Required to link, but force an assert to ensure it is never actually + * called. */ + configASSERT( ( void * ) incr == NULL ); + return NULL; } - diff --git a/FreeRTOS/Demo/RL78_multiple_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/RL78_multiple_IAR/FreeRTOSConfig.h index d52832b9219..e7c4e0fd6a9 100644 --- a/FreeRTOS/Demo/RL78_multiple_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RL78_multiple_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RL78_multiple_IAR/demo_specific_io.h b/FreeRTOS/Demo/RL78_multiple_IAR/demo_specific_io.h index d92e8a60c8d..040a8a56b99 100644 --- a/FreeRTOS/Demo/RL78_multiple_IAR/demo_specific_io.h +++ b/FreeRTOS/Demo/RL78_multiple_IAR/demo_specific_io.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RL78_multiple_IAR/main.c b/FreeRTOS/Demo/RL78_multiple_IAR/main.c index 6b1844ed850..1f8eaa30c23 100644 --- a/FreeRTOS/Demo/RL78_multiple_IAR/main.c +++ b/FreeRTOS/Demo/RL78_multiple_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -57,7 +57,7 @@ #include "demo_specific_io.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ + * or 0 to run the more comprehensive test and demo application. */ #define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 /*-----------------------------------------------------------*/ @@ -73,13 +73,14 @@ extern void main_full( void ); * This function is called from the C startup routine to setup the processor - * in particular the CPU clock source. */ -int __low_level_init(void); +int __low_level_init( void ); /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /* Prototype for the application-implemented timer for the OS tick */ @@ -88,18 +89,18 @@ void vApplicationSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ /* This variable is not actually used, but provided to allow an example of how -to write an ISR to be included in this file. */ + * to write an ISR to be included in this file. */ static SemaphoreHandle_t xSemaphore = NULL; /* RL78 Option Byte Definition. Watchdog disabled, LVI enabled, OCD interface -enabled. */ -__root __far const unsigned char OptionByte[] @ 0x00C0 = + * enabled. */ +__root __far const unsigned char OptionByte[] @0x00C0 = { 0x6eU, 0xffU, 0xe8U, 0x85U }; /* Security byte definition */ -__root __far const unsigned char ucSecurityCode[] @ 0x00C4 = +__root __far const unsigned char ucSecurityCode[] @0x00C4 = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; @@ -109,7 +110,7 @@ __root __far const unsigned char ucSecurityCode[] @ 0x00C4 = void main( void ) { /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ + * of this file. */ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 { main_blinky(); @@ -136,25 +137,25 @@ void vAnExampleISR_C_Handler( void ) * Also see the documentation page for this demo on the FreeRTOS.org website * for full instructions. */ -short sHigherPriorityTaskWoken = pdFALSE; + short sHigherPriorityTaskWoken = pdFALSE; /* Handler code goes here...*/ /* For purposes of demonstration, assume at some point the hander calls - xSemaphoreGiveFromISR().*/ + * xSemaphoreGiveFromISR().*/ xSemaphoreGiveFromISR( xSemaphore, &sHigherPriorityTaskWoken ); /* If giving the semaphore unblocked a task, and the unblocked task has a - priority higher than or equal to the currently running task, then - sHigherPriorityTaskWoken will have been set to pdTRUE internally within the - xSemaphoreGiveFromISR() function. Passing a pdTRUE value to - portYIELD_FROM_ISR() will cause this interrupt to return directly to the - higher priority unblocked task. */ + * priority higher than or equal to the currently running task, then + * sHigherPriorityTaskWoken will have been set to pdTRUE internally within the + * xSemaphoreGiveFromISR() function. Passing a pdTRUE value to + * portYIELD_FROM_ISR() will cause this interrupt to return directly to the + * higher priority unblocked task. */ portYIELD_FROM_ISR( sHigherPriorityTaskWoken ); } /*-----------------------------------------------------------*/ -int __low_level_init(void) +int __low_level_init( void ) { portDISABLE_INTERRUPTS(); @@ -184,14 +185,14 @@ int __low_level_init(void) void vApplicationSetupTimerInterrupt( void ) { -const uint16_t usClockHz = 15000UL; /* Internal clock. */ -const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; + const uint16_t usClockHz = 15000UL; /* Internal clock. */ + const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; /* Use the internal 15 kHz clock. */ OSMC = ( uint8_t ) 0x16; /* The clock source for the Interval Timer peripheral used for generating - the tick interrupt depends on the RL78 device in use. */ + * the tick interrupt depends on the RL78 device in use. */ #if configTICK_VECTOR == 0x38 { /* Supply the interval timer clock. */ @@ -232,48 +233,55 @@ const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; /* Enable INTIT interrupt. */ TMKAMK = ( uint8_t ) 0; } - #else - #error "It is necessary to configure a suitable timer interrupt for the tick." - #endif + #else /* if configTICK_VECTOR == 0x38 */ + #error "It is necessary to configure a suitable timer interrupt for the tick." + #endif /* if configTICK_VECTOR == 0x38 */ } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ taskDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { ( void ) pcTaskName; ( void ) pxTask; /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. */ taskDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { -volatile size_t xFreeHeapSpace; + volatile size_t xFreeHeapSpace; /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ + * cycle of the idle task. It must *NOT* attempt to block. In this case the + * idle task just queries the amount of FreeRTOS heap that remains. See the + * memory management section on the http://www.FreeRTOS.org web site for memory + * management options. If there is a lot of heap memory free then the + * configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + * RAM. */ xFreeHeapSpace = xPortGetFreeHeapSize(); /* Remove compiler warning about xFreeHeapSpace being set but never used. */ diff --git a/FreeRTOS/Demo/RL78_multiple_IAR/main_blinky.c b/FreeRTOS/Demo/RL78_multiple_IAR/main_blinky.c index 683458b5822..4cfef2c934f 100644 --- a/FreeRTOS/Demo/RL78_multiple_IAR/main_blinky.c +++ b/FreeRTOS/Demo/RL78_multiple_IAR/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -74,33 +74,33 @@ #include "demo_specific_io.h" /* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) /* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + * to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) /* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * will remove items as they are added, meaning the send task should always find + * the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* Used to check the task parameter passing in both supported memory models. */ #if __DATA_MODEL__ == __DATA_MODEL_FAR__ - #define mainQUEUE_SEND_PARAMETER ( ( void * ) 0x12345678UL ) - #define mainQUEUE_RECEIVE_PARAMETER ( ( void * ) 0x11223344UL ) + #define mainQUEUE_SEND_PARAMETER ( ( void * ) 0x12345678UL ) + #define mainQUEUE_RECEIVE_PARAMETER ( ( void * ) 0x11223344UL ) #else - #define mainQUEUE_SEND_PARAMETER ( ( void * ) 0x1234U ) - #define mainQUEUE_RECEIVE_PARAMETER ( ( void * ) 0x1122U ) + #define mainQUEUE_SEND_PARAMETER ( ( void * ) 0x1234U ) + #define mainQUEUE_RECEIVE_PARAMETER ( ( void * ) 0x1122U ) #endif /*-----------------------------------------------------------*/ /* * The tasks as described in the comments at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Called by main() to create the simply blinky style application if @@ -123,13 +123,13 @@ void main_blinky( void ) if( xQueue != NULL ) { /* Start the two tasks as described in the comments at the top of this - file. */ + * file. */ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just used to check the port in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just used to check the port in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); @@ -138,18 +138,20 @@ void main_blinky( void ) } /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. http://www.freertos.org/a00111.html. */ - for( ;; ); + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. http://www.freertos.org/a00111.html. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; + TickType_t xNextWakeTime; + const unsigned long ulValueToSend = 100UL; /* Check the parameter was passed in correctly. */ configASSERT( pvParameters == mainQUEUE_SEND_PARAMETER ) @@ -157,7 +159,7 @@ const unsigned long ulValueToSend = 100UL; /* Initialise xNextWakeTime - this only needs to be done once. */ xNextWakeTime = xTaskGetTickCount(); - for( ;; ) + for( ; ; ) { /* Place this task in the blocked state until it is time to run again. */ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); @@ -173,15 +175,15 @@ const unsigned long ulValueToSend = 100UL; } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; + unsigned long ulReceivedValue; + const unsigned long ulExpectedValue = 100UL; /* Check the parameter was passed in correctly. */ configASSERT( pvParameters == mainQUEUE_RECEIVE_PARAMETER ) - for( ;; ) + for( ; ; ) { /* * Wait until something arrives in the queue - this task will block diff --git a/FreeRTOS/Demo/RL78_multiple_IAR/main_full.c b/FreeRTOS/Demo/RL78_multiple_IAR/main_full.c index 484648ea1b3..d8b9e09b5a2 100644 --- a/FreeRTOS/Demo/RL78_multiple_IAR/main_full.c +++ b/FreeRTOS/Demo/RL78_multiple_IAR/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -92,30 +92,30 @@ #include "demo_specific_io.h" /* The period at which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks, the check tasks, or the demo timer. -ms are converted to the equivalent in ticks using the portTICK_PERIOD_MS -constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks, the check tasks, or the demo timer. + * ms are converted to the equivalent in ticks using the portTICK_PERIOD_MS + * constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /* These two definitions are used to set the period of the demo timer. The demo -timer period is always relative to the check timer period, so the check timer -can determine if the demo timer has expired the expected number of times between -its own executions. */ + * timer period is always relative to the check timer period, so the check timer + * can determine if the demo timer has expired the expected number of times between + * its own executions. */ #define mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT ( 100UL ) -#define mainDEMO_TIMER_PERIOD_MS ( mainCHECK_TIMER_PERIOD_MS / mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT ) +#define mainDEMO_TIMER_PERIOD_MS ( mainCHECK_TIMER_PERIOD_MS / mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0U ) +#define mainDONT_BLOCK ( 0U ) /* Values that are passed as parameters into the reg test tasks (purely to -ensure task parameters are passed correctly). */ -#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x1234 ) -#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x5678 ) + * ensure task parameters are passed correctly). */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x1234 ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x5678 ) /*-----------------------------------------------------------*/ @@ -137,8 +137,8 @@ static void prvDemoTimerCallback( TimerHandle_t xTimer ); */ extern void vRegTest1Task( void ); extern void vRegTest2Task( void ); -static void prvRegTest1Entry( void *pvParameters ); -static void prvRegTest2Entry( void *pvParameters ); +static void prvRegTest1Entry( void * pvParameters ); +static void prvRegTest2Entry( void * pvParameters ); /* * Called if a RegTest task discovers an error as a mechanism to stop the @@ -156,11 +156,11 @@ void main_full( void ); /*-----------------------------------------------------------*/ /* Variables that are incremented on each cycle of the two reg tests to allow -the check timer to know that they are still executing. */ + * the check timer to know that they are still executing. */ unsigned short usRegTest1LoopCounter = 0, usRegTest2LoopCounter; /* The check timer. This uses prvCheckTimerCallback() as its callback -function. */ + * function. */ static TimerHandle_t xCheckTimer = NULL; /* The demo timer. This uses prvDemoTimerCallback() as its callback function. */ @@ -176,40 +176,40 @@ void main_full( void ) /* Creates all the tasks and timers, then starts the scheduler. */ /* First create the 'standard demo' tasks. These are used to demonstrate - API functions being used and also to test the kernel port. More information - is provided on the FreeRTOS.org WEB site. */ + * API functions being used and also to test the kernel port. More information + * is provided on the FreeRTOS.org WEB site. */ vStartDynamicPriorityTasks(); vStartPolledQueueTasks( tskIDLE_PRIORITY ); vCreateBlockTimeTasks(); /* Create the RegTest tasks as described at the top of this file. */ - xTaskCreate( prvRegTest1Entry, /* The function that implements the task. */ - "Reg1", /* Text name for the task - to assist debugging only, not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack allocated to the task (in words, not bytes). */ - mainREG_TEST_1_PARAMETER, /* The parameter passed into the task. */ - tskIDLE_PRIORITY, /* The priority at which the task will execute. */ - NULL ); /* Used to pass the handle of the created task out to the function caller - not used in this case. */ + xTaskCreate( prvRegTest1Entry, /* The function that implements the task. */ + "Reg1", /* Text name for the task - to assist debugging only, not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack allocated to the task (in words, not bytes). */ + mainREG_TEST_1_PARAMETER, /* The parameter passed into the task. */ + tskIDLE_PRIORITY, /* The priority at which the task will execute. */ + NULL ); /* Used to pass the handle of the created task out to the function caller - not used in this case. */ xTaskCreate( prvRegTest2Entry, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback ); /* The callback function that inspects the status of all the other tasks. */ + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback ); /* The callback function that inspects the status of all the other tasks. */ /* Create the software timer that just increments a variable for demo - purposes. */ - xDemoTimer = xTimerCreate( "DemoTimer",/* A text name, purely to help debugging. */ - ( mainDEMO_TIMER_PERIOD_MS ), /* The timer period, in this case it is always calculated relative to the check timer period (see the definition of mainDEMO_TIMER_PERIOD_MS). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvDemoTimerCallback ); /* The callback function that inspects the status of all the other tasks. */ + * purposes. */ + xDemoTimer = xTimerCreate( "DemoTimer", /* A text name, purely to help debugging. */ + ( mainDEMO_TIMER_PERIOD_MS ), /* The timer period, in this case it is always calculated relative to the check timer period (see the definition of mainDEMO_TIMER_PERIOD_MS). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvDemoTimerCallback ); /* The callback function that inspects the status of all the other tasks. */ /* Start both the check timer and the demo timer. The timers won't actually - start until the scheduler is started. */ + * start until the scheduler is started. */ xTimerStart( xCheckTimer, mainDONT_BLOCK ); xTimerStart( xDemoTimer, mainDONT_BLOCK ); @@ -217,10 +217,12 @@ void main_full( void ) vTaskStartScheduler(); /* If all is well execution will never reach here as the scheduler will be - running. If this null loop is reached then it is likely there was - insufficient FreeRTOS heap available for the idle task and/or timer task to - be created. See http://www.freertos.org/a00111.html. */ - for( ;; ); + * running. If this null loop is reached then it is likely there was + * insufficient FreeRTOS heap available for the idle task and/or timer task to + * be created. See http://www.freertos.org/a00111.html. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ @@ -230,17 +232,17 @@ static void prvDemoTimerCallback( TimerHandle_t xTimer ) ( void ) xTimer; /* The demo timer has expired. All it does is increment a variable. The - period of the demo timer is relative to that of the check timer, so the - check timer knows how many times this variable should have been incremented - between each execution of the check timer's own callback. */ + * period of the demo timer is relative to that of the check timer, so the + * check timer knows how many times this variable should have been incremented + * between each execution of the check timer's own callback. */ ulDemoSoftwareTimerCounter++; } /*-----------------------------------------------------------*/ static void prvCheckTimerCallback( TimerHandle_t xTimer ) { -static portBASE_TYPE xChangedTimerPeriodAlready = pdFALSE, xErrorStatus = pdPASS; -static unsigned short usLastRegTest1Counter = 0, usLastRegTest2Counter = 0; + static portBASE_TYPE xChangedTimerPeriodAlready = pdFALSE, xErrorStatus = pdPASS; + static unsigned short usLastRegTest1Counter = 0, usLastRegTest2Counter = 0; /* Remove compiler warning about unused parameter. */ ( void ) xTimer; @@ -262,7 +264,7 @@ static unsigned short usLastRegTest1Counter = 0, usLastRegTest2Counter = 0; } /* Indicate an error if either of the reg test loop counters have not - incremented since the last time this function was called. */ + * incremented since the last time this function was called. */ if( usLastRegTest1Counter == usRegTest1LoopCounter ) { xErrorStatus = pdFAIL; @@ -282,14 +284,14 @@ static unsigned short usLastRegTest1Counter = 0, usLastRegTest2Counter = 0; } /* Ensure that the demo software timer has expired - mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT times in between - each call of this function. A critical section is not required to access - ulDemoSoftwareTimerCounter as the variable is only accessed from another - software timer callback, and only one software timer callback can be - executing at any time. */ + * mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT times in between + * each call of this function. A critical section is not required to access + * ulDemoSoftwareTimerCounter as the variable is only accessed from another + * software timer callback, and only one software timer callback can be + * executing at any time. */ if( ( ulDemoSoftwareTimerCounter < ( mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT - 1 ) ) || ( ulDemoSoftwareTimerCounter > ( mainDEMO_TIMER_INCREMENTS_PER_CHECK_TIMER_TIMEOUT + 1 ) ) - ) + ) { xErrorStatus = pdFAIL; } @@ -301,19 +303,19 @@ static unsigned short usLastRegTest1Counter = 0, usLastRegTest2Counter = 0; if( ( xErrorStatus == pdFAIL ) && ( xChangedTimerPeriodAlready == pdFALSE ) ) { /* An error has occurred, but the timer's period has not yet been changed, - change it now, and remember that it has been changed. Shortening the - timer's period means the LED will toggle at a faster rate, giving a - visible indication that something has gone wrong. */ + * change it now, and remember that it has been changed. Shortening the + * timer's period means the LED will toggle at a faster rate, giving a + * visible indication that something has gone wrong. */ xChangedTimerPeriodAlready = pdTRUE; /* This call to xTimerChangePeriod() uses a zero block time. Functions - called from inside of a timer callback function must *never* attempt to - block. */ + * called from inside of a timer callback function must *never* attempt to + * block. */ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); } /* Toggle the LED. The toggle rate will depend on whether or not an error - has been found in any tasks. */ + * has been found in any tasks. */ LED_BIT = !LED_BIT; } /*-----------------------------------------------------------*/ @@ -321,17 +323,19 @@ static unsigned short usLastRegTest1Counter = 0, usLastRegTest2Counter = 0; void vRegTestError( void ) { /* Called by both reg test tasks if an error is found. There is no way out - of this function so the loop counter of the calling task will stop - incrementing, which will result in the check timer signaling an error. */ - for( ;; ); + * of this function so the loop counter of the calling task will stop + * incrementing, which will result in the check timer signaling an error. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvRegTest1Entry( void *pvParameters ) +static void prvRegTest1Entry( void * pvParameters ) { /* If the parameter has its expected value then start the first reg test - task (this is only done to test that the RTOS port is correctly handling - task parameters. */ + * task (this is only done to test that the RTOS port is correctly handling + * task parameters. */ if( pvParameters == mainREG_TEST_1_PARAMETER ) { vRegTest1Task(); @@ -342,15 +346,15 @@ static void prvRegTest1Entry( void *pvParameters ) } /* It is not possible to get here as neither of the two functions called - above will ever return. */ + * above will ever return. */ } /*-----------------------------------------------------------*/ -static void prvRegTest2Entry( void *pvParameters ) +static void prvRegTest2Entry( void * pvParameters ) { /* If the parameter has its expected value then start the first reg test - task (this is only done to test that the RTOS port is correctly handling - task parameters. */ + * task (this is only done to test that the RTOS port is correctly handling + * task parameters. */ if( pvParameters == mainREG_TEST_2_PARAMETER ) { vRegTest2Task(); @@ -361,7 +365,6 @@ static void prvRegTest2Entry( void *pvParameters ) } /* It is not possible to get here as neither of the two functions called - above will ever return. */ + * above will ever return. */ } /*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h index 18763242473..15ba7af866e 100644 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c index 72ae59ef0f3..f3cc76a3a7c 100644 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c +++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c index 7f38b90d121..1892200f11c 100644 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c +++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c index 9e6f03f9d73..ef60539eebd 100644 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c +++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c index 6b663243998..7f32e08994f 100644 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c +++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h index c28c0ae7047..d5ea8483902 100644 --- a/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c b/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c index 72ae59ef0f3..f3cc76a3a7c 100644 --- a/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c +++ b/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h b/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h index c998416033f..2ff5c0b9a79 100644 --- a/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h +++ b/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/main.c b/FreeRTOS/Demo/RX100-RSK_IAR/main.c index 8e51a6b30ba..9f6d27af358 100644 --- a/FreeRTOS/Demo/RX100-RSK_IAR/main.c +++ b/FreeRTOS/Demo/RX100-RSK_IAR/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -59,105 +59,113 @@ extern void main_low_power( void ); extern void main_full( void ); /* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ + * within this file. */ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); void vApplicationTickHook( void ); /*-----------------------------------------------------------*/ /* See the documentation page for this demo on the FreeRTOS.org web site for -full information - including hardware setup requirements. */ + * full information - including hardware setup requirements. */ void main( void ) { - /* Call the Renesas provided setup. */ - vHardwareSetup(); - lcd_initialize(); - lcd_display( LCD_LINE1, "FreeRTOS" ); - - /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */ - #if configCREATE_LOW_POWER_DEMO == 1 - { - lcd_display( LCD_LINE2, "LP Demo" ); - main_low_power(); - } - #else - { - lcd_display( LCD_LINE2, "Ful Demo" ); - main_full(); - } - #endif + /* Call the Renesas provided setup. */ + vHardwareSetup(); + lcd_initialize(); + lcd_display( LCD_LINE1, "FreeRTOS" ); + + /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */ + #if configCREATE_LOW_POWER_DEMO == 1 + { + lcd_display( LCD_LINE2, "LP Demo" ); + main_low_power(); + } + #else + { + lcd_display( LCD_LINE2, "Ful Demo" ); + main_full(); + } + #endif } /*-----------------------------------------------------------*/ void vApplicationMallocFailedHook( void ) { - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size - of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE - in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size + * of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE + * in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + * to query the size of free heap space that remains (although it does not + * provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationIdleHook( void ) { - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If the application makes use of the + * vTaskDelete() API function (as this demo application does) then it is also + * important that vApplicationIdleHook() is permitted to return to its calling + * function, because it is the responsibility of the idle task to clean up + * memory allocated by the kernel to any task that has since been deleted. */ } /*-----------------------------------------------------------*/ -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) { - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is - called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is + * called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ void vApplicationTickHook( void ) { - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ } /*-----------------------------------------------------------*/ void vAssertCalled( void ) { -volatile unsigned long ul = 0; - - taskENTER_CRITICAL(); - { - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - __asm volatile( "NOP" ); - } - } - taskEXIT_CRITICAL(); + volatile unsigned long ul = 0; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + * function. */ + while( ul == 0 ) + { + __asm volatile ( "NOP" ); + } + } + taskEXIT_CRITICAL(); } diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c b/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c index c4c81278e3a..485d3f45682 100644 --- a/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c +++ b/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -65,7 +65,7 @@ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started. * The PowerON_Reset_PC() supplied in resetprg.c with this demo has * Change_PSW_PM_to_UserMode() commented out to ensure this is the case. -*/ + */ /* Standard includes. */ #include @@ -88,211 +88,213 @@ /* Variables that are incremented on each iteration of the reg test tasks are -declared outside of the #if configCREATE_LOW_POWER_DEMO conditional compilation -to prevent linker issues when configCREATE_LOW_POWER_DEMO is set to 1. The -check timer inspects these variables to ensure they are still incrementing as -expected. If a variable stops incrementing then it is likely that its associate -task has stalled. */ + * declared outside of the #if configCREATE_LOW_POWER_DEMO conditional compilation + * to prevent linker issues when configCREATE_LOW_POWER_DEMO is set to 1. The + * check timer inspects these variables to ensure they are still incrementing as + * expected. If a variable stops incrementing then it is likely that its associate + * task has stalled. */ unsigned long volatile ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL; /* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set -to 0, otherwise the code in main_low_power.c is used. */ + * to 0, otherwise the code in main_low_power.c is used. */ #if configCREATE_LOW_POWER_DEMO == 0 /* Values that are passed into the reg test tasks using the task parameter. -The tasks check that the values are passed in correctly. */ -#define mainREG_TEST_1_PARAMETER ( 0x12121212UL ) -#define mainREG_TEST_2_PARAMETER ( 0x12345678UL ) + * The tasks check that the values are passed in correctly. */ + #define mainREG_TEST_1_PARAMETER ( 0x12121212UL ) + #define mainREG_TEST_2_PARAMETER ( 0x12345678UL ) /* Priorities at which the standard demo tasks are created. */ -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + #define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + #define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) /* The LED toggled by the check timer. */ -#define mainCHECK_LED ( 0 ) + #define mainCHECK_LED ( 0 ) /* The period at which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + * have been reported by any of the standard demo tasks. ms are converted to the + * equivalent in ticks using the portTICK_PERIOD_MS constant. */ + #define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) /* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + * reported in one of the standard demo tasks. ms are converted to the equivalent + * in ticks using the portTICK_PERIOD_MS constant. */ + #define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) /* A block time of zero simple means "Don't Block". */ -#define mainDONT_BLOCK ( 0UL ) + #define mainDONT_BLOCK ( 0UL ) /* * The reg test tasks as described at the top of this file. */ -static void prvRegTest1Task( void *pvParameters ); -static void prvRegTest2Task( void *pvParameters ); + static void prvRegTest1Task( void * pvParameters ); + static void prvRegTest2Task( void * pvParameters ); /* * The actual implementation of the reg test functionality, which, because of * the direct register access, have to be in assembly. */ -void vRegTest1Implementation( void ); -void vRegTest2Implementation( void ); + void vRegTest1Implementation( void ); + void vRegTest2Implementation( void ); /* * The check timer callback function, as described at the top of this file. */ -static void prvCheckTimerCallback( TimerHandle_t xTimer ); + static void prvCheckTimerCallback( TimerHandle_t xTimer ); /*-----------------------------------------------------------*/ /* The check timer. This uses prvCheckTimerCallback() as its callback -function. */ -static TimerHandle_t xCheckTimer = NULL; + * function. */ + static TimerHandle_t xCheckTimer = NULL; /*-----------------------------------------------------------*/ -void main_full( void ) -{ - /* Start the reg test tasks which test the context switching mechanism. */ - xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* Create the standard demo tasks. */ - vCreateBlockTimeTasks(); - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartRecursiveMutexTasks(); - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation in order to ascertain whether - or not the correct/expected number of tasks are running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer",/* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - configASSERT( xCheckTimer ); - - /* Start the check timer. It will actually start when the scheduler is - started. */ - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - - /* Start the tasks running. */ - vTaskStartScheduler(); - - /* If all is well execution will never reach here as the scheduler will be - running. If this null loop is reached then it is likely there was - insufficient FreeRTOS heap available for the idle task and/or timer task to - be created. See http://www.freertos.org/a00111.html. */ - for( ;; ); -} + void main_full( void ) + { + /* Start the reg test tasks which test the context switching mechanism. */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the standard demo tasks. */ + vCreateBlockTimeTasks(); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartRecursiveMutexTasks(); + + /* The suicide tasks must be created last as they need to know how many + * tasks were running prior to their creation in order to ascertain whether + * or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Create the software timer that performs the 'check' functionality, + * as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + configASSERT( xCheckTimer ); + + /* Start the check timer. It will actually start when the scheduler is + * started. */ + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + + /* Start the tasks running. */ + vTaskStartScheduler(); + + /* If all is well execution will never reach here as the scheduler will be + * running. If this null loop is reached then it is likely there was + * insufficient FreeRTOS heap available for the idle task and/or timer task to + * be created. See http://www.freertos.org/a00111.html. */ + for( ; ; ) + { + } + } /*-----------------------------------------------------------*/ -static void prvCheckTimerCallback( TimerHandle_t xTimer ) -{ -static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS; -static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL; - - /* Remove compiler warnings about unused parameters. */ - ( void ) xTimer; - - /* Check the standard demo tasks are running without error. */ - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - lErrorStatus = pdFAIL; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - lErrorStatus = pdFAIL; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - lErrorStatus = pdFAIL; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - lErrorStatus = pdFAIL; - } - - /* Check the reg test tasks are still cycling. They will stop incrementing - their loop counters if they encounter an error. */ - if( ulRegTest1CycleCount == ulLastRegTest1CycleCount ) - { - lErrorStatus = pdFAIL; - } - - if( ulRegTest2CycleCount == ulLastRegTest2CycleCount ) - { - lErrorStatus = pdFAIL; - } - - /* Remember the loop counter values this time around so they can be checked - again the next time this callback function executes. */ - ulLastRegTest1CycleCount = ulRegTest1CycleCount; - ulLastRegTest2CycleCount = ulRegTest2CycleCount; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every three seconds then everything is ok. A faster toggle - indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - /* Was an error detected this time through the callback execution? */ - if( lErrorStatus != pdPASS ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } -} + static void prvCheckTimerCallback( TimerHandle_t xTimer ) + { + static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS; + static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL; + + /* Remove compiler warnings about unused parameters. */ + ( void ) xTimer; + + /* Check the standard demo tasks are running without error. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + lErrorStatus = pdFAIL; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + lErrorStatus = pdFAIL; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + lErrorStatus = pdFAIL; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + lErrorStatus = pdFAIL; + } + + /* Check the reg test tasks are still cycling. They will stop incrementing + * their loop counters if they encounter an error. */ + if( ulRegTest1CycleCount == ulLastRegTest1CycleCount ) + { + lErrorStatus = pdFAIL; + } + + if( ulRegTest2CycleCount == ulLastRegTest2CycleCount ) + { + lErrorStatus = pdFAIL; + } + + /* Remember the loop counter values this time around so they can be checked + * again the next time this callback function executes. */ + ulLastRegTest1CycleCount = ulRegTest1CycleCount; + ulLastRegTest2CycleCount = ulRegTest2CycleCount; + + /* Toggle the check LED to give an indication of the system status. If + * the LED toggles every three seconds then everything is ok. A faster toggle + * indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + /* Was an error detected this time through the callback execution? */ + if( lErrorStatus != pdPASS ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + * Functions called from inside of a timer callback function must + * never* attempt to block. */ + xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } + } /*-----------------------------------------------------------*/ /* This function is explained in the comments at the top of this file. */ -static void prvRegTest1Task( void *pvParameters ) -{ - if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER ) - { - /* The parameter did not contain the expected value. */ - for( ;; ) - { - /* Stop the tick interrupt so its obvious something has gone wrong. */ - taskDISABLE_INTERRUPTS(); - } - } - - /* This is an inline asm function that never returns. */ - vRegTest1Implementation(); -} + static void prvRegTest1Task( void * pvParameters ) + { + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ; ; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest1Implementation(); + } /*-----------------------------------------------------------*/ /* This function is explained in the comments at the top of this file. */ -static void prvRegTest2Task( void *pvParameters ) -{ - if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER ) - { - /* The parameter did not contain the expected value. */ - for( ;; ) - { - /* Stop the tick interrupt so its obvious something has gone wrong. */ - taskDISABLE_INTERRUPTS(); - } - } - - /* This is an inline asm function that never returns. */ - vRegTest2Implementation(); -} + static void prvRegTest2Task( void * pvParameters ) + { + if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ; ; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest2Implementation(); + } /*-----------------------------------------------------------*/ #endif /* configCREATE_LOW_POWER_DEMO */ diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c b/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c index 20f9f68df02..d22bd3ead6a 100644 --- a/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c +++ b/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -122,43 +122,43 @@ #include "partest.h" /* Priorities at which the Rx and Tx tasks are created. */ -#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) /* The number of items the queue can hold. This is 1 as the Rx task will -remove items as they are added so the Tx task should always find the queue -empty. */ -#define mainQUEUE_LENGTH ( 1 ) + * remove items as they are added so the Tx task should always find the queue + * empty. */ +#define mainQUEUE_LENGTH ( 1 ) /* The LED used to indicate that a value has been received on the queue. */ -#define mainQUEUE_LED ( 0 ) +#define mainQUEUE_LED ( 0 ) /* The LED used to indicate that full power is being used (the MCU is not in -deep sleep or software standby mode). */ -#define mainFULL_POWER_LED ( 1 ) + * deep sleep or software standby mode). */ +#define mainFULL_POWER_LED ( 1 ) /* The LED used to indicate that deep sleep mode is being used. */ -#define mainDEEP_SLEEP_LED ( 2 ) +#define mainDEEP_SLEEP_LED ( 2 ) /* The Tx task sends to the queue with a frequency that is set by the value -read from the potentiometer until the value goes above that set by the -mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks -indefinitely on a semaphore. */ -#define mainSOFTWARE_STANDBY_DELAY ( 3000UL ) + * read from the potentiometer until the value goes above that set by the + * mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks + * indefinitely on a semaphore. */ +#define mainSOFTWARE_STANDBY_DELAY ( 3000UL ) /* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0 ) +#define mainDONT_BLOCK ( 0 ) /* The value that is sent from the Tx task to the Rx task on the queue. */ -#define mainQUEUED_VALUE ( 100UL ) +#define mainQUEUED_VALUE ( 100UL ) /*-----------------------------------------------------------*/ /* * The Rx and Tx tasks as described at the top of this file. */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); /* * Reads and returns the value of the ADC connected to the potentiometer built @@ -183,207 +183,209 @@ static SemaphoreHandle_t xSemaphore = NULL; void main_low_power( void ) { - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - configASSERT( xQueue ); - - /* Create the semaphore that is 'given' by an interrupt generated from a - button push. */ - vSemaphoreCreateBinary( xSemaphore ); - configASSERT( xSemaphore ); - - /* Make sure the semaphore starts in the expected state - no button pushes - have yet occurred. A block time of zero can be used as it is guaranteed - that the semaphore will be available because it has just been created. */ - xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); - - /* Start the two tasks as described at the top of this file. */ - xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL ); - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* The CPU is currently running, not sleeping, so turn on the LED that - shows the CPU is not in a sleep mode. */ - vParTestSetLED( mainFULL_POWER_LED, pdTRUE ); - - /* Start the scheduler running running. */ - vTaskStartScheduler(); - - /* If all is well the next line of code will not be reached as the - scheduler will be running. If the next line is reached then it is likely - there was insufficient FreeRTOS heap available for the idle task and/or - timer task to be created. See http://www.freertos.org/a00111.html. */ - for( ;; ); + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + configASSERT( xQueue ); + + /* Create the semaphore that is 'given' by an interrupt generated from a + * button push. */ + vSemaphoreCreateBinary( xSemaphore ); + configASSERT( xSemaphore ); + + /* Make sure the semaphore starts in the expected state - no button pushes + * have yet occurred. A block time of zero can be used as it is guaranteed + * that the semaphore will be available because it has just been created. */ + xSemaphoreTake( xSemaphore, mainDONT_BLOCK ); + + /* Start the two tasks as described at the top of this file. */ + xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL ); + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* The CPU is currently running, not sleeping, so turn on the LED that + * shows the CPU is not in a sleep mode. */ + vParTestSetLED( mainFULL_POWER_LED, pdTRUE ); + + /* Start the scheduler running running. */ + vTaskStartScheduler(); + + /* If all is well the next line of code will not be reached as the + * scheduler will be running. If the next line is reached then it is likely + * there was insufficient FreeRTOS heap available for the idle task and/or + * timer task to be created. See http://www.freertos.org/a00111.html. */ + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ -static void prvQueueSendTask( void *pvParameters ) +static void prvQueueSendTask( void * pvParameters ) { -TickType_t xDelay; -const unsigned long ulValueToSend = mainQUEUED_VALUE; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* The delay period between successive sends to the queue is set by - the potentiometer reading. */ - xDelay = ( TickType_t ) prvReadPOT(); - - /* If the block time is greater than 3000 milliseconds then block - indefinitely waiting for a button push. */ - if( xDelay > mainSOFTWARE_STANDBY_DELAY ) - { - /* As this is an indefinite delay the kernel will place the CPU - into software standby mode the next time the idle task runs. */ - xSemaphoreTake( xSemaphore, portMAX_DELAY ); - } - else - { - /* Convert a time in milliseconds to a time in ticks. */ - xDelay /= portTICK_PERIOD_MS; - - /* Place this task in the blocked state until it is time to run - again. As this is not an indefinite sleep the kernel will place - the CPU into the deep sleep state when the idle task next runs. */ - vTaskDelay( xDelay ); - } - - /* Send to the queue - causing the queue receive task to flash its LED. - It should not be necessary to block on the queue send because the Rx - task will have removed the last queued item. */ - xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); - } + TickType_t xDelay; + const unsigned long ulValueToSend = mainQUEUED_VALUE; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* The delay period between successive sends to the queue is set by + * the potentiometer reading. */ + xDelay = ( TickType_t ) prvReadPOT(); + + /* If the block time is greater than 3000 milliseconds then block + * indefinitely waiting for a button push. */ + if( xDelay > mainSOFTWARE_STANDBY_DELAY ) + { + /* As this is an indefinite delay the kernel will place the CPU + * into software standby mode the next time the idle task runs. */ + xSemaphoreTake( xSemaphore, portMAX_DELAY ); + } + else + { + /* Convert a time in milliseconds to a time in ticks. */ + xDelay /= portTICK_PERIOD_MS; + + /* Place this task in the blocked state until it is time to run + * again. As this is not an indefinite sleep the kernel will place + * the CPU into the deep sleep state when the idle task next runs. */ + vTaskDelay( xDelay ); + } + + /* Send to the queue - causing the queue receive task to flash its LED. + * It should not be necessary to block on the queue send because the Rx + * task will have removed the last queued item. */ + xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK ); + } } /*-----------------------------------------------------------*/ -static void prvQueueReceiveTask( void *pvParameters ) +static void prvQueueReceiveTask( void * pvParameters ) { -unsigned long ulReceivedValue; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have arrived, but is it the expected - value? If it is, toggle the LED. */ - if( ulReceivedValue == mainQUEUED_VALUE ) - { - vParTestToggleLED( mainQUEUE_LED ); - } - } + unsigned long ulReceivedValue; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have arrived, but is it the expected + * value? If it is, toggle the LED. */ + if( ulReceivedValue == mainQUEUED_VALUE ) + { + vParTestToggleLED( mainQUEUE_LED ); + } + } } /*-----------------------------------------------------------*/ void vPreSleepProcessing( unsigned long ulExpectedIdleTime ) { - /* Called by the kernel before it places the MCU into a sleep mode because - configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing(). - - NOTE: Additional actions can be taken here to get the power consumption - even lower. For example, the ADC input used by this demo could be turned - off here, and then back on again in the post sleep processing function. - For maximum power saving ensure all unused pins are in their lowest power - state. */ - - /* Avoid compiler warnings about the unused parameter. */ - ( void ) ulExpectedIdleTime; - - /* Is the MCU about to enter deep sleep mode or software standby mode? */ - if( SYSTEM.SBYCR.BIT.SSBY == 0 ) - { - /* Turn on the LED that indicates deep sleep mode is being entered. */ - vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE ); - } - else - { - /* Software standby mode is being used, so no LEDs are illuminated to - ensure minimum power readings are obtained. Ensure the Queue LED is - also off. */ - vParTestSetLED( mainQUEUE_LED, pdFALSE ); - } - - /* Turn off the LED that indicates full power is being used. */ - vParTestSetLED( mainFULL_POWER_LED, pdFALSE ); + /* Called by the kernel before it places the MCU into a sleep mode because + * configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing(). + * + * NOTE: Additional actions can be taken here to get the power consumption + * even lower. For example, the ADC input used by this demo could be turned + * off here, and then back on again in the post sleep processing function. + * For maximum power saving ensure all unused pins are in their lowest power + * state. */ + + /* Avoid compiler warnings about the unused parameter. */ + ( void ) ulExpectedIdleTime; + + /* Is the MCU about to enter deep sleep mode or software standby mode? */ + if( SYSTEM.SBYCR.BIT.SSBY == 0 ) + { + /* Turn on the LED that indicates deep sleep mode is being entered. */ + vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE ); + } + else + { + /* Software standby mode is being used, so no LEDs are illuminated to + * ensure minimum power readings are obtained. Ensure the Queue LED is + * also off. */ + vParTestSetLED( mainQUEUE_LED, pdFALSE ); + } + + /* Turn off the LED that indicates full power is being used. */ + vParTestSetLED( mainFULL_POWER_LED, pdFALSE ); } /*-----------------------------------------------------------*/ void vPostSleepProcessing( unsigned long ulExpectedIdleTime ) { - /* Called by the kernel when the MCU exits a sleep mode because - configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */ + /* Called by the kernel when the MCU exits a sleep mode because + * configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */ - /* Avoid compiler warnings about the unused parameter. */ - ( void ) ulExpectedIdleTime; + /* Avoid compiler warnings about the unused parameter. */ + ( void ) ulExpectedIdleTime; - /* Turn off the LED that indicates deep sleep mode, and turn on the LED - that indicates full power is being used. */ - vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE ); - vParTestSetLED( mainFULL_POWER_LED, pdTRUE ); + /* Turn off the LED that indicates deep sleep mode, and turn on the LED + * that indicates full power is being used. */ + vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE ); + vParTestSetLED( mainFULL_POWER_LED, pdTRUE ); } /*-----------------------------------------------------------*/ static unsigned short prvReadPOT( void ) { -unsigned short usADCValue; -const unsigned short usMinADCValue = 128; - - /* Start an ADC scan. */ - S12AD.ADCSR.BIT.ADST = 1; - while( S12AD.ADCSR.BIT.ADST == 1 ) - { - /* Just waiting for the ADC scan to complete. Inefficient - polling! */ - } - - usADCValue = S12AD.ADDR4; - - /* Don't let the ADC value get too small as the LED behaviour will look - erratic. */ - if( usADCValue < usMinADCValue ) - { - usADCValue = usMinADCValue; - } - - return usADCValue; + unsigned short usADCValue; + const unsigned short usMinADCValue = 128; + + /* Start an ADC scan. */ + S12AD.ADCSR.BIT.ADST = 1; + + while( S12AD.ADCSR.BIT.ADST == 1 ) + { + /* Just waiting for the ADC scan to complete. Inefficient + * polling! */ + } + + usADCValue = S12AD.ADDR4; + + /* Don't let the ADC value get too small as the LED behaviour will look + * erratic. */ + if( usADCValue < usMinADCValue ) + { + usADCValue = usMinADCValue; + } + + return usADCValue; } /*-----------------------------------------------------------*/ #pragma vector = VECT_ICU_IRQ0, VECT_ICU_IRQ1, VECT_ICU_IRQ4 __interrupt void vButtonInterrupt1( void ) { -long lHigherPriorityTaskWoken = pdFALSE; - - /* The semaphore is only created when the build is configured to create the - low power demo. */ - if( xSemaphore != NULL ) - { - /* This interrupt will bring the CPU out of deep sleep and software - standby modes. Give the semaphore that was used to place the Tx task - into an indefinite sleep. */ - if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 ) - { - xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken ); - } - else - { - /* The semaphore was already available, so the task is not blocked - on it and there is no point giving it. */ - } - - /* If giving the semaphore caused a task to leave the Blocked state, - and the task that left the Blocked state has a priority equal to or - above the priority of the task that this interrupt interrupted, then - lHigherPriorityTaskWoken will have been set to pdTRUE inside the call - to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause - a context switch to the unblocked task. */ - portYIELD_FROM_ISR( lHigherPriorityTaskWoken ); - } + long lHigherPriorityTaskWoken = pdFALSE; + + /* The semaphore is only created when the build is configured to create the + * low power demo. */ + if( xSemaphore != NULL ) + { + /* This interrupt will bring the CPU out of deep sleep and software + * standby modes. Give the semaphore that was used to place the Tx task + * into an indefinite sleep. */ + if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 ) + { + xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken ); + } + else + { + /* The semaphore was already available, so the task is not blocked + * on it and there is no point giving it. */ + } + + /* If giving the semaphore caused a task to leave the Blocked state, + * and the task that left the Blocked state has a priority equal to or + * above the priority of the task that this interrupt interrupted, then + * lHigherPriorityTaskWoken will have been set to pdTRUE inside the call + * to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause + * a context switch to the unblocked task. */ + portYIELD_FROM_ISR( lHigherPriorityTaskWoken ); + } } - diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h index 69310f5f5a0..5be83a217d6 100644 --- a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c index 72ae59ef0f3..f3cc76a3a7c 100644 --- a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c +++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c index 767c58ca430..480e7437c2f 100644 --- a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c +++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c index 9b306c6fce4..11a0fccc40d 100644 --- a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c +++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c index 1f0e1817f25..2288f7812d3 100644 --- a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c +++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c index c390230c615..49d10398a70 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index 1e7a9912a17..29f838e8557 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index 595bd9bd310..cadb773adc9 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c index 2a5b8a0f1d8..100845c8c2a 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h index 619752578e0..8c5f632e6ec 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/main.c index 27c1f24c594..83a24c3d7a0 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_GCC_e2studio_IAR/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c index c390230c615..49d10398a70 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h index 8867fd1ee09..a16d5eb6d61 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c index e67c978b0eb..9d6109da5ea 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c index 02642be01c1..090105bc740 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/main.c index 41eb478b5d8..a46ebac462f 100644 --- a/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/main.c +++ b/FreeRTOS/Demo/RX100_RX113-RSK_Renesas_e2studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ButtonAndLCD.c b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ButtonAndLCD.c index 2f0f7fd2b69..f0969de0aca 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ButtonAndLCD.c +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ButtonAndLCD.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h index 8ef845cd994..3866f2f7818 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c index 88daf86ab01..5a5f62d994e 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/IntQueueTimer.c index ce1fe905986..e707bd2e922 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ParTest.c b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ParTest.c index 0b84dd9a665..a23e025050a 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ParTest.c +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/ButtonAndLCD.h b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/ButtonAndLCD.h index 42ab28a71ba..590a6ba9b5b 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/ButtonAndLCD.h +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/ButtonAndLCD.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-blinky.c b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-blinky.c index 98f79a42131..9055885dc61 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-blinky.c +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-full.c b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-full.c index 9d2815a2710..251973c126a 100644 --- a/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-full.c +++ b/FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c index 877d603cb3e..369f741e392 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index 50205726a49..3b5fab85c4f 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index b40a5fa8d1d..9e588307063 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c index c53fd1f8cba..62df37472d2 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h index 619752578e0..8c5f632e6ec 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c index fee383e0de5..2259baeb95b 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c index 877d603cb3e..369f741e392 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h index 313fdfd1f58..621eec69c51 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c index 1d278f25dc3..5a9d946b882 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c index f930a61374d..71b62394c24 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c index 69e2b747667..3da55b28dad 100644 --- a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h index 0d46a75b0b7..9e3dcdb27af 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c index 88daf86ab01..5a5f62d994e 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/HighFrequencyTimerTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c index ce1fe905986..e707bd2e922 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c index 0b84dd9a665..a23e025050a 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/include/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c index 8f3e30b3b41..b3bab791c0c 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -19,8 +19,8 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS * */ diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c index c10a5b9a8cc..e67cb76119e 100644 --- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c +++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/main-full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/FreeRTOSConfig.h index 1c71cb65358..71bfabd8ed8 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.c b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.c index ce35edd3bfb..9818b398fbc 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.h b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/ParTest.c b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/ParTest.c index 2835d56ca58..3b9110d6ad9 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/ParTest.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main.c b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main.c index 22067bb8d3b..91d6e452133 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_blinky.c b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_blinky.c index 77e56bd8ed2..662587aba38 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_blinky.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_full.c b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_full.c index 7b949a15a8b..09189f93c9d 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_full.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/FreeRTOSConfig.h b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/FreeRTOSConfig.h index 1c71cb65358..71bfabd8ed8 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.c b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.c index 103197cdcb5..96c1b9b3e40 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.h b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.h index 4fb214c4093..dc540323649 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/ParTest.c b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/ParTest.c index c1f6b2db94a..ea36c0dbd21 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/ParTest.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main.c b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main.c index d548f4d32b8..c24e4a992d3 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_blinky.c b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_blinky.c index 77e56bd8ed2..662587aba38 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_blinky.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_full.c b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_full.c index 00bd999961a..8509ec078ab 100644 --- a/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_full.c +++ b/FreeRTOS/Demo/RX600_RX64M_RSK_Renesas_e2studio/Source/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c index 6af776b2262..26d6a89ff47 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index e122b0dcfa4..4563da077b8 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index 8726b6e021f..f01179528ba 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c index 25450e1de9f..d6009220e5d 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h index 619752578e0..8c5f632e6ec 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c index f87ddeae061..4580fbd9d75 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c index 6af776b2262..26d6a89ff47 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h index 3759cf111b6..456e710045c 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c index d43f9f1b8e0..dc28b74e6c7 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h index 76d462f796c..8f1a766766e 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c index 4b4af75e8da..645d2c058ec 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c index ea8d075ed81..34eb54e5125 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c index 1a2a4dd5c36..7dccf30842e 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c index 65243e53af4..e945e1858f0 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h index a3fe268cf8d..3b9f6729476 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c index 64fbed10bc1..08cd9f6e491 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c index a2468dbc7d6..e1002e695eb 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h index 8b44fb16de4..5ff63166ca6 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h index 91cbfd6e0fa..b39827e5ef5 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c index 1a2a4dd5c36..7dccf30842e 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c index 65243e53af4..e945e1858f0 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h index a3fe268cf8d..3b9f6729476 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c index 64fbed10bc1..08cd9f6e491 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c index a2468dbc7d6..e1002e695eb 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h index 8b44fb16de4..5ff63166ca6 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h index 91cbfd6e0fa..b39827e5ef5 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c index 1a2a4dd5c36..7dccf30842e 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c index 65243e53af4..e945e1858f0 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h index a3fe268cf8d..3b9f6729476 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c index 64fbed10bc1..08cd9f6e491 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c index a2468dbc7d6..e1002e695eb 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h index 8b44fb16de4..5ff63166ca6 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h index 91cbfd6e0fa..b39827e5ef5 100644 --- a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.c b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.c index a80ae326d8e..bfe747b6618 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.c +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.h b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.h index 25498a05309..7698485c6b6 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.h +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/interrupt_handler_task.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.c b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.c index 2a8dcebfb20..f9f15cc00a7 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.c +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.h b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.h index ed6ccb8922a..a2a59de3c19 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.h +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/led_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/main.c b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/main.c index 7b34a7d615b..da3e0977ba7 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/main.c +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.c b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.c index 283b7356161..0d2d6060ead 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.c +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.h b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.h index c930083c3d8..de6d6592c99 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.h +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Application/uart_demo.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Config/FreeRTOSConfig.h index 1b936bf92c2..0e29284bd8c 100644 --- a/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/Config/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/T-HEAD_CB2201_CDK/FreeRTOSConfig.h b/FreeRTOS/Demo/T-HEAD_CB2201_CDK/FreeRTOSConfig.h index 270e4daf0fd..438ba43739b 100644 --- a/FreeRTOS/Demo/T-HEAD_CB2201_CDK/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/T-HEAD_CB2201_CDK/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.project b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.project deleted file mode 100644 index 51db76b71e1..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.project +++ /dev/null @@ -1,382 +0,0 @@ - - - RTOSDemo - - - XtensaInfo - - - - com.tensilica.xide.cdt.xtensamanagedbuilder - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - com.tensilica.xide.cdt.XtensaCProjectNature - com.tensilica.xide.cdt.XtensaCProjectExeNature - com.tensilica.xide.cdt.XideManagedProjectNature - - - - CommonDemoTasks - 2 - virtual:/virtual - - - FreeRTOS_Source - 2 - virtual:/virtual - - - CommonDemoTasks/AbortDelay.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/AbortDelay.c - - - CommonDemoTasks/BlockQ.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/BlockQ.c - - - CommonDemoTasks/EventGroupsDemo.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/EventGroupsDemo.c - - - CommonDemoTasks/GenQTest.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/GenQTest.c - - - CommonDemoTasks/IntQueue.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/IntQueue.c - - - CommonDemoTasks/IntSemTest.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/IntSemTest.c - - - CommonDemoTasks/MessageBufferDemo.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/MessageBufferDemo.c - - - CommonDemoTasks/PollQ.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/PollQ.c - - - CommonDemoTasks/QPeek.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/QPeek.c - - - CommonDemoTasks/QueueOverwrite.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/QueueOverwrite.c - - - CommonDemoTasks/QueueSet.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/QueueSet.c - - - CommonDemoTasks/QueueSetPolling.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/QueueSetPolling.c - - - CommonDemoTasks/StaticAllocation.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/StaticAllocation.c - - - CommonDemoTasks/StreamBufferDemo.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/StreamBufferDemo.c - - - CommonDemoTasks/StreamBufferInterrupt.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/StreamBufferInterrupt.c - - - CommonDemoTasks/TaskNotify.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/TaskNotify.c - - - CommonDemoTasks/TimerDemo.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/TimerDemo.c - - - CommonDemoTasks/blocktim.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/blocktim.c - - - CommonDemoTasks/countsem.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/countsem.c - - - CommonDemoTasks/death.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/death.c - - - CommonDemoTasks/flop.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/flop.c - - - CommonDemoTasks/include - 2 - PARENT-1-PROJECT_LOC/Common/include - - - CommonDemoTasks/integer.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/integer.c - - - CommonDemoTasks/recmutex.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/recmutex.c - - - CommonDemoTasks/semtest.c - 1 - PARENT-1-PROJECT_LOC/Common/Minimal/semtest.c - - - FreeRTOS_Source/event_groups.c - 1 - PARENT-2-PROJECT_LOC/Source/event_groups.c - - - FreeRTOS_Source/include - 2 - virtual:/virtual - - - FreeRTOS_Source/list.c - 1 - PARENT-2-PROJECT_LOC/Source/list.c - - - FreeRTOS_Source/portable - 2 - virtual:/virtual - - - FreeRTOS_Source/queue.c - 1 - PARENT-2-PROJECT_LOC/Source/queue.c - - - FreeRTOS_Source/readme.txt - 1 - PARENT-2-PROJECT_LOC/Source/readme.txt - - - FreeRTOS_Source/stream_buffer.c - 1 - PARENT-2-PROJECT_LOC/Source/stream_buffer.c - - - FreeRTOS_Source/tasks.c - 1 - PARENT-2-PROJECT_LOC/Source/tasks.c - - - FreeRTOS_Source/timers.c - 1 - PARENT-2-PROJECT_LOC/Source/timers.c - - - FreeRTOS_Source/include/FreeRTOS.h - 1 - PARENT-2-PROJECT_LOC/Source/include/FreeRTOS.h - - - FreeRTOS_Source/include/event_groups.h - 1 - PARENT-2-PROJECT_LOC/Source/include/event_groups.h - - - FreeRTOS_Source/include/list.h - 1 - PARENT-2-PROJECT_LOC/Source/include/list.h - - - FreeRTOS_Source/include/message_buffer.h - 1 - PARENT-2-PROJECT_LOC/Source/include/message_buffer.h - - - FreeRTOS_Source/include/mpu_prototypes.h - 1 - PARENT-2-PROJECT_LOC/Source/include/mpu_prototypes.h - - - FreeRTOS_Source/include/mpu_wrappers.h - 1 - PARENT-2-PROJECT_LOC/Source/include/mpu_wrappers.h - - - FreeRTOS_Source/include/portable.h - 1 - PARENT-2-PROJECT_LOC/Source/include/portable.h - - - FreeRTOS_Source/include/projdefs.h - 1 - PARENT-2-PROJECT_LOC/Source/include/projdefs.h - - - FreeRTOS_Source/include/queue.h - 1 - PARENT-2-PROJECT_LOC/Source/include/queue.h - - - FreeRTOS_Source/include/semphr.h - 1 - PARENT-2-PROJECT_LOC/Source/include/semphr.h - - - FreeRTOS_Source/include/stream_buffer.h - 1 - PARENT-2-PROJECT_LOC/Source/include/stream_buffer.h - - - FreeRTOS_Source/include/task.h - 1 - PARENT-2-PROJECT_LOC/Source/include/task.h - - - FreeRTOS_Source/include/timers.h - 1 - PARENT-2-PROJECT_LOC/Source/include/timers.h - - - FreeRTOS_Source/portable/MemMang - 2 - virtual:/virtual - - - FreeRTOS_Source/portable/XCC - 2 - virtual:/virtual - - - FreeRTOS_Source/portable/MemMang/heap_4.c - 1 - PARENT-2-PROJECT_LOC/Source/portable/MemMang/heap_4.c - - - FreeRTOS_Source/portable/XCC/port.c - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/port.c - - - FreeRTOS_Source/portable/XCC/portasm.S - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/portasm.S - - - FreeRTOS_Source/portable/XCC/portbenchmark.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h - - - FreeRTOS_Source/portable/XCC/portclib.c - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/portclib.c - - - FreeRTOS_Source/portable/XCC/portmacro.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h - - - FreeRTOS_Source/portable/XCC/porttrace.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h - - - FreeRTOS_Source/portable/XCC/readme_xtensa.txt - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt - - - FreeRTOS_Source/portable/XCC/xtensa_api.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h - - - FreeRTOS_Source/portable/XCC/xtensa_config.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h - - - FreeRTOS_Source/portable/XCC/xtensa_context.S - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S - - - FreeRTOS_Source/portable/XCC/xtensa_context.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h - - - FreeRTOS_Source/portable/XCC/xtensa_init.c - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c - - - FreeRTOS_Source/portable/XCC/xtensa_intr.c - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c - - - FreeRTOS_Source/portable/XCC/xtensa_intr_asm.S - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S - - - FreeRTOS_Source/portable/XCC/xtensa_overlay_os_hook.c - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c - - - FreeRTOS_Source/portable/XCC/xtensa_rtos.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h - - - FreeRTOS_Source/portable/XCC/xtensa_timer.h - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h - - - FreeRTOS_Source/portable/XCC/xtensa_vectors.S - 1 - PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S - - - diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.settings/targets/xtensa/CommonTarget.bts b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.settings/targets/xtensa/CommonTarget.bts deleted file mode 100644 index 430333b7cb0..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.settings/targets/xtensa/CommonTarget.bts +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.settings/targets/xtensa/Debug.bts b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.settings/targets/xtensa/Debug.bts deleted file mode 100644 index 9a6fd1fadcd..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.settings/targets/xtensa/Debug.bts +++ /dev/null @@ -1,52 +0,0 @@ - - - - - - - - Includes - - ${workspace_loc:RTOSDemo/FreeRTOS_Source/include} - ${workspace_loc:RTOSDemo/FreeRTOS_Source/portable/XCC} - ${workspace_loc:RTOSDemo} - - - - - - - - Optimization - - - - Debug - - - - - - - - AssemblerIncludeDebug - - - - AssemblerLongCall - - - - - - - - CreateMinsize - - - - - - - - diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.xxproject b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.xxproject deleted file mode 100644 index 06a21cd9d31..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/.xxproject +++ /dev/null @@ -1,21 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/FreeRTOSConfig.h b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/FreeRTOSConfig.h deleted file mode 100644 index c2b48f97f81..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/FreeRTOSConfig.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - - -/* Required for configuration-dependent settings. */ -#include "xtensa_config.h" - -/*--------------------------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *--------------------------------------------------------------------------- - */ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 - -#ifdef SMALL_TEST - #define configUSE_TICK_HOOK 0 -#else - #define configUSE_TICK_HOOK 1 -#endif - -#define configTICK_RATE_HZ ( 1000 ) - -/* Default clock rate for simulator */ -#define configCPU_CLOCK_HZ 10000000 - -/* Max possible priorities. */ -#define configMAX_PRIORITIES ( 7 ) - -/** - * Minimal stack size. This may need to be increased for your application. - * - * @note: The FreeRTOS demos may not work reliably with stack size < 4KB. The - * Xtensa-specific examples should be fine with XT_STACK_MIN_SIZE. - * - * @note: The size is defined in terms of StackType_t units not bytes. - */ -#if !( defined XT_STACK_MIN_SIZE ) - #error XT_STACK_MIN_SIZE not defined, did you include xtensa_config.h ? -#endif - -#ifdef SMALL_TEST - #define configMINIMAL_STACK_SIZE ( XT_STACK_MIN_SIZE / sizeof( StackType_t ) ) -#else - #define configMINIMAL_STACK_SIZE ( XT_STACK_MIN_SIZE > 1024 ? XT_STACK_MIN_SIZE : 1024 ) -#endif - -/** - * The Xtensa port uses a separate interrupt stack. Adjust the stack size to - * suit the needs of your specific application. - * - * @note: the size is defined in bytes. - */ -#ifndef configISR_STACK_SIZE - #define configISR_STACK_SIZE 2048 -#endif - -/** - * Minimal heap size to make sure examples can run on memory limited configs. - * Adjust this to suit your system. - */ -#ifdef SMALL_TEST - #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) -#else - #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 512 * 1024 ) ) -#endif - -#define configMAX_TASK_NAME_LEN ( 8 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 -#define configUSE_TRACE_FACILITY_2 0 /* Provided by Xtensa port patch. */ -#define configBENCHMARK 0 /* Provided by Xtensa port patch. */ -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configQUEUE_REGISTRY_SIZE 0 - -#ifdef SMALL_TEST - #define configUSE_MUTEXES 1 - #define configUSE_RECURSIVE_MUTEXES 1 - #define configUSE_COUNTING_SEMAPHORES 1 - #define configCHECK_FOR_STACK_OVERFLOW 0 -#else - #define configUSE_MUTEXES 1 - #define configUSE_RECURSIVE_MUTEXES 1 - #define configUSE_COUNTING_SEMAPHORES 1 - #define configCHECK_FOR_STACK_OVERFLOW 2 -#endif - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/** - * Set the following definitions to 1 to include the API function, or zero to - * exclude the API function. - */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_xTaskAbortDelay 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 - -/** - * The priority at which the tick interrupt runs. This should probably be kept - * at 1. - */ -#define configKERNEL_INTERRUPT_PRIORITY 1 - -/** - * The maximum interrupt priority from which FreeRTOS.org API functions can be - * called. Only API functions that end in ...FromISR() can be used within - * interrupts. - */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL - -/** - * XT_USE_THREAD_SAFE_CLIB is defined in xtensa_config.h and can be overridden - * from the compiler/make command line. The small test however always disables C - * lib thread safety to minimize size. - */ -#ifdef SMALL_TEST - #define configUSE_NEWLIB_REENTRANT 0 -#else - #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) - #if XT_HAVE_THREAD_SAFE_CLIB - #define configUSE_NEWLIB_REENTRANT 0 - #else - #error "Error: thread-safe C library support not available for this C library." - #endif - #else - #define configUSE_NEWLIB_REENTRANT 0 - #endif -#endif - -/* Test FreeRTOS timers (with timer task) and more. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) -#define configTIMER_QUEUE_LENGTH 10 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -#ifdef SMALL_TEST - #define INCLUDE_xTimerPendFunctionCall 0 - #define INCLUDE_eTaskGetState 0 - #define configUSE_QUEUE_SETS 0 -#else - #define INCLUDE_xTimerPendFunctionCall 1 - #define INCLUDE_eTaskGetState 1 - #define configUSE_QUEUE_SETS 1 -#endif - -/** - * Specific config for XTENSA (these can be deleted and they will take default - * values). - */ -#if ( !defined XT_SIMULATOR ) && ( !defined XT_BOARD ) - #define configXT_SIMULATOR 1 /* Simulator mode. */ - #define configXT_BOARD 0 /* Board mode. */ -#endif - -#ifndef SMALL_TEST - #if ( !defined XT_INTEXC_HOOKS ) - #define configXT_INTEXC_HOOKS 1 /* Exception hooks used by certain tests. */ - #endif - - #if configUSE_TRACE_FACILITY_2 - #define configASSERT_2 1 /* Specific to Xtensa port. */ - #endif -#endif - -/** - * It is a good idea to define configASSERT() while developing. configASSERT() - * uses the same semantics as the standard C assert() macro. - */ -#if !defined __ASSEMBLER__ - extern void vAssertCalled( unsigned long ulLine, const char * const pcFileName ); -#endif -#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ ) - -#define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN ( 2 ) /* Used by stream buffer tests. */ - -#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/IntQueueTimer.c b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/IntQueueTimer.c deleted file mode 100644 index d48742f3e53..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/IntQueueTimer.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "IntQueueTimer.h" -#include "IntQueue.h" - -/* Xtensa includes. */ -#include -#include -#include -#include -/*-----------------------------------------------------------*/ - -/* Check if Timer1 is available. */ -#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED - #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL - #define SECOND_TIMER_AVAILABLE 1 - #endif -#endif - -#ifndef SECOND_TIMER_AVAILABLE - #define SECOND_TIMER_AVAILABLE 0 -#endif - -/** - * Timer0 is used to drive systick and therefore we use Timer1 - * as second interrupt which runs on a higher priority than - * Timer0. This ensures that systick will get interrupted by - * this timer and hence we can test interrupt nesting. - */ -#define SECOND_TIMER_INDEX 1 - -/** - * Frequency of the second timer - This timer is configured at - * a frequency offset of 17 from the systick timer. - */ -#define SECOND_TIMER_TICK_RATE_HZ ( configTICK_RATE_HZ + 17 ) -#define SECOND_TIMER_TICK_DIVISOR ( configCPU_CLOCK_HZ / SECOND_TIMER_TICK_RATE_HZ ) -/*-----------------------------------------------------------*/ - -/* Defined in main_full.c. */ -extern BaseType_t xTimerForQueueTestInitialized; -/*-----------------------------------------------------------*/ - -/** - * Interrupt handler for timer interrupt. - */ -#if( SECOND_TIMER_AVAILABLE == 1 ) - static void prvTimer2Handler( void *arg ); -#endif /* SECOND_TIMER_AVAILABLE */ -/*-----------------------------------------------------------*/ - -void vInitialiseTimerForIntQueueTest( void ) -{ -unsigned currentCycleCount, firstComparatorValue; - - /* Inform the tick hook function that it can access queues now. */ - xTimerForQueueTestInitialized = pdTRUE; - - #if( SECOND_TIMER_AVAILABLE == 1 ) - { - /* Install the interrupt handler for second timer. */ - xt_set_interrupt_handler( XCHAL_TIMER1_INTERRUPT, prvTimer2Handler, NULL ); - - /* Read the current cycle count. */ - currentCycleCount = xthal_get_ccount(); - - /* Calculate time of the first timer interrupt. */ - firstComparatorValue = currentCycleCount + SECOND_TIMER_TICK_DIVISOR; - - /* Set the comparator. */ - xthal_set_ccompare( SECOND_TIMER_INDEX, firstComparatorValue ); - - /* Enable timer interrupt. */ - xt_ints_on( ( 1 << XCHAL_TIMER1_INTERRUPT ) ); - } - #endif /* SECOND_TIMER_AVAILABLE */ -} -/*-----------------------------------------------------------*/ - -/* - * Xtensa timers work by comparing a cycle counter with a preset value. - * Once the match occurs an interrupt is generated, and the handler has - * to set a new cycle count into the comparator. To avoid clock drift - * due to interrupt latency, the new cycle count is computed from the - * old, not the time the interrupt was serviced. However if a timer - * interrupt is ever serviced more than one tick late, it is necessary - * to process multiple ticks until the new cycle count is in the future, - * otherwise the next timer interrupt would not occur until after the - * cycle counter had wrapped (2^32 cycles later). - -do { - ticks++; - old_ccompare = read_ccompare_i(); - write_ccompare_i( old_ccompare + divisor ); - service one tick; - diff = read_ccount() - old_ccompare; -} while ( diff > divisor ); -*/ -#if( SECOND_TIMER_AVAILABLE == 1 ) - - static void prvTimer2Handler( void *arg ) - { - unsigned oldComparatorValue, newComparatorValue, currentCycleCount; - - /* Unused arguments. */ - ( void )arg; - - do - { - /* Read old comparator value. */ - oldComparatorValue = xthal_get_ccompare( SECOND_TIMER_INDEX ); - - /* Calculate the new comparator value. */ - newComparatorValue = oldComparatorValue + SECOND_TIMER_TICK_DIVISOR; - - /* Update comparator and clear interrupt. */ - xthal_set_ccompare( SECOND_TIMER_INDEX, newComparatorValue ); - - /* Process. */ - portYIELD_FROM_ISR( xSecondTimerHandler() ); - - /* Ensure comparator update is complete. */ - xthal_icache_sync(); - - /* Read current cycle count to check if we need to process more - * ticks to catch up. */ - currentCycleCount = xthal_get_ccount(); - - } while( ( currentCycleCount - oldComparatorValue ) > SECOND_TIMER_TICK_DIVISOR ); - } - -#endif /* SECOND_TIMER_AVAILABLE */ -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main.c b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main.c deleted file mode 100644 index 4465540f238..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/****************************************************************************** - * This project provides two demo applications: - * - A simple blinky style demo application. - * - A more comprehensive test and demo application. - * The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY macro is used to select between the two. - * - * The simply blinky demo is implemented and described in the file main_blinky.c. - * The more comprehensive test and demo application is implemented and described - * in the file main_full.c. - * - * This file implements the code that is not demo specific, including the FreeRTOS - * hook functions. - * - ******************************************************************************* - */ - -/* Standard includes. */ -#include -#include - -/* FreeRTOS kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/** - * This project provides two demo applications: - * - A simple blinky style demo application. - * - A more comprehensive test and demo application. - * The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY macro is used to select between the two. - * - * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 then the blinky demo will be - * built. The blinky demo is implemented and described in main_blinky.c. - * - * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0 then the comprehensive test - * and demo application will be built. The comprehensive test and demo application - * is implemented and described in main_full.c. - */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 -/*-----------------------------------------------------------*/ - -/** - * The entry function for the blinky demo application. - * - * This is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - */ -extern void main_blinky( void ); - -/** - * The entry function for the comprehensive test and demo application. - * - * This is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. - */ -extern void main_full( void ); - -/** - * Prototypes for the standard FreeRTOS application hook (callback) functions - * implemented within this file. - * - * @see http://www.freertos.org/a00016.html - */ -void vApplicationMallocFailedHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); -void vApplicationTickHook( void ); - -/** - * The function called from the tick hook. - * - * @note Only the comprehensive demo uses application hook (callback) functions. - * - * @see http://www.freertos.org/a00016.html - */ -void vFullDemoTickHookFunction( void ); -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - * of this file. */ - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - * function that will get called if a call to pvPortMalloc() fails. - * pvPortMalloc() is called internally by the kernel whenever a task, queue, - * timer or semaphore is created. It is also called by various parts of the - * demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then - * the size of the heap available to pvPortMalloc() is defined by - * configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() - * API function can be used to query the size of free heap space that remains - * (although it does not provide information on how the remaining heap might be - * fragmented). See http://www.freertos.org/a00111.html for more information. - */ - vAssertCalled( __LINE__, __FILE__ ); -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - * function is called if a stack overflow is detected. */ - vAssertCalled( __LINE__, __FILE__ ); -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - /* This function will be called by each tick interrupt if - * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - * added here, but the tick hook is called from an interrupt context, so - * code must not attempt to block, and only the interrupt safe FreeRTOS API - * functions can be used (those that end in FromISR()). */ - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - vFullDemoTickHookFunction(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ -} -/*-----------------------------------------------------------*/ - -void vAssertCalled( unsigned long ulLine, const char * const pcFileName ) -{ -static BaseType_t xPrinted = pdFALSE; -volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; - - /* Called if an assertion passed to configASSERT() fails. See - * https://www.FreeRTOS.org/a00110.html#configASSERT for more information. */ - - /* Parameters are not used. */ - ( void ) ulLine; - ( void ) pcFileName; - - taskENTER_CRITICAL(); - { - /* You can step out of this function to debug the assertion by using - * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero - * value. */ - while( ulSetToNonZeroInDebuggerToContinue == 0 ) - { - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - } - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main_blinky.c b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main_blinky.c deleted file mode 100644 index 3b99e3df3eb..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main_blinky.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/****************************************************************************** - * NOTE: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, are defined - * in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, one software timer, and two tasks. It then - * starts the scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. It uses vTaskDelayUntil() to create a periodic task that sends - * the value 100 to the queue every 200 milliseconds. - * - * The Queue Send Software Timer: - * The timer is an auto-reload timer with a period of two seconds. The timer's - * callback function writes the value 200 to the queue. The callback function - * is implemented by prvQueueSendTimerCallback() within this file. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() waits for data to arrive on the queue. - * When data is received, the task checks the value of the data, then outputs a - * message to indicate if the data came from the queue send task or the queue - * send software timer. - * - * Expected Behavior: - * - The queue send task writes to the queue every 200ms, so every 200ms the - * queue receive task will output a message indicating that data was received - * on the queue from the queue send task. - * - The queue send software timer has a period of two seconds, so every two - * seconds the queue receive task will output a message indicating that data - * was received on the queue from the queue send software timer. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "semphr.h" - -/** - * Priorities at which the tasks are created. - */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/** - * The rate at which data is sent to the queue. The times are converted from - * milliseconds to ticks using the pdMS_TO_TICKS() macro. - */ -#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) -#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) - -/** - * The number of items the queue can hold at once. - */ -#define mainQUEUE_LENGTH ( 2 ) - -/** - * The values sent to the queue receive task from the queue send task and the - * queue send software timer respectively. - */ -#define mainVALUE_SENT_FROM_TASK ( 100UL ) -#define mainVALUE_SENT_FROM_TIMER ( 200UL ) -/*-----------------------------------------------------------*/ - -/** - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/** - * The callback function executed when the software timer expires. - */ -static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); -/*-----------------------------------------------------------*/ - -/** - * The queue used by both tasks. - */ -static QueueHandle_t xQueue = NULL; - -/** - * A software timer that is started from the tick hook. - */ -static TimerHandle_t xTimer = NULL; -/*-----------------------------------------------------------*/ - -void main_blinky( void ) -{ -const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - * file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this simple case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer, but don't start it yet. */ - xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ - xTimerPeriod, /* The period of the software timer in ticks. */ - pdTRUE, /* xAutoReload is set to pdTRUE. */ - NULL, /* The timer's ID is not used. */ - prvQueueSendTimerCallback );/* The function executed when the timer expires. */ - - if( xTimer != NULL ) - { - xTimerStart( xTimer, 0 ); - } - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - * line will never be reached. If the following line does execute, then - * there was insufficient FreeRTOS heap memory available for the idle and/or - * timer tasks to be created. See the memory management section on the - * FreeRTOS web site for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - * The block time is specified in ticks, pdMS_TO_TICKS() was used to - * convert a time specified in milliseconds into a time specified in ticks. - * While in the Blocked state this task will not consume any CPU time. */ - vTaskDelayUntil( &xNextWakeTime, xBlockTime ); - - /* Send to the queue - causing the queue receive task to unblock and - * write to the console. 0 is used as the block time so the send operation - * will not block - it shouldn't need to block as the queue should always - * have at least one space at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) -{ -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; - - /* This is the software timer callback function. The software timer has a - * period of two seconds and is reset each time a key is pressed. This - * callback function will execute if the timer expires, which will only happen - * if a key is not pressed for two seconds. */ - - /* Avoid compiler warnings resulting from the unused parameter. */ - ( void ) xTimerHandle; - - /* Send to the queue - causing the queue receive task to unblock and - * write out a message. This function is called from the timer/daemon task, - * so must not block. Hence the block time is set to 0. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -uint32_t ulReceivedValue; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - * FreeRTOSConfig.h. It will not use any CPU time while it is in the - * Blocked state. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - * is it an expected value? This is the only task that uses stdout so its - * ok to call printf() directly. Do not call printf from any other task. */ - if( ulReceivedValue == mainVALUE_SENT_FROM_TASK ) - { - printf( "Message received from task\r\n" ); - } - else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER ) - { - printf( "Message received from software timer\r\n" ); - } - else - { - printf( "Unexpected message\r\n" ); - } - - fflush( stdout ); - } -} -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main_full.c b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main_full.c deleted file mode 100644 index 2e99c090b83..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/main_full.c +++ /dev/null @@ -1,481 +0,0 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/****************************************************************************** - * NOTE: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, are defined - * in main.c. - ****************************************************************************** - * - * main_full() creates all the demo application tasks, then starts the scheduler. - * The web documentation provides more details of the standard demo application - * tasks, which provide no particular functionality but do provide a good - * example of how to use the FreeRTOS API. - * - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Register tests": - * prvRegTest1Task and prvRegTest2Task implement register tests. These functions - * are just entry points and actual tests are written in the assembler file - * regtest_xtensa.S. These tests populate core registers with a known set of - * values and keep verifying them in a loop. Any corruption will indicate an - * error in context switching mechanism. - * - * "Check" task: - * This only executes every five seconds but has a high priority to ensure it - * gets processor time. Its main function is to check that all the standard demo - * tasks are still operational. While no errors have been discovered the check - * task will print out "No errors", the current simulated tick time, free heap - * size and the minimum free heap size so far. If an error is discovered in the - * execution of a task then the check task will print out an appropriate error - * message. - */ - - -/* Standard includes. */ -#include -#include - -/* Kernel includes. */ -#include -#include -#include -#include -#include - -/* Standard demo includes. */ -#include "BlockQ.h" -#include "integer.h" -#include "semtest.h" -#include "PollQ.h" -#include "GenQTest.h" -#include "QPeek.h" -#include "recmutex.h" -#include "flop.h" -#include "TimerDemo.h" -#include "countsem.h" -#include "death.h" -#include "QueueSet.h" -#include "QueueOverwrite.h" -#include "EventGroupsDemo.h" -#include "IntSemTest.h" -#include "TaskNotify.h" -#include "QueueSetPolling.h" -#include "StaticAllocation.h" -#include "blocktim.h" -#include "AbortDelay.h" -#include "MessageBufferDemo.h" -#include "StreamBufferDemo.h" -#include "StreamBufferInterrupt.h" - -/** - * Priorities at which the tasks are created. - */ -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) - -/** - * Period used in timer tests. - */ -#define mainTIMER_TEST_PERIOD ( 50 ) - -/** - * Parameters that are passed into the register check tasks solely for the - * purpose of ensuring parameters are passed into tasks correctly. - */ -#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) -#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) - -/** - * Determines whether to enable interrupt queue tests. - * - * Interrupt queue tests are used to test interrupt nesting and enabling them - * interferes with proper functioning of other tests. This macro controls - * whether to enable interrupt queue tests or all other tests: - * - * * When mainENABLE_INT_QUEUE_TESTS is set to 1, interrupt queue tests are - * enabled and every other test is disabled. - * * When mainENABLE_INT_QUEUE_TESTS is set to 0, interrupt queue tests are - * disabled and every other test is enabled. - */ -#define mainENABLE_INT_QUEUE_TESTS ( 0 ) -/*-----------------------------------------------------------*/ - -/** - * The task that periodically checks that all the standard demo tasks are - * still executing and error free. - */ -static void prvCheckTask( void *pvParameters ); - -/** - * Tasks that implement register tests. - */ -static void prvRegTest1Task( void *pvParameters ); -static void prvRegTest2Task( void *pvParameters ); - -/** - * Functions that implement register tests. - * - * These are implemented in assembler file regtest_xtensa.S. - */ -extern void vRegTest1( void ); -extern void vRegTest2( void ); -/*-----------------------------------------------------------*/ - -/** - * The variable into which error messages are latched. - */ -static char *pcStatusMessage = "No errors"; - -/** - * The following two variables are used to communicate the status of the - * register check tasks to the check task. If the variables keep incrementing, - * then the register check tasks have not discovered any errors. If a variable - * stops incrementing, then an error has been found. - */ -volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; - -/** - * The following variable is used to communicate whether the timers for the - * IntQueue tests have been Initialized. This is needed to ensure that the queues - * are accessed from the tick hook only after they have been created in the - * interrupt queue test. - */ -volatile BaseType_t xTimerForQueueTestInitialized = pdFALSE; -/*-----------------------------------------------------------*/ - -int main_full( void ) -{ - /* Start the check task as described at the top of this file. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - #if( mainENABLE_INT_QUEUE_TESTS == 0 ) - { - /* Create the standard demo tasks. */ - vStartTaskNotifyTask(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - - vStartQueuePeekTasks(); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartCountingSemaphoreTasks(); - vStartQueueSetTasks(); - - vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); - vStartEventGroupTasks(); - vStartInterruptSemaphoreTasks(); - vStartQueueSetPollingTask(); - vCreateBlockTimeTasks(); - - #if( configUSE_PREEMPTION != 0 ) - { - /* Don't expect these tasks to pass when preemption is not used. */ - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - } - #endif - - vCreateAbortDelayTasks(); - vStartMessageBufferTasks( configMINIMAL_STACK_SIZE ); - - vStartStreamBufferTasks(); - vStartStreamBufferInterruptDemo(); - - /* Create the register check tasks, as described at the top of this file */ - xTaskCreate( prvRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they need to know how many - * tasks were running prior to their creation. This then allows them to - * ascertain whether or not the correct/expected number of tasks are - * running at any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - } - #else /* mainENABLE_INT_QUEUE_TESTS */ - { - /* Start interrupt queue test tasks. */ - vStartInterruptQueueTasks(); - } - #endif /* mainENABLE_INT_QUEUE_TESTS */ - - /* Start the scheduler itself. */ - vTaskStartScheduler(); - - /* Should never get here unless there was not enough heap space to create - * the idle and other system tasks. */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const TickType_t xCycleFrequency = pdMS_TO_TICKS( 5000UL ); -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. */ - vTaskDelayUntil( &xNextWakeTime, xCycleFrequency ); - - #if( mainENABLE_INT_QUEUE_TESTS == 0 ) - { - /* Check the standard demo tasks are running without error. */ - #if( configUSE_PREEMPTION != 0 ) - { - /* These tasks are only created when preemption is used. */ - if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE ) - { - pcStatusMessage = "Error: TimerDemo"; - } - } - #endif - - if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: Notification"; - } - else if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: BlockQueue"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: SemTest"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: PollQueue"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: IntMath"; - } - else if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: GenQueue"; - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: QueuePeek"; - } - else if( xAreMathsTaskStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Flop"; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: RecMutex"; - } - else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: CountSem"; - } - else if( xAreQueueSetTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Queue set"; - } - else if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Queue overwrite"; - } - else if( xAreEventGroupTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: EventGroup"; - } - else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: IntSem"; - } - else if( xAreQueueSetPollTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Queue set polling"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Block time"; - } - else if( xAreAbortDelayTestTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Abort delay"; - } - else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: MessageBuffer"; - } - else if( xAreStreamBufferTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: StreamBuffer"; - } - else if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Stream buffer interrupt"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: Death"; - } - else if( ulLastRegTest1Value == ulRegTest1Counter ) - { - pcStatusMessage = "Error: Reg Test 1"; - } - else if( ulLastRegTest2Value == ulRegTest2Counter ) - { - pcStatusMessage = "Error: Reg Test 2"; - } - - /* Update register test counters. */ - ulLastRegTest1Value = ulRegTest1Counter; - ulLastRegTest2Value = ulRegTest2Counter; - } - #else /* mainENABLE_INT_QUEUE_TESTS */ - { - if( xAreIntQueueTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: IntQueue"; - } - } - #endif /* mainENABLE_INT_QUEUE_TESTS */ - - /* This is the only task that uses stdout so its ok to call printf() - * directly. Do not call printf from any other task. */ - printf( "%s - tick count %zu - free heap %zu - min free heap %zu\r\n", pcStatusMessage, - xTaskGetTickCount(), - xPortGetFreeHeapSize(), - xPortGetMinimumEverFreeHeapSize() ); - } -} -/*-----------------------------------------------------------*/ - -/* Called by vApplicationTickHook(), which is defined in main.c. */ -void vFullDemoTickHookFunction( void ) -{ -TaskHandle_t xTimerTask; - - #if( mainENABLE_INT_QUEUE_TESTS == 0 ) - { - /* Exercise using task notifications from an interrupt. */ - xNotifyTaskFromISR(); - - /* Write to a queue that is in use as part of the queue set demo to - * demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - /* Exercise event groups from interrupts. */ - vPeriodicEventGroupsProcessing(); - - /* Exercise giving mutexes from an interrupt. */ - vInterruptSemaphorePeriodicTest(); - - /* Queue set access from interrupt. */ - vQueueSetPollingInterruptAccess(); - - /* Call the periodic timer test, which tests the timer API functions that - * can be called from an ISR. */ - #if( configUSE_PREEMPTION != 0 ) - { - /* Only created when preemption is used. */ - vTimerPeriodicISRTests(); - } - #endif - - /* Writes to stream buffer byte by byte to test the stream buffer trigger - * level functionality. */ - vPeriodicStreamBufferProcessing(); - - /* Writes a string to a string buffer four bytes at a time to demonstrate - * a stream being sent from an interrupt to a task. */ - vBasicStreamBufferSendFromISR(); - } - #else /* mainENABLE_INT_QUEUE_TESTS */ - { - /* Access queues from interrupt. Make sure to access after the queues have - * been created. */ - if( xTimerForQueueTestInitialized == pdTRUE ) - { - portYIELD_FROM_ISR( xFirstTimerHandler() ); - } - } - #endif /* mainENABLE_INT_QUEUE_TESTS */ -} -/*-----------------------------------------------------------*/ - -static void prvRegTest1Task( void *pvParameters ) -{ - /* Although the regtest task is written in assembly, its entry point is - * written in C for convenience of checking the task parameter is being - * passed in correctly. */ - if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) - { - /* Start the part of the test that is written in assembly. */ - vRegTest1(); - } - - /* The following line will only execute if the task parameter is found to - * be incorrect. The check task will detect that the regtest loop counter is - * not being incremented and flag an error. */ - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvRegTest2Task( void *pvParameters ) -{ - /* Although the regtest task is written in assembly, its entry point is - * written in C for convenience of checking the task parameter is being - * passed in correctly. */ - if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) - { - /* Start the part of the test that is written in assembly. */ - vRegTest2(); - } - - /* The following line will only execute if the task parameter is found to - * be incorrect. The check task will detect that the regtest loop counter is - * not being incremented and flag an error. */ - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/moved_to_Partner-Supported-Demos b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/moved_to_Partner-Supported-Demos new file mode 100644 index 00000000000..734d4efae35 --- /dev/null +++ b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/moved_to_Partner-Supported-Demos @@ -0,0 +1,3 @@ +All Tensilica demos have been moved to a new location: + +FreeRTOS/Demo/ThirdParty/Partner-Supported-Demos/Cadence_Xtensa_ISS_xt-clang/ diff --git a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/regtest_xtensa.S b/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/regtest_xtensa.S deleted file mode 100644 index cbb766ceaa0..00000000000 --- a/FreeRTOS/Demo/Tensilica_Simulator_Xplorer_XCC/regtest_xtensa.S +++ /dev/null @@ -1,216 +0,0 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -#include "FreeRTOSConfig.h" -//#include "ISR_Support.h" - - .extern ulRegTest1Counter - .extern ulRegTest2Counter - .extern vPortYield - - .global vRegTest1 - .global vRegTest2 - - .text - .align 4 - - -/*-----------------------------------------------------------*/ - -vRegTest1: - - /* Set initial values into the general purpose registers. - * a0 = return address, a1 = stack pointer. */ -#ifdef __XTENSA_WINDOWED_ABI__ - entry a1, 64 - s32i a0, a1, 0 /* Save return address. */ -#else - addi a1, a1, -64 - s32i a0, a1, 0 /* Save return address. */ - s32i a12, a1, 4 /* Save callee-saved regs if call0 ABI. */ - s32i a13, a1, 8 - s32i a14, a1, 12 - s32i a15, a1, 16 -#endif - movi a2, 0x11111111 - movi a3, 0x22222222 - movi a4, 0x33333333 - movi a5, 0x44444444 - movi a6, 0x55555555 - movi a7, 0x66666666 - movi a8, 0x77777777 - movi a9, 0x88888888 - movi a10, 0x99999999 - movi a11, 0xaaaaaaaa - movi a12, 0xbbbbbbbb - movi a13, 0xcccccccc - movi a14, 0xdddddddd - movi a15, 0xeeeeeeee - -_RegTest1Loop: - - /* Loop checking the values originally loaded into the general purpose - * registers remain through the life of the task. */ - movi a0, 0x11111111 - bne a0, a2, _RegTest1Error - movi a0, 0x22222222 - bne a0, a3, _RegTest1Error - movi a0, 0x33333333 - bne a0, a4, _RegTest1Error - movi a0, 0x44444444 - bne a0, a5, _RegTest1Error - movi a0, 0x55555555 - bne a0, a6, _RegTest1Error - movi a0, 0x66666666 - bne a0, a7, _RegTest1Error - movi a0, 0x77777777 - bne a0, a8, _RegTest1Error - movi a0, 0x88888888 - bne a0, a9, _RegTest1Error - movi a0, 0x99999999 - bne a0, a10, _RegTest1Error - movi a0, 0xaaaaaaaa - bne a0, a11, _RegTest1Error - movi a0, 0xbbbbbbbb - bne a0, a12, _RegTest1Error - movi a0, 0xcccccccc - bne a0, a13, _RegTest1Error - movi a0, 0xdddddddd - bne a0, a14, _RegTest1Error - movi a0, 0xeeeeeeee - bne a0, a15, _RegTest1Error - - /* Incrememnt the loop counter to prove this task has not gone into the - * error null loop. */ - s32i a2, a1, 20 - movi a2, ulRegTest1Counter - l32i a0, a2, 0 - addi a0, a0, 1 - s32i a0, a2, 0 - l32i a2, a1, 20 - - /* Loop again. */ - j _RegTest1Loop - -_RegTest1Error: -.L1: - j .L1 - - - .align 4 - -/*-----------------------------------------------------------*/ - -vRegTest2: - - /* Set initial values into the general purpose registers. - * a0 = return address, a1 = stack pointer. */ -#ifdef __XTENSA_WINDOWED_ABI__ - entry a1, 64 - s32i a0, a1, 0 /* Save return address. */ -#else - addi a1, a1, -64 - s32i a0, a1, 0 /* Save return address. */ - s32i a12, a1, 4 /* Save callee-saved regs if call0 ABI. */ - s32i a13, a1, 8 - s32i a14, a1, 12 - s32i a15, a1, 16 -#endif - -_ReInit: - - movi a2, 0x01010101 - movi a3, 0x02020202 - movi a4, 0x03030303 - movi a5, 0x04040404 - movi a6, 0x05050505 - movi a7, 0x06060606 - movi a8, 0x07070707 - movi a9, 0x08080808 - movi a10, 0x09090909 - movi a11, 0x0a0a0a0a - movi a12, 0x0b0b0b0b - movi a13, 0x0c0c0c0c - movi a14, 0x0d0d0d0d - movi a15, 0x0e0e0e0e - -_RegTest2Loop: - - /* Loop checking the values originally loaded into the general purpose - * registers remain through the life of the task. */ - movi a0, 0x01010101 - bne a0, a2, _RegTest1Error - movi a0, 0x02020202 - bne a0, a3, _RegTest1Error - movi a0, 0x03030303 - bne a0, a4, _RegTest1Error - movi a0, 0x04040404 - bne a0, a5, _RegTest1Error - movi a0, 0x05050505 - bne a0, a6, _RegTest1Error - movi a0, 0x06060606 - bne a0, a7, _RegTest1Error - movi a0, 0x07070707 - bne a0, a8, _RegTest1Error - movi a0, 0x08080808 - bne a0, a9, _RegTest1Error - movi a0, 0x09090909 - bne a0, a10, _RegTest1Error - movi a0, 0x0a0a0a0a - bne a0, a11, _RegTest1Error - movi a0, 0x0b0b0b0b - bne a0, a12, _RegTest1Error - movi a0, 0x0c0c0c0c - bne a0, a13, _RegTest1Error - movi a0, 0x0d0d0d0d - bne a0, a14, _RegTest1Error - movi a0, 0x0e0e0e0e - bne a0, a15, _RegTest1Error - - /* Force a yield from one of the reg test tasks to increase coverage. - * IMPORTANT: this call will trash some number of registers. Branch - * to _ReInit to set things up again. */ -#ifdef __XTENSA_WINDOWED_ABI__ - call8 vPortYield -#else - call0 vPortYield -#endif - - /* Increment the loop counter to prove this task has not gone into the - * error null loop. */ - s32i a2, a1, 20 - movi a2, ulRegTest2Counter - l32i a0, a2, 0 - addi a0, a0, 1 - s32i a0, a2, 0 - l32i a2, a1, 20 - - /* Loop again. */ - j _ReInit /* See comments above about not using j _RegTest2Loop. */ - -_RegTest2Error: -.L2: - j .L2 diff --git a/FreeRTOS/Demo/ThirdParty/Community-Supported-Demos b/FreeRTOS/Demo/ThirdParty/Community-Supported-Demos index 1ba24b127f1..272ca5bfbe0 160000 --- a/FreeRTOS/Demo/ThirdParty/Community-Supported-Demos +++ b/FreeRTOS/Demo/ThirdParty/Community-Supported-Demos @@ -1 +1 @@ -Subproject commit 1ba24b127f11544263209a65f49cffdd7e42f04a +Subproject commit 272ca5bfbe0ea8a5e24a19a4a0e2bd4bf00b4066 diff --git a/FreeRTOS/Demo/ThirdParty/Partner-Supported-Demos b/FreeRTOS/Demo/ThirdParty/Partner-Supported-Demos index 44b2426a9bb..022783f7c75 160000 --- a/FreeRTOS/Demo/ThirdParty/Partner-Supported-Demos +++ b/FreeRTOS/Demo/ThirdParty/Partner-Supported-Demos @@ -1 +1 @@ -Subproject commit 44b2426a9bba9456a8f7d0dfe2a5f849122f18be +Subproject commit 022783f7c75e5c5aa3e2e07606318e7fdae2c79e diff --git a/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.c b/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.c index 8a19ba5423d..b156150ac79 100644 --- a/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.c +++ b/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.h b/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.h index bb7f02d9f33..3e7c1b2aaf2 100644 --- a/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.h +++ b/FreeRTOS/Demo/ThirdParty/Template/IntQueueTimer.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ThirdParty/Template/RegTests.c b/FreeRTOS/Demo/ThirdParty/Template/RegTests.c index fc9b935d07e..3201bbd2bc9 100644 --- a/FreeRTOS/Demo/ThirdParty/Template/RegTests.c +++ b/FreeRTOS/Demo/ThirdParty/Template/RegTests.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ThirdParty/Template/RegTests.h b/FreeRTOS/Demo/ThirdParty/Template/RegTests.h index 5b5dffe9785..260603083d9 100644 --- a/FreeRTOS/Demo/ThirdParty/Template/RegTests.h +++ b/FreeRTOS/Demo/ThirdParty/Template/RegTests.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ThirdParty/Template/TestRunner.c b/FreeRTOS/Demo/ThirdParty/Template/TestRunner.c index 3782087bf1c..e584cc1832a 100644 --- a/FreeRTOS/Demo/ThirdParty/Template/TestRunner.c +++ b/FreeRTOS/Demo/ThirdParty/Template/TestRunner.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/ThirdParty/Template/TestRunner.h b/FreeRTOS/Demo/ThirdParty/Template/TestRunner.h index 2a17f6ce510..150996dca3d 100644 --- a/FreeRTOS/Demo/ThirdParty/Template/TestRunner.h +++ b/FreeRTOS/Demo/ThirdParty/Template/TestRunner.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/FreeRTOSConfig.h index 79f21b34906..85b98d46108 100644 --- a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/FreeRTOSConfig.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.c b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.c index 12b2a80d65a..71b836c4a89 100644 --- a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.c +++ b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.h b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.h index 4b64fd60cd6..ff5c4261ea8 100644 --- a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.h +++ b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/InterruptNestTest.h @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/ParTest.c b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/ParTest.c index 519f07d58bd..efd945e4cec 100644 --- a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/ParTest.c +++ b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/ParTest.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/main.c b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/main.c index 22bf7b38562..1b5ff5b1397 100644 --- a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/main.c +++ b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/serial.c b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/serial.c index 4343965c434..43140ce8d34 100644 --- a/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/serial.c +++ b/FreeRTOS/Demo/TriCore_TC1782_TriBoard_GCC/RTOSDemo/serial.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h index 504f296e98c..83f13695a40 100644 --- a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h @@ -1,126 +1,128 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. See - * https://www.FreeRTOS.org/a00110.html - *----------------------------------------------------------*/ - -/* Setting configSUPPORT_STATIC_ALLOCATION to 1 allows RTOS objects to be -created using only application supplied memory. No dynamic memory allocation -will be performed. */ -#define configSUPPORT_STATIC_ALLOCATION 1 - -/* Setting configSUPPORT_DYNAMIC_ALLOCATION to 0 results in all calls to -pvPortMalloc() returning NULL, and all calls to vPortFree() being ignored. -Therefore the application can be built without providing an implementation of -either of these functions (so none of the normal heap_n.c files described on -http://www.freertos.org/a00111.html are required). Note that -configTOTAL_HEAP_SIZE is not defined. */ -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Other constants as described on http://www.freertos.org/a00110.html */ -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 -#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 50 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the win32 thread. */ -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configCHECK_FOR_STACK_OVERFLOW 0 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 20 -#define configUSE_MALLOC_FAILED_HOOK 0 /* pvPortMalloc() is not used. */ -#define configUSE_APPLICATION_TASK_TAG 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_ALTERNATIVE_API 0 -#define configUSE_QUEUE_SETS 1 -#define configUSE_TASK_NOTIFICATIONS 1 - -/* Software timer related configuration options. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define configTIMER_QUEUE_LENGTH 20 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) - -#define configMAX_PRIORITIES ( 7 ) - -/* Run time stats gathering configuration options. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() -#define portGET_RUN_TIME_COUNTER_VALUE() - -/* Co-routine related configuration options. */ -#define configUSE_CO_ROUTINES 0 - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. In most cases the linker will remove unused -functions anyway. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskAbortDelay 1 - -/* It is a good idea to define configASSERT() while developing. configASSERT() -uses the same semantics as the standard C assert() macro. */ -extern void vAssertCalled( unsigned long ulLine, const char * const pcFileName ); -#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ ) - - -#endif /* FREERTOS_CONFIG_H */ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. See + * https://www.FreeRTOS.org/a00110.html + *----------------------------------------------------------*/ + +/* Setting configSUPPORT_STATIC_ALLOCATION to 1 allows RTOS objects to be +created using only application supplied memory. No dynamic memory allocation +will be performed. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +/* Setting configSUPPORT_DYNAMIC_ALLOCATION to 0 results in all calls to +pvPortMalloc() returning NULL, and all calls to vPortFree() being ignored. +Therefore the application can be built without providing an implementation of +either of these functions (so none of the normal heap_n.c files described on +http://www.freertos.org/a00111.html are required). Note that +configTOTAL_HEAP_SIZE is not defined. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Other constants as described on http://www.freertos.org/a00110.html */ +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 50 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the win32 thread. */ +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 20 +#define configUSE_MALLOC_FAILED_HOOK 0 /* pvPortMalloc() is not used. */ +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_TASK_NOTIFICATIONS 1 + +/* Software timer related configuration options. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +#define configMAX_PRIORITIES ( 7 ) + +/* Run time stats gathering configuration options. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() + +/* Co-routine related configuration options. */ +#define configUSE_CO_ROUTINES 0 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. In most cases the linker will remove unused +functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 + +/* It is a good idea to define configASSERT() while developing. configASSERT() +uses the same semantics as the standard C assert() macro. */ +extern void vAssertCalled( unsigned long ulLine, const char * const pcFileName ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ ) + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.sln b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.sln index 6afed9a6fc2..17f59aa1a52 100644 --- a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.sln +++ b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.sln @@ -1,25 +1,22 @@ - -Microsoft Visual Studio Solution File, Format Version 12.00 -# Visual Studio 14 -VisualStudioVersion = 14.0.24720.0 -MinimumVisualStudioVersion = 10.0.40219.1 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|Win32 = Debug|Win32 - Optimised|Win32 = Optimised|Win32 - Release|Win32 = Release|Win32 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Optimised|Win32.ActiveCfg = Optimised|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Optimised|Win32.Build.0 = Optimised|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection -EndGlobal + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 16 +VisualStudioVersion = 16.0.34114.132 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {00C48E34-7E90-42FF-A6FE-1E1FA985B8AD} + EndGlobalSection +EndGlobal diff --git a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.vcxproj b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.vcxproj index 999f3e50718..4ceefcccdd3 100644 --- a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.vcxproj +++ b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/WIN32.vcxproj @@ -1,247 +1,247 @@ - - - - - Debug - Win32 - - - Optimised - Win32 - - - Release - Win32 - - - - {C686325E-3261-42F7-AEB1-DDE5280E1CEB} - RTOSDemo - - - - Application - false - MultiByte - v142 - - - Application - false - MultiByte - v142 - - - Application - false - MultiByte - v142 - - - - - - - - - - - - - - - - - - - <_ProjectFileVersion>10.0.30319.1 - .\Debug\ - .\Debug\ - .\Debug\ - .\Debug\ - true - true - .\Release\ - .\Release\ - false - - - - .\Debug/WIN32.tlb - - - - - Disabled - ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\Include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) - WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - EnableFastChecks - MultiThreadedDebug - .\Debug/WIN32.pch - .\Debug/ - .\Debug/ - .\Debug/ - Level4 - true - EditAndContinue - false - /wd4210 %(AdditionalOptions) - - - _DEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Debug/RTOSDemo.exe - true - true - .\Debug/WIN32.pdb - Console - MachineX86 - %(AdditionalDependencies) - false - - - true - .\Debug/WIN32.bsc - - - - - .\Debug/WIN32.tlb - - - - - Full - ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\Include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) - WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - Default - MultiThreadedDebug - .\Debug/WIN32.pch - .\Debug/ - .\Debug/ - .\Debug/ - Level4 - true - EditAndContinue - false - /wd4210 %(AdditionalOptions) - - - _DEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Debug/RTOSDemo.exe - true - true - .\Debug/WIN32.pdb - Console - MachineX86 - %(AdditionalDependencies) - false - - - true - .\Debug/WIN32.bsc - - - - - .\Release/WIN32.tlb - - - - - MaxSpeed - OnlyExplicitInline - WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - true - MultiThreaded - true - .\Release/WIN32.pch - .\Release/ - .\Release/ - .\Release/ - Level3 - true - ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;.;%(AdditionalIncludeDirectories) - - - NDEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Release/RTOSDemo.exe - true - .\Release/WIN32.pdb - Console - MachineX86 - - - true - .\Release/WIN32.bsc - - - - - - - - - %(AdditionalIncludeDirectories) - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - %(PreprocessorDefinitions) - - - - - - - - - - - - - - - - - - - + + + + + Debug + Win32 + + + Optimised + Win32 + + + Release + Win32 + + + + {C686325E-3261-42F7-AEB1-DDE5280E1CEB} + RTOSDemo + + + + Application + false + MultiByte + v142 + + + Application + false + MultiByte + v142 + + + Application + false + MultiByte + v142 + + + + + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.30319.1 + .\Debug\ + .\Debug\ + .\Debug\ + .\Debug\ + true + true + .\Release\ + .\Release\ + false + + + + .\Debug/WIN32.tlb + + + + + Disabled + ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\Include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebug + .\Debug/WIN32.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level4 + true + EditAndContinue + false + /wd4210 %(AdditionalOptions) + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Debug/RTOSDemo.exe + true + true + .\Debug/WIN32.pdb + Console + MachineX86 + %(AdditionalDependencies) + false + + + true + .\Debug/WIN32.bsc + + + + + .\Debug/WIN32.tlb + + + + + Full + ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\Include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + Default + MultiThreadedDebug + .\Debug/WIN32.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level4 + true + EditAndContinue + false + /wd4210 %(AdditionalOptions) + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Debug/RTOSDemo.exe + true + true + .\Debug/WIN32.pdb + Console + MachineX86 + %(AdditionalDependencies) + false + + + true + .\Debug/WIN32.bsc + + + + + .\Release/WIN32.tlb + + + + + MaxSpeed + OnlyExplicitInline + WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + MultiThreaded + true + .\Release/WIN32.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;.;%(AdditionalIncludeDirectories) + + + NDEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Release/RTOSDemo.exe + true + .\Release/WIN32.pdb + Console + MachineX86 + + + true + .\Release/WIN32.bsc + + + + + + + + + %(AdditionalIncludeDirectories) + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/main.c b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/main.c index 84d0d585762..a5a92fc26b5 100644 --- a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/main.c +++ b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/main.c @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in diff --git a/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h b/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h index 6170a062d58..039e8bf690d 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h @@ -1,133 +1,145 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. See - * https://www.FreeRTOS.org/a00110.html - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 1 -#define configUSE_DAEMON_TASK_STARTUP_HOOK 1 -#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the win32 thread. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 49 * 1024 ) ) /* This demo tests heap_5 so places multiple blocks within this total heap size. See mainREGION_1_SIZE to mainREGION_3_SIZE definitions in main.c. */ -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configCHECK_FOR_STACK_OVERFLOW 0 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 20 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_ALTERNATIVE_API 0 -#define configUSE_QUEUE_SETS 1 -#define configUSE_TASK_NOTIFICATIONS 1 -#define configTASK_NOTIFICATION_ARRAY_ENTRIES 5 -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configINITIAL_TICK_COUNT ( ( TickType_t ) 0 ) /* For test. */ -#define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 1 /* As there are a lot of tasks running. */ - -/* Software timer related configuration options. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define configTIMER_QUEUE_LENGTH 20 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) - -#define configMAX_PRIORITIES ( 7 ) - -/* Run time stats gathering configuration options. */ -#define configRUN_TIME_COUNTER_TYPE uint64_t -configRUN_TIME_COUNTER_TYPE ulGetRunTimeCounterValue( void ); /* Prototype of function that returns run time counter. */ -void vConfigureTimerForRunTimeStats( void ); /* Prototype of function that initialises the run time counter. */ -#define configGENERATE_RUN_TIME_STATS 1 -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() -#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() - -/* Co-routine related configuration options. */ -#define configUSE_CO_ROUTINES 1 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. In most cases the linker will remove unused -functions anyway. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 -#define INCLUDE_xTaskGetSchedulerState 1 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 -#define INCLUDE_xTaskGetIdleTaskHandle 1 -#define INCLUDE_xTaskGetHandle 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xSemaphoreGetMutexHolder 1 -#define INCLUDE_xTimerPendFunctionCall 1 -#define INCLUDE_xTaskAbortDelay 1 - -/* The Win32 target is capable of running all the tests tasks at the same - * time. */ -#define configRUN_ADDITIONAL_TESTS 1 - -/* It is a good idea to define configASSERT() while developing. configASSERT() -uses the same semantics as the standard C assert() macro. */ -extern void vAssertCalled( unsigned long ulLine, const char * const pcFileName ); -#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ ) - -#define configINCLUDE_MESSAGE_BUFFER_AMP_DEMO 0 -#if ( configINCLUDE_MESSAGE_BUFFER_AMP_DEMO == 1 ) - extern void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer ); - #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer ) -#endif /* configINCLUDE_MESSAGE_BUFFER_AMP_DEMO */ - -/* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */ -#include "trcRecorder.h" - -#endif /* FREERTOS_CONFIG_H */ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. See + * https://www.FreeRTOS.org/a00110.html + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 1 +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the win32 thread. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 490 * 1024 ) ) /* This demo tests heap_5 so places multiple blocks within this total heap size. See mainREGION_1_SIZE to mainREGION_3_SIZE definitions in main.c. */ +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 20 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 5 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configINITIAL_TICK_COUNT ( ( TickType_t ) 0 ) /* For test. */ +#define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 1 /* As there are a lot of tasks running. */ + + /* Tick type width is defined based on the target platform(32bit or 64bit). */ +#ifdef _M_X64 + #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_64_BITS +#else + #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS +#endif + +/* Software timer related configuration options. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +#define configMAX_PRIORITIES ( 7 ) + +/* Run time stats gathering configuration options. */ +#define configRUN_TIME_COUNTER_TYPE uint64_t +configRUN_TIME_COUNTER_TYPE ulGetRunTimeCounterValue( void ); /* Prototype of function that returns run time counter. */ +void vConfigureTimerForRunTimeStats( void ); /* Prototype of function that initialises the run time counter. */ +#define configGENERATE_RUN_TIME_STATS 1 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() +#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + +/* Co-routine related configuration options. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. In most cases the linker will remove unused +functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 + +/* The Win32 target is capable of running all the tests tasks at the same + * time. */ +#define configRUN_ADDITIONAL_TESTS 1 + +/* It is a good idea to define configASSERT() while developing. configASSERT() +uses the same semantics as the standard C assert() macro. */ +extern void vAssertCalled( unsigned long ulLine, const char * const pcFileName ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ ) + +#define configINCLUDE_MESSAGE_BUFFER_AMP_DEMO 0 +#if ( configINCLUDE_MESSAGE_BUFFER_AMP_DEMO == 1 ) + extern void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer ); + #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer ) +#endif /* configINCLUDE_MESSAGE_BUFFER_AMP_DEMO */ + +#ifdef WIN32_LEAN_AND_MEAN + #include "winsock2.h" +#else + #include +#endif /* WIN32_LEAN_AND_MEAN */ + +/* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */ +#include "trcRecorder.h" + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/WIN32-MSVC/Run-time-stats-utils.c b/FreeRTOS/Demo/WIN32-MSVC/Run-time-stats-utils.c index a11ae456c0b..06bc5b360da 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/Run-time-stats-utils.c +++ b/FreeRTOS/Demo/WIN32-MSVC/Run-time-stats-utils.c @@ -1,98 +1,98 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/* - * Utility functions required to gather run time statistics. See: - * https://www.FreeRTOS.org/rtos-run-time-stats.html - * - * Note that this is a simulated port, where simulated time is a lot slower than - * real time, therefore the run time counter values have no real meaningful - * units. - * - * Also note that it is assumed this demo is going to be used for short periods - * of time only, and therefore timer overflows are not handled. -*/ - -/* FreeRTOS includes. */ -#include - -/* Variables used in the creation of the run time stats time base. Run time -stats record how much time each task spends in the Running state. */ -static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL; - -/*-----------------------------------------------------------*/ - -void vConfigureTimerForRunTimeStats( void ) -{ -LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue; - - /* Initialise the variables used to create the run time stats time base. - Run time stats record how much time each task spends in the Running - state. */ - - if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 ) - { - llTicksPerHundedthMillisecond = 1; - } - else - { - /* How many times does the performance counter increment in 1/100th - millisecond. */ - llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL; - - /* What is the performance counter value now, this will be subtracted - from readings taken at run time. */ - QueryPerformanceCounter( &liInitialRunTimeValue ); - llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart; - } -} -/*-----------------------------------------------------------*/ - -configRUN_TIME_COUNTER_TYPE ulGetRunTimeCounterValue( void ) -{ -LARGE_INTEGER liCurrentCount; -configRUN_TIME_COUNTER_TYPE ulReturn; - - /* What is the performance counter value now? */ - QueryPerformanceCounter( &liCurrentCount ); - - /* Subtract the performance counter value reading taken when the - application started to get a count from that reference point, then - scale to (simulated) 1/100ths of a millisecond. */ - if( llTicksPerHundedthMillisecond == 0 ) - { - /* The trace macros are probably calling this function before the - scheduler has been started. */ - ulReturn = 0; - } - else - { - ulReturn = ( configRUN_TIME_COUNTER_TYPE ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond ); - } - - return ulReturn; -} -/*-----------------------------------------------------------*/ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Utility functions required to gather run time statistics. See: + * https://www.FreeRTOS.org/rtos-run-time-stats.html + * + * Note that this is a simulated port, where simulated time is a lot slower than + * real time, therefore the run time counter values have no real meaningful + * units. + * + * Also note that it is assumed this demo is going to be used for short periods + * of time only, and therefore timer overflows are not handled. +*/ + +/* FreeRTOS includes. */ +#include + +/* Variables used in the creation of the run time stats time base. Run time +stats record how much time each task spends in the Running state. */ +static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL; + +/*-----------------------------------------------------------*/ + +void vConfigureTimerForRunTimeStats( void ) +{ +LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue; + + /* Initialise the variables used to create the run time stats time base. + Run time stats record how much time each task spends in the Running + state. */ + + if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 ) + { + llTicksPerHundedthMillisecond = 1; + } + else + { + /* How many times does the performance counter increment in 1/100th + millisecond. */ + llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL; + + /* What is the performance counter value now, this will be subtracted + from readings taken at run time. */ + QueryPerformanceCounter( &liInitialRunTimeValue ); + llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart; + } +} +/*-----------------------------------------------------------*/ + +configRUN_TIME_COUNTER_TYPE ulGetRunTimeCounterValue( void ) +{ +LARGE_INTEGER liCurrentCount; +configRUN_TIME_COUNTER_TYPE ulReturn; + + /* What is the performance counter value now? */ + QueryPerformanceCounter( &liCurrentCount ); + + /* Subtract the performance counter value reading taken when the + application started to get a count from that reference point, then + scale to (simulated) 1/100ths of a millisecond. */ + if( llTicksPerHundedthMillisecond == 0 ) + { + /* The trace macros are probably calling this function before the + scheduler has been started. */ + ulReturn = 0; + } + else + { + ulReturn = ( configRUN_TIME_COUNTER_TYPE ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond ); + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/WIN32-MSVC/WIN32.sln b/FreeRTOS/Demo/WIN32-MSVC/WIN32.sln index 43545ea5dea..28f6d4e2614 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/WIN32.sln +++ b/FreeRTOS/Demo/WIN32-MSVC/WIN32.sln @@ -1,25 +1,24 @@ - -Microsoft Visual Studio Solution File, Format Version 12.00 -# Visual Studio 14 -VisualStudioVersion = 14.0.25420.1 -MinimumVisualStudioVersion = 10.0.40219.1 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|Win32 = Debug|Win32 - Optimised|Win32 = Optimised|Win32 - Release|Win32 = Release|Win32 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Optimised|Win32.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Optimised|Win32.Build.0 = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Debug|Win32 - {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Debug|Win32 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection -EndGlobal +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 17 +VisualStudioVersion = 17.8.34330.188 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|x64.ActiveCfg = Debug|x64 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|x64.Build.0 = Debug|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {64031909-AD3F-4A9D-A145-A4A28A326595} + EndGlobalSection +EndGlobal diff --git a/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj b/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj index f773363dd7d..50fe3c9f941 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj +++ b/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj @@ -1,162 +1,167 @@ - - - - - Debug - Win32 - - - - {C686325E-3261-42F7-AEB1-DDE5280E1CEB} - RTOSDemo - - - - Application - false - MultiByte - v142 - - - - - - - - - - - <_ProjectFileVersion>10.0.30319.1 - .\Debug\ - .\Debug\ - true - - - - .\Debug/WIN32.tlb - - - - - Disabled - ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) - WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0601;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) - EnableFastChecks - MultiThreadedDebug - .\Debug/WIN32.pch - .\Debug/ - .\Debug/ - .\Debug/ - Level4 - true - EditAndContinue - false - /wd4210 %(AdditionalOptions) - 4574;4820;4668;4255;4710;%(DisableSpecificWarnings) - - - _DEBUG;%(PreprocessorDefinitions) - 0x0c09 - - - .\Debug/RTOSDemo.exe - true - true - .\Debug/WIN32.pdb - Console - MachineX86 - %(AdditionalDependencies) - false - - - true - .\Debug/WIN32.bsc - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - - - %(AdditionalIncludeDirectories) - %(PreprocessorDefinitions) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + Debug + Win32 + + + Debug + x64 + + + + {C686325E-3261-42F7-AEB1-DDE5280E1CEB} + RTOSDemo + 10.0 + + + + Application + false + MultiByte + v143 + + + + + + + + + + + <_ProjectFileVersion>10.0.30319.1 + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\ + true + + + + .\Debug/WIN32.tlb + + + + + Disabled + ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) + WIN32;WIN32_LEAN_AND_MEAN;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0601;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebug + Level4 + true + EditAndContinue + false + /wd4210 %(AdditionalOptions) + 4574;4820;4668;4255;4710;%(DisableSpecificWarnings) + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + $(OutDir)$(TargetName)$(TargetExt) + true + true + Console + MachineX86 + %(AdditionalDependencies) + false + + + true + .\Debug/WIN32.bsc + + + + + ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\kernelports\FreeRTOS\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-Trace\include;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj.filters b/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj.filters index b0892b5f3f7..64a87bb7986 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj.filters +++ b/FreeRTOS/Demo/WIN32-MSVC/WIN32.vcxproj.filters @@ -1,235 +1,235 @@ - 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- - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - FreeRTOS Source\Source - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source - - - FreeRTOS Source\Source - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - FreeRTOS Source\Source - - - FreeRTOS Source\Source\Portable - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo - - - Demo App Source\Blinky_Demo - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\FreeRTOS+Trace Recorder - - - Demo App Source\FreeRTOS+Trace Recorder - - - FreeRTOS Source\Source - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - Demo App Source\Full_Demo\Common Demo Tasks - - - - - Configuration Files - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - Configuration Files - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - FreeRTOS Source\Include - - - Configuration Files - - - Configuration Files - - - Configuration Files - - - Demo App Source\FreeRTOS+Trace Recorder\include - - - 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* FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/****************************************************************************** - * This project provides two demo applications. A simple blinky style project, - * and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. - * The simply blinky demo is implemented and described in main_blinky.c. The - * more comprehensive test and demo application is implemented and described in - * main_full.c. - * - * This file implements the code that is not demo specific, including the - * hardware setup and FreeRTOS hook functions. - * - ******************************************************************************* - * NOTE: Windows will not be running the FreeRTOS demo threads continuously, so - * do not expect to get real time behaviour from the FreeRTOS Windows port, or - * this demo application. Also, the timing information in the FreeRTOS+Trace - * logs have no meaningful units. See the documentation page for the Windows - * port for further information: - * https://www.FreeRTOS.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html - * - * - ******************************************************************************* - */ - -/* Standard includes. */ -#include -#include -#include - -/* Visual studio intrinsics used so the __debugbreak() function is available - * should an assert get hit. */ -#include - -/* FreeRTOS kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* FreeRTOS+Trace includes. */ -#include "trcRecorder.h" - -/* This project provides two demo applications. A simple blinky style demo - * application, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. - * - * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built. - * The blinky demo is implemented and described in main_blinky.c. - * - * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and - * demo application will be built. The comprehensive test and demo application is - * implemented and described in main_full.c. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 - -/* This demo uses heap_5.c, and these constants define the sizes of the regions - * that make up the total heap. heap_5 is only used for test and example purposes - * as this demo could easily create one large heap region instead of multiple - * smaller heap regions - in which case heap_4.c would be the more appropriate - * choice. See http://www.freertos.org/a00111.html for an explanation. */ -#define mainREGION_1_SIZE 8201 -#define mainREGION_2_SIZE 23905 -#define mainREGION_3_SIZE 16807 - -/* This demo allows for users to perform actions with the keyboard. */ -#define mainNO_KEY_PRESS_VALUE -1 -#define mainOUTPUT_TRACE_KEY 't' -#define mainINTERRUPT_NUMBER_KEYBOARD 3 - -/* This demo allows to save a trace file. */ -#define mainTRACE_FILE_NAME "Trace.dump" - -/*-----------------------------------------------------------*/ - -/* - * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. - */ -extern void main_blinky( void ); -extern void main_full( void ); - -/* - * Only the comprehensive demo uses application hook (callback) functions. See - * https://www.FreeRTOS.org/a00016.html for more information. - */ -extern void vFullDemoTickHookFunction( void ); -extern void vFullDemoIdleFunction( void ); - -/* - * This demo uses heap_5.c, so start by defining some heap regions. It is not - * necessary for this demo to use heap_5, as it could define one large heap - * region. Heap_5 is only used for test and example purposes. See - * https://www.FreeRTOS.org/a00111.html for an explanation. - */ -static void prvInitialiseHeap( void ); - -/* - * Prototypes for the standard FreeRTOS application hook (callback) functions - * implemented within this file. See http://www.freertos.org/a00016.html . - */ -void vApplicationMallocFailedHook( void ); -void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, - char * pcTaskName ); -void vApplicationTickHook( void ); -void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, - StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ); -void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, - StackType_t ** ppxTimerTaskStackBuffer, - uint32_t * pulTimerTaskStackSize ); - -/* - * Writes trace data to a disk file when the trace recording is stopped. - * This function will simply overwrite any trace files that already exist. - */ -static void prvSaveTraceFile( void ); - -/* - * Windows thread function to capture keyboard input from outside of the - * FreeRTOS simulator. This thread passes data safely into the FreeRTOS - * simulator using a stream buffer. - */ -static DWORD WINAPI prvWindowsKeyboardInputThread( void * pvParam ); - -/* - * Interrupt handler for when keyboard input is received. - */ -static uint32_t prvKeyboardInterruptHandler( void ); - -/* - * Keyboard interrupt handler for the blinky demo. - */ -extern void vBlinkyKeyboardInterruptHandler( int xKeyPressed ); - -/*-----------------------------------------------------------*/ - -/* When configSUPPORT_STATIC_ALLOCATION is set to 1 the application writer can - * use a callback function to optionally provide the memory required by the idle - * and timer tasks. This is the stack that will be used by the timer task. It is - * declared here, as a global, so it can be checked by a test that is implemented - * in a different file. */ -StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - -/* Thread handle for the keyboard input Windows thread. */ -static HANDLE xWindowsKeyboardInputThreadHandle = NULL; - -/* This stores the last key pressed that has not been handled. - * Keyboard input is retrieved by the prvWindowsKeyboardInputThread - * Windows thread and stored here. This is then read by the idle - * task and handled appropriately. */ -static int xKeyPressed = mainNO_KEY_PRESS_VALUE; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* This demo uses heap_5.c, so start by defining some heap regions. heap_5 - * is only used for test and example reasons. Heap_4 is more appropriate. See - * http://www.freertos.org/a00111.html for an explanation. */ - prvInitialiseHeap(); - - /* Initialise the trace recorder. Use of the trace recorder is optional. - * See http://www.FreeRTOS.org/trace for more information. */ - - configASSERT( xTraceInitialize() == TRC_SUCCESS ); - - /* Start the trace recording - the recording is written to a file if - * configASSERT() is called. */ - printf( - "Trace started.\r\n" - "The trace will be dumped to the file \"%s\" whenever a call to configASSERT()\r\n" - "fails or the \'%c\' key is pressed.\r\n" - "Note that the trace output uses the ring buffer mode, meaning that the output trace\r\n" - "will only be the most recent data able to fit within the trace recorder buffer.\r\n", - mainTRACE_FILE_NAME, mainOUTPUT_TRACE_KEY ); - - configASSERT( xTraceEnable( TRC_START ) == TRC_SUCCESS ); - - /* Set interrupt handler for keyboard input. */ - vPortSetInterruptHandler( mainINTERRUPT_NUMBER_KEYBOARD, prvKeyboardInterruptHandler ); - - /* Start keyboard input handling thread. */ - xWindowsKeyboardInputThreadHandle = CreateThread( - NULL, /* Pointer to thread security attributes. */ - 0, /* Initial thread stack size, in bytes. */ - prvWindowsKeyboardInputThread, /* Pointer to thread function. */ - NULL, /* Argument for new thread. */ - 0, /* Creation flags. */ - NULL ); - - /* Use the cores that are not used by the FreeRTOS tasks for the Windows thread. */ - SetThreadAffinityMask( xWindowsKeyboardInputThreadHandle, ~0x01u ); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - * of this file. */ - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - printf( "\nStarting the blinky demo.\r\n" ); - main_blinky(); - } - #else - { - printf( "\nStarting the full demo.\r\n" ); - main_full(); - } - #endif /* if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) */ - - return 0; -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - * function that will get called if a call to pvPortMalloc() fails. - * pvPortMalloc() is called internally by the kernel whenever a task, queue, - * timer or semaphore is created. It is also called by various parts of the - * demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the - * size of the heap available to pvPortMalloc() is defined by - * configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() - * API function can be used to query the size of free heap space that remains - * (although it does not provide information on how the remaining heap might be - * fragmented). See http://www.freertos.org/a00111.html for more - * information. */ - vAssertCalled( __LINE__, __FILE__ ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - * task. It is essential that code added to this hook function never attempts - * to block in any way (for example, call xQueueReceive() with a block time - * specified, or call vTaskDelay()). If application tasks make use of the - * vTaskDelete() API function to delete themselves then it is also important - * that vApplicationIdleHook() is permitted to return to its calling function, - * because it is the responsibility of the idle task to clean up memory - * allocated by the kernel to any task that has since deleted itself. */ - - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - /* Call the idle task processing used by the full demo. The simple - * blinky demo does not use the idle task hook. */ - vFullDemoIdleFunction(); - } - #endif -} - -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( TaskHandle_t pxTask, - char * pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - * function is called if a stack overflow is detected. This function is - * provided as an example only as stack overflow checking does not function - * when running the FreeRTOS Windows port. */ - vAssertCalled( __LINE__, __FILE__ ); -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - /* This function will be called by each tick interrupt if - * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - * added here, but the tick hook is called from an interrupt context, so - * code must not attempt to block, and only the interrupt safe FreeRTOS API - * functions can be used (those that end in FromISR()). */ - - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) - { - vFullDemoTickHookFunction(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ -} -/*-----------------------------------------------------------*/ - -void vApplicationDaemonTaskStartupHook( void ) -{ - /* This function will be called once only, when the daemon task starts to - * execute (sometimes called the timer task). This is useful if the - * application includes initialisation code that would benefit from executing - * after the scheduler has been started. */ -} -/*-----------------------------------------------------------*/ - -void vAssertCalled( unsigned long ulLine, - const char * const pcFileName ) -{ - static BaseType_t xPrinted = pdFALSE; - volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; - - /* Called if an assertion passed to configASSERT() fails. See - * http://www.freertos.org/a00110.html#configASSERT for more information. */ - - /* Parameters are not used. */ - ( void ) ulLine; - ( void ) pcFileName; - - taskENTER_CRITICAL(); - { - printf( "ASSERT! Line %ld, file %s, GetLastError() %ld\r\n", ulLine, pcFileName, GetLastError() ); - - /* Stop the trace recording and save the trace. */ - ( void ) xTraceDisable(); - prvSaveTraceFile(); - - /* Cause debugger break point if being debugged. */ - __debugbreak(); - - /* You can step out of this function to debug the assertion by using - * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero - * value. */ - while( ulSetToNonZeroInDebuggerToContinue == 0 ) - { - __asm { - NOP - }; - __asm { - NOP - }; - } - - /* Re-enable the trace recording. */ - ( void ) xTraceEnable( TRC_START ); - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static void prvSaveTraceFile( void ) -{ - FILE * pxOutputFile; - - fopen_s( &pxOutputFile, mainTRACE_FILE_NAME, "wb" ); - - if( pxOutputFile != NULL ) - { - fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile ); - fclose( pxOutputFile ); - printf( "\r\nTrace output saved to %s\r\n\r\n", mainTRACE_FILE_NAME ); - } - else - { - printf( "\r\nFailed to create trace dump file\r\n\r\n" ); - } -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseHeap( void ) -{ -/* The Windows demo could create one large heap region, in which case it would - * be appropriate to use heap_4. However, purely for demonstration purposes, - * heap_5 is used instead, so start by defining some heap regions. No - * initialisation is required when any other heap implementation is used. See - * http://www.freertos.org/a00111.html for more information. - * - * The xHeapRegions structure requires the regions to be defined in start address - * order, so this just creates one big array, then populates the structure with - * offsets into the array - with gaps in between and messy alignment just for test - * purposes. */ - static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; - volatile uint32_t ulAdditionalOffset = 19; /* Just to prevent 'condition is always true' warnings in configASSERT(). */ - const HeapRegion_t xHeapRegions[] = - { - /* Start address with dummy offsets Size */ - { ucHeap + 1, mainREGION_1_SIZE }, - { ucHeap + 15 + mainREGION_1_SIZE, mainREGION_2_SIZE }, - { ucHeap + 19 + mainREGION_1_SIZE + mainREGION_2_SIZE, mainREGION_3_SIZE }, - { NULL, 0 } - }; - - /* Sanity check that the sizes and offsets defined actually fit into the - * array. */ - configASSERT( ( ulAdditionalOffset + mainREGION_1_SIZE + mainREGION_2_SIZE + mainREGION_3_SIZE ) < configTOTAL_HEAP_SIZE ); - - /* Prevent compiler warnings when configASSERT() is not defined. */ - ( void ) ulAdditionalOffset; - - vPortDefineHeapRegions( xHeapRegions ); -} -/*-----------------------------------------------------------*/ - -/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an - * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is - * used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, - StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ) -{ -/* If the buffers to be provided to the Idle task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xIdleTaskTCB; - static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - * state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - * Note that, as the array is necessarily of type StackType_t, - * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} -/*-----------------------------------------------------------*/ - -/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the - * application must provide an implementation of vApplicationGetTimerTaskMemory() - * to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, - StackType_t ** ppxTimerTaskStackBuffer, - uint32_t * pulTimerTaskStackSize ) -{ -/* If the buffers to be provided to the Timer task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xTimerTaskTCB; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - * task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - * Note that, as the array is necessarily of type StackType_t, - * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} -/*-----------------------------------------------------------*/ - -/* - * Interrupt handler for when keyboard input is received. - */ -static uint32_t prvKeyboardInterruptHandler( void ) -{ - /* Handle keyboard input. */ - switch( xKeyPressed ) - { - case mainNO_KEY_PRESS_VALUE: - break; - - case mainOUTPUT_TRACE_KEY: - /* Saving the trace file requires Windows system calls, so enter a critical - * section to prevent deadlock or errors resulting from calling a Windows - * system call from within the FreeRTOS simulator. */ - portENTER_CRITICAL(); - { - ( void ) xTraceDisable(); - prvSaveTraceFile(); - ( void ) xTraceEnable( TRC_START ); - } - portEXIT_CRITICAL(); - break; - - default: - #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - /* Call the keyboard interrupt handler for the blinky demo. */ - vBlinkyKeyboardInterruptHandler( xKeyPressed ); - #endif - break; - } - - /* This interrupt does not require a context switch so return pdFALSE */ - return pdFALSE; -} - -/*-----------------------------------------------------------*/ - -/* - * Windows thread function to capture keyboard input from outside of the - * FreeRTOS simulator. This thread passes data into the simulator using - * an integer. - */ -static DWORD WINAPI prvWindowsKeyboardInputThread( void * pvParam ) -{ - ( void ) pvParam; - - for( ; ; ) - { - /* Block on acquiring a key press. */ - xKeyPressed = _getch(); - - /* Notify FreeRTOS simulator that there is a keyboard interrupt. - * This will trigger prvKeyboardInterruptHandler. - */ - vPortGenerateSimulatedInterrupt( mainINTERRUPT_NUMBER_KEYBOARD ); - } - - /* Should not get here so return negative exit status. */ - return -1; -} - -/*-----------------------------------------------------------*/ - -/* The below code is used by the trace recorder for timing. */ -static uint32_t ulEntryTime = 0; - -void vTraceTimerReset( void ) -{ - ulEntryTime = xTaskGetTickCount(); -} - -uint32_t uiTraceTimerGetFrequency( void ) -{ - return configTICK_RATE_HZ; -} - -uint32_t uiTraceTimerGetValue( void ) -{ - return( xTaskGetTickCount() - ulEntryTime ); -} +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. + * The simply blinky demo is implemented and described in main_blinky.c. The + * more comprehensive test and demo application is implemented and described in + * main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and FreeRTOS hook functions. + * + ******************************************************************************* + * NOTE: Windows will not be running the FreeRTOS demo threads continuously, so + * do not expect to get real time behaviour from the FreeRTOS Windows port, or + * this demo application. Also, the timing information in the FreeRTOS+Trace + * logs have no meaningful units. See the documentation page for the Windows + * port for further information: + * https://www.FreeRTOS.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html + * + * + ******************************************************************************* + */ + +/* Standard includes. */ +#include +#include +#include + +#ifdef WIN32_LEAN_AND_MEAN + #include "winsock2.h" +#else + #include +#endif /* WIN32_LEAN_AND_MEAN */ + +/* Visual studio intrinsics used so the __debugbreak() function is available + * should an assert get hit. */ +#include + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+Trace includes. */ +#include "trcRecorder.h" + +/* This project provides two demo applications. A simple blinky style demo + * application, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two. + * + * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built. + * The blinky demo is implemented and described in main_blinky.c. + * + * If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and + * demo application will be built. The comprehensive test and demo application is + * implemented and described in main_full.c. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/* This demo uses heap_5.c, and these constants define the sizes of the regions + * that make up the total heap. heap_5 is only used for test and example purposes + * as this demo could easily create one large heap region instead of multiple + * smaller heap regions - in which case heap_4.c would be the more appropriate + * choice. See http://www.freertos.org/a00111.html for an explanation. */ +#define mainREGION_1_SIZE 82010 +#define mainREGION_2_SIZE 239050 +#define mainREGION_3_SIZE 168070 + +/* This demo allows for users to perform actions with the keyboard. */ +#define mainNO_KEY_PRESS_VALUE -1 +#define mainOUTPUT_TRACE_KEY 't' +#define mainINTERRUPT_NUMBER_KEYBOARD 3 + +/* This demo allows to save a trace file. */ +#define mainTRACE_FILE_NAME "Trace.dump" + +/*-----------------------------------------------------------*/ + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +extern void main_blinky( void ); +extern void main_full( void ); + +/* + * Only the comprehensive demo uses application hook (callback) functions. See + * https://www.FreeRTOS.org/a00016.html for more information. + */ +extern void vFullDemoTickHookFunction( void ); +extern void vFullDemoIdleFunction( void ); + +/* + * This demo uses heap_5.c, so start by defining some heap regions. It is not + * necessary for this demo to use heap_5, as it could define one large heap + * region. Heap_5 is only used for test and example purposes. See + * https://www.FreeRTOS.org/a00111.html for an explanation. + */ +static void prvInitialiseHeap( void ); + +/* + * Prototypes for the standard FreeRTOS application hook (callback) functions + * implemented within this file. See http://www.freertos.org/a00016.html . + */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ); +void vApplicationTickHook( void ); +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxIdleTaskStackSize ); +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ); + +/* + * Writes trace data to a disk file when the trace recording is stopped. + * This function will simply overwrite any trace files that already exist. + */ +static void prvSaveTraceFile( void ); + +/* + * Windows thread function to capture keyboard input from outside of the + * FreeRTOS simulator. This thread passes data safely into the FreeRTOS + * simulator using a stream buffer. + */ +static int32_t WINAPI prvWindowsKeyboardInputThread( void * pvParam ); + +/* + * Interrupt handler for when keyboard input is received. + */ +static uint32_t prvKeyboardInterruptHandler( void ); + +/* + * Keyboard interrupt handler for the blinky demo. + */ +extern void vBlinkyKeyboardInterruptHandler( int xKeyPressed ); + +/*-----------------------------------------------------------*/ + +/* When configSUPPORT_STATIC_ALLOCATION is set to 1 the application writer can + * use a callback function to optionally provide the memory required by the idle + * and timer tasks. This is the stack that will be used by the timer task. It is + * declared here, as a global, so it can be checked by a test that is implemented + * in a different file. */ +StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + +/* Thread handle for the keyboard input Windows thread. */ +static HANDLE xWindowsKeyboardInputThreadHandle = NULL; + +/* This stores the last key pressed that has not been handled. + * Keyboard input is retrieved by the prvWindowsKeyboardInputThread + * Windows thread and stored here. This is then read by the idle + * task and handled appropriately. */ +static int xKeyPressed = mainNO_KEY_PRESS_VALUE; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* This demo uses heap_5.c, so start by defining some heap regions. heap_5 + * is only used for test and example reasons. Heap_4 is more appropriate. See + * http://www.freertos.org/a00111.html for an explanation. */ + prvInitialiseHeap(); + + /* Initialise the trace recorder. Use of the trace recorder is optional. + * See http://www.FreeRTOS.org/trace for more information. */ + + configASSERT( xTraceInitialize() == TRC_SUCCESS ); + + /* Start the trace recording - the recording is written to a file if + * configASSERT() is called. */ + printf( + "Trace started.\r\n" + "The trace will be dumped to the file \"%s\" whenever a call to configASSERT()\r\n" + "fails or the \'%c\' key is pressed.\r\n" + "Note that the trace output uses the ring buffer mode, meaning that the output trace\r\n" + "will only be the most recent data able to fit within the trace recorder buffer.\r\n", + mainTRACE_FILE_NAME, mainOUTPUT_TRACE_KEY ); + + configASSERT( xTraceEnable( TRC_START ) == TRC_SUCCESS ); + + /* Set interrupt handler for keyboard input. */ + vPortSetInterruptHandler( mainINTERRUPT_NUMBER_KEYBOARD, prvKeyboardInterruptHandler ); + + /* Start keyboard input handling thread. */ + xWindowsKeyboardInputThreadHandle = CreateThread( + NULL, /* Pointer to thread security attributes. */ + 0, /* Initial thread stack size, in bytes. */ + prvWindowsKeyboardInputThread, /* Pointer to thread function. */ + NULL, /* Argument for new thread. */ + 0, /* Creation flags. */ + NULL ); + + /* Use the cores that are not used by the FreeRTOS tasks for the Windows thread. */ + SetThreadAffinityMask( xWindowsKeyboardInputThreadHandle, ~0x01u ); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + * of this file. */ + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + printf( "\nStarting the blinky demo.\r\n" ); + main_blinky(); + } + #else + { + printf( "\nStarting the full demo.\r\n" ); + main_full(); + } + #endif /* if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) */ + + return 0; +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + * function that will get called if a call to pvPortMalloc() fails. + * pvPortMalloc() is called internally by the kernel whenever a task, queue, + * timer or semaphore is created. It is also called by various parts of the + * demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the + * size of the heap available to pvPortMalloc() is defined by + * configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() + * API function can be used to query the size of free heap space that remains + * (although it does not provide information on how the remaining heap might be + * fragmented). See http://www.freertos.org/a00111.html for more + * information. */ + vAssertCalled( __LINE__, __FILE__ ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If application tasks make use of the + * vTaskDelete() API function to delete themselves then it is also important + * that vApplicationIdleHook() is permitted to return to its calling function, + * because it is the responsibility of the idle task to clean up memory + * allocated by the kernel to any task that has since deleted itself. */ + + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + { + /* Call the idle task processing used by the full demo. The simple + * blinky demo does not use the idle task hook. */ + vFullDemoIdleFunction(); + } + #endif +} + +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, + char * pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + * function is called if a stack overflow is detected. This function is + * provided as an example only as stack overflow checking does not function + * when running the FreeRTOS Windows port. */ + vAssertCalled( __LINE__, __FILE__ ); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + /* This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). */ + + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) + { + vFullDemoTickHookFunction(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ +} +/*-----------------------------------------------------------*/ + +void vApplicationDaemonTaskStartupHook( void ) +{ + /* This function will be called once only, when the daemon task starts to + * execute (sometimes called the timer task). This is useful if the + * application includes initialisation code that would benefit from executing + * after the scheduler has been started. */ +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( unsigned long ulLine, + const char * const pcFileName ) +{ + static BaseType_t xPrinted = pdFALSE; + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + + /* Parameters are not used. */ + ( void ) ulLine; + ( void ) pcFileName; + + taskENTER_CRITICAL(); + { + printf( "ASSERT! Line %ld, file %s, GetLastError() %ld\r\n", ulLine, pcFileName, GetLastError() ); + + /* Stop the trace recording and save the trace. */ + ( void ) xTraceDisable(); + prvSaveTraceFile(); + + /* Cause debugger break point if being debugged. */ + __debugbreak(); + + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __nop(); + } + + /* Re-enable the trace recording. */ + ( void ) xTraceEnable( TRC_START ); + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvSaveTraceFile( void ) +{ + FILE * pxOutputFile; + + fopen_s( &pxOutputFile, mainTRACE_FILE_NAME, "wb" ); + + if( pxOutputFile != NULL ) + { + fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile ); + fclose( pxOutputFile ); + printf( "\r\nTrace output saved to %s\r\n\r\n", mainTRACE_FILE_NAME ); + } + else + { + printf( "\r\nFailed to create trace dump file\r\n\r\n" ); + } +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseHeap( void ) +{ +/* The Windows demo could create one large heap region, in which case it would + * be appropriate to use heap_4. However, purely for demonstration purposes, + * heap_5 is used instead, so start by defining some heap regions. No + * initialisation is required when any other heap implementation is used. See + * http://www.freertos.org/a00111.html for more information. + * + * The xHeapRegions structure requires the regions to be defined in start address + * order, so this just creates one big array, then populates the structure with + * offsets into the array - with gaps in between and messy alignment just for test + * purposes. */ + static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; + volatile uint32_t ulAdditionalOffset = 19; /* Just to prevent 'condition is always true' warnings in configASSERT(). */ + const HeapRegion_t xHeapRegions[] = + { + /* Start address with dummy offsets Size */ + { ucHeap + 1, mainREGION_1_SIZE }, + { ucHeap + 15 + mainREGION_1_SIZE, mainREGION_2_SIZE }, + { ucHeap + 19 + mainREGION_1_SIZE + mainREGION_2_SIZE, mainREGION_3_SIZE }, + { NULL, 0 } + }; + + /* Sanity check that the sizes and offsets defined actually fit into the + * array. */ + configASSERT( ( ulAdditionalOffset + mainREGION_1_SIZE + mainREGION_2_SIZE + mainREGION_3_SIZE ) < configTOTAL_HEAP_SIZE ); + + /* Prevent compiler warnings when configASSERT() is not defined. */ + ( void ) ulAdditionalOffset; + + vPortDefineHeapRegions( xHeapRegions ); +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxIdleTaskStackSize ) +{ +/* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ + +/* + * Interrupt handler for when keyboard input is received. + */ +static uint32_t prvKeyboardInterruptHandler( void ) +{ + /* Handle keyboard input. */ + switch( xKeyPressed ) + { + case mainNO_KEY_PRESS_VALUE: + break; + + case mainOUTPUT_TRACE_KEY: + + /* Saving the trace file requires Windows system calls, so enter a critical + * section to prevent deadlock or errors resulting from calling a Windows + * system call from within the FreeRTOS simulator. */ + portENTER_CRITICAL(); + { + ( void ) xTraceDisable(); + prvSaveTraceFile(); + ( void ) xTraceEnable( TRC_START ); + } + portEXIT_CRITICAL(); + break; + + default: + #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + /* Call the keyboard interrupt handler for the blinky demo. */ + vBlinkyKeyboardInterruptHandler( xKeyPressed ); + #endif + break; + } + + /* This interrupt does not require a context switch so return pdFALSE */ + return pdFALSE; +} + +/*-----------------------------------------------------------*/ + +/* + * Windows thread function to capture keyboard input from outside of the + * FreeRTOS simulator. This thread passes data into the simulator using + * an integer. + */ +static int32_t WINAPI prvWindowsKeyboardInputThread( void * pvParam ) +{ + ( void ) pvParam; + + for( ; ; ) + { + /* Block on acquiring a key press. */ + xKeyPressed = _getch(); + + /* Notify FreeRTOS simulator that there is a keyboard interrupt. + * This will trigger prvKeyboardInterruptHandler. + */ + vPortGenerateSimulatedInterrupt( mainINTERRUPT_NUMBER_KEYBOARD ); + } + + /* Should not get here so return negative exit status. */ + return -1; +} + +/*-----------------------------------------------------------*/ + +/* The below code is used by the trace recorder for timing. */ +static uint32_t ulEntryTime = 0; + +void vTraceTimerReset( void ) +{ + ulEntryTime = xTaskGetTickCount(); +} + +uint32_t uiTraceTimerGetFrequency( void ) +{ + return configTICK_RATE_HZ; +} + +uint32_t uiTraceTimerGetValue( void ) +{ + return( xTaskGetTickCount() - ulEntryTime ); +} diff --git a/FreeRTOS/Demo/WIN32-MSVC/main_blinky.c b/FreeRTOS/Demo/WIN32-MSVC/main_blinky.c index 5ef86e6cd66..cf02ed8ded3 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/main_blinky.c +++ b/FreeRTOS/Demo/WIN32-MSVC/main_blinky.c @@ -1,305 +1,305 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/****************************************************************************** - * NOTE: Windows will not be running the FreeRTOS demo threads continuously, so - * do not expect to get real time behaviour from the FreeRTOS Windows port, or - * this demo application. Also, the timing information in the FreeRTOS+Trace - * logs have no meaningful units. See the documentation page for the Windows - * port for further information: - * https://www.FreeRTOS.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html - * - * NOTE 2: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the simply blinky version. Console output - * is used in place of the normal LED toggling. - * - * NOTE 3: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, are defined - * in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, one software timer, and two tasks. It then - * starts the scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. It uses vTaskDelayUntil() to create a periodic task that sends - * the value 100 to the queue every 200 milliseconds (please read the notes - * above regarding the accuracy of timing under Windows). - * - * The Queue Send Software Timer: - * The timer is a one-shot timer that is reset by a key press. The timer's - * period is set to two seconds - if the timer expires then its callback - * function writes the value 200 to the queue. The callback function is - * implemented by prvQueueSendTimerCallback() within this file. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() waits for data to arrive on the queue. - * When data is received, the task checks the value of the data, then outputs a - * message to indicate if the data came from the queue send task or the queue - * send software timer. - * - * Expected Behaviour: - * - The queue send task writes to the queue every 200ms, so every 200ms the - * queue receive task will output a message indicating that data was received - * on the queue from the queue send task. - * - The queue send software timer has a period of two seconds, and is reset - * each time a key is pressed. So if two seconds expire without a key being - * pressed then the queue receive task will output a message indicating that - * data was received on the queue from the queue send software timer. - * - * NOTE: Console input and output relies on Windows system calls, which can - * interfere with the execution of the FreeRTOS Windows port. This demo only - * uses Windows system call occasionally. Heavier use of Windows system calls - * can crash the port. - */ - -/* Standard includes. */ -#include -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "semphr.h" - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The times are converted from -milliseconds to ticks using the pdMS_TO_TICKS() macro. */ -#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) -#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) - -/* The number of items the queue can hold at once. */ -#define mainQUEUE_LENGTH ( 2 ) - -/* The values sent to the queue receive task from the queue send task and the -queue send software timer respectively. */ -#define mainVALUE_SENT_FROM_TASK ( 100UL ) -#define mainVALUE_SENT_FROM_TIMER ( 200UL ) - -/* This demo allows for users to perform actions with the keyboard. */ -#define mainNO_KEY_PRESS_VALUE ( -1 ) -#define mainRESET_TIMER_KEY ( 'r' ) - -/*-----------------------------------------------------------*/ - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/* - * The callback function executed when the software timer expires. - */ -static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); - -/*-----------------------------------------------------------*/ - -/* The queue used by both tasks. */ -static QueueHandle_t xQueue = NULL; - -/* A software timer that is started from the tick hook. */ -static TimerHandle_t xTimer = NULL; - -/*-----------------------------------------------------------*/ - -/*** SEE THE COMMENTS AT THE TOP OF THIS FILE ***/ -void main_blinky( void ) -{ -const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; - - printf( "\r\nStarting the blinky demo. Press \'%c\' to reset the software timer used in this demo.\r\n\r\n", mainRESET_TIMER_KEY ); - - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this simple case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Create the software timer, but don't start it yet. */ - xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ - xTimerPeriod, /* The period of the software timer in ticks. */ - pdTRUE, /* xAutoReload is set to pdTRUE, so this timer goes off periodically with a period of xTimerPeriod ticks. */ - NULL, /* The timer's ID is not used. */ - prvQueueSendTimerCallback );/* The function executed when the timer expires. */ - - xTimerStart( xTimer, 0 ); /* The scheduler has not started so use a block time of 0. */ - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, pdMS_TO_TICKS() was used to - convert a time specified in milliseconds into a time specified in ticks. - While in the Blocked state this task will not consume any CPU time. */ - vTaskDelayUntil( &xNextWakeTime, xBlockTime ); - - /* Send to the queue - causing the queue receive task to unblock and - write to the console. 0 is used as the block time so the send operation - will not block - it shouldn't need to block as the queue should always - have at least one space at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) -{ -const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; - - /* This is the software timer callback function. The software timer has a - period of two seconds and is reset each time a key is pressed. This - callback function will execute if the timer expires, which will only happen - if a key is not pressed for two seconds. */ - - /* Avoid compiler warnings resulting from the unused parameter. */ - ( void ) xTimerHandle; - - /* Send to the queue - causing the queue receive task to unblock and - write out a message. This function is called from the timer/daemon task, so - must not block. Hence the block time is set to 0. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -uint32_t ulReceivedValue; - - /* Prevent the compiler warning about the unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. It will not use any CPU time while it is in the - Blocked state. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* Enter critical section to use printf. Not doing this could potentially cause - a deadlock if the FreeRTOS simulator switches contexts and another task - tries to call printf - it should be noted that use of printf within - the FreeRTOS simulator is unsafe, but used here for simplicity. */ - taskENTER_CRITICAL(); - { - /* To get here something must have been received from the queue, but - is it an expected value? Normally calling printf() from a task is not - a good idea. Here there is lots of stack space and only one task is - using console IO so it is ok. However, note the comments at the top of - this file about the risks of making Windows system calls (such as - console output) from a FreeRTOS task. */ - if (ulReceivedValue == mainVALUE_SENT_FROM_TASK) - { - printf("Message received from task - idle time %llu%%\r\n", ulTaskGetIdleRunTimePercent()); - } - else if (ulReceivedValue == mainVALUE_SENT_FROM_TIMER) - { - printf("Message received from software timer\r\n"); - } - else - { - printf("Unexpected message\r\n"); - } - } - taskEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -/* Called from prvKeyboardInterruptSimulatorTask(), which is defined in main.c. */ -void vBlinkyKeyboardInterruptHandler( int xKeyPressed ) -{ - /* Handle keyboard input. */ - switch ( xKeyPressed ) - { - case mainRESET_TIMER_KEY: - - if ( xTimer != NULL ) - { - /* Critical section around printf to prevent a deadlock - on context switch. */ - taskENTER_CRITICAL(); - { - printf("\r\nResetting software timer.\r\n\r\n"); - } - taskEXIT_CRITICAL(); - - /* Reset the software timer. */ - xTimerReset( xTimer, portMAX_DELAY ); - } - - break; - - default: - break; - } -} - - +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/****************************************************************************** + * NOTE: Windows will not be running the FreeRTOS demo threads continuously, so + * do not expect to get real time behaviour from the FreeRTOS Windows port, or + * this demo application. Also, the timing information in the FreeRTOS+Trace + * logs have no meaningful units. See the documentation page for the Windows + * port for further information: + * https://www.FreeRTOS.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html + * + * NOTE 2: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky version. Console output + * is used in place of the normal LED toggling. + * + * NOTE 3: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, are defined + * in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, one software timer, and two tasks. It then + * starts the scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It uses vTaskDelayUntil() to create a periodic task that sends + * the value 100 to the queue every 200 milliseconds (please read the notes + * above regarding the accuracy of timing under Windows). + * + * The Queue Send Software Timer: + * The timer is a one-shot timer that is reset by a key press. The timer's + * period is set to two seconds - if the timer expires then its callback + * function writes the value 200 to the queue. The callback function is + * implemented by prvQueueSendTimerCallback() within this file. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() waits for data to arrive on the queue. + * When data is received, the task checks the value of the data, then outputs a + * message to indicate if the data came from the queue send task or the queue + * send software timer. + * + * Expected Behaviour: + * - The queue send task writes to the queue every 200ms, so every 200ms the + * queue receive task will output a message indicating that data was received + * on the queue from the queue send task. + * - The queue send software timer has a period of two seconds, and is reset + * each time a key is pressed. So if two seconds expire without a key being + * pressed then the queue receive task will output a message indicating that + * data was received on the queue from the queue send software timer. + * + * NOTE: Console input and output relies on Windows system calls, which can + * interfere with the execution of the FreeRTOS Windows port. This demo only + * uses Windows system call occasionally. Heavier use of Windows system calls + * can crash the port. + */ + +/* Standard includes. */ +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The times are converted from + * milliseconds to ticks using the pdMS_TO_TICKS() macro. */ +#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) +#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + +/* The number of items the queue can hold at once. */ +#define mainQUEUE_LENGTH ( 2 ) + +/* The values sent to the queue receive task from the queue send task and the + * queue send software timer respectively. */ +#define mainVALUE_SENT_FROM_TASK ( 100UL ) +#define mainVALUE_SENT_FROM_TIMER ( 200UL ) + +/* This demo allows for users to perform actions with the keyboard. */ +#define mainNO_KEY_PRESS_VALUE ( -1 ) +#define mainRESET_TIMER_KEY ( 'r' ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void * pvParameters ); +static void prvQueueSendTask( void * pvParameters ); + +/* + * The callback function executed when the software timer expires. + */ +static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/* A software timer that is started from the tick hook. */ +static TimerHandle_t xTimer = NULL; + +/*-----------------------------------------------------------*/ + +/*** SEE THE COMMENTS AT THE TOP OF THIS FILE ***/ +void main_blinky( void ) +{ + const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS; + + printf( "\r\nStarting the blinky demo. Press \'%c\' to reset the software timer used in this demo.\r\n\r\n", mainRESET_TIMER_KEY ); + + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + * file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this simple case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the software timer, but don't start it yet. */ + xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */ + xTimerPeriod, /* The period of the software timer in ticks. */ + pdTRUE, /* xAutoReload is set to pdTRUE, so this timer goes off periodically with a period of xTimerPeriod ticks. */ + NULL, /* The timer's ID is not used. */ + prvQueueSendTimerCallback ); /* The function executed when the timer expires. */ + + xTimerStart( xTimer, 0 ); /* The scheduler has not started so use a block time of 0. */ + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was insufficient FreeRTOS heap memory available for the idle and/or + * timer tasks to be created. See the memory management section on the + * FreeRTOS web site for more details. */ + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void * pvParameters ) +{ + TickType_t xNextWakeTime; + const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in ticks. + * While in the Blocked state this task will not consume any CPU time. */ + vTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock and + * write to the console. 0 is used as the block time so the send operation + * will not block - it shouldn't need to block as the queue should always + * have at least one space at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) +{ + const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER; + + /* This is the software timer callback function. The software timer has a + * period of two seconds and is reset each time a key is pressed. This + * callback function will execute if the timer expires, which will only happen + * if a key is not pressed for two seconds. */ + + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; + + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon task, so + * must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void * pvParameters ) +{ + uint32_t ulReceivedValue; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* Enter critical section to use printf. Not doing this could potentially cause + * a deadlock if the FreeRTOS simulator switches contexts and another task + * tries to call printf - it should be noted that use of printf within + * the FreeRTOS simulator is unsafe, but used here for simplicity. */ + taskENTER_CRITICAL(); + { + /* To get here something must have been received from the queue, but + * is it an expected value? Normally calling printf() from a task is not + * a good idea. Here there is lots of stack space and only one task is + * using console IO so it is ok. However, note the comments at the top of + * this file about the risks of making Windows system calls (such as + * console output) from a FreeRTOS task. */ + if( ulReceivedValue == mainVALUE_SENT_FROM_TASK ) + { + printf( "Message received from task - idle time %llu%%\r\n", ulTaskGetIdleRunTimePercent() ); + } + else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER ) + { + printf( "Message received from software timer\r\n" ); + } + else + { + printf( "Unexpected message\r\n" ); + } + } + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +/* Called from prvKeyboardInterruptSimulatorTask(), which is defined in main.c. */ +void vBlinkyKeyboardInterruptHandler( int xKeyPressed ) +{ + /* Handle keyboard input. */ + switch( xKeyPressed ) + { + case mainRESET_TIMER_KEY: + + if( xTimer != NULL ) + { + /* Critical section around printf to prevent a deadlock + * on context switch. */ + taskENTER_CRITICAL(); + { + printf( "\r\nResetting software timer.\r\n\r\n" ); + } + taskEXIT_CRITICAL(); + + /* Reset the software timer. */ + xTimerReset( xTimer, portMAX_DELAY ); + } + + break; + + default: + break; + } +} diff --git a/FreeRTOS/Demo/WIN32-MSVC/main_full.c b/FreeRTOS/Demo/WIN32-MSVC/main_full.c index 9b98c09ebe6..c8e582e9d7b 100644 --- a/FreeRTOS/Demo/WIN32-MSVC/main_full.c +++ b/FreeRTOS/Demo/WIN32-MSVC/main_full.c @@ -1,816 +1,821 @@ -/* - * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/* - ******************************************************************************* - * NOTE 1: The Win32 port is a simulation (or is that emulation?) only! Do not - * expect to get real time behaviour from the Win32 port or this demo - * application. It is provided as a convenient development and demonstration - * test bed only. - * - * Windows will not be running the FreeRTOS simulator threads continuously, so - * the timing information in the FreeRTOS+Trace logs have no meaningful units. - * See the documentation page for the Windows simulator for an explanation of - * the slow timing: - * https://www.FreeRTOS.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html - * - READ THE WEB DOCUMENTATION FOR THIS PORT FOR MORE INFORMATION ON USING IT - - * - * NOTE 2: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the comprehensive test and demo version. - * - * NOTE 3: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, are defined in - * main.c. - ******************************************************************************* - * - * main() creates all the demo application tasks, then starts the scheduler. - * The web documentation provides more details of the standard demo application - * tasks, which provide no particular functionality but do provide a good - * example of how to use the FreeRTOS API. - * - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Check" task - This only executes every five seconds but has a high priority - * to ensure it gets processor time. Its main function is to check that all the - * standard demo tasks are still operational. While no errors have been - * discovered the check task will print out "OK" and the current simulated tick - * time. If an error is discovered in the execution of a task then the check - * task will print out an appropriate error message. - * - */ - - -/* Standard includes. */ -#include -#include - -/* Kernel includes. */ -#include -#include -#include -#include -#include - -/* Standard demo includes. */ -#include "BlockQ.h" -#include "integer.h" -#include "semtest.h" -#include "PollQ.h" -#include "GenQTest.h" -#include "QPeek.h" -#include "recmutex.h" -#include "flop.h" -#include "TimerDemo.h" -#include "countsem.h" -#include "death.h" -#include "dynamic.h" -#include "QueueSet.h" -#include "QueueOverwrite.h" -#include "EventGroupsDemo.h" -#include "IntSemTest.h" -#include "TaskNotify.h" -#include "TaskNotifyArray.h" -#include "QueueSetPolling.h" -#include "StaticAllocation.h" -#include "blocktim.h" -#include "AbortDelay.h" -#include "MessageBufferDemo.h" -#include "StreamBufferDemo.h" -#include "StreamBufferInterrupt.h" -#include "MessageBufferAMP.h" - -/* Priorities at which the tasks are created. */ -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) - -#define mainTIMER_TEST_PERIOD ( 50 ) - -/* Task function prototypes. */ -static void prvCheckTask( void *pvParameters ); - -/* A task that is created from the idle task to test the functionality of -eTaskStateGet(). */ -static void prvTestTask( void *pvParameters ); - -/* - * Called from the idle task hook function to demonstrate a few utility - * functions that are not demonstrated by any of the standard demo tasks. - */ -static void prvDemonstrateTaskStateAndHandleGetFunctions( void ); - -/* - * Called from the idle task hook function to demonstrate the use of - * xTimerPendFunctionCall() as xTimerPendFunctionCall() is not demonstrated by - * any of the standard demo tasks. - */ -static void prvDemonstratePendingFunctionCall( void ); - -/* - * The function that is pended by prvDemonstratePendingFunctionCall(). - */ -static void prvPendedFunction( void *pvParameter1, uint32_t ulParameter2 ); - -/* - * prvDemonstrateTimerQueryFunctions() is called from the idle task hook - * function to demonstrate the use of functions that query information about a - * software timer. prvTestTimerCallback() is the callback function for the - * timer being queried. - */ -static void prvDemonstrateTimerQueryFunctions( void ); -static void prvTestTimerCallback( TimerHandle_t xTimer ); - -/* - * A task to demonstrate the use of the xQueueSpacesAvailable() function. - */ -static void prvDemoQueueSpaceFunctions( void *pvParameters ); - -/* - * Tasks that ensure indefinite delays are truly indefinite. - */ -static void prvPermanentlyBlockingSemaphoreTask( void *pvParameters ); -static void prvPermanentlyBlockingNotificationTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The variable into which error messages are latched. */ -static char *pcStatusMessage = "No errors"; - -/* This semaphore is created purely to test using the vSemaphoreDelete() and -semaphore tracing API functions. It has no other purpose. */ -static SemaphoreHandle_t xMutexToDelete = NULL; - -/*-----------------------------------------------------------*/ - -int main_full( void ) -{ - /* Start the check task as described at the top of this file. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Create the standard demo tasks. */ - vStartTaskNotifyTask(); - vStartTaskNotifyArrayTask(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); - vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); - vStartQueuePeekTasks(); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartCountingSemaphoreTasks(); - vStartDynamicPriorityTasks(); - vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); - vStartEventGroupTasks(); - vStartInterruptSemaphoreTasks(); - vCreateBlockTimeTasks(); - vCreateAbortDelayTasks(); - xTaskCreate( prvDemoQueueSpaceFunctions, "QSpace", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvPermanentlyBlockingSemaphoreTask, "BlockSem", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvPermanentlyBlockingNotificationTask, "BlockNoti", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - vStartMessageBufferTasks( configMINIMAL_STACK_SIZE ); - vStartStreamBufferTasks(); - vStartStreamBufferInterruptDemo(); - vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE ); - - #if( configUSE_QUEUE_SETS == 1 ) - { - vStartQueueSetTasks(); - vStartQueueSetPollingTask(); - } - #endif - - #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - { - vStartStaticallyAllocatedTasks(); - } - #endif - - #if( configUSE_PREEMPTION != 0 ) - { - /* Don't expect these tasks to pass when preemption is not used. */ - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - } - #endif - - /* The suicide tasks must be created last as they need to know how many - tasks were running prior to their creation. This then allows them to - ascertain whether or not the correct/expected number of tasks are running at - any given time. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Create the semaphore that will be deleted in the idle task hook. This - is done purely to test the use of vSemaphoreDelete(). */ - xMutexToDelete = xSemaphoreCreateMutex(); - - /* Start the scheduler itself. */ - vTaskStartScheduler(); - - /* Should never get here unless there was not enough heap space to create - the idle and other system tasks. */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const TickType_t xCycleFrequency = pdMS_TO_TICKS( 5000UL ); -HeapStats_t xHeapStats; - - /* Just to remove compiler warning. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. */ - vTaskDelayUntil( &xNextWakeTime, xCycleFrequency ); - - /* Check the standard demo tasks are running without error. */ - #if( configUSE_PREEMPTION != 0 ) - { - /* These tasks are only created when preemption is used. */ - if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE ) - { - pcStatusMessage = "Error: TimerDemo"; - } - } - #endif - - if( xAreStreamBufferTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: StreamBuffer"; - } - else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: MessageBuffer"; - } - else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: Notification"; - } - else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: NotificationArray"; - } - else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: IntSem"; - } - else if( xAreEventGroupTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: EventGroup"; - } - else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: IntMath"; - } - else if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: GenQueue"; - } - else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: QueuePeek"; - } - else if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: BlockQueue"; - } - else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: SemTest"; - } - else if( xArePollingQueuesStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: PollQueue"; - } - else if( xAreMathsTaskStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Flop"; - } - else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: RecMutex"; - } - else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: CountSem"; - } - else if( xIsCreateTaskStillRunning() != pdTRUE ) - { - pcStatusMessage = "Error: Death"; - } - else if( xAreDynamicPriorityTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Dynamic"; - } - else if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Queue overwrite"; - } - else if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Block time"; - } - else if( xAreAbortDelayTestTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Abort delay"; - } - else if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Stream buffer interrupt"; - } - else if( xAreMessageBufferAMPTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Message buffer AMP"; - } - - #if( configUSE_QUEUE_SETS == 1 ) - else if( xAreQueueSetTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Queue set"; - } - else if( xAreQueueSetPollTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Queue set polling"; - } - #endif - - #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - else if( xAreStaticAllocationTasksStillRunning() != pdPASS ) - { - pcStatusMessage = "Error: Static allocation"; - } - #endif /* configSUPPORT_STATIC_ALLOCATION */ - - /* This is the only task that uses stdout so its ok to call printf() - directly. */ - vPortGetHeapStats( &xHeapStats ); - - configASSERT( xHeapStats.xAvailableHeapSpaceInBytes == xPortGetFreeHeapSize() ); - configASSERT( xHeapStats.xMinimumEverFreeBytesRemaining == xPortGetMinimumEverFreeHeapSize() ); - - printf( "%s - tick count %zu - free heap %zu - min free heap %zu - largest free block %zu - idle time %llu%%\r\n", - pcStatusMessage, - xTaskGetTickCount(), - xHeapStats.xAvailableHeapSpaceInBytes, - xHeapStats.xMinimumEverFreeBytesRemaining, - xHeapStats.xSizeOfLargestFreeBlockInBytes, - ulTaskGetIdleRunTimePercent() ); - } -} -/*-----------------------------------------------------------*/ - -static void prvTestTask( void *pvParameters ) -{ -const unsigned long ulMSToSleep = 5; - - /* Just to remove compiler warnings. */ - ( void ) pvParameters; - - /* This task is just used to test the eTaskStateGet() function. It - does not have anything to do. */ - for( ;; ) - { - /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are - tasks waiting to be terminated by the idle task. */ - Sleep( ulMSToSleep ); - } -} -/*-----------------------------------------------------------*/ - -/* Called from vApplicationIdleHook(), which is defined in main.c. */ -void vFullDemoIdleFunction( void ) -{ -const unsigned long ulMSToSleep = 15; -void *pvAllocated; - - /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are - tasks waiting to be terminated by the idle task. */ - Sleep( ulMSToSleep ); - - /* Demonstrate a few utility functions that are not demonstrated by any of - the standard demo tasks. */ - prvDemonstrateTaskStateAndHandleGetFunctions(); - - /* Demonstrate the use of xTimerPendFunctionCall(), which is not - demonstrated by any of the standard demo tasks. */ - prvDemonstratePendingFunctionCall(); - - /* Demonstrate the use of functions that query information about a software - timer. */ - prvDemonstrateTimerQueryFunctions(); - - - /* If xMutexToDelete has not already been deleted, then delete it now. - This is done purely to demonstrate the use of, and test, the - vSemaphoreDelete() macro. Care must be taken not to delete a semaphore - that has tasks blocked on it. */ - if( xMutexToDelete != NULL ) - { - /* For test purposes, add the mutex to the registry, then remove it - again, before it is deleted - checking its name is as expected before - and after the assertion into the registry and its removal from the - registry. */ - configASSERT( pcQueueGetName( xMutexToDelete ) == NULL ); - vQueueAddToRegistry( xMutexToDelete, "Test_Mutex" ); - configASSERT( strcmp( pcQueueGetName( xMutexToDelete ), "Test_Mutex" ) == 0 ); - vQueueUnregisterQueue( xMutexToDelete ); - configASSERT( pcQueueGetName( xMutexToDelete ) == NULL ); - - vSemaphoreDelete( xMutexToDelete ); - xMutexToDelete = NULL; - } - - /* Exercise heap_5 a bit. The malloc failed hook will trap failed - allocations so there is no need to test here. */ - pvAllocated = pvPortMalloc( ( rand() % 500 ) + 1 ); - vPortFree( pvAllocated ); -} -/*-----------------------------------------------------------*/ - -/* Called by vApplicationTickHook(), which is defined in main.c. */ -void vFullDemoTickHookFunction( void ) -{ -TaskHandle_t xTimerTask; - - /* Call the periodic timer test, which tests the timer API functions that - can be called from an ISR. */ - #if( configUSE_PREEMPTION != 0 ) - { - /* Only created when preemption is used. */ - vTimerPeriodicISRTests(); - } - #endif - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - #if( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */ - { - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - vQueueSetPollingInterruptAccess(); - } - #endif - - /* Exercise event groups from interrupts. */ - vPeriodicEventGroupsProcessing(); - - /* Exercise giving mutexes from an interrupt. */ - vInterruptSemaphorePeriodicTest(); - - /* Exercise using task notifications from an interrupt. */ - xNotifyTaskFromISR(); - xNotifyArrayTaskFromISR(); - - /* Writes to stream buffer byte by byte to test the stream buffer trigger - level functionality. */ - vPeriodicStreamBufferProcessing(); - - /* Writes a string to a string buffer four bytes at a time to demonstrate - a stream being sent from an interrupt to a task. */ - vBasicStreamBufferSendFromISR(); - - /* For code coverage purposes. */ - xTimerTask = xTimerGetTimerDaemonTaskHandle(); - configASSERT( uxTaskPriorityGetFromISR( xTimerTask ) == configTIMER_TASK_PRIORITY ); -} -/*-----------------------------------------------------------*/ - -static void prvPendedFunction( void *pvParameter1, uint32_t ulParameter2 ) -{ -static uint32_t ulLastParameter1 = 1000UL, ulLastParameter2 = 0UL; -uint32_t ulParameter1; - - ulParameter1 = ( uint32_t ) pvParameter1; - - /* Ensure the parameters are as expected. */ - configASSERT( ulParameter1 == ( ulLastParameter1 + 1 ) ); - configASSERT( ulParameter2 == ( ulLastParameter2 + 1 ) ); - - /* Remember the parameters for the next time the function is called. */ - ulLastParameter1 = ulParameter1; - ulLastParameter2 = ulParameter2; -} -/*-----------------------------------------------------------*/ - -static void prvTestTimerCallback( TimerHandle_t xTimer ) -{ - /* This is the callback function for the timer accessed by - prvDemonstrateTimerQueryFunctions(). The callback does not do anything. */ - ( void ) xTimer; -} -/*-----------------------------------------------------------*/ - -static void prvDemonstrateTimerQueryFunctions( void ) -{ -static TimerHandle_t xTimer = NULL; -const char *pcTimerName = "TestTimer"; -volatile TickType_t xExpiryTime; -const TickType_t xDontBlock = 0; - - if( xTimer == NULL ) - { - xTimer = xTimerCreate( pcTimerName, portMAX_DELAY, pdTRUE, NULL, prvTestTimerCallback ); - - if( xTimer != NULL ) - { - /* Called from the idle task so a block time must not be - specified. */ - xTimerStart( xTimer, xDontBlock ); - } - } - - if( xTimer != NULL ) - { - /* Demonstrate querying a timer's name. */ - configASSERT( strcmp( pcTimerGetName( xTimer ), pcTimerName ) == 0 ); - - /* Demonstrate querying a timer's period. */ - configASSERT( xTimerGetPeriod( xTimer ) == portMAX_DELAY ); - - /* Demonstrate querying a timer's next expiry time, although nothing is - done with the returned value. Note if the expiry time is less than the - maximum tick count then the expiry time has overflowed from the current - time. In this case the expiry time was set to portMAX_DELAY, so it is - expected to be less than the current time until the current time has - itself overflowed. */ - xExpiryTime = xTimerGetExpiryTime( xTimer ); - ( void ) xExpiryTime; - } -} -/*-----------------------------------------------------------*/ - -static void prvDemonstratePendingFunctionCall( void ) -{ -static uint32_t ulParameter1 = 1000UL, ulParameter2 = 0UL; -const TickType_t xDontBlock = 0; /* This is called from the idle task so must *not* attempt to block. */ - - /* prvPendedFunction() just expects the parameters to be incremented by one - each time it is called. */ - ulParameter1++; - ulParameter2++; - - /* Pend the function call, sending the parameters. */ - xTimerPendFunctionCall( prvPendedFunction, ( void * ) ulParameter1, ulParameter2, xDontBlock ); -} -/*-----------------------------------------------------------*/ - -static void prvDemonstrateTaskStateAndHandleGetFunctions( void ) -{ -TaskHandle_t xIdleTaskHandle, xTimerTaskHandle; -char *pcTaskName; -static portBASE_TYPE xPerformedOneShotTests = pdFALSE; -TaskHandle_t xTestTask; -TaskStatus_t xTaskInfo; -extern StackType_t uxTimerTaskStack[]; - - /* Demonstrate the use of the xTimerGetTimerDaemonTaskHandle() and - xTaskGetIdleTaskHandle() functions. Also try using the function that sets - the task number. */ - xIdleTaskHandle = xTaskGetIdleTaskHandle(); - xTimerTaskHandle = xTimerGetTimerDaemonTaskHandle(); - - /* This is the idle hook, so the current task handle should equal the - returned idle task handle. */ - if( xTaskGetCurrentTaskHandle() != xIdleTaskHandle ) - { - pcStatusMessage = "Error: Returned idle task handle was incorrect"; - } - - /* Check the same handle is obtained using the idle task's name. First try - with the wrong name, then the right name. */ - if( xTaskGetHandle( "Idle" ) == xIdleTaskHandle ) - { - pcStatusMessage = "Error: Returned handle for name Idle was incorrect"; - } - - if( xTaskGetHandle( "IDLE" ) != xIdleTaskHandle ) - { - pcStatusMessage = "Error: Returned handle for name Idle was incorrect"; - } - - /* Check the timer task handle was returned correctly. */ - pcTaskName = pcTaskGetName( xTimerTaskHandle ); - if( strcmp( pcTaskName, "Tmr Svc" ) != 0 ) - { - pcStatusMessage = "Error: Returned timer task handle was incorrect"; - } - - if( xTaskGetHandle( "Tmr Svc" ) != xTimerTaskHandle ) - { - pcStatusMessage = "Error: Returned handle for name Tmr Svc was incorrect"; - } - - /* This task is running, make sure it's state is returned as running. */ - if( eTaskStateGet( xIdleTaskHandle ) != eRunning ) - { - pcStatusMessage = "Error: Returned idle task state was incorrect"; - } - - /* If this task is running, then the timer task must be blocked. */ - if( eTaskStateGet( xTimerTaskHandle ) != eBlocked ) - { - pcStatusMessage = "Error: Returned timer task state was incorrect"; - } - - /* Also with the vTaskGetInfo() function. */ - vTaskGetInfo( xTimerTaskHandle, /* The task being queried. */ - &xTaskInfo, /* The structure into which information on the task will be written. */ - pdTRUE, /* Include the task's high watermark in the structure. */ - eInvalid ); /* Include the task state in the structure. */ - - /* Check the information returned by vTaskGetInfo() is as expected. */ - if( ( xTaskInfo.eCurrentState != eBlocked ) || - ( strcmp( xTaskInfo.pcTaskName, "Tmr Svc" ) != 0 ) || - ( xTaskInfo.uxCurrentPriority != configTIMER_TASK_PRIORITY ) || - ( xTaskInfo.pxStackBase != uxTimerTaskStack ) || - ( xTaskInfo.xHandle != xTimerTaskHandle ) ) - { - pcStatusMessage = "Error: vTaskGetInfo() returned incorrect information about the timer task"; - } - - /* Other tests that should only be performed once follow. The test task - is not created on each iteration because to do so would cause the death - task to report an error (too many tasks running). */ - if( xPerformedOneShotTests == pdFALSE ) - { - /* Don't run this part of the test again. */ - xPerformedOneShotTests = pdTRUE; - - /* Create a test task to use to test other eTaskStateGet() return values. */ - if( xTaskCreate( prvTestTask, "Test", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTestTask ) == pdPASS ) - { - /* If this task is running, the test task must be in the ready state. */ - if( eTaskStateGet( xTestTask ) != eReady ) - { - pcStatusMessage = "Error: Returned test task state was incorrect 1"; - } - - /* Now suspend the test task and check its state is reported correctly. */ - vTaskSuspend( xTestTask ); - if( eTaskStateGet( xTestTask ) != eSuspended ) - { - pcStatusMessage = "Error: Returned test task state was incorrect 2"; - } - - /* Now delete the task and check its state is reported correctly. */ - vTaskDelete( xTestTask ); - if( eTaskStateGet( xTestTask ) != eDeleted ) - { - pcStatusMessage = "Error: Returned test task state was incorrect 3"; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvDemoQueueSpaceFunctions( void *pvParameters ) -{ -QueueHandle_t xQueue = NULL; -const unsigned portBASE_TYPE uxQueueLength = 10; -unsigned portBASE_TYPE uxReturn, x; - - /* Remove compiler warnings. */ - ( void ) pvParameters; - - /* Create the queue that will be used. Nothing is actually going to be - sent or received so the queue item size is set to 0. */ - xQueue = xQueueCreate( uxQueueLength, 0 ); - configASSERT( xQueue ); - - for( ;; ) - { - for( x = 0; x < uxQueueLength; x++ ) - { - /* Ask how many messages are available... */ - uxReturn = uxQueueMessagesWaiting( xQueue ); - - /* Check the number of messages being reported as being available - is as expected, and force an assert if not. */ - if( uxReturn != x ) - { - /* xQueue cannot be NULL so this is deliberately causing an - assert to be triggered as there is an error. */ - configASSERT( xQueue == NULL ); - } - - /* Ask how many spaces remain in the queue... */ - uxReturn = uxQueueSpacesAvailable( xQueue ); - - /* Check the number of spaces being reported as being available - is as expected, and force an assert if not. */ - if( uxReturn != ( uxQueueLength - x ) ) - { - /* xQueue cannot be NULL so this is deliberately causing an - assert to be triggered as there is an error. */ - configASSERT( xQueue == NULL ); - } - - /* Fill one more space in the queue. */ - xQueueSendToBack( xQueue, NULL, 0 ); - } - - /* Perform the same check while the queue is full. */ - uxReturn = uxQueueMessagesWaiting( xQueue ); - if( uxReturn != uxQueueLength ) - { - configASSERT( xQueue == NULL ); - } - - uxReturn = uxQueueSpacesAvailable( xQueue ); - - if( uxReturn != 0 ) - { - configASSERT( xQueue == NULL ); - } - - /* The queue is full, start again. */ - xQueueReset( xQueue ); - - #if( configUSE_PREEMPTION == 0 ) - taskYIELD(); - #endif - } -} -/*-----------------------------------------------------------*/ - -static void prvPermanentlyBlockingSemaphoreTask( void *pvParameters ) -{ -SemaphoreHandle_t xSemaphore; - - /* Prevent compiler warning about unused parameter in the case that - configASSERT() is not defined. */ - ( void ) pvParameters; - - /* This task should block on a semaphore, and never return. */ - xSemaphore = xSemaphoreCreateBinary(); - configASSERT( xSemaphore ); - - xSemaphoreTake( xSemaphore, portMAX_DELAY ); - - /* The above xSemaphoreTake() call should never return, force an assert if - it does. */ - configASSERT( pvParameters != NULL ); - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvPermanentlyBlockingNotificationTask( void *pvParameters ) -{ - /* Prevent compiler warning about unused parameter in the case that - configASSERT() is not defined. */ - ( void ) pvParameters; - - /* This task should block on a task notification, and never return. */ - ulTaskNotifyTake( pdTRUE, portMAX_DELAY ); - - /* The above ulTaskNotifyTake() call should never return, force an assert - if it does. */ - configASSERT( pvParameters != NULL ); - vTaskDelete( NULL ); -} - - - +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + ******************************************************************************* + * NOTE 1: The Win32 port is a simulation (or is that emulation?) only! Do not + * expect to get real time behaviour from the Win32 port or this demo + * application. It is provided as a convenient development and demonstration + * test bed only. + * + * Windows will not be running the FreeRTOS simulator threads continuously, so + * the timing information in the FreeRTOS+Trace logs have no meaningful units. + * See the documentation page for the Windows simulator for an explanation of + * the slow timing: + * https://www.FreeRTOS.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html + * - READ THE WEB DOCUMENTATION FOR THIS PORT FOR MORE INFORMATION ON USING IT - + * + * NOTE 2: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the comprehensive test and demo version. + * + * NOTE 3: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, are defined in + * main.c. + ******************************************************************************* + * + * main() creates all the demo application tasks, then starts the scheduler. + * The web documentation provides more details of the standard demo application + * tasks, which provide no particular functionality but do provide a good + * example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Check" task - This only executes every five seconds but has a high priority + * to ensure it gets processor time. Its main function is to check that all the + * standard demo tasks are still operational. While no errors have been + * discovered the check task will print out "OK" and the current simulated tick + * time. If an error is discovered in the execution of a task then the check + * task will print out an appropriate error message. + * + */ + + +/* Standard includes. */ +#include +#include + +/* Kernel includes. */ +#include +#include +#include +#include +#include + +/* Standard demo includes. */ +#include "BlockQ.h" +#include "integer.h" +#include "semtest.h" +#include "PollQ.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "recmutex.h" +#include "flop.h" +#include "TimerDemo.h" +#include "countsem.h" +#include "death.h" +#include "dynamic.h" +#include "QueueSet.h" +#include "QueueOverwrite.h" +#include "EventGroupsDemo.h" +#include "IntSemTest.h" +#include "TaskNotify.h" +#include "TaskNotifyArray.h" +#include "QueueSetPolling.h" +#include "StaticAllocation.h" +#include "blocktim.h" +#include "AbortDelay.h" +#include "MessageBufferDemo.h" +#include "StreamBufferDemo.h" +#include "StreamBufferInterrupt.h" +#include "MessageBufferAMP.h" + +/* Priorities at which the tasks are created. */ +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +#define mainTIMER_TEST_PERIOD ( 50 ) + +/* Task function prototypes. */ +static void prvCheckTask( void * pvParameters ); + +/* A task that is created from the idle task to test the functionality of + * eTaskStateGet(). */ +static void prvTestTask( void * pvParameters ); + +/* + * Called from the idle task hook function to demonstrate a few utility + * functions that are not demonstrated by any of the standard demo tasks. + */ +static void prvDemonstrateTaskStateAndHandleGetFunctions( void ); + +/* + * Called from the idle task hook function to demonstrate the use of + * xTimerPendFunctionCall() as xTimerPendFunctionCall() is not demonstrated by + * any of the standard demo tasks. + */ +static void prvDemonstratePendingFunctionCall( void ); + +/* + * The function that is pended by prvDemonstratePendingFunctionCall(). + */ +static void prvPendedFunction( void * pvParameter1, + uint32_t ulParameter2 ); + +/* + * prvDemonstrateTimerQueryFunctions() is called from the idle task hook + * function to demonstrate the use of functions that query information about a + * software timer. prvTestTimerCallback() is the callback function for the + * timer being queried. + */ +static void prvDemonstrateTimerQueryFunctions( void ); +static void prvTestTimerCallback( TimerHandle_t xTimer ); + +/* + * A task to demonstrate the use of the xQueueSpacesAvailable() function. + */ +static void prvDemoQueueSpaceFunctions( void * pvParameters ); + +/* + * Tasks that ensure indefinite delays are truly indefinite. + */ +static void prvPermanentlyBlockingSemaphoreTask( void * pvParameters ); +static void prvPermanentlyBlockingNotificationTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The variable into which error messages are latched. */ +static char * pcStatusMessage = "No errors"; + +/* This semaphore is created purely to test using the vSemaphoreDelete() and + * semaphore tracing API functions. It has no other purpose. */ +static SemaphoreHandle_t xMutexToDelete = NULL; + +/*-----------------------------------------------------------*/ + +int main_full( void ) +{ + /* Start the check task as described at the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the standard demo tasks. */ + vStartTaskNotifyTask(); + vStartTaskNotifyArrayTask(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartCountingSemaphoreTasks(); + vStartDynamicPriorityTasks(); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartInterruptSemaphoreTasks(); + vCreateBlockTimeTasks(); + vCreateAbortDelayTasks(); + xTaskCreate( prvDemoQueueSpaceFunctions, "QSpace", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvPermanentlyBlockingSemaphoreTask, "BlockSem", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvPermanentlyBlockingNotificationTask, "BlockNoti", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + vStartMessageBufferTasks( configMINIMAL_STACK_SIZE ); + vStartStreamBufferTasks(); + vStartStreamBufferInterruptDemo(); + vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE ); + + #if ( configUSE_QUEUE_SETS == 1 ) + { + vStartQueueSetTasks(); + vStartQueueSetPollingTask(); + } + #endif + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + vStartStaticallyAllocatedTasks(); + } + #endif + + #if ( configUSE_PREEMPTION != 0 ) + { + /* Don't expect these tasks to pass when preemption is not used. */ + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + } + #endif + + /* The suicide tasks must be created last as they need to know how many + * tasks were running prior to their creation. This then allows them to + * ascertain whether or not the correct/expected number of tasks are running at + * any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Create the semaphore that will be deleted in the idle task hook. This + * is done purely to test the use of vSemaphoreDelete(). */ + xMutexToDelete = xSemaphoreCreateMutex(); + + /* Start the scheduler itself. */ + vTaskStartScheduler(); + + /* Should never get here unless there was not enough heap space to create + * the idle and other system tasks. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void * pvParameters ) +{ + TickType_t xNextWakeTime; + const TickType_t xCycleFrequency = pdMS_TO_TICKS( 5000UL ); + HeapStats_t xHeapStats; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, xCycleFrequency ); + + /* Check the standard demo tasks are running without error. */ + #if ( configUSE_PREEMPTION != 0 ) + { + /* These tasks are only created when preemption is used. */ + if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE ) + { + pcStatusMessage = "Error: TimerDemo"; + } + } + #endif + + if( xAreStreamBufferTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: StreamBuffer"; + } + else if( xAreMessageBufferTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: MessageBuffer"; + } + else if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: Notification"; + } + else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: NotificationArray"; + } + else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: IntSem"; + } + else if( xAreEventGroupTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: EventGroup"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: IntMath"; + } + else if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: GenQueue"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: QueuePeek"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: BlockQueue"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: SemTest"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: PollQueue"; + } + else if( xAreMathsTaskStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Flop"; + } + else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: RecMutex"; + } + else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: CountSem"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + pcStatusMessage = "Error: Death"; + } + else if( xAreDynamicPriorityTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Dynamic"; + } + else if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Queue overwrite"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Block time"; + } + else if( xAreAbortDelayTestTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Abort delay"; + } + else if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Stream buffer interrupt"; + } + else if( xAreMessageBufferAMPTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Message buffer AMP"; + } + + #if ( configUSE_QUEUE_SETS == 1 ) + else if( xAreQueueSetTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Queue set"; + } + else if( xAreQueueSetPollTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Queue set polling"; + } + #endif + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + else if( xAreStaticAllocationTasksStillRunning() != pdPASS ) + { + pcStatusMessage = "Error: Static allocation"; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + /* This is the only task that uses stdout so its ok to call printf() + * directly. */ + vPortGetHeapStats( &xHeapStats ); + + configASSERT( xHeapStats.xAvailableHeapSpaceInBytes == xPortGetFreeHeapSize() ); + configASSERT( xHeapStats.xMinimumEverFreeBytesRemaining == xPortGetMinimumEverFreeHeapSize() ); + + printf( "%s - tick count %zu - free heap %zu - min free heap %zu - largest free block %zu - idle time %llu%%\r\n", + pcStatusMessage, + xTaskGetTickCount(), + xHeapStats.xAvailableHeapSpaceInBytes, + xHeapStats.xMinimumEverFreeBytesRemaining, + xHeapStats.xSizeOfLargestFreeBlockInBytes, + ulTaskGetIdleRunTimePercent() ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTestTask( void * pvParameters ) +{ + const unsigned long ulMSToSleep = 5; + + /* Just to remove compiler warnings. */ + ( void ) pvParameters; + + /* This task is just used to test the eTaskStateGet() function. It + * does not have anything to do. */ + for( ; ; ) + { + /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are + * tasks waiting to be terminated by the idle task. */ + Sleep( ulMSToSleep ); + } +} +/*-----------------------------------------------------------*/ + +/* Called from vApplicationIdleHook(), which is defined in main.c. */ +void vFullDemoIdleFunction( void ) +{ + const unsigned long ulMSToSleep = 15; + void * pvAllocated; + + /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are + * tasks waiting to be terminated by the idle task. */ + Sleep( ulMSToSleep ); + + /* Demonstrate a few utility functions that are not demonstrated by any of + * the standard demo tasks. */ + prvDemonstrateTaskStateAndHandleGetFunctions(); + + /* Demonstrate the use of xTimerPendFunctionCall(), which is not + * demonstrated by any of the standard demo tasks. */ + prvDemonstratePendingFunctionCall(); + + /* Demonstrate the use of functions that query information about a software + * timer. */ + prvDemonstrateTimerQueryFunctions(); + + /* If xMutexToDelete has not already been deleted, then delete it now. + * This is done purely to demonstrate the use of, and test, the + * vSemaphoreDelete() macro. Care must be taken not to delete a semaphore + * that has tasks blocked on it. */ + if( xMutexToDelete != NULL ) + { + /* For test purposes, add the mutex to the registry, then remove it + * again, before it is deleted - checking its name is as expected before + * and after the assertion into the registry and its removal from the + * registry. */ + configASSERT( pcQueueGetName( xMutexToDelete ) == NULL ); + vQueueAddToRegistry( xMutexToDelete, "Test_Mutex" ); + configASSERT( strcmp( pcQueueGetName( xMutexToDelete ), "Test_Mutex" ) == 0 ); + vQueueUnregisterQueue( xMutexToDelete ); + configASSERT( pcQueueGetName( xMutexToDelete ) == NULL ); + + vSemaphoreDelete( xMutexToDelete ); + xMutexToDelete = NULL; + } + + /* Exercise heap_5 a bit. The malloc failed hook will trap failed + * allocations so there is no need to test here. */ + pvAllocated = pvPortMalloc( ( size_t )( rand() % 500 ) + 1 ); + vPortFree( pvAllocated ); +} +/*-----------------------------------------------------------*/ + +/* Called by vApplicationTickHook(), which is defined in main.c. */ +void vFullDemoTickHookFunction( void ) +{ + TaskHandle_t xTimerTask; + + /* Call the periodic timer test, which tests the timer API functions that + * can be called from an ISR. */ + #if ( configUSE_PREEMPTION != 0 ) + { + /* Only created when preemption is used. */ + vTimerPeriodicISRTests(); + } + #endif + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + #if ( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */ + { + /* Write to a queue that is in use as part of the queue set demo to + * demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + vQueueSetPollingInterruptAccess(); + } + #endif + + /* Exercise event groups from interrupts. */ + vPeriodicEventGroupsProcessing(); + + /* Exercise giving mutexes from an interrupt. */ + vInterruptSemaphorePeriodicTest(); + + /* Exercise using task notifications from an interrupt. */ + xNotifyTaskFromISR(); + xNotifyArrayTaskFromISR(); + + /* Writes to stream buffer byte by byte to test the stream buffer trigger + * level functionality. */ + vPeriodicStreamBufferProcessing(); + + /* Writes a string to a string buffer four bytes at a time to demonstrate + * a stream being sent from an interrupt to a task. */ + vBasicStreamBufferSendFromISR(); + + /* For code coverage purposes. */ + xTimerTask = xTimerGetTimerDaemonTaskHandle(); + configASSERT( uxTaskPriorityGetFromISR( xTimerTask ) == configTIMER_TASK_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +static void prvPendedFunction( void * pvParameter1, + uint32_t ulParameter2 ) +{ + static UBaseType_t uxLastParameter1 = 1000UL; + static uint32_t ulLastParameter2 = 0UL; + UBaseType_t uxParameter1; + + uxParameter1 = ( UBaseType_t ) pvParameter1; + + /* Ensure the parameters are as expected. */ + configASSERT( uxParameter1 == ( uxLastParameter1 + 1 ) ); + configASSERT( ulParameter2 == ( ulLastParameter2 + 1 ) ); + + /* Remember the parameters for the next time the function is called. */ + uxLastParameter1 = uxParameter1; + ulLastParameter2 = ulParameter2; +} +/*-----------------------------------------------------------*/ + +static void prvTestTimerCallback( TimerHandle_t xTimer ) +{ + /* This is the callback function for the timer accessed by + * prvDemonstrateTimerQueryFunctions(). The callback does not do anything. */ + ( void ) xTimer; +} +/*-----------------------------------------------------------*/ + +static void prvDemonstrateTimerQueryFunctions( void ) +{ + static TimerHandle_t xTimer = NULL; + const char * pcTimerName = "TestTimer"; + volatile TickType_t xExpiryTime; + const TickType_t xDontBlock = 0; + + if( xTimer == NULL ) + { + xTimer = xTimerCreate( pcTimerName, portMAX_DELAY, pdTRUE, NULL, prvTestTimerCallback ); + + if( xTimer != NULL ) + { + /* Called from the idle task so a block time must not be + * specified. */ + xTimerStart( xTimer, xDontBlock ); + } + } + + if( xTimer != NULL ) + { + /* Demonstrate querying a timer's name. */ + configASSERT( strcmp( pcTimerGetName( xTimer ), pcTimerName ) == 0 ); + + /* Demonstrate querying a timer's period. */ + configASSERT( xTimerGetPeriod( xTimer ) == portMAX_DELAY ); + + /* Demonstrate querying a timer's next expiry time, although nothing is + * done with the returned value. Note if the expiry time is less than the + * maximum tick count then the expiry time has overflowed from the current + * time. In this case the expiry time was set to portMAX_DELAY, so it is + * expected to be less than the current time until the current time has + * itself overflowed. */ + xExpiryTime = xTimerGetExpiryTime( xTimer ); + ( void ) xExpiryTime; + } +} +/*-----------------------------------------------------------*/ + +static void prvDemonstratePendingFunctionCall( void ) +{ + static UBaseType_t uxParameter1 = 1000UL; + static uint32_t ulParameter2 = 0UL; + const TickType_t xDontBlock = 0; /* This is called from the idle task so must *not* attempt to block. */ + + /* prvPendedFunction() just expects the parameters to be incremented by one + * each time it is called. */ + + uxParameter1++; + ulParameter2++; + + /* Pend the function call, sending the parameters. */ + xTimerPendFunctionCall( prvPendedFunction, ( void * ) uxParameter1, ulParameter2, xDontBlock ); +} +/*-----------------------------------------------------------*/ + +static void prvDemonstrateTaskStateAndHandleGetFunctions( void ) +{ + TaskHandle_t xIdleTaskHandle, xTimerTaskHandle; + char * pcTaskName; + static portBASE_TYPE xPerformedOneShotTests = pdFALSE; + TaskHandle_t xTestTask; + TaskStatus_t xTaskInfo; + extern StackType_t uxTimerTaskStack[]; + + /* Demonstrate the use of the xTimerGetTimerDaemonTaskHandle() and + * xTaskGetIdleTaskHandle() functions. Also try using the function that sets + * the task number. */ + xIdleTaskHandle = xTaskGetIdleTaskHandle(); + xTimerTaskHandle = xTimerGetTimerDaemonTaskHandle(); + + /* This is the idle hook, so the current task handle should equal the + * returned idle task handle. */ + if( xTaskGetCurrentTaskHandle() != xIdleTaskHandle ) + { + pcStatusMessage = "Error: Returned idle task handle was incorrect"; + } + + /* Check the same handle is obtained using the idle task's name. First try + * with the wrong name, then the right name. */ + if( xTaskGetHandle( "Idle" ) == xIdleTaskHandle ) + { + pcStatusMessage = "Error: Returned handle for name Idle was incorrect"; + } + + if( xTaskGetHandle( "IDLE" ) != xIdleTaskHandle ) + { + pcStatusMessage = "Error: Returned handle for name Idle was incorrect"; + } + + /* Check the timer task handle was returned correctly. */ + pcTaskName = pcTaskGetName( xTimerTaskHandle ); + + if( strcmp( pcTaskName, "Tmr Svc" ) != 0 ) + { + pcStatusMessage = "Error: Returned timer task handle was incorrect"; + } + + if( xTaskGetHandle( "Tmr Svc" ) != xTimerTaskHandle ) + { + pcStatusMessage = "Error: Returned handle for name Tmr Svc was incorrect"; + } + + /* This task is running, make sure it's state is returned as running. */ + if( eTaskStateGet( xIdleTaskHandle ) != eRunning ) + { + pcStatusMessage = "Error: Returned idle task state was incorrect"; + } + + /* If this task is running, then the timer task must be blocked. */ + if( eTaskStateGet( xTimerTaskHandle ) != eBlocked ) + { + pcStatusMessage = "Error: Returned timer task state was incorrect"; + } + + /* Also with the vTaskGetInfo() function. */ + vTaskGetInfo( xTimerTaskHandle, /* The task being queried. */ + &xTaskInfo, /* The structure into which information on the task will be written. */ + pdTRUE, /* Include the task's high watermark in the structure. */ + eInvalid ); /* Include the task state in the structure. */ + + /* Check the information returned by vTaskGetInfo() is as expected. */ + if( ( xTaskInfo.eCurrentState != eBlocked ) || + ( strcmp( xTaskInfo.pcTaskName, "Tmr Svc" ) != 0 ) || + ( xTaskInfo.uxCurrentPriority != configTIMER_TASK_PRIORITY ) || + ( xTaskInfo.pxStackBase != uxTimerTaskStack ) || + ( xTaskInfo.xHandle != xTimerTaskHandle ) ) + { + pcStatusMessage = "Error: vTaskGetInfo() returned incorrect information about the timer task"; + } + + /* Other tests that should only be performed once follow. The test task + * is not created on each iteration because to do so would cause the death + * task to report an error (too many tasks running). */ + if( xPerformedOneShotTests == pdFALSE ) + { + /* Don't run this part of the test again. */ + xPerformedOneShotTests = pdTRUE; + + /* Create a test task to use to test other eTaskStateGet() return values. */ + if( xTaskCreate( prvTestTask, "Test", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTestTask ) == pdPASS ) + { + /* If this task is running, the test task must be in the ready state. */ + if( eTaskStateGet( xTestTask ) != eReady ) + { + pcStatusMessage = "Error: Returned test task state was incorrect 1"; + } + + /* Now suspend the test task and check its state is reported correctly. */ + vTaskSuspend( xTestTask ); + + if( eTaskStateGet( xTestTask ) != eSuspended ) + { + pcStatusMessage = "Error: Returned test task state was incorrect 2"; + } + + /* Now delete the task and check its state is reported correctly. */ + vTaskDelete( xTestTask ); + + if( eTaskStateGet( xTestTask ) != eDeleted ) + { + pcStatusMessage = "Error: Returned test task state was incorrect 3"; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvDemoQueueSpaceFunctions( void * pvParameters ) +{ + QueueHandle_t xQueue = NULL; + const unsigned portBASE_TYPE uxQueueLength = 10; + unsigned portBASE_TYPE uxReturn, x; + + /* Remove compiler warnings. */ + ( void ) pvParameters; + + /* Create the queue that will be used. Nothing is actually going to be + * sent or received so the queue item size is set to 0. */ + xQueue = xQueueCreate( uxQueueLength, 0 ); + configASSERT( xQueue ); + + for( ; ; ) + { + for( x = 0; x < uxQueueLength; x++ ) + { + /* Ask how many messages are available... */ + uxReturn = uxQueueMessagesWaiting( xQueue ); + + /* Check the number of messages being reported as being available + * is as expected, and force an assert if not. */ + if( uxReturn != x ) + { + /* xQueue cannot be NULL so this is deliberately causing an + * assert to be triggered as there is an error. */ + configASSERT( xQueue == NULL ); + } + + /* Ask how many spaces remain in the queue... */ + uxReturn = uxQueueSpacesAvailable( xQueue ); + + /* Check the number of spaces being reported as being available + * is as expected, and force an assert if not. */ + if( uxReturn != ( uxQueueLength - x ) ) + { + /* xQueue cannot be NULL so this is deliberately causing an + * assert to be triggered as there is an error. */ + configASSERT( xQueue == NULL ); + } + + /* Fill one more space in the queue. */ + xQueueSendToBack( xQueue, NULL, 0 ); + } + + /* Perform the same check while the queue is full. */ + uxReturn = uxQueueMessagesWaiting( xQueue ); + + if( uxReturn != uxQueueLength ) + { + configASSERT( xQueue == NULL ); + } + + uxReturn = uxQueueSpacesAvailable( xQueue ); + + if( uxReturn != 0 ) + { + configASSERT( xQueue == NULL ); + } + + /* The queue is full, start again. */ + xQueueReset( xQueue ); + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static void prvPermanentlyBlockingSemaphoreTask( void * pvParameters ) +{ + SemaphoreHandle_t xSemaphore; + + /* Prevent compiler warning about unused parameter in the case that + * configASSERT() is not defined. */ + ( void ) pvParameters; + + /* This task should block on a semaphore, and never return. */ + xSemaphore = xSemaphoreCreateBinary(); + configASSERT( xSemaphore ); + + xSemaphoreTake( xSemaphore, portMAX_DELAY ); + + /* The above xSemaphoreTake() call should never return, force an assert if + * it does. */ + configASSERT( pvParameters != NULL ); + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvPermanentlyBlockingNotificationTask( void * pvParameters ) +{ + /* Prevent compiler warning about unused parameter in the case that + * configASSERT() is not defined. */ + ( void ) pvParameters; + + /* This task should block on a task notification, and never return. */ + ulTaskNotifyTake( pdTRUE, portMAX_DELAY ); + + /* The above ulTaskNotifyTake() call should never return, force an assert + * if it does. */ + configASSERT( pvParameters != NULL ); + vTaskDelete( NULL ); +} diff --git a/FreeRTOS/Demo/WIN32-MingW/.cproject b/FreeRTOS/Demo/WIN32-MingW/.cproject index 0cc3eaa9372..89dd1c2386f 100644 --- a/FreeRTOS/Demo/WIN32-MingW/.cproject +++ b/FreeRTOS/Demo/WIN32-MingW/.cproject @@ -30,7 +30,8 @@