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cputest.cpp
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#include "cputest.h"
#include "cputbl_test.h"
#include "readcpu.h"
#include "disasm.h"
#include "ini.h"
#include "fpp.h"
#include "zlib.h"
#include "options.h"
#define MAX_REGISTERS 16
static uae_u32 registers[] =
{
0x00000010,
0x00000000,
0xffffffff,
0xffffff00,
0xffff0000,
0x80008080,
0x7fff7fff,
0xaaaaaaaa,
0x00000000,
0x00000080,
0x00008000,
0x00007fff,
0xfffffffe,
0xffffff00,
0x00000000, // replaced with opcode memory
0x00000000 // replaced with stack
};
static floatx80 fpuregisters[8];
static uae_u32 fpu_fpiar, fpu_fpcr, fpu_fpsr;
const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };
const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 };
int movem_index1[256];
int movem_index2[256];
int movem_next[256];
int hardware_bus_error, hardware_bus_error_fake;
struct mmufixup mmufixup[2];
cpuop_func *cpufunctbl[65536];
struct cputbl_data
{
uae_s16 length;
uae_s8 disp020[2];
uae_u8 branch;
};
static struct cputbl_data cpudatatbl[65536];
struct regstruct regs;
struct flag_struct regflags;
int cpu_cycles;
static int verbose = 1;
static int feature_exception3_data = 0;
static int feature_exception3_instruction = 0;
static int feature_sr_mask = 0;
static int feature_min_interrupt_mask = 0;
static int feature_loop_mode = 0;
static int feature_loop_mode_register = -1;
static int feature_loop_mode_68010 = 0;
static int feature_full_extension_format = 0;
static int feature_test_rounds = 2;
static int feature_flag_mode = 0;
static int feature_usp = 0;
static int feature_exception_vectors = 0;
static int feature_interrupts = 0;
static int feature_randomize = 0;
static TCHAR *feature_instruction_size = NULL;
static uae_u32 feature_addressing_modes[2];
static int feature_gzip = 0;
static int ad8r[2], pc8r[2];
static int multi_mode;
#define MAX_TARGET_EA 20
static uae_u32 feature_target_ea[MAX_TARGET_EA][3];
static int target_ea_src_cnt, target_ea_dst_cnt, target_ea_opcode_cnt;
static int target_ea_src_max, target_ea_dst_max, target_ea_opcode_max;
static uae_u32 target_ea[3];
static int maincpu[6];
#define HIGH_MEMORY_START (addressing_mask == 0xffffffff ? 0xffff8000 : 0x00ff8000)
// large enough for RTD
#define STACK_SIZE (0x8000 + 8)
#define RESERVED_SUPERSTACK 1024
// space between superstack and USP
#define RESERVED_USERSTACK_EXTRA 64
// space for extra exception, not part of test region
#define EXTRA_RESERVED_SPACE 1024
static uae_u32 test_low_memory_start;
static uae_u32 test_low_memory_end;
static uae_u32 test_high_memory_start;
static uae_u32 test_high_memory_end;
static uae_u32 low_memory_size = 32768;
static uae_u32 high_memory_size = 32768;
static uae_u32 safe_memory_start;
static uae_u32 safe_memory_end;
static int safe_memory_mode;
static uae_u32 user_stack_memory, super_stack_memory;
static uae_u32 user_stack_memory_use;
static uae_u8 *low_memory, *high_memory, *test_memory;
static uae_u8 *low_memory_temp, *high_memory_temp, *test_memory_temp;
static uae_u8 dummy_memory[4];
static uaecptr test_memory_start, test_memory_end, opcode_memory_start;
static uae_u32 test_memory_size;
static int hmem_rom, lmem_rom;
static uae_u8 *opcode_memory;
static uae_u8 *storage_buffer;
static char inst_name[16+1];
static int storage_buffer_watermark_size;
static int storage_buffer_watermark;
static int max_storage_buffer;
static bool out_of_test_space;
static uaecptr out_of_test_space_addr;
static int forced_immediate_mode;
static int test_exception;
static int test_exception_extra;
static int exception_stack_frame_size;
static uae_u8 exception_extra_frame[100];
static int exception_extra_frame_size, exception_extra_frame_type;
static uaecptr test_exception_addr;
static int test_exception_3_w;
static int test_exception_3_fc;
static int test_exception_3_size;
static int test_exception_3_di;
static int test_exception_opcode;
static uae_u32 trace_store_pc;
static uae_u16 trace_store_sr;
static uae_u8 imm8_cnt;
static uae_u16 imm16_cnt;
static uae_u32 imm32_cnt;
static uae_u32 immabsl_cnt;
static uae_u32 addressing_mask;
static int opcodecnt;
static int cpu_stopped;
static int cpu_halted;
static int cpu_lvl = 0;
static int test_count;
static int testing_active;
static uae_u16 testing_active_opcode;
static time_t starttime;
static int filecount;
static uae_u16 sr_undefined_mask;
static int low_memory_accessed;
static int high_memory_accessed;
static int test_memory_accessed;
static uae_u16 extra_or, extra_and;
static uae_u32 cur_registers[MAX_REGISTERS];
static uae_u16 read_buffer_prev;
static int interrupt_count;
struct uae_prefs currprefs;
struct accesshistory
{
uaecptr addr;
uae_u32 val;
uae_u32 oldval;
int size;
bool donotsave;
};
static int ahcnt_current, ahcnt_written;
static int noaccesshistory = 0;
#define MAX_ACCESSHIST 16000
static struct accesshistory ahist[MAX_ACCESSHIST];
static int is_superstack_use_required(void)
{
switch (testing_active_opcode)
{
case 0x4e73: // RTE
return 1;
}
return 0;
}
#define OPCODE_AREA 32
#define BRANCHTARGET_AREA 4
static bool valid_address(uaecptr addr, int size, int w)
{
addr &= addressing_mask;
size--;
if (low_memory_size != 0xffffffff && addr + size < low_memory_size) {
if (addr < test_low_memory_start || test_low_memory_start == 0xffffffff)
goto oob;
// exception vectors needed during tests
if ((addr + size >= 0x08 && addr < 0x30 || (addr + size >= 0x80 && addr < 0xc0)) && regs.vbr == 0)
goto oob;
if (addr + size >= test_low_memory_end)
goto oob;
if (w && lmem_rom)
goto oob;
low_memory_accessed = w ? -1 : 1;
return 1;
}
if (high_memory_size != 0xffffffff && addr >= HIGH_MEMORY_START && addr <= HIGH_MEMORY_START + 0x7fff) {
if (addr < test_high_memory_start || test_high_memory_start == 0xffffffff)
goto oob;
if (addr + size >= test_high_memory_end)
goto oob;
if (w && hmem_rom)
goto oob;
high_memory_accessed = w ? -1 : 1;
return 1;
}
if (addr >= super_stack_memory - RESERVED_SUPERSTACK && addr + size < super_stack_memory) {
// allow only instructions that have to access super stack, for example RTE
// read-only
if (w) {
goto oob;
}
if (testing_active) {
if (is_superstack_use_required()) {
test_memory_accessed = 1;
return 1;
}
}
goto oob;
}
if (addr >= test_memory_end && addr + size < test_memory_end + EXTRA_RESERVED_SPACE) {
if (testing_active < 0)
return 1;
}
if (addr >= test_memory_start && addr + size < test_memory_end) {
// make sure we don't modify our test instruction
if (testing_active && w) {
if (addr >= opcode_memory_start && addr + size < opcode_memory_start + OPCODE_AREA)
goto oob;
}
test_memory_accessed = w ? -1 : 1;
return 1;
}
oob:
return 0;
}
static bool is_nowrite_address(uaecptr addr, int size)
{
return addr + size > safe_memory_start && addr < safe_memory_end;
}
static void validate_addr(uaecptr addr, int size)
{
if (valid_address(addr, size, 0))
return;
wprintf(_T(" Trying to store invalid memory address %08x!?\n"), addr);
abort();
}
static uae_u8 *get_addr(uaecptr addr, int size, int w)
{
// allow debug output to read memory even if oob condition
if (w >= 0 && out_of_test_space)
goto oob;
if (!valid_address(addr, 1, w))
goto oob;
if (size > 1) {
if (!valid_address(addr + size - 1, 1, w))
goto oob;
}
addr &= addressing_mask;
size--;
if (low_memory_size != 0xffffffff && addr + size < low_memory_size) {
return low_memory + addr;
} else if (high_memory_size != 0xffffffff && addr >= HIGH_MEMORY_START && addr <= HIGH_MEMORY_START + 0x7fff) {
return high_memory + (addr - HIGH_MEMORY_START);
} else if (addr >= test_memory_start && addr + size < test_memory_end + EXTRA_RESERVED_SPACE) {
return test_memory + (addr - test_memory_start);
}
oob:
if (w >= 0) {
if (!out_of_test_space) {
out_of_test_space = true;
out_of_test_space_addr = addr;
}
}
dummy_memory[0] = 0;
dummy_memory[1] = 0;
dummy_memory[2] = 0;
dummy_memory[3] = 0;
return dummy_memory;
}
void do_cycles_test(int cycles)
{
if (!testing_active)
return;
cpu_cycles += cycles;
}
static void add_memory_cycles(int c)
{
if (!testing_active)
return;
if (trace_store_pc != 0xffffffff)
return;
cpu_cycles += c * 4;
}
static void check_bus_error(uaecptr addr, int write, int fc)
{
if (!testing_active)
return;
if (safe_memory_start == 0xffffffff && safe_memory_end == 0xffffffff)
return;
if (addr >= safe_memory_start && addr < safe_memory_end) {
hardware_bus_error_fake = -1;
if ((safe_memory_mode & 4) && !write && (fc & 2)) {
hardware_bus_error |= 4;
hardware_bus_error_fake |= 1;
} else if ((safe_memory_mode & 1) && !write && !(fc & 2)) {
hardware_bus_error |= 1;
hardware_bus_error_fake |= 1;
} else if ((safe_memory_mode & 2) && write) {
hardware_bus_error |= 2;
hardware_bus_error_fake |= 2;
}
if (!write && (fc & 2) && feature_usp == 3) {
out_of_test_space = true;
out_of_test_space_addr = addr;
}
}
}
static uae_u8 get_ibyte_test(uaecptr addr)
{
check_bus_error(addr, 0, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 0);
add_memory_cycles(1);
return *p;
}
static uae_u16 get_iword_test(uaecptr addr)
{
check_bus_error(addr, 0, regs.s ? 6 : 2);
if (addr & 1) {
return (get_ibyte_test(addr + 0) << 8) | (get_ibyte_test(addr + 1) << 0);
} else {
uae_u8 *p = get_addr(addr, 2, 0);
add_memory_cycles(1);
return (p[0] << 8) | (p[1]);
}
}
uae_u16 get_word_test_prefetch(int o)
{
// no real prefetch
if (cpu_lvl < 2)
o -= 2;
add_memory_cycles(-1);
regs.irc = get_iword_test(m68k_getpci() + o + 2);
read_buffer_prev = regs.read_buffer;
regs.read_buffer = regs.irc;
return get_iword_test(m68k_getpci() + o);
}
static void previoussame(uaecptr addr, int size)
{
if (!ahcnt_current || ahcnt_current == ahcnt_written)
return;
// Move from SR does two writes to same address.
// Loop mode can write different values to same address.
// Mark old values as do not save.
for (int i = ahcnt_written; i < ahcnt_current; i++) {
struct accesshistory *ah = &ahist[i];
if (ah->size == size && ah->addr == addr) {
ah->donotsave = true;
}
if (size == sz_long) {
if (ah->size == sz_word && ah->addr == addr) {
ah->donotsave = true;
}
if (ah->size == sz_word && ah->addr == addr + 2) {
ah->donotsave = true;
}
}
}
}
void put_byte_test(uaecptr addr, uae_u32 v)
{
if (!testing_active && is_nowrite_address(addr, 1))
return;
check_bus_error(addr, 1, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 1);
if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
previoussame(addr, sz_byte);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
abort();
}
struct accesshistory *ah = &ahist[ahcnt_current++];
ah->addr = addr;
ah->val = v & 0xff;
ah->oldval = *p;
ah->size = sz_byte;
ah->donotsave = false;
}
regs.write_buffer &= 0xff00;
regs.write_buffer |= v & 0xff;
*p = v;
add_memory_cycles(1);
}
void put_word_test(uaecptr addr, uae_u32 v)
{
if (!testing_active && is_nowrite_address(addr, 1))
return;
check_bus_error(addr, 1, regs.s ? 5 : 1);
if (addr & 1) {
put_byte_test(addr + 0, v >> 8);
put_byte_test(addr + 1, v >> 0);
} else {
uae_u8 *p = get_addr(addr, 2, 1);
if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
previoussame(addr, sz_word);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
abort();
}
struct accesshistory *ah = &ahist[ahcnt_current++];
ah->addr = addr;
ah->val = v & 0xffff;
ah->oldval = (p[0] << 8) | p[1];
ah->size = sz_word;
ah->donotsave = false;
}
p[0] = v >> 8;
p[1] = v & 0xff;
}
regs.write_buffer = v;
add_memory_cycles(1);
}
void put_long_test(uaecptr addr, uae_u32 v)
{
if (!testing_active && is_nowrite_address(addr, 1))
return;
check_bus_error(addr, 1, regs.s ? 5 : 1);
if (addr & 1) {
put_byte_test(addr + 0, v >> 24);
put_word_test(addr + 1, v >> 8);
put_byte_test(addr + 3, v >> 0);
} else if (addr & 2) {
put_word_test(addr + 0, v >> 16);
put_word_test(addr + 2, v >> 0);
} else {
uae_u8 *p = get_addr(addr, 4, 1);
if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
previoussame(addr, sz_long);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
abort();
}
struct accesshistory *ah = &ahist[ahcnt_current++];
ah->addr = addr;
ah->val = v;
ah->oldval = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
ah->size = sz_long;
ah->donotsave = false;
}
p[0] = v >> 24;
p[1] = v >> 16;
p[2] = v >> 8;
p[3] = v >> 0;
add_memory_cycles(2);
}
regs.write_buffer = v;
}
static void undo_memory(struct accesshistory *ahp, int end)
{
out_of_test_space = 0;
noaccesshistory = 1;
for (int i = ahcnt_current - 1; i >= end; i--) {
struct accesshistory *ah = &ahp[i];
switch (ah->size)
{
case sz_byte:
put_byte_test(ah->addr, ah->oldval);
break;
case sz_word:
put_word_test(ah->addr, ah->oldval);
break;
case sz_long:
put_long_test(ah->addr, ah->oldval);
break;
}
}
noaccesshistory = 0;
if (out_of_test_space) {
wprintf(_T(" undo_memory out of test space fault!?\n"));
abort();
}
ahcnt_current = end;
}
uae_u32 get_byte_test(uaecptr addr)
{
check_bus_error(addr, 0, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 0);
read_buffer_prev = regs.read_buffer;
regs.read_buffer &= 0xff00;
regs.read_buffer |= *p;
add_memory_cycles(1);
return *p;
}
uae_u32 get_word_test(uaecptr addr)
{
uae_u16 v;
check_bus_error(addr, 0, regs.s ? 5 : 1);
if (addr & 1) {
v = (get_byte_test(addr + 0) << 8) | (get_byte_test(addr + 1) << 0);
} else {
uae_u8 *p = get_addr(addr, 2, 0);
v = (p[0] << 8) | (p[1]);
}
read_buffer_prev = regs.read_buffer;
regs.read_buffer = v;
add_memory_cycles(1);
return v;
}
uae_u32 get_long_test(uaecptr addr)
{
uae_u32 v;
check_bus_error(addr, 0, regs.s ? 5 : 1);
if (addr & 1) {
uae_u8 v0 = get_byte_test(addr + 0);
uae_u16 v1 = get_word_test(addr + 1);
uae_u8 v3 = get_byte_test(addr + 3);
v = (v0 << 24) | (v1 << 8) | (v3 << 0);
} else if (addr & 2) {
uae_u16 v0 = get_word_test(addr + 0);
uae_u16 v1 = get_word_test(addr + 2);
v = (v0 << 16) | (v1 << 0);
} else {
uae_u8 *p = get_addr(addr, 4, 0);
v = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]);
add_memory_cycles(2);
}
read_buffer_prev = regs.read_buffer;
regs.read_buffer = v;
return v;
}
uae_u32 get_byte_debug(uaecptr addr)
{
uae_u8 *p = get_addr(addr, 1, -1);
return *p;
}
uae_u32 get_word_debug(uaecptr addr)
{
uae_u8 *p = get_addr(addr, 2, -1);
return (p[0] << 8) | (p[1]);
}
uae_u32 get_long_debug(uaecptr addr)
{
uae_u8 *p = get_addr(addr, 4, -1);
return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]);
}
uae_u32 get_iword_debug(uaecptr addr)
{
return get_word_debug(addr);
}
uae_u32 get_ilong_debug(uaecptr addr)
{
return get_long_debug(addr);
}
uae_u32 get_byte_cache_debug(uaecptr addr, bool *cached)
{
*cached = false;
return get_byte_test(addr);
}
uae_u32 get_word_cache_debug(uaecptr addr, bool *cached)
{
*cached = false;
return get_word_test(addr);
}
uae_u32 get_long_cache_debug(uaecptr addr, bool *cached)
{
*cached = false;
return get_long_test(addr);
}
uae_u32 sfc_nommu_get_byte(uaecptr addr)
{
return get_byte_test(addr);
}
uae_u32 sfc_nommu_get_word(uaecptr addr)
{
return get_word_test(addr);
}
uae_u32 sfc_nommu_get_long(uaecptr addr)
{
return get_long_test(addr);
}
void dfc_nommu_put_byte(uaecptr addr, uae_u32 v)
{
put_byte_test(addr, v);
}
void dfc_nommu_put_word(uaecptr addr, uae_u32 v)
{
put_word_test(addr, v);
}
void dfc_nommu_put_long(uaecptr addr, uae_u32 v)
{
put_long_test(addr, v);
}
uae_u16 get_wordi_test(int o)
{
uae_u32 v = get_word_test_prefetch(o);
regs.pc += 2;
return v;
}
uae_u32 memory_get_byte(uaecptr addr)
{
return get_byte_test(addr);
}
uae_u32 memory_get_word(uaecptr addr)
{
return get_word_test(addr);
}
uae_u32 memory_get_wordi(uaecptr addr)
{
return get_word_test(addr);
}
uae_u32 memory_get_long(uaecptr addr)
{
return get_long_test(addr);
}
uae_u32 memory_get_longi(uaecptr addr)
{
return get_long_test(addr);
}
void memory_put_long(uaecptr addr, uae_u32 v)
{
put_long_test(addr, v);
}
void memory_put_word(uaecptr addr, uae_u32 v)
{
put_word_test(addr, v);
}
void memory_put_byte(uaecptr addr, uae_u32 v)
{
put_byte_test(addr, v);
}
uae_u8 *memory_get_real_address(uaecptr addr)
{
return NULL;
}
uae_u32 next_iword_test(void)
{
uae_u32 v = get_word_test_prefetch(0);
regs.pc += 2;
return v;
}
uae_u32 next_ilong_test(void)
{
uae_u32 v = get_word_test_prefetch(0) << 16;
v |= get_word_test_prefetch(2);
regs.pc += 4;
return v;
}
bool mmu_op30(uaecptr pc, uae_u32 opcode, uae_u16 extra, uaecptr extraa)
{
m68k_setpc(pc);
op_illg(opcode);
return true;
}
bool is_cycle_ce(uaecptr addr)
{
return 0;
}
void ipl_fetch(void)
{
}
int intlev(void)
{
return 0;
}
uae_u32(*x_get_long)(uaecptr);
uae_u32(*x_get_word)(uaecptr);
uae_u32(*x_get_byte)(uaecptr);
void (*x_put_long)(uaecptr, uae_u32);
void (*x_put_word)(uaecptr, uae_u32);
void (*x_put_byte)(uaecptr, uae_u32);
uae_u32(*x_cp_get_long)(uaecptr);
uae_u32(*x_cp_get_word)(uaecptr);
uae_u32(*x_cp_get_byte)(uaecptr);
void (*x_cp_put_long)(uaecptr, uae_u32);
void (*x_cp_put_word)(uaecptr, uae_u32);
void (*x_cp_put_byte)(uaecptr, uae_u32);
uae_u32(*x_cp_next_iword)(void);
uae_u32(*x_cp_next_ilong)(void);
uae_u32(*x_next_iword)(void);
uae_u32(*x_next_ilong)(void);
void (*x_do_cycles)(unsigned long);
uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
void m68k_do_rts_ce(void)
{
uaecptr pc;
pc = x_get_word(m68k_areg(regs, 7)) << 16;
pc |= x_get_word(m68k_areg(regs, 7) + 2);
m68k_areg(regs, 7) += 4;
m68k_setpci(pc);
}
void m68k_do_bsr_ce(uaecptr oldpc, uae_s32 offset)
{
m68k_areg(regs, 7) -= 4;
x_put_word(m68k_areg(regs, 7), oldpc >> 16);
x_put_word(m68k_areg(regs, 7) + 2, oldpc);
m68k_incpci(offset);
}
void m68k_do_jsr_ce(uaecptr oldpc, uaecptr dest)
{
m68k_areg(regs, 7) -= 4;
x_put_word(m68k_areg(regs, 7), oldpc >> 16);
x_put_word(m68k_areg(regs, 7) + 2, oldpc);
m68k_setpci(dest);
}
static int SPCFLAG_TRACE, SPCFLAG_DOTRACE;
uae_u32 get_disp_ea_test(uae_u32 base, uae_u32 dp)
{
int reg = (dp >> 12) & 15;
uae_s32 regd = regs.regs[reg];
if ((dp & 0x800) == 0)
regd = (uae_s32)(uae_s16)regd;
return base + (uae_s8)dp + regd;
}
static void activate_trace(void)
{
SPCFLAG_TRACE = 0;
SPCFLAG_DOTRACE = 1;
}
static void do_trace(void)
{
regs.trace_pc = regs.pc;
if (regs.t0 && !regs.t1 && currprefs.cpu_model >= 68020) {
// this is obsolete
return;
}
if (regs.t1) {
activate_trace();
}
}
void REGPARAM2 MakeSR(void)
{
regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
| (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
| (GET_XFLG() << 4) | (GET_NFLG() << 3)
| (GET_ZFLG() << 2) | (GET_VFLG() << 1)
| GET_CFLG());
}
void MakeFromSR_x(int t0trace)
{
int oldm = regs.m;
int olds = regs.s;
int oldt0 = regs.t0;
int oldt1 = regs.t1;
SET_XFLG((regs.sr >> 4) & 1);
SET_NFLG((regs.sr >> 3) & 1);
SET_ZFLG((regs.sr >> 2) & 1);
SET_VFLG((regs.sr >> 1) & 1);
SET_CFLG(regs.sr & 1);
if (regs.t1 == ((regs.sr >> 15) & 1) &&
regs.t0 == ((regs.sr >> 14) & 1) &&
regs.s == ((regs.sr >> 13) & 1) &&
regs.m == ((regs.sr >> 12) & 1) &&
regs.intmask == ((regs.sr >> 8) & 7))
return;
regs.t1 = (regs.sr >> 15) & 1;
regs.t0 = (regs.sr >> 14) & 1;
regs.s = (regs.sr >> 13) & 1;
regs.m = (regs.sr >> 12) & 1;
regs.intmask = (regs.sr >> 8) & 7;
if (currprefs.cpu_model >= 68020) {
/* 68060 does not have MSP but does have M-bit.. */
if (currprefs.cpu_model >= 68060)
regs.msp = regs.isp;
if (olds != regs.s) {
if (olds) {
if (oldm)
regs.msp = m68k_areg (regs, 7);
else
regs.isp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.usp;
} else {
regs.usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
}
} else if (olds && oldm != regs.m) {
if (oldm) {
regs.msp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.isp;
} else {
regs.isp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.msp;
}
}
if (currprefs.cpu_model >= 68060)
regs.t0 = 0;
} else {
regs.t0 = regs.m = 0;
if (olds != regs.s) {
if (olds) {
regs.isp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.usp;
} else {
regs.usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.isp;
}
}
}
if (regs.t1 || regs.t0) {
SPCFLAG_TRACE = 1;
} else {
/* Keep SPCFLAG_DOTRACE, we still want a trace exception for
SR-modifying instructions (including STOP). */
SPCFLAG_TRACE = 0;
}
// STOP SR-modification does not generate T0
// If this SR modification set Tx bit, no trace until next instruction.
if ((oldt0 && t0trace && currprefs.cpu_model >= 68020) || oldt1) {
// Always trace if Tx bits were already set, even if this SR modification cleared them.
activate_trace();
}
}
void REGPARAM2 MakeFromSR_T0(void)
{
MakeFromSR_x(1);
}
void REGPARAM2 MakeFromSR(void)
{
MakeFromSR_x(0);
}
void cpu_halt(int halt)
{
cpu_halted = halt;
}
void m68k_setstopped(void)
{
/* A traced STOP instruction drops through immediately without
actually stopping. */
if (SPCFLAG_DOTRACE == 0) {
cpu_stopped = 1;
} else {
cpu_stopped = 0;
}
}
void check_t0_trace(void)
{
if (regs.t0 && !regs.t1 && currprefs.cpu_model >= 68020) {
SPCFLAG_TRACE = 0;
SPCFLAG_DOTRACE = 1;
}
}
void cpureset(void)
{
cpu_halted = -1;
}
static void doexcstack2(void)
{
// generate exception but don't store it with test results
int noac = noaccesshistory;
int ta = testing_active;
int cycs = cpu_cycles;
noaccesshistory = 1;
testing_active = -1;
int opcode = (opcode_memory[0] << 8) | (opcode_memory[1]);
if (test_exception_opcode >= 0) {
opcode = test_exception_opcode;
}
if (SPCFLAG_DOTRACE && test_exception == 9) {
SPCFLAG_DOTRACE = 0;
}
int sv = regs.s;
uaecptr tmp = m68k_areg(regs, 7);
m68k_areg(regs, 7) = test_memory_end + EXTRA_RESERVED_SPACE;
if (cpu_lvl == 0) {
if (test_exception == 2 || test_exception == 3) {
uae_u16 mode = (sv ? 4 : 0) | test_exception_3_fc;
mode |= test_exception_3_w ? 0 : 16;
Exception_build_68000_address_error_stack_frame(mode, opcode, test_exception_addr, regs.pc);
SPCFLAG_DOTRACE = 0;
}
} else if (cpu_lvl == 1) {
if (test_exception == 2 || test_exception == 3) {
uae_u16 ssw = (sv ? 4 : 0) | test_exception_3_fc;
ssw |= test_exception_3_di > 0 ? 0x0000 : (test_exception_3_di < 0 ? (0x2000 | 0x1000) : 0x2000);
ssw |= (!test_exception_3_w && test_exception_3_di) ? 0x1000 : 0x000; // DF
ssw |= (test_exception_opcode & 0x10000) ? 0x0400 : 0x0000; // HB
ssw |= test_exception_3_size == 0 ? 0x0200 : 0x0000; // BY
ssw |= test_exception_3_w ? 0x0000 : 0x0100; // RW
ssw |= (test_exception_opcode & 0x80000) ? 0x0800 : 0x0000; // RM
regs.mmu_fault_addr = test_exception_addr;
Exception_build_stack_frame(regs.instruction_pc, regs.pc, ssw, test_exception, 0x08);
SPCFLAG_DOTRACE = 0;
} else {
Exception_build_stack_frame_common(regs.instruction_pc, regs.pc, 0, test_exception);
}
} else if (cpu_lvl == 2 || cpu_lvl == 3) {
if (test_exception == 3) {
uae_u16 ssw = (sv ? 4 : 0) | test_exception_3_fc;
ssw |= 0x20;
regs.mmu_fault_addr = test_exception_addr;
Exception_build_stack_frame(regs.instruction_pc, regs.pc, ssw, test_exception, 0x0b);
} else {
Exception_build_stack_frame_common(regs.instruction_pc, regs.pc, 0, test_exception);
}
} else {
if (test_exception == 3) {
if (currprefs.cpu_model >= 68040)
test_exception_addr &= ~1;
Exception_build_stack_frame(test_exception_addr, regs.pc, 0, test_exception, 0x02);
} else {
Exception_build_stack_frame_common(regs.instruction_pc, regs.pc, 0, test_exception);
}
}
exception_stack_frame_size = test_memory_end + EXTRA_RESERVED_SPACE - m68k_areg(regs, 7);
m68k_areg(regs, 7) = tmp;
testing_active = ta;
noaccesshistory = noac;
cpu_cycles = cycs;
}
static void doexcstack(void)
{
bool g1 = generates_group1_exception(regs.ir);
doexcstack2();
if (test_exception < 4)
return;
// did we got bus error or address error
// when fetching exception vector?
// (bus error not yet tested)
if (!feature_exception_vectors)
return;
int interrupt = test_exception >= 24 && test_exception < 24 + 8;
int original_exception = test_exception;
// odd exception vector
test_exception = 3;
test_exception_addr = feature_exception_vectors;
// store original exception stack (which may not be complete)
uae_u8 *sf = test_memory + test_memory_size + EXTRA_RESERVED_SPACE - exception_stack_frame_size;