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A SW colleague asked whether it is possible to discover the number of level/priority bits, and number of supported interrupts, at run-time.
This use case would be a read-only implementation of the smclicconfig registers, ideally with the number of interrupt sources readable in the top 12 bits. It's of particular interest to us because when the CLIC is implemented in a soft CPU, there could be many different customer parameterizations - which increases the value of discovery by SW.
This request is very much in the nice-to-have category...
The text was updated successfully, but these errors were encountered:
A SW colleague asked whether it is possible to discover the number of level/priority bits, and number of supported interrupts, at run-time.
This use case would be a read-only implementation of the smclicconfig registers, ideally with the number of interrupt sources readable in the top 12 bits. It's of particular interest to us because when the CLIC is implemented in a soft CPU, there could be many different customer parameterizations - which increases the value of discovery by SW.
This request is very much in the nice-to-have category...
The text was updated successfully, but these errors were encountered: