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main.lst
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main.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .data 00000118 00800100 0000101a 000010ae 2**0
CONTENTS, ALLOC, LOAD, DATA
1 .text 0000101a 00000000 00000000 00000094 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .bss 0000008b 00800218 00800218 000011c6 2**0
ALLOC
3 .stab 0000369c 00000000 00000000 000011c8 2**2
CONTENTS, READONLY, DEBUGGING
4 .stabstr 000018e4 00000000 00000000 00004864 2**0
CONTENTS, READONLY, DEBUGGING
5 .comment 00000011 00000000 00000000 00006148 2**0
CONTENTS, READONLY
6 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 0000615c 2**2
CONTENTS, READONLY
7 .debug_info 000005f4 00000000 00000000 00006198 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_abbrev 000005a2 00000000 00000000 0000678c 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_line 0000001a 00000000 00000000 00006d2e 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_str 00000208 00000000 00000000 00006d48 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 0c 94 46 00 jmp 0x8c ; 0x8c <__ctors_end>
4: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
8: 0c 94 e1 00 jmp 0x1c2 ; 0x1c2 <__vector_2>
c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
10: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
14: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
18: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
1c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
20: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
24: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
28: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
2c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
30: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
34: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
38: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
3c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
40: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
44: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
48: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
4c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
50: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
54: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
58: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
5c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
60: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
64: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt>
68: 96 03 fmuls r17, r22
6a: 98 03 fmulsu r17, r16
6c: 9a 03 fmulsu r17, r18
6e: 9c 03 fmulsu r17, r20
70: 9e 03 fmulsu r17, r22
72: 92 03 fmuls r17, r18
74: 94 03 fmuls r17, r20
76: 13 04 cpc r1, r3
78: 15 04 cpc r1, r5
7a: 1c 04 cpc r1, r12
7c: 1e 04 cpc r1, r14
7e: 29 04 cpc r2, r9
80: 3f 04 cpc r3, r15
82: 4d 04 cpc r4, r13
84: 5c 04 cpc r5, r12
86: 61 04 cpc r6, r1
88: 0b 04 cpc r0, r11
8a: 0f 04 cpc r0, r15
0000008c <__ctors_end>:
8c: 11 24 eor r1, r1
8e: 1f be out 0x3f, r1 ; 63
90: cf ef ldi r28, 0xFF ; 255
92: d8 e0 ldi r29, 0x08 ; 8
94: de bf out 0x3e, r29 ; 62
96: cd bf out 0x3d, r28 ; 61
00000098 <__do_copy_data>:
98: 12 e0 ldi r17, 0x02 ; 2
9a: a0 e0 ldi r26, 0x00 ; 0
9c: b1 e0 ldi r27, 0x01 ; 1
9e: ea e1 ldi r30, 0x1A ; 26
a0: f0 e1 ldi r31, 0x10 ; 16
a2: 02 c0 rjmp .+4 ; 0xa8 <__do_copy_data+0x10>
a4: 05 90 lpm r0, Z+
a6: 0d 92 st X+, r0
a8: a8 31 cpi r26, 0x18 ; 24
aa: b1 07 cpc r27, r17
ac: d9 f7 brne .-10 ; 0xa4 <__do_copy_data+0xc>
000000ae <__do_clear_bss>:
ae: 22 e0 ldi r18, 0x02 ; 2
b0: a8 e1 ldi r26, 0x18 ; 24
b2: b2 e0 ldi r27, 0x02 ; 2
b4: 01 c0 rjmp .+2 ; 0xb8 <.do_clear_bss_start>
000000b6 <.do_clear_bss_loop>:
b6: 1d 92 st X+, r1
000000b8 <.do_clear_bss_start>:
b8: a3 3a cpi r26, 0xA3 ; 163
ba: b2 07 cpc r27, r18
bc: e1 f7 brne .-8 ; 0xb6 <.do_clear_bss_loop>
be: 0e 94 c6 07 call 0xf8c ; 0xf8c <main>
c2: 0c 94 0b 08 jmp 0x1016 ; 0x1016 <_exit>
000000c6 <__bad_interrupt>:
c6: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
000000ca <TimerInit>:
void TimerInit() { //8 bit timer, set up 10Khz (15.625Khz)
// tho it dosn't have to be a 8 bit timer, it dosn't matter really
// as long as all the diodes down my left side hurt, nothing really matters.
// robot with a brain the size of a planet, and they have me writing c code, pathetic.
TCCR1B = (1<<CS10)|(1<<CS12); // 16MHz / 1024 !!!PROCESSOR!!!!
ca: 85 e0 ldi r24, 0x05 ; 5
cc: 80 93 81 00 sts 0x0081, r24 ; 0x800081 <__TEXT_REGION_LENGTH__+0x7f8081>
TimerReset();
d0: 10 92 85 00 sts 0x0085, r1 ; 0x800085 <__TEXT_REGION_LENGTH__+0x7f8085>
d4: 10 92 84 00 sts 0x0084, r1 ; 0x800084 <__TEXT_REGION_LENGTH__+0x7f8084>
d8: 08 95 ret
000000da <Int1Init>:
}
void Int1Init() {
EICRA = (1<<ISC10); // trigger interrupt on any edge !!!PROCESSOR!!!!
da: 84 e0 ldi r24, 0x04 ; 4
dc: 80 93 69 00 sts 0x0069, r24 ; 0x800069 <__TEXT_REGION_LENGTH__+0x7f8069>
SetBit(INT1, EIMSK); // enable the interrupt !!!PROCESSOR!!!!
e0: e9 9a sbi 0x1d, 1 ; 29
e2: 08 95 ret
000000e4 <OnEdge>:
void OnEdge() {
volatile static unsigned BitCount;
volatile static unsigned int IRRecReg;
unsigned int count;
count = TCNT1; // snap shot of timer0 !!!PROCESSOR!!!!
e4: 80 91 84 00 lds r24, 0x0084 ; 0x800084 <__TEXT_REGION_LENGTH__+0x7f8084>
e8: 90 91 85 00 lds r25, 0x0085 ; 0x800085 <__TEXT_REGION_LENGTH__+0x7f8085>
if (0) {
} else if (count > STARTTHRES) { // 4.5ms
ec: 89 32 cpi r24, 0x29 ; 41
ee: 91 05 cpc r25, r1
f0: 78 f0 brcs .+30 ; 0x110 <OnEdge+0x2c>
BitCount = 0; // clear reciever register counter
f2: 10 92 1b 02 sts 0x021B, r1 ; 0x80021b <BitCount.1621+0x1>
f6: 10 92 1a 02 sts 0x021A, r1 ; 0x80021a <BitCount.1621>
IRRecReg = 0;
fa: 10 92 19 02 sts 0x0219, r1 ; 0x800219 <__data_end+0x1>
fe: 10 92 18 02 sts 0x0218, r1 ; 0x800218 <__data_end>
IRRecReg <<= 1;
BitCount++;
}
// set to recieve 8 bits
if (BitCount == 32){
102: 80 91 1a 02 lds r24, 0x021A ; 0x80021a <BitCount.1621>
106: 90 91 1b 02 lds r25, 0x021B ; 0x80021b <BitCount.1621+0x1>
10a: 80 97 sbiw r24, 0x20 ; 32
10c: 31 f1 breq .+76 ; 0x15a <OnEdge+0x76>
10e: 08 95 ret
if (0) {
} else if (count > STARTTHRES) { // 4.5ms
BitCount = 0; // clear reciever register counter
IRRecReg = 0;
} else if (count > HIGHTHRES) { // 1.64 pulse = 1
110: 42 97 sbiw r24, 0x12 ; 18
112: 08 f4 brcc .+2 ; 0x116 <OnEdge+0x32>
114: 42 c0 rjmp .+132 ; 0x19a <OnEdge+0xb6>
IRRecReg <<= 1;
116: 80 91 18 02 lds r24, 0x0218 ; 0x800218 <__data_end>
11a: 90 91 19 02 lds r25, 0x0219 ; 0x800219 <__data_end+0x1>
11e: 88 0f add r24, r24
120: 99 1f adc r25, r25
122: 90 93 19 02 sts 0x0219, r25 ; 0x800219 <__data_end+0x1>
126: 80 93 18 02 sts 0x0218, r24 ; 0x800218 <__data_end>
IRRecReg |= 0x01; // no this is not an error, dont ask!
12a: 80 91 18 02 lds r24, 0x0218 ; 0x800218 <__data_end>
12e: 90 91 19 02 lds r25, 0x0219 ; 0x800219 <__data_end+0x1>
132: 81 60 ori r24, 0x01 ; 1
134: 90 93 19 02 sts 0x0219, r25 ; 0x800219 <__data_end+0x1>
138: 80 93 18 02 sts 0x0218, r24 ; 0x800218 <__data_end>
BitCount++;
13c: 80 91 1a 02 lds r24, 0x021A ; 0x80021a <BitCount.1621>
140: 90 91 1b 02 lds r25, 0x021B ; 0x80021b <BitCount.1621+0x1>
144: 01 96 adiw r24, 0x01 ; 1
146: 90 93 1b 02 sts 0x021B, r25 ; 0x80021b <BitCount.1621+0x1>
14a: 80 93 1a 02 sts 0x021A, r24 ; 0x80021a <BitCount.1621>
IRRecReg <<= 1;
BitCount++;
}
// set to recieve 8 bits
if (BitCount == 32){
14e: 80 91 1a 02 lds r24, 0x021A ; 0x80021a <BitCount.1621>
152: 90 91 1b 02 lds r25, 0x021B ; 0x80021b <BitCount.1621+0x1>
156: 80 97 sbiw r24, 0x20 ; 32
158: d1 f6 brne .-76 ; 0x10e <OnEdge+0x2a>
if ((~IRRecReg & 0xFF) == (IRRecReg >> 8)) { // error checking
15a: 80 91 18 02 lds r24, 0x0218 ; 0x800218 <__data_end>
15e: 90 91 19 02 lds r25, 0x0219 ; 0x800219 <__data_end+0x1>
162: 20 91 18 02 lds r18, 0x0218 ; 0x800218 <__data_end>
166: 30 91 19 02 lds r19, 0x0219 ; 0x800219 <__data_end+0x1>
16a: 80 95 com r24
16c: 90 95 com r25
16e: 99 27 eor r25, r25
170: 23 2f mov r18, r19
172: 33 27 eor r19, r19
174: 82 17 cp r24, r18
176: 93 07 cpc r25, r19
178: 51 f6 brne .-108 ; 0x10e <OnEdge+0x2a>
IRData = IRRecReg >> 8;
17a: 80 91 18 02 lds r24, 0x0218 ; 0x800218 <__data_end>
17e: 90 91 19 02 lds r25, 0x0219 ; 0x800219 <__data_end+0x1>
182: 89 2f mov r24, r25
184: 99 27 eor r25, r25
186: 90 93 1e 02 sts 0x021E, r25 ; 0x80021e <IRData+0x1>
18a: 80 93 1d 02 sts 0x021D, r24 ; 0x80021d <IRData>
SetBit(IRDR, IRStatus); // set data ready flag
18e: 80 91 1f 02 lds r24, 0x021F ; 0x80021f <IRStatus>
192: 80 68 ori r24, 0x80 ; 128
194: 80 93 1f 02 sts 0x021F, r24 ; 0x80021f <IRStatus>
198: 08 95 ret
} else if (count > HIGHTHRES) { // 1.64 pulse = 1
IRRecReg <<= 1;
IRRecReg |= 0x01; // no this is not an error, dont ask!
BitCount++;
} else { // 0.5ms pulse = 0
IRRecReg <<= 1;
19a: 80 91 18 02 lds r24, 0x0218 ; 0x800218 <__data_end>
19e: 90 91 19 02 lds r25, 0x0219 ; 0x800219 <__data_end+0x1>
1a2: 88 0f add r24, r24
1a4: 99 1f adc r25, r25
1a6: 90 93 19 02 sts 0x0219, r25 ; 0x800219 <__data_end+0x1>
1aa: 80 93 18 02 sts 0x0218, r24 ; 0x800218 <__data_end>
BitCount++;
1ae: 80 91 1a 02 lds r24, 0x021A ; 0x80021a <BitCount.1621>
1b2: 90 91 1b 02 lds r25, 0x021B ; 0x80021b <BitCount.1621+0x1>
1b6: 01 96 adiw r24, 0x01 ; 1
1b8: 90 93 1b 02 sts 0x021B, r25 ; 0x80021b <BitCount.1621+0x1>
1bc: 80 93 1a 02 sts 0x021A, r24 ; 0x80021a <BitCount.1621>
1c0: a0 cf rjmp .-192 ; 0x102 <OnEdge+0x1e>
000001c2 <__vector_2>:
EICRA = (1<<ISC10); // trigger interrupt on any edge !!!PROCESSOR!!!!
SetBit(INT1, EIMSK); // enable the interrupt !!!PROCESSOR!!!!
}
ISR (INT1_vect) {
1c2: 1f 92 push r1
1c4: 0f 92 push r0
1c6: 0f b6 in r0, 0x3f ; 63
1c8: 0f 92 push r0
1ca: 11 24 eor r1, r1
1cc: 2f 93 push r18
1ce: 3f 93 push r19
1d0: 4f 93 push r20
1d2: 5f 93 push r21
1d4: 6f 93 push r22
1d6: 7f 93 push r23
1d8: 8f 93 push r24
1da: 9f 93 push r25
1dc: af 93 push r26
1de: bf 93 push r27
1e0: ef 93 push r30
1e2: ff 93 push r31
if (IRH()) { // bit just went high, reset timer
1e4: 4b 9b sbis 0x09, 3 ; 9
1e6: 15 c0 rjmp .+42 ; 0x212 <__vector_2+0x50>
TimerReset(); // start timing
1e8: 10 92 85 00 sts 0x0085, r1 ; 0x800085 <__TEXT_REGION_LENGTH__+0x7f8085>
1ec: 10 92 84 00 sts 0x0084, r1 ; 0x800084 <__TEXT_REGION_LENGTH__+0x7f8084>
} else { // bit just went low, check value of time
OnEdge();
}
}
1f0: ff 91 pop r31
1f2: ef 91 pop r30
1f4: bf 91 pop r27
1f6: af 91 pop r26
1f8: 9f 91 pop r25
1fa: 8f 91 pop r24
1fc: 7f 91 pop r23
1fe: 6f 91 pop r22
200: 5f 91 pop r21
202: 4f 91 pop r20
204: 3f 91 pop r19
206: 2f 91 pop r18
208: 0f 90 pop r0
20a: 0f be out 0x3f, r0 ; 63
20c: 0f 90 pop r0
20e: 1f 90 pop r1
210: 18 95 reti
ISR (INT1_vect) {
if (IRH()) { // bit just went high, reset timer
TimerReset(); // start timing
} else { // bit just went low, check value of time
OnEdge();
212: 0e 94 72 00 call 0xe4 ; 0xe4 <OnEdge>
}
}
216: ec cf rjmp .-40 ; 0x1f0 <__vector_2+0x2e>
00000218 <beep>:
IOPin_t BEEPER = { 1, &PINB };
// for 16Mhz
void beep(uint8_t delay, uint8_t cycles) {
218: cf 92 push r12
21a: df 92 push r13
21c: ef 92 push r14
21e: ff 92 push r15
220: 1f 93 push r17
222: cf 93 push r28
224: df 93 push r29
while(cycles--) {
226: 66 23 and r22, r22
228: a9 f1 breq .+106 ; 0x294 <beep+0x7c>
22a: 90 e2 ldi r25, 0x20 ; 32
22c: 89 9f mul r24, r25
22e: 60 01 movw r12, r0
230: 11 24 eor r1, r1
232: 0d 2c mov r0, r13
234: 00 0c add r0, r0
236: ee 08 sbc r14, r14
238: ff 08 sbc r15, r15
23a: 16 2f mov r17, r22
Delay(delay*32);
SetPin(BEEPER, 0);
23c: c1 e0 ldi r28, 0x01 ; 1
23e: d0 e0 ldi r29, 0x00 ; 0
IOPin_t BEEPER = { 1, &PINB };
// for 16Mhz
void beep(uint8_t delay, uint8_t cycles) {
while(cycles--) {
Delay(delay*32);
240: c7 01 movw r24, r14
242: b6 01 movw r22, r12
244: 0e 94 a4 07 call 0xf48 ; 0xf48 <Delay>
SetPin(BEEPER, 0);
248: e0 91 01 01 lds r30, 0x0101 ; 0x800101 <__DATA_REGION_ORIGIN__+0x1>
24c: f0 91 02 01 lds r31, 0x0102 ; 0x800102 <__DATA_REGION_ORIGIN__+0x2>
250: 92 81 ldd r25, Z+2 ; 0x02
252: 9e 01 movw r18, r28
254: 00 90 00 01 lds r0, 0x0100 ; 0x800100 <__DATA_REGION_ORIGIN__>
258: 02 c0 rjmp .+4 ; 0x25e <beep+0x46>
25a: 22 0f add r18, r18
25c: 33 1f adc r19, r19
25e: 0a 94 dec r0
260: e2 f7 brpl .-8 ; 0x25a <beep+0x42>
262: 82 2f mov r24, r18
264: 80 95 com r24
266: 89 23 and r24, r25
268: 82 83 std Z+2, r24 ; 0x02
Delay(delay*32);
26a: c7 01 movw r24, r14
26c: b6 01 movw r22, r12
26e: 0e 94 a4 07 call 0xf48 ; 0xf48 <Delay>
SetPin(BEEPER, 1);
272: e0 91 01 01 lds r30, 0x0101 ; 0x800101 <__DATA_REGION_ORIGIN__+0x1>
276: f0 91 02 01 lds r31, 0x0102 ; 0x800102 <__DATA_REGION_ORIGIN__+0x2>
27a: 22 81 ldd r18, Z+2 ; 0x02
27c: ce 01 movw r24, r28
27e: 00 90 00 01 lds r0, 0x0100 ; 0x800100 <__DATA_REGION_ORIGIN__>
282: 02 c0 rjmp .+4 ; 0x288 <beep+0x70>
284: 88 0f add r24, r24
286: 99 1f adc r25, r25
288: 0a 94 dec r0
28a: e2 f7 brpl .-8 ; 0x284 <beep+0x6c>
28c: 82 2b or r24, r18
28e: 82 83 std Z+2, r24 ; 0x02
290: 11 50 subi r17, 0x01 ; 1
IOPin_t BEEPER = { 1, &PINB };
// for 16Mhz
void beep(uint8_t delay, uint8_t cycles) {
while(cycles--) {
292: b1 f6 brne .-84 ; 0x240 <beep+0x28>
Delay(delay*32);
SetPin(BEEPER, 0);
Delay(delay*32);
SetPin(BEEPER, 1);
}
}
294: df 91 pop r29
296: cf 91 pop r28
298: 1f 91 pop r17
29a: ff 90 pop r15
29c: ef 90 pop r14
29e: df 90 pop r13
2a0: cf 90 pop r12
2a2: 08 95 ret
000002a4 <event_error>:
void event_error() {
beep(200, 45);
2a4: 6d e2 ldi r22, 0x2D ; 45
2a6: 88 ec ldi r24, 0xC8 ; 200
2a8: 0c 94 0c 01 jmp 0x218 ; 0x218 <beep>
000002ac <event_cmdOK>:
}
void event_cmdOK() {
beep(20, 128);
2ac: 60 e8 ldi r22, 0x80 ; 128
2ae: 84 e1 ldi r24, 0x14 ; 20
2b0: 0c 94 0c 01 jmp 0x218 ; 0x218 <beep>
000002b4 <event_digitOK>:
}
void event_digitOK() {
beep(16, 128);
2b4: 60 e8 ldi r22, 0x80 ; 128
2b6: 80 e1 ldi r24, 0x10 ; 16
2b8: 0c 94 0c 01 jmp 0x218 ; 0x218 <beep>
000002bc <printNumDec32>:
uint8_t BCDLUT1[] = {0,2,4,6,8,0,2,4,6,8}; // ones place for x2
uint8_t BCDLUT2[] = {0,0,0,0,0,1,1,1,1,1}; // carry for x2
void printNumDec32 ( uint32_t bv ) {
2bc: 2f 92 push r2
2be: 3f 92 push r3
2c0: 4f 92 push r4
2c2: 5f 92 push r5
2c4: 6f 92 push r6
2c6: 7f 92 push r7
2c8: 8f 92 push r8
2ca: 9f 92 push r9
2cc: af 92 push r10
2ce: bf 92 push r11
2d0: cf 92 push r12
2d2: df 92 push r13
2d4: ef 92 push r14
2d6: ff 92 push r15
2d8: 0f 93 push r16
2da: 1f 93 push r17
2dc: cf 93 push r28
2de: df 93 push r29
2e0: e0 e2 ldi r30, 0x20 ; 32
2e2: f0 e0 ldi r31, 0x00 ; 0
uint32_t i;
uint8_t d0, d1, d2, d3, d4, d5, d6, d7, d8, d9; // ssh.
d0 = d1 = d2 = d3 = d4 = d5 = d6 = d7 = d8 = d9 = 0;
2e4: 41 2c mov r4, r1
2e6: d0 e0 ldi r29, 0x00 ; 0
2e8: c0 e0 ldi r28, 0x00 ; 0
2ea: 10 e0 ldi r17, 0x00 ; 0
2ec: 00 e0 ldi r16, 0x00 ; 0
2ee: b1 2c mov r11, r1
2f0: a1 2c mov r10, r1
2f2: 91 2c mov r9, r1
2f4: 81 2c mov r8, r1
2f6: 51 2c mov r5, r1
for (i = 0x80000000; i ; i>>=1) {
2f8: c1 2c mov r12, r1
2fa: d1 2c mov r13, r1
2fc: e1 2c mov r14, r1
2fe: 30 e8 ldi r19, 0x80 ; 128
300: f3 2e mov r15, r19
d9 <<= 1;
302: 74 2c mov r7, r4
304: 77 0c add r7, r7
d9 |= BCDLUT2[d8];
306: 2d 2f mov r18, r29
308: 30 e0 ldi r19, 0x00 ; 0
30a: a9 01 movw r20, r18
30c: 4d 5f subi r20, 0xFD ; 253
30e: 5e 4f sbci r21, 0xFE ; 254
310: da 01 movw r26, r20
312: 4c 91 ld r20, X
314: 47 2c mov r4, r7
316: 44 2a or r4, r20
d8 = BCDLUT1[d8];
d8 |= BCDLUT2[d7];
318: 4c 2f mov r20, r28
31a: 50 e0 ldi r21, 0x00 ; 0
for (i = 0x80000000; i ; i>>=1) {
d9 <<= 1;
d9 |= BCDLUT2[d8];
d8 = BCDLUT1[d8];
31c: 23 5f subi r18, 0xF3 ; 243
31e: 3e 4f sbci r19, 0xFE ; 254
d8 |= BCDLUT2[d7];
320: da 01 movw r26, r20
322: ad 5f subi r26, 0xFD ; 253
324: be 4f sbci r27, 0xFE ; 254
326: e9 01 movw r28, r18
328: 38 81 ld r19, Y
32a: 2c 91 ld r18, X
32c: d3 2f mov r29, r19
32e: d2 2b or r29, r18
d7 = BCDLUT1[d7];
d7 |= BCDLUT2[d6];
330: 21 2f mov r18, r17
332: 30 e0 ldi r19, 0x00 ; 0
d9 |= BCDLUT2[d8];
d8 = BCDLUT1[d8];
d8 |= BCDLUT2[d7];
d7 = BCDLUT1[d7];
334: da 01 movw r26, r20
336: a3 5f subi r26, 0xF3 ; 243
338: be 4f sbci r27, 0xFE ; 254
d7 |= BCDLUT2[d6];
33a: a9 01 movw r20, r18
33c: 4d 5f subi r20, 0xFD ; 253
33e: 5e 4f sbci r21, 0xFE ; 254
340: cc 91 ld r28, X
342: da 01 movw r26, r20
344: 4c 91 ld r20, X
346: c4 2b or r28, r20
d6 = BCDLUT1[d6];
d6 |= BCDLUT2[d5];
348: 40 2f mov r20, r16
34a: 50 e0 ldi r21, 0x00 ; 0
d8 |= BCDLUT2[d7];
d7 = BCDLUT1[d7];
d7 |= BCDLUT2[d6];
d6 = BCDLUT1[d6];
34c: 23 5f subi r18, 0xF3 ; 243
34e: 3e 4f sbci r19, 0xFE ; 254
d6 |= BCDLUT2[d5];
350: 8a 01 movw r16, r20
352: 0d 5f subi r16, 0xFD ; 253
354: 1e 4f sbci r17, 0xFE ; 254
356: d9 01 movw r26, r18
358: 3c 91 ld r19, X
35a: d8 01 movw r26, r16
35c: 2c 91 ld r18, X
35e: 13 2f mov r17, r19
360: 12 2b or r17, r18
d5 = BCDLUT1[d5];
d5 |= BCDLUT2[d4];
362: 2b 2d mov r18, r11
364: 30 e0 ldi r19, 0x00 ; 0
d7 |= BCDLUT2[d6];
d6 = BCDLUT1[d6];
d6 |= BCDLUT2[d5];
d5 = BCDLUT1[d5];
366: 43 5f subi r20, 0xF3 ; 243
368: 5e 4f sbci r21, 0xFE ; 254
d5 |= BCDLUT2[d4];
36a: d9 01 movw r26, r18
36c: ad 5f subi r26, 0xFD ; 253
36e: be 4f sbci r27, 0xFE ; 254
370: 3d 01 movw r6, r26
372: da 01 movw r26, r20
374: 0c 91 ld r16, X
376: d3 01 movw r26, r6
378: 4c 91 ld r20, X
37a: 04 2b or r16, r20
d4 = BCDLUT1[d4];
d4 |= BCDLUT2[d3];
37c: 4a 2d mov r20, r10
37e: 50 e0 ldi r21, 0x00 ; 0
d6 |= BCDLUT2[d5];
d5 = BCDLUT1[d5];
d5 |= BCDLUT2[d4];
d4 = BCDLUT1[d4];
380: 23 5f subi r18, 0xF3 ; 243
382: 3e 4f sbci r19, 0xFE ; 254
d4 |= BCDLUT2[d3];
384: da 01 movw r26, r20
386: ad 5f subi r26, 0xFD ; 253
388: be 4f sbci r27, 0xFE ; 254
38a: 5d 01 movw r10, r26
38c: d9 01 movw r26, r18
38e: 3c 91 ld r19, X
390: d5 01 movw r26, r10
392: 2c 91 ld r18, X
394: b3 2e mov r11, r19
396: b2 2a or r11, r18
d3 = BCDLUT1[d3];
d3 |= BCDLUT2[d2];
398: 29 2d mov r18, r9
39a: 30 e0 ldi r19, 0x00 ; 0
d5 |= BCDLUT2[d4];
d4 = BCDLUT1[d4];
d4 |= BCDLUT2[d3];
d3 = BCDLUT1[d3];
39c: 43 5f subi r20, 0xF3 ; 243
39e: 5e 4f sbci r21, 0xFE ; 254
d3 |= BCDLUT2[d2];
3a0: d9 01 movw r26, r18
3a2: ad 5f subi r26, 0xFD ; 253
3a4: be 4f sbci r27, 0xFE ; 254
3a6: 3d 01 movw r6, r26
3a8: da 01 movw r26, r20
3aa: ac 90 ld r10, X
3ac: d3 01 movw r26, r6
3ae: 4c 91 ld r20, X
3b0: a4 2a or r10, r20
d2 = BCDLUT1[d2];
d2 |= BCDLUT2[d1];
3b2: 48 2d mov r20, r8
3b4: 50 e0 ldi r21, 0x00 ; 0
d4 |= BCDLUT2[d3];
d3 = BCDLUT1[d3];
d3 |= BCDLUT2[d2];
d2 = BCDLUT1[d2];
3b6: 23 5f subi r18, 0xF3 ; 243
3b8: 3e 4f sbci r19, 0xFE ; 254
d2 |= BCDLUT2[d1];
3ba: da 01 movw r26, r20
3bc: ad 5f subi r26, 0xFD ; 253
3be: be 4f sbci r27, 0xFE ; 254
3c0: 4d 01 movw r8, r26
3c2: d9 01 movw r26, r18
3c4: 3c 91 ld r19, X
3c6: d4 01 movw r26, r8
3c8: 2c 91 ld r18, X
3ca: 93 2e mov r9, r19
3cc: 92 2a or r9, r18
d1 = BCDLUT1[d1];
d1 |= BCDLUT2[d0];
3ce: 25 2d mov r18, r5
3d0: 30 e0 ldi r19, 0x00 ; 0
d3 |= BCDLUT2[d2];
d2 = BCDLUT1[d2];
d2 |= BCDLUT2[d1];
d1 = BCDLUT1[d1];
3d2: 43 5f subi r20, 0xF3 ; 243
3d4: 5e 4f sbci r21, 0xFE ; 254
d1 |= BCDLUT2[d0];
3d6: d9 01 movw r26, r18
3d8: ad 5f subi r26, 0xFD ; 253
3da: be 4f sbci r27, 0xFE ; 254
3dc: 3d 01 movw r6, r26
3de: da 01 movw r26, r20
3e0: 8c 90 ld r8, X
3e2: d3 01 movw r26, r6
3e4: 4c 91 ld r20, X
3e6: 84 2a or r8, r20
d0 = BCDLUT1[d0];
3e8: 23 5f subi r18, 0xF3 ; 243
3ea: 3e 4f sbci r19, 0xFE ; 254
3ec: d9 01 movw r26, r18
3ee: 5c 90 ld r5, X
if (bv & i) d0 |= 1;
3f0: 9b 01 movw r18, r22
3f2: ac 01 movw r20, r24
3f4: 2c 21 and r18, r12
3f6: 3d 21 and r19, r13
3f8: 4e 21 and r20, r14
3fa: 5f 21 and r21, r15
3fc: 23 2b or r18, r19
3fe: 24 2b or r18, r20
400: 25 2b or r18, r21
402: 19 f0 breq .+6 ; 0x40a <__EEPROM_REGION_LENGTH__+0xa>
404: b5 2d mov r27, r5
406: b1 60 ori r27, 0x01 ; 1
408: 5b 2e mov r5, r27
uint32_t i;
uint8_t d0, d1, d2, d3, d4, d5, d6, d7, d8, d9; // ssh.
d0 = d1 = d2 = d3 = d4 = d5 = d6 = d7 = d8 = d9 = 0;
for (i = 0x80000000; i ; i>>=1) {
40a: f6 94 lsr r15
40c: e7 94 ror r14
40e: d7 94 ror r13
410: c7 94 ror r12
412: 31 97 sbiw r30, 0x01 ; 1
414: 09 f0 breq .+2 ; 0x418 <__EEPROM_REGION_LENGTH__+0x18>
416: 75 cf rjmp .-278 ; 0x302 <printNumDec32+0x46>
if (bv & i) d0 |= 1;
}
USART_Transmit( d9|0x30 );
418: 84 2d mov r24, r4
41a: 80 63 ori r24, 0x30 ; 48
41c: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d8|0x30 );
420: 8d 2f mov r24, r29
422: 80 63 ori r24, 0x30 ; 48
424: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d7|0x30 );
428: 8c 2f mov r24, r28
42a: 80 63 ori r24, 0x30 ; 48
42c: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d6|0x30 );
430: 81 2f mov r24, r17
432: 80 63 ori r24, 0x30 ; 48
434: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d5|0x30 );
438: 80 2f mov r24, r16
43a: 80 63 ori r24, 0x30 ; 48
43c: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d4|0x30 );
440: 8b 2d mov r24, r11
442: 80 63 ori r24, 0x30 ; 48
444: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d3|0x30 );
448: 8a 2d mov r24, r10
44a: 80 63 ori r24, 0x30 ; 48
44c: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d2|0x30 );
450: 89 2d mov r24, r9
452: 80 63 ori r24, 0x30 ; 48
454: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d1|0x30 );
458: 88 2d mov r24, r8
45a: 80 63 ori r24, 0x30 ; 48
45c: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d0|0x30 );
460: 85 2d mov r24, r5
462: 80 63 ori r24, 0x30 ; 48
}
464: df 91 pop r29
466: cf 91 pop r28
468: 1f 91 pop r17
46a: 0f 91 pop r16
46c: ff 90 pop r15
46e: ef 90 pop r14
470: df 90 pop r13
472: cf 90 pop r12
474: bf 90 pop r11
476: af 90 pop r10
478: 9f 90 pop r9
47a: 8f 90 pop r8
47c: 7f 90 pop r7
47e: 6f 90 pop r6
480: 5f 90 pop r5
482: 4f 90 pop r4
484: 3f 90 pop r3
486: 2f 90 pop r2
USART_Transmit( d5|0x30 );
USART_Transmit( d4|0x30 );
USART_Transmit( d3|0x30 );
USART_Transmit( d2|0x30 );
USART_Transmit( d1|0x30 );
USART_Transmit( d0|0x30 );
488: 0c 94 bf 07 jmp 0xf7e ; 0xf7e <USART_Transmit>
0000048c <printNumDec16>:
}
}
void printNumDec16( uint16_t bv ) {
48c: cf 92 push r12
48e: df 92 push r13
490: ef 92 push r14
492: ff 92 push r15
494: 0f 93 push r16
496: 1f 93 push r17
498: cf 93 push r28
49a: df 93 push r29
49c: 6c 01 movw r12, r24
49e: e0 e1 ldi r30, 0x10 ; 16
4a0: f0 e0 ldi r31, 0x00 ; 0
uint16_t i;
uint8_t d0, d1, d2, d3, d4; // ssh.
d0 = d1 = d2 = d3 = d4 = 0;
4a2: 80 e0 ldi r24, 0x00 ; 0
4a4: 10 e0 ldi r17, 0x00 ; 0
4a6: 00 e0 ldi r16, 0x00 ; 0
4a8: d0 e0 ldi r29, 0x00 ; 0
4aa: c0 e0 ldi r28, 0x00 ; 0
for (i = 0x8000; i ; i>>=1) {
4ac: 60 e0 ldi r22, 0x00 ; 0
4ae: 70 e8 ldi r23, 0x80 ; 128
d4 <<= 1;
4b0: 88 0f add r24, r24
d4 |= BCDLUT2[d3];
4b2: 41 2f mov r20, r17
4b4: 50 e0 ldi r21, 0x00 ; 0
4b6: 9a 01 movw r18, r20
4b8: 2d 5f subi r18, 0xFD ; 253
4ba: 3e 4f sbci r19, 0xFE ; 254
4bc: d9 01 movw r26, r18
4be: 9c 91 ld r25, X
4c0: 89 2b or r24, r25
d3 = BCDLUT1[d3];
d3 |= BCDLUT2[d2];
4c2: 20 2f mov r18, r16
4c4: 30 e0 ldi r19, 0x00 ; 0
for (i = 0x8000; i ; i>>=1) {
d4 <<= 1;
d4 |= BCDLUT2[d3];
d3 = BCDLUT1[d3];
4c6: 43 5f subi r20, 0xF3 ; 243
4c8: 5e 4f sbci r21, 0xFE ; 254
d3 |= BCDLUT2[d2];
4ca: d9 01 movw r26, r18
4cc: ad 5f subi r26, 0xFD ; 253
4ce: be 4f sbci r27, 0xFE ; 254
4d0: 7d 01 movw r14, r26
4d2: da 01 movw r26, r20
4d4: 1c 91 ld r17, X
4d6: d7 01 movw r26, r14
4d8: 9c 91 ld r25, X
4da: 19 2b or r17, r25
d2 = BCDLUT1[d2];
d2 |= BCDLUT2[d1];
4dc: 4d 2f mov r20, r29
4de: 50 e0 ldi r21, 0x00 ; 0
d4 |= BCDLUT2[d3];
d3 = BCDLUT1[d3];
d3 |= BCDLUT2[d2];
d2 = BCDLUT1[d2];
4e0: 23 5f subi r18, 0xF3 ; 243
4e2: 3e 4f sbci r19, 0xFE ; 254
d2 |= BCDLUT2[d1];
4e4: da 01 movw r26, r20
4e6: ad 5f subi r26, 0xFD ; 253
4e8: be 4f sbci r27, 0xFE ; 254
4ea: 7d 01 movw r14, r26
4ec: d9 01 movw r26, r18
4ee: 2c 91 ld r18, X
4f0: d7 01 movw r26, r14
4f2: 9c 91 ld r25, X
4f4: 02 2f mov r16, r18
4f6: 09 2b or r16, r25
d1 = BCDLUT1[d1];
d1 |= BCDLUT2[d0];
4f8: 2c 2f mov r18, r28
4fa: 30 e0 ldi r19, 0x00 ; 0
d3 |= BCDLUT2[d2];
d2 = BCDLUT1[d2];
d2 |= BCDLUT2[d1];
d1 = BCDLUT1[d1];
4fc: 43 5f subi r20, 0xF3 ; 243
4fe: 5e 4f sbci r21, 0xFE ; 254
d1 |= BCDLUT2[d0];
500: e9 01 movw r28, r18
502: cd 5f subi r28, 0xFD ; 253
504: de 4f sbci r29, 0xFE ; 254
506: da 01 movw r26, r20
508: 4c 91 ld r20, X
50a: 98 81 ld r25, Y
50c: d4 2f mov r29, r20
50e: d9 2b or r29, r25
d0 = BCDLUT1[d0];
510: 23 5f subi r18, 0xF3 ; 243
512: 3e 4f sbci r19, 0xFE ; 254
514: d9 01 movw r26, r18
516: cc 91 ld r28, X
if (bv & i) d0 |= 1;
518: 96 01 movw r18, r12
51a: 26 23 and r18, r22
51c: 37 23 and r19, r23
51e: 23 2b or r18, r19
520: 09 f0 breq .+2 ; 0x524 <printNumDec16+0x98>
522: c1 60 ori r28, 0x01 ; 1
uint16_t i;
uint8_t d0, d1, d2, d3, d4; // ssh.
d0 = d1 = d2 = d3 = d4 = 0;
for (i = 0x8000; i ; i>>=1) {
524: 76 95 lsr r23
526: 67 95 ror r22
528: 31 97 sbiw r30, 0x01 ; 1
52a: 11 f6 brne .-124 ; 0x4b0 <printNumDec16+0x24>
if (bv & i) d0 |= 1;
}
USART_Transmit( d4|0x30 );
52c: 80 63 ori r24, 0x30 ; 48
52e: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d3|0x30 );
532: 81 2f mov r24, r17
534: 80 63 ori r24, 0x30 ; 48
536: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d2|0x30 );
53a: 80 2f mov r24, r16
53c: 80 63 ori r24, 0x30 ; 48
53e: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d1|0x30 );
542: 8d 2f mov r24, r29
544: 80 63 ori r24, 0x30 ; 48
546: 0e 94 bf 07 call 0xf7e ; 0xf7e <USART_Transmit>
USART_Transmit( d0|0x30 );
54a: 8c 2f mov r24, r28
54c: 80 63 ori r24, 0x30 ; 48
}
54e: df 91 pop r29
550: cf 91 pop r28
552: 1f 91 pop r17
554: 0f 91 pop r16
556: ff 90 pop r15
558: ef 90 pop r14
55a: df 90 pop r13
55c: cf 90 pop r12
USART_Transmit( d4|0x30 );
USART_Transmit( d3|0x30 );
USART_Transmit( d2|0x30 );
USART_Transmit( d1|0x30 );
USART_Transmit( d0|0x30 );
55e: 0c 94 bf 07 jmp 0xf7e ; 0xf7e <USART_Transmit>
00000562 <printSignNumDec16>:
USART_Transmit( d0|0x30 );
}
void printSignNumDec16( int16_t bv) {
562: cf 93 push r28
564: df 93 push r29
if (bv < 0) {
566: 97 fd sbrc r25, 7
568: 04 c0 rjmp .+8 ; 0x572 <printSignNumDec16+0x10>
printNumDec16(-bv);
} else {
printNumDec16(bv);
}
}
56a: df 91 pop r29
56c: cf 91 pop r28
void printSignNumDec16( int16_t bv) {
if (bv < 0) {
USART_Transmit( '-' );
printNumDec16(-bv);
} else {
printNumDec16(bv);
56e: 0c 94 46 02 jmp 0x48c ; 0x48c <printNumDec16>