From 2ff31df3dc146b03e61d55bac2005b22bb98d900 Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Wed, 12 Feb 2025 09:24:28 +0000
Subject: [PATCH] riscv: add basic `stvec` unit tests

Adds basic unit tests for the `stvec` CSR.
---
 riscv/src/register/stvec.rs | 41 +++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/riscv/src/register/stvec.rs b/riscv/src/register/stvec.rs
index 09e25749..81a80a61 100644
--- a/riscv/src/register/stvec.rs
+++ b/riscv/src/register/stvec.rs
@@ -54,3 +54,44 @@ impl Stvec {
         }
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_stvec() {
+        let mut stvec = Stvec::from_bits(0);
+
+        [TrapMode::Direct, TrapMode::Vectored]
+            .into_iter()
+            .for_each(|trap_mode| {
+                test_csr_field!(stvec, trap_mode: trap_mode);
+            });
+
+        (1..=usize::BITS)
+            .map(|r| (((1u128 << r) - 1) as usize) & !TRAP_MASK)
+            .for_each(|address| {
+                stvec.set_address(address);
+                assert_eq!(stvec.address(), address);
+
+                assert_eq!(stvec.try_set_address(address), Ok(()));
+                assert_eq!(stvec.address(), address);
+            });
+
+        (1..=usize::BITS)
+            .filter_map(|r| match ((1u128 << r) - 1) as usize {
+                addr if (addr & TRAP_MASK) != 0 => Some(addr),
+                _ => None,
+            })
+            .for_each(|address| {
+                assert_eq!(
+                    stvec.try_set_address(address),
+                    Err(Error::InvalidFieldVariant {
+                        field: "stvec::address",
+                        value: address,
+                    })
+                );
+            });
+    }
+}