transcript

# Reading C:/altera/15.0/modelsim_ase/tcl/vsim/pref.tcl
# OpenFile C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:01:33 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(138): near ";": expecting ')'
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(144): near "if": expecting ';'
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(150): No feasible entries for prefix operator "xor".
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(150): Type error resolving prefix expression "xor" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(152): near "when": expecting END
# End time: 13:01:33 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 5, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:01:51 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(150): No feasible entries for prefix operator "xor".
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(150): Type error resolving prefix expression "xor" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(154): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(154): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(156): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(156): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(158): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(158): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(160): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(160): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(165): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(165): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(167): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(167): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(169): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(169): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(175): VHDL Compiler exiting
# End time: 13:01:51 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 17, Warnings: 0
# Modified modelsim.ini
# Modified modelsim.ini
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:02:05 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(154): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(154): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(156): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(156): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(158): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(158): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(160): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(160): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(165): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(165): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(167): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(167): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(169): Illegal target for signal assignment.
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(169): (vcom-1136) Unknown identifier "out_code".
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(175): VHDL Compiler exiting
# End time: 13:02:05 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 15, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:18:47 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(156): near "when": expecting END
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(135): (vcom-1339) Case statement choices cover only 2 out of 6561 cases.
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(164): VHDL Compiler exiting
# End time: 13:18:47 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 3, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:19:00 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(135): (vcom-1339) Case statement choices cover only 3 out of 6561 cases.
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(165): VHDL Compiler exiting
# End time: 13:19:00 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:19:01 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(135): (vcom-1339) Case statement choices cover only 3 out of 6561 cases.
# 
# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(165): VHDL Compiler exiting
# End time: 13:19:01 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:19:09 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:19:09 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:19:10 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:19:10 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:19:54 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:19:55 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
add wave -position insertpoint N
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:30:21 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:30:21 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:30:21 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# ** Error: alu_tb.vhd(79): Signal "status_t" is type ieee.NUMERIC_STD.UNSIGNED; expecting type work.status_type.alu_status.
# ** Error: alu_tb.vhd(413): VHDL Compiler exiting
# End time: 13:30:21 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# C:/altera/15.0/modelsim_ase/win32aloem/vcom failed.
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:30:40 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:30:41 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:30:41 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:30:41 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -gui C:\Users\scarte9\ECSE487-ALU\alu_16.vhd 
# Start time: 13:30:41 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 4 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 6 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 10 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 12 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 18 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 22 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 24 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 26 ns  Iteration: 0  Instance: /alu_tb
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:34:43 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:34:44 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:34:44 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:34:44 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:34:45 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 4 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 6 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 10 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 12 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 18 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 22 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 24 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 26 ns  Iteration: 0  Instance: /alu_tb
vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:36:27 on Feb 06,2016
# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:36:27 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:36:54 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:36:54 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:36:54 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:36:54 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:36:55 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:37:31 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:37:32 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:37:32 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:37:32 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:37:33 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:37:57 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:37:57 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:37:57 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:37:58 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:37:59 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:38:39 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:38:39 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:38:39 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:38:40 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:38:40 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
quit -sim
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:46:35 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:46:35 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:46:35 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:46:35 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:46:35 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confims parity is high for even bits and negative number
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case shows a status of no set values
#    Time: 4 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confims parity is high for even bits and negative number
#    Time: 6 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: checking condition with overflow
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confims negative number and no parity bit set
#    Time: 10 ns  Iteration: 0  Instance: /alu_tb
# ** Note: checking condition with overflow -- Status is wrong to demonstrate no esiting error
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confirms function of zero number and even parity
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confirms even parity
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function: no overflow due to barrel shift
#    Time: 22 ns  Iteration: 0  Instance: /alu_tb
# ** Note: Parity and negative
#    Time: 22 ns  Iteration: 0  Instance: /alu_tb
# ** Note: checking negative value
#    Time: 24 ns  Iteration: 0  Instance: /alu_tb
source alu_tb.tcl
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:47:05 on Feb 06,2016
# vcom -reportprogress 300 alu_16.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity alu_16
# -- Compiling architecture implementation of alu_16
# End time: 13:47:05 on Feb 06,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:47:05 on Feb 06,2016
# vcom -reportprogress 300 alu_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package status_type
# -- Compiling entity alu_tb
# -- Compiling architecture testbed of alu_tb
# End time: 13:47:06 on Feb 06,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vsim 
# Start time: 13:47:06 on Feb 06,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.status_type(body)
# Loading work.alu_tb(testbed)
# Loading work.alu_16(implementation)
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /alu_tb/dut
# ** Note: begin test case for add function
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confims parity is high for even bits and negative number
#    Time: 2 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case shows a status of no set values
#    Time: 4 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confims parity is high for even bits and negative number
#    Time: 6 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for SUB function
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: checking condition with overflow
#    Time: 8 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confims negative number and no parity bit set
#    Time: 10 ns  Iteration: 0  Instance: /alu_tb
# ** Note: checking condition with overflow -- Status is wrong to demonstrate non-exiting error
#    Time: 14 ns  Iteration: 0  Instance: /alu_tb
# ** Error: status output incorrect
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for AND function
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confirms function of zero number and even parity
#    Time: 16 ns  Iteration: 0  Instance: /alu_tb
# ** Note: test case confirms even parity
#    Time: 20 ns  Iteration: 0  Instance: /alu_tb
# ** Note: begin test case for ASR function: no overflow due to barrel shift
#    Time: 22 ns  Iteration: 0  Instance: /alu_tb
# ** Note: Parity and negative
#    Time: 22 ns  Iteration: 0  Instance: /alu_tb
# ** Note: checking negative value
#    Time: 24 ns  Iteration: 0  Instance: /alu_tb